1//Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp 2// Spec Reference: ldimmhalf lz dreg 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9INIT_R_REGS -1; 10 11 12// test Dreg 13R0 = 0x0001 (Z); 14R1 = 0x0003 (Z); 15R2 = 0x0005 (Z); 16R3 = 0x0007 (Z); 17R4 = 0x0009 (Z); 18R5 = 0x000b (Z); 19R6 = 0x000d (Z); 20R7 = 0x000f (Z); 21CHECKREG r0, 0x00000001; 22CHECKREG r1, 0x00000003; 23CHECKREG r2, 0x00000005; 24CHECKREG r3, 0x00000007; 25CHECKREG r4, 0x00000009; 26CHECKREG r5, 0x0000000b; 27CHECKREG r6, 0x0000000d; 28CHECKREG r7, 0x0000000f; 29 30R0 = 0x0010 (Z); 31R1 = 0x0030 (Z); 32R2 = 0x0050 (Z); 33R3 = 0x0070 (Z); 34R4 = 0x0090 (Z); 35R5 = 0x00b0 (Z); 36R6 = 0x00d0 (Z); 37R7 = 0x00f0 (Z); 38CHECKREG r0, 0x00000010; 39CHECKREG r1, 0x00000030; 40CHECKREG r2, 0x00000050; 41CHECKREG r3, 0x00000070; 42CHECKREG r4, 0x00000090; 43CHECKREG r5, 0x000000b0; 44CHECKREG r6, 0x000000d0; 45CHECKREG r7, 0x000000f0; 46 47R0 = 0x0100 (Z); 48R1 = 0x0300 (Z); 49R2 = 0x0500 (Z); 50R3 = 0x0700 (Z); 51R4 = 0x0900 (Z); 52R5 = 0x0b00 (Z); 53R6 = 0x0d00 (Z); 54R7 = 0x0f00 (Z); 55CHECKREG r0, 0x00000100; 56CHECKREG r1, 0x00000300; 57CHECKREG r2, 0x00000500; 58CHECKREG r3, 0x00000700; 59CHECKREG r4, 0x00000900; 60CHECKREG r5, 0x00000b00; 61CHECKREG r6, 0x00000d00; 62CHECKREG r7, 0x00000f00; 63 64R0 = 0x1000 (Z); 65R1 = 0x3000 (Z); 66R2 = 0x5000 (Z); 67R3 = 0x7000 (Z); 68R4 = 0x9000 (Z); 69R5 = 0xb000 (Z); 70R6 = 0xd000 (Z); 71R7 = 0xf000 (Z); 72CHECKREG r0, 0x00001000; 73CHECKREG r1, 0x00003000; 74CHECKREG r2, 0x00005000; 75CHECKREG r3, 0x00007000; 76CHECKREG r4, 0x00009000; 77CHECKREG r5, 0x0000b000; 78CHECKREG r6, 0x0000d000; 79CHECKREG r7, 0x0000f000; 80 81pass 82