xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/c_interr_disable.S (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c) 
1//Original:/proj/frio/dv/testcases/core/c_interr_disable/c_interr_disable.dsp
2// Spec Reference: CLI STI interrupt on HW TIMER to disable interrupt
3# mach: bfin
4# sim: --environment operating
5
6#include "test.h"
7.include "testutils.inc"
8start
9
10//
11// Include Files
12//
13
14include(std.inc)
15include(selfcheck.inc)
16
17// Defines
18
19#ifndef TCNTL
20#define TCNTL            0xFFE03000
21#endif
22#ifndef TPERIOD
23#define TPERIOD          0xFFE03004
24#endif
25#ifndef TSCALE
26#define TSCALE           0xFFE03008
27#endif
28#ifndef TCOUNT
29#define TCOUNT           0xFFE0300c
30#endif
31#ifndef EVT
32#define EVT              0xFFE02000
33#endif
34#ifndef EVT15
35#define EVT15            0xFFE0203c
36#endif
37#ifndef EVT_OVERRIDE
38#define EVT_OVERRIDE     0xFFE02100
39#endif
40#ifndef ITABLE
41#define ITABLE           0x000FF000
42#endif
43#ifndef PROGRAM_STACK
44#define PROGRAM_STACK    0x000FF100
45#endif
46#ifndef STACKSIZE
47#define STACKSIZE        0x00000300
48#endif
49
50// Boot code
51
52 BOOT :
53INIT_R_REGS(0);                             // Initialize Dregs
54INIT_P_REGS(0);                             // Initialize Pregs
55
56     // CHECK_INIT(p5,   0x00BFFFFC);
57     // CHECK_INIT(p5,   0xE0000000);
58include(symtable.inc)
59CHECK_INIT_DEF(p5);
60
61
62LD32(sp, 0x000FF200);
63LD32(p0, EVT);              // Setup Event Vectors and Handlers
64
65LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
66        [ P0 ++ ] = R0;
67
68LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
69        [ P0 ++ ] = R0;
70
71LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
72        [ P0 ++ ] = R0;
73
74LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
75        [ P0 ++ ] = R0;
76
77        [ P0 ++ ] = R0;                // IVT4 not used
78
79LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
80        [ P0 ++ ] = R0;
81
82LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
83        [ P0 ++ ] = R0;
84
85LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
86        [ P0 ++ ] = R0;
87
88LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
89        [ P0 ++ ] = R0;
90
91LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
92        [ P0 ++ ] = R0;
93
94LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
95        [ P0 ++ ] = R0;
96
97LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
98        [ P0 ++ ] = R0;
99
100LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
101        [ P0 ++ ] = R0;
102
103LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
104        [ P0 ++ ] = R0;
105
106LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
107        [ P0 ++ ] = R0;
108
109LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
110        [ P0 ++ ] = R0;
111
112LD32(p0, EVT_OVERRIDE);
113        R0 = 0;
114        [ P0 ++ ] = R0;
115        R0 = -1;     // Change this to mask interrupts (*)
116        [ P0 ] = R0;   // IMASK
117
118LD32_LABEL(p1, START);
119
120LD32(p0, EVT15);
121        [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
122CSYNC;
123RAISE 15;    // after we RTI, INT 15 should be taken
124
125LD32_LABEL(r7, START);
126RETI = r7;
127NOP;        // Workaround for Bug 217
128RTI;
129NOP;
130NOP;
131NOP;
132NOP;
133NOP;
134NOP;
135NOP;
136NOP;
137DUMMY:
138	  NOP;
139NOP;
140NOP;
141NOP;
142NOP;
143NOP;
144NOP;
145NOP;
146NOP;
147NOP;
148
149//.code 0x200
150 START :
151        R7 = 0x0;
152        R6 = 0x1;
153        [ -- SP ] = RETI;        // Enable Nested Interrupts
154
155CLI R1;                                           // stop interrupt
156WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
157WR_MMR(TPERIOD, 0x00000050, p0, r0);
158WR_MMR(TCOUNT,  0x00000013, p0, r0);
159WR_MMR(TSCALE,  0x00000000, p0, r0);
160CSYNC;
161        // Read the contents of the Timer
162
163RD_MMR(TPERIOD, p0, r2);
164CHECKREG(r2,    0x00000050);
165
166//      RD_MMR(TCOUNT, p0, r3);
167//      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
168
169
170WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
171CSYNC;
172
173RD_MMR(TPERIOD, p0, r4);
174CHECKREG(r4,    0x00000050);
175
176//      RD_MMR(TCNTL, p0, r5);
177//      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
178
179WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
180CSYNC;
181NOP;
182WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
183WR_MMR(TPERIOD, 0x00000015, p0, r0);
184WR_MMR(TCOUNT,  0x00000013, p0, r0);
185WR_MMR(TSCALE,  0x00000002, p0, r0);
186WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
187CSYNC;
188NOP;
189NOP;
190NOP;
191NOP;
192NOP;
193NOP;
194NOP;
195NOP;
196NOP;
197NOP;
198NOP;
199NOP;
200NOP;
201NOP;
202NOP;
203JUMP.S label4;
204        R4.L = 0x1111;                             // Will be killed
205        R4.H = 0x1111;                             // Will be killed
206NOP;
207NOP;
208NOP;
209label5: R5.H = 0x7777;
210        R5.L = 0x7888;
211JUMP.S label6;
212        R5.L = 0x1111;                             // Will be killed
213        R5.H = 0x1111;                             // Will be killed
214NOP;
215NOP;
216NOP;
217NOP;
218NOP;
219NOP;
220label4: R4.H = 0x5555;
221        R4.L = 0x6666;
222NOP;
223JUMP.S label5;
224        R5.L = 0x2222;     // Will be killed
225        R5.H = 0x2222;     // Will be killed
226NOP;
227NOP;
228NOP;
229NOP;
230label6: R3.H = 0x7999;
231        R3.L = 0x7aaa;
232NOP;
233NOP;
234NOP;
235NOP;
236NOP;
237NOP;
238NOP;
239                                                    // With auto reload
240        // Read the contents of the Timer
241
242RD_MMR(TPERIOD, p0, r2);
243CHECKREG(r2,    0x00000015);
244
245//      RD_MMR(TCNTL , p0, r3);
246//      CHECKREG(r3,    0x0000000F);
247CHECKREG(r7,    0x00000000);    // no interrupt being serviced
248WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
249CSYNC;
250STI R1;
251NOP;
252CHECKREG(r7,    0x00000001);    // interrupt being serviced
253//      WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
254//      csync;
255NOP;
256
257
258
259
260
261dbg_pass;        // Call Endtest Macro
262
263
264
265//*********************************************************************
266//
267// Handlers for Events
268//
269
270EHANDLE:            // Emulation Handler 0
271RTE;
272
273RHANDLE:            // Reset Handler 1
274RTI;
275
276NHANDLE:            // NMI Handler 2
277RTN;
278
279XHANDLE:            // Exception Handler 3
280RTX;
281
282HWHANDLE:           // HW Error Handler 5
283RTI;
284
285THANDLE:            // Timer Handler 6
286        R7 = R7 + R6;
287RTI;
288
289I7HANDLE:           // IVG 7 Handler
290RTI;
291
292I8HANDLE:           // IVG 8 Handler
293RTI;
294
295I9HANDLE:           // IVG 9 Handler
296RTI;
297
298I10HANDLE:          // IVG 10 Handler
299RTI;
300
301I11HANDLE:          // IVG 11 Handler
302RTI;
303
304I12HANDLE:          // IVG 12 Handler
305RTI;
306
307I13HANDLE:          // IVG 13 Handler
308RTI;
309
310I14HANDLE:          // IVG 14 Handler
311RTI;
312
313I15HANDLE:          // IVG 15 Handler
314        R5 = RETI;
315        P0 = R5;
316JUMP ( P0 );
317RTI;
318
319.section MEM_DATA_ADDR_1,"aw"
320
321.space (STACKSIZE);
322STACK:
323NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug
324