1//Original:/testcases/core/c_dsp32shiftim_af_s/c_dsp32shiftim_af_s.dsp 2# mach: bfin 3 4.include "testutils.inc" 5 start 6 7 8// Spec Reference: dsp32shiftimm ashift: ashift saturated 9 10 11imm32 r0, 0x81230001; 12imm32 r1, 0x19345678; 13imm32 r2, 0x23c56789; 14imm32 r3, 0x3ed6789a; 15imm32 r4, 0x85d789ab; 16imm32 r5, 0x967f9abc; 17imm32 r6, 0xa789bbcd; 18imm32 r7, 0xb891acde; 19R0 = R0 << 0 (S); 20R1 = R1 << 3 (S); 21R2 = R2 << 7 (S); 22R3 = R3 << 8 (S); 23R4 = R4 << 15 (S); 24R5 = R5 << 24 (S); 25R6 = R6 << 31 (S); 26R7 = R7 << 20 (S); 27CHECKREG r0, 0x81230001; 28CHECKREG r1, 0x7FFFFFFF; 29CHECKREG r2, 0x7FFFFFFF; 30CHECKREG r3, 0x7FFFFFFF; 31CHECKREG r4, 0x80000000; 32CHECKREG r5, 0x80000000; 33CHECKREG r6, 0x80000000; 34CHECKREG r7, 0x80000000; 35 36imm32 r0, 0xa1230001; 37imm32 r1, 0x1e345678; 38imm32 r2, 0x23f56789; 39imm32 r3, 0x34db789a; 40imm32 r4, 0x85a7a9ab; 41imm32 r5, 0x967c9abc; 42imm32 r6, 0xa78dabcd; 43imm32 r7, 0xb8914cde; 44R6 = R0 >>> 1; 45R7 = R1 >>> 3; 46R0 = R2 >>> 7; 47R1 = R3 >>> 8; 48R2 = R4 >>> 15; 49R3 = R5 >>> 24; 50R4 = R6 >>> 31; 51R5 = R7 >>> 20; 52CHECKREG r0, 0x0047EACF; 53CHECKREG r1, 0x0034DB78; 54CHECKREG r2, 0xFFFF0B4F; 55CHECKREG r3, 0xFFFFFF96; 56CHECKREG r4, 0xFFFFFFFF; 57CHECKREG r5, 0x0000003C; 58CHECKREG r6, 0xD0918000; 59CHECKREG r7, 0x03C68ACF; 60 61 62 63pass 64