1//Original:/testcases/core/c_dsp32shiftim_af/c_dsp32shiftim_af.dsp 2# mach: bfin 3 4.include "testutils.inc" 5 start 6 7 8// Spec Reference: dsp32shiftimm ashift: ashift 9 10 11imm32 r0, 0xa1230001; 12imm32 r1, 0x1b345678; 13imm32 r2, 0x23c56789; 14imm32 r3, 0x34d6789a; 15imm32 r4, 0x85a789ab; 16imm32 r5, 0x967c9abc; 17imm32 r6, 0xa789abcd; 18imm32 r7, 0xb8912cde; 19R0 = R0 << 0; 20R1 = R1 << 3; 21R2 = R2 << 7; 22R3 = R3 << 8; 23R4 = R4 << 15; 24R5 = R5 << 24; 25R6 = R6 << 31; 26R7 = R7 << 20; 27CHECKREG r0, 0xA1230001; 28CHECKREG r1, 0xD9A2B3C0; 29CHECKREG r2, 0xE2B3C480; 30CHECKREG r3, 0xD6789A00; 31CHECKREG r4, 0xC4D58000; 32CHECKREG r5, 0xBC000000; 33CHECKREG r6, 0x80000000; 34CHECKREG r7, 0xCDE00000; 35 36imm32 r0, 0xa1230001; 37imm32 r1, 0x1b345678; 38imm32 r2, 0x23c56789; 39imm32 r3, 0x34d6789a; 40imm32 r4, 0x85a789ab; 41imm32 r5, 0x967c9abc; 42imm32 r6, 0xa789abcd; 43imm32 r7, 0xb8912cde; 44R6 = R0 >>> 1; 45R7 = R1 >>> 3; 46R0 = R2 >>> 7; 47R1 = R3 >>> 8; 48R2 = R4 >>> 15; 49R3 = R5 >>> 24; 50R4 = R6 >>> 31; 51R5 = R7 >>> 20; 52CHECKREG r0, 0x00478ACF; 53CHECKREG r1, 0x0034D678; 54CHECKREG r2, 0xFFFF0B4F; 55CHECKREG r3, 0xFFFFFF96; 56CHECKREG r4, 0xFFFFFFFF; 57CHECKREG r5, 0x00000036; 58CHECKREG r6, 0xD0918000; 59CHECKREG r7, 0x03668ACF; 60 61 62 63pass 64