xref: /netbsd-src/external/gpl3/gdb/dist/sim/testsuite/bfin/c_dsp32shift_lmix.s (revision 4b169a6ba595ae283ca507b26b15fdff40495b1c) 
1//Original:/testcases/core/c_dsp32shift_lmix/c_dsp32shift_lmix.dsp
2// Spec Reference: dsp32shift lshift: mix
3# mach: bfin
4
5.include "testutils.inc"
6	start
7
8
9
10imm32 r4, 0x00000000;
11imm32 r5, 0x00000000;
12imm32 r6, 0x00000000;
13imm32 r7, 0x00000000;
14
15// lshift : positive data, count (+)=left (half reg)
16imm32 r0, 0x00010001;
17imm32 r1, 1;
18imm32 r2, 0x00020002;
19imm32 r3, 2;
20R4.H = LSHIFT R0.H BY R1.L;
21R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x00020002 */
22R5.H = LSHIFT R2.H BY R3.L;
23R5.L = LSHIFT R2.L BY R3.L; /* r5 = 0x00080008 */
24R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x00020002 */
25R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x00080008 */
26CHECKREG r4, 0x00020002;
27CHECKREG r5, 0x00080008;
28CHECKREG r6, 0x00020002;
29CHECKREG r7, 0x00080008;
30
31// lshift : (full reg)
32imm32 r1, 3;
33imm32 r3, 4;
34R6 = LSHIFT R0 BY R1.L; /* r6 = 0x00080010 */
35R7 = LSHIFT R2 BY R3.L;
36CHECKREG r6, 0x00080008; /* r7 = 0x00100010 */
37CHECKREG r7, 0x00200020;
38
39A0 = 0;
40A0.L = R0.L;
41A0.H = R0.H;
42A0 = LSHIFT A0 BY R1.L; /* a0 = 0x00080008 */
43R5 = A0.w; /* r5 = 0x00080008 */
44CHECKREG r5, 0x00080008;
45
46imm32 r4, 0x30000003;
47imm32 r1, 1;
48R6 = LSHIFT R4 BY R1.L; /* r5 = 0x60000006 */
49imm32 r1, 2;
50R7 = LSHIFT R4 BY R1.L; /* r5 = 0xc000000c like LSHIFT */
51CHECKREG r6, 0x60000006;
52CHECKREG r7, 0xc000000c;
53
54
55// lshift : count (-)=right (half reg)
56imm32 r0, 0x10001000;
57imm32 r1, -1;
58imm32 r2, 0x10001000;
59imm32 r3, -2;
60R4.H = LSHIFT R0.H BY R1.L;
61R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x08000800 */
62R5.H = LSHIFT R2.H BY R3.L;
63R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x04000400 */
64R6 = LSHIFT R0 BY R1.L (V); /* r4 = 0x08000800 */
65R7 = LSHIFT R2 BY R3.L (V); /* r4 = 0x04000400 */
66CHECKREG r4, 0x08000800;
67CHECKREG r5, 0x04000400;
68CHECKREG r6, 0x08000800;
69CHECKREG r7, 0x04000400;
70
71// lshift : (full reg)
72imm32 r1, -3;
73imm32 r3, -4;
74R6 = LSHIFT R0 BY R1.L; /* r6 = 0x02000200 */
75R7 = LSHIFT R2 BY R3.L; /* r7 = 0x01000100 */
76CHECKREG r6, 0x02000200;
77CHECKREG r7, 0x01000100;
78
79// NEGATIVE
80// lshift : NEGATIVE data, count (+)=left (half reg)
81imm32 r0, 0xc00f800f;
82imm32 r1, 1;
83imm32 r2, 0xe00fe00f;
84imm32 r3, 2;
85R4.H = LSHIFT R0.H BY R1.L;
86R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x801e001e */
87R5.H = LSHIFT R2.H BY R3.L;
88R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x803c803c */
89CHECKREG r4, 0x801e001e;
90CHECKREG r5, 0x803c803c;
91
92imm32 r0, 0xc80fe00f;
93imm32 r2, 0xe40fe00f;
94imm32 r1, 4;
95imm32 r3, 5;
96R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
97R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
98CHECKREG r6, 0x80fe00f0;
99CHECKREG r7, 0x81fc01e0;
100
101imm32 r0, 0xf80fe00f;
102imm32 r2, 0xfc0fe00f;
103R6 = LSHIFT R0 BY R1.L; /* r6 = 0x80fe00f0 */
104R7 = LSHIFT R2 BY R3.L; /* r7 = 0x81fc01e0 */
105CHECKREG r6, 0x80fe00f0;
106CHECKREG r7, 0x81fc01e0;
107
108
109
110// lshift : NEGATIVE data, count (-)=right (half reg) Working ok
111imm32 r0, 0x80f080f0;
112imm32 r1, -1;
113imm32 r2, 0x80f080f0;
114imm32 r3, -2;
115R4.H = LSHIFT R0.H BY R1.L;
116R4.L = LSHIFT R0.L BY R1.L; /* r4 = 0x40784078 */
117R5.H = LSHIFT R2.H BY R3.L;
118R5.L = LSHIFT R2.L BY R3.L; /* r4 = 0x203c203c */
119CHECKREG r4, 0x40784078;
120CHECKREG r5, 0x203c203c;
121R6 = LSHIFT R0 BY R1.L (V); /* r6 = 0x40784078 */
122R7 = LSHIFT R2 BY R3.L (V); /* r7 = 0x203c203c */
123CHECKREG r6, 0x40784078;
124CHECKREG r7, 0x203c203c;
125
126// lshift : (full reg)
127imm32 r1, -3;
128imm32 r3, -4;
129R6 = LSHIFT R0 BY R1.L; /* r6 = 0x101e101e */
130R7 = LSHIFT R2 BY R3.L; /* r7 = 0x080f080f */
131CHECKREG r6, 0x101e101e;
132CHECKREG r7, 0x080f080f;
133
134
135
136pass
137