1//Original:/testcases/core/c_dsp32alu_sgn/c_dsp32alu_sgn.dsp 2// Spec Reference: dsp32alu dreg_lo(hi) = rnd dregs 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8imm32 r0, 0x456789ab; 9imm32 r1, 0x6689abcd; 10imm32 r2, 0x47445555; 11imm32 r3, 0x68667777; 12R4.H = R4.L = SIGN(R2.H) * R0.H + SIGN(R2.L) * R0.L; 13R5.H = R5.L = SIGN(R2.H) * R1.H + SIGN(R2.L) * R1.L; 14R6.H = R6.L = SIGN(R2.H) * R2.H + SIGN(R2.L) * R2.L; 15R7.H = R7.L = SIGN(R2.H) * R3.H + SIGN(R2.L) * R3.L; 16CHECKREG r4, 0xCF12CF12; 17CHECKREG r5, 0x12561256; 18CHECKREG r6, 0x9C999C99; 19CHECKREG r7, 0xDFDDDFDD; 20 21imm32 r0, 0x496789ab; 22imm32 r1, 0x6489abcd; 23imm32 r2, 0x4b445555; 24imm32 r3, 0x6c647777; 25imm32 r4, 0x8d889999; 26imm32 r5, 0xaeaa4bbb; 27imm32 r6, 0xcfccd44d; 28imm32 r7, 0xe1eefff4; 29R0.H = R0.L = SIGN(R3.H) * R4.H + SIGN(R3.L) * R4.L; 30R1.H = R1.L = SIGN(R3.H) * R5.H + SIGN(R3.L) * R5.L; 31R2.H = R2.L = SIGN(R3.H) * R6.H + SIGN(R3.L) * R6.L; 32R3.H = R3.L = SIGN(R3.H) * R7.H + SIGN(R3.L) * R7.L; 33CHECKREG r0, 0x27212721; 34CHECKREG r1, 0xFA65FA65; 35CHECKREG r2, 0xA419A419; 36CHECKREG r3, 0xE1E2E1E2; 37 38 39pass 40