1//Original:/testcases/core/c_dsp32alu_minmin/c_dsp32alu_minmin.dsp 2// Spec Reference: dsp32alu dregs = min / min ( dregs, dregs) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9 10 11imm32 r0, 0x25678911; 12imm32 r1, 0x2389ab1d; 13imm32 r2, 0x2a445345; 14imm32 r3, 0x46657717; 15imm32 r4, 0xd567e91b; 16imm32 r5, 0x6789af1d; 17imm32 r6, 0x74445d85; 18imm32 r7, 0x8666a779; 19R0 = MIN ( R0 , R0 ) (V); 20R1 = MIN ( R0 , R1 ) (V); 21R2 = MIN ( R0 , R2 ) (V); 22R3 = MIN ( R0 , R3 ) (V); 23R4 = MIN ( R0 , R4 ) (V); 24R5 = MIN ( R0 , R5 ) (V); 25R6 = MIN ( R0 , R6 ) (V); 26R7 = MIN ( R0 , R7 ) (V); 27CHECKREG r0, 0x25678911; 28CHECKREG r1, 0x23898911; 29CHECKREG r2, 0x25678911; 30CHECKREG r3, 0x25678911; 31CHECKREG r4, 0xD5678911; 32CHECKREG r5, 0x25678911; 33CHECKREG r6, 0x25678911; 34CHECKREG r7, 0x86668911; 35 36imm32 r0, 0x9567892b; 37imm32 r1, 0xa789ab2d; 38imm32 r2, 0xb4445525; 39imm32 r3, 0xc6667727; 40imm32 r4, 0xd8889929; 41imm32 r5, 0xeaaabb2b; 42imm32 r6, 0xfcccdd2d; 43imm32 r7, 0x0eeeffff; 44R0 = MIN ( R1 , R0 ) (V); 45R1 = MIN ( R1 , R1 ) (V); 46R2 = MIN ( R1 , R2 ) (V); 47R3 = MIN ( R1 , R3 ) (V); 48R4 = MIN ( R1 , R4 ) (V); 49R5 = MIN ( R1 , R5 ) (V); 50R6 = MIN ( R1 , R6 ) (V); 51R7 = MIN ( R1 , R7 ) (V); 52CHECKREG r0, 0x9567892B; 53CHECKREG r1, 0xA789AB2D; 54CHECKREG r2, 0xA789AB2D; 55CHECKREG r3, 0xA789AB2D; 56CHECKREG r4, 0xA7899929; 57CHECKREG r5, 0xA789AB2D; 58CHECKREG r6, 0xA789AB2D; 59CHECKREG r7, 0xA789AB2D; 60 61imm32 r0, 0x416789ab; 62imm32 r1, 0x5289abcd; 63imm32 r2, 0x43445555; 64imm32 r3, 0xa466a777; 65imm32 r4, 0x45678dab; 66imm32 r5, 0xf689abcd; 67imm32 r6, 0x47445555; 68imm32 r7, 0x68667777; 69R0 = MIN ( R2 , R0 ) (V); 70R1 = MIN ( R2 , R1 ) (V); 71R2 = MIN ( R2 , R2 ) (V); 72R3 = MIN ( R2 , R3 ) (V); 73R4 = MIN ( R2 , R4 ) (V); 74R5 = MIN ( R2 , R5 ) (V); 75R6 = MIN ( R2 , R6 ) (V); 76R7 = MIN ( R2 , R7 ) (V); 77CHECKREG r0, 0x416789AB; 78CHECKREG r1, 0x4344ABCD; 79CHECKREG r2, 0x43445555; 80CHECKREG r3, 0xA466A777; 81CHECKREG r4, 0x43448DAB; 82CHECKREG r5, 0xF689ABCD; 83CHECKREG r6, 0x43445555; 84CHECKREG r7, 0x43445555; 85 86imm32 r0, 0x9567892b; 87imm32 r1, 0xa789ab2d; 88imm32 r2, 0xb4445525; 89imm32 r3, 0xc6667727; 90imm32 r0, 0x9567892b; 91imm32 r1, 0xa789ab2d; 92imm32 r2, 0xb4445525; 93imm32 r3, 0xc6667727; 94R0 = MIN ( R3 , R0 ) (V); 95R1 = MIN ( R3 , R1 ) (V); 96R2 = MIN ( R3 , R2 ) (V); 97R3 = MIN ( R3 , R3 ) (V); 98R4 = MIN ( R3 , R4 ) (V); 99R5 = MIN ( R3 , R5 ) (V); 100R6 = MIN ( R3 , R6 ) (V); 101R7 = MIN ( R3 , R7 ) (V); 102CHECKREG r0, 0x9567892B; 103CHECKREG r1, 0xA789AB2D; 104CHECKREG r2, 0xB4445525; 105CHECKREG r3, 0xC6667727; 106CHECKREG r4, 0xC6668DAB; 107CHECKREG r5, 0xC666ABCD; 108CHECKREG r6, 0xC6665555; 109CHECKREG r7, 0xC6665555; 110 111imm32 r0, 0x5537891b; 112imm32 r1, 0x6759ab2d; 113imm32 r2, 0x74555535; 114imm32 r3, 0x86665747; 115imm32 r4, 0x98789565; 116imm32 r5, 0xaa8abb5b; 117imm32 r6, 0xcc9cdd85; 118imm32 r7, 0xeeaeff9f; 119R0 = MIN ( R4 , R0 ) (V); 120R1 = MIN ( R4 , R1 ) (V); 121R2 = MIN ( R4 , R2 ) (V); 122R3 = MIN ( R4 , R3 ) (V); 123R4 = MIN ( R4 , R4 ) (V); 124R5 = MIN ( R4 , R5 ) (V); 125R6 = MIN ( R4 , R6 ) (V); 126R7 = MIN ( R4 , R7 ) (V); 127CHECKREG r0, 0x9878891B; 128CHECKREG r1, 0x98789565; 129CHECKREG r2, 0x98789565; 130CHECKREG r3, 0x86669565; 131CHECKREG r4, 0x98789565; 132CHECKREG r5, 0x98789565; 133CHECKREG r6, 0x98789565; 134CHECKREG r7, 0x98789565; 135 136imm32 r0, 0x256b89ab; 137imm32 r1, 0x64764bcd; 138imm32 r2, 0x49736564; 139imm32 r3, 0x61278394; 140imm32 r4, 0x98876439; 141imm32 r5, 0xaaaa0bbb; 142imm32 r6, 0xcccc1ddd; 143imm32 r7, 0x43346fff; 144R0 = MIN ( R5 , R0 ) (V); 145R1 = MIN ( R5 , R1 ) (V); 146R2 = MIN ( R5 , R2 ) (V); 147R3 = MIN ( R5 , R3 ) (V); 148R4 = MIN ( R5 , R4 ) (V); 149R5 = MIN ( R5 , R5 ) (V); 150R6 = MIN ( R5 , R6 ) (V); 151R7 = MIN ( R5 , R7 ) (V); 152CHECKREG r0, 0xAAAA89AB; 153CHECKREG r1, 0xAAAA0BBB; 154CHECKREG r2, 0xAAAA0BBB; 155CHECKREG r3, 0xAAAA8394; 156CHECKREG r4, 0x98870BBB; 157CHECKREG r5, 0xAAAA0BBB; 158CHECKREG r6, 0xAAAA0BBB; 159CHECKREG r7, 0xAAAA0BBB; 160 161imm32 r0, 0x456739ab; 162imm32 r1, 0x67694bcd; 163imm32 r2, 0x03456755; 164imm32 r3, 0x66666777; 165imm32 r4, 0x12345699; 166imm32 r5, 0x45678b6b; 167imm32 r6, 0x043290d6; 168imm32 r7, 0x1234567f; 169R0 = MIN ( R6 , R0 ) (V); 170R1 = MIN ( R6 , R1 ) (V); 171R2 = MIN ( R6 , R2 ) (V); 172R3 = MIN ( R6 , R3 ) (V); 173R4 = MIN ( R6 , R4 ) (V); 174R5 = MIN ( R6 , R5 ) (V); 175R6 = MIN ( R6 , R6 ) (V); 176R7 = MIN ( R6 , R7 ) (V); 177CHECKREG r0, 0x043290D6; 178CHECKREG r1, 0x043290D6; 179CHECKREG r2, 0x034590D6; 180CHECKREG r3, 0x043290D6; 181CHECKREG r4, 0x043290D6; 182CHECKREG r5, 0x04328B6B; 183CHECKREG r6, 0x043290D6; 184CHECKREG r7, 0x043290D6; 185 186imm32 r0, 0x976789ab; 187imm32 r1, 0x6779abcd; 188imm32 r2, 0x8345a755; 189imm32 r3, 0x5678b007; 190imm32 r4, 0x789ab799; 191imm32 r5, 0xaaaa0bbb; 192imm32 r6, 0x89ab1d7d; 193imm32 r7, 0xabcd2ff7; 194R0 = MIN ( R7 , R0 ) (V); 195R1 = MIN ( R7 , R1 ) (V); 196R2 = MIN ( R7 , R2 ) (V); 197R3 = MIN ( R7 , R3 ) (V); 198R4 = MIN ( R7 , R4 ) (V); 199R5 = MIN ( R7 , R5 ) (V); 200R6 = MIN ( R7 , R6 ) (V); 201R7 = MIN ( R7 , R7 ) (V); 202CHECKREG r0, 0x976789AB; 203CHECKREG r1, 0xABCDABCD; 204CHECKREG r2, 0x8345A755; 205CHECKREG r3, 0xABCDB007; 206CHECKREG r4, 0xABCDB799; 207CHECKREG r5, 0xAAAA0BBB; 208CHECKREG r6, 0x89AB1D7D; 209CHECKREG r7, 0xABCD2FF7; 210imm32 r0, 0x456739ab; 211imm32 r1, 0x67694bcd; 212imm32 r2, 0x03456755; 213imm32 r3, 0x66666777; 214imm32 r4, 0x12345699; 215imm32 r5, 0x45678b6b; 216imm32 r6, 0x043290d6; 217imm32 r7, 0x1234567f; 218R4 = MIN ( R4 , R7 ) (V); 219R5 = MIN ( R5 , R5 ) (V); 220R2 = MIN ( R6 , R3 ) (V); 221R6 = MIN ( R0 , R4 ) (V); 222R0 = MIN ( R1 , R6 ) (V); 223R2 = MIN ( R2 , R1 ) (V); 224R1 = MIN ( R3 , R0 ) (V); 225R7 = MIN ( R7 , R4 ) (V); 226CHECKREG r0, 0x123439AB; 227CHECKREG r1, 0x123439AB; 228CHECKREG r2, 0x043290D6; 229CHECKREG r3, 0x66666777; 230CHECKREG r4, 0x1234567F; 231CHECKREG r5, 0x45678B6B; 232CHECKREG r6, 0x123439AB; 233CHECKREG r7, 0x1234567F; 234 235imm32 r0, 0xa76789ab; 236imm32 r1, 0x6779abcd; 237imm32 r2, 0xb3456755; 238imm32 r3, 0x5678d007; 239imm32 r4, 0x789ab799; 240imm32 r5, 0xaaaa0bbb; 241imm32 r6, 0x89ab1d7d; 242imm32 r7, 0xabcd2ff7; 243R3 = MIN ( R4 , R0 ) (V); 244R5 = MIN ( R5 , R1 ) (V); 245R2 = MIN ( R2 , R2 ) (V); 246R7 = MIN ( R7 , R3 ) (V); 247R4 = MIN ( R3 , R4 ) (V); 248R0 = MIN ( R1 , R5 ) (V); 249R1 = MIN ( R0 , R6 ) (V); 250R6 = MIN ( R6 , R7 ) (V); 251CHECKREG r0, 0xAAAAABCD; 252CHECKREG r1, 0x89ABABCD; 253CHECKREG r2, 0xB3456755; 254CHECKREG r3, 0xA76789AB; 255CHECKREG r4, 0xA76789AB; 256CHECKREG r5, 0xAAAAABCD; 257CHECKREG r6, 0x89AB89AB; 258CHECKREG r7, 0xA76789AB; 259 260 261pass 262