1//Original:/testcases/core/c_cc_regmvlogi_mvbrsft_s1/c_cc_regmvlogi_mvbrsft_s1.dsp 2// Spec Reference: cc: set (regmv & logi2op) used (ccmv & brcc & dsp32sft) 3# mach: bfin 4 5.include "testutils.inc" 6 start 7 8 9A0 = 0; 10A1 = 0; 11 12imm32 r0, 0x00000020; // cc=1 13imm32 r1, 0x00000000; // cc=0 14imm32 r2, 0x62b61557; 15imm32 r3, 0x07300007; 16imm32 r4, 0x00740088; 17imm32 r5, 0x609950aa; 18imm32 r6, 0x20bb06cc; 19imm32 r7, 0x00000002; 20 21 22ASTAT = R0; // cc=1 REGMV 23R5 = R0 + R2; // comp3op dr plus dr 24IF CC R1 = R3; // ccmov 25ASTAT = R1; // cc=0 REGMV 26R4 >>= R7; // alu2op sft 27IF CC R3 = R2; // ccmv 28CC = R0 < R1; // ccflag 29R3.H = R1.L + R3.H (S); // dsp32alu 30IF CC R4 = R5; // ccmv 31CC = ! BITTST( R0 , 4 ); // cc = 0 32R1 = R0 +|- R1 , R6 = R0 -|+ R1 (ASR); // dsp32alu sft 33IF CC R4 = R5; // ccmv 34CC = BITTST ( R1 , 4 ); // cc = 0 35R3.L = R5.L << 1; // dsp32shiftim 36IF !CC JUMP LABEL1; // branch 37CC = ! CC; 38R1 = ( A1 = R7.L * R4.L ), R0 = ( A0 = R7.H * R4.H ) (S2RND); // dsp32mac pair 39IF !CC JUMP LABEL2 (BP); // branch 40LABEL1: 41 R2 = R0 + R2; 42JUMP.S END; 43LABEL2: 44 R7 = R5 - R3; 45CC = R0 < R1; // ccflag 46R5 = R0 + R2; // comp3op dr plus dr 47IF CC JUMP END (BP); // branch on 48R4 = R5 + R7; 49 50END: 51 52CHECKREG r0, 0x00000020; 53CHECKREG r1, 0x0398000C; 54CHECKREG r2, 0x62B61577; 55CHECKREG r3, 0x07372AEE; 56CHECKREG r4, 0x62B61577; 57CHECKREG r5, 0x62B61577; 58CHECKREG r6, 0xFC680013; 59CHECKREG r7, 0x00000002; 60 61imm32 r0, 0x00000020; 62imm32 r1, 0x00000000; 63imm32 r2, 0x62661557; 64imm32 r3, 0x073b0007; 65imm32 r4, 0x01f49088; 66imm32 r5, 0x6e2959aa; 67imm32 r6, 0xa0b506cc; 68imm32 r7, 0x00000002; 69 70 71 ASTAT = R0; // cc=1 REGMV 72 R4.H = R1.L + R0.L (S); // dsp32alu 73 R2 = ROT R2 BY 1; // dsp32shiftim_rot 74 ASTAT = R1; // cc=0 REGMV 75 A1 = R2.L * R3.L, A0 += R2.L * R3.H; // dsp32mac 76 R3 = ROT R3 BY 1; // dsp32shiftim_rot 77 CC = ! BITTST( R0 , 4 ); // cc = 0 78 R4.L = R5.L << 1; // dsp32shiftimm 79 R6 = ROT R4 BY 5; // dsp32shiftim_rot 80 CC = BITTST ( R1 , 4 ); // cc = 0 81 R7 = R0 + R2; // comp3op dr plus dr 82 IF CC R4 = R5; // ccmov 83 A0 += A1 (W32); // dsp32alu a0 + a1 84 CC = BITTST ( R0 , 4 ); // cc = 1 85 R5 = ROT R6 BY R7.L; 86 R0 = A0.w; 87 R1 = A1.w; 88 89CHECKREG r0, 0x026B943C; 90CHECKREG r1, 0x00025592; 91CHECKREG r2, 0xC4CC2AAF; 92CHECKREG r3, 0x0E76000E; 93CHECKREG r4, 0x0020B354; 94CHECKREG r5, 0x35480105; 95CHECKREG r6, 0x04166A90; 96CHECKREG r7, 0xC4CC2ACF; 97 98pass 99