1 /* Simulator for the Renesas (formerly Hitachi) / SuperH Inc. SH architecture. 2 3 Written by Steve Chamberlain of Cygnus Support. 4 sac@cygnus.com 5 6 This file is part of SH sim 7 8 9 THIS SOFTWARE IS NOT COPYRIGHTED 10 11 Cygnus offers the following for use in the public domain. Cygnus 12 makes no warranty with regard to the software or it's performance 13 and the user accepts the software "AS IS" with all faults. 14 15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO 16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. 18 19 */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include <ctype.h> 25 #include <stdio.h> 26 #include <errno.h> 27 #include <signal.h> 28 #include <unistd.h> 29 #ifdef HAVE_MMAP 30 #include <sys/mman.h> 31 # ifndef MAP_FAILED 32 # define MAP_FAILED -1 33 # endif 34 # if !defined (MAP_ANONYMOUS) && defined (MAP_ANON) 35 # define MAP_ANONYMOUS MAP_ANON 36 # endif 37 #endif 38 39 #include <string.h> 40 #include <stdlib.h> 41 #include <sys/stat.h> 42 #include <time.h> 43 #include <sys/time.h> 44 #ifdef HAVE_UTIME_H 45 #include <utime.h> 46 #endif 47 #ifndef _WIN32 48 #include <sys/wait.h> 49 #endif 50 51 #include "bfd.h" 52 #include "sim/callback.h" 53 #include "sim/sim.h" 54 #include "sim/sim-sh.h" 55 56 #include "sim-main.h" 57 #include "sim-base.h" 58 #include "sim-options.h" 59 60 #include "target-newlib-syscall.h" 61 62 #include "sh-sim.h" 63 64 #include <math.h> 65 66 #ifdef _WIN32 67 #include <float.h> /* Needed for _isnan() */ 68 #ifndef isnan 69 #define isnan _isnan 70 #endif 71 #endif 72 73 #ifndef SIGBUS 74 #define SIGBUS SIGSEGV 75 #endif 76 77 #ifndef SIGQUIT 78 #define SIGQUIT SIGTERM 79 #endif 80 81 #ifndef SIGTRAP 82 #define SIGTRAP 5 83 #endif 84 85 /* TODO: Stop using these names. */ 86 #undef SEXT 87 #undef SEXT32 88 89 extern unsigned short sh_jump_table[], sh_dsp_table[0x1000], ppi_table[]; 90 91 #define O_RECOMPILE 85 92 #define DEFINE_TABLE 93 #define DISASSEMBLER_TABLE 94 95 /* Define the rate at which the simulator should poll the host 96 for a quit. */ 97 #define POLL_QUIT_INTERVAL 0x60000 98 99 /* TODO: Move into sim_cpu. */ 100 saved_state_type saved_state; 101 102 struct loop_bounds { unsigned char *start, *end; }; 103 104 /* These variables are at file scope so that functions other than 105 sim_resume can use the fetch/store macros */ 106 107 #define target_little_endian (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE) 108 static int global_endianw, endianb; 109 static int target_dsp; 110 #define host_little_endian (HOST_BYTE_ORDER == BFD_ENDIAN_LITTLE) 111 112 static int maskw = 0; 113 static int maskl = 0; 114 115 /* Short hand definitions of the registers */ 116 117 #define SBIT(x) ((x)&sbit) 118 #define R0 saved_state.asregs.regs[0] 119 #define Rn saved_state.asregs.regs[n] 120 #define Rm saved_state.asregs.regs[m] 121 #define UR0 (unsigned int) (saved_state.asregs.regs[0]) 122 #define UR (unsigned int) R 123 #define UR (unsigned int) R 124 #define SR0 saved_state.asregs.regs[0] 125 #define CREG(n) (saved_state.asregs.cregs[(n)]) 126 #define GBR saved_state.asregs.gbr 127 #define VBR saved_state.asregs.vbr 128 #define DBR saved_state.asregs.dbr 129 #define TBR saved_state.asregs.tbr 130 #define IBCR saved_state.asregs.ibcr 131 #define IBNR saved_state.asregs.ibnr 132 #define BANKN (saved_state.asregs.ibnr & 0x1ff) 133 #define ME ((saved_state.asregs.ibnr >> 14) & 0x3) 134 #define SSR saved_state.asregs.ssr 135 #define SPC saved_state.asregs.spc 136 #define SGR saved_state.asregs.sgr 137 #define SREG(n) (saved_state.asregs.sregs[(n)]) 138 #define MACH saved_state.asregs.mach 139 #define MACL saved_state.asregs.macl 140 #define PR saved_state.asregs.pr 141 #define FPUL saved_state.asregs.fpul 142 143 #define PC insn_ptr 144 145 146 147 /* Alternate bank of registers r0-r7 */ 148 149 /* Note: code controling SR handles flips between BANK0 and BANK1 */ 150 #define Rn_BANK(n) (saved_state.asregs.bank[(n)]) 151 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.bank[(n)] = (EXP); } while (0) 152 153 154 /* Manipulate SR */ 155 156 #define SR_MASK_BO (1 << 14) 157 #define SR_MASK_CS (1 << 13) 158 #define SR_MASK_DMY (1 << 11) 159 #define SR_MASK_DMX (1 << 10) 160 #define SR_MASK_M (1 << 9) 161 #define SR_MASK_Q (1 << 8) 162 #define SR_MASK_I (0xf << 4) 163 #define SR_MASK_S (1 << 1) 164 #define SR_MASK_T (1 << 0) 165 166 #define SR_MASK_BL (1 << 28) 167 #define SR_MASK_RB (1 << 29) 168 #define SR_MASK_MD (1 << 30) 169 #define SR_MASK_RC 0x0fff0000 170 #define SR_RC_INCREMENT -0x00010000 171 172 #define BO ((saved_state.asregs.sr & SR_MASK_BO) != 0) 173 #define CS ((saved_state.asregs.sr & SR_MASK_CS) != 0) 174 #define M ((saved_state.asregs.sr & SR_MASK_M) != 0) 175 #define Q ((saved_state.asregs.sr & SR_MASK_Q) != 0) 176 #define S ((saved_state.asregs.sr & SR_MASK_S) != 0) 177 #define T ((saved_state.asregs.sr & SR_MASK_T) != 0) 178 #define LDST ((saved_state.asregs.ldst) != 0) 179 180 #define SR_BL ((saved_state.asregs.sr & SR_MASK_BL) != 0) 181 #define SR_RB ((saved_state.asregs.sr & SR_MASK_RB) != 0) 182 #define SR_MD ((saved_state.asregs.sr & SR_MASK_MD) != 0) 183 #define SR_DMY ((saved_state.asregs.sr & SR_MASK_DMY) != 0) 184 #define SR_DMX ((saved_state.asregs.sr & SR_MASK_DMX) != 0) 185 #define SR_RC ((saved_state.asregs.sr & SR_MASK_RC)) 186 187 /* Note: don't use this for privileged bits */ 188 #define SET_SR_BIT(EXP, BIT) \ 189 do { \ 190 if ((EXP) & 1) \ 191 saved_state.asregs.sr |= (BIT); \ 192 else \ 193 saved_state.asregs.sr &= ~(BIT); \ 194 } while (0) 195 196 #define SET_SR_BO(EXP) SET_SR_BIT ((EXP), SR_MASK_BO) 197 #define SET_SR_CS(EXP) SET_SR_BIT ((EXP), SR_MASK_CS) 198 #define SET_BANKN(EXP) \ 199 do { \ 200 IBNR = (IBNR & 0xfe00) | ((EXP) & 0x1f); \ 201 } while (0) 202 #define SET_ME(EXP) \ 203 do { \ 204 IBNR = (IBNR & 0x3fff) | (((EXP) & 0x3) << 14); \ 205 } while (0) 206 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M) 207 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q) 208 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S) 209 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T) 210 #define SET_LDST(EXP) (saved_state.asregs.ldst = ((EXP) != 0)) 211 212 /* stc currently relies on being able to read SR without modifications. */ 213 #define GET_SR() (saved_state.asregs.sr - 0) 214 215 #define SET_SR(x) set_sr (x) 216 217 #define SET_RC(x) \ 218 (saved_state.asregs.sr \ 219 = (saved_state.asregs.sr & 0xf000ffff) | ((x) & 0xfff) << 16) 220 221 /* Manipulate FPSCR */ 222 223 #define FPSCR_MASK_FR (1 << 21) 224 #define FPSCR_MASK_SZ (1 << 20) 225 #define FPSCR_MASK_PR (1 << 19) 226 227 #define FPSCR_FR ((GET_FPSCR () & FPSCR_MASK_FR) != 0) 228 #define FPSCR_SZ ((GET_FPSCR () & FPSCR_MASK_SZ) != 0) 229 #define FPSCR_PR ((GET_FPSCR () & FPSCR_MASK_PR) != 0) 230 231 static void 232 set_fpscr1 (int x) 233 { 234 int old = saved_state.asregs.fpscr; 235 saved_state.asregs.fpscr = (x); 236 /* swap the floating point register banks */ 237 if ((saved_state.asregs.fpscr ^ old) & FPSCR_MASK_FR 238 /* Ignore bit change if simulating sh-dsp. */ 239 && ! target_dsp) 240 { 241 union fregs_u tmpf = saved_state.asregs.fregs[0]; 242 saved_state.asregs.fregs[0] = saved_state.asregs.fregs[1]; 243 saved_state.asregs.fregs[1] = tmpf; 244 } 245 } 246 247 /* sts relies on being able to read fpscr directly. */ 248 #define GET_FPSCR() (saved_state.asregs.fpscr) 249 #define SET_FPSCR(x) \ 250 do { \ 251 set_fpscr1 (x); \ 252 } while (0) 253 254 #define DSR (saved_state.asregs.fpscr) 255 256 #define RAISE_EXCEPTION(x) \ 257 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0) 258 259 #define RAISE_EXCEPTION_IF_IN_DELAY_SLOT() \ 260 if (in_delay_slot) RAISE_EXCEPTION (SIGILL) 261 262 /* This function exists mainly for the purpose of setting a breakpoint to 263 catch simulated bus errors when running the simulator under GDB. */ 264 265 static void 266 raise_exception (int x) 267 { 268 RAISE_EXCEPTION (x); 269 } 270 271 static void 272 raise_buserror (void) 273 { 274 raise_exception (SIGBUS); 275 } 276 277 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \ 278 forbidden_addr_bits, data, retval) \ 279 do { \ 280 if (addr & forbidden_addr_bits) \ 281 { \ 282 raise_buserror (); \ 283 return retval; \ 284 } \ 285 else if ((addr & saved_state.asregs.xyram_select) \ 286 == saved_state.asregs.xram_start) \ 287 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \ 288 else if ((addr & saved_state.asregs.xyram_select) \ 289 == saved_state.asregs.yram_start) \ 290 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \ 291 else if ((unsigned) addr >> 24 == 0xf0 \ 292 && bits_written == 32 && (data & 1) == 0) \ 293 /* This invalidates (if not associative) or might invalidate \ 294 (if associative) an instruction cache line. This is used for \ 295 trampolines. Since we don't simulate the cache, this is a no-op \ 296 as far as the simulator is concerned. */ \ 297 return retval; \ 298 else \ 299 { \ 300 if (bits_written == 8 && addr > 0x5000000) \ 301 IOMEM (addr, 1, data); \ 302 /* We can't do anything useful with the other stuff, so fail. */ \ 303 raise_buserror (); \ 304 return retval; \ 305 } \ 306 } while (0) 307 308 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume 309 being implemented by ../common/sim_resume.c and the below should 310 make a call to sim_engine_halt */ 311 312 #define BUSERROR(addr, mask) ((addr) & (mask)) 313 314 #define WRITE_BUSERROR(addr, mask, data, addr_func) \ 315 do \ 316 { \ 317 if (addr & mask) \ 318 { \ 319 addr_func (addr, data); \ 320 return; \ 321 } \ 322 } \ 323 while (0) 324 325 #define READ_BUSERROR(addr, mask, addr_func) \ 326 do \ 327 { \ 328 if (addr & mask) \ 329 return addr_func (addr); \ 330 } \ 331 while (0) 332 333 /* Define this to enable register lifetime checking. 334 The compiler generates "add #0,rn" insns to mark registers as invalid, 335 the simulator uses this info to call fail if it finds a ref to an invalid 336 register before a def 337 338 #define PARANOID 339 */ 340 341 #ifdef PARANOID 342 int valid[16]; 343 #define CREF(x) if (!valid[x]) fail (); 344 #define CDEF(x) valid[x] = 1; 345 #define UNDEF(x) valid[x] = 0; 346 #else 347 #define CREF(x) 348 #define CDEF(x) 349 #define UNDEF(x) 350 #endif 351 352 static void parse_and_set_memory_size (SIM_DESC sd, const char *str); 353 static int IOMEM (int addr, int write, int value); 354 static struct loop_bounds get_loop_bounds (int, int, unsigned char *, 355 unsigned char *, int, int); 356 static void process_wlat_addr (int, int); 357 static void process_wwat_addr (int, int); 358 static void process_wbat_addr (int, int); 359 static int process_rlat_addr (int); 360 static int process_rwat_addr (int); 361 static int process_rbat_addr (int); 362 363 /* Floating point registers */ 364 365 #define DR(n) (get_dr (n)) 366 static double 367 get_dr (int n) 368 { 369 n = (n & ~1); 370 if (host_little_endian) 371 { 372 union 373 { 374 int i[2]; 375 double d; 376 } dr; 377 dr.i[1] = saved_state.asregs.fregs[0].i[n + 0]; 378 dr.i[0] = saved_state.asregs.fregs[0].i[n + 1]; 379 return dr.d; 380 } 381 else 382 return (saved_state.asregs.fregs[0].d[n >> 1]); 383 } 384 385 #define SET_DR(n, EXP) set_dr ((n), (EXP)) 386 static void 387 set_dr (int n, double exp) 388 { 389 n = (n & ~1); 390 if (host_little_endian) 391 { 392 union 393 { 394 int i[2]; 395 double d; 396 } dr; 397 dr.d = exp; 398 saved_state.asregs.fregs[0].i[n + 0] = dr.i[1]; 399 saved_state.asregs.fregs[0].i[n + 1] = dr.i[0]; 400 } 401 else 402 saved_state.asregs.fregs[0].d[n >> 1] = exp; 403 } 404 405 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP)) 406 #define FI(n) (saved_state.asregs.fregs[0].i[(n)]) 407 408 #define FR(n) (saved_state.asregs.fregs[0].f[(n)]) 409 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP)) 410 411 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e)) 412 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f]) 413 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP)) 414 415 #define RS saved_state.asregs.rs 416 #define RE saved_state.asregs.re 417 #define MOD (saved_state.asregs.mod) 418 #define SET_MOD(i) \ 419 (MOD = (i), \ 420 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \ 421 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16)) 422 423 #define DSP_R(n) saved_state.asregs.sregs[(n)] 424 #define DSP_GRD(n) DSP_R ((n) + 8) 425 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n))) 426 #define A1 DSP_R (5) 427 #define A0 DSP_R (7) 428 #define X0 DSP_R (8) 429 #define X1 DSP_R (9) 430 #define Y0 DSP_R (10) 431 #define Y1 DSP_R (11) 432 #define M0 DSP_R (12) 433 #define A1G DSP_R (13) 434 #define M1 DSP_R (14) 435 #define A0G DSP_R (15) 436 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */ 437 #define MOD_ME DSP_GRD (17) 438 #define MOD_DELTA DSP_GRD (18) 439 440 #define FP_OP(n, OP, m) \ 441 { \ 442 if (FPSCR_PR) \ 443 { \ 444 if (((n) & 1) || ((m) & 1)) \ 445 RAISE_EXCEPTION (SIGILL); \ 446 else \ 447 SET_DR (n, (DR (n) OP DR (m))); \ 448 } \ 449 else \ 450 SET_FR (n, (FR (n) OP FR (m))); \ 451 } while (0) 452 453 #define FP_UNARY(n, OP) \ 454 { \ 455 if (FPSCR_PR) \ 456 { \ 457 if ((n) & 1) \ 458 RAISE_EXCEPTION (SIGILL); \ 459 else \ 460 SET_DR (n, (OP (DR (n)))); \ 461 } \ 462 else \ 463 SET_FR (n, (OP (FR (n)))); \ 464 } while (0) 465 466 #define FP_CMP(n, OP, m) \ 467 { \ 468 if (FPSCR_PR) \ 469 { \ 470 if (((n) & 1) || ((m) & 1)) \ 471 RAISE_EXCEPTION (SIGILL); \ 472 else \ 473 SET_SR_T (DR (n) OP DR (m)); \ 474 } \ 475 else \ 476 SET_SR_T (FR (n) OP FR (m)); \ 477 } while (0) 478 479 static void 480 set_sr (int new_sr) 481 { 482 /* do we need to swap banks */ 483 int old_gpr = SR_MD && SR_RB; 484 int new_gpr = (new_sr & SR_MASK_MD) && (new_sr & SR_MASK_RB); 485 if (old_gpr != new_gpr) 486 { 487 int i, tmp; 488 for (i = 0; i < 8; i++) 489 { 490 tmp = saved_state.asregs.bank[i]; 491 saved_state.asregs.bank[i] = saved_state.asregs.regs[i]; 492 saved_state.asregs.regs[i] = tmp; 493 } 494 } 495 saved_state.asregs.sr = new_sr; 496 SET_MOD (MOD); 497 } 498 499 static INLINE void 500 wlat_fast (unsigned char *memory, int x, int value, int maskl) 501 { 502 int v = value; 503 unsigned int *p = (unsigned int *) (memory + x); 504 WRITE_BUSERROR (x, maskl, v, process_wlat_addr); 505 *p = v; 506 } 507 508 static INLINE void 509 wwat_fast (unsigned char *memory, int x, int value, int maskw, int endianw) 510 { 511 int v = value; 512 unsigned short *p = (unsigned short *) (memory + (x ^ endianw)); 513 WRITE_BUSERROR (x, maskw, v, process_wwat_addr); 514 *p = v; 515 } 516 517 static INLINE void 518 wbat_fast (unsigned char *memory, int x, int value, int maskb) 519 { 520 unsigned char *p = memory + (x ^ endianb); 521 WRITE_BUSERROR (x, maskb, value, process_wbat_addr); 522 523 p[0] = value; 524 } 525 526 /* Read functions */ 527 528 static INLINE int 529 rlat_fast (unsigned char *memory, int x, int maskl) 530 { 531 unsigned int *p = (unsigned int *) (memory + x); 532 READ_BUSERROR (x, maskl, process_rlat_addr); 533 534 return *p; 535 } 536 537 static INLINE int 538 rwat_fast (unsigned char *memory, int x, int maskw, int endianw) 539 { 540 unsigned short *p = (unsigned short *) (memory + (x ^ endianw)); 541 READ_BUSERROR (x, maskw, process_rwat_addr); 542 543 return *p; 544 } 545 546 static INLINE int 547 riat_fast (unsigned char *insn_ptr, int endianw) 548 { 549 unsigned short *p = (unsigned short *) ((uintptr_t) insn_ptr ^ endianw); 550 551 return *p; 552 } 553 554 static INLINE int 555 rbat_fast (unsigned char *memory, int x, int maskb) 556 { 557 unsigned char *p = memory + (x ^ endianb); 558 READ_BUSERROR (x, maskb, process_rbat_addr); 559 560 return *p; 561 } 562 563 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw)) 564 #define RLAT(x) (rlat_fast (memory, x, maskl)) 565 #define RBAT(x) (rbat_fast (memory, x, maskb)) 566 #define RIAT(p) (riat_fast ((p), endianw)) 567 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw)) 568 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl)) 569 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb)) 570 571 #define RUWAT(x) (RWAT (x) & 0xffff) 572 #define RSWAT(x) ((short) (RWAT (x))) 573 #define RSLAT(x) ((long) (RLAT (x))) 574 #define RSBAT(x) (SEXT (RBAT (x))) 575 576 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl))) 577 static int 578 do_rdat (unsigned char *memory, int x, int n, int maskl) 579 { 580 int f0; 581 int f1; 582 int i = (n & 1); 583 int j = (n & ~1); 584 f0 = rlat_fast (memory, x + 0, maskl); 585 f1 = rlat_fast (memory, x + 4, maskl); 586 saved_state.asregs.fregs[i].i[(j + 0)] = f0; 587 saved_state.asregs.fregs[i].i[(j + 1)] = f1; 588 return 0; 589 } 590 591 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl))) 592 static int 593 do_wdat (unsigned char *memory, int x, int n, int maskl) 594 { 595 int f0; 596 int f1; 597 int i = (n & 1); 598 int j = (n & ~1); 599 f0 = saved_state.asregs.fregs[i].i[(j + 0)]; 600 f1 = saved_state.asregs.fregs[i].i[(j + 1)]; 601 wlat_fast (memory, (x + 0), f0, maskl); 602 wlat_fast (memory, (x + 4), f1, maskl); 603 return 0; 604 } 605 606 static void 607 process_wlat_addr (int addr, int value) 608 { 609 unsigned int *ptr; 610 611 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 32, 3, value, ); 612 *ptr = value; 613 } 614 615 static void 616 process_wwat_addr (int addr, int value) 617 { 618 unsigned short *ptr; 619 620 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 16, 1, value, ); 621 *ptr = value; 622 } 623 624 static void 625 process_wbat_addr (int addr, int value) 626 { 627 unsigned char *ptr; 628 629 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, 8, 0, value, ); 630 *ptr = value; 631 } 632 633 static int 634 process_rlat_addr (int addr) 635 { 636 unsigned char *ptr; 637 638 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -32, 3, -1, 0); 639 return *ptr; 640 } 641 642 static int 643 process_rwat_addr (int addr) 644 { 645 unsigned char *ptr; 646 647 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -16, 1, -1, 0); 648 return *ptr; 649 } 650 651 static int 652 process_rbat_addr (int addr) 653 { 654 unsigned char *ptr; 655 656 PROCESS_SPECIAL_ADDRESS (addr, endianb, ptr, -8, 0, -1, 0); 657 return *ptr; 658 } 659 660 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80) 661 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800) 662 #define SEXTW(y) ((int) ((short) y)) 663 #if 0 664 #define SEXT32(x) ((int) ((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1) 665 #else 666 #define SEXT32(x) ((int) (x)) 667 #endif 668 #define SIGN32(x) (SEXT32 (x) >> 31) 669 670 /* convert pointer from target to host value. */ 671 #define PT2H(x) ((x) + memory) 672 /* convert pointer from host to target value. */ 673 #define PH2T(x) ((x) - memory) 674 675 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2)) 676 677 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip); 678 679 static int in_delay_slot = 0; 680 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); in_delay_slot = 1; goto top; 681 682 #define CHECK_INSN_PTR(p) \ 683 do { \ 684 if (saved_state.asregs.exception || PH2T (p) & maskw) \ 685 saved_state.asregs.insn_end = 0; \ 686 else if (p < loop.end) \ 687 saved_state.asregs.insn_end = loop.end; \ 688 else \ 689 saved_state.asregs.insn_end = mem_end; \ 690 } while (0) 691 692 #ifdef ACE_FAST 693 694 #define MA(n) 695 #define L(x) 696 #define TL(x) 697 #define TB(x) 698 699 #else 700 701 #define MA(n) \ 702 do { memstalls += ((((uintptr_t) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0) 703 704 #define L(x) thislock = x; 705 #define TL(x) if ((x) == prevlock) stalls++; 706 #define TB(x,y) if ((x) == prevlock || (y) == prevlock) stalls++; 707 708 #endif 709 710 #if defined(__GO32__) 711 int sim_memory_size = 19; 712 #else 713 int sim_memory_size = 30; 714 #endif 715 716 static int sim_profile_size = 17; 717 static int nsamples; 718 719 #undef TB 720 #define TB(x,y) 721 722 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */ 723 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */ 724 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */ 725 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */ 726 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */ 727 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */ 728 729 #define SCI_RDRF 0x40 /* Recieve data register full */ 730 #define SCI_TDRE 0x80 /* Transmit data register empty */ 731 732 static int 733 IOMEM (int addr, int write, int value) 734 { 735 if (write) 736 { 737 switch (addr) 738 { 739 case TDR1: 740 if (value != '\r') 741 { 742 putchar (value); 743 fflush (stdout); 744 } 745 break; 746 } 747 } 748 else 749 { 750 switch (addr) 751 { 752 case RDR1: 753 return getchar (); 754 } 755 } 756 return 0; 757 } 758 759 static int 760 get_now (void) 761 { 762 return time (NULL); 763 } 764 765 static int 766 now_persec (void) 767 { 768 return 1; 769 } 770 771 static FILE *profile_file; 772 773 static INLINE unsigned 774 swap (unsigned n) 775 { 776 if (endianb) 777 n = (n << 24 | (n & 0xff00) << 8 778 | (n & 0xff0000) >> 8 | (n & 0xff000000) >> 24); 779 return n; 780 } 781 782 static INLINE unsigned short 783 swap16 (unsigned short n) 784 { 785 if (endianb) 786 n = n << 8 | (n & 0xff00) >> 8; 787 return n; 788 } 789 790 static void 791 swapout (int n) 792 { 793 if (profile_file) 794 { 795 union { char b[4]; int n; } u; 796 u.n = swap (n); 797 fwrite (u.b, 4, 1, profile_file); 798 } 799 } 800 801 static void 802 swapout16 (int n) 803 { 804 union { char b[4]; int n; } u; 805 u.n = swap16 (n); 806 fwrite (u.b, 2, 1, profile_file); 807 } 808 809 /* Turn a pointer in a register into a pointer into real memory. */ 810 811 static char * 812 ptr (int x) 813 { 814 return (char *) (x + saved_state.asregs.memory); 815 } 816 817 /* STR points to a zero-terminated string in target byte order. Return 818 the number of bytes that need to be converted to host byte order in order 819 to use this string as a zero-terminated string on the host. 820 (Not counting the rounding up needed to operate on entire words.) */ 821 static int 822 strswaplen (int str) 823 { 824 unsigned char *memory = saved_state.asregs.memory; 825 int end; 826 int endian = endianb; 827 828 if (! endian) 829 return 0; 830 end = str; 831 for (end = str; memory[end ^ endian]; end++) ; 832 return end - str + 1; 833 } 834 835 static void 836 strnswap (int str, int len) 837 { 838 int *start, *end; 839 840 if (! endianb || ! len) 841 return; 842 start = (int *) ptr (str & ~3); 843 end = (int *) ptr (str + len); 844 do 845 { 846 int old = *start; 847 *start = (old << 24 | (old & 0xff00) << 8 848 | (old & 0xff0000) >> 8 | (old & 0xff000000) >> 24); 849 start++; 850 } 851 while (start < end); 852 } 853 854 /* Simulate a monitor trap, put the result into r0 and errno into r1 855 return offset by which to adjust pc. */ 856 857 static int 858 trap (SIM_DESC sd, int i, int *regs, unsigned char *insn_ptr, 859 unsigned char *memory, int maskl, int maskw, int endianw) 860 { 861 host_callback *callback = STATE_CALLBACK (sd); 862 char **prog_argv = STATE_PROG_ARGV (sd); 863 864 switch (i) 865 { 866 case 1: 867 printf ("%c", regs[0]); 868 break; 869 case 2: 870 raise_exception (SIGQUIT); 871 break; 872 case 3: /* FIXME: for backwards compat, should be removed */ 873 case 33: 874 { 875 unsigned int countp = * (unsigned int *) (insn_ptr + 4); 876 877 WLAT (countp, RLAT (countp) + 1); 878 return 6; 879 } 880 case 34: 881 { 882 int perrno = errno; 883 errno = 0; 884 885 switch (regs[4]) 886 { 887 888 #if !defined(__GO32__) && !defined(_WIN32) 889 case TARGET_NEWLIB_SH_SYS_fork: 890 regs[0] = fork (); 891 break; 892 /* This would work only if endianness matched between host and target. 893 Besides, it's quite dangerous. */ 894 #if 0 895 case TARGET_NEWLIB_SH_SYS_execve: 896 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 897 (char **) ptr (regs[7])); 898 break; 899 case TARGET_NEWLIB_SH_SYS_execv: 900 regs[0] = execve (ptr (regs[5]), (char **) ptr (regs[6]), 0); 901 break; 902 #endif 903 case TARGET_NEWLIB_SH_SYS_pipe: 904 { 905 regs[0] = (BUSERROR (regs[5], maskl) 906 ? -EINVAL 907 : pipe ((int *) ptr (regs[5]))); 908 } 909 break; 910 911 case TARGET_NEWLIB_SH_SYS_wait: 912 regs[0] = wait ((int *) ptr (regs[5])); 913 break; 914 #endif /* !defined(__GO32__) && !defined(_WIN32) */ 915 916 case TARGET_NEWLIB_SH_SYS_read: 917 strnswap (regs[6], regs[7]); 918 regs[0] 919 = callback->read (callback, regs[5], ptr (regs[6]), regs[7]); 920 strnswap (regs[6], regs[7]); 921 break; 922 case TARGET_NEWLIB_SH_SYS_write: 923 strnswap (regs[6], regs[7]); 924 if (regs[5] == 1) 925 regs[0] = (int) callback->write_stdout (callback, 926 ptr (regs[6]), regs[7]); 927 else 928 regs[0] = (int) callback->write (callback, regs[5], 929 ptr (regs[6]), regs[7]); 930 strnswap (regs[6], regs[7]); 931 break; 932 case TARGET_NEWLIB_SH_SYS_lseek: 933 regs[0] = callback->lseek (callback,regs[5], regs[6], regs[7]); 934 break; 935 case TARGET_NEWLIB_SH_SYS_close: 936 regs[0] = callback->close (callback,regs[5]); 937 break; 938 case TARGET_NEWLIB_SH_SYS_open: 939 { 940 int len = strswaplen (regs[5]); 941 strnswap (regs[5], len); 942 regs[0] = callback->open (callback, ptr (regs[5]), regs[6]); 943 strnswap (regs[5], len); 944 break; 945 } 946 case TARGET_NEWLIB_SH_SYS_exit: 947 /* EXIT - caller can look in r5 to work out the reason */ 948 raise_exception (SIGQUIT); 949 regs[0] = regs[5]; 950 break; 951 952 case TARGET_NEWLIB_SH_SYS_stat: /* added at hmsi */ 953 /* stat system call */ 954 { 955 struct stat host_stat; 956 int buf; 957 int len = strswaplen (regs[5]); 958 959 strnswap (regs[5], len); 960 regs[0] = stat (ptr (regs[5]), &host_stat); 961 strnswap (regs[5], len); 962 963 buf = regs[6]; 964 965 WWAT (buf, host_stat.st_dev); 966 buf += 2; 967 WWAT (buf, host_stat.st_ino); 968 buf += 2; 969 WLAT (buf, host_stat.st_mode); 970 buf += 4; 971 WWAT (buf, host_stat.st_nlink); 972 buf += 2; 973 WWAT (buf, host_stat.st_uid); 974 buf += 2; 975 WWAT (buf, host_stat.st_gid); 976 buf += 2; 977 WWAT (buf, host_stat.st_rdev); 978 buf += 2; 979 WLAT (buf, host_stat.st_size); 980 buf += 4; 981 WLAT (buf, host_stat.st_atime); 982 buf += 4; 983 WLAT (buf, 0); 984 buf += 4; 985 WLAT (buf, host_stat.st_mtime); 986 buf += 4; 987 WLAT (buf, 0); 988 buf += 4; 989 WLAT (buf, host_stat.st_ctime); 990 buf += 4; 991 WLAT (buf, 0); 992 buf += 4; 993 WLAT (buf, 0); 994 buf += 4; 995 WLAT (buf, 0); 996 buf += 4; 997 } 998 break; 999 1000 #ifndef _WIN32 1001 case TARGET_NEWLIB_SH_SYS_chown: 1002 { 1003 int len = strswaplen (regs[5]); 1004 1005 strnswap (regs[5], len); 1006 regs[0] = chown (ptr (regs[5]), regs[6], regs[7]); 1007 strnswap (regs[5], len); 1008 break; 1009 } 1010 #endif /* _WIN32 */ 1011 case TARGET_NEWLIB_SH_SYS_chmod: 1012 { 1013 int len = strswaplen (regs[5]); 1014 1015 strnswap (regs[5], len); 1016 regs[0] = chmod (ptr (regs[5]), regs[6]); 1017 strnswap (regs[5], len); 1018 break; 1019 } 1020 case TARGET_NEWLIB_SH_SYS_utime: 1021 { 1022 /* Cast the second argument to void *, to avoid type mismatch 1023 if a prototype is present. */ 1024 int len = strswaplen (regs[5]); 1025 1026 strnswap (regs[5], len); 1027 #ifdef HAVE_UTIME_H 1028 regs[0] = utime (ptr (regs[5]), (void *) ptr (regs[6])); 1029 #else 1030 errno = ENOSYS; 1031 regs[0] = -1; 1032 #endif 1033 strnswap (regs[5], len); 1034 break; 1035 } 1036 case TARGET_NEWLIB_SH_SYS_argc: 1037 regs[0] = countargv (prog_argv); 1038 break; 1039 case TARGET_NEWLIB_SH_SYS_argnlen: 1040 if (regs[5] < countargv (prog_argv)) 1041 regs[0] = strlen (prog_argv[regs[5]]); 1042 else 1043 regs[0] = -1; 1044 break; 1045 case TARGET_NEWLIB_SH_SYS_argn: 1046 if (regs[5] < countargv (prog_argv)) 1047 { 1048 /* Include the termination byte. */ 1049 int len = strlen (prog_argv[regs[5]]) + 1; 1050 regs[0] = sim_write (0, regs[6], prog_argv[regs[5]], len); 1051 } 1052 else 1053 regs[0] = -1; 1054 break; 1055 case TARGET_NEWLIB_SH_SYS_time: 1056 regs[0] = get_now (); 1057 break; 1058 case TARGET_NEWLIB_SH_SYS_ftruncate: 1059 regs[0] = callback->ftruncate (callback, regs[5], regs[6]); 1060 break; 1061 case TARGET_NEWLIB_SH_SYS_truncate: 1062 { 1063 int len = strswaplen (regs[5]); 1064 strnswap (regs[5], len); 1065 regs[0] = callback->truncate (callback, ptr (regs[5]), regs[6]); 1066 strnswap (regs[5], len); 1067 break; 1068 } 1069 default: 1070 regs[0] = -1; 1071 break; 1072 } 1073 regs[1] = callback->get_errno (callback); 1074 errno = perrno; 1075 } 1076 break; 1077 1078 case 13: /* Set IBNR */ 1079 IBNR = regs[0] & 0xffff; 1080 break; 1081 case 14: /* Set IBCR */ 1082 IBCR = regs[0] & 0xffff; 1083 break; 1084 case 0xc3: 1085 case 255: 1086 raise_exception (SIGTRAP); 1087 if (i == 0xc3) 1088 return -2; 1089 break; 1090 } 1091 return 0; 1092 } 1093 1094 static void 1095 div1 (int *R, int iRn2, int iRn1/*, int T*/) 1096 { 1097 unsigned long tmp0; 1098 unsigned char old_q, tmp1; 1099 1100 old_q = Q; 1101 SET_SR_Q ((unsigned char) ((0x80000000 & R[iRn1]) != 0)); 1102 R[iRn1] <<= 1; 1103 R[iRn1] |= (unsigned long) T; 1104 1105 if (!old_q) 1106 { 1107 if (!M) 1108 { 1109 tmp0 = R[iRn1]; 1110 R[iRn1] -= R[iRn2]; 1111 tmp1 = (R[iRn1] > tmp0); 1112 if (!Q) 1113 SET_SR_Q (tmp1); 1114 else 1115 SET_SR_Q ((unsigned char) (tmp1 == 0)); 1116 } 1117 else 1118 { 1119 tmp0 = R[iRn1]; 1120 R[iRn1] += R[iRn2]; 1121 tmp1 = (R[iRn1] < tmp0); 1122 if (!Q) 1123 SET_SR_Q ((unsigned char) (tmp1 == 0)); 1124 else 1125 SET_SR_Q (tmp1); 1126 } 1127 } 1128 else 1129 { 1130 if (!M) 1131 { 1132 tmp0 = R[iRn1]; 1133 R[iRn1] += R[iRn2]; 1134 tmp1 = (R[iRn1] < tmp0); 1135 if (!Q) 1136 SET_SR_Q (tmp1); 1137 else 1138 SET_SR_Q ((unsigned char) (tmp1 == 0)); 1139 } 1140 else 1141 { 1142 tmp0 = R[iRn1]; 1143 R[iRn1] -= R[iRn2]; 1144 tmp1 = (R[iRn1] > tmp0); 1145 if (!Q) 1146 SET_SR_Q ((unsigned char) (tmp1 == 0)); 1147 else 1148 SET_SR_Q (tmp1); 1149 } 1150 } 1151 /*T = (Q == M);*/ 1152 SET_SR_T (Q == M); 1153 /*return T;*/ 1154 } 1155 1156 static void 1157 dmul_s (uint32_t rm, uint32_t rn) 1158 { 1159 int64_t res = (int64_t)(int32_t)rm * (int64_t)(int32_t)rn; 1160 MACH = (uint32_t)((uint64_t)res >> 32); 1161 MACL = (uint32_t)res; 1162 } 1163 1164 static void 1165 dmul_u (uint32_t rm, uint32_t rn) 1166 { 1167 uint64_t res = (uint64_t)(uint32_t)rm * (uint64_t)(uint32_t)rn; 1168 MACH = (uint32_t)(res >> 32); 1169 MACL = (uint32_t)res; 1170 } 1171 1172 static void 1173 macw (int *regs, unsigned char *memory, int n, int m, int endianw) 1174 { 1175 long tempm, tempn; 1176 long prod, macl, sum; 1177 1178 tempm=RSWAT (regs[m]); regs[m]+=2; 1179 tempn=RSWAT (regs[n]); regs[n]+=2; 1180 1181 macl = MACL; 1182 prod = (long) (short) tempm * (long) (short) tempn; 1183 sum = prod + macl; 1184 if (S) 1185 { 1186 if ((~(prod ^ macl) & (sum ^ prod)) < 0) 1187 { 1188 /* MACH's lsb is a sticky overflow bit. */ 1189 MACH |= 1; 1190 /* Store the smallest negative number in MACL if prod is 1191 negative, and the largest positive number otherwise. */ 1192 sum = 0x7fffffff + (prod < 0); 1193 } 1194 } 1195 else 1196 { 1197 long mach; 1198 /* Add to MACH the sign extended product, and carry from low sum. */ 1199 mach = MACH + (-(prod < 0)) + ((unsigned long) sum < prod); 1200 /* Sign extend at 10:th bit in MACH. */ 1201 MACH = (mach & 0x1ff) | -(mach & 0x200); 1202 } 1203 MACL = sum; 1204 } 1205 1206 static void 1207 macl (int *regs, unsigned char *memory, int n, int m) 1208 { 1209 long tempm, tempn; 1210 long macl, mach; 1211 long long ans; 1212 long long mac64; 1213 1214 tempm = RSLAT (regs[m]); 1215 regs[m] += 4; 1216 1217 tempn = RSLAT (regs[n]); 1218 regs[n] += 4; 1219 1220 mach = MACH; 1221 macl = MACL; 1222 1223 mac64 = ((long long) macl & 0xffffffff) | 1224 ((long long) mach & 0xffffffff) << 32; 1225 1226 ans = (long long) tempm * (long long) tempn; /* Multiply 32bit * 32bit */ 1227 1228 mac64 += ans; /* Accumulate 64bit + 64 bit */ 1229 1230 macl = (long) (mac64 & 0xffffffff); 1231 mach = (long) ((mac64 >> 32) & 0xffffffff); 1232 1233 if (S) /* Store only 48 bits of the result */ 1234 { 1235 if (mach < 0) /* Result is negative */ 1236 { 1237 mach = mach & 0x0000ffff; /* Mask higher 16 bits */ 1238 mach |= 0xffff8000; /* Sign extend higher 16 bits */ 1239 } 1240 else 1241 mach = mach & 0x00007fff; /* Postive Result */ 1242 } 1243 1244 MACL = macl; 1245 MACH = mach; 1246 } 1247 1248 enum { 1249 B_BCLR = 0, 1250 B_BSET = 1, 1251 B_BST = 2, 1252 B_BLD = 3, 1253 B_BAND = 4, 1254 B_BOR = 5, 1255 B_BXOR = 6, 1256 B_BLDNOT = 11, 1257 B_BANDNOT = 12, 1258 B_BORNOT = 13, 1259 1260 MOVB_RM = 0x0000, 1261 MOVW_RM = 0x1000, 1262 MOVL_RM = 0x2000, 1263 FMOV_RM = 0x3000, 1264 MOVB_MR = 0x4000, 1265 MOVW_MR = 0x5000, 1266 MOVL_MR = 0x6000, 1267 FMOV_MR = 0x7000, 1268 MOVU_BMR = 0x8000, 1269 MOVU_WMR = 0x9000, 1270 }; 1271 1272 /* Do extended displacement move instructions. */ 1273 static void 1274 do_long_move_insn (int op, int disp12, int m, int n, int *thatlock) 1275 { 1276 int memstalls = 0; 1277 int thislock = *thatlock; 1278 int endianw = global_endianw; 1279 int *R = &(saved_state.asregs.regs[0]); 1280 unsigned char *memory = saved_state.asregs.memory; 1281 int maskb = ~((saved_state.asregs.msize - 1) & ~0); 1282 unsigned char *insn_ptr = PT2H (saved_state.asregs.pc); 1283 1284 switch (op) { 1285 case MOVB_RM: /* signed */ 1286 WBAT (disp12 * 1 + R[n], R[m]); 1287 break; 1288 case MOVW_RM: 1289 WWAT (disp12 * 2 + R[n], R[m]); 1290 break; 1291 case MOVL_RM: 1292 WLAT (disp12 * 4 + R[n], R[m]); 1293 break; 1294 case FMOV_RM: /* floating point */ 1295 if (FPSCR_SZ) 1296 { 1297 MA (1); 1298 WDAT (R[n] + 8 * disp12, m); 1299 } 1300 else 1301 WLAT (R[n] + 4 * disp12, FI (m)); 1302 break; 1303 case MOVB_MR: 1304 R[n] = RSBAT (disp12 * 1 + R[m]); 1305 L (n); 1306 break; 1307 case MOVW_MR: 1308 R[n] = RSWAT (disp12 * 2 + R[m]); 1309 L (n); 1310 break; 1311 case MOVL_MR: 1312 R[n] = RLAT (disp12 * 4 + R[m]); 1313 L (n); 1314 break; 1315 case FMOV_MR: 1316 if (FPSCR_SZ) { 1317 MA (1); 1318 RDAT (R[m] + 8 * disp12, n); 1319 } 1320 else 1321 SET_FI (n, RLAT (R[m] + 4 * disp12)); 1322 break; 1323 case MOVU_BMR: /* unsigned */ 1324 R[n] = RBAT (disp12 * 1 + R[m]); 1325 L (n); 1326 break; 1327 case MOVU_WMR: 1328 R[n] = RWAT (disp12 * 2 + R[m]); 1329 L (n); 1330 break; 1331 default: 1332 RAISE_EXCEPTION (SIGINT); 1333 exit (1); 1334 } 1335 saved_state.asregs.memstalls += memstalls; 1336 *thatlock = thislock; 1337 } 1338 1339 /* Do binary logical bit-manipulation insns. */ 1340 static void 1341 do_blog_insn (int imm, int addr, int binop, 1342 unsigned char *memory, int maskb) 1343 { 1344 int oldval = RBAT (addr); 1345 1346 switch (binop) { 1347 case B_BCLR: /* bclr.b */ 1348 WBAT (addr, oldval & ~imm); 1349 break; 1350 case B_BSET: /* bset.b */ 1351 WBAT (addr, oldval | imm); 1352 break; 1353 case B_BST: /* bst.b */ 1354 if (T) 1355 WBAT (addr, oldval | imm); 1356 else 1357 WBAT (addr, oldval & ~imm); 1358 break; 1359 case B_BLD: /* bld.b */ 1360 SET_SR_T ((oldval & imm) != 0); 1361 break; 1362 case B_BAND: /* band.b */ 1363 SET_SR_T (T && ((oldval & imm) != 0)); 1364 break; 1365 case B_BOR: /* bor.b */ 1366 SET_SR_T (T || ((oldval & imm) != 0)); 1367 break; 1368 case B_BXOR: /* bxor.b */ 1369 SET_SR_T (T ^ ((oldval & imm) != 0)); 1370 break; 1371 case B_BLDNOT: /* bldnot.b */ 1372 SET_SR_T ((oldval & imm) == 0); 1373 break; 1374 case B_BANDNOT: /* bandnot.b */ 1375 SET_SR_T (T && ((oldval & imm) == 0)); 1376 break; 1377 case B_BORNOT: /* bornot.b */ 1378 SET_SR_T (T || ((oldval & imm) == 0)); 1379 break; 1380 } 1381 } 1382 1383 static float 1384 fsca_s (int in, double (*f) (double)) 1385 { 1386 double rad = ldexp ((in & 0xffff), -15) * 3.141592653589793238462643383; 1387 double result = (*f) (rad); 1388 double error, upper, lower, frac; 1389 int exp; 1390 1391 /* Search the value with the maximum error that is still within the 1392 architectural spec. */ 1393 error = ldexp (1., -21); 1394 /* compensate for calculation inaccuracy by reducing error. */ 1395 error = error - ldexp (1., -50); 1396 upper = result + error; 1397 frac = frexp (upper, &exp); 1398 upper = ldexp (floor (ldexp (frac, 24)), exp - 24); 1399 lower = result - error; 1400 frac = frexp (lower, &exp); 1401 lower = ldexp (ceil (ldexp (frac, 24)), exp - 24); 1402 return fabs (upper - result) >= fabs (lower - result) ? upper : lower; 1403 } 1404 1405 static float 1406 fsrra_s (float in) 1407 { 1408 double result = 1. / sqrt (in); 1409 int exp; 1410 double frac, upper, lower, error, eps; 1411 1412 /* refine result */ 1413 result = result - (result * result * in - 1) * 0.5 * result; 1414 /* Search the value with the maximum error that is still within the 1415 architectural spec. */ 1416 frac = frexp (result, &exp); 1417 frac = ldexp (frac, 24); 1418 error = 4.0; /* 1 << 24-1-21 */ 1419 /* use eps to compensate for possible 1 ulp error in our 'exact' result. */ 1420 eps = ldexp (1., -29); 1421 upper = floor (frac + error - eps); 1422 if (upper > 16777216.) 1423 upper = floor ((frac + error - eps) * 0.5) * 2.; 1424 lower = ceil ((frac - error + eps) * 2) * .5; 1425 if (lower > 8388608.) 1426 lower = ceil (frac - error + eps); 1427 upper = ldexp (upper, exp - 24); 1428 lower = ldexp (lower, exp - 24); 1429 return upper - result >= result - lower ? upper : lower; 1430 } 1431 1432 1433 /* GET_LOOP_BOUNDS {EXTENDED} 1434 These two functions compute the actual starting and ending point 1435 of the repeat loop, based on the RS and RE registers (repeat start, 1436 repeat stop). The extended version is called for LDRC, and the 1437 regular version is called for SETRC. The difference is that for 1438 LDRC, the loop start and end instructions are literally the ones 1439 pointed to by RS and RE -- for SETRC, they're not (see docs). */ 1440 1441 static struct loop_bounds 1442 get_loop_bounds_ext (int rs, int re, unsigned char *memory, 1443 unsigned char *mem_end, int maskw, int endianw) 1444 { 1445 struct loop_bounds loop; 1446 1447 /* FIXME: should I verify RS < RE? */ 1448 loop.start = PT2H (RS); /* FIXME not using the params? */ 1449 loop.end = PT2H (RE & ~1); /* Ignore bit 0 of RE. */ 1450 SKIP_INSN (loop.end); 1451 if (loop.end >= mem_end) 1452 loop.end = PT2H (0); 1453 return loop; 1454 } 1455 1456 static struct loop_bounds 1457 get_loop_bounds (int rs, int re, unsigned char *memory, unsigned char *mem_end, 1458 int maskw, int endianw) 1459 { 1460 struct loop_bounds loop; 1461 1462 if (SR_RC) 1463 { 1464 if (RS >= RE) 1465 { 1466 loop.start = PT2H (RE - 4); 1467 SKIP_INSN (loop.start); 1468 loop.end = loop.start; 1469 if (RS - RE == 0) 1470 SKIP_INSN (loop.end); 1471 if (RS - RE <= 2) 1472 SKIP_INSN (loop.end); 1473 SKIP_INSN (loop.end); 1474 } 1475 else 1476 { 1477 loop.start = PT2H (RS); 1478 loop.end = PT2H (RE - 4); 1479 SKIP_INSN (loop.end); 1480 SKIP_INSN (loop.end); 1481 SKIP_INSN (loop.end); 1482 SKIP_INSN (loop.end); 1483 } 1484 if (loop.end >= mem_end) 1485 loop.end = PT2H (0); 1486 } 1487 else 1488 loop.end = PT2H (0); 1489 1490 return loop; 1491 } 1492 1493 #include "ppi.c" 1494 1495 /* Provide calloc / free versions that use an anonymous mmap. This can 1496 significantly cut the start-up time when a large simulator memory is 1497 required, because pages are only zeroed on demand. */ 1498 #ifdef MAP_ANONYMOUS 1499 static void * 1500 mcalloc (size_t nmemb, size_t size) 1501 { 1502 if (nmemb != 1) 1503 size *= nmemb; 1504 return mmap (0, size, PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_ANONYMOUS, 1505 -1, 0); 1506 } 1507 1508 #define mfree(start,length) munmap ((start), (length)) 1509 #else 1510 #define mcalloc calloc 1511 #define mfree(start,length) free(start) 1512 #endif 1513 1514 /* Set the memory size to the power of two provided. */ 1515 1516 static void 1517 sim_size (int power) 1518 { 1519 sim_memory_size = power; 1520 1521 if (saved_state.asregs.memory) 1522 { 1523 mfree (saved_state.asregs.memory, saved_state.asregs.msize); 1524 } 1525 1526 saved_state.asregs.msize = 1 << power; 1527 1528 saved_state.asregs.memory = 1529 (unsigned char *) mcalloc (1, saved_state.asregs.msize); 1530 1531 if (!saved_state.asregs.memory) 1532 { 1533 fprintf (stderr, 1534 "Not enough VM for simulation of %d bytes of RAM\n", 1535 saved_state.asregs.msize); 1536 1537 saved_state.asregs.msize = 1; 1538 saved_state.asregs.memory = (unsigned char *) mcalloc (1, 1); 1539 } 1540 } 1541 1542 static void 1543 init_dsp (struct bfd *abfd) 1544 { 1545 int was_dsp = target_dsp; 1546 unsigned long mach = bfd_get_mach (abfd); 1547 1548 if (mach == bfd_mach_sh_dsp || 1549 mach == bfd_mach_sh4al_dsp || 1550 mach == bfd_mach_sh3_dsp) 1551 { 1552 int ram_area_size, xram_start, yram_start; 1553 int new_select; 1554 1555 target_dsp = 1; 1556 if (mach == bfd_mach_sh_dsp) 1557 { 1558 /* SH7410 (orig. sh-sdp): 1559 4KB each for X & Y memory; 1560 On-chip X RAM 0x0800f000-0x0800ffff 1561 On-chip Y RAM 0x0801f000-0x0801ffff */ 1562 xram_start = 0x0800f000; 1563 ram_area_size = 0x1000; 1564 } 1565 if (mach == bfd_mach_sh3_dsp || mach == bfd_mach_sh4al_dsp) 1566 { 1567 /* SH7612: 1568 8KB each for X & Y memory; 1569 On-chip X RAM 0x1000e000-0x1000ffff 1570 On-chip Y RAM 0x1001e000-0x1001ffff */ 1571 xram_start = 0x1000e000; 1572 ram_area_size = 0x2000; 1573 } 1574 yram_start = xram_start + 0x10000; 1575 new_select = ~(ram_area_size - 1); 1576 if (saved_state.asregs.xyram_select != new_select) 1577 { 1578 saved_state.asregs.xyram_select = new_select; 1579 free (saved_state.asregs.xmem); 1580 free (saved_state.asregs.ymem); 1581 saved_state.asregs.xmem = 1582 (unsigned char *) calloc (1, ram_area_size); 1583 saved_state.asregs.ymem = 1584 (unsigned char *) calloc (1, ram_area_size); 1585 1586 /* Disable use of X / Y mmeory if not allocated. */ 1587 if (! saved_state.asregs.xmem || ! saved_state.asregs.ymem) 1588 { 1589 saved_state.asregs.xyram_select = 0; 1590 if (saved_state.asregs.xmem) 1591 free (saved_state.asregs.xmem); 1592 if (saved_state.asregs.ymem) 1593 free (saved_state.asregs.ymem); 1594 } 1595 } 1596 saved_state.asregs.xram_start = xram_start; 1597 saved_state.asregs.yram_start = yram_start; 1598 saved_state.asregs.xmem_offset = saved_state.asregs.xmem - xram_start; 1599 saved_state.asregs.ymem_offset = saved_state.asregs.ymem - yram_start; 1600 } 1601 else 1602 { 1603 target_dsp = 0; 1604 if (saved_state.asregs.xyram_select) 1605 { 1606 saved_state.asregs.xyram_select = 0; 1607 free (saved_state.asregs.xmem); 1608 free (saved_state.asregs.ymem); 1609 } 1610 } 1611 1612 if (! saved_state.asregs.xyram_select) 1613 { 1614 saved_state.asregs.xram_start = 1; 1615 saved_state.asregs.yram_start = 1; 1616 } 1617 1618 if (saved_state.asregs.regstack == NULL) 1619 saved_state.asregs.regstack = 1620 calloc (512, sizeof *saved_state.asregs.regstack); 1621 1622 if (target_dsp != was_dsp) 1623 { 1624 int i, tmp; 1625 1626 for (i = ARRAY_SIZE (sh_dsp_table) - 1; i >= 0; i--) 1627 { 1628 tmp = sh_jump_table[0xf000 + i]; 1629 sh_jump_table[0xf000 + i] = sh_dsp_table[i]; 1630 sh_dsp_table[i] = tmp; 1631 } 1632 } 1633 } 1634 1635 static void 1636 init_pointers (void) 1637 { 1638 if (saved_state.asregs.msize != 1 << sim_memory_size) 1639 { 1640 sim_size (sim_memory_size); 1641 } 1642 1643 if (saved_state.asregs.profile && !profile_file) 1644 { 1645 profile_file = fopen ("gmon.out", "wb"); 1646 /* Seek to where to put the call arc data */ 1647 nsamples = (1 << sim_profile_size); 1648 1649 fseek (profile_file, nsamples * 2 + 12, 0); 1650 1651 if (!profile_file) 1652 { 1653 fprintf (stderr, "Can't open gmon.out\n"); 1654 } 1655 else 1656 { 1657 saved_state.asregs.profile_hist = 1658 (unsigned short *) calloc (64, (nsamples * sizeof (short) / 64)); 1659 } 1660 } 1661 } 1662 1663 static void 1664 dump_profile (void) 1665 { 1666 unsigned int minpc; 1667 unsigned int maxpc; 1668 int i; 1669 1670 minpc = 0; 1671 maxpc = (1 << sim_profile_size); 1672 1673 fseek (profile_file, 0L, 0); 1674 swapout (minpc << PROFILE_SHIFT); 1675 swapout (maxpc << PROFILE_SHIFT); 1676 swapout (nsamples * 2 + 12); 1677 for (i = 0; i < nsamples; i++) 1678 swapout16 (saved_state.asregs.profile_hist[i]); 1679 1680 } 1681 1682 static void 1683 gotcall (int from, int to) 1684 { 1685 swapout (from); 1686 swapout (to); 1687 swapout (1); 1688 } 1689 1690 #define MMASKB ((saved_state.asregs.msize -1) & ~0) 1691 1692 void 1693 sim_resume (SIM_DESC sd, int step, int siggnal) 1694 { 1695 register unsigned char *insn_ptr; 1696 unsigned char *mem_end; 1697 struct loop_bounds loop; 1698 register int cycles = 0; 1699 register int stalls = 0; 1700 register int memstalls = 0; 1701 register int insts = 0; 1702 register int prevlock; 1703 #if 1 1704 int thislock; 1705 #else 1706 register int thislock; 1707 #endif 1708 register unsigned int doprofile; 1709 register int pollcount = 0; 1710 /* endianw is used for every insn fetch, hence it makes sense to cache it. 1711 endianb is used less often. */ 1712 register int endianw = global_endianw; 1713 1714 int tick_start = get_now (); 1715 void (*prev_fpe) (); 1716 1717 register unsigned short *jump_table = sh_jump_table; 1718 1719 register int *R = &(saved_state.asregs.regs[0]); 1720 /*register int T;*/ 1721 #ifndef PR 1722 register int PR; 1723 #endif 1724 1725 register int maskb = ~((saved_state.asregs.msize - 1) & ~0); 1726 register int maskw = ~((saved_state.asregs.msize - 1) & ~1); 1727 register int maskl = ~((saved_state.asregs.msize - 1) & ~3); 1728 register unsigned char *memory; 1729 register unsigned int sbit = ((unsigned int) 1 << 31); 1730 1731 prev_fpe = signal (SIGFPE, SIG_IGN); 1732 1733 init_pointers (); 1734 saved_state.asregs.exception = 0; 1735 1736 memory = saved_state.asregs.memory; 1737 mem_end = memory + saved_state.asregs.msize; 1738 1739 if (RE & 1) 1740 loop = get_loop_bounds_ext (RS, RE, memory, mem_end, maskw, endianw); 1741 else 1742 loop = get_loop_bounds (RS, RE, memory, mem_end, maskw, endianw); 1743 1744 insn_ptr = PT2H (saved_state.asregs.pc); 1745 CHECK_INSN_PTR (insn_ptr); 1746 1747 #ifndef PR 1748 PR = saved_state.asregs.pr; 1749 #endif 1750 /*T = GET_SR () & SR_MASK_T;*/ 1751 prevlock = saved_state.asregs.prevlock; 1752 thislock = saved_state.asregs.thislock; 1753 doprofile = saved_state.asregs.profile; 1754 1755 /* If profiling not enabled, disable it by asking for 1756 profiles infrequently. */ 1757 if (doprofile == 0) 1758 doprofile = ~0; 1759 1760 loop: 1761 if (step && insn_ptr < saved_state.asregs.insn_end) 1762 { 1763 if (saved_state.asregs.exception) 1764 /* This can happen if we've already been single-stepping and 1765 encountered a loop end. */ 1766 saved_state.asregs.insn_end = insn_ptr; 1767 else 1768 { 1769 saved_state.asregs.exception = SIGTRAP; 1770 saved_state.asregs.insn_end = insn_ptr + 2; 1771 } 1772 } 1773 1774 while (insn_ptr < saved_state.asregs.insn_end) 1775 { 1776 register unsigned int iword = RIAT (insn_ptr); 1777 register unsigned int ult; 1778 register unsigned char *nip = insn_ptr + 2; 1779 1780 #ifndef ACE_FAST 1781 insts++; 1782 #endif 1783 top: 1784 1785 #include "code.c" 1786 1787 1788 in_delay_slot = 0; 1789 insn_ptr = nip; 1790 1791 if (--pollcount < 0) 1792 { 1793 host_callback *callback = STATE_CALLBACK (sd); 1794 1795 pollcount = POLL_QUIT_INTERVAL; 1796 if ((*callback->poll_quit) != NULL 1797 && (*callback->poll_quit) (callback)) 1798 { 1799 sim_stop (sd); 1800 } 1801 } 1802 1803 #ifndef ACE_FAST 1804 prevlock = thislock; 1805 thislock = 30; 1806 cycles++; 1807 1808 if (cycles >= doprofile) 1809 { 1810 1811 saved_state.asregs.cycles += doprofile; 1812 cycles -= doprofile; 1813 if (saved_state.asregs.profile_hist) 1814 { 1815 int n = PH2T (insn_ptr) >> PROFILE_SHIFT; 1816 if (n < nsamples) 1817 { 1818 int i = saved_state.asregs.profile_hist[n]; 1819 if (i < 65000) 1820 saved_state.asregs.profile_hist[n] = i + 1; 1821 } 1822 1823 } 1824 } 1825 #endif 1826 } 1827 if (saved_state.asregs.insn_end == loop.end) 1828 { 1829 saved_state.asregs.sr += SR_RC_INCREMENT; 1830 if (SR_RC) 1831 insn_ptr = loop.start; 1832 else 1833 { 1834 saved_state.asregs.insn_end = mem_end; 1835 loop.end = PT2H (0); 1836 } 1837 goto loop; 1838 } 1839 1840 if (saved_state.asregs.exception == SIGILL 1841 || saved_state.asregs.exception == SIGBUS) 1842 { 1843 insn_ptr -= 2; 1844 } 1845 /* Check for SIGBUS due to insn fetch. */ 1846 else if (! saved_state.asregs.exception) 1847 saved_state.asregs.exception = SIGBUS; 1848 1849 saved_state.asregs.ticks += get_now () - tick_start; 1850 saved_state.asregs.cycles += cycles; 1851 saved_state.asregs.stalls += stalls; 1852 saved_state.asregs.memstalls += memstalls; 1853 saved_state.asregs.insts += insts; 1854 saved_state.asregs.pc = PH2T (insn_ptr); 1855 #ifndef PR 1856 saved_state.asregs.pr = PR; 1857 #endif 1858 1859 saved_state.asregs.prevlock = prevlock; 1860 saved_state.asregs.thislock = thislock; 1861 1862 if (profile_file) 1863 { 1864 dump_profile (); 1865 } 1866 1867 signal (SIGFPE, prev_fpe); 1868 } 1869 1870 uint64_t 1871 sim_write (SIM_DESC sd, uint64_t addr, const void *buffer, uint64_t size) 1872 { 1873 int i; 1874 const unsigned char *data = buffer; 1875 1876 init_pointers (); 1877 1878 for (i = 0; i < size; i++) 1879 { 1880 saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb] = data[i]; 1881 } 1882 return size; 1883 } 1884 1885 uint64_t 1886 sim_read (SIM_DESC sd, uint64_t addr, void *buffer, uint64_t size) 1887 { 1888 int i; 1889 unsigned char *data = buffer; 1890 1891 init_pointers (); 1892 1893 for (i = 0; i < size; i++) 1894 { 1895 data[i] = saved_state.asregs.memory[(MMASKB & (addr + i)) ^ endianb]; 1896 } 1897 return size; 1898 } 1899 1900 static int gdb_bank_number; 1901 enum { 1902 REGBANK_MACH = 15, 1903 REGBANK_IVN = 16, 1904 REGBANK_PR = 17, 1905 REGBANK_GBR = 18, 1906 REGBANK_MACL = 19 1907 }; 1908 1909 static int 1910 sh_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) 1911 { 1912 unsigned val; 1913 1914 init_pointers (); 1915 val = swap (* (int *) memory); 1916 switch (rn) 1917 { 1918 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: 1919 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: 1920 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: 1921 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: 1922 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: 1923 case SIM_SH_R15_REGNUM: 1924 saved_state.asregs.regs[rn] = val; 1925 break; 1926 case SIM_SH_PC_REGNUM: 1927 saved_state.asregs.pc = val; 1928 break; 1929 case SIM_SH_PR_REGNUM: 1930 PR = val; 1931 break; 1932 case SIM_SH_GBR_REGNUM: 1933 GBR = val; 1934 break; 1935 case SIM_SH_VBR_REGNUM: 1936 VBR = val; 1937 break; 1938 case SIM_SH_MACH_REGNUM: 1939 MACH = val; 1940 break; 1941 case SIM_SH_MACL_REGNUM: 1942 MACL = val; 1943 break; 1944 case SIM_SH_SR_REGNUM: 1945 SET_SR (val); 1946 break; 1947 case SIM_SH_FPUL_REGNUM: 1948 FPUL = val; 1949 break; 1950 case SIM_SH_FPSCR_REGNUM: 1951 SET_FPSCR (val); 1952 break; 1953 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: 1954 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: 1955 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: 1956 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: 1957 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: 1958 case SIM_SH_FR15_REGNUM: 1959 SET_FI (rn - SIM_SH_FR0_REGNUM, val); 1960 break; 1961 case SIM_SH_DSR_REGNUM: 1962 DSR = val; 1963 break; 1964 case SIM_SH_A0G_REGNUM: 1965 A0G = val; 1966 break; 1967 case SIM_SH_A0_REGNUM: 1968 A0 = val; 1969 break; 1970 case SIM_SH_A1G_REGNUM: 1971 A1G = val; 1972 break; 1973 case SIM_SH_A1_REGNUM: 1974 A1 = val; 1975 break; 1976 case SIM_SH_M0_REGNUM: 1977 M0 = val; 1978 break; 1979 case SIM_SH_M1_REGNUM: 1980 M1 = val; 1981 break; 1982 case SIM_SH_X0_REGNUM: 1983 X0 = val; 1984 break; 1985 case SIM_SH_X1_REGNUM: 1986 X1 = val; 1987 break; 1988 case SIM_SH_Y0_REGNUM: 1989 Y0 = val; 1990 break; 1991 case SIM_SH_Y1_REGNUM: 1992 Y1 = val; 1993 break; 1994 case SIM_SH_MOD_REGNUM: 1995 SET_MOD (val); 1996 break; 1997 case SIM_SH_RS_REGNUM: 1998 RS = val; 1999 break; 2000 case SIM_SH_RE_REGNUM: 2001 RE = val; 2002 break; 2003 case SIM_SH_SSR_REGNUM: 2004 SSR = val; 2005 break; 2006 case SIM_SH_SPC_REGNUM: 2007 SPC = val; 2008 break; 2009 /* The rn_bank idiosyncracies are not due to hardware differences, but to 2010 a weird aliasing naming scheme for sh3 / sh3e / sh4. */ 2011 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: 2012 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: 2013 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: 2014 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: 2015 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) 2016 { 2017 rn -= SIM_SH_R0_BANK0_REGNUM; 2018 saved_state.asregs.regstack[gdb_bank_number].regs[rn] = val; 2019 } 2020 else 2021 if (SR_MD && SR_RB) 2022 Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) = val; 2023 else 2024 saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM] = val; 2025 break; 2026 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: 2027 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: 2028 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: 2029 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: 2030 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) 2031 { 2032 rn -= SIM_SH_R0_BANK1_REGNUM; 2033 saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8] = val; 2034 } 2035 else 2036 if (SR_MD && SR_RB) 2037 saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM] = val; 2038 else 2039 Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) = val; 2040 break; 2041 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: 2042 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: 2043 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: 2044 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: 2045 SET_Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM, val); 2046 break; 2047 case SIM_SH_TBR_REGNUM: 2048 TBR = val; 2049 break; 2050 case SIM_SH_IBNR_REGNUM: 2051 IBNR = val; 2052 break; 2053 case SIM_SH_IBCR_REGNUM: 2054 IBCR = val; 2055 break; 2056 case SIM_SH_BANK_REGNUM: 2057 /* This is a pseudo-register maintained just for gdb. 2058 It tells us what register bank gdb would like to read/write. */ 2059 gdb_bank_number = val; 2060 break; 2061 case SIM_SH_BANK_MACL_REGNUM: 2062 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL] = val; 2063 break; 2064 case SIM_SH_BANK_GBR_REGNUM: 2065 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR] = val; 2066 break; 2067 case SIM_SH_BANK_PR_REGNUM: 2068 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR] = val; 2069 break; 2070 case SIM_SH_BANK_IVN_REGNUM: 2071 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN] = val; 2072 break; 2073 case SIM_SH_BANK_MACH_REGNUM: 2074 saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH] = val; 2075 break; 2076 default: 2077 return 0; 2078 } 2079 return length; 2080 } 2081 2082 static int 2083 sh_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) 2084 { 2085 int val; 2086 2087 init_pointers (); 2088 switch (rn) 2089 { 2090 case SIM_SH_R0_REGNUM: case SIM_SH_R1_REGNUM: case SIM_SH_R2_REGNUM: 2091 case SIM_SH_R3_REGNUM: case SIM_SH_R4_REGNUM: case SIM_SH_R5_REGNUM: 2092 case SIM_SH_R6_REGNUM: case SIM_SH_R7_REGNUM: case SIM_SH_R8_REGNUM: 2093 case SIM_SH_R9_REGNUM: case SIM_SH_R10_REGNUM: case SIM_SH_R11_REGNUM: 2094 case SIM_SH_R12_REGNUM: case SIM_SH_R13_REGNUM: case SIM_SH_R14_REGNUM: 2095 case SIM_SH_R15_REGNUM: 2096 val = saved_state.asregs.regs[rn]; 2097 break; 2098 case SIM_SH_PC_REGNUM: 2099 val = saved_state.asregs.pc; 2100 break; 2101 case SIM_SH_PR_REGNUM: 2102 val = PR; 2103 break; 2104 case SIM_SH_GBR_REGNUM: 2105 val = GBR; 2106 break; 2107 case SIM_SH_VBR_REGNUM: 2108 val = VBR; 2109 break; 2110 case SIM_SH_MACH_REGNUM: 2111 val = MACH; 2112 break; 2113 case SIM_SH_MACL_REGNUM: 2114 val = MACL; 2115 break; 2116 case SIM_SH_SR_REGNUM: 2117 val = GET_SR (); 2118 break; 2119 case SIM_SH_FPUL_REGNUM: 2120 val = FPUL; 2121 break; 2122 case SIM_SH_FPSCR_REGNUM: 2123 val = GET_FPSCR (); 2124 break; 2125 case SIM_SH_FR0_REGNUM: case SIM_SH_FR1_REGNUM: case SIM_SH_FR2_REGNUM: 2126 case SIM_SH_FR3_REGNUM: case SIM_SH_FR4_REGNUM: case SIM_SH_FR5_REGNUM: 2127 case SIM_SH_FR6_REGNUM: case SIM_SH_FR7_REGNUM: case SIM_SH_FR8_REGNUM: 2128 case SIM_SH_FR9_REGNUM: case SIM_SH_FR10_REGNUM: case SIM_SH_FR11_REGNUM: 2129 case SIM_SH_FR12_REGNUM: case SIM_SH_FR13_REGNUM: case SIM_SH_FR14_REGNUM: 2130 case SIM_SH_FR15_REGNUM: 2131 val = FI (rn - SIM_SH_FR0_REGNUM); 2132 break; 2133 case SIM_SH_DSR_REGNUM: 2134 val = DSR; 2135 break; 2136 case SIM_SH_A0G_REGNUM: 2137 val = SEXT (A0G); 2138 break; 2139 case SIM_SH_A0_REGNUM: 2140 val = A0; 2141 break; 2142 case SIM_SH_A1G_REGNUM: 2143 val = SEXT (A1G); 2144 break; 2145 case SIM_SH_A1_REGNUM: 2146 val = A1; 2147 break; 2148 case SIM_SH_M0_REGNUM: 2149 val = M0; 2150 break; 2151 case SIM_SH_M1_REGNUM: 2152 val = M1; 2153 break; 2154 case SIM_SH_X0_REGNUM: 2155 val = X0; 2156 break; 2157 case SIM_SH_X1_REGNUM: 2158 val = X1; 2159 break; 2160 case SIM_SH_Y0_REGNUM: 2161 val = Y0; 2162 break; 2163 case SIM_SH_Y1_REGNUM: 2164 val = Y1; 2165 break; 2166 case SIM_SH_MOD_REGNUM: 2167 val = MOD; 2168 break; 2169 case SIM_SH_RS_REGNUM: 2170 val = RS; 2171 break; 2172 case SIM_SH_RE_REGNUM: 2173 val = RE; 2174 break; 2175 case SIM_SH_SSR_REGNUM: 2176 val = SSR; 2177 break; 2178 case SIM_SH_SPC_REGNUM: 2179 val = SPC; 2180 break; 2181 /* The rn_bank idiosyncracies are not due to hardware differences, but to 2182 a weird aliasing naming scheme for sh3 / sh3e / sh4. */ 2183 case SIM_SH_R0_BANK0_REGNUM: case SIM_SH_R1_BANK0_REGNUM: 2184 case SIM_SH_R2_BANK0_REGNUM: case SIM_SH_R3_BANK0_REGNUM: 2185 case SIM_SH_R4_BANK0_REGNUM: case SIM_SH_R5_BANK0_REGNUM: 2186 case SIM_SH_R6_BANK0_REGNUM: case SIM_SH_R7_BANK0_REGNUM: 2187 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) 2188 { 2189 rn -= SIM_SH_R0_BANK0_REGNUM; 2190 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn]; 2191 } 2192 else 2193 val = (SR_MD && SR_RB 2194 ? Rn_BANK (rn - SIM_SH_R0_BANK0_REGNUM) 2195 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK0_REGNUM]); 2196 break; 2197 case SIM_SH_R0_BANK1_REGNUM: case SIM_SH_R1_BANK1_REGNUM: 2198 case SIM_SH_R2_BANK1_REGNUM: case SIM_SH_R3_BANK1_REGNUM: 2199 case SIM_SH_R4_BANK1_REGNUM: case SIM_SH_R5_BANK1_REGNUM: 2200 case SIM_SH_R6_BANK1_REGNUM: case SIM_SH_R7_BANK1_REGNUM: 2201 if (saved_state.asregs.bfd_mach == bfd_mach_sh2a) 2202 { 2203 rn -= SIM_SH_R0_BANK1_REGNUM; 2204 val = saved_state.asregs.regstack[gdb_bank_number].regs[rn + 8]; 2205 } 2206 else 2207 val = (! SR_MD || ! SR_RB 2208 ? Rn_BANK (rn - SIM_SH_R0_BANK1_REGNUM) 2209 : saved_state.asregs.regs[rn - SIM_SH_R0_BANK1_REGNUM]); 2210 break; 2211 case SIM_SH_R0_BANK_REGNUM: case SIM_SH_R1_BANK_REGNUM: 2212 case SIM_SH_R2_BANK_REGNUM: case SIM_SH_R3_BANK_REGNUM: 2213 case SIM_SH_R4_BANK_REGNUM: case SIM_SH_R5_BANK_REGNUM: 2214 case SIM_SH_R6_BANK_REGNUM: case SIM_SH_R7_BANK_REGNUM: 2215 val = Rn_BANK (rn - SIM_SH_R0_BANK_REGNUM); 2216 break; 2217 case SIM_SH_TBR_REGNUM: 2218 val = TBR; 2219 break; 2220 case SIM_SH_IBNR_REGNUM: 2221 val = IBNR; 2222 break; 2223 case SIM_SH_IBCR_REGNUM: 2224 val = IBCR; 2225 break; 2226 case SIM_SH_BANK_REGNUM: 2227 /* This is a pseudo-register maintained just for gdb. 2228 It tells us what register bank gdb would like to read/write. */ 2229 val = gdb_bank_number; 2230 break; 2231 case SIM_SH_BANK_MACL_REGNUM: 2232 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACL]; 2233 break; 2234 case SIM_SH_BANK_GBR_REGNUM: 2235 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_GBR]; 2236 break; 2237 case SIM_SH_BANK_PR_REGNUM: 2238 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_PR]; 2239 break; 2240 case SIM_SH_BANK_IVN_REGNUM: 2241 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_IVN]; 2242 break; 2243 case SIM_SH_BANK_MACH_REGNUM: 2244 val = saved_state.asregs.regstack[gdb_bank_number].regs[REGBANK_MACH]; 2245 break; 2246 default: 2247 return 0; 2248 } 2249 * (int *) memory = swap (val); 2250 return length; 2251 } 2252 2253 void 2254 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason, int *sigrc) 2255 { 2256 /* The SH simulator uses SIGQUIT to indicate that the program has 2257 exited, so we must check for it here and translate it to exit. */ 2258 if (saved_state.asregs.exception == SIGQUIT) 2259 { 2260 *reason = sim_exited; 2261 *sigrc = saved_state.asregs.regs[5]; 2262 } 2263 else 2264 { 2265 *reason = sim_stopped; 2266 *sigrc = saved_state.asregs.exception; 2267 } 2268 } 2269 2270 void 2271 sim_info (SIM_DESC sd, bool verbose) 2272 { 2273 double timetaken = 2274 (double) saved_state.asregs.ticks / (double) now_persec (); 2275 double virttime = saved_state.asregs.cycles / 36.0e6; 2276 2277 sim_io_printf (sd, "\n\n# instructions executed %10d\n", 2278 saved_state.asregs.insts); 2279 sim_io_printf (sd, "# cycles %10d\n", 2280 saved_state.asregs.cycles); 2281 sim_io_printf (sd, "# pipeline stalls %10d\n", 2282 saved_state.asregs.stalls); 2283 sim_io_printf (sd, "# misaligned load/store %10d\n", 2284 saved_state.asregs.memstalls); 2285 sim_io_printf (sd, "# real time taken %10.4f\n", timetaken); 2286 sim_io_printf (sd, "# virtual time taken %10.4f\n", virttime); 2287 sim_io_printf (sd, "# profiling size %10d\n", sim_profile_size); 2288 sim_io_printf (sd, "# profiling frequency %10d\n", 2289 saved_state.asregs.profile); 2290 sim_io_printf (sd, "# profile maxpc %10x\n", 2291 (1 << sim_profile_size) << PROFILE_SHIFT); 2292 2293 if (timetaken != 0) 2294 { 2295 sim_io_printf (sd, "# cycles/second %10d\n", 2296 (int) (saved_state.asregs.cycles / timetaken)); 2297 sim_io_printf (sd, "# simulation ratio %10.4f\n", 2298 virttime / timetaken); 2299 } 2300 } 2301 2302 static sim_cia 2303 sh_pc_get (sim_cpu *cpu) 2304 { 2305 return saved_state.asregs.pc; 2306 } 2307 2308 static void 2309 sh_pc_set (sim_cpu *cpu, sim_cia pc) 2310 { 2311 saved_state.asregs.pc = pc; 2312 } 2313 2314 static void 2315 free_state (SIM_DESC sd) 2316 { 2317 if (STATE_MODULES (sd) != NULL) 2318 sim_module_uninstall (sd); 2319 sim_cpu_free_all (sd); 2320 sim_state_free (sd); 2321 } 2322 2323 SIM_DESC 2324 sim_open (SIM_OPEN_KIND kind, host_callback *cb, 2325 struct bfd *abfd, char * const *argv) 2326 { 2327 char * const *p; 2328 int i; 2329 union 2330 { 2331 int i; 2332 short s[2]; 2333 char c[4]; 2334 } 2335 mem_word; 2336 2337 SIM_DESC sd = sim_state_alloc (kind, cb); 2338 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER); 2339 2340 /* Set default options before parsing user options. */ 2341 current_alignment = STRICT_ALIGNMENT; 2342 cb->syscall_map = cb_sh_syscall_map; 2343 2344 /* The cpu data is kept in a separately allocated chunk of memory. */ 2345 if (sim_cpu_alloc_all (sd, 0) != SIM_RC_OK) 2346 { 2347 free_state (sd); 2348 return 0; 2349 } 2350 2351 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 2352 { 2353 free_state (sd); 2354 return 0; 2355 } 2356 2357 /* The parser will print an error message for us, so we silently return. */ 2358 if (sim_parse_args (sd, argv) != SIM_RC_OK) 2359 { 2360 free_state (sd); 2361 return 0; 2362 } 2363 2364 /* Check for/establish the a reference program image. */ 2365 if (sim_analyze_program (sd, STATE_PROG_FILE (sd), abfd) != SIM_RC_OK) 2366 { 2367 free_state (sd); 2368 return 0; 2369 } 2370 2371 /* Configure/verify the target byte order and other runtime 2372 configuration options. */ 2373 if (sim_config (sd) != SIM_RC_OK) 2374 { 2375 sim_module_uninstall (sd); 2376 return 0; 2377 } 2378 2379 if (sim_post_argv_init (sd) != SIM_RC_OK) 2380 { 2381 /* Uninstall the modules to avoid memory leaks, 2382 file descriptor leaks, etc. */ 2383 sim_module_uninstall (sd); 2384 return 0; 2385 } 2386 2387 /* CPU specific initialization. */ 2388 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 2389 { 2390 SIM_CPU *cpu = STATE_CPU (sd, i); 2391 2392 CPU_REG_FETCH (cpu) = sh_reg_fetch; 2393 CPU_REG_STORE (cpu) = sh_reg_store; 2394 CPU_PC_FETCH (cpu) = sh_pc_get; 2395 CPU_PC_STORE (cpu) = sh_pc_set; 2396 } 2397 2398 for (p = argv + 1; *p != NULL; ++p) 2399 { 2400 if (isdigit (**p)) 2401 parse_and_set_memory_size (sd, *p); 2402 } 2403 2404 if (abfd) 2405 init_dsp (abfd); 2406 2407 for (i = 4; (i -= 2) >= 0; ) 2408 mem_word.s[i >> 1] = i; 2409 global_endianw = mem_word.i >> (target_little_endian ? 0 : 16) & 0xffff; 2410 2411 for (i = 4; --i >= 0; ) 2412 mem_word.c[i] = i; 2413 endianb = mem_word.i >> (target_little_endian ? 0 : 24) & 0xff; 2414 2415 return sd; 2416 } 2417 2418 static void 2419 parse_and_set_memory_size (SIM_DESC sd, const char *str) 2420 { 2421 int n; 2422 2423 n = strtol (str, NULL, 10); 2424 if (n > 0 && n <= 31) 2425 sim_memory_size = n; 2426 else 2427 sim_io_printf (sd, "Bad memory size %d; must be 1 to 31, inclusive\n", n); 2428 } 2429 2430 SIM_RC 2431 sim_create_inferior (SIM_DESC sd, struct bfd *prog_bfd, 2432 char * const *argv, char * const *env) 2433 { 2434 /* Clear the registers. */ 2435 memset (&saved_state, 0, 2436 (char*) &saved_state.asregs.end_of_registers - (char*) &saved_state); 2437 2438 /* Set the PC. */ 2439 if (prog_bfd != NULL) 2440 saved_state.asregs.pc = bfd_get_start_address (prog_bfd); 2441 2442 /* Set the bfd machine type. */ 2443 if (prog_bfd != NULL) 2444 saved_state.asregs.bfd_mach = bfd_get_mach (prog_bfd); 2445 2446 if (prog_bfd != NULL) 2447 init_dsp (prog_bfd); 2448 2449 return SIM_RC_OK; 2450 } 2451 2452 void 2453 sim_do_command (SIM_DESC sd, const char *cmd) 2454 { 2455 const char *sms_cmd = "set-memory-size"; 2456 int cmdsize; 2457 2458 if (cmd == NULL || *cmd == '\0') 2459 { 2460 cmd = "help"; 2461 } 2462 2463 cmdsize = strlen (sms_cmd); 2464 if (strncmp (cmd, sms_cmd, cmdsize) == 0 2465 && strchr (" \t", cmd[cmdsize]) != NULL) 2466 { 2467 parse_and_set_memory_size (sd, cmd + cmdsize + 1); 2468 } 2469 else if (strcmp (cmd, "help") == 0) 2470 { 2471 sim_io_printf (sd, "List of SH simulator commands:\n\n"); 2472 sim_io_printf (sd, "set-memory-size <n> -- Set the number of address bits to use\n"); 2473 sim_io_printf (sd, "\n"); 2474 } 2475 else 2476 { 2477 sim_io_printf (sd, "Error: \"%s\" is not a valid SH simulator command.\n", cmd); 2478 } 2479 } 2480