1 /* This file is part of the program psim. 2 3 Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 18 */ 19 20 21 #ifndef _PSIM_CONFIG_H_ 22 #define _PSIM_CONFIG_H_ 23 24 25 /* endianness of the host/target: 26 27 If the build process is aware (at compile time) of the endianness 28 of the host/target it is able to eliminate slower generic endian 29 handling code. 30 31 Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */ 32 33 #ifndef WITH_HOST_BYTE_ORDER 34 #define WITH_HOST_BYTE_ORDER 0 /*unknown*/ 35 #endif 36 37 #ifndef WITH_TARGET_BYTE_ORDER 38 #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/ 39 #endif 40 41 extern int current_host_byte_order; 42 #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \ 43 ? WITH_HOST_BYTE_ORDER \ 44 : current_host_byte_order) 45 extern int current_target_byte_order; 46 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \ 47 ? WITH_TARGET_BYTE_ORDER \ 48 : current_target_byte_order) 49 50 51 /* PowerPC XOR endian. 52 53 In addition to the above, the simulator can support the PowerPC's 54 horrible XOR endian mode. This feature makes it possible to 55 control the endian mode of a processor using the MSR. */ 56 57 #ifndef WITH_XOR_ENDIAN 58 #define WITH_XOR_ENDIAN 8 59 #endif 60 61 62 /* Intel host BSWAP support: 63 64 Whether to use bswap on the 486 and pentiums rather than the 386 65 sequence that uses xchgb/rorl/xchgb */ 66 #ifndef WITH_BSWAP 67 #define WITH_BSWAP 0 68 #endif 69 70 71 /* SMP support: 72 73 Sets a limit on the number of processors that can be simulated. If 74 WITH_SMP is set to zero (0), the simulator is restricted to 75 suporting only on processor (and as a consequence leaves the SMP 76 code out of the build process). 77 78 The actual number of processors is taken from the device 79 /options/smp@<nr-cpu> */ 80 81 #ifndef WITH_SMP 82 #define WITH_SMP 5 83 #endif 84 #if WITH_SMP 85 #define MAX_NR_PROCESSORS WITH_SMP 86 #else 87 #define MAX_NR_PROCESSORS 1 88 #endif 89 90 91 /* Word size of host/target: 92 93 Set these according to your host and target requirements. At this 94 point in time, I've only compiled (not run) for a 64bit and never 95 built for a 64bit host. This will always remain a compile time 96 option */ 97 98 #ifndef WITH_TARGET_WORD_BITSIZE 99 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */ 100 #endif 101 102 #ifndef WITH_HOST_WORD_BITSIZE 103 #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */ 104 #endif 105 106 107 /* Program environment: 108 109 Three environments are available - UEA (user), VEA (virtual) and 110 OEA (perating). The former two are environment that users would 111 expect to see (VEA includes things like coherency and the time 112 base) while OEA is what an operating system expects to see. By 113 setting these to specific values, the build process is able to 114 eliminate non relevent environment code 115 116 CURRENT_ENVIRONMENT specifies which of vea or oea is required for 117 the current runtime. */ 118 119 #define USER_ENVIRONMENT 1 120 #define VIRTUAL_ENVIRONMENT 2 121 #define OPERATING_ENVIRONMENT 3 122 123 #ifndef WITH_ENVIRONMENT 124 #define WITH_ENVIRONMENT 0 125 #endif 126 127 extern int current_environment; 128 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \ 129 ? WITH_ENVIRONMENT \ 130 : current_environment) 131 132 133 /* Optional VEA/OEA code: 134 135 The below, required for the OEA model may also be included in the 136 VEA model however, as far as I can tell only make things 137 slower... */ 138 139 140 /* Events. Devices modeling real H/W need to be able to efficiently 141 schedule things to do at known times in the future. The event 142 queue implements this. Unfortunatly this adds the need to check 143 for any events once each full instruction cycle. */ 144 145 #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) 146 147 148 /* Time base: 149 150 The PowerPC architecture includes the addition of both a time base 151 register and a decrement timer. Like events adds to the overhead 152 of of some instruction cycles. */ 153 154 #ifndef WITH_TIME_BASE 155 #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT) 156 #endif 157 158 159 /* Callback/Default Memory. 160 161 Core includes a builtin memory type (raw_memory) that is 162 implemented using an array. raw_memory does not require any 163 additional functions etc. 164 165 Callback memory is where the core calls a core device for the data 166 it requires. 167 168 Default memory is an extenstion of this where for addresses that do 169 not map into either a callback or core memory range a default map 170 can be used. 171 172 The OEA model uses callback memory for devices and default memory 173 for buses. 174 175 The VEA model uses callback memory to capture `page faults'. 176 177 While it may be possible to eliminate callback/default memory (and 178 hence also eliminate an additional test per memory fetch) it 179 probably is not worth the effort. 180 181 BTW, while raw_memory could have been implemented as a callback, 182 profiling has shown that there is a biger win (at least for the 183 x86) in eliminating a function call for the most common 184 (raw_memory) case. */ 185 186 #define WITH_CALLBACK_MEMORY 1 187 188 189 /* Alignment: 190 191 The PowerPC may or may not handle miss aligned transfers. An 192 implementation normally handles miss aligned transfers in big 193 endian mode but generates an exception in little endian mode. 194 195 This model. Instead allows both little and big endian modes to 196 either take exceptions or handle miss aligned transfers. 197 198 If 0 is specified then for big-endian mode miss alligned accesses 199 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the 200 processor will fault on them (STRICT_ALIGNMENT). */ 201 202 #define NONSTRICT_ALIGNMENT 1 203 #define STRICT_ALIGNMENT 2 204 205 #ifndef WITH_ALIGNMENT 206 #define WITH_ALIGNMENT 0 207 #endif 208 209 extern int current_alignment; 210 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \ 211 ? WITH_ALIGNMENT \ 212 : current_alignment) 213 214 215 /* Floating point suport: 216 217 Still under development. */ 218 219 #define SOFT_FLOATING_POINT 1 220 #define HARD_FLOATING_POINT 2 221 222 #ifndef WITH_FLOATING_POINT 223 #define WITH_FLOATING_POINT HARD_FLOATING_POINT 224 #endif 225 extern int current_floating_point; 226 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \ 227 ? WITH_FLOATING_POINT \ 228 : current_floating_point) 229 230 231 /* Debugging: 232 233 Control the inclusion of debugging code. */ 234 235 /* Include the tracing code. Disabling this eliminates all tracing 236 code */ 237 238 #ifndef WITH_TRACE 239 #define WITH_TRACE 1 240 #endif 241 242 /* include code that checks assertions scattered through out the 243 program */ 244 245 #ifndef WITH_ASSERT 246 #define WITH_ASSERT 1 247 #endif 248 249 /* Whether to check instructions for reserved bits being set */ 250 251 #ifndef WITH_RESERVED_BITS 252 #define WITH_RESERVED_BITS 1 253 #endif 254 255 /* include monitoring code */ 256 257 #define MONITOR_INSTRUCTION_ISSUE 1 258 #define MONITOR_LOAD_STORE_UNIT 2 259 #ifndef WITH_MON 260 #define WITH_MON (MONITOR_LOAD_STORE_UNIT \ 261 | MONITOR_INSTRUCTION_ISSUE) 262 #endif 263 264 /* Current CPU model (models are in the generated models.h include file) */ 265 #ifndef WITH_MODEL 266 #define WITH_MODEL 0 267 #endif 268 269 #define CURRENT_MODEL (WITH_MODEL \ 270 ? WITH_MODEL \ 271 : current_model) 272 273 #ifndef WITH_DEFAULT_MODEL 274 #define WITH_DEFAULT_MODEL DEFAULT_MODEL 275 #endif 276 277 #define MODEL_ISSUE_IGNORE (-1) 278 #define MODEL_ISSUE_PROCESS 1 279 280 #ifndef WITH_MODEL_ISSUE 281 #define WITH_MODEL_ISSUE 0 282 #endif 283 284 extern int current_model_issue; 285 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \ 286 ? WITH_MODEL_ISSUE \ 287 : current_model_issue) 288 289 /* Whether or not input/output just uses stdio, or uses printf_filtered for 290 output, and polling input for input. */ 291 292 #define DONT_USE_STDIO 2 293 #define DO_USE_STDIO 1 294 295 #ifndef WITH_STDIO 296 #define WITH_STDIO 0 297 #endif 298 299 extern int current_stdio; 300 #define CURRENT_STDIO (WITH_STDIO \ 301 ? WITH_STDIO \ 302 : current_stdio) 303 304 305 306 /* INLINE CODE SELECTION: 307 308 GCC -O3 attempts to inline any function or procedure in scope. The 309 options below facilitate fine grained control over what is and what 310 isn't made inline. For instance it can control things down to a 311 specific modules static routines. Doing this allows the compiler 312 to both eliminate the overhead of function calls and (as a 313 consequence) also eliminate further dead code. 314 315 On a CISC (x86) I've found that I can achieve an order of magnitude 316 speed improvement (x3-x5). In the case of RISC (sparc) while the 317 performance gain isn't as great it is still significant. 318 319 Each module is controled by the macro <module>_INLINE which can 320 have the values described below 321 322 0 Do not inline any thing for the given module 323 324 The following additional values are `bit fields' and can be 325 combined. 326 327 REVEAL_MODULE: 328 329 Include the C file for the module into the file being compiled 330 but do not make the functions within the module inline. 331 332 While of no apparent benefit, this makes it possible for the 333 included module, when compiled to inline its calls to what 334 would otherwize be external functions. 335 336 INLINE_MODULE: 337 338 Make external functions within the module `inline'. Thus if 339 the module is included into a file being compiled, calls to 340 its funtions can be eliminated. 2 implies 1. 341 342 PSIM_INLINE_LOCALS: 343 344 Make internal (static) functions within the module `inline'. 345 346 The following abreviations are available: 347 348 INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE) 349 350 ALL_INLINE == (REVEAL_MODULE | INLINE_MODULE | PSIM_INLINE_LOCALS) 351 352 In addition to this, modules have been put into two categories. 353 354 Simple modules - eg sim-endian.h bits.h 355 356 Because these modules are small and simple and do not have 357 any complex interpendencies they are configured, if 358 <module>_INLINE is so enabled, to inline themselves in all 359 modules that include those files. 360 361 For the default build, this is a real win as all byte 362 conversion and bit manipulation functions are inlined. 363 364 Complex modules - the rest 365 366 These are all handled using the files inline.h and inline.c. 367 psim.c includes the above which in turn include any remaining 368 code. 369 370 IMPLEMENTATION: 371 372 The inline ability is enabled by prefixing every data / function 373 declaration and definition with one of the following: 374 375 376 INLINE_<module> 377 378 Prefix to any global function that is a candidate for being 379 inline. 380 381 values - `', `static', `static INLINE' 382 383 384 EXTERN_<module> 385 386 Prefix to any global data structures for the module. Global 387 functions that are not to be inlined shall also be prefixed 388 with this. 389 390 values - `', `static', `static' 391 392 393 STATIC_INLINE_<module> 394 395 Prefix to any local (static) function that is a candidate for 396 being made inline. 397 398 values - `static', `static INLINE' 399 400 401 static 402 403 Prefix all local data structures. Local functions that are not 404 to be inlined shall also be prefixed with this. 405 406 values - `static', `static' 407 408 nb: will not work for modules that are being inlined for every 409 use (white lie). 410 411 412 extern 413 #ifndef _INLINE_C_ 414 #endif 415 416 Prefix to any declaration of a global object (function or 417 variable) that should not be inlined and should have only one 418 definition. The #ifndef wrapper goes around the definition 419 propper to ensure that only one copy is generated. 420 421 nb: this will not work when a module is being inlined for every 422 use. 423 424 425 STATIC_<module> 426 427 Replaced by either `static' or `EXTERN_MODULE'. 428 429 430 REALITY CHECK: 431 432 This is not for the faint hearted. I've seen GCC get up to 500mb 433 trying to compile what this can create. 434 435 Some of the modules do not yet implement the WITH_INLINE_STATIC 436 option. Instead they use the macro STATIC_INLINE to control their 437 local function. 438 439 Because of the way that GCC parses __attribute__(), the macro's 440 need to be adjacent to the function name rather than at the start 441 of the line vis: 442 443 int STATIC_INLINE_MODULE f(void); 444 void INLINE_MODULE *g(void); 445 446 */ 447 448 #define REVEAL_MODULE 1 449 #define INLINE_MODULE 2 450 #define INCLUDE_MODULE (INLINE_MODULE | REVEAL_MODULE) 451 #define PSIM_INLINE_LOCALS 4 452 #define ALL_INLINE 7 453 454 /* Your compilers inline reserved word */ 455 456 #ifndef INLINE 457 #if defined(__GNUC__) && defined(__OPTIMIZE__) 458 #define INLINE __inline__ 459 #else 460 #define INLINE /*inline*/ 461 #endif 462 #endif 463 464 465 /* Your compilers pass parameters in registers reserved word */ 466 467 #ifndef WITH_REGPARM 468 #define WITH_REGPARM 0 469 #endif 470 471 /* Your compilers use an alternative calling sequence reserved word */ 472 473 #ifndef WITH_STDCALL 474 #define WITH_STDCALL 0 475 #endif 476 477 #if !defined REGPARM 478 #if defined(__GNUC__) && (defined(__i386__) || defined(__i486__) || defined(__i586__) || defined(__i686__)) 479 #if (WITH_REGPARM && WITH_STDCALL) 480 #define REGPARM __attribute__((__regparm__(WITH_REGPARM),__stdcall__)) 481 #else 482 #if (WITH_REGPARM && !WITH_STDCALL) 483 #define REGPARM __attribute__((__regparm__(WITH_REGPARM))) 484 #else 485 #if (!WITH_REGPARM && WITH_STDCALL) 486 #define REGPARM __attribute__((__stdcall__)) 487 #endif 488 #endif 489 #endif 490 #endif 491 #endif 492 493 #if !defined REGPARM 494 #define REGPARM 495 #endif 496 497 498 499 /* Default prefix for static functions */ 500 501 #ifndef STATIC_INLINE 502 #define STATIC_INLINE static INLINE 503 #endif 504 505 /* Default macro to simplify control several of key the inlines */ 506 507 #ifndef DEFAULT_INLINE 508 #define DEFAULT_INLINE PSIM_INLINE_LOCALS 509 #endif 510 511 /* Code that converts between hosts and target byte order. Used on 512 every memory access (instruction and data). See sim-endian.h for 513 additional byte swapping configuration information. This module 514 can inline for all callers */ 515 516 #ifndef SIM_ENDIAN_INLINE 517 #define SIM_ENDIAN_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 518 #endif 519 520 /* Low level bit manipulation routines. This module can inline for all 521 callers */ 522 523 #ifndef BITS_INLINE 524 #define BITS_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 525 #endif 526 527 /* Code that gives access to various CPU internals such as registers. 528 Used every time an instruction is executed */ 529 530 #ifndef CPU_INLINE 531 #define CPU_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 532 #endif 533 534 /* Code that translates between an effective and real address. Used 535 by every load or store. */ 536 537 #ifndef VM_INLINE 538 #define VM_INLINE DEFAULT_INLINE 539 #endif 540 541 /* Code that loads/stores data to/from the memory data structure. 542 Used by every load or store */ 543 544 #ifndef CORE_INLINE 545 #define CORE_INLINE DEFAULT_INLINE 546 #endif 547 548 /* Code to check for and process any events scheduled in the future. 549 Called once per instruction cycle */ 550 551 #ifndef EVENTS_INLINE 552 #define EVENTS_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 553 #endif 554 555 /* Code monotoring the processors performance. It counts events on 556 every instruction cycle */ 557 558 #ifndef MON_INLINE 559 #define MON_INLINE (DEFAULT_INLINE ? ALL_INLINE : 0) 560 #endif 561 562 /* Code called on the rare occasions that an interrupt occures. */ 563 564 #ifndef INTERRUPTS_INLINE 565 #define INTERRUPTS_INLINE DEFAULT_INLINE 566 #endif 567 568 /* Code called on the rare occasion that either gdb or the device tree 569 need to manipulate a register within a processor */ 570 571 #ifndef REGISTERS_INLINE 572 #define REGISTERS_INLINE DEFAULT_INLINE 573 #endif 574 575 /* Code called on the rare occasion that a processor is manipulating 576 real hardware instead of RAM. 577 578 Also, most of the functions in devices.c are always called through 579 a jump table. */ 580 581 #ifndef DEVICE_INLINE 582 #define DEVICE_INLINE (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0) 583 #endif 584 585 /* Code called used while the device tree is being built. 586 587 Inlining this is of no benefit */ 588 589 #ifndef TREE_INLINE 590 #define TREE_INLINE (DEFAULT_INLINE ? PSIM_INLINE_LOCALS : 0) 591 #endif 592 593 /* Code called whenever information on a Special Purpose Register is 594 required. Called by the mflr/mtlr pseudo instructions */ 595 596 #ifndef SPREG_INLINE 597 #define SPREG_INLINE DEFAULT_INLINE 598 #endif 599 600 /* Functions modeling the semantics of each instruction. Two cases to 601 consider, firstly of idecode is implemented with a switch then this 602 allows the idecode function to inline each semantic function 603 (avoiding a call). The second case is when idecode is using a 604 table, even then while the semantic functions can't be inlined, 605 setting it to one still enables each semantic function to inline 606 anything they call (if that code is marked for being inlined). 607 608 WARNING: you need lots (like 200mb of swap) of swap. Setting this 609 to 1 is useful when using a table as it enables the sematic code to 610 inline all of their called functions */ 611 612 #ifndef SEMANTICS_INLINE 613 #define SEMANTICS_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 614 #endif 615 616 /* When using the instruction cache, code to decode an instruction and 617 install it into the cache. Normally called when ever there is a 618 miss in the instruction cache. */ 619 620 #ifndef ICACHE_INLINE 621 #define ICACHE_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 622 #endif 623 624 /* General functions called by semantics functions but part of the 625 instruction table. Although called by the semantic functions the 626 frequency of calls is low. Consequently the need to inline this 627 code is reduced. */ 628 629 #ifndef SUPPORT_INLINE 630 #define SUPPORT_INLINE PSIM_INLINE_LOCALS 631 #endif 632 633 /* Model specific code used in simulating functional units. Note, it actaully 634 pays NOT to inline the PowerPC model functions (at least on the x86). This 635 is because if it is inlined, each PowerPC instruction gets a separate copy 636 of the code, which is not friendly to the cache. */ 637 638 #ifndef MODEL_INLINE 639 #define MODEL_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 640 #endif 641 642 /* Code to print out what options we were compiled with. Because this 643 is called at process startup, it doesn't have to be inlined, but 644 if it isn't brought in and the model routines are inline, the model 645 routines will be pulled in twice. */ 646 647 #ifndef OPTIONS_INLINE 648 #define OPTIONS_INLINE MODEL_INLINE 649 #endif 650 651 /* idecode acts as the hub of the system, everything else is imported 652 into this file */ 653 654 #ifndef IDECOCE_INLINE 655 #define IDECODE_INLINE PSIM_INLINE_LOCALS 656 #endif 657 658 /* psim, isn't actually inlined */ 659 660 #ifndef PSIM_INLINE 661 #define PSIM_INLINE PSIM_INLINE_LOCALS 662 #endif 663 664 /* Code to emulate os or rom compatibility. This code is called via a 665 table and hence there is little benefit in making it inline */ 666 667 #ifndef OS_EMUL_INLINE 668 #define OS_EMUL_INLINE 0 669 #endif 670 671 #endif /* _PSIM_CONFIG_H */ 672