1 /* OpenRISC simulator support code 2 Copyright (C) 2017-2024 Free Software Foundation, Inc. 3 4 This file is part of GDB, the GNU debugger. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 18 19 /* This must come before any other includes. */ 20 #include "defs.h" 21 22 #define WANT_CPU_OR1K32BF 23 #define WANT_CPU 24 25 #include "sim-main.h" 26 #include "symcat.h" 27 #include "cgen-ops.h" 28 #include "cgen-mem.h" 29 #include "cpuall.h" 30 31 #include <string.h> 32 33 int 34 or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len) 35 { 36 if (rn < 32) 37 SETTWI (buf, GET_H_GPR (rn)); 38 else 39 switch (rn) 40 { 41 case PPC_REGNUM: 42 SETTWI (buf, GET_H_SYS_PPC ()); 43 break; 44 case PC_REGNUM: 45 SETTWI (buf, GET_H_PC ()); 46 break; 47 case SR_REGNUM: 48 SETTWI (buf, GET_H_SYS_SR ()); 49 break; 50 default: 51 return 0; 52 } 53 return sizeof (WI); /* WI from arch.h */ 54 } 55 56 int 57 or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, int len) 58 { 59 if (rn < 32) 60 SET_H_GPR (rn, GETTWI (buf)); 61 else 62 switch (rn) 63 { 64 case PPC_REGNUM: 65 SET_H_SYS_PPC (GETTWI (buf)); 66 break; 67 case PC_REGNUM: 68 SET_H_PC (GETTWI (buf)); 69 break; 70 case SR_REGNUM: 71 SET_H_SYS_SR (GETTWI (buf)); 72 break; 73 default: 74 return 0; 75 } 76 return sizeof (WI); /* WI from arch.h */ 77 } 78 79 int 80 or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc, 81 int unit_num, int referenced) 82 { 83 return -1; 84 } 85 86 int 87 or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc, 88 int unit_num, int referenced) 89 { 90 return -1; 91 } 92 93 void 94 or1k32bf_model_insn_before (sim_cpu *current_cpu, int first_p) 95 { 96 } 97 98 void 99 or1k32bf_model_insn_after (sim_cpu *current_cpu, int last_p, int cycles) 100 { 101 } 102 103 USI 104 or1k32bf_h_spr_get_raw (sim_cpu *current_cpu, USI addr) 105 { 106 SIM_DESC sd = CPU_STATE (current_cpu); 107 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 108 109 SIM_ASSERT (addr < NUM_SPR); 110 return or1k_cpu->spr[addr]; 111 } 112 113 void 114 or1k32bf_h_spr_set_raw (sim_cpu *current_cpu, USI addr, USI val) 115 { 116 SIM_DESC sd = CPU_STATE (current_cpu); 117 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 118 119 SIM_ASSERT (addr < NUM_SPR); 120 or1k_cpu->spr[addr] = val; 121 } 122 123 USI 124 or1k32bf_h_spr_field_get_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb) 125 { 126 SIM_DESC sd = CPU_STATE (current_cpu); 127 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 128 129 SIM_ASSERT (addr < NUM_SPR); 130 return LSEXTRACTED (or1k_cpu->spr[addr], msb, lsb); 131 } 132 133 void 134 or1k32bf_h_spr_field_set_raw (sim_cpu *current_cpu, USI addr, int msb, int lsb, 135 USI val) 136 { 137 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 138 139 or1k_cpu->spr[addr] &= ~LSMASK32 (msb, lsb); 140 or1k_cpu->spr[addr] |= LSINSERTED (val, msb, lsb); 141 } 142 143 /* Initialize a sim cpu object. */ 144 void 145 or1k_cpu_init (SIM_DESC sd, sim_cpu *current_cpu, const USI or1k_vr, 146 const USI or1k_upr, const USI or1k_cpucfgr) 147 { 148 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 149 150 /* Set the configuration registers passed from the user. */ 151 SET_H_SYS_VR (or1k_vr); 152 SET_H_SYS_UPR (or1k_upr); 153 SET_H_SYS_CPUCFGR (or1k_cpucfgr); 154 155 #define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \ 156 do \ 157 { \ 158 USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \ 159 if (!(test)) \ 160 sim_io_eprintf \ 161 (sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \ 162 #FIELD, #INDEX, field); \ 163 } while (0) 164 165 /* Set flags indicating if we are in a delay slot or not. */ 166 or1k_cpu->next_delay_slot = 0; 167 or1k_cpu->delay_slot = 0; 168 169 /* Verify any user passed fields and warn on configurations we don't 170 support. */ 171 CHECK_SPR_FIELD (SYS, UPR, UP, field == 1); 172 CHECK_SPR_FIELD (SYS, UPR, DCP, field == 0); 173 CHECK_SPR_FIELD (SYS, UPR, ICP, field == 0); 174 CHECK_SPR_FIELD (SYS, UPR, DMP, field == 0); 175 CHECK_SPR_FIELD (SYS, UPR, MP, field == 0); 176 CHECK_SPR_FIELD (SYS, UPR, IMP, field == 0); 177 CHECK_SPR_FIELD (SYS, UPR, DUP, field == 0); 178 CHECK_SPR_FIELD (SYS, UPR, PCUP, field == 0); 179 CHECK_SPR_FIELD (SYS, UPR, PICP, field == 0); 180 CHECK_SPR_FIELD (SYS, UPR, PMP, field == 0); 181 CHECK_SPR_FIELD (SYS, UPR, TTP, field == 0); 182 CHECK_SPR_FIELD (SYS, UPR, CUP, field == 0); 183 184 CHECK_SPR_FIELD (SYS, CPUCFGR, NSGR, field == 0); 185 CHECK_SPR_FIELD (SYS, CPUCFGR, CGF, field == 0); 186 CHECK_SPR_FIELD (SYS, CPUCFGR, OB32S, field == 1); 187 CHECK_SPR_FIELD (SYS, CPUCFGR, OF32S, field == 1); 188 CHECK_SPR_FIELD (SYS, CPUCFGR, OB64S, field == 0); 189 CHECK_SPR_FIELD (SYS, CPUCFGR, OF64S, field == 0); 190 CHECK_SPR_FIELD (SYS, CPUCFGR, OV64S, field == 0); 191 192 #undef CHECK_SPR_FIELD 193 194 /* Configure the fpu operations and mark fpu available. */ 195 cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), 196 or1k32bf_fpu_error); 197 SET_H_SYS_CPUCFGR_OF32S (1); 198 199 /* Set the UPR[UP] flag, even if the user tried to unset it, as we always 200 support the Unit Present Register. */ 201 SET_H_SYS_UPR_UP (1); 202 203 /* Set the supervisor register to indicate we are in supervisor mode and 204 set the Fixed-One bit which must always be set. */ 205 SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM | SPR_FIELD_MASK_SYS_SR_FO); 206 207 /* Clear the floating point control status register. */ 208 SET_H_SYS_FPCSR (0); 209 } 210 211 void 212 or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc) 213 { 214 SIM_DESC sd = CPU_STATE (current_cpu); 215 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 216 217 or1k_cpu->delay_slot = or1k_cpu->next_delay_slot; 218 or1k_cpu->next_delay_slot = 0; 219 220 if (or1k_cpu->delay_slot && 221 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & 222 CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT)) 223 { 224 USI pc; 225 #ifdef WITH_SCACHE 226 pc = vpc->argbuf.addr; 227 #else 228 pc = vpc; 229 #endif 230 sim_io_error (sd, "invalid instruction in a delay slot at PC 0x%08x", 231 pc); 232 } 233 234 } 235 236 void 237 or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, const IDESC *idesc) 238 { 239 SIM_DESC sd = CPU_STATE (current_cpu); 240 struct or1k_sim_cpu *or1k_cpu = OR1K_SIM_CPU (current_cpu); 241 USI ppc; 242 243 #ifdef WITH_SCACHE 244 ppc = vpc->argbuf.addr; 245 #else 246 ppc = vpc; 247 #endif 248 249 SET_H_SYS_PPC (ppc); 250 251 if (!GET_H_SYS_CPUCFGR_ND () && 252 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc)->idata)) & 253 CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI)) 254 { 255 SIM_ASSERT (!or1k_cpu->delay_slot); 256 or1k_cpu->next_delay_slot = 1; 257 } 258 } 259 260 void 261 or1k32bf_nop (sim_cpu *current_cpu, USI uimm16) 262 { 263 SIM_DESC sd = CPU_STATE (current_cpu); 264 265 switch (uimm16) 266 { 267 268 case NOP_NOP: 269 break; 270 271 case NOP_EXIT: 272 sim_io_printf (CPU_STATE (current_cpu), "exit(%d)\n", GET_H_GPR (3)); 273 ATTRIBUTE_FALLTHROUGH; 274 case NOP_EXIT_SILENT: 275 sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu), 276 sim_exited, GET_H_GPR (3)); 277 break; 278 279 case NOP_REPORT: 280 sim_io_printf (CPU_STATE (current_cpu), "report(0x%08x);\n", 281 GET_H_GPR (3)); 282 break; 283 284 case NOP_PUTC: 285 sim_io_printf (CPU_STATE (current_cpu), "%c", 286 (char) (GET_H_GPR (3) & 0xff)); 287 break; 288 289 default: 290 sim_io_eprintf (sd, "WARNING: l.nop with unsupported code 0x%08x\n", 291 uimm16); 292 break; 293 } 294 295 } 296 297 /* Build an address value used for load and store instructions. For example, 298 the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte 299 address represented by rA + I. Here the argument base is rA, offset is I 300 and the size is the read size in bytes. Note, OpenRISC requires that word 301 and half-word access be word and half-word aligned respectively, the check 302 for alignment is not needed here. */ 303 304 USI 305 or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, 306 int size) 307 { 308 SIM_DESC sd = CPU_STATE (current_cpu); 309 310 USI addr = base + offset; 311 312 /* If little endian load/store is enabled we adjust the byte and half-word 313 addresses to the little endian equivalent. */ 314 if (GET_H_SYS_SR_LEE ()) 315 { 316 switch (size) 317 { 318 319 case 4: /* We are retrieving the entire word no adjustment. */ 320 break; 321 322 case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0. */ 323 addr ^= 0x2; 324 break; 325 326 case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc. */ 327 addr ^= 0x3; 328 break; 329 330 default: 331 SIM_ASSERT (0); 332 return 0; 333 } 334 } 335 336 return addr; 337 } 338 339 /* The find first 1 instruction returns the location of the first set bit 340 in the argument register. */ 341 342 USI 343 or1k32bf_ff1 (sim_cpu *current_cpu, USI val) 344 { 345 USI bit; 346 USI ret; 347 for (bit = 1, ret = 1; bit; bit <<= 1, ret++) 348 { 349 if (val & bit) 350 return ret; 351 } 352 return 0; 353 } 354 355 /* The find last 1 instruction returns the location of the last set bit in 356 the argument register. */ 357 358 USI 359 or1k32bf_fl1 (sim_cpu *current_cpu, USI val) 360 { 361 USI bit; 362 USI ret; 363 for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--) 364 { 365 if (val & bit) 366 return ret; 367 } 368 return 0; 369 } 370