1// -*- C -*- 2// 3// <insn> ::= 4// <insn-word> { "+" <insn-word> } 5// ":" <format-name> 6// ":" <filter-flags> 7// ":" <options> 8// ":" <name> 9// <nl> 10// { <insn-model> } 11// { <insn-mnemonic> } 12// <code-block> 13// 14 15 16// IGEN config - mips16 17// :option:16::insn-bit-size:16 18// :option:16::hi-bit-nr:15 19:option:16::insn-specifying-widths:true 20:option:16::gen-delayed-branch:false 21 22// IGEN config - mips32/64.. 23// :option:32::insn-bit-size:32 24// :option:32::hi-bit-nr:31 25:option:32::insn-specifying-widths:true 26:option:32::gen-delayed-branch:false 27 28 29// Generate separate simulators for each target 30// :option:::multi-sim:true 31 32 33// Models known by this simulator are defined below. 34// 35// When placing models in the instruction descriptions, please place 36// them one per line, in the order given here. 37 38// MIPS ISAs: 39// 40// Instructions and related functions for these models are included in 41// this file. 42:model:::mipsI:mips3000: 43:model:::mipsII:mips6000: 44:model:::mipsIII:mips4000: 45:model:::mipsIV:mips8000: 46:model:::mipsV:mipsisaV: 47:model:::mips32:mipsisa32: 48:model:::mips32r2:mipsisa32r2: 49:model:::mips32r6:mipsisa32r6: 50:model:::mips64:mipsisa64: 51:model:::mips64r2:mipsisa64r2: 52:model:::mips64r6:mipsisa64r6: 53 54// Vendor ISAs: 55// 56// Standard MIPS ISA instructions used for these models are listed here, 57// as are functions needed by those standard instructions. Instructions 58// which are model-dependent and which are not in the standard MIPS ISAs 59// (or which pre-date or use different encodings than the standard 60// instructions) are (for the most part) in separate .igen files. 61:model:::vr4100:mips4100: // vr.igen 62:model:::vr4120:mips4120: 63:model:::vr5000:mips5000: 64:model:::vr5400:mips5400: 65:model:::vr5500:mips5500: 66:model:::r3900:mips3900: // tx.igen 67 68// MIPS Application Specific Extensions (ASEs) 69// 70// Instructions for the ASEs are in separate .igen files. 71// ASEs add instructions on to a base ISA. 72:model:::mips16:mips16: // m16.igen (and m16.dc) 73:model:::mips16e:mips16e: // m16e.igen 74:model:::mips3d:mips3d: // mips3d.igen 75:model:::mdmx:mdmx: // mdmx.igen 76:model:::dsp:dsp: // dsp.igen 77:model:::dsp2:dsp2: // dsp2.igen 78:model:::smartmips:smartmips: // smartmips.igen 79:model:::micromips32:micromips64: // micromips.igen 80:model:::micromips64:micromips64: // micromips.igen 81:model:::micromipsdsp:micromipsdsp: // micromipsdsp.igen 82 83// Vendor Extensions 84// 85// Instructions specific to these extensions are in separate .igen files. 86// Extensions add instructions on to a base ISA. 87:model:::sb1:sb1: // sb1.igen 88 89 90// Pseudo instructions known by IGEN 91:internal::::illegal: 92{ 93 SignalException (ReservedInstruction, 0); 94} 95 96 97// Pseudo instructions known by interp.c 98// For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK 99000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD 100"rsvd <OP>" 101{ 102 SignalException (ReservedInstruction, instruction_0); 103} 104 105 106 107// Helpers: 108// 109// Check if given instruction is CTI, if so signal 110// 111:function:::void:signal_if_cti:instruction_word instr 112{ 113 uint32_t maj = (instr & 0xfc000000) >> 26; 114 uint32_t special = instr & 0x3f; 115 if ((maj & 0x3e) == 0x06 /* Branch/Jump */ 116 || ((maj & 0x38) == 0 && !((maj & 0x6) == 0)) 117 || maj == 0x18 118 || (maj & 0x37) == 0x32 119 || (maj & 0x37) == 0x36 120 || ((maj == 0) && (special == 0x9)) 121 /* DERET/ERET/WAIT */ 122 || ((maj == 0x10) && (instr & 0x02000000) 123 && (special == 0x1f || special == 0x18 || special == 0x20))) 124 { 125 SignalException (ReservedInstruction, instr); 126 } 127} 128 129// 130// Simulate a 32 bit delayslot instruction 131// 132 133:function:::address_word:delayslot32:address_word target 134{ 135 instruction_word delay_insn; 136 sim_events_slip (SD, 1); 137 DSPC = CIA; 138 CIA = CIA + 4; /* NOTE not mips16 */ 139 STATE |= simDELAYSLOT; 140 delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ 141 signal_if_cti (SD_, delay_insn); 142 ENGINE_ISSUE_PREFIX_HOOK(); 143 idecode_issue (CPU_, delay_insn, (CIA)); 144 STATE &= ~simDELAYSLOT; 145 return target; 146} 147 148// 149// Simulate a 32 bit forbidden slot instruction 150// 151 152:function:::address_word:forbiddenslot32: 153*mips32r6: 154*mips64r6: 155{ 156 instruction_word delay_insn; 157 sim_events_slip (SD, 1); 158 DSPC = CIA; 159 CIA = CIA + 4; 160 STATE |= simFORBIDDENSLOT; 161 delay_insn = IMEM32 (CIA); 162 signal_if_cti (SD_, delay_insn); 163 ENGINE_ISSUE_PREFIX_HOOK (); 164 idecode_issue (CPU_, delay_insn, (CIA)); 165 STATE &= ~simFORBIDDENSLOT; 166 return CIA + 4; 167} 168 169:function:::address_word:nullify_next_insn32: 170{ 171 sim_events_slip (SD, 1); 172 dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction"); 173 return CIA + 8; 174} 175 176 177// Helper: 178// 179// Calculate an effective address given a base and an offset. 180// 181 182:function:::address_word:loadstore_ea:address_word base, address_word offset 183*mipsI: 184*mipsII: 185*mipsIII: 186*mipsIV: 187*mipsV: 188*mips32: 189*mips32r2: 190*mips32r6: 191*vr4100: 192*vr5000: 193*r3900: 194*micromips32: 195{ 196 return base + offset; 197} 198 199:function:::address_word:loadstore_ea:address_word base, address_word offset 200*mips64: 201*mips64r2: 202*micromips64: 203*mips64r6: 204{ 205#if 0 /* XXX FIXME: enable this only after some additional testing. */ 206 /* If in user mode and UX is not set, use 32-bit compatibility effective 207 address computations as defined in the MIPS64 Architecture for 208 Programmers Volume III, Revision 0.95, section 4.9. */ 209 if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX)) 210 == (ksu_user << status_KSU_shift)) 211 return (address_word)((int32_t)base + (int32_t)offset); 212#endif 213 return base + offset; 214} 215 216 217// Helper: 218// 219// Check that a 32-bit register value is properly sign-extended. 220// (See NotWordValue in ISA spec.) 221// 222 223:function:::int:not_word_value:unsigned_word value 224*mipsI: 225*mipsII: 226*mipsIII: 227*mipsIV: 228*mipsV: 229*vr4100: 230*vr5000: 231*r3900: 232*mips32: 233*mips32r2: 234*mips32r6: 235*mips64: 236*mips64r2: 237*micromips32: 238*micromips64: 239*mips64r6: 240{ 241#if WITH_TARGET_WORD_BITSIZE == 64 242 return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 243#else 244 return 0; 245#endif 246} 247 248// Helper: 249// 250// Handle UNPREDICTABLE operation behaviour. The goal here is to prevent 251// theoretically portable code which invokes non-portable behaviour from 252// running with no indication of the portability issue. 253// (See definition of UNPREDICTABLE in ISA spec.) 254// 255 256:function:::void:unpredictable: 257*mipsI: 258*mipsII: 259*mipsIII: 260*mipsIV: 261*mipsV: 262*vr4100: 263*vr5000: 264*r3900: 265{ 266} 267 268:function:::void:unpredictable: 269*mips32: 270*mips32r2: 271*mips32r6: 272*mips64: 273*mips64r2: 274*micromips32: 275*micromips64: 276*mips64r6: 277{ 278 unpredictable_action (CPU, CIA); 279} 280 281 282// Helpers: 283// 284// Check that an access to a HI/LO register meets timing requirements 285// 286// In all MIPS ISAs, 287// 288// OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO}) 289// makes subsequent MF{HI or LO} UNPREDICTABLE. (1) 290// 291// The following restrictions exist for MIPS I - MIPS III: 292// 293// MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions 294// in between makes MF UNPREDICTABLE. (2) 295// 296// MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions 297// in between makes MF UNPREDICTABLE. (3) 298// 299// On the r3900, restriction (2) is not present, and restriction (3) is not 300// present for multiplication. 301// 302// Unfortunately, there seems to be some confusion about whether the last 303// two restrictions should apply to "MIPS IV" as well. One edition of 304// the MIPS IV ISA says they do, but references in later ISA documents 305// suggest they don't. 306// 307// In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have 308// these restrictions, while others, like the VR5500, don't. To accomodate 309// such differences, the MIPS IV and MIPS V version of these helper functions 310// use auxillary routines to determine whether the restriction applies. 311 312// check_mf_cycles: 313// 314// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo 315// to check for restrictions (2) and (3) above. 316// 317:function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new 318{ 319 if (history->mf.timestamp + 3 > time) 320 { 321 sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n", 322 itable[MY_INDEX].name, 323 new, (long) CIA, 324 (long) history->mf.cia); 325 return 0; 326 } 327 return 1; 328} 329 330 331// check_mt_hilo: 332// 333// Check for restriction (2) above (for ISAs/processors that have it), 334// and record timestamps for restriction (1) above. 335// 336:function:::int:check_mt_hilo:hilo_history *history 337*mipsI: 338*mipsII: 339*mipsIII: 340*vr4100: 341*vr5000: 342{ 343 int64_t time = sim_events_time (SD); 344 int ok = check_mf_cycles (SD_, history, time, "MT"); 345 history->mt.timestamp = time; 346 history->mt.cia = CIA; 347 return ok; 348} 349 350:function:::int:check_mt_hilo:hilo_history *history 351*mipsIV: 352*mipsV: 353{ 354 int64_t time = sim_events_time (SD); 355 int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD) 356 || check_mf_cycles (SD_, history, time, "MT")); 357 history->mt.timestamp = time; 358 history->mt.cia = CIA; 359 return ok; 360} 361 362:function:::int:check_mt_hilo:hilo_history *history 363*mips32: 364*mips32r2: 365*mips32r6: 366*mips64: 367*mips64r2: 368*mips64r6: 369*r3900: 370*micromips32: 371*micromips64: 372{ 373 int64_t time = sim_events_time (SD); 374 history->mt.timestamp = time; 375 history->mt.cia = CIA; 376 return 1; 377} 378 379 380// check_mf_hilo: 381// 382// Check for restriction (1) above, and record timestamps for 383// restriction (2) and (3) above. 384// 385:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer 386*mipsI: 387*mipsII: 388*mipsIII: 389*mipsIV: 390*mipsV: 391*mips32: 392*mips32r2: 393*mips32r6: 394*mips64: 395*mips64r2: 396*mips64r6: 397*vr4100: 398*vr5000: 399*r3900: 400*micromips32: 401*micromips64: 402{ 403 int64_t time = sim_events_time (SD); 404 int ok = 1; 405 if (peer != NULL 406 && peer->mt.timestamp > history->op.timestamp 407 && history->mt.timestamp < history->op.timestamp 408 && ! (history->mf.timestamp > history->op.timestamp 409 && history->mf.timestamp < peer->mt.timestamp) 410 && ! (peer->mf.timestamp > history->op.timestamp 411 && peer->mf.timestamp < peer->mt.timestamp)) 412 { 413 /* The peer has been written to since the last OP yet we have 414 not */ 415 sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n", 416 itable[MY_INDEX].name, 417 (long) CIA, 418 (long) history->op.cia, 419 (long) peer->mt.cia); 420 ok = 0; 421 } 422 history->mf.timestamp = time; 423 history->mf.cia = CIA; 424 return ok; 425} 426 427 428 429// check_mult_hilo: 430// 431// Check for restriction (3) above (for ISAs/processors that have it) 432// for MULT ops, and record timestamps for restriction (1) above. 433// 434:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 435*mipsI: 436*mipsII: 437*mipsIII: 438*vr4100: 439*vr5000: 440{ 441 int64_t time = sim_events_time (SD); 442 int ok = (check_mf_cycles (SD_, hi, time, "OP") 443 && check_mf_cycles (SD_, lo, time, "OP")); 444 hi->op.timestamp = time; 445 lo->op.timestamp = time; 446 hi->op.cia = CIA; 447 lo->op.cia = CIA; 448 return ok; 449} 450 451:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 452*mipsIV: 453*mipsV: 454{ 455 int64_t time = sim_events_time (SD); 456 int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD) 457 || (check_mf_cycles (SD_, hi, time, "OP") 458 && check_mf_cycles (SD_, lo, time, "OP"))); 459 hi->op.timestamp = time; 460 lo->op.timestamp = time; 461 hi->op.cia = CIA; 462 lo->op.cia = CIA; 463 return ok; 464} 465 466:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo 467*mips32: 468*mips32r2: 469*mips32r6: 470*mips64: 471*mips64r2: 472*mips64r6: 473*r3900: 474*micromips32: 475*micromips64: 476{ 477 /* FIXME: could record the fact that a stall occured if we want */ 478 int64_t time = sim_events_time (SD); 479 hi->op.timestamp = time; 480 lo->op.timestamp = time; 481 hi->op.cia = CIA; 482 lo->op.cia = CIA; 483 return 1; 484} 485 486 487// check_div_hilo: 488// 489// Check for restriction (3) above (for ISAs/processors that have it) 490// for DIV ops, and record timestamps for restriction (1) above. 491// 492:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 493*mipsI: 494*mipsII: 495*mipsIII: 496*vr4100: 497*vr5000: 498*r3900: 499{ 500 int64_t time = sim_events_time (SD); 501 int ok = (check_mf_cycles (SD_, hi, time, "OP") 502 && check_mf_cycles (SD_, lo, time, "OP")); 503 hi->op.timestamp = time; 504 lo->op.timestamp = time; 505 hi->op.cia = CIA; 506 lo->op.cia = CIA; 507 return ok; 508} 509 510:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 511*mipsIV: 512*mipsV: 513{ 514 int64_t time = sim_events_time (SD); 515 int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD) 516 || (check_mf_cycles (SD_, hi, time, "OP") 517 && check_mf_cycles (SD_, lo, time, "OP"))); 518 hi->op.timestamp = time; 519 lo->op.timestamp = time; 520 hi->op.cia = CIA; 521 lo->op.cia = CIA; 522 return ok; 523} 524 525:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo 526*mips32: 527*mips32r2: 528*mips32r6: 529*mips64: 530*mips64r2: 531*micromips32: 532*micromips64: 533*mips64r6: 534{ 535 int64_t time = sim_events_time (SD); 536 hi->op.timestamp = time; 537 lo->op.timestamp = time; 538 hi->op.cia = CIA; 539 lo->op.cia = CIA; 540 return 1; 541} 542 543 544// Helper: 545// 546// Check that the 64-bit instruction can currently be used, and signal 547// a ReservedInstruction exception if not. 548// 549 550:function:::void:check_u64:instruction_word insn 551*mipsIII: 552*mipsIV: 553*mipsV: 554*vr4100: 555*vr5000: 556*vr5400: 557*vr5500: 558*r3900: 559{ 560 // The check should be similar to mips64 for any with PX/UX bit equivalents. 561} 562 563:function:::void:check_u64:instruction_word insn 564*mips16e: 565*mips64: 566*mips64r2: 567*mips32: 568*mips32r2: 569*mips32r6: 570*micromips64: 571*micromips32: 572*mips64r6: 573{ 574#if 0 /* XXX FIXME: enable this only after some additional testing. */ 575 if (UserMode && (SR & (status_UX|status_PX)) == 0) 576 SignalException (ReservedInstruction, insn); 577#endif 578} 579 580 581 582// 583// MIPS Architecture: 584// 585// CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2) 586// 587 588 589:function:::void:do_add:int rs, int rt, int rd 590{ 591 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 592 Unpredictable (); 593 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 594 { 595 ALU32_BEGIN (GPR[rs]); 596 ALU32_ADD (GPR[rt]); 597 ALU32_END (GPR[rd]); /* This checks for overflow. */ 598 } 599 TRACE_ALU_RESULT (GPR[rd]); 600} 601 602:function:::void:do_addi:int rs, int rt, uint16_t immediate 603{ 604 if (NotWordValue (GPR[rs])) 605 Unpredictable (); 606 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 607 { 608 ALU32_BEGIN (GPR[rs]); 609 ALU32_ADD (EXTEND16 (immediate)); 610 ALU32_END (GPR[rt]); /* This checks for overflow. */ 611 } 612 TRACE_ALU_RESULT (GPR[rt]); 613} 614 615:function:::void:do_andi:int rs, int rt, unsigned int immediate 616{ 617 TRACE_ALU_INPUT2 (GPR[rs], immediate); 618 GPR[rt] = GPR[rs] & immediate; 619 TRACE_ALU_RESULT (GPR[rt]); 620} 621 622:function:::void:do_dadd:int rd, int rs, int rt 623{ 624 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 625 { 626 ALU64_BEGIN (GPR[rs]); 627 ALU64_ADD (GPR[rt]); 628 ALU64_END (GPR[rd]); /* This checks for overflow. */ 629 } 630 TRACE_ALU_RESULT (GPR[rd]); 631} 632 633:function:::void:do_daddi:int rt, int rs, int immediate 634{ 635 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 636 { 637 ALU64_BEGIN (GPR[rs]); 638 ALU64_ADD (EXTEND16 (immediate)); 639 ALU64_END (GPR[rt]); /* This checks for overflow. */ 640 } 641 TRACE_ALU_RESULT (GPR[rt]); 642} 643 644:function:::void:do_dsll32:int rd, int rt, int shift 645{ 646 int s = 32 + shift; 647 TRACE_ALU_INPUT2 (GPR[rt], s); 648 GPR[rd] = GPR[rt] << s; 649 TRACE_ALU_RESULT (GPR[rd]); 650} 651 652:function:::void:do_dsra32:int rd, int rt, int shift 653{ 654 int s = 32 + shift; 655 TRACE_ALU_INPUT2 (GPR[rt], s); 656 GPR[rd] = ((int64_t) GPR[rt]) >> s; 657 TRACE_ALU_RESULT (GPR[rd]); 658} 659 660:function:::void:do_dsrl32:int rd, int rt, int shift 661{ 662 int s = 32 + shift; 663 TRACE_ALU_INPUT2 (GPR[rt], s); 664 GPR[rd] = (uint64_t) GPR[rt] >> s; 665 TRACE_ALU_RESULT (GPR[rd]); 666} 667 668:function:::void:do_dsub:int rd, int rs, int rt 669{ 670 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 671 { 672 ALU64_BEGIN (GPR[rs]); 673 ALU64_SUB (GPR[rt]); 674 ALU64_END (GPR[rd]); /* This checks for overflow. */ 675 } 676 TRACE_ALU_RESULT (GPR[rd]); 677} 678 679:function:::void:do_break:address_word instruction_0 680{ 681 /* Check for some break instruction which are reserved for use by the 682 simulator. */ 683 unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK; 684 if (break_code == (HALT_INSTRUCTION & HALT_INSTRUCTION_MASK) || 685 break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) 686 { 687 sim_engine_halt (SD, CPU, NULL, cia, 688 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF)); 689 } 690 else if (break_code == (BREAKPOINT_INSTRUCTION & HALT_INSTRUCTION_MASK) || 691 break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK)) 692 { 693 if (STATE & simDELAYSLOT) 694 PC = cia - 4; /* reference the branch instruction */ 695 else 696 PC = cia; 697 SignalException (BreakPoint, instruction_0); 698 } 699 700 else 701 { 702 /* If we get this far, we're not an instruction reserved by the sim. Raise 703 the exception. */ 704 SignalException (BreakPoint, instruction_0); 705 } 706} 707 708:function:::void:do_break16:address_word instruction_0 709{ 710 if (STATE & simDELAYSLOT) 711 PC = cia - 2; /* reference the branch instruction */ 712 else 713 PC = cia; 714 SignalException (BreakPoint, instruction_0); 715} 716 717:function:::void:do_clo:int rd, int rs 718{ 719 uint32_t temp = GPR[rs]; 720 uint32_t i, mask; 721 if (NotWordValue (GPR[rs])) 722 Unpredictable (); 723 TRACE_ALU_INPUT1 (GPR[rs]); 724 for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) 725 { 726 if ((temp & mask) == 0) 727 break; 728 mask >>= 1; 729 } 730 GPR[rd] = EXTEND32 (i); 731 TRACE_ALU_RESULT (GPR[rd]); 732} 733 734:function:::void:do_clz:int rd, int rs 735{ 736 uint32_t temp = GPR[rs]; 737 uint32_t i, mask; 738 if (NotWordValue (GPR[rs])) 739 Unpredictable (); 740 TRACE_ALU_INPUT1 (GPR[rs]); 741 for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i) 742 { 743 if ((temp & mask) != 0) 744 break; 745 mask >>= 1; 746 } 747 GPR[rd] = EXTEND32 (i); 748 TRACE_ALU_RESULT (GPR[rd]); 749} 750 751:function:::void:do_dclo:int rd, int rs 752{ 753 uint64_t temp = GPR[rs]; 754 uint32_t i; 755 uint64_t mask; 756 TRACE_ALU_INPUT1 (GPR[rs]); 757 for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) 758 { 759 if ((temp & mask) == 0) 760 break; 761 mask >>= 1; 762 } 763 GPR[rd] = EXTEND32 (i); 764 TRACE_ALU_RESULT (GPR[rd]); 765} 766 767:function:::void:do_dclz:int rd, int rs 768{ 769 uint64_t temp = GPR[rs]; 770 uint32_t i; 771 uint64_t mask; 772 TRACE_ALU_INPUT1 (GPR[rs]); 773 for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i) 774 { 775 if ((temp & mask) != 0) 776 break; 777 mask >>= 1; 778 } 779 GPR[rd] = EXTEND32 (i); 780 TRACE_ALU_RESULT (GPR[rd]); 781} 782 783:function:::void:do_lb:int rt, int offset, int base 784{ 785 GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base], 786 EXTEND16 (offset))); 787} 788 789:function:::void:do_lh:int rt, int offset, int base 790{ 791 GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base], 792 EXTEND16 (offset))); 793} 794 795:function:::void:do_lwr:int rt, int offset, int base 796{ 797 GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base], 798 EXTEND16 (offset), GPR[rt])); 799} 800 801:function:::void:do_lwl:int rt, int offset, int base 802{ 803 GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base], 804 EXTEND16 (offset), GPR[rt])); 805} 806 807:function:::void:do_lwc:int num, int rt, int offset, int base 808{ 809 COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base], 810 EXTEND16 (offset))); 811} 812 813:function:::void:do_lw:int rt, int offset, int base 814{ 815 GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base], 816 EXTEND16 (offset))); 817} 818 819:function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0 820{ 821 check_u64 (SD_, instruction_0); 822 GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset)); 823} 824 825:function:::void:do_lhu:int rt, int offset, int base 826{ 827 GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset)); 828} 829 830:function:::void:do_ldc:int num, int rt, int offset, int base 831{ 832 COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base], 833 EXTEND16 (offset))); 834} 835 836:function:::void:do_lbu:int rt, int offset, int base 837{ 838 GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset)); 839} 840 841:function:::void:do_ll:int rt, int insn_offset, int basereg 842{ 843 address_word base = GPR[basereg]; 844 address_word offset = EXTEND16 (insn_offset); 845 { 846 address_word vaddr = loadstore_ea (SD_, base, offset); 847 address_word paddr = vaddr; 848 if ((vaddr & 3) != 0) 849 { 850 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, 851 sim_core_unaligned_signal); 852 } 853 else 854 { 855 uint64_t memval = 0; 856 uint64_t memval1 = 0; 857 uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 858 unsigned int shift = 2; 859 unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0); 860 unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0); 861 unsigned int byte; 862 paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift))); 863 LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr, 864 isDATA, isREAL); 865 byte = ((vaddr & mask) ^ (bigend << shift)); 866 GPR[rt] = EXTEND32 (memval >> (8 * byte)); 867 LLBIT = 1; 868 } 869 } 870} 871 872:function:::void:do_lld:int rt, int roffset, int rbase 873{ 874 address_word base = GPR[rbase]; 875 address_word offset = EXTEND16 (roffset); 876 { 877 address_word vaddr = loadstore_ea (SD_, base, offset); 878 address_word paddr = vaddr; 879 880 if ((vaddr & 7) != 0) 881 { 882 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, 883 sim_core_unaligned_signal); 884 } 885 else 886 { 887 uint64_t memval = 0; 888 uint64_t memval1 = 0; 889 LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr, 890 isDATA, isREAL); 891 GPR[rt] = memval; 892 LLBIT = 1; 893 } 894 } 895} 896 897:function:::void:do_lui:int rt, int immediate 898{ 899 TRACE_ALU_INPUT1 (immediate); 900 GPR[rt] = EXTEND32 (immediate << 16); 901 TRACE_ALU_RESULT (GPR[rt]); 902} 903 904:function:::void:do_madd:int rs, int rt 905{ 906 int64_t temp; 907 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 908 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 909 Unpredictable (); 910 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 911 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 912 + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 913 LO = EXTEND32 (temp); 914 HI = EXTEND32 (VH4_8 (temp)); 915 TRACE_ALU_RESULT2 (HI, LO); 916} 917 918:function:::void:do_dsp_madd:int ac, int rs, int rt 919{ 920 int64_t temp; 921 if (ac == 0) 922 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 923 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 924 Unpredictable (); 925 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 926 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 927 + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 928 DSPLO(ac) = EXTEND32 (temp); 929 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 930 if (ac == 0) 931 TRACE_ALU_RESULT2 (HI, LO); 932} 933 934:function:::void:do_maddu:int rs, int rt 935{ 936 uint64_t temp; 937 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 938 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 939 Unpredictable (); 940 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 941 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 942 + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 943 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 944 LO = EXTEND32 (temp); 945 HI = EXTEND32 (VH4_8 (temp)); 946 TRACE_ALU_RESULT2 (HI, LO); 947} 948 949:function:::void:do_dsp_maddu:int ac, int rs, int rt 950{ 951 uint64_t temp; 952 if (ac == 0) 953 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 954 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 955 Unpredictable (); 956 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 957 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 958 + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 959 if (ac == 0) 960 ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp; /* SmartMIPS */ 961 DSPLO(ac) = EXTEND32 (temp); 962 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 963 if (ac == 0) 964 TRACE_ALU_RESULT2 (HI, LO); 965} 966 967:function:::void:do_dsp_mfhi:int ac, int rd 968{ 969 if (ac == 0) 970 do_mfhi (SD_, rd); 971 else 972 GPR[rd] = DSPHI(ac); 973} 974 975:function:::void:do_dsp_mflo:int ac, int rd 976{ 977 if (ac == 0) 978 do_mflo (SD_, rd); 979 else 980 GPR[rd] = DSPLO(ac); 981} 982 983:function:::void:do_movn:int rd, int rs, int rt 984{ 985 if (GPR[rt] != 0) 986 { 987 GPR[rd] = GPR[rs]; 988 TRACE_ALU_RESULT (GPR[rd]); 989 } 990} 991 992:function:::void:do_movz:int rd, int rs, int rt 993{ 994 if (GPR[rt] == 0) 995 { 996 GPR[rd] = GPR[rs]; 997 TRACE_ALU_RESULT (GPR[rd]); 998 } 999} 1000 1001:function:::void:do_msub:int rs, int rt 1002{ 1003 int64_t temp; 1004 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1005 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1006 Unpredictable (); 1007 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1008 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 1009 - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 1010 LO = EXTEND32 (temp); 1011 HI = EXTEND32 (VH4_8 (temp)); 1012 TRACE_ALU_RESULT2 (HI, LO); 1013} 1014 1015:function:::void:do_dsp_msub:int ac, int rs, int rt 1016{ 1017 int64_t temp; 1018 if (ac == 0) 1019 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1020 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1021 Unpredictable (); 1022 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1023 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 1024 - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs]))); 1025 DSPLO(ac) = EXTEND32 (temp); 1026 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 1027 if (ac == 0) 1028 TRACE_ALU_RESULT2 (HI, LO); 1029} 1030 1031:function:::void:do_msubu:int rs, int rt 1032{ 1033 uint64_t temp; 1034 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1035 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1036 Unpredictable (); 1037 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1038 temp = (U8_4 (VL4_8 (HI), VL4_8 (LO)) 1039 - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 1040 LO = EXTEND32 (temp); 1041 HI = EXTEND32 (VH4_8 (temp)); 1042 TRACE_ALU_RESULT2 (HI, LO); 1043} 1044 1045:function:::void:do_dsp_msubu:int ac, int rs, int rt 1046{ 1047 uint64_t temp; 1048 if (ac == 0) 1049 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1050 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1051 Unpredictable (); 1052 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1053 temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac))) 1054 - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt]))); 1055 DSPLO(ac) = EXTEND32 (temp); 1056 DSPHI(ac) = EXTEND32 (VH4_8 (temp)); 1057 if (ac == 0) 1058 TRACE_ALU_RESULT2 (HI, LO); 1059} 1060 1061:function:::void:do_mthi:int rs 1062{ 1063 check_mt_hilo (SD_, HIHISTORY); 1064 HI = GPR[rs]; 1065} 1066 1067:function:::void:do_dsp_mthi:int ac, int rs 1068{ 1069 if (ac == 0) 1070 check_mt_hilo (SD_, HIHISTORY); 1071 DSPHI(ac) = GPR[rs]; 1072} 1073 1074:function:::void:do_mtlo:int rs 1075{ 1076 check_mt_hilo (SD_, LOHISTORY); 1077 LO = GPR[rs]; 1078} 1079 1080:function:::void:do_dsp_mtlo:int ac, int rs 1081{ 1082 if (ac == 0) 1083 check_mt_hilo (SD_, LOHISTORY); 1084 DSPLO(ac) = GPR[rs]; 1085} 1086 1087:function:::void:do_mul:int rd, int rs, int rt 1088{ 1089 int64_t prod; 1090 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1091 Unpredictable (); 1092 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1093 prod = (((int64_t)(int32_t) GPR[rs]) 1094 * ((int64_t)(int32_t) GPR[rt])); 1095 GPR[rd] = EXTEND32 (VL4_8 (prod)); 1096 TRACE_ALU_RESULT (GPR[rd]); 1097} 1098 1099:function:::void:do_dsp_mult:int ac, int rs, int rt 1100{ 1101 int64_t prod; 1102 if (ac == 0) 1103 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1104 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1105 Unpredictable (); 1106 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1107 prod = ((int64_t)(int32_t) GPR[rs]) 1108 * ((int64_t)(int32_t) GPR[rt]); 1109 DSPLO(ac) = EXTEND32 (VL4_8 (prod)); 1110 DSPHI(ac) = EXTEND32 (VH4_8 (prod)); 1111 if (ac == 0) 1112 { 1113 ACX = 0; /* SmartMIPS */ 1114 TRACE_ALU_RESULT2 (HI, LO); 1115 } 1116} 1117 1118:function:::void:do_dsp_multu:int ac, int rs, int rt 1119{ 1120 uint64_t prod; 1121 if (ac == 0) 1122 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 1123 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1124 Unpredictable (); 1125 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1126 prod = ((uint64_t)(uint32_t) GPR[rs]) 1127 * ((uint64_t)(uint32_t) GPR[rt]); 1128 DSPLO(ac) = EXTEND32 (VL4_8 (prod)); 1129 DSPHI(ac) = EXTEND32 (VH4_8 (prod)); 1130 if (ac == 0) 1131 TRACE_ALU_RESULT2 (HI, LO); 1132} 1133 1134:function:::void:do_pref:int hint, int insn_offset, int insn_base 1135{ 1136 /* 1137 address_word base = GPR[insn_base]; 1138 address_word offset = EXTEND16 (insn_offset); 1139 address_word vaddr = loadstore_ea (SD_, base, offset); 1140 address_word paddr = vaddr; 1141 Prefetch (paddr, vaddr, isDATA, hint); 1142 */ 1143} 1144 1145:function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit 1146{ 1147 address_word base = GPR[basereg]; 1148 address_word offset = EXTEND16 (offsetarg); 1149 { 1150 address_word vaddr = loadstore_ea (SD_, base, offset); 1151 address_word paddr = vaddr; 1152 1153 if ((vaddr & 3) != 0) 1154 { 1155 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, 1156 sim_core_unaligned_signal); 1157 } 1158 else 1159 { 1160 uint64_t memval = 0; 1161 uint64_t memval1 = 0; 1162 uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1163 address_word reverseendian = 1164 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 1165 address_word bigendiancpu = 1166 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); 1167 unsigned int byte; 1168 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 1169 byte = ((vaddr & mask) ^ bigendiancpu); 1170 memval = ((uint64_t) GPR[rt] << (8 * byte)); 1171 if (LLBIT) 1172 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, 1173 isREAL); 1174 if (store_ll_bit) 1175 GPR[rt] = LLBIT; 1176 } 1177 } 1178} 1179 1180:function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit 1181{ 1182 address_word base = GPR[rbase]; 1183 address_word offset = EXTEND16 (roffset); 1184 { 1185 address_word vaddr = loadstore_ea (SD_, base, offset); 1186 address_word paddr = vaddr; 1187 1188 if ((vaddr & 7) != 0) 1189 { 1190 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, 1191 sim_core_unaligned_signal); 1192 } 1193 else 1194 { 1195 uint64_t memval = 0; 1196 uint64_t memval1 = 0; 1197 memval = GPR[rt]; 1198 if (LLBIT) 1199 StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr, 1200 isREAL); 1201 if (store_ll_bit) 1202 GPR[rt] = LLBIT; 1203 } 1204 } 1205} 1206 1207:function:::void:do_sub:int rs, int rt, int rd 1208{ 1209 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1210 Unpredictable (); 1211 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1212 { 1213 ALU32_BEGIN (GPR[rs]); 1214 ALU32_SUB (GPR[rt]); 1215 ALU32_END (GPR[rd]); /* This checks for overflow. */ 1216 } 1217 TRACE_ALU_RESULT (GPR[rd]); 1218} 1219 1220:function:::void:do_sw:int rt, int offset, int base 1221{ 1222 do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]); 1223} 1224 1225:function:::void:do_teq:int rs, int rt, address_word instruction_0 1226{ 1227 if ((signed_word) GPR[rs] == (signed_word) GPR[rt]) 1228 SignalException (Trap, instruction_0); 1229} 1230 1231:function:::void:do_teqi:int rs, int immediate, address_word instruction_0 1232{ 1233 if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate)) 1234 SignalException (Trap, instruction_0); 1235} 1236 1237:function:::void:do_tge:int rs, int rt, address_word instruction_0 1238{ 1239 if ((signed_word) GPR[rs] >= (signed_word) GPR[rt]) 1240 SignalException (Trap, instruction_0); 1241} 1242 1243:function:::void:do_tgei:int rs, int immediate, address_word instruction_0 1244{ 1245 if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate)) 1246 SignalException (Trap, instruction_0); 1247} 1248 1249:function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0 1250{ 1251 if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate)) 1252 SignalException (Trap, instruction_0); 1253} 1254 1255:function:::void:do_tgeu:int rs ,int rt, address_word instruction_0 1256{ 1257 if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt]) 1258 SignalException (Trap, instruction_0); 1259} 1260 1261:function:::void:do_tlt:int rs, int rt, address_word instruction_0 1262{ 1263 if ((signed_word) GPR[rs] < (signed_word) GPR[rt]) 1264 SignalException (Trap, instruction_0); 1265} 1266 1267:function:::void:do_tlti:int rs, int immediate, address_word instruction_0 1268{ 1269 if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)) 1270 SignalException (Trap, instruction_0); 1271} 1272 1273:function:::void:do_tltiu:int rs, int immediate, address_word instruction_0 1274{ 1275 if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)) 1276 SignalException (Trap, instruction_0); 1277} 1278 1279:function:::void:do_tltu:int rs, int rt, address_word instruction_0 1280{ 1281 if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]) 1282 SignalException (Trap, instruction_0); 1283} 1284 1285:function:::void:do_tne:int rs, int rt, address_word instruction_0 1286{ 1287 if ((signed_word) GPR[rs] != (signed_word) GPR[rt]) 1288 SignalException (Trap, instruction_0); 1289} 1290 1291:function:::void:do_tnei:int rs, int immediate, address_word instruction_0 1292{ 1293 if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate)) 1294 SignalException (Trap, instruction_0); 1295} 1296 1297:function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0 1298{ 1299 check_fpu (SD_); 1300 check_fmt_p (SD_, fmt, instruction_0); 1301 StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt)); 1302} 1303 1304:function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 1305{ 1306 check_fpu (SD_); 1307 check_fmt_p (SD_, fmt, instruction_0); 1308 StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); 1309} 1310 1311:function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0 1312{ 1313 uint64_t fsx; 1314 uint64_t ftx; 1315 uint64_t fdx; 1316 check_fpu (SD_); 1317 check_u64 (SD_, instruction_0); 1318 fsx = ValueFPR (fs, fmt_ps); 1319 if ((GPR[rs] & 0x3) != 0) 1320 Unpredictable (); 1321 if ((GPR[rs] & 0x4) == 0) 1322 fdx = fsx; 1323 else 1324 { 1325 ftx = ValueFPR (ft, fmt_ps); 1326 if (BigEndianCPU) 1327 fdx = PackPS (PSLower (fsx), PSUpper (ftx)); 1328 else 1329 fdx = PackPS (PSLower (ftx), PSUpper (fsx)); 1330 } 1331 StoreFPR (fd, fmt_ps, fdx); 1332} 1333 1334:function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0 1335{ 1336 check_fpu (SD_); 1337 check_fmt_p (SD_, fmt, instruction_0); 1338 Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc); 1339 TRACE_ALU_RESULT (ValueFCR (31)); 1340} 1341 1342:function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0 1343{ 1344 check_fpu (SD_); 1345 check_fmt_p (SD_, fmt, instruction_0); 1346 StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt, 1347 type)); 1348} 1349 1350:function:::void:do_cfc1:int rt, int fs 1351{ 1352 check_fpu (SD_); 1353 if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31) 1354 { 1355 unsigned_word fcr = ValueFCR (fs); 1356 TRACE_ALU_INPUT1 (fcr); 1357 GPR[rt] = fcr; 1358 } 1359 /* else NOP */ 1360 TRACE_ALU_RESULT (GPR[rt]); 1361} 1362 1363:function:::void:do_ctc1:int rt, int fs 1364{ 1365 check_fpu (SD_); 1366 TRACE_ALU_INPUT1 (GPR[rt]); 1367 if (fs == 25 || fs == 26 || fs == 28 || fs == 31) 1368 StoreFCR (fs, GPR[rt]); 1369 /* else NOP */ 1370} 1371 1372:function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0 1373{ 1374 check_fpu (SD_); 1375 if ((fmt == fmt_double) | 0) 1376 SignalException (ReservedInstruction, instruction_0); 1377 StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt, 1378 fmt_double)); 1379} 1380 1381:function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0 1382{ 1383 check_fpu (SD_); 1384 if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word))) 1385 SignalException (ReservedInstruction, instruction_0); 1386 StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt, 1387 fmt_long)); 1388} 1389 1390:function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0 1391{ 1392 check_fpu (SD_); 1393 check_u64 (SD_, instruction_0); 1394 StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single), 1395 ValueFPR (ft, fmt_single))); 1396} 1397 1398:function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0 1399{ 1400 check_fpu (SD_); 1401 if ((fmt == fmt_single) | 0) 1402 SignalException (ReservedInstruction, instruction_0); 1403 StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt, 1404 fmt_single)); 1405} 1406 1407:function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0 1408{ 1409 check_fpu (SD_); 1410 check_u64 (SD_, instruction_0); 1411 StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps))); 1412} 1413 1414:function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0 1415{ 1416 check_fpu (SD_); 1417 check_u64 (SD_, instruction_0); 1418 StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps))); 1419} 1420 1421:function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0 1422{ 1423 check_fpu (SD_); 1424 if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word))) 1425 SignalException (ReservedInstruction, instruction_0); 1426 StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt, 1427 fmt_word)); 1428} 1429 1430:function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 1431{ 1432 check_fpu (SD_); 1433 StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); 1434} 1435 1436:function:::void:do_dmfc1b:int rt, int fs 1437*mipsIV: 1438*mipsV: 1439*mips64: 1440*mips64r2: 1441*mips64r6: 1442*vr4100: 1443*vr5000: 1444*r3900: 1445*micromips64: 1446{ 1447 if (SizeFGR () == 64) 1448 GPR[rt] = FGR[fs]; 1449 else if ((fs & 0x1) == 0) 1450 GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs]; 1451 else 1452 Unpredictable (); 1453 TRACE_ALU_RESULT (GPR[rt]); 1454} 1455 1456:function:::void:do_dmtc1b:int rt, int fs 1457{ 1458 if (SizeFGR () == 64) 1459 StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); 1460 else if ((fs & 0x1) == 0) 1461 StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]); 1462 else 1463 Unpredictable (); 1464} 1465 1466:function:::void:do_floor_fmt:int type, int fmt, int fd, int fs 1467{ 1468 check_fpu (SD_); 1469 StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt, 1470 type)); 1471} 1472 1473:function:::void:do_luxc1_32:int fd, int rindex, int rbase 1474*mips32r2: 1475*micromips32: 1476{ 1477 address_word base = GPR[rbase]; 1478 address_word index = GPR[rindex]; 1479 address_word vaddr = base + index; 1480 check_fpu (SD_); 1481 if (SizeFGR () != 64) 1482 Unpredictable (); 1483 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 1484 if ((vaddr & 0x7) != 0) 1485 index -= (vaddr & 0x7); 1486 COP_LD (1, fd, do_load_double (SD_, base, index)); 1487} 1488 1489:function:::void:do_luxc1_64:int fd, int rindex, int rbase 1490{ 1491 address_word base = GPR[rbase]; 1492 address_word index = GPR[rindex]; 1493 address_word vaddr = base + index; 1494 if (SizeFGR () != 64) 1495 Unpredictable (); 1496 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 1497 if ((vaddr & 0x7) != 0) 1498 index -= (vaddr & 0x7); 1499 COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index)); 1500 1501} 1502 1503:function:::void:do_lwc1:int ft, int offset, int base 1504{ 1505 check_fpu (SD_); 1506 COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base], 1507 EXTEND16 (offset))); 1508} 1509 1510:function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0 1511{ 1512 check_fpu (SD_); 1513 check_u64 (SD_, instruction_0); 1514 COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index])); 1515} 1516 1517:function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 1518{ 1519 check_fpu (SD_); 1520 check_u64 (SD_, instruction_0); 1521 check_fmt_p (SD_, fmt, instruction_0); 1522 StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), 1523 ValueFPR (fr, fmt), fmt)); 1524} 1525 1526:function:::void:do_mfc1b:int rt, int fs 1527{ 1528 check_fpu (SD_); 1529 GPR[rt] = EXTEND32 (FGR[fs]); 1530 TRACE_ALU_RESULT (GPR[rt]); 1531} 1532 1533:function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0 1534{ 1535 check_fpu (SD_); 1536 check_fmt_p (SD_, fmt, instruction_0); 1537 StoreFPR (fd, fmt, ValueFPR (fs, fmt)); 1538} 1539 1540:function:::void:do_movtf:int tf, int rd, int rs, int cc 1541{ 1542 check_fpu (SD_); 1543 if (GETFCC(cc) == tf) 1544 GPR[rd] = GPR[rs]; 1545} 1546 1547:function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc 1548{ 1549 check_fpu (SD_); 1550 if (fmt != fmt_ps) 1551 { 1552 if (GETFCC(cc) == tf) 1553 StoreFPR (fd, fmt, ValueFPR (fs, fmt)); 1554 else 1555 StoreFPR (fd, fmt, ValueFPR (fd, fmt)); /* set fmt */ 1556 } 1557 else 1558 { 1559 uint64_t fdx; 1560 fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd, 1561 fmt_ps)), 1562 PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd, 1563 fmt_ps))); 1564 StoreFPR (fd, fmt_ps, fdx); 1565 } 1566} 1567 1568:function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt 1569{ 1570 check_fpu (SD_); 1571 if (GPR[rt] != 0) 1572 StoreFPR (fd, fmt, ValueFPR (fs, fmt)); 1573 else 1574 StoreFPR (fd, fmt, ValueFPR (fd, fmt)); 1575} 1576 1577:function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt 1578{ 1579 check_fpu (SD_); 1580 if (GPR[rt] == 0) 1581 StoreFPR (fd, fmt, ValueFPR (fs, fmt)); 1582 else 1583 StoreFPR (fd, fmt, ValueFPR (fd, fmt)); 1584} 1585 1586:function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 1587{ 1588 check_fpu (SD_); 1589 check_u64 (SD_, instruction_0); 1590 check_fmt_p (SD_, fmt, instruction_0); 1591 StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), 1592 ValueFPR (fr, fmt), fmt)); 1593} 1594 1595:function:::void:do_mtc1b:int rt, int fs 1596{ 1597 check_fpu (SD_); 1598 StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt])); 1599} 1600 1601:function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 1602{ 1603 check_fpu (SD_); 1604 check_fmt_p (SD_, fmt, instruction_0); 1605 StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); 1606} 1607 1608:function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0 1609{ 1610 check_fpu (SD_); 1611 check_fmt_p (SD_, fmt, instruction_0); 1612 StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt)); 1613} 1614 1615:function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 1616{ 1617 check_fpu (SD_); 1618 check_u64 (SD_, instruction_0); 1619 check_fmt_p (SD_, fmt, instruction_0); 1620 StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt), 1621 ValueFPR (fr, fmt), fmt)); 1622} 1623 1624:function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0 1625{ 1626 check_fpu (SD_); 1627 check_u64 (SD_, instruction_0); 1628 check_fmt_p (SD_, fmt, instruction_0); 1629 StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), 1630 ValueFPR (fr, fmt), fmt)); 1631} 1632 1633:function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0 1634{ 1635 check_fpu (SD_); 1636 check_u64 (SD_, instruction_0); 1637 StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), 1638 PSLower (ValueFPR (ft, fmt_ps)))); 1639} 1640 1641:function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0 1642{ 1643 check_fpu (SD_); 1644 check_u64 (SD_, instruction_0); 1645 StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)), 1646 PSUpper (ValueFPR (ft, fmt_ps)))); 1647} 1648 1649:function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0 1650{ 1651 check_fpu (SD_); 1652 check_u64 (SD_, instruction_0); 1653 StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), 1654 PSLower (ValueFPR (ft, fmt_ps)))); 1655} 1656 1657:function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0 1658{ 1659 check_fpu (SD_); 1660 check_u64 (SD_, instruction_0); 1661 StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)), 1662 PSUpper (ValueFPR (ft, fmt_ps)))); 1663} 1664 1665:function:::void:do_recip_fmt:int fmt, int fd, int fs 1666{ 1667 check_fpu (SD_); 1668 StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt)); 1669} 1670 1671:function:::void:do_round_fmt:int type, int fmt, int fd, int fs 1672{ 1673 check_fpu (SD_); 1674 StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt, 1675 type)); 1676} 1677 1678:function:::void:do_rsqrt_fmt:int fmt, int fd, int fs 1679{ 1680 check_fpu (SD_); 1681 StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt)); 1682} 1683 1684:function:::void:do_prefx:int hint, int rindex, int rbase 1685{ 1686 /* 1687 address_word base = GPR[rbase]; 1688 address_word index = GPR[rindex]; 1689 address_word vaddr = loadstore_ea (SD_, base, index); 1690 address_word paddr = vaddr; 1691 Prefetch (paddr, vaddr, isDATA, hint); 1692 */ 1693} 1694 1695:function:::void:do_sdc1:int ft, int offset, int base 1696*mipsII: 1697*mips32: 1698*mips32r2: 1699*mips32r6: 1700*micromips32: 1701{ 1702 check_fpu (SD_); 1703 do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft)); 1704} 1705 1706:function:::void:do_suxc1_32:int fs, int rindex, int rbase 1707*mips32r2: 1708*micromips32: 1709{ 1710 address_word base = GPR[rbase]; 1711 address_word index = GPR[rindex]; 1712 address_word vaddr = base + index; 1713 check_fpu (SD_); 1714 if (SizeFGR () != 64) 1715 Unpredictable (); 1716 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 1717 if ((vaddr & 0x7) != 0) 1718 index -= (vaddr & 0x7); 1719 do_store_double (SD_, base, index, COP_SD (1, fs)); 1720} 1721 1722:function:::void:do_suxc1_64:int fs, int rindex, int rbase 1723{ 1724 address_word base = GPR[rbase]; 1725 address_word index = GPR[rindex]; 1726 address_word vaddr = base + index; 1727 if (SizeFGR () != 64) 1728 Unpredictable (); 1729 /* Arrange for the bottom 3 bits of (base + index) to be 0. */ 1730 if ((vaddr & 0x7) != 0) 1731 index -= (vaddr & 0x7); 1732 do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs)); 1733} 1734 1735:function:::void:do_sqrt_fmt:int fmt, int fd, int fs 1736{ 1737 check_fpu (SD_); 1738 StoreFPR (fd, fmt, (SquareRoot (ValueFPR (fs, fmt), fmt))); 1739} 1740 1741:function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0 1742{ 1743 check_fpu (SD_); 1744 check_fmt_p (SD_, fmt, instruction_0); 1745 StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt)); 1746} 1747 1748:function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0 1749{ 1750 address_word base = GPR[rbase]; 1751 address_word offset = EXTEND16 (roffset); 1752 check_fpu (SD_); 1753 { 1754 address_word vaddr = loadstore_ea (SD_, base, offset); 1755 address_word paddr = vaddr; 1756 1757 if ((vaddr & 3) != 0) 1758 { 1759 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, 1760 write_transfer, sim_core_unaligned_signal); 1761 } 1762 else 1763 { 1764 uword64 memval = 0; 1765 uword64 memval1 = 0; 1766 uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1767 address_word reverseendian = 1768 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 1769 address_word bigendiancpu = 1770 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); 1771 unsigned int byte; 1772 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 1773 byte = ((vaddr & mask) ^ bigendiancpu); 1774 memval = (((uword64)COP_SW(1, ft)) << (8 * byte)); 1775 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL); 1776 } 1777 } 1778} 1779 1780:function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0 1781{ 1782 address_word base = GPR[rbase]; 1783 address_word index = GPR[rindex]; 1784 check_fpu (SD_); 1785 check_u64 (SD_, instruction_0); 1786 { 1787 address_word vaddr = loadstore_ea (SD_, base, index); 1788 address_word paddr = vaddr; 1789 1790 if ((vaddr & 3) != 0) 1791 { 1792 SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, 1793 sim_core_unaligned_signal); 1794 } 1795 else 1796 { 1797 uint64_t memval = 0; 1798 uint64_t memval1 = 0; 1799 uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 1800 address_word reverseendian = 1801 (ReverseEndian ? (mask ^ AccessLength_WORD) : 0); 1802 address_word bigendiancpu = 1803 (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0); 1804 unsigned int byte; 1805 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 1806 byte = ((vaddr & mask) ^ bigendiancpu); 1807 memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte)); 1808 StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, 1809 isREAL); 1810 } 1811 } 1812} 1813 1814:function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs 1815{ 1816 check_fpu (SD_); 1817 StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt, 1818 type)); 1819} 1820 1821000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD 1822"add r<RD>, r<RS>, r<RT>" 1823*mipsI: 1824*mipsII: 1825*mipsIII: 1826*mipsIV: 1827*mipsV: 1828*mips32: 1829*mips32r2: 1830*mips32r6: 1831*mips64: 1832*mips64r2: 1833*mips64r6: 1834*vr4100: 1835*vr5000: 1836*r3900: 1837{ 1838 do_add (SD_, RS, RT, RD); 1839} 1840 1841 1842 1843001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI 1844"addi r<RT>, r<RS>, <IMMEDIATE>" 1845*mipsI: 1846*mipsII: 1847*mipsIII: 1848*mipsIV: 1849*mipsV: 1850*mips32: 1851*mips32r2: 1852*mips64: 1853*mips64r2: 1854*vr4100: 1855*vr5000: 1856*r3900: 1857{ 1858 do_addi (SD_, RS, RT, IMMEDIATE); 1859} 1860 1861 1862 1863:function:::void:do_addiu:int rs, int rt, uint16_t immediate 1864{ 1865 if (NotWordValue (GPR[rs])) 1866 Unpredictable (); 1867 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 1868 GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate)); 1869 TRACE_ALU_RESULT (GPR[rt]); 1870} 1871 1872001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU 1873"addiu r<RT>, r<RS>, <IMMEDIATE>" 1874*mipsI: 1875*mipsII: 1876*mipsIII: 1877*mipsIV: 1878*mipsV: 1879*mips32: 1880*mips32r2: 1881*mips32r6: 1882*mips64: 1883*mips64r2: 1884*mips64r6: 1885*vr4100: 1886*vr5000: 1887*r3900: 1888{ 1889 do_addiu (SD_, RS, RT, IMMEDIATE); 1890} 1891 1892 1893 1894:function:::void:do_addu:int rs, int rt, int rd 1895{ 1896 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 1897 Unpredictable (); 1898 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1899 GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]); 1900 TRACE_ALU_RESULT (GPR[rd]); 1901} 1902 1903000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU 1904"addu r<RD>, r<RS>, r<RT>" 1905*mipsI: 1906*mipsII: 1907*mipsIII: 1908*mipsIV: 1909*mipsV: 1910*mips32: 1911*mips32r2: 1912*mips32r6: 1913*mips64: 1914*mips64r2: 1915*mips64r6: 1916*vr4100: 1917*vr5000: 1918*r3900: 1919{ 1920 do_addu (SD_, RS, RT, RD); 1921} 1922 1923 1924 1925:function:::void:do_and:int rs, int rt, int rd 1926{ 1927 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 1928 GPR[rd] = GPR[rs] & GPR[rt]; 1929 TRACE_ALU_RESULT (GPR[rd]); 1930} 1931 1932000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND 1933"and r<RD>, r<RS>, r<RT>" 1934*mipsI: 1935*mipsII: 1936*mipsIII: 1937*mipsIV: 1938*mipsV: 1939*mips32: 1940*mips32r2: 1941*mips32r6: 1942*mips64: 1943*mips64r2: 1944*mips64r6: 1945*vr4100: 1946*vr5000: 1947*r3900: 1948{ 1949 do_and (SD_, RS, RT, RD); 1950} 1951 1952 1953 1954001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI 1955"andi r<RT>, r<RS>, %#lx<IMMEDIATE>" 1956*mipsI: 1957*mipsII: 1958*mipsIII: 1959*mipsIV: 1960*mipsV: 1961*mips32: 1962*mips32r2: 1963*mips32r6: 1964*mips64: 1965*mips64r2: 1966*mips64r6: 1967*vr4100: 1968*vr5000: 1969*r3900: 1970{ 1971 do_andi (SD_,RS, RT, IMMEDIATE); 1972} 1973 1974 1975 1976000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ 1977"beq r<RS>, r<RT>, <OFFSET>" 1978*mipsI: 1979*mipsII: 1980*mipsIII: 1981*mipsIV: 1982*mipsV: 1983*mips32: 1984*mips32r2: 1985*mips64: 1986*mips64r2: 1987*vr4100: 1988*vr5000: 1989*r3900: 1990{ 1991 address_word offset = EXTEND16 (OFFSET) << 2; 1992 if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) 1993 { 1994 DELAY_SLOT (NIA + offset); 1995 } 1996} 1997 1998 1999000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ 2000"beq r<RS>, r<RT>, <OFFSET>" 2001*mips32r6: 2002*mips64r6: 2003{ 2004 address_word offset = EXTEND16 (OFFSET) << 2; 2005 if (GPR[RS] == GPR[RT]) 2006 DELAY_SLOT (NIA + offset); 2007 else 2008 FORBIDDEN_SLOT (); 2009} 2010 2011010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL 2012"beql r<RS>, r<RT>, <OFFSET>" 2013*mipsII: 2014*mipsIII: 2015*mipsIV: 2016*mipsV: 2017*mips32: 2018*mips32r2: 2019*mips64: 2020*mips64r2: 2021*vr4100: 2022*vr5000: 2023*r3900: 2024{ 2025 address_word offset = EXTEND16 (OFFSET) << 2; 2026 if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) 2027 { 2028 DELAY_SLOT (NIA + offset); 2029 } 2030 else 2031 NULLIFY_NEXT_INSTRUCTION (); 2032} 2033 2034 2035 2036000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ 2037"bgez r<RS>, <OFFSET>" 2038*mipsI: 2039*mipsII: 2040*mipsIII: 2041*mipsIV: 2042*mipsV: 2043*mips32: 2044*mips32r2: 2045*mips32r6: 2046*mips64: 2047*mips64r2: 2048*mips64r6: 2049*vr4100: 2050*vr5000: 2051*r3900: 2052{ 2053 address_word offset = EXTEND16 (OFFSET) << 2; 2054 if ((signed_word) GPR[RS] >= 0) 2055 { 2056 DELAY_SLOT (NIA + offset); 2057 } 2058} 2059 2060 2061 2062000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL 2063"bgezal r<RS>, <OFFSET>" 2064*mipsI: 2065*mipsII: 2066*mipsIII: 2067*mipsIV: 2068*mipsV: 2069*mips32: 2070*mips32r2: 2071*mips64: 2072*mips64r2: 2073*vr4100: 2074*vr5000: 2075*r3900: 2076{ 2077 address_word offset = EXTEND16 (OFFSET) << 2; 2078 if (RS == 31) 2079 Unpredictable (); 2080 RA = (CIA + 8); 2081 if ((signed_word) GPR[RS] >= 0) 2082 { 2083 DELAY_SLOT (NIA + offset); 2084 } 2085} 2086 2087000001,00000,10001,16.OFFSET:REGIMM:32::BAL 2088"bal <OFFSET>" 2089*mips32r6: 2090*mips64r6: 2091{ 2092 address_word offset = EXTEND16 (OFFSET) << 2; 2093 RA = (CIA + 8); 2094 DELAY_SLOT (NIA + offset); 2095} 2096 2097000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL 2098"bgezall r<RS>, <OFFSET>" 2099*mipsII: 2100*mipsIII: 2101*mipsIV: 2102*mipsV: 2103*mips32: 2104*mips32r2: 2105*mips64: 2106*mips64r2: 2107*vr4100: 2108*vr5000: 2109*r3900: 2110{ 2111 address_word offset = EXTEND16 (OFFSET) << 2; 2112 if (RS == 31) 2113 Unpredictable (); 2114 RA = (CIA + 8); 2115 /* NOTE: The branch occurs AFTER the next instruction has been 2116 executed */ 2117 if ((signed_word) GPR[RS] >= 0) 2118 { 2119 DELAY_SLOT (NIA + offset); 2120 } 2121 else 2122 NULLIFY_NEXT_INSTRUCTION (); 2123} 2124 2125 2126 2127000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL 2128"bgezl r<RS>, <OFFSET>" 2129*mipsII: 2130*mipsIII: 2131*mipsIV: 2132*mipsV: 2133*mips32: 2134*mips32r2: 2135*mips64: 2136*mips64r2: 2137*vr4100: 2138*vr5000: 2139*r3900: 2140{ 2141 address_word offset = EXTEND16 (OFFSET) << 2; 2142 if ((signed_word) GPR[RS] >= 0) 2143 { 2144 DELAY_SLOT (NIA + offset); 2145 } 2146 else 2147 NULLIFY_NEXT_INSTRUCTION (); 2148} 2149 2150 2151 2152000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ 2153"bgtz r<RS>, <OFFSET>" 2154*mipsI: 2155*mipsII: 2156*mipsIII: 2157*mipsIV: 2158*mipsV: 2159*mips32: 2160*mips32r2: 2161*mips32r6: 2162*mips64: 2163*mips64r2: 2164*mips64r6: 2165*vr4100: 2166*vr5000: 2167*r3900: 2168{ 2169 address_word offset = EXTEND16 (OFFSET) << 2; 2170 if ((signed_word) GPR[RS] > 0) 2171 { 2172 DELAY_SLOT (NIA + offset); 2173 } 2174} 2175 2176 2177 2178010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL 2179"bgtzl r<RS>, <OFFSET>" 2180*mipsII: 2181*mipsIII: 2182*mipsIV: 2183*mipsV: 2184*mips32: 2185*mips32r2: 2186*mips64: 2187*mips64r2: 2188*vr4100: 2189*vr5000: 2190*r3900: 2191{ 2192 address_word offset = EXTEND16 (OFFSET) << 2; 2193 /* NOTE: The branch occurs AFTER the next instruction has been 2194 executed */ 2195 if ((signed_word) GPR[RS] > 0) 2196 { 2197 DELAY_SLOT (NIA + offset); 2198 } 2199 else 2200 NULLIFY_NEXT_INSTRUCTION (); 2201} 2202 2203 2204 2205000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ 2206"blez r<RS>, <OFFSET>" 2207*mipsI: 2208*mipsII: 2209*mipsIII: 2210*mipsIV: 2211*mipsV: 2212*mips32: 2213*mips32r2: 2214*mips32r6: 2215*mips64: 2216*mips64r2: 2217*mips64r6: 2218*vr4100: 2219*vr5000: 2220*r3900: 2221{ 2222 address_word offset = EXTEND16 (OFFSET) << 2; 2223 /* NOTE: The branch occurs AFTER the next instruction has been 2224 executed */ 2225 if ((signed_word) GPR[RS] <= 0) 2226 { 2227 DELAY_SLOT (NIA + offset); 2228 } 2229} 2230 2231 2232 2233010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL 2234"bgezl r<RS>, <OFFSET>" 2235*mipsII: 2236*mipsIII: 2237*mipsIV: 2238*mipsV: 2239*mips32: 2240*mips32r2: 2241*mips64: 2242*mips64r2: 2243*vr4100: 2244*vr5000: 2245*r3900: 2246{ 2247 address_word offset = EXTEND16 (OFFSET) << 2; 2248 if ((signed_word) GPR[RS] <= 0) 2249 { 2250 DELAY_SLOT (NIA + offset); 2251 } 2252 else 2253 NULLIFY_NEXT_INSTRUCTION (); 2254} 2255 2256 2257 2258000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ 2259"bltz r<RS>, <OFFSET>" 2260*mipsI: 2261*mipsII: 2262*mipsIII: 2263*mipsIV: 2264*mipsV: 2265*mips32: 2266*mips32r2: 2267*mips32r6: 2268*mips64: 2269*mips64r2: 2270*mips64r6: 2271*vr4100: 2272*vr5000: 2273*r3900: 2274{ 2275 address_word offset = EXTEND16 (OFFSET) << 2; 2276 if ((signed_word) GPR[RS] < 0) 2277 { 2278 DELAY_SLOT (NIA + offset); 2279 } 2280} 2281 2282 2283 2284000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL 2285"bltzal r<RS>, <OFFSET>" 2286*mipsI: 2287*mipsII: 2288*mipsIII: 2289*mipsIV: 2290*mipsV: 2291*mips32: 2292*mips32r2: 2293*mips64: 2294*mips64r2: 2295*vr4100: 2296*vr5000: 2297*r3900: 2298{ 2299 address_word offset = EXTEND16 (OFFSET) << 2; 2300 if (RS == 31) 2301 Unpredictable (); 2302 RA = (CIA + 8); 2303 /* NOTE: The branch occurs AFTER the next instruction has been 2304 executed */ 2305 if ((signed_word) GPR[RS] < 0) 2306 { 2307 DELAY_SLOT (NIA + offset); 2308 } 2309} 2310 2311 2312 2313000001,00000,10000,16.OFFSET:REGIMM:32::NAL 2314"nal <OFFSET>" 2315*mips32r6: 2316*mips64r6: 2317{ 2318 address_word offset = EXTEND16 (OFFSET) << 2; 2319 RA = (CIA + 8); 2320 FORBIDDEN_SLOT (); 2321} 2322 2323 2324 2325000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL 2326"bltzall r<RS>, <OFFSET>" 2327*mipsII: 2328*mipsIII: 2329*mipsIV: 2330*mipsV: 2331*mips32: 2332*mips32r2: 2333*mips64: 2334*mips64r2: 2335*vr4100: 2336*vr5000: 2337*r3900: 2338{ 2339 address_word offset = EXTEND16 (OFFSET) << 2; 2340 if (RS == 31) 2341 Unpredictable (); 2342 RA = (CIA + 8); 2343 if ((signed_word) GPR[RS] < 0) 2344 { 2345 DELAY_SLOT (NIA + offset); 2346 } 2347 else 2348 NULLIFY_NEXT_INSTRUCTION (); 2349} 2350 2351 2352 2353000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL 2354"bltzl r<RS>, <OFFSET>" 2355*mipsII: 2356*mipsIII: 2357*mipsIV: 2358*mipsV: 2359*mips32: 2360*mips32r2: 2361*mips64: 2362*mips64r2: 2363*vr4100: 2364*vr5000: 2365*r3900: 2366{ 2367 address_word offset = EXTEND16 (OFFSET) << 2; 2368 /* NOTE: The branch occurs AFTER the next instruction has been 2369 executed */ 2370 if ((signed_word) GPR[RS] < 0) 2371 { 2372 DELAY_SLOT (NIA + offset); 2373 } 2374 else 2375 NULLIFY_NEXT_INSTRUCTION (); 2376} 2377 2378 2379 2380000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE 2381"bne r<RS>, r<RT>, <OFFSET>" 2382*mipsI: 2383*mipsII: 2384*mipsIII: 2385*mipsIV: 2386*mipsV: 2387*mips32: 2388*mips32r2: 2389*mips32r6: 2390*mips64: 2391*mips64r2: 2392*mips64r6: 2393*vr4100: 2394*vr5000: 2395*r3900: 2396{ 2397 address_word offset = EXTEND16 (OFFSET) << 2; 2398 if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) 2399 { 2400 DELAY_SLOT (NIA + offset); 2401 } 2402} 2403 2404 2405 2406010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL 2407"bnel r<RS>, r<RT>, <OFFSET>" 2408*mipsII: 2409*mipsIII: 2410*mipsIV: 2411*mipsV: 2412*mips32: 2413*mips32r2: 2414*mips64: 2415*mips64r2: 2416*vr4100: 2417*vr5000: 2418*r3900: 2419{ 2420 address_word offset = EXTEND16 (OFFSET) << 2; 2421 if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) 2422 { 2423 DELAY_SLOT (NIA + offset); 2424 } 2425 else 2426 NULLIFY_NEXT_INSTRUCTION (); 2427} 2428 2429 2430 2431000000,20.CODE,001101:SPECIAL:32::BREAK 2432"break %#lx<CODE>" 2433*mipsI: 2434*mipsII: 2435*mipsIII: 2436*mipsIV: 2437*mipsV: 2438*mips32: 2439*mips32r2: 2440*mips32r6: 2441*mips64: 2442*mips64r2: 2443*mips64r6: 2444*vr4100: 2445*vr5000: 2446*r3900: 2447{ 2448 do_break (SD_, instruction_0); 2449} 2450 2451 2452 2453011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO 2454"clo r<RD>, r<RS>" 2455*mips32: 2456*mips32r2: 2457*mips64: 2458*mips64r2: 2459*vr5500: 2460{ 2461 if (RT != RD) 2462 Unpredictable (); 2463 do_clo (SD_, RD, RS); 2464} 2465 2466 2467 2468011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ 2469"clz r<RD>, r<RS>" 2470*mips32: 2471*mips32r2: 2472*mips64: 2473*mips64r2: 2474*vr5500: 2475{ 2476 if (RT != RD) 2477 Unpredictable (); 2478 do_clz (SD_, RD, RS); 2479} 2480 2481 2482 2483000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD 2484"dadd r<RD>, r<RS>, r<RT>" 2485*mipsIII: 2486*mipsIV: 2487*mipsV: 2488*mips64: 2489*mips64r2: 2490*mips64r6: 2491*vr4100: 2492*vr5000: 2493{ 2494 check_u64 (SD_, instruction_0); 2495 do_dadd (SD_, RD, RS, RT); 2496} 2497 2498 2499 2500011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI 2501"daddi r<RT>, r<RS>, <IMMEDIATE>" 2502*mipsIII: 2503*mipsIV: 2504*mipsV: 2505*mips64: 2506*mips64r2: 2507*vr4100: 2508*vr5000: 2509{ 2510 check_u64 (SD_, instruction_0); 2511 do_daddi (SD_, RT, RS, IMMEDIATE); 2512} 2513 2514 2515 2516:function:::void:do_daddiu:int rs, int rt, uint16_t immediate 2517{ 2518 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 2519 GPR[rt] = GPR[rs] + EXTEND16 (immediate); 2520 TRACE_ALU_RESULT (GPR[rt]); 2521} 2522 2523011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU 2524"daddiu r<RT>, r<RS>, <IMMEDIATE>" 2525*mipsIII: 2526*mipsIV: 2527*mipsV: 2528*mips64: 2529*mips64r2: 2530*mips64r6: 2531*vr4100: 2532*vr5000: 2533{ 2534 check_u64 (SD_, instruction_0); 2535 do_daddiu (SD_, RS, RT, IMMEDIATE); 2536} 2537 2538 2539 2540:function:::void:do_daddu:int rs, int rt, int rd 2541{ 2542 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2543 GPR[rd] = GPR[rs] + GPR[rt]; 2544 TRACE_ALU_RESULT (GPR[rd]); 2545} 2546 2547000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU 2548"daddu r<RD>, r<RS>, r<RT>" 2549*mipsIII: 2550*mipsIV: 2551*mipsV: 2552*mips64: 2553*mips64r2: 2554*mips64r6: 2555*vr4100: 2556*vr5000: 2557{ 2558 check_u64 (SD_, instruction_0); 2559 do_daddu (SD_, RS, RT, RD); 2560} 2561 2562 2563 2564011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO 2565"dclo r<RD>, r<RS>" 2566*mips64: 2567*mips64r2: 2568*vr5500: 2569{ 2570 if (RT != RD) 2571 Unpredictable (); 2572 check_u64 (SD_, instruction_0); 2573 if (RT != RD) 2574 Unpredictable (); 2575 do_dclo (SD_, RD, RS); 2576} 2577 2578 2579 2580011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ 2581"dclz r<RD>, r<RS>" 2582*mips64: 2583*mips64r2: 2584*vr5500: 2585{ 2586 if (RT != RD) 2587 Unpredictable (); 2588 check_u64 (SD_, instruction_0); 2589 if (RT != RD) 2590 Unpredictable (); 2591 do_dclz (SD_, RD, RS); 2592} 2593 2594 2595 2596:function:::void:do_ddiv:int rs, int rt 2597{ 2598 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2599 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2600 { 2601 int64_t n = GPR[rs]; 2602 int64_t d = GPR[rt]; 2603 int64_t hi; 2604 int64_t lo; 2605 if (d == 0) 2606 { 2607 lo = SIGNED64 (0x8000000000000000); 2608 hi = 0; 2609 } 2610 else if (d == -1 && n == SIGNED64 (0x8000000000000000)) 2611 { 2612 lo = SIGNED64 (0x8000000000000000); 2613 hi = 0; 2614 } 2615 else 2616 { 2617 lo = (n / d); 2618 hi = (n % d); 2619 } 2620 HI = hi; 2621 LO = lo; 2622 } 2623 TRACE_ALU_RESULT2 (HI, LO); 2624} 2625 2626000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV 2627"ddiv r<RS>, r<RT>" 2628*mipsIII: 2629*mipsIV: 2630*mipsV: 2631*mips64: 2632*mips64r2: 2633*vr4100: 2634*vr5000: 2635{ 2636 check_u64 (SD_, instruction_0); 2637 do_ddiv (SD_, RS, RT); 2638} 2639 2640 2641 2642:function:::void:do_ddivu:int rs, int rt 2643{ 2644 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2645 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2646 { 2647 uint64_t n = GPR[rs]; 2648 uint64_t d = GPR[rt]; 2649 uint64_t hi; 2650 uint64_t lo; 2651 if (d == 0) 2652 { 2653 lo = SIGNED64 (0x8000000000000000); 2654 hi = 0; 2655 } 2656 else 2657 { 2658 lo = (n / d); 2659 hi = (n % d); 2660 } 2661 HI = hi; 2662 LO = lo; 2663 } 2664 TRACE_ALU_RESULT2 (HI, LO); 2665} 2666 2667000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU 2668"ddivu r<RS>, r<RT>" 2669*mipsIII: 2670*mipsIV: 2671*mipsV: 2672*mips64: 2673*mips64r2: 2674*vr4100: 2675*vr5000: 2676{ 2677 check_u64 (SD_, instruction_0); 2678 do_ddivu (SD_, RS, RT); 2679} 2680 2681:function:::void:do_div:int rs, int rt 2682{ 2683 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2684 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2685 { 2686 int32_t n = GPR[rs]; 2687 int32_t d = GPR[rt]; 2688 if (d == 0) 2689 { 2690 LO = EXTEND32 (0x80000000); 2691 HI = EXTEND32 (0); 2692 } 2693 else if (n == SIGNED32 (0x80000000) && d == -1) 2694 { 2695 LO = EXTEND32 (0x80000000); 2696 HI = EXTEND32 (0); 2697 } 2698 else 2699 { 2700 LO = EXTEND32 (n / d); 2701 HI = EXTEND32 (n % d); 2702 } 2703 } 2704 TRACE_ALU_RESULT2 (HI, LO); 2705} 2706 2707000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV 2708"div r<RS>, r<RT>" 2709*mipsI: 2710*mipsII: 2711*mipsIII: 2712*mipsIV: 2713*mipsV: 2714*mips32: 2715*mips32r2: 2716*mips64: 2717*mips64r2: 2718*vr4100: 2719*vr5000: 2720*r3900: 2721{ 2722 do_div (SD_, RS, RT); 2723} 2724 2725 2726 2727:function:::void:do_divu:int rs, int rt 2728{ 2729 check_div_hilo (SD_, HIHISTORY, LOHISTORY); 2730 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2731 { 2732 uint32_t n = GPR[rs]; 2733 uint32_t d = GPR[rt]; 2734 if (d == 0) 2735 { 2736 LO = EXTEND32 (0x80000000); 2737 HI = EXTEND32 (0); 2738 } 2739 else 2740 { 2741 LO = EXTEND32 (n / d); 2742 HI = EXTEND32 (n % d); 2743 } 2744 } 2745 TRACE_ALU_RESULT2 (HI, LO); 2746} 2747 2748000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU 2749"divu r<RS>, r<RT>" 2750*mipsI: 2751*mipsII: 2752*mipsIII: 2753*mipsIV: 2754*mipsV: 2755*mips32: 2756*mips32r2: 2757*mips64: 2758*mips64r2: 2759*vr4100: 2760*vr5000: 2761*r3900: 2762{ 2763 do_divu (SD_, RS, RT); 2764} 2765 2766 2767:function:::void:do_dmultx:int rs, int rt, int rd, int signed_p 2768{ 2769 uint64_t lo; 2770 uint64_t hi; 2771 uint64_t m00; 2772 uint64_t m01; 2773 uint64_t m10; 2774 uint64_t m11; 2775 uint64_t mid; 2776 int sign; 2777 uint64_t op1 = GPR[rs]; 2778 uint64_t op2 = GPR[rt]; 2779 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 2780 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 2781 /* make signed multiply unsigned */ 2782 sign = 0; 2783 if (signed_p) 2784 { 2785 if ((int64_t) op1 < 0) 2786 { 2787 op1 = - op1; 2788 ++sign; 2789 } 2790 if ((int64_t) op2 < 0) 2791 { 2792 op2 = - op2; 2793 ++sign; 2794 } 2795 } 2796 /* multiply out the 4 sub products */ 2797 m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2)); 2798 m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2)); 2799 m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2)); 2800 m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2)); 2801 /* add the products */ 2802 mid = ((uint64_t) VH4_8 (m00) 2803 + (uint64_t) VL4_8 (m10) 2804 + (uint64_t) VL4_8 (m01)); 2805 lo = U8_4 (mid, m00); 2806 hi = (m11 2807 + (uint64_t) VH4_8 (mid) 2808 + (uint64_t) VH4_8 (m01) 2809 + (uint64_t) VH4_8 (m10)); 2810 /* fix the sign */ 2811 if (sign & 1) 2812 { 2813 lo = -lo; 2814 if (lo == 0) 2815 hi = -hi; 2816 else 2817 hi = -hi - 1; 2818 } 2819 /* save the result HI/LO (and a gpr) */ 2820 LO = lo; 2821 HI = hi; 2822 if (rd != 0) 2823 GPR[rd] = lo; 2824 TRACE_ALU_RESULT2 (HI, LO); 2825} 2826 2827:function:::void:do_dmult:int rs, int rt, int rd 2828{ 2829 do_dmultx (SD_, rs, rt, rd, 1); 2830} 2831 2832000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT 2833"dmult r<RS>, r<RT>" 2834*mipsIII: 2835*mipsIV: 2836*mipsV: 2837*mips64: 2838*mips64r2: 2839*vr4100: 2840{ 2841 check_u64 (SD_, instruction_0); 2842 do_dmult (SD_, RS, RT, 0); 2843} 2844 2845000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT 2846"dmult r<RS>, r<RT>":RD == 0 2847"dmult r<RD>, r<RS>, r<RT>" 2848*vr5000: 2849{ 2850 check_u64 (SD_, instruction_0); 2851 do_dmult (SD_, RS, RT, RD); 2852} 2853 2854 2855 2856:function:::void:do_dmultu:int rs, int rt, int rd 2857{ 2858 do_dmultx (SD_, rs, rt, rd, 0); 2859} 2860 2861000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU 2862"dmultu r<RS>, r<RT>" 2863*mipsIII: 2864*mipsIV: 2865*mipsV: 2866*mips64: 2867*mips64r2: 2868*vr4100: 2869{ 2870 check_u64 (SD_, instruction_0); 2871 do_dmultu (SD_, RS, RT, 0); 2872} 2873 2874000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU 2875"dmultu r<RD>, r<RS>, r<RT>":RD == 0 2876"dmultu r<RS>, r<RT>" 2877*vr5000: 2878{ 2879 check_u64 (SD_, instruction_0); 2880 do_dmultu (SD_, RS, RT, RD); 2881} 2882 2883 2884:function:::uint64_t:do_dror:uint64_t x,uint64_t y 2885{ 2886 uint64_t result; 2887 2888 y &= 63; 2889 TRACE_ALU_INPUT2 (x, y); 2890 result = ROTR64 (x, y); 2891 TRACE_ALU_RESULT (result); 2892 return result; 2893} 2894 2895000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR 2896"dror r<RD>, r<RT>, <SHIFT>" 2897*mips64r2: 2898*mips64r6: 2899*vr5400: 2900*vr5500: 2901{ 2902 check_u64 (SD_, instruction_0); 2903 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT); 2904} 2905 2906000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32 2907"dror32 r<RD>, r<RT>, <SHIFT>" 2908*mips64r2: 2909*mips64r6: 2910*vr5400: 2911*vr5500: 2912{ 2913 check_u64 (SD_, instruction_0); 2914 GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32); 2915} 2916 2917000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV 2918"drorv r<RD>, r<RT>, r<RS>" 2919*mips64r2: 2920*mips64r6: 2921*vr5400: 2922*vr5500: 2923{ 2924 check_u64 (SD_, instruction_0); 2925 GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]); 2926} 2927 2928 2929:function:::void:do_dsll:int rt, int rd, int shift 2930{ 2931 TRACE_ALU_INPUT2 (GPR[rt], shift); 2932 GPR[rd] = GPR[rt] << shift; 2933 TRACE_ALU_RESULT (GPR[rd]); 2934} 2935 2936000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL 2937"dsll r<RD>, r<RT>, <SHIFT>" 2938*mipsIII: 2939*mipsIV: 2940*mipsV: 2941*mips64: 2942*mips64r2: 2943*mips64r6: 2944*vr4100: 2945*vr5000: 2946{ 2947 check_u64 (SD_, instruction_0); 2948 do_dsll (SD_, RT, RD, SHIFT); 2949} 2950 2951 2952000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32 2953"dsll32 r<RD>, r<RT>, <SHIFT>" 2954*mipsIII: 2955*mipsIV: 2956*mipsV: 2957*mips64: 2958*mips64r2: 2959*mips64r6: 2960*vr4100: 2961*vr5000: 2962{ 2963 check_u64 (SD_, instruction_0); 2964 do_dsll32 (SD_, RD, RT, SHIFT); 2965} 2966 2967:function:::void:do_dsllv:int rs, int rt, int rd 2968{ 2969 int s = MASKED64 (GPR[rs], 5, 0); 2970 TRACE_ALU_INPUT2 (GPR[rt], s); 2971 GPR[rd] = GPR[rt] << s; 2972 TRACE_ALU_RESULT (GPR[rd]); 2973} 2974 2975000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV 2976"dsllv r<RD>, r<RT>, r<RS>" 2977*mipsIII: 2978*mipsIV: 2979*mipsV: 2980*mips64: 2981*mips64r2: 2982*mips64r6: 2983*vr4100: 2984*vr5000: 2985{ 2986 check_u64 (SD_, instruction_0); 2987 do_dsllv (SD_, RS, RT, RD); 2988} 2989 2990:function:::void:do_dsra:int rt, int rd, int shift 2991{ 2992 TRACE_ALU_INPUT2 (GPR[rt], shift); 2993 GPR[rd] = ((int64_t) GPR[rt]) >> shift; 2994 TRACE_ALU_RESULT (GPR[rd]); 2995} 2996 2997 2998000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA 2999"dsra r<RD>, r<RT>, <SHIFT>" 3000*mipsIII: 3001*mipsIV: 3002*mipsV: 3003*mips64: 3004*mips64r2: 3005*mips64r6: 3006*vr4100: 3007*vr5000: 3008{ 3009 check_u64 (SD_, instruction_0); 3010 do_dsra (SD_, RT, RD, SHIFT); 3011} 3012 3013 3014000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32 3015"dsra32 r<RD>, r<RT>, <SHIFT>" 3016*mipsIII: 3017*mipsIV: 3018*mipsV: 3019*mips64: 3020*mips64r2: 3021*mips64r6: 3022*vr4100: 3023*vr5000: 3024{ 3025 check_u64 (SD_, instruction_0); 3026 do_dsra32 (SD_, RD, RT, SHIFT); 3027} 3028 3029 3030:function:::void:do_dsrav:int rs, int rt, int rd 3031{ 3032 int s = MASKED64 (GPR[rs], 5, 0); 3033 TRACE_ALU_INPUT2 (GPR[rt], s); 3034 GPR[rd] = ((int64_t) GPR[rt]) >> s; 3035 TRACE_ALU_RESULT (GPR[rd]); 3036} 3037 3038000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV 3039"dsrav r<RD>, r<RT>, r<RS>" 3040*mipsIII: 3041*mipsIV: 3042*mipsV: 3043*mips64: 3044*mips64r2: 3045*mips64r6: 3046*vr4100: 3047*vr5000: 3048{ 3049 check_u64 (SD_, instruction_0); 3050 do_dsrav (SD_, RS, RT, RD); 3051} 3052 3053:function:::void:do_dsrl:int rt, int rd, int shift 3054{ 3055 TRACE_ALU_INPUT2 (GPR[rt], shift); 3056 GPR[rd] = (uint64_t) GPR[rt] >> shift; 3057 TRACE_ALU_RESULT (GPR[rd]); 3058} 3059 3060 3061000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL 3062"dsrl r<RD>, r<RT>, <SHIFT>" 3063*mipsIII: 3064*mipsIV: 3065*mipsV: 3066*mips64: 3067*mips64r2: 3068*mips64r6: 3069*vr4100: 3070*vr5000: 3071{ 3072 check_u64 (SD_, instruction_0); 3073 do_dsrl (SD_, RT, RD, SHIFT); 3074} 3075 3076 3077000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32 3078"dsrl32 r<RD>, r<RT>, <SHIFT>" 3079*mipsIII: 3080*mipsIV: 3081*mipsV: 3082*mips64: 3083*mips64r2: 3084*mips64r6: 3085*vr4100: 3086*vr5000: 3087{ 3088 check_u64 (SD_, instruction_0); 3089 do_dsrl32 (SD_, RD, RT, SHIFT); 3090} 3091 3092 3093:function:::void:do_dsrlv:int rs, int rt, int rd 3094{ 3095 int s = MASKED64 (GPR[rs], 5, 0); 3096 TRACE_ALU_INPUT2 (GPR[rt], s); 3097 GPR[rd] = (uint64_t) GPR[rt] >> s; 3098 TRACE_ALU_RESULT (GPR[rd]); 3099} 3100 3101 3102 3103000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV 3104"dsrlv r<RD>, r<RT>, r<RS>" 3105*mipsIII: 3106*mipsIV: 3107*mipsV: 3108*mips64: 3109*mips64r2: 3110*mips64r6: 3111*vr4100: 3112*vr5000: 3113{ 3114 check_u64 (SD_, instruction_0); 3115 do_dsrlv (SD_, RS, RT, RD); 3116} 3117 3118 3119000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB 3120"dsub r<RD>, r<RS>, r<RT>" 3121*mipsIII: 3122*mipsIV: 3123*mipsV: 3124*mips64: 3125*mips64r2: 3126*mips64r6: 3127*vr4100: 3128*vr5000: 3129{ 3130 check_u64 (SD_, instruction_0); 3131 do_dsub (SD_, RD, RS, RT); 3132} 3133 3134 3135:function:::void:do_dsubu:int rs, int rt, int rd 3136{ 3137 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3138 GPR[rd] = GPR[rs] - GPR[rt]; 3139 TRACE_ALU_RESULT (GPR[rd]); 3140} 3141 3142000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU 3143"dsubu r<RD>, r<RS>, r<RT>" 3144*mipsIII: 3145*mipsIV: 3146*mipsV: 3147*mips64: 3148*mips64r2: 3149*mips64r6: 3150*vr4100: 3151*vr5000: 3152{ 3153 check_u64 (SD_, instruction_0); 3154 do_dsubu (SD_, RS, RT, RD); 3155} 3156 3157 3158000010,26.INSTR_INDEX:NORMAL:32::J 3159"j <INSTR_INDEX>" 3160*mipsI: 3161*mipsII: 3162*mipsIII: 3163*mipsIV: 3164*mipsV: 3165*mips32: 3166*mips32r2: 3167*mips32r6: 3168*mips64: 3169*mips64r2: 3170*mips64r6: 3171*vr4100: 3172*vr5000: 3173*r3900: 3174{ 3175 /* NOTE: The region used is that of the delay slot NIA and NOT the 3176 current instruction */ 3177 address_word region = (NIA & MASK (63, 28)); 3178 DELAY_SLOT (region | (INSTR_INDEX << 2)); 3179} 3180 3181 3182000011,26.INSTR_INDEX:NORMAL:32::JAL 3183"jal <INSTR_INDEX>" 3184*mipsI: 3185*mipsII: 3186*mipsIII: 3187*mipsIV: 3188*mipsV: 3189*mips32: 3190*mips32r2: 3191*mips32r6: 3192*mips64: 3193*mips64r2: 3194*mips64r6: 3195*vr4100: 3196*vr5000: 3197*r3900: 3198{ 3199 /* NOTE: The region used is that of the delay slot and NOT the 3200 current instruction */ 3201 address_word region = (NIA & MASK (63, 28)); 3202 GPR[31] = CIA + 8; 3203 DELAY_SLOT (region | (INSTR_INDEX << 2)); 3204} 3205 3206000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR 3207"jalr r<RS>":RD == 31 3208"jalr r<RD>, r<RS>" 3209*mipsI: 3210*mipsII: 3211*mipsIII: 3212*mipsIV: 3213*mipsV: 3214*mips32: 3215*mips32r2: 3216*mips32r6: 3217*mips64: 3218*mips64r2: 3219*mips64r6: 3220*vr4100: 3221*vr5000: 3222*r3900: 3223{ 3224 address_word temp = GPR[RS]; 3225 GPR[RD] = CIA + 8; 3226 DELAY_SLOT (temp); 3227} 3228 3229000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB 3230"jalr.hb r<RS>":RD == 31 3231"jalr.hb r<RD>, r<RS>" 3232*mips32r2: 3233*mips32r6: 3234*mips64r2: 3235*mips64r6: 3236{ 3237 address_word temp = GPR[RS]; 3238 GPR[RD] = CIA + 8; 3239 DELAY_SLOT (temp); 3240} 3241 3242000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR 3243"jr r<RS>" 3244*mipsI: 3245*mipsII: 3246*mipsIII: 3247*mipsIV: 3248*mipsV: 3249*mips32: 3250*mips32r2: 3251*mips32r6: 3252*mips64: 3253*mips64r2: 3254*mips64r6: 3255*vr4100: 3256*vr5000: 3257*r3900: 3258{ 3259 DELAY_SLOT (GPR[RS]); 3260} 3261 3262000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB 3263"jr.hb r<RS>" 3264*mips32r2: 3265*mips32r6: 3266*mips64r2: 3267*mips64r6: 3268{ 3269 DELAY_SLOT (GPR[RS]); 3270} 3271 3272:function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset 3273{ 3274 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3275 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); 3276 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 3277 unsigned int byte; 3278 address_word paddr; 3279 uint64_t memval; 3280 address_word vaddr; 3281 3282 paddr = vaddr = loadstore_ea (SD_, base, offset); 3283 if ((vaddr & access) != 0) 3284 { 3285 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal); 3286 } 3287 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 3288 LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL); 3289 byte = ((vaddr & mask) ^ bigendiancpu); 3290 return (memval >> (8 * byte)); 3291} 3292 3293:function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt 3294{ 3295 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3296 address_word reverseendian = (ReverseEndian ? -1 : 0); 3297 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 3298 unsigned int byte; 3299 unsigned int word; 3300 address_word paddr; 3301 uint64_t memval; 3302 address_word vaddr; 3303 int nr_lhs_bits; 3304 int nr_rhs_bits; 3305 unsigned_word lhs_mask; 3306 unsigned_word temp; 3307 3308 paddr = vaddr = loadstore_ea (SD_, base, offset); 3309 paddr = (paddr ^ (reverseendian & mask)); 3310 if (BigEndianMem == 0) 3311 paddr = paddr & ~access; 3312 3313 /* compute where within the word/mem we are */ 3314 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ 3315 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ 3316 nr_lhs_bits = 8 * byte + 8; 3317 nr_rhs_bits = 8 * access - 8 * byte; 3318 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 3319 3320 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 3321 (long) ((uint64_t) vaddr >> 32), (long) vaddr, 3322 (long) ((uint64_t) paddr >> 32), (long) paddr, 3323 word, byte, nr_lhs_bits, nr_rhs_bits); */ 3324 3325 LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL); 3326 if (word == 0) 3327 { 3328 /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */ 3329 temp = (memval << nr_rhs_bits); 3330 } 3331 else 3332 { 3333 /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */ 3334 temp = (memval >> nr_lhs_bits); 3335 } 3336 lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits); 3337 rt = (rt & ~lhs_mask) | (temp & lhs_mask); 3338 3339 /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n", 3340 (long) ((uint64_t) memval >> 32), (long) memval, 3341 (long) ((uint64_t) temp >> 32), (long) temp, 3342 (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask, 3343 (long) (rt >> 32), (long) rt); */ 3344 return rt; 3345} 3346 3347:function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt 3348{ 3349 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 3350 address_word reverseendian = (ReverseEndian ? -1 : 0); 3351 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 3352 unsigned int byte; 3353 address_word paddr; 3354 uint64_t memval; 3355 address_word vaddr; 3356 3357 paddr = vaddr = loadstore_ea (SD_, base, offset); 3358 /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */ 3359 paddr = (paddr ^ (reverseendian & mask)); 3360 if (BigEndianMem != 0) 3361 paddr = paddr & ~access; 3362 byte = ((vaddr & mask) ^ (bigendiancpu & mask)); 3363 /* NOTE: SPEC is wrong, had `byte' not `access - byte'. See SW. */ 3364 LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL); 3365 /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n", 3366 (long) paddr, byte, (long) paddr, (long) memval); */ 3367 { 3368 unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0); 3369 rt &= ~screen; 3370 rt |= (memval >> (8 * byte)) & screen; 3371 } 3372 return rt; 3373} 3374 3375 3376100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB 3377"lb r<RT>, <OFFSET>(r<BASE>)" 3378*mipsI: 3379*mipsII: 3380*mipsIII: 3381*mipsIV: 3382*mipsV: 3383*mips32: 3384*mips32r2: 3385*mips32r6: 3386*mips64: 3387*mips64r2: 3388*mips64r6: 3389*vr4100: 3390*vr5000: 3391*r3900: 3392{ 3393 do_lb (SD_,RT,OFFSET,BASE); 3394} 3395 3396 3397100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU 3398"lbu r<RT>, <OFFSET>(r<BASE>)" 3399*mipsI: 3400*mipsII: 3401*mipsIII: 3402*mipsIV: 3403*mipsV: 3404*mips32: 3405*mips32r2: 3406*mips32r6: 3407*mips64: 3408*mips64r2: 3409*mips64r6: 3410*vr4100: 3411*vr5000: 3412*r3900: 3413{ 3414 do_lbu (SD_, RT,OFFSET,BASE); 3415} 3416 3417 3418110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD 3419"ld r<RT>, <OFFSET>(r<BASE>)" 3420*mipsIII: 3421*mipsIV: 3422*mipsV: 3423*mips64: 3424*mips64r2: 3425*mips64r6: 3426*vr4100: 3427*vr5000: 3428{ 3429 check_u64 (SD_, instruction_0); 3430 GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); 3431} 3432 3433 34341101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz 3435"ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 3436*mipsII: 3437*mipsIII: 3438*mipsIV: 3439*mipsV: 3440*mips32: 3441*mips32r2: 3442*mips64: 3443*mips64r2: 3444*vr4100: 3445*vr5000: 3446*r3900: 3447{ 3448 do_ldc (SD_, ZZ, RT, OFFSET, BASE); 3449} 3450 3451 3452 3453 3454011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL 3455"ldl r<RT>, <OFFSET>(r<BASE>)" 3456*mipsIII: 3457*mipsIV: 3458*mipsV: 3459*mips64: 3460*mips64r2: 3461*vr4100: 3462*vr5000: 3463{ 3464 check_u64 (SD_, instruction_0); 3465 GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3466} 3467 3468 3469011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR 3470"ldr r<RT>, <OFFSET>(r<BASE>)" 3471*mipsIII: 3472*mipsIV: 3473*mipsV: 3474*mips64: 3475*mips64r2: 3476*vr4100: 3477*vr5000: 3478{ 3479 check_u64 (SD_, instruction_0); 3480 GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 3481} 3482 3483 3484100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH 3485"lh r<RT>, <OFFSET>(r<BASE>)" 3486*mipsI: 3487*mipsII: 3488*mipsIII: 3489*mipsIV: 3490*mipsV: 3491*mips32: 3492*mips32r2: 3493*mips32r6: 3494*mips64: 3495*mips64r2: 3496*mips64r6: 3497*vr4100: 3498*vr5000: 3499*r3900: 3500{ 3501 do_lh (SD_,RT,OFFSET,BASE); 3502} 3503 3504 3505100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU 3506"lhu r<RT>, <OFFSET>(r<BASE>)" 3507*mipsI: 3508*mipsII: 3509*mipsIII: 3510*mipsIV: 3511*mipsV: 3512*mips32: 3513*mips32r2: 3514*mips32r6: 3515*mips64: 3516*mips64r2: 3517*mips64r6: 3518*vr4100: 3519*vr5000: 3520*r3900: 3521{ 3522 do_lhu (SD_,RT,OFFSET,BASE); 3523} 3524 3525 3526110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL 3527"ll r<RT>, <OFFSET>(r<BASE>)" 3528*mipsII: 3529*mipsIII: 3530*mipsIV: 3531*mipsV: 3532*mips32: 3533*mips32r2: 3534*mips64: 3535*mips64r2: 3536*vr4100: 3537*vr5000: 3538{ 3539 do_ll (SD_, RT, OFFSET, BASE); 3540} 3541 3542 3543110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD 3544"lld r<RT>, <OFFSET>(r<BASE>)" 3545*mipsIII: 3546*mipsIV: 3547*mipsV: 3548*mips64: 3549*mips64r2: 3550*vr4100: 3551*vr5000: 3552{ 3553 check_u64 (SD_, instruction_0); 3554 do_lld (SD_, RT, OFFSET, BASE); 3555} 3556 3557 3558001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI 3559"lui r<RT>, %#lx<IMMEDIATE>" 3560*mipsI: 3561*mipsII: 3562*mipsIII: 3563*mipsIV: 3564*mipsV: 3565*mips32: 3566*mips32r2: 3567*mips32r6: 3568*mips64: 3569*mips64r2: 3570*mips64r6: 3571*vr4100: 3572*vr5000: 3573*r3900: 3574{ 3575 do_lui (SD_, RT, IMMEDIATE); 3576} 3577 3578 3579100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW 3580"lw r<RT>, <OFFSET>(r<BASE>)" 3581*mipsI: 3582*mipsII: 3583*mipsIII: 3584*mipsIV: 3585*mipsV: 3586*mips32: 3587*mips32r2: 3588*mips32r6: 3589*mips64: 3590*mips64r2: 3591*mips64r6: 3592*vr4100: 3593*vr5000: 3594*r3900: 3595{ 3596 do_lw (SD_,RT,OFFSET,BASE); 3597} 3598 3599 36001100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz 3601"lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 3602*mipsI: 3603*mipsII: 3604*mipsIII: 3605*mipsIV: 3606*mipsV: 3607*mips32: 3608*mips32r2: 3609*mips64: 3610*mips64r2: 3611*vr4100: 3612*vr5000: 3613*r3900: 3614{ 3615 do_lwc (SD_, ZZ, RT, OFFSET, BASE); 3616} 3617 3618 3619100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL 3620"lwl r<RT>, <OFFSET>(r<BASE>)" 3621*mipsI: 3622*mipsII: 3623*mipsIII: 3624*mipsIV: 3625*mipsV: 3626*mips32: 3627*mips32r2: 3628*mips64: 3629*mips64r2: 3630*vr4100: 3631*vr5000: 3632*r3900: 3633{ 3634 do_lwl (SD_, RT, OFFSET, BASE); 3635} 3636 3637 3638100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR 3639"lwr r<RT>, <OFFSET>(r<BASE>)" 3640*mipsI: 3641*mipsII: 3642*mipsIII: 3643*mipsIV: 3644*mipsV: 3645*mips32: 3646*mips32r2: 3647*mips64: 3648*mips64r2: 3649*vr4100: 3650*vr5000: 3651*r3900: 3652{ 3653 do_lwr (SD_, RT, OFFSET, BASE); 3654} 3655 3656 3657100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU 3658"lwu r<RT>, <OFFSET>(r<BASE>)" 3659*mipsIII: 3660*mipsIV: 3661*mipsV: 3662*mips64: 3663*mips64r2: 3664*mips64r6: 3665*vr4100: 3666*vr5000: 3667{ 3668 do_lwu (SD_, RT, OFFSET, BASE, instruction_0); 3669} 3670 3671 3672 3673011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD 3674"madd r<RS>, r<RT>" 3675*mips32: 3676*mips64: 3677*vr5500: 3678{ 3679 do_madd (SD_, RS, RT); 3680} 3681 3682 3683011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD 3684"madd r<RS>, r<RT>":AC == 0 3685"madd ac<AC>, r<RS>, r<RT>" 3686*mips32r2: 3687*mips64r2: 3688*dsp2: 3689{ 3690 do_dsp_madd (SD_, AC, RS, RT); 3691} 3692 3693 3694011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU 3695"maddu r<RS>, r<RT>" 3696*mips32: 3697*mips64: 3698*vr5500: 3699{ 3700 do_maddu (SD_, RS, RT); 3701} 3702 3703 3704011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU 3705"maddu r<RS>, r<RT>":AC == 0 3706"maddu ac<AC>, r<RS>, r<RT>" 3707*mips32r2: 3708*mips64r2: 3709*dsp2: 3710{ 3711 do_dsp_maddu (SD_, AC, RS, RT); 3712} 3713 3714 3715:function:::void:do_mfhi:int rd 3716{ 3717 check_mf_hilo (SD_, HIHISTORY, LOHISTORY); 3718 TRACE_ALU_INPUT1 (HI); 3719 GPR[rd] = HI; 3720 TRACE_ALU_RESULT (GPR[rd]); 3721} 3722 3723000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI 3724"mfhi r<RD>" 3725*mipsI: 3726*mipsII: 3727*mipsIII: 3728*mipsIV: 3729*mipsV: 3730*vr4100: 3731*vr5000: 3732*r3900: 3733*mips32: 3734*mips64: 3735{ 3736 do_mfhi (SD_, RD); 3737} 3738 3739 3740000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI 3741"mfhi r<RD>":AC == 0 3742"mfhi r<RD>, ac<AC>" 3743*mips32r2: 3744*mips64r2: 3745*dsp: 3746{ 3747 do_dsp_mfhi (SD_, AC, RD); 3748} 3749 3750 3751:function:::void:do_mflo:int rd 3752{ 3753 check_mf_hilo (SD_, LOHISTORY, HIHISTORY); 3754 TRACE_ALU_INPUT1 (LO); 3755 GPR[rd] = LO; 3756 TRACE_ALU_RESULT (GPR[rd]); 3757} 3758 3759000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO 3760"mflo r<RD>" 3761*mipsI: 3762*mipsII: 3763*mipsIII: 3764*mipsIV: 3765*mipsV: 3766*vr4100: 3767*vr5000: 3768*r3900: 3769*mips32: 3770*mips64: 3771{ 3772 do_mflo (SD_, RD); 3773} 3774 3775 3776000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO 3777"mflo r<RD>":AC == 0 3778"mflo r<RD>, ac<AC>" 3779*mips32r2: 3780*mips64r2: 3781*dsp: 3782{ 3783 do_dsp_mflo (SD_, AC, RD); 3784} 3785 3786 3787000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN 3788"movn r<RD>, r<RS>, r<RT>" 3789*mipsIV: 3790*mipsV: 3791*mips32: 3792*mips32r2: 3793*mips64: 3794*mips64r2: 3795*vr5000: 3796{ 3797 do_movn (SD_, RD, RS, RT); 3798} 3799 3800 3801 3802000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ 3803"movz r<RD>, r<RS>, r<RT>" 3804*mipsIV: 3805*mipsV: 3806*mips32: 3807*mips32r2: 3808*mips64: 3809*mips64r2: 3810*vr5000: 3811{ 3812 do_movz (SD_, RD, RS, RT); 3813} 3814 3815 3816 3817011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB 3818"msub r<RS>, r<RT>" 3819*mips32: 3820*mips64: 3821*vr5500: 3822{ 3823 do_msub (SD_, RS, RT); 3824} 3825 3826 3827011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB 3828"msub r<RS>, r<RT>":AC == 0 3829"msub ac<AC>, r<RS>, r<RT>" 3830*mips32r2: 3831*mips64r2: 3832*dsp2: 3833{ 3834 do_dsp_msub (SD_, AC, RS, RT); 3835} 3836 3837 3838011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU 3839"msubu r<RS>, r<RT>" 3840*mips32: 3841*mips64: 3842*vr5500: 3843{ 3844 do_msubu (SD_, RS, RT); 3845} 3846 3847 3848011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU 3849"msubu r<RS>, r<RT>":AC == 0 3850"msubu ac<AC>, r<RS>, r<RT>" 3851*mips32r2: 3852*mips64r2: 3853*dsp2: 3854{ 3855 do_dsp_msubu (SD_, AC, RS, RT); 3856} 3857 3858 3859000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI 3860"mthi r<RS>" 3861*mipsI: 3862*mipsII: 3863*mipsIII: 3864*mipsIV: 3865*mipsV: 3866*vr4100: 3867*vr5000: 3868*r3900: 3869*mips32: 3870*mips64: 3871{ 3872 do_mthi (SD_, RS); 3873} 3874 3875 3876000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI 3877"mthi r<RS>":AC == 0 3878"mthi r<RS>, ac<AC>" 3879*mips32r2: 3880*mips64r2: 3881*dsp: 3882{ 3883 do_dsp_mthi (SD_, AC, RS); 3884} 3885 3886 3887000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO 3888"mtlo r<RS>" 3889*mipsI: 3890*mipsII: 3891*mipsIII: 3892*mipsIV: 3893*mipsV: 3894*vr4100: 3895*vr5000: 3896*r3900: 3897*mips32: 3898*mips64: 3899{ 3900 do_mtlo (SD_, RS); 3901} 3902 3903 3904000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO 3905"mtlo r<RS>":AC == 0 3906"mtlo r<RS>, ac<AC>" 3907*mips32r2: 3908*mips64r2: 3909*dsp: 3910{ 3911 do_dsp_mtlo (SD_, AC, RS); 3912} 3913 3914 3915011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL 3916"mul r<RD>, r<RS>, r<RT>" 3917*mips32: 3918*mips32r2: 3919*mips64: 3920*mips64r2: 3921*vr5500: 3922{ 3923 do_mul (SD_, RD, RS, RT); 3924} 3925 3926 3927 3928:function:::void:do_mult:int rs, int rt, int rd 3929{ 3930 int64_t prod; 3931 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 3932 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 3933 Unpredictable (); 3934 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3935 prod = (((int64_t)(int32_t) GPR[rs]) 3936 * ((int64_t)(int32_t) GPR[rt])); 3937 LO = EXTEND32 (VL4_8 (prod)); 3938 HI = EXTEND32 (VH4_8 (prod)); 3939 ACX = 0; /* SmartMIPS */ 3940 if (rd != 0) 3941 GPR[rd] = LO; 3942 TRACE_ALU_RESULT2 (HI, LO); 3943} 3944 3945000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT 3946"mult r<RS>, r<RT>" 3947*mipsI: 3948*mipsII: 3949*mipsIII: 3950*mipsIV: 3951*mipsV: 3952*mips32: 3953*mips64: 3954*vr4100: 3955{ 3956 do_mult (SD_, RS, RT, 0); 3957} 3958 3959 3960000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT 3961"mult r<RS>, r<RT>":AC == 0 3962"mult ac<AC>, r<RS>, r<RT>" 3963*mips32r2: 3964*mips64r2: 3965*dsp2: 3966{ 3967 do_dsp_mult (SD_, AC, RS, RT); 3968} 3969 3970 3971000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT 3972"mult r<RS>, r<RT>":RD == 0 3973"mult r<RD>, r<RS>, r<RT>" 3974*vr5000: 3975*r3900: 3976{ 3977 do_mult (SD_, RS, RT, RD); 3978} 3979 3980 3981:function:::void:do_multu:int rs, int rt, int rd 3982{ 3983 uint64_t prod; 3984 check_mult_hilo (SD_, HIHISTORY, LOHISTORY); 3985 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 3986 Unpredictable (); 3987 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 3988 prod = (((uint64_t)(uint32_t) GPR[rs]) 3989 * ((uint64_t)(uint32_t) GPR[rt])); 3990 LO = EXTEND32 (VL4_8 (prod)); 3991 HI = EXTEND32 (VH4_8 (prod)); 3992 if (rd != 0) 3993 GPR[rd] = LO; 3994 TRACE_ALU_RESULT2 (HI, LO); 3995} 3996 3997000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU 3998"multu r<RS>, r<RT>" 3999*mipsI: 4000*mipsII: 4001*mipsIII: 4002*mipsIV: 4003*mipsV: 4004*mips32: 4005*mips64: 4006*vr4100: 4007{ 4008 do_multu (SD_, RS, RT, 0); 4009} 4010 4011 4012000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU 4013"multu r<RS>, r<RT>":AC == 0 4014"multu r<RS>, r<RT>" 4015*mips32r2: 4016*mips64r2: 4017*dsp2: 4018{ 4019 do_dsp_multu (SD_, AC, RS, RT); 4020} 4021 4022 4023000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU 4024"multu r<RS>, r<RT>":RD == 0 4025"multu r<RD>, r<RS>, r<RT>" 4026*vr5000: 4027*r3900: 4028{ 4029 do_multu (SD_, RS, RT, RD); 4030} 4031 4032 4033:function:::void:do_nor:int rs, int rt, int rd 4034{ 4035 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4036 GPR[rd] = ~ (GPR[rs] | GPR[rt]); 4037 TRACE_ALU_RESULT (GPR[rd]); 4038} 4039 4040000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR 4041"nor r<RD>, r<RS>, r<RT>" 4042*mipsI: 4043*mipsII: 4044*mipsIII: 4045*mipsIV: 4046*mipsV: 4047*mips32: 4048*mips32r2: 4049*mips32r6: 4050*mips64: 4051*mips64r2: 4052*mips64r6: 4053*vr4100: 4054*vr5000: 4055*r3900: 4056{ 4057 do_nor (SD_, RS, RT, RD); 4058} 4059 4060 4061:function:::void:do_or:int rs, int rt, int rd 4062{ 4063 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4064 GPR[rd] = (GPR[rs] | GPR[rt]); 4065 TRACE_ALU_RESULT (GPR[rd]); 4066} 4067 4068000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR 4069"or r<RD>, r<RS>, r<RT>" 4070*mipsI: 4071*mipsII: 4072*mipsIII: 4073*mipsIV: 4074*mipsV: 4075*mips32: 4076*mips32r2: 4077*mips32r6: 4078*mips64: 4079*mips64r2: 4080*mips64r6: 4081*vr4100: 4082*vr5000: 4083*r3900: 4084{ 4085 do_or (SD_, RS, RT, RD); 4086} 4087 4088 4089 4090:function:::void:do_ori:int rs, int rt, unsigned immediate 4091{ 4092 TRACE_ALU_INPUT2 (GPR[rs], immediate); 4093 GPR[rt] = (GPR[rs] | immediate); 4094 TRACE_ALU_RESULT (GPR[rt]); 4095} 4096 4097001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI 4098"ori r<RT>, r<RS>, %#lx<IMMEDIATE>" 4099*mipsI: 4100*mipsII: 4101*mipsIII: 4102*mipsIV: 4103*mipsV: 4104*mips32: 4105*mips32r2: 4106*mips32r6: 4107*mips64: 4108*mips64r2: 4109*mips64r6: 4110*vr4100: 4111*vr5000: 4112*r3900: 4113{ 4114 do_ori (SD_, RS, RT, IMMEDIATE); 4115} 4116 4117 4118110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF 4119"pref <HINT>, <OFFSET>(r<BASE>)" 4120*mipsIV: 4121*mipsV: 4122*mips32: 4123*mips32r2: 4124*mips64: 4125*mips64r2: 4126*vr5000: 4127{ 4128 do_pref (SD_, HINT, OFFSET, BASE); 4129} 4130 4131 4132:function:::uint64_t:do_ror:uint32_t x,uint32_t y 4133{ 4134 uint64_t result; 4135 4136 y &= 31; 4137 TRACE_ALU_INPUT2 (x, y); 4138 result = EXTEND32 (ROTR32 (x, y)); 4139 TRACE_ALU_RESULT (result); 4140 return result; 4141} 4142 4143000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR 4144"ror r<RD>, r<RT>, <SHIFT>" 4145*mips32r2: 4146*mips32r6: 4147*mips64r2: 4148*mips64r6: 4149*smartmips: 4150*vr5400: 4151*vr5500: 4152{ 4153 GPR[RD] = do_ror (SD_, GPR[RT], SHIFT); 4154} 4155 4156000000,5.RS,5.RT,5.RD,00001,000110::32::RORV 4157"rorv r<RD>, r<RT>, r<RS>" 4158*mips32r2: 4159*mips32r6: 4160*mips64r2: 4161*mips64r6: 4162*smartmips: 4163*vr5400: 4164*vr5500: 4165{ 4166 GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]); 4167} 4168 4169 4170:function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word 4171{ 4172 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 4173 address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0); 4174 address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0); 4175 unsigned int byte; 4176 address_word paddr; 4177 uint64_t memval; 4178 address_word vaddr; 4179 4180 paddr = vaddr = loadstore_ea (SD_, base, offset); 4181 if ((vaddr & access) != 0) 4182 { 4183 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal); 4184 } 4185 paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian)); 4186 byte = ((vaddr & mask) ^ bigendiancpu); 4187 memval = (word << (8 * byte)); 4188 StoreMemory (access, memval, 0, paddr, vaddr, isREAL); 4189} 4190 4191:function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt 4192{ 4193 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 4194 address_word reverseendian = (ReverseEndian ? -1 : 0); 4195 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 4196 unsigned int byte; 4197 unsigned int word; 4198 address_word paddr; 4199 uint64_t memval; 4200 address_word vaddr; 4201 int nr_lhs_bits; 4202 int nr_rhs_bits; 4203 4204 paddr = vaddr = loadstore_ea (SD_, base, offset); 4205 paddr = (paddr ^ (reverseendian & mask)); 4206 if (BigEndianMem == 0) 4207 paddr = paddr & ~access; 4208 4209 /* compute where within the word/mem we are */ 4210 byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */ 4211 word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */ 4212 nr_lhs_bits = 8 * byte + 8; 4213 nr_rhs_bits = 8 * access - 8 * byte; 4214 /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */ 4215 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n", 4216 (long) ((uint64_t) vaddr >> 32), (long) vaddr, 4217 (long) ((uint64_t) paddr >> 32), (long) paddr, 4218 word, byte, nr_lhs_bits, nr_rhs_bits); */ 4219 4220 if (word == 0) 4221 { 4222 memval = (rt >> nr_rhs_bits); 4223 } 4224 else 4225 { 4226 memval = (rt << nr_lhs_bits); 4227 } 4228 /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n", 4229 (long) ((uint64_t) rt >> 32), (long) rt, 4230 (long) ((uint64_t) memval >> 32), (long) memval); */ 4231 StoreMemory (byte, memval, 0, paddr, vaddr, isREAL); 4232} 4233 4234:function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt 4235{ 4236 address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3); 4237 address_word reverseendian = (ReverseEndian ? -1 : 0); 4238 address_word bigendiancpu = (BigEndianCPU ? -1 : 0); 4239 unsigned int byte; 4240 address_word paddr; 4241 uint64_t memval; 4242 address_word vaddr; 4243 4244 paddr = vaddr = loadstore_ea (SD_, base, offset); 4245 paddr = (paddr ^ (reverseendian & mask)); 4246 if (BigEndianMem != 0) 4247 paddr &= ~access; 4248 byte = ((vaddr & mask) ^ (bigendiancpu & mask)); 4249 memval = (rt << (byte * 8)); 4250 StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL); 4251} 4252 4253 4254101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB 4255"sb r<RT>, <OFFSET>(r<BASE>)" 4256*mipsI: 4257*mipsII: 4258*mipsIII: 4259*mipsIV: 4260*mipsV: 4261*mips32: 4262*mips32r2: 4263*mips32r6: 4264*mips64: 4265*mips64r2: 4266*mips64r6: 4267*vr4100: 4268*vr5000: 4269*r3900: 4270{ 4271 do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4272} 4273 4274 4275111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC 4276"sc r<RT>, <OFFSET>(r<BASE>)" 4277*mipsII: 4278*mipsIII: 4279*mipsIV: 4280*mipsV: 4281*mips32: 4282*mips32r2: 4283*mips64: 4284*mips64r2: 4285*vr4100: 4286*vr5000: 4287{ 4288 do_sc (SD_, RT, OFFSET, BASE, instruction_0, 1); 4289} 4290 4291 4292111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD 4293"scd r<RT>, <OFFSET>(r<BASE>)" 4294*mipsIII: 4295*mipsIV: 4296*mipsV: 4297*mips64: 4298*mips64r2: 4299*vr4100: 4300*vr5000: 4301{ 4302 check_u64 (SD_, instruction_0); 4303 do_scd (SD_, RT, OFFSET, BASE, 1); 4304} 4305 4306 4307111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD 4308"sd r<RT>, <OFFSET>(r<BASE>)" 4309*mipsIII: 4310*mipsIV: 4311*mipsV: 4312*mips64: 4313*mips64r2: 4314*mips64r6: 4315*vr4100: 4316*vr5000: 4317{ 4318 check_u64 (SD_, instruction_0); 4319 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4320} 4321 4322 43231111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz 4324"sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 4325*mipsII: 4326*mipsIII: 4327*mipsIV: 4328*mipsV: 4329*mips32: 4330*mips32r2: 4331*mips64: 4332*mips64r2: 4333*vr4100: 4334*vr5000: 4335{ 4336 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); 4337} 4338 4339 4340101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL 4341"sdl r<RT>, <OFFSET>(r<BASE>)" 4342*mipsIII: 4343*mipsIV: 4344*mipsV: 4345*mips64: 4346*mips64r2: 4347*vr4100: 4348*vr5000: 4349{ 4350 check_u64 (SD_, instruction_0); 4351 do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4352} 4353 4354 4355101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR 4356"sdr r<RT>, <OFFSET>(r<BASE>)" 4357*mipsIII: 4358*mipsIV: 4359*mipsV: 4360*mips64: 4361*mips64r2: 4362*vr4100: 4363*vr5000: 4364{ 4365 check_u64 (SD_, instruction_0); 4366 do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4367} 4368 4369 4370 4371101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH 4372"sh r<RT>, <OFFSET>(r<BASE>)" 4373*mipsI: 4374*mipsII: 4375*mipsIII: 4376*mipsIV: 4377*mipsV: 4378*mips32: 4379*mips32r2: 4380*mips32r6: 4381*mips64: 4382*mips64r2: 4383*mips64r6: 4384*vr4100: 4385*vr5000: 4386*r3900: 4387{ 4388 do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4389} 4390 4391 4392:function:::void:do_sll:int rt, int rd, int shift 4393{ 4394 uint32_t temp = (GPR[rt] << shift); 4395 TRACE_ALU_INPUT2 (GPR[rt], shift); 4396 GPR[rd] = EXTEND32 (temp); 4397 TRACE_ALU_RESULT (GPR[rd]); 4398} 4399 4400000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa 4401"nop":RD == 0 && RT == 0 && SHIFT == 0 4402"sll r<RD>, r<RT>, <SHIFT>" 4403*mipsI: 4404*mipsII: 4405*mipsIII: 4406*mipsIV: 4407*mipsV: 4408*vr4100: 4409*vr5000: 4410*r3900: 4411{ 4412 /* Skip shift for NOP, so that there won't be lots of extraneous 4413 trace output. */ 4414 if (RD != 0 || RT != 0 || SHIFT != 0) 4415 do_sll (SD_, RT, RD, SHIFT); 4416} 4417 4418000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb 4419"nop":RD == 0 && RT == 0 && SHIFT == 0 4420"ssnop":RD == 0 && RT == 0 && SHIFT == 1 4421"ehb":RD == 0 && RT == 0 && SHIFT == 3 4422"sll r<RD>, r<RT>, <SHIFT>" 4423*mips32: 4424*mips32r2: 4425*mips32r6: 4426*mips64: 4427*mips64r2: 4428*mips64r6: 4429{ 4430 do_sll (SD_, RT, RD, SHIFT); 4431} 4432 4433 4434:function:::void:do_sllv:int rs, int rt, int rd 4435{ 4436 int s = MASKED (GPR[rs], 4, 0); 4437 uint32_t temp = (GPR[rt] << s); 4438 TRACE_ALU_INPUT2 (GPR[rt], s); 4439 GPR[rd] = EXTEND32 (temp); 4440 TRACE_ALU_RESULT (GPR[rd]); 4441} 4442 4443000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV 4444"sllv r<RD>, r<RT>, r<RS>" 4445*mipsI: 4446*mipsII: 4447*mipsIII: 4448*mipsIV: 4449*mipsV: 4450*mips32: 4451*mips32r2: 4452*mips32r6: 4453*mips64: 4454*mips64r2: 4455*mips64r6: 4456*vr4100: 4457*vr5000: 4458*r3900: 4459{ 4460 do_sllv (SD_, RS, RT, RD); 4461} 4462 4463 4464:function:::void:do_slt:int rs, int rt, int rd 4465{ 4466 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4467 GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]); 4468 TRACE_ALU_RESULT (GPR[rd]); 4469} 4470 4471000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT 4472"slt r<RD>, r<RS>, r<RT>" 4473*mipsI: 4474*mipsII: 4475*mipsIII: 4476*mipsIV: 4477*mipsV: 4478*mips32: 4479*mips32r2: 4480*mips32r6: 4481*mips64: 4482*mips64r2: 4483*mips64r6: 4484*vr4100: 4485*vr5000: 4486*r3900: 4487{ 4488 do_slt (SD_, RS, RT, RD); 4489} 4490 4491 4492:function:::void:do_slti:int rs, int rt, uint16_t immediate 4493{ 4494 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 4495 GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate)); 4496 TRACE_ALU_RESULT (GPR[rt]); 4497} 4498 4499001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI 4500"slti r<RT>, r<RS>, <IMMEDIATE>" 4501*mipsI: 4502*mipsII: 4503*mipsIII: 4504*mipsIV: 4505*mipsV: 4506*mips32: 4507*mips32r2: 4508*mips32r6: 4509*mips64: 4510*mips64r2: 4511*mips64r6: 4512*vr4100: 4513*vr5000: 4514*r3900: 4515{ 4516 do_slti (SD_, RS, RT, IMMEDIATE); 4517} 4518 4519 4520:function:::void:do_sltiu:int rs, int rt, uint16_t immediate 4521{ 4522 TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate)); 4523 GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate)); 4524 TRACE_ALU_RESULT (GPR[rt]); 4525} 4526 4527001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU 4528"sltiu r<RT>, r<RS>, <IMMEDIATE>" 4529*mipsI: 4530*mipsII: 4531*mipsIII: 4532*mipsIV: 4533*mipsV: 4534*mips32: 4535*mips32r2: 4536*mips32r6: 4537*mips64: 4538*mips64r2: 4539*mips64r6: 4540*vr4100: 4541*vr5000: 4542*r3900: 4543{ 4544 do_sltiu (SD_, RS, RT, IMMEDIATE); 4545} 4546 4547 4548 4549:function:::void:do_sltu:int rs, int rt, int rd 4550{ 4551 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4552 GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]); 4553 TRACE_ALU_RESULT (GPR[rd]); 4554} 4555 4556000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU 4557"sltu r<RD>, r<RS>, r<RT>" 4558*mipsI: 4559*mipsII: 4560*mipsIII: 4561*mipsIV: 4562*mipsV: 4563*mips32: 4564*mips32r2: 4565*mips32r6: 4566*mips64: 4567*mips64r2: 4568*mips64r6: 4569*vr4100: 4570*vr5000: 4571*r3900: 4572{ 4573 do_sltu (SD_, RS, RT, RD); 4574} 4575 4576 4577:function:::void:do_sra:int rt, int rd, int shift 4578{ 4579 int32_t temp = (int32_t) GPR[rt] >> shift; 4580 if (NotWordValue (GPR[rt])) 4581 Unpredictable (); 4582 TRACE_ALU_INPUT2 (GPR[rt], shift); 4583 GPR[rd] = EXTEND32 (temp); 4584 TRACE_ALU_RESULT (GPR[rd]); 4585} 4586 4587000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA 4588"sra r<RD>, r<RT>, <SHIFT>" 4589*mipsI: 4590*mipsII: 4591*mipsIII: 4592*mipsIV: 4593*mipsV: 4594*mips32: 4595*mips32r2: 4596*mips32r6: 4597*mips64: 4598*mips64r2: 4599*mips64r6: 4600*vr4100: 4601*vr5000: 4602*r3900: 4603{ 4604 do_sra (SD_, RT, RD, SHIFT); 4605} 4606 4607 4608 4609:function:::void:do_srav:int rs, int rt, int rd 4610{ 4611 int s = MASKED (GPR[rs], 4, 0); 4612 int32_t temp = (int32_t) GPR[rt] >> s; 4613 if (NotWordValue (GPR[rt])) 4614 Unpredictable (); 4615 TRACE_ALU_INPUT2 (GPR[rt], s); 4616 GPR[rd] = EXTEND32 (temp); 4617 TRACE_ALU_RESULT (GPR[rd]); 4618} 4619 4620000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV 4621"srav r<RD>, r<RT>, r<RS>" 4622*mipsI: 4623*mipsII: 4624*mipsIII: 4625*mipsIV: 4626*mipsV: 4627*mips32: 4628*mips32r2: 4629*mips32r6: 4630*mips64: 4631*mips64r2: 4632*mips64r6: 4633*vr4100: 4634*vr5000: 4635*r3900: 4636{ 4637 do_srav (SD_, RS, RT, RD); 4638} 4639 4640 4641 4642:function:::void:do_srl:int rt, int rd, int shift 4643{ 4644 uint32_t temp = (uint32_t) GPR[rt] >> shift; 4645 if (NotWordValue (GPR[rt])) 4646 Unpredictable (); 4647 TRACE_ALU_INPUT2 (GPR[rt], shift); 4648 GPR[rd] = EXTEND32 (temp); 4649 TRACE_ALU_RESULT (GPR[rd]); 4650} 4651 4652000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL 4653"srl r<RD>, r<RT>, <SHIFT>" 4654*mipsI: 4655*mipsII: 4656*mipsIII: 4657*mipsIV: 4658*mipsV: 4659*mips32: 4660*mips32r2: 4661*mips32r6: 4662*mips64: 4663*mips64r2: 4664*mips64r6: 4665*vr4100: 4666*vr5000: 4667*r3900: 4668{ 4669 do_srl (SD_, RT, RD, SHIFT); 4670} 4671 4672 4673:function:::void:do_srlv:int rs, int rt, int rd 4674{ 4675 int s = MASKED (GPR[rs], 4, 0); 4676 uint32_t temp = (uint32_t) GPR[rt] >> s; 4677 if (NotWordValue (GPR[rt])) 4678 Unpredictable (); 4679 TRACE_ALU_INPUT2 (GPR[rt], s); 4680 GPR[rd] = EXTEND32 (temp); 4681 TRACE_ALU_RESULT (GPR[rd]); 4682} 4683 4684000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV 4685"srlv r<RD>, r<RT>, r<RS>" 4686*mipsI: 4687*mipsII: 4688*mipsIII: 4689*mipsIV: 4690*mipsV: 4691*mips32: 4692*mips32r2: 4693*mips32r6: 4694*mips64: 4695*mips64r2: 4696*mips64r6: 4697*vr4100: 4698*vr5000: 4699*r3900: 4700{ 4701 do_srlv (SD_, RS, RT, RD); 4702} 4703 4704 4705000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB 4706"sub r<RD>, r<RS>, r<RT>" 4707*mipsI: 4708*mipsII: 4709*mipsIII: 4710*mipsIV: 4711*mipsV: 4712*mips32: 4713*mips32r2: 4714*mips32r6: 4715*mips64: 4716*mips64r2: 4717*mips64r6: 4718*vr4100: 4719*vr5000: 4720*r3900: 4721{ 4722 do_sub (SD_, RD, RS, RT); 4723} 4724 4725 4726:function:::void:do_subu:int rs, int rt, int rd 4727{ 4728 if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt])) 4729 Unpredictable (); 4730 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 4731 GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]); 4732 TRACE_ALU_RESULT (GPR[rd]); 4733} 4734 4735000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU 4736"subu r<RD>, r<RS>, r<RT>" 4737*mipsI: 4738*mipsII: 4739*mipsIII: 4740*mipsIV: 4741*mipsV: 4742*mips32: 4743*mips32r2: 4744*mips32r6: 4745*mips64: 4746*mips64r2: 4747*mips64r6: 4748*vr4100: 4749*vr5000: 4750*r3900: 4751{ 4752 do_subu (SD_, RS, RT, RD); 4753} 4754 4755 4756101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW 4757"sw r<RT>, <OFFSET>(r<BASE>)" 4758*mipsI: 4759*mipsII: 4760*mipsIII: 4761*mipsIV: 4762*mipsV: 4763*mips32: 4764*mips32r2: 4765*mips32r6: 4766*mips64: 4767*mips64r2: 4768*mips64r6: 4769*vr4100: 4770*r3900: 4771*vr5000: 4772{ 4773 do_sw (SD_, RT, OFFSET, BASE); 4774} 4775 4776 47771110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz 4778"swc<ZZ> r<RT>, <OFFSET>(r<BASE>)" 4779*mipsI: 4780*mipsII: 4781*mipsIII: 4782*mipsIV: 4783*mipsV: 4784*mips32: 4785*mips32r2: 4786*mips64: 4787*mips64r2: 4788*vr4100: 4789*vr5000: 4790*r3900: 4791{ 4792 do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); 4793} 4794 4795 4796101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL 4797"swl r<RT>, <OFFSET>(r<BASE>)" 4798*mipsI: 4799*mipsII: 4800*mipsIII: 4801*mipsIV: 4802*mipsV: 4803*mips32: 4804*mips32r2: 4805*mips64: 4806*mips64r2: 4807*vr4100: 4808*vr5000: 4809*r3900: 4810{ 4811 do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4812} 4813 4814 4815101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR 4816"swr r<RT>, <OFFSET>(r<BASE>)" 4817*mipsI: 4818*mipsII: 4819*mipsIII: 4820*mipsIV: 4821*mipsV: 4822*mips32: 4823*mips32r2: 4824*mips64: 4825*mips64r2: 4826*vr4100: 4827*vr5000: 4828*r3900: 4829{ 4830 do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); 4831} 4832 4833 4834000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC 4835"sync":STYPE == 0 4836"sync <STYPE>" 4837*mipsII: 4838*mipsIII: 4839*mipsIV: 4840*mipsV: 4841*mips32: 4842*mips32r2: 4843*mips32r6: 4844*mips64: 4845*mips64r2: 4846*mips64r6: 4847*vr4100: 4848*vr5000: 4849*r3900: 4850{ 4851 SyncOperation (STYPE); 4852} 4853 4854 4855000000,20.CODE,001100:SPECIAL:32::SYSCALL 4856"syscall %#lx<CODE>" 4857*mipsI: 4858*mipsII: 4859*mipsIII: 4860*mipsIV: 4861*mipsV: 4862*mips32: 4863*mips32r2: 4864*mips32r6: 4865*mips64: 4866*mips64r2: 4867*mips64r6: 4868*vr4100: 4869*vr5000: 4870*r3900: 4871{ 4872 SignalException (SystemCall, instruction_0); 4873} 4874 4875 4876000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ 4877"teq r<RS>, r<RT>" 4878*mipsII: 4879*mipsIII: 4880*mipsIV: 4881*mipsV: 4882*mips32: 4883*mips32r2: 4884*mips32r6: 4885*mips64: 4886*mips64r2: 4887*mips64r6: 4888*vr4100: 4889*vr5000: 4890{ 4891 do_teq (SD_, RS, RT, instruction_0); 4892} 4893 4894 4895000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI 4896"teqi r<RS>, <IMMEDIATE>" 4897*mipsII: 4898*mipsIII: 4899*mipsIV: 4900*mipsV: 4901*mips32: 4902*mips32r2: 4903*mips64: 4904*mips64r2: 4905*vr4100: 4906*vr5000: 4907{ 4908 do_teqi (SD_, RS, IMMEDIATE, instruction_0); 4909} 4910 4911 4912000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE 4913"tge r<RS>, r<RT>" 4914*mipsII: 4915*mipsIII: 4916*mipsIV: 4917*mipsV: 4918*mips32: 4919*mips32r2: 4920*mips32r6: 4921*mips64: 4922*mips64r2: 4923*mips64r6: 4924*vr4100: 4925*vr5000: 4926{ 4927 do_tge (SD_, RS, RT, instruction_0); 4928} 4929 4930 4931000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI 4932"tgei r<RS>, <IMMEDIATE>" 4933*mipsII: 4934*mipsIII: 4935*mipsIV: 4936*mipsV: 4937*mips32: 4938*mips32r2: 4939*mips64: 4940*mips64r2: 4941*vr4100: 4942*vr5000: 4943{ 4944 do_tgei (SD_, RS, IMMEDIATE, instruction_0); 4945} 4946 4947 4948000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU 4949"tgeiu r<RS>, <IMMEDIATE>" 4950*mipsII: 4951*mipsIII: 4952*mipsIV: 4953*mipsV: 4954*mips32: 4955*mips32r2: 4956*mips64: 4957*mips64r2: 4958*vr4100: 4959*vr5000: 4960{ 4961 do_tgeiu (SD_, RS, IMMEDIATE, instruction_0); 4962} 4963 4964 4965000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU 4966"tgeu r<RS>, r<RT>" 4967*mipsII: 4968*mipsIII: 4969*mipsIV: 4970*mipsV: 4971*mips32: 4972*mips32r2: 4973*mips32r6: 4974*mips64: 4975*mips64r2: 4976*mips64r6: 4977*vr4100: 4978*vr5000: 4979{ 4980 do_tgeu (SD_, RS, RT, instruction_0); 4981} 4982 4983 4984000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT 4985"tlt r<RS>, r<RT>" 4986*mipsII: 4987*mipsIII: 4988*mipsIV: 4989*mipsV: 4990*mips32: 4991*mips32r2: 4992*mips32r6: 4993*mips64: 4994*mips64r2: 4995*mips64r6: 4996*vr4100: 4997*vr5000: 4998{ 4999 do_tlt (SD_, RS, RT, instruction_0); 5000} 5001 5002 5003000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI 5004"tlti r<RS>, <IMMEDIATE>" 5005*mipsII: 5006*mipsIII: 5007*mipsIV: 5008*mipsV: 5009*mips32: 5010*mips32r2: 5011*mips64: 5012*mips64r2: 5013*vr4100: 5014*vr5000: 5015{ 5016 do_tlti (SD_, RS, IMMEDIATE, instruction_0); 5017} 5018 5019 5020000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU 5021"tltiu r<RS>, <IMMEDIATE>" 5022*mipsII: 5023*mipsIII: 5024*mipsIV: 5025*mipsV: 5026*mips32: 5027*mips32r2: 5028*mips64: 5029*mips64r2: 5030*vr4100: 5031*vr5000: 5032{ 5033 do_tltiu (SD_, RS, IMMEDIATE, instruction_0); 5034} 5035 5036 5037000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU 5038"tltu r<RS>, r<RT>" 5039*mipsII: 5040*mipsIII: 5041*mipsIV: 5042*mipsV: 5043*mips32: 5044*mips32r2: 5045*mips32r6: 5046*mips64: 5047*mips64r2: 5048*mips64r6: 5049*vr4100: 5050*vr5000: 5051{ 5052 do_tltu (SD_, RS, RT, instruction_0); 5053} 5054 5055 5056000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE 5057"tne r<RS>, r<RT>" 5058*mipsII: 5059*mipsIII: 5060*mipsIV: 5061*mipsV: 5062*mips32: 5063*mips32r2: 5064*mips32r6: 5065*mips64: 5066*mips64r2: 5067*mips64r6: 5068*vr4100: 5069*vr5000: 5070{ 5071 do_tne (SD_, RS, RT, instruction_0); 5072} 5073 5074 5075000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI 5076"tnei r<RS>, <IMMEDIATE>" 5077*mipsII: 5078*mipsIII: 5079*mipsIV: 5080*mipsV: 5081*mips32: 5082*mips32r2: 5083*mips64: 5084*mips64r2: 5085*vr4100: 5086*vr5000: 5087{ 5088 do_tnei (SD_, RS, IMMEDIATE, instruction_0); 5089} 5090 5091 5092:function:::void:do_xor:int rs, int rt, int rd 5093{ 5094 TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]); 5095 GPR[rd] = GPR[rs] ^ GPR[rt]; 5096 TRACE_ALU_RESULT (GPR[rd]); 5097} 5098 5099000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR 5100"xor r<RD>, r<RS>, r<RT>" 5101*mipsI: 5102*mipsII: 5103*mipsIII: 5104*mipsIV: 5105*mipsV: 5106*mips32: 5107*mips32r2: 5108*mips32r6: 5109*mips64: 5110*mips64r2: 5111*mips64r6: 5112*vr4100: 5113*vr5000: 5114*r3900: 5115{ 5116 do_xor (SD_, RS, RT, RD); 5117} 5118 5119 5120:function:::void:do_xori:int rs, int rt, uint16_t immediate 5121{ 5122 TRACE_ALU_INPUT2 (GPR[rs], immediate); 5123 GPR[rt] = GPR[rs] ^ immediate; 5124 TRACE_ALU_RESULT (GPR[rt]); 5125} 5126 5127001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI 5128"xori r<RT>, r<RS>, %#lx<IMMEDIATE>" 5129*mipsI: 5130*mipsII: 5131*mipsIII: 5132*mipsIV: 5133*mipsV: 5134*mips32: 5135*mips32r2: 5136*mips32r6: 5137*mips64: 5138*mips64r2: 5139*mips64r6: 5140*vr4100: 5141*vr5000: 5142*r3900: 5143{ 5144 do_xori (SD_, RS, RT, IMMEDIATE); 5145} 5146 5147 5148// 5149// MIPS Architecture: 5150// 5151// FPU Instruction Set (COP1 & COP1X) 5152// 5153 5154 5155:%s::::FMT:int fmt 5156{ 5157 switch (fmt) 5158 { 5159 case fmt_single: return "s"; 5160 case fmt_double: return "d"; 5161 case fmt_word: return "w"; 5162 case fmt_long: return "l"; 5163 case fmt_ps: return "ps"; 5164 default: return "?"; 5165 } 5166} 5167 5168:%s::::TF:int tf 5169{ 5170 if (tf) 5171 return "t"; 5172 else 5173 return "f"; 5174} 5175 5176:%s::::ND:int nd 5177{ 5178 if (nd) 5179 return "l"; 5180 else 5181 return ""; 5182} 5183 5184:%s::::COND:int cond 5185{ 5186 switch (cond) 5187 { 5188 case 00: return "f"; 5189 case 01: return "un"; 5190 case 02: return "eq"; 5191 case 03: return "ueq"; 5192 case 04: return "olt"; 5193 case 05: return "ult"; 5194 case 06: return "ole"; 5195 case 07: return "ule"; 5196 case 010: return "sf"; 5197 case 011: return "ngle"; 5198 case 012: return "seq"; 5199 case 013: return "ngl"; 5200 case 014: return "lt"; 5201 case 015: return "nge"; 5202 case 016: return "le"; 5203 case 017: return "ngt"; 5204 default: return "?"; 5205 } 5206} 5207 5208 5209// Helpers: 5210// 5211// Check that the given FPU format is usable, and signal a 5212// ReservedInstruction exception if not. 5213// 5214 5215// check_fmt_p checks that the format is single, double, or paired single. 5216:function:::void:check_fmt_p:int fmt, instruction_word insn 5217*mipsI: 5218*mipsII: 5219*mipsIII: 5220*mipsIV: 5221*mips32: 5222*mips32r6: 5223*mips64r6: 5224*vr4100: 5225*vr5000: 5226*r3900: 5227{ 5228 /* None of these ISAs support Paired Single, so just fall back to 5229 the single/double check. */ 5230 if ((fmt != fmt_single) && (fmt != fmt_double)) 5231 SignalException (ReservedInstruction, insn); 5232} 5233 5234:function:::void:check_fmt_p:int fmt, instruction_word insn 5235*mips32r2: 5236*micromips32: 5237{ 5238 if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps)) 5239 SignalException (ReservedInstruction, insn); 5240} 5241 5242:function:::void:check_fmt_p:int fmt, instruction_word insn 5243*mipsV: 5244*mips64: 5245*mips64r2: 5246*micromips64: 5247{ 5248 if ((fmt != fmt_single) && (fmt != fmt_double) 5249 && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0))) 5250 SignalException (ReservedInstruction, insn); 5251} 5252 5253 5254// Helper: 5255// 5256// Check that the FPU is currently usable, and signal a CoProcessorUnusable 5257// exception if not. 5258// 5259 5260:function:::void:check_fpu: 5261*mipsI: 5262*mipsII: 5263*mipsIII: 5264*mipsIV: 5265*mipsV: 5266*mips32: 5267*mips32r2: 5268*mips64: 5269*mips64r2: 5270*vr4100: 5271*vr5000: 5272*r3900: 5273*micromips32: 5274*micromips64: 5275{ 5276 if (! COP_Usable (1)) 5277 SignalExceptionCoProcessorUnusable (1); 5278 5279 FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask); 5280 sim_fpu_quiet_nan_inverted = true; 5281} 5282 5283// Helper: 5284// 5285// Check that the FPU is currently usable, and signal a CoProcessorUnusable 5286// exception if not. 5287// 5288 5289:function:::void:check_fpu: 5290*mips32r6: 5291*mips64r6: 5292{ 5293 if (! COP_Usable (1)) 5294 SignalExceptionCoProcessorUnusable (1); 5295 5296 FCSR |= (fcsr_NAN2008_mask | fcsr_ABS2008_mask); 5297 sim_fpu_quiet_nan_inverted = 0; 5298 sim_fpu_set_mode (sim_fpu_ieee754_2008); 5299} 5300 5301// Helper: 5302// 5303// Load a double word FP value using 2 32-bit memory cycles a la MIPS II 5304// or MIPS32. do_load cannot be used instead because it returns an 5305// unsigned_word, which is limited to the size of the machine's registers. 5306// 5307 5308:function:::uint64_t:do_load_double:address_word base, address_word offset 5309*mipsII: 5310*mips32: 5311*mips32r2: 5312*mips32r6: 5313*micromips32: 5314{ 5315 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 5316 address_word vaddr; 5317 address_word paddr; 5318 uint64_t memval; 5319 uint64_t v; 5320 5321 paddr = vaddr = loadstore_ea (SD_, base, offset); 5322 if ((vaddr & AccessLength_DOUBLEWORD) != 0) 5323 { 5324 SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, 5325 AccessLength_DOUBLEWORD + 1, vaddr, read_transfer, 5326 sim_core_unaligned_signal); 5327 } 5328 LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL); 5329 v = (uint64_t)memval; 5330 LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA, 5331 isREAL); 5332 return (bigendian ? ((v << 32) | memval) : (v | (memval << 32))); 5333} 5334 5335 5336// Helper: 5337// 5338// Store a double word FP value using 2 32-bit memory cycles a la MIPS II 5339// or MIPS32. do_load cannot be used instead because it returns an 5340// unsigned_word, which is limited to the size of the machine's registers. 5341// 5342 5343:function:::void:do_store_double:address_word base, address_word offset, uint64_t v 5344*mipsII: 5345*mips32: 5346*mips32r2: 5347*micromips32: 5348 *mips32r6: 5349{ 5350 int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian); 5351 address_word vaddr; 5352 address_word paddr; 5353 uint64_t memval; 5354 5355 paddr = vaddr = loadstore_ea (SD_, base, offset); 5356 if ((vaddr & AccessLength_DOUBLEWORD) != 0) 5357 { 5358 SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, 5359 AccessLength_DOUBLEWORD + 1, vaddr, write_transfer, 5360 sim_core_unaligned_signal); 5361 } 5362 memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF)); 5363 StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL); 5364 memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32)); 5365 StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL); 5366} 5367 5368 5369010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt 5370"abs.%s<FMT> f<FD>, f<FS>" 5371*mipsI: 5372*mipsII: 5373*mipsIII: 5374*mipsIV: 5375*mipsV: 5376*mips32: 5377*mips32r2: 5378*mips32r6: 5379*mips64: 5380*mips64r2: 5381*mips64r6: 5382*vr4100: 5383*vr5000: 5384*r3900: 5385{ 5386 do_abs_fmt (SD_, FMT, FD, FS, instruction_0); 5387} 5388 5389 5390 5391010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt 5392"add.%s<FMT> f<FD>, f<FS>, f<FT>" 5393*mipsI: 5394*mipsII: 5395*mipsIII: 5396*mipsIV: 5397*mipsV: 5398*mips32: 5399*mips32r2: 5400*mips32r6: 5401*mips64: 5402*mips64r2: 5403*mips64r6: 5404*vr4100: 5405*vr5000: 5406*r3900: 5407{ 5408 do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0); 5409} 5410 5411 5412010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS 5413"alnv.ps f<FD>, f<FS>, f<FT>, r<RS>" 5414*mipsV: 5415*mips32r2: 5416*mips64: 5417*mips64r2: 5418{ 5419 do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0); 5420} 5421 5422 5423// BC1F 5424// BC1FL 5425// BC1T 5426// BC1TL 5427 5428010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a 5429"bc1%s<TF>%s<ND> <OFFSET>" 5430*mipsI: 5431*mipsII: 5432*mipsIII: 5433{ 5434 check_fpu (SD_); 5435 TRACE_BRANCH_INPUT (PREVCOC1()); 5436 if (PREVCOC1() == TF) 5437 { 5438 address_word dest = NIA + (EXTEND16 (OFFSET) << 2); 5439 TRACE_BRANCH_RESULT (dest); 5440 DELAY_SLOT (dest); 5441 } 5442 else if (ND) 5443 { 5444 TRACE_BRANCH_RESULT (0); 5445 NULLIFY_NEXT_INSTRUCTION (); 5446 } 5447 else 5448 { 5449 TRACE_BRANCH_RESULT (NIA); 5450 } 5451} 5452 5453010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b 5454"bc1%s<TF>%s<ND> <OFFSET>":CC == 0 5455"bc1%s<TF>%s<ND> <CC>, <OFFSET>" 5456*mipsIV: 5457*mipsV: 5458*mips32: 5459*mips32r2: 5460*mips64: 5461*mips64r2: 5462#*vr4100: 5463*vr5000: 5464*r3900: 5465{ 5466 check_fpu (SD_); 5467 if (GETFCC(CC) == TF) 5468 { 5469 address_word dest = NIA + (EXTEND16 (OFFSET) << 2); 5470 DELAY_SLOT (dest); 5471 } 5472 else if (ND) 5473 { 5474 NULLIFY_NEXT_INSTRUCTION (); 5475 } 5476} 5477 5478 5479010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta 5480"c.%s<COND>.%s<FMT> f<FS>, f<FT>" 5481*mipsI: 5482*mipsII: 5483*mipsIII: 5484{ 5485 int fmt = FMT; 5486 check_fpu (SD_); 5487 Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0); 5488 TRACE_ALU_RESULT (ValueFCR (31)); 5489} 5490 5491010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb 5492"c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0 5493"c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>" 5494*mipsIV: 5495*mipsV: 5496*mips32: 5497*mips32r2: 5498*mips64: 5499*mips64r2: 5500*vr4100: 5501*vr5000: 5502*r3900: 5503{ 5504 do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0); 5505} 5506 5507 5508010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt 5509"ceil.l.%s<FMT> f<FD>, f<FS>" 5510*mipsIII: 5511*mipsIV: 5512*mipsV: 5513*mips32r2: 5514*mips32r6: 5515*mips64: 5516*mips64r2: 5517*mips64r6: 5518*vr4100: 5519*vr5000: 5520*r3900: 5521{ 5522 do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0); 5523} 5524 5525 5526010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W 5527"ceil.w.%s<FMT> f<FD>, f<FS>" 5528*mipsII: 5529*mipsIII: 5530*mipsIV: 5531*mipsV: 5532*mips32: 5533*mips32r2: 5534*mips32r6: 5535*mips64: 5536*mips64r2: 5537*mips64r6: 5538*vr4100: 5539*vr5000: 5540*r3900: 5541{ 5542 do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0); 5543} 5544 5545 5546010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a 5547"cfc1 r<RT>, f<FS>" 5548*mipsI: 5549*mipsII: 5550*mipsIII: 5551{ 5552 check_fpu (SD_); 5553 if (FS == 0) 5554 PENDING_FILL (RT, EXTEND32 (FCR0)); 5555 else if (FS == 31) 5556 PENDING_FILL (RT, EXTEND32 (FCR31)); 5557 /* else NOP */ 5558} 5559 5560010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b 5561"cfc1 r<RT>, f<FS>" 5562*mipsIV: 5563*vr4100: 5564*vr5000: 5565*r3900: 5566{ 5567 check_fpu (SD_); 5568 if (FS == 0 || FS == 31) 5569 { 5570 unsigned_word fcr = ValueFCR (FS); 5571 TRACE_ALU_INPUT1 (fcr); 5572 GPR[RT] = fcr; 5573 } 5574 /* else NOP */ 5575 TRACE_ALU_RESULT (GPR[RT]); 5576} 5577 5578010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c 5579"cfc1 r<RT>, f<FS>" 5580*mipsV: 5581*mips32: 5582*mips32r2: 5583*mips32r6: 5584*mips64: 5585*mips64r2: 5586*mips64r6: 5587{ 5588 do_cfc1 (SD_, RT, FS); 5589} 5590 5591010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a 5592"ctc1 r<RT>, f<FS>" 5593*mipsI: 5594*mipsII: 5595*mipsIII: 5596{ 5597 check_fpu (SD_); 5598 if (FS == 31) 5599 PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT])); 5600 /* else NOP */ 5601} 5602 5603010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b 5604"ctc1 r<RT>, f<FS>" 5605*mipsIV: 5606*vr4100: 5607*vr5000: 5608*r3900: 5609{ 5610 check_fpu (SD_); 5611 TRACE_ALU_INPUT1 (GPR[RT]); 5612 if (FS == 31) 5613 StoreFCR (FS, GPR[RT]); 5614 /* else NOP */ 5615} 5616 5617010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c 5618"ctc1 r<RT>, f<FS>" 5619*mipsV: 5620*mips32: 5621*mips32r2: 5622*mips32r6: 5623*mips64: 5624*mips64r2: 5625*mips64r6: 5626{ 5627 do_ctc1 (SD_, RT, FS); 5628} 5629 5630 5631// 5632// FIXME: Does not correctly differentiate between mips* 5633// 5634010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt 5635"cvt.d.%s<FMT> f<FD>, f<FS>" 5636*mipsI: 5637*mipsII: 5638*mipsIII: 5639*mipsIV: 5640*mipsV: 5641*mips32: 5642*mips32r2: 5643*mips32r6: 5644*mips64: 5645*mips64r2: 5646*mips64r6: 5647*vr4100: 5648*vr5000: 5649*r3900: 5650{ 5651 do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0); 5652} 5653 5654 5655010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt 5656"cvt.l.%s<FMT> f<FD>, f<FS>" 5657*mipsIII: 5658*mipsIV: 5659*mipsV: 5660*mips32r2: 5661*mips32r6: 5662*mips64: 5663*mips64r2: 5664*mips64r6: 5665*vr4100: 5666*vr5000: 5667*r3900: 5668{ 5669 do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0); 5670} 5671 5672 5673010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S 5674"cvt.ps.s f<FD>, f<FS>, f<FT>" 5675*mipsV: 5676*mips32r2: 5677*mips64: 5678*mips64r2: 5679{ 5680 do_cvt_ps_s (SD_, FD, FS, FT, instruction_0); 5681} 5682 5683 5684// 5685// FIXME: Does not correctly differentiate between mips* 5686// 5687010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt 5688"cvt.s.%s<FMT> f<FD>, f<FS>" 5689*mipsI: 5690*mipsII: 5691*mipsIII: 5692*mipsIV: 5693*mipsV: 5694*mips32: 5695*mips32r2: 5696*mips32r6: 5697*mips64: 5698*mips64r2: 5699*mips64r6: 5700*vr4100: 5701*vr5000: 5702*r3900: 5703{ 5704 do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0); 5705} 5706 5707 5708010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL 5709"cvt.s.pl f<FD>, f<FS>" 5710*mipsV: 5711*mips32r2: 5712*mips64: 5713*mips64r2: 5714{ 5715 do_cvt_s_pl (SD_, FD, FS, instruction_0); 5716} 5717 5718 5719010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU 5720"cvt.s.pu f<FD>, f<FS>" 5721*mipsV: 5722*mips32r2: 5723*mips64: 5724*mips64r2: 5725{ 5726 do_cvt_s_pu (SD_, FD, FS, instruction_0); 5727} 5728 5729 5730010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt 5731"cvt.w.%s<FMT> f<FD>, f<FS>" 5732*mipsI: 5733*mipsII: 5734*mipsIII: 5735*mipsIV: 5736*mipsV: 5737*mips32: 5738*mips32r2: 5739*mips32r6: 5740*mips64: 5741*mips64r2: 5742*mips64r6: 5743*vr4100: 5744*vr5000: 5745*r3900: 5746{ 5747 do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0); 5748} 5749 5750 5751010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt 5752"div.%s<FMT> f<FD>, f<FS>, f<FT>" 5753*mipsI: 5754*mipsII: 5755*mipsIII: 5756*mipsIV: 5757*mipsV: 5758*mips32: 5759*mips32r2: 5760*mips32r6: 5761*mips64: 5762*mips64r2: 5763*mips64r6: 5764*vr4100: 5765*vr5000: 5766*r3900: 5767{ 5768 do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0); 5769} 5770 5771 5772010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a 5773"dmfc1 r<RT>, f<FS>" 5774*mipsIII: 5775{ 5776 uint64_t v; 5777 check_fpu (SD_); 5778 check_u64 (SD_, instruction_0); 5779 if (SizeFGR () == 64) 5780 v = FGR[FS]; 5781 else if ((FS & 0x1) == 0) 5782 v = SET64HI (FGR[FS+1]) | FGR[FS]; 5783 else 5784 Unpredictable (); 5785 PENDING_FILL (RT, v); 5786 TRACE_ALU_RESULT (v); 5787} 5788 5789010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b 5790"dmfc1 r<RT>, f<FS>" 5791*mipsIV: 5792*mipsV: 5793*mips64: 5794*mips64r2: 5795*mips64r6: 5796*vr4100: 5797*vr5000: 5798*r3900: 5799{ 5800 check_fpu (SD_); 5801 check_u64 (SD_, instruction_0); 5802 do_dmfc1b (SD_, RT, FS); 5803} 5804 5805 5806010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a 5807"dmtc1 r<RT>, f<FS>" 5808*mipsIII: 5809{ 5810 uint64_t v; 5811 check_fpu (SD_); 5812 check_u64 (SD_, instruction_0); 5813 if (SizeFGR () == 64) 5814 PENDING_FILL ((FS + FGR_BASE), GPR[RT]); 5815 else if ((FS & 0x1) == 0) 5816 { 5817 PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT])); 5818 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); 5819 } 5820 else 5821 Unpredictable (); 5822 TRACE_FP_RESULT (GPR[RT]); 5823} 5824 5825010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b 5826"dmtc1 r<RT>, f<FS>" 5827*mipsIV: 5828*mipsV: 5829*mips64: 5830*mips64r2: 5831*mips64r6: 5832*vr4100: 5833*vr5000: 5834*r3900: 5835{ 5836 check_fpu (SD_); 5837 check_u64 (SD_, instruction_0); 5838 do_dmtc1b (SD_, RT, FS); 5839} 5840 5841 5842010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt 5843"floor.l.%s<FMT> f<FD>, f<FS>" 5844*mipsIII: 5845*mipsIV: 5846*mipsV: 5847*mips32r2: 5848*mips32r6: 5849*mips64: 5850*mips64r2: 5851*mips64r6: 5852*vr4100: 5853*vr5000: 5854*r3900: 5855{ 5856 do_floor_fmt (SD_, fmt_long, FMT, FD, FS); 5857} 5858 5859 5860010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt 5861"floor.w.%s<FMT> f<FD>, f<FS>" 5862*mipsII: 5863*mipsIII: 5864*mipsIV: 5865*mipsV: 5866*mips32: 5867*mips32r2: 5868*mips32r6: 5869*mips64: 5870*mips64r2: 5871*mips64r6: 5872*vr4100: 5873*vr5000: 5874*r3900: 5875{ 5876 do_floor_fmt (SD_, fmt_word, FMT, FD, FS); 5877} 5878 5879 5880110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a 5881"ldc1 f<FT>, <OFFSET>(r<BASE>)" 5882*mipsII: 5883*mips32: 5884*mips32r2: 5885*mips32r6: 5886{ 5887 check_fpu (SD_); 5888 COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET))); 5889} 5890 5891 5892110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b 5893"ldc1 f<FT>, <OFFSET>(r<BASE>)" 5894*mipsIII: 5895*mipsIV: 5896*mipsV: 5897*mips64: 5898*mips64r2: 5899*mips64r6: 5900*vr4100: 5901*vr5000: 5902*r3900: 5903{ 5904 check_fpu (SD_); 5905 COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); 5906} 5907 5908 5909010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1 5910"ldxc1 f<FD>, r<INDEX>(r<BASE>)" 5911*mips32r2: 5912{ 5913 check_fpu (SD_); 5914 COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX])); 5915} 5916 5917 5918010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1 5919"ldxc1 f<FD>, r<INDEX>(r<BASE>)" 5920*mipsIV: 5921*mipsV: 5922*mips64: 5923*mips64r2: 5924*vr5000: 5925{ 5926 check_fpu (SD_); 5927 check_u64 (SD_, instruction_0); 5928 COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX])); 5929} 5930 5931 5932010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1 5933"luxc1 f<FD>, r<INDEX>(r<BASE>)" 5934*mips32r2: 5935{ 5936 do_luxc1_32 (SD_, FD, INDEX, BASE); 5937} 5938 5939 5940010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1 5941"luxc1 f<FD>, r<INDEX>(r<BASE>)" 5942*mipsV: 5943*mips64: 5944*mips64r2: 5945{ 5946 check_fpu (SD_); 5947 check_u64 (SD_, instruction_0); 5948 do_luxc1_64 (SD_, FD, INDEX, BASE); 5949} 5950 5951 5952110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1 5953"lwc1 f<FT>, <OFFSET>(r<BASE>)" 5954*mipsI: 5955*mipsII: 5956*mipsIII: 5957*mipsIV: 5958*mipsV: 5959*mips32: 5960*mips32r2: 5961*mips32r6: 5962*mips64: 5963*mips64r2: 5964*mips64r6: 5965*vr4100: 5966*vr5000: 5967*r3900: 5968{ 5969 do_lwc1 (SD_, FT, OFFSET, BASE); 5970} 5971 5972 5973010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1 5974"lwxc1 f<FD>, r<INDEX>(r<BASE>)" 5975*mipsIV: 5976*mipsV: 5977*mips32r2: 5978*mips64: 5979*mips64r2: 5980*vr5000: 5981{ 5982 do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0); 5983} 5984 5985 5986 5987010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt 5988"madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 5989*mipsIV: 5990*mipsV: 5991*mips32r2: 5992*mips64: 5993*mips64r2: 5994*vr5000: 5995{ 5996 do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); 5997} 5998 5999 6000010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a 6001"mfc1 r<RT>, f<FS>" 6002*mipsI: 6003*mipsII: 6004*mipsIII: 6005{ 6006 uint64_t v; 6007 check_fpu (SD_); 6008 v = EXTEND32 (FGR[FS]); 6009 PENDING_FILL (RT, v); 6010 TRACE_ALU_RESULT (v); 6011} 6012 6013010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b 6014"mfc1 r<RT>, f<FS>" 6015*mipsIV: 6016*mipsV: 6017*mips32: 6018*mips32r2: 6019*mips32r6: 6020*mips64: 6021*mips64r2: 6022*mips64r6: 6023*vr4100: 6024*vr5000: 6025*r3900: 6026{ 6027 do_mfc1b (SD_, RT, FS); 6028} 6029 6030 6031010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt 6032"mov.%s<FMT> f<FD>, f<FS>" 6033*mipsI: 6034*mipsII: 6035*mipsIII: 6036*mipsIV: 6037*mipsV: 6038*mips32: 6039*mips32r2: 6040*mips32r6: 6041*mips64: 6042*mips64r2: 6043*mips64r6: 6044*vr4100: 6045*vr5000: 6046*r3900: 6047{ 6048 do_mov_fmt (SD_, FMT, FD, FS, instruction_0); 6049} 6050 6051 6052// MOVF 6053// MOVT 6054000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf 6055"mov%s<TF> r<RD>, r<RS>, <CC>" 6056*mipsIV: 6057*mipsV: 6058*mips32: 6059*mips32r2: 6060*mips64: 6061*mips64r2: 6062*vr5000: 6063{ 6064 do_movtf (SD_, TF, RD, RS, CC); 6065} 6066 6067 6068// MOVF.fmt 6069// MOVT.fmt 6070010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt 6071"mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>" 6072*mipsIV: 6073*mipsV: 6074*mips32: 6075*mips32r2: 6076*mips64: 6077*mips64r2: 6078*vr5000: 6079{ 6080 do_movtf_fmt (SD_, TF, FMT, FD, FS, CC); 6081} 6082 6083 6084010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt 6085"movn.%s<FMT> f<FD>, f<FS>, r<RT>" 6086*mipsIV: 6087*mipsV: 6088*mips32: 6089*mips32r2: 6090*mips64: 6091*mips64r2: 6092*vr5000: 6093{ 6094 do_movn_fmt (SD_, FMT, FD, FS, RT); 6095} 6096 6097 6098// MOVT see MOVtf 6099 6100 6101// MOVT.fmt see MOVtf.fmt 6102 6103 6104 6105010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt 6106"movz.%s<FMT> f<FD>, f<FS>, r<RT>" 6107*mipsIV: 6108*mipsV: 6109*mips32: 6110*mips32r2: 6111*mips64: 6112*mips64r2: 6113*vr5000: 6114{ 6115 do_movz_fmt (SD_, FMT, FD, FS, RT); 6116} 6117 6118 6119010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt 6120"msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 6121*mipsIV: 6122*mipsV: 6123*mips32r2: 6124*mips64: 6125*mips64r2: 6126*vr5000: 6127{ 6128 do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); 6129} 6130 6131 6132010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a 6133"mtc1 r<RT>, f<FS>" 6134*mipsI: 6135*mipsII: 6136*mipsIII: 6137{ 6138 check_fpu (SD_); 6139 if (SizeFGR () == 64) 6140 PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT]))); 6141 else 6142 PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT])); 6143 TRACE_FP_RESULT (GPR[RT]); 6144} 6145 6146010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b 6147"mtc1 r<RT>, f<FS>" 6148*mipsIV: 6149*mipsV: 6150*mips32: 6151*mips32r2: 6152*mips32r6: 6153*mips64: 6154*mips64r2: 6155*mips64r6: 6156*vr4100: 6157*vr5000: 6158*r3900: 6159{ 6160 do_mtc1b (SD_, RT, FS); 6161} 6162 6163 6164010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt 6165"mul.%s<FMT> f<FD>, f<FS>, f<FT>" 6166*mipsI: 6167*mipsII: 6168*mipsIII: 6169*mipsIV: 6170*mipsV: 6171*mips32: 6172*mips32r2: 6173*mips32r6: 6174*mips64: 6175*mips64r2: 6176*mips64r6: 6177*vr4100: 6178*vr5000: 6179*r3900: 6180{ 6181 do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0); 6182} 6183 6184 6185010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt 6186"neg.%s<FMT> f<FD>, f<FS>" 6187*mipsI: 6188*mipsII: 6189*mipsIII: 6190*mipsIV: 6191*mipsV: 6192*mips32: 6193*mips32r2: 6194*mips32r6: 6195*mips64: 6196*mips64r2: 6197*mips64r6: 6198*vr4100: 6199*vr5000: 6200*r3900: 6201{ 6202 do_neg_fmt (SD_, FMT, FD, FS, instruction_0); 6203} 6204 6205 6206010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt 6207"nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 6208*mipsIV: 6209*mipsV: 6210*mips32r2: 6211*mips64: 6212*mips64r2: 6213*vr5000: 6214{ 6215 do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); 6216} 6217 6218 6219010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt 6220"nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>" 6221*mipsIV: 6222*mipsV: 6223*mips32r2: 6224*mips64: 6225*mips64r2: 6226*vr5000: 6227{ 6228 do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0); 6229} 6230 6231 6232010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS 6233"pll.ps f<FD>, f<FS>, f<FT>" 6234*mipsV: 6235*mips32r2: 6236*mips64: 6237*mips64r2: 6238{ 6239 do_pll_ps (SD_, FD, FS, FT, instruction_0); 6240} 6241 6242 6243010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS 6244"plu.ps f<FD>, f<FS>, f<FT>" 6245*mipsV: 6246*mips32r2: 6247*mips64: 6248*mips64r2: 6249{ 6250 do_plu_ps (SD_, FD, FS, FT, instruction_0); 6251} 6252 6253 6254010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX 6255"prefx <HINT>, r<INDEX>(r<BASE>)" 6256*mipsIV: 6257*mipsV: 6258*mips32r2: 6259*mips64: 6260*mips64r2: 6261*vr5000: 6262{ 6263 do_prefx (SD_, HINT, INDEX, BASE); 6264} 6265 6266 6267010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS 6268"pul.ps f<FD>, f<FS>, f<FT>" 6269*mipsV: 6270*mips32r2: 6271*mips64: 6272*mips64r2: 6273{ 6274 do_pul_ps (SD_, FD, FS, FT, instruction_0); 6275} 6276 6277 6278010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS 6279"puu.ps f<FD>, f<FS>, f<FT>" 6280*mipsV: 6281*mips32r2: 6282*mips64: 6283*mips64r2: 6284{ 6285 do_puu_ps (SD_, FD, FS, FT, instruction_0); 6286} 6287 6288 6289010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt 6290"recip.%s<FMT> f<FD>, f<FS>" 6291*mipsIV: 6292*mipsV: 6293*mips32r2: 6294*mips32r6: 6295*mips64: 6296*mips64r2: 6297*mips64r6: 6298*vr5000: 6299{ 6300 do_recip_fmt (SD_, FMT, FD, FS); 6301} 6302 6303 6304010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt 6305"round.l.%s<FMT> f<FD>, f<FS>" 6306*mipsIII: 6307*mipsIV: 6308*mipsV: 6309*mips32r2: 6310*mips32r6: 6311*mips64: 6312*mips64r2: 6313*mips64r6: 6314*vr4100: 6315*vr5000: 6316*r3900: 6317{ 6318 do_round_fmt (SD_, fmt_long, FMT, FD, FS); 6319} 6320 6321 6322010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt 6323"round.w.%s<FMT> f<FD>, f<FS>" 6324*mipsII: 6325*mipsIII: 6326*mipsIV: 6327*mipsV: 6328*mips32: 6329*mips32r2: 6330*mips32r6: 6331*mips64: 6332*mips64r2: 6333*mips64r6: 6334*vr4100: 6335*vr5000: 6336*r3900: 6337{ 6338 do_round_fmt (SD_, fmt_word, FMT, FD, FS); 6339} 6340 6341 6342010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt 6343"rsqrt.%s<FMT> f<FD>, f<FS>" 6344*mipsIV: 6345*mipsV: 6346*mips32r2: 6347*mips32r6: 6348*mips64: 6349*mips64r2: 6350*mips64r6: 6351*vr5000: 6352{ 6353 do_rsqrt_fmt (SD_, FMT, FD, FS); 6354} 6355 6356 6357111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a 6358"sdc1 f<FT>, <OFFSET>(r<BASE>)" 6359*mipsII: 6360*mips32: 6361*mips32r2: 6362*mips32r6: 6363{ 6364 do_sdc1 (SD_, FT, OFFSET, BASE); 6365} 6366 6367 6368111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b 6369"sdc1 f<FT>, <OFFSET>(r<BASE>)" 6370*mipsIII: 6371*mipsIV: 6372*mipsV: 6373*mips64: 6374*mips64r2: 6375*mips64r6: 6376*vr4100: 6377*vr5000: 6378*r3900: 6379{ 6380 check_fpu (SD_); 6381 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT)); 6382} 6383 6384 6385010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1 6386"sdxc1 f<FS>, r<INDEX>(r<BASE>)" 6387*mips32r2: 6388{ 6389 check_fpu (SD_); 6390 do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); 6391} 6392 6393 6394010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1 6395"sdxc1 f<FS>, r<INDEX>(r<BASE>)" 6396*mipsIV: 6397*mipsV: 6398*mips64: 6399*mips64r2: 6400*vr5000: 6401{ 6402 check_fpu (SD_); 6403 check_u64 (SD_, instruction_0); 6404 do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS)); 6405} 6406 6407 6408010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1 6409"suxc1 f<FS>, r<INDEX>(r<BASE>)" 6410*mips32r2: 6411{ 6412 do_suxc1_32 (SD_, FS, INDEX, BASE); 6413} 6414 6415 6416010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1 6417"suxc1 f<FS>, r<INDEX>(r<BASE>)" 6418*mipsV: 6419*mips64: 6420*mips64r2: 6421{ 6422 check_fpu (SD_); 6423 check_u64 (SD_, instruction_0); 6424 do_suxc1_64 (SD_, FS, INDEX, BASE); 6425} 6426 6427 6428010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt 6429"sqrt.%s<FMT> f<FD>, f<FS>" 6430*mipsII: 6431*mipsIII: 6432*mipsIV: 6433*mipsV: 6434*mips32: 6435*mips32r2: 6436*mips32r6: 6437*mips64: 6438*mips64r2: 6439*mips64r6: 6440*vr4100: 6441*vr5000: 6442*r3900: 6443{ 6444 do_sqrt_fmt (SD_, FMT, FD, FS); 6445} 6446 6447 6448010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt 6449"sub.%s<FMT> f<FD>, f<FS>, f<FT>" 6450*mipsI: 6451*mipsII: 6452*mipsIII: 6453*mipsIV: 6454*mipsV: 6455*mips32: 6456*mips32r2: 6457*mips32r6: 6458*mips64: 6459*mips64r2: 6460*mips64r6: 6461*vr4100: 6462*vr5000: 6463*r3900: 6464{ 6465 do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0); 6466} 6467 6468 6469 6470111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1 6471"swc1 f<FT>, <OFFSET>(r<BASE>)" 6472*mipsI: 6473*mipsII: 6474*mipsIII: 6475*mipsIV: 6476*mipsV: 6477*mips32: 6478*mips32r2: 6479*mips32r6: 6480*mips64: 6481*mips64r2: 6482*mips64r6: 6483*vr4100: 6484*vr5000: 6485*r3900: 6486{ 6487 do_swc1 (SD_, FT, OFFSET, BASE, instruction_0); 6488} 6489 6490 6491010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1 6492"swxc1 f<FS>, r<INDEX>(r<BASE>)" 6493*mipsIV: 6494*mipsV: 6495*mips32r2: 6496*mips64: 6497*mips64r2: 6498*vr5000: 6499{ 6500 do_swxc1 (SD_, FS, INDEX, BASE, instruction_0); 6501} 6502 6503 6504010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt 6505"trunc.l.%s<FMT> f<FD>, f<FS>" 6506*mipsIII: 6507*mipsIV: 6508*mipsV: 6509*mips32r2: 6510*mips32r6: 6511*mips64: 6512*mips64r2: 6513*mips64r6: 6514*vr4100: 6515*vr5000: 6516*r3900: 6517{ 6518 do_trunc_fmt (SD_, fmt_long, FMT, FD, FS); 6519} 6520 6521 6522010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W 6523"trunc.w.%s<FMT> f<FD>, f<FS>" 6524*mipsII: 6525*mipsIII: 6526*mipsIV: 6527*mipsV: 6528*mips32: 6529*mips32r2: 6530*mips32r6: 6531*mips64: 6532*mips64r2: 6533*mips64r6: 6534*vr4100: 6535*vr5000: 6536*r3900: 6537{ 6538 do_trunc_fmt (SD_, fmt_word, FMT, FD, FS); 6539} 6540 6541 6542// 6543// MIPS Architecture: 6544// 6545// System Control Instruction Set (COP0) 6546// 6547 6548 6549010000,01000,00000,16.OFFSET:COP0:32::BC0F 6550"bc0f <OFFSET>" 6551*mipsI: 6552*mipsII: 6553*mipsIII: 6554*mipsIV: 6555*mipsV: 6556*mips32: 6557*mips32r2: 6558*mips32r6: 6559*mips64: 6560*mips64r2: 6561*mips64r6: 6562*vr4100: 6563*vr5000: 6564 6565010000,01000,00000,16.OFFSET:COP0:32::BC0F 6566"bc0f <OFFSET>" 6567// stub needed for eCos as tx39 hardware bug workaround 6568*r3900: 6569{ 6570 /* do nothing */ 6571} 6572 6573 6574010000,01000,00010,16.OFFSET:COP0:32::BC0FL 6575"bc0fl <OFFSET>" 6576*mipsI: 6577*mipsII: 6578*mipsIII: 6579*mipsIV: 6580*mipsV: 6581*mips32: 6582*mips32r2: 6583*mips32r6: 6584*mips64: 6585*mips64r2: 6586*mips64r6: 6587*vr4100: 6588*vr5000: 6589 6590 6591010000,01000,00001,16.OFFSET:COP0:32::BC0T 6592"bc0t <OFFSET>" 6593*mipsI: 6594*mipsII: 6595*mipsIII: 6596*mipsIV: 6597*mipsV: 6598*mips32: 6599*mips32r2: 6600*mips32r6: 6601*mips64: 6602*mips64r2: 6603*mips64r6: 6604*vr4100: 6605 6606 6607010000,01000,00011,16.OFFSET:COP0:32::BC0TL 6608"bc0tl <OFFSET>" 6609*mipsI: 6610*mipsII: 6611*mipsIII: 6612*mipsIV: 6613*mipsV: 6614*mips32: 6615*mips32r2: 6616*mips32r6: 6617*mips64: 6618*mips64r2: 6619*mips64r6: 6620*vr4100: 6621*vr5000: 6622 6623:function:::void:do_cache:int op, int rbase, int roffset, address_word instruction_0 6624{ 6625 address_word base = GPR[rbase]; 6626 address_word offset = EXTEND16 (roffset); 6627 { 6628 address_word vaddr = loadstore_ea (SD_, base, offset); 6629 address_word paddr = vaddr; 6630 CacheOp(op, vaddr, paddr, instruction_0); 6631 } 6632} 6633 6634101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE 6635"cache <OP>, <OFFSET>(r<BASE>)" 6636*mipsIII: 6637*mipsIV: 6638*mipsV: 6639*mips32: 6640*mips32r2: 6641*mips64: 6642*mips64r2: 6643*vr4100: 6644*vr5000: 6645*r3900: 6646{ 6647 do_cache (SD_, OP, BASE, OFFSET, instruction_0); 6648} 6649 6650 6651010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0 6652"dmfc0 r<RT>, r<RD>" 6653*mipsIII: 6654*mipsIV: 6655*mipsV: 6656*mips64: 6657*mips64r2: 6658*mips64r6: 6659{ 6660 check_u64 (SD_, instruction_0); 6661 DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL); 6662} 6663 6664 6665010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0 6666"dmtc0 r<RT>, r<RD>" 6667*mipsIII: 6668*mipsIV: 6669*mipsV: 6670*mips64: 6671*mips64r2: 6672*mips64r6: 6673{ 6674 check_u64 (SD_, instruction_0); 6675 DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL); 6676} 6677 6678 6679010000,1,0000000000000000000,011000:COP0:32::ERET 6680"eret" 6681*mipsIII: 6682*mipsIV: 6683*mipsV: 6684*mips32: 6685*mips32r2: 6686*mips32r6: 6687*mips64: 6688*mips64r2: 6689*mips64r6: 6690*vr4100: 6691*vr5000: 6692{ 6693 if (SR & status_ERL) 6694 { 6695 /* Oops, not yet available */ 6696 sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported"); 6697 NIA = EPC; 6698 SR &= ~status_ERL; 6699 } 6700 else 6701 { 6702 NIA = EPC; 6703 SR &= ~status_EXL; 6704 } 6705} 6706 6707 6708010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0 6709"mfc0 r<RT>, r<RD> # <SEL>" 6710*mipsI: 6711*mipsII: 6712*mipsIII: 6713*mipsIV: 6714*mipsV: 6715*mips32: 6716*mips32r2: 6717*mips32r6: 6718*mips64: 6719*mips64r2: 6720*mips64r6: 6721*vr4100: 6722*vr5000: 6723*r3900: 6724{ 6725 TRACE_ALU_INPUT0 (); 6726 DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL); 6727 TRACE_ALU_RESULT (GPR[RT]); 6728} 6729 6730010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0 6731"mtc0 r<RT>, r<RD> # <SEL>" 6732*mipsI: 6733*mipsII: 6734*mipsIII: 6735*mipsIV: 6736*mipsV: 6737*mips32: 6738*mips32r2: 6739*mips32r6: 6740*mips64: 6741*mips64r2: 6742*mips64r6: 6743*vr4100: 6744*vr5000: 6745*r3900: 6746{ 6747 DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL); 6748} 6749 6750 6751010000,1,0000000000000000000,010000:COP0:32::RFE 6752"rfe" 6753*mipsI: 6754*mipsII: 6755*mipsIII: 6756*mipsIV: 6757*mipsV: 6758*vr4100: 6759*vr5000: 6760*r3900: 6761{ 6762 DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10); 6763} 6764 6765 67660100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz 6767"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>" 6768*mipsI: 6769*mipsII: 6770*mipsIII: 6771*mipsIV: 6772*mipsV: 6773*mips32: 6774*mips32r2: 6775*mips32r6: 6776*mips64: 6777*mips64r2: 6778*mips64r6: 6779*vr4100: 6780*r3900: 6781{ 6782 DecodeCoproc (instruction_0, 2, 0, 0, 0, 0); 6783} 6784 6785 6786 6787010000,1,0000000000000000000,001000:COP0:32::TLBP 6788"tlbp" 6789*mipsI: 6790*mipsII: 6791*mipsIII: 6792*mipsIV: 6793*mipsV: 6794*mips32: 6795*mips32r2: 6796*mips32r6: 6797*mips64: 6798*mips64r2: 6799*mips64r6: 6800*vr4100: 6801*vr5000: 6802 6803 6804010000,1,0000000000000000000,000001:COP0:32::TLBR 6805"tlbr" 6806*mipsI: 6807*mipsII: 6808*mipsIII: 6809*mipsIV: 6810*mipsV: 6811*mips32: 6812*mips32r2: 6813*mips32r6: 6814*mips64: 6815*mips64r2: 6816*mips64r6: 6817*vr4100: 6818*vr5000: 6819 6820 6821010000,1,0000000000000000000,000010:COP0:32::TLBWI 6822"tlbwi" 6823*mipsI: 6824*mipsII: 6825*mipsIII: 6826*mipsIV: 6827*mipsV: 6828*mips32: 6829*mips32r2: 6830*mips32r6: 6831*mips64: 6832*mips64r2: 6833*mips64r6: 6834*vr4100: 6835*vr5000: 6836 6837 6838010000,1,0000000000000000000,000110:COP0:32::TLBWR 6839"tlbwr" 6840*mipsI: 6841*mipsII: 6842*mipsIII: 6843*mipsIV: 6844*mipsV: 6845*mips32: 6846*mips32r2: 6847*mips32r6: 6848*mips64: 6849*mips64r2: 6850*mips64r6: 6851*vr4100: 6852*vr5000: 6853 6854 6855:include:::mips3264r2.igen 6856:include:::mips3264r6.igen 6857:include:::m16.igen 6858:include:::m16e.igen 6859:include:::mdmx.igen 6860:include:::mips3d.igen 6861:include:::sb1.igen 6862:include:::tx.igen 6863:include:::vr.igen 6864:include:::dsp.igen 6865:include:::dsp2.igen 6866:include:::smartmips.igen 6867:include:::micromips.igen 6868:include:::micromipsdsp.igen 6869 6870