1 /* This file is part of the program GDB, the GNU debugger. 2 3 Copyright (C) 1998-2024 Free Software Foundation, Inc. 4 Contributed by Cygnus Solutions. 5 6 This program is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3 of the License, or 9 (at your option) any later version. 10 11 This program is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this program. If not, see <http://www.gnu.org/licenses/>. 18 19 */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include "sim-main.h" 25 #include "hw-main.h" 26 27 /* DEVICE 28 29 30 tx3904cpu - tx3904 cpu virtual device 31 32 33 DESCRIPTION 34 35 36 Implements the external tx3904 functionality. This includes the 37 delivery of of interrupts generated from other devices and the 38 handling of device specific registers. 39 40 41 PROPERTIES 42 43 none 44 45 46 PORTS 47 48 49 reset (input) 50 51 Currently ignored. 52 53 54 nmi (input) 55 56 Deliver a non-maskable interrupt to the processor. 57 58 59 level (input) 60 61 Deliver a maskable interrupt of given level, corresponding to 62 IP[5:0], to processor. 63 64 65 66 BUGS 67 68 69 When delivering an interrupt, this code assumes that there is only 70 one processor (number 0). 71 72 This code does not attempt to be efficient at handling pending 73 interrupts. It simply schedules the interrupt delivery handler 74 every instruction cycle until all pending interrupts go away. An 75 alternative implementation might modify instructions that change 76 the PSW and have them check to see if the change makes an interrupt 77 delivery possible. 78 79 */ 80 81 82 83 struct tx3904cpu { 84 /* Pending interrupts for delivery by event handler */ 85 int pending_reset, pending_nmi, pending_level; 86 struct hw_event* event; 87 }; 88 89 90 91 /* input port ID's */ 92 93 enum { 94 RESET_PORT, 95 NMI_PORT, 96 LEVEL_PORT, 97 }; 98 99 100 static const struct hw_port_descriptor tx3904cpu_ports[] = { 101 102 /* interrupt inputs */ 103 { "reset", RESET_PORT, 0, input_port, }, 104 { "nmi", NMI_PORT, 0, input_port, }, 105 { "level", LEVEL_PORT, 0, input_port, }, 106 107 { NULL, }, 108 }; 109 110 111 /* Finish off the partially created hw device. Attach our local 112 callbacks. Wire up our port names etc */ 113 114 static hw_port_event_method tx3904cpu_port_event; 115 116 117 118 static void 119 tx3904cpu_finish (struct hw *me) 120 { 121 struct tx3904cpu *controller; 122 123 controller = HW_ZALLOC (me, struct tx3904cpu); 124 set_hw_data (me, controller); 125 set_hw_ports (me, tx3904cpu_ports); 126 set_hw_port_event (me, tx3904cpu_port_event); 127 128 /* Initialize the pending interrupt flags */ 129 controller->pending_level = 0; 130 controller->pending_reset = 0; 131 controller->pending_nmi = 0; 132 controller->event = NULL; 133 } 134 135 136 137 /* An event arrives on an interrupt port */ 138 139 static void 140 deliver_tx3904cpu_interrupt (struct hw *me, 141 void *data) 142 { 143 struct tx3904cpu *controller = hw_data (me); 144 SIM_DESC sd = hw_system (me); 145 sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ 146 address_word cia = CPU_PC_GET (cpu); 147 148 #define CPU cpu 149 #define SD sd 150 151 if (controller->pending_reset) 152 { 153 controller->pending_reset = 0; 154 HW_TRACE ((me, "reset pc=0x%08lx", (long) CPU_PC_GET (cpu))); 155 SignalExceptionNMIReset(); 156 } 157 else if (controller->pending_nmi) 158 { 159 controller->pending_nmi = 0; 160 HW_TRACE ((me, "nmi pc=0x%08lx", (long) CPU_PC_GET (cpu))); 161 SignalExceptionNMIReset(); 162 } 163 else if (controller->pending_level) 164 { 165 HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx", 166 controller->pending_level, 167 (long) CPU_PC_GET (cpu), (long) SR)); 168 169 /* Clear CAUSE register. It may stay this way if the interrupt 170 was cleared with a negative pending_level. */ 171 CAUSE &= ~ (cause_IP_mask << cause_IP_shift); 172 173 if (controller->pending_level > 0) /* interrupt set */ 174 { 175 /* set hardware-interrupt subfields of CAUSE register */ 176 CAUSE |= (controller->pending_level & cause_IP_mask) << cause_IP_shift; 177 178 /* check for enabled / unmasked interrupts */ 179 if ((SR & status_IEc) && 180 (controller->pending_level & ((SR >> status_IM_shift) & status_IM_mask))) 181 { 182 controller->pending_level = 0; 183 SignalExceptionInterrupt(0 /* dummy value */); 184 } 185 else 186 { 187 /* reschedule soon */ 188 if (controller->event != NULL) 189 hw_event_queue_deschedule(me, controller->event); 190 controller->event = 191 hw_event_queue_schedule (me, 1, deliver_tx3904cpu_interrupt, NULL); 192 } 193 } /* interrupt set */ 194 } 195 #undef CPU 196 #undef SD 197 } 198 199 200 static void 201 tx3904cpu_port_event (struct hw *me, 202 int my_port, 203 struct hw *source, 204 int source_port, 205 int level) 206 { 207 struct tx3904cpu *controller = hw_data (me); 208 209 switch (my_port) 210 { 211 case RESET_PORT: 212 controller->pending_reset = 1; 213 HW_TRACE ((me, "port-in reset")); 214 break; 215 216 case NMI_PORT: 217 controller->pending_nmi = 1; 218 HW_TRACE ((me, "port-in nmi")); 219 break; 220 221 case LEVEL_PORT: 222 /* level == 0 means that the interrupt was cleared */ 223 if (level == 0) 224 controller->pending_level = -1; /* signal end of interrupt */ 225 else 226 controller->pending_level = level; 227 HW_TRACE ((me, "port-in level=%d", level)); 228 break; 229 230 default: 231 hw_abort (me, "bad switch"); 232 break; 233 } 234 235 /* Schedule an event to be delivered immediately after current 236 instruction. */ 237 if (controller->event != NULL) 238 hw_event_queue_deschedule(me, controller->event); 239 controller->event = 240 hw_event_queue_schedule (me, 0, deliver_tx3904cpu_interrupt, NULL); 241 } 242 243 244 const struct hw_descriptor dv_tx3904cpu_descriptor[] = { 245 { "tx3904cpu", tx3904cpu_finish, }, 246 { NULL }, 247 }; 248