12021-07-01 Mike Frysinger <vapier@gentoo.org> 2 3 * configure.ac: Delete SIM_AC_OPTION_RESERVED_BITS call. 4 * aclocal.m4: Regenerate. 5 * configure: Regenerate. 6 72021-06-30 Mike Frysinger <vapier@gentoo.org> 8 9 * configure: Regenerate. 10 112021-06-22 Mike Frysinger <vapier@gentoo.org> 12 13 * configure: Regenerate. 14 152021-06-21 Mike Frysinger <vapier@gentoo.org> 16 17 * aclocal.m4: Regenerate. 18 * configure: Regenerate. 19 202021-06-21 Mike Frysinger <vapier@gentoo.org> 21 22 * Makefile.in (SIM_EXTRA_HW_DEVICES): Define. 23 * configure.ac (SIM_AC_OPTION_HARDWARE): Delete call. 24 * configure: Regenerate. 25 262021-06-20 Mike Frysinger <vapier@gentoo.org> 27 28 * configure.ac (SIM_AC_COMMON): Delete. 29 * aclocal.m4, configure: Regenerate. 30 312021-06-20 Mike Frysinger <vapier@gentoo.org> 32 33 * aclocal.m4: Regenerate. 34 * configure: Regenerate. 35 362021-06-19 Mike Frysinger <vapier@gentoo.org> 37 38 * aclocal.m4: Regenerate. 39 * configure: Regenerate. 40 412021-06-19 Mike Frysinger <vapier@gentoo.org> 42 43 * configure.ac: Delete AC_PATH_X call. 44 * configure: Regenerate. 45 462021-06-19 Mike Frysinger <vapier@gentoo.org> 47 48 * configure.ac: Delete AC_CHECK_LIB calls. 49 * configure: Regenerate. 50 512021-06-18 Mike Frysinger <vapier@gentoo.org> 52 53 * aclocal.m4, configure: Regenerate. 54 552021-06-18 Mike Frysinger <vapier@gentoo.org> 56 57 * Makefile.in (SIM_WERROR_CFLAGS): New variable. 58 * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS. 59 * configure: Regenerate. 60 612021-06-18 Mike Frysinger <vapier@gentoo.org> 62 63 * interp.c: Include sim-signal.h. 64 652021-06-17 Mike Frysinger <vapier@gentoo.org> 66 67 * configure.ac: Delete SIM_AC_OPTION_ENDIAN call. 68 * aclocal.m4, configure: Regenerate. 69 702021-06-16 Mike Frysinger <vapier@gentoo.org> 71 72 * interp.c (dotrace): Make comment const. 73 * sim-main.h (dotrace): Likewise. Add ATTRIBUTE_PRINTF. 74 752021-06-16 Mike Frysinger <vapier@gentoo.org> 76 77 * interp.c (sim_monitor): Change ap type to address_word*. 78 (_P, P): New macros. Rewrite dynamic printf logic to use these. 79 802021-06-16 Mike Frysinger <vapier@gentoo.org> 81 82 * dv-tx3904sio.c (tx3904sio_fifo_push): Change next_buf to 83 unsigned_1. 84 852021-06-16 Mike Frysinger <vapier@gentoo.org> 86 87 * dv-tx3904irc.c (tx3904irc_io_write_buffer): Initialize 88 register_value to 0. 89 902021-06-16 Mike Frysinger <vapier@gentoo.org> 91 92 * configure: Regenerate. 93 942021-06-16 Mike Frysinger <vapier@gentoo.org> 95 96 * interp.c (sim_open): Change %lx to %x and PRIx macros. 97 982021-06-16 Mike Frysinger <vapier@gentoo.org> 99 100 * configure: Regenerate. 101 * config.in: Removed. 102 1032021-06-15 Mike Frysinger <vapier@gentoo.org> 104 105 * config.in, configure: Regenerate. 106 1072021-06-12 Mike Frysinger <vapier@gentoo.org> 108 109 * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT. 110 1112021-06-12 Mike Frysinger <vapier@gentoo.org> 112 113 * aclocal.m4, config.in, configure: Regenerate. 114 1152021-06-12 Mike Frysinger <vapier@gentoo.org> 116 117 * configure.ac: Delete call to AC_CHECK_FUNCS. 118 * config.in, configure: Regenerate. 119 1202021-06-08 Mike Frysinger <vapier@gentoo.org> 121 122 * Makefile.in: Replace $(IGEN) with $(IGEN_RUN) and ../igen/igen 123 with $(IGEN). 124 1252021-05-29 Mike Frysinger <vapier@gentoo.org> 126 127 * interp.c [!HAVE_DV_SOCKSER] (sockser_addr): Define to NULL. 128 1292021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com> 130 131 * interp.c (sim_open): Add shadow mappings from 32-bit 132 address space to 64-bit sign-extended address space. 133 1342021-05-22 Faraz Shahbazker <fshahbazker@wavecomp.com> 135 136 * interp.c (sim_create_inferior): Only truncate sign extension 137 bits for 32-bit target models. 138 1392021-05-17 Mike Frysinger <vapier@gentoo.org> 140 141 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete. 142 1432021-05-17 Mike Frysinger <vapier@gentoo.org> 144 145 * interp.c (sim_open): Switch to sim_state_alloc_extra. 146 * micromips.igen: Change SD to mips_sim_state. 147 * micromipsrun.c (sim_engine_run): Likewise. 148 * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define. 149 (watch_options_install): Delete. 150 (struct swatch): Delete. 151 (struct sim_state): Delete. 152 (struct mips_sim_state): New struct. 153 (MIPS_SIM_STATE): Define. 154 1552021-05-16 Mike Frysinger <vapier@gentoo.org> 156 157 * interp.c: Replace config.h include with defs.h. 158 * cp1.c, dsp.c, dv-tx3904cpu.c, dv-tx3904irc.c, dv-tx3904sio.c, 159 dv-tx3904tmr.c, m16run.c, mdmx.c, micromipsrun.c, sim-main.c: 160 Include defs.h. 161 1622021-05-16 Mike Frysinger <vapier@gentoo.org> 163 164 * config.in, configure: Regenerate. 165 1662021-05-14 Mike Frysinger <vapier@gentoo.org> 167 168 * interp.c: Update include path. 169 1702021-05-04 Mike Frysinger <vapier@gentoo.org> 171 172 * dv-tx3904sio.c: Include stdlib.h. 173 1742021-05-04 Mike Frysinger <vapier@gentoo.org> 175 176 * configure.ac (hw_extra_devices): Inline contents into 177 SIM_AC_OPTION_HARDWARE and delete. 178 * configure: Regenerate. 179 1802021-05-04 Mike Frysinger <vapier@gentoo.org> 181 182 * Makefile.in (SIM_IGEN_OBJ): Change @mips_igen_engine@ to engine.o. 183 (MIPS_EXTRA_LIB, SIM_EXTRA_LIBS): Delete. 184 * configure.ac (mips_igen_engine, mips_extra_libs): Delete. 185 * configure: Regenerate. 186 1872021-05-04 Mike Frysinger <vapier@gentoo.org> 188 189 * mdmx.c (qh_acc): Change 2nd AccAddAQH to AccAddLQH. 190 1912021-05-04 Mike Frysinger <vapier@gentoo.org> 192 193 * configure: Regenerate. 194 1952021-05-01 Mike Frysinger <vapier@gentoo.org> 196 197 * cp1.c (store_fcr): Mark static. 198 1992021-05-01 Mike Frysinger <vapier@gentoo.org> 200 201 * config.in, configure: Regenerate. 202 2032021-04-23 Mike Frysinger <vapier@gentoo.org> 204 205 * configure.ac (hw_enabled): Delete. 206 (SIM_AC_OPTION_HARDWARE): Delete first two args. 207 * configure: Regenerate. 208 2092021-04-22 Tom Tromey <tom@tromey.com> 210 211 * configure, config.in: Rebuild. 212 2132021-04-22 Tom Tromey <tom@tromey.com> 214 215 * Makefile.in (interp.o, m16run.o, micromipsrun.o, multi-run.o): 216 Remove. 217 (SIM_EXTRA_DEPS): New variable. 218 2192021-04-22 Tom Tromey <tom@tromey.com> 220 221 * configure: Rebuild. 222 2232021-04-21 Mike Frysinger <vapier@gentoo.org> 224 225 * aclocal.m4: Regenerate. 226 2272021-04-21 Simon Marchi <simon.marchi@polymtl.ca> 228 229 * configure: Regenerate. 230 2312021-04-18 Mike Frysinger <vapier@gentoo.org> 232 233 * configure: Regenerate. 234 2352021-04-12 Mike Frysinger <vapier@gentoo.org> 236 237 * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all. 238 2392021-04-08 Simon Marchi <simon.marchi@polymtl.ca> 240 241 * Makefile.in: Set ASAN_OPTIONS when running igen. 242 2432021-04-04 Steve Ellcey <sellcey@mips.com> 244 Faraz Shahbazker <fshahbazker@wavecomp.com> 245 246 * interp.c (sim_monitor): Add switch entries for unlink (13), 247 lseek (14), and stat (15). 248 2492021-04-02 Mike Frysinger <vapier@gentoo.org> 250 251 * Makefile.in (../igen/igen): Delete rule. 252 (tmp-igen, tmp-m16, tmp-micromips): Delete ../igen make. 253 2542021-04-02 Mike Frysinger <vapier@gentoo.org> 255 256 * aclocal.m4, configure: Regenerate. 257 2582021-02-28 Mike Frysinger <vapier@gentoo.org> 259 260 * configure: Regenerate. 261 2622021-02-27 Mike Frysinger <vapier@gentoo.org> 263 264 * Makefile.in (SIM_EXTRA_ALL): Delete. 265 (all): New target. 266 2672021-02-21 Mike Frysinger <vapier@gentoo.org> 268 269 * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4. 270 * aclocal.m4, configure: Regenerate. 271 2722021-02-13 Mike Frysinger <vapier@gentoo.org> 273 274 * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS. 275 * aclocal.m4, configure: Regenerate. 276 2772021-02-06 Mike Frysinger <vapier@gentoo.org> 278 279 * interp.c (sim_open): Delete call to STATE_WATCHPOINTS. 280 2812021-02-06 Mike Frysinger <vapier@gentoo.org> 282 283 * configure: Regenerate. 284 2852021-01-30 Mike Frysinger <vapier@gentoo.org> 286 287 * interp.c (sim_open): Delete STATE_WATCHPOINTS (sd)->sizeof_pc. 288 2892021-01-11 Mike Frysinger <vapier@gentoo.org> 290 291 * config.in, configure: Regenerate. 292 * interp.c: Delete HAVE_STRING_H, HAVE_STRINGS_H, HAVE_STDLIB_H, 293 and strings.h include. 294 2952021-01-09 Mike Frysinger <vapier@gentoo.org> 296 297 * configure: Regenerate. 298 2992021-01-09 Mike Frysinger <vapier@gentoo.org> 300 301 * configure.ac (SIM_AC_OPTION_WARNINGS): Pass "no". 302 * configure: Regenerate. 303 3042021-01-08 Mike Frysinger <vapier@gentoo.org> 305 306 * configure: Regenerate. 307 3082021-01-04 Mike Frysinger <vapier@gentoo.org> 309 310 * configure: Regenerate. 311 3122020-12-31 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change) 313 314 * sim-main.c: Include <stdlib.h>. 315 3162020-12-14 Pavel I. Kryukov <kryukov@frtk.ru> (tiny change) 317 318 * cp1.c: Include <stdlib.h>. 319 3202020-07-29 Simon Marchi <simon.marchi@efficios.com> 321 322 * configure: Re-generate. 323 3242017-09-06 John Baldwin <jhb@FreeBSD.org> 325 326 * configure: Regenerate. 327 3282016-11-11 Mike Frysinger <vapier@gentoo.org> 329 330 PR sim/20808 331 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Define CPU to cpu 332 and SD to sd. 333 3342016-11-11 Mike Frysinger <vapier@gentoo.org> 335 336 PR sim/20809 337 * mips.igen (check_u64): Enable for `r3900'. 338 3392016-02-05 Mike Frysinger <vapier@gentoo.org> 340 341 * configure.ac (sim_engine_run): Change sd->base.prog_bfd to 342 STATE_PROG_BFD (sd). 343 * configure: Regenerate. 344 3452016-01-18 Andrew Bennett <andrew.bennett@imgtec.com> 346 Maciej W. Rozycki <macro@imgtec.com> 347 348 PR sim/19441 349 * micromips.igen (delayslot_micromips): Enable for `micromips32', 350 `micromips64' and `micromipsdsp' only. 351 (process_isa_mode): Enable for `micromips32' and `micromips64' only. 352 (do_micromips_jalr, do_micromips_jal): Likewise. 353 (compute_movep_src_reg): Likewise. 354 (compute_andi16_imm): Likewise. 355 (convert_fmt_micromips): Likewise. 356 (convert_fmt_micromips_cvt_d): Likewise. 357 (convert_fmt_micromips_cvt_s): Likewise. 358 (FMT_MICROMIPS): Likewise. 359 (FMT_MICROMIPS_CVT_D): Likewise. 360 (FMT_MICROMIPS_CVT_S): Likewise. 361 3622016-01-12 Mike Frysinger <vapier@gentoo.org> 363 364 * interp.c: Include elf-bfd.h. 365 (sim_create_inferior): Truncate pc to 32-bits when EI_CLASS is 366 ELFCLASS32. 367 3682016-01-10 Mike Frysinger <vapier@gentoo.org> 369 370 * config.in, configure: Regenerate. 371 3722016-01-10 Mike Frysinger <vapier@gentoo.org> 373 374 * configure: Regenerate. 375 3762016-01-10 Mike Frysinger <vapier@gentoo.org> 377 378 * configure: Regenerate. 379 3802016-01-10 Mike Frysinger <vapier@gentoo.org> 381 382 * configure: Regenerate. 383 3842016-01-10 Mike Frysinger <vapier@gentoo.org> 385 386 * configure: Regenerate. 387 3882016-01-10 Mike Frysinger <vapier@gentoo.org> 389 390 * configure.ac (SIM_AC_OPTION_SMP): Delete call. 391 * configure: Regenerate. 392 3932016-01-10 Mike Frysinger <vapier@gentoo.org> 394 395 * configure.ac (SIM_AC_OPTION_INLINE): Delete call. 396 * configure: Regenerate. 397 3982016-01-10 Mike Frysinger <vapier@gentoo.org> 399 400 * configure: Regenerate. 401 4022016-01-10 Mike Frysinger <vapier@gentoo.org> 403 404 * configure: Regenerate. 405 4062016-01-09 Mike Frysinger <vapier@gentoo.org> 407 408 * config.in, configure: Regenerate. 409 4102016-01-06 Mike Frysinger <vapier@gentoo.org> 411 412 * interp.c (sim_open): Mark argv const. 413 (sim_create_inferior): Mark argv and env const. 414 4152016-01-04 Mike Frysinger <vapier@gentoo.org> 416 417 * configure: Regenerate. 418 4192016-01-03 Mike Frysinger <vapier@gentoo.org> 420 421 * interp.c (sim_open): Update sim_parse_args comment. 422 4232016-01-03 Mike Frysinger <vapier@gentoo.org> 424 425 * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. 426 * configure: Regenerate. 427 4282016-01-02 Mike Frysinger <vapier@gentoo.org> 429 430 * configure.ac (mips_endian): Change LITTLE_ENDIAN to LITTLE. 431 (default_endian): Likewise. Change BIG_ENDIAN to BIG. 432 * configure: Regenerate. 433 * sim-main.h (BigEndianMem): Change BIG_ENDIAN to BFD_ENDIAN_BIG. 434 4352016-01-02 Mike Frysinger <vapier@gentoo.org> 436 437 * dv-tx3904cpu.c (CPU, SD): Delete. 438 4392015-12-30 Mike Frysinger <vapier@gentoo.org> 440 441 * wrapper.c (mips_reg_store, mips_reg_fetch): Define. 442 (sim_open): Call CPU_REG_FETCH/CPU_REG_STORE. 443 (sim_store_register): Rename to ... 444 (mips_reg_store): ... this. Delete local cpu var. 445 Update sim_io_eprintf calls. 446 (sim_fetch_register): Rename to ... 447 (mips_reg_fetch): ... this. Delete local cpu var. 448 Update sim_io_eprintf calls. 449 4502015-12-27 Mike Frysinger <vapier@gentoo.org> 451 452 * Makefile.in (SIM_OBJS): Delete sim-hload.o. 453 4542015-12-26 Mike Frysinger <vapier@gentoo.org> 455 456 * config.in, configure: Regenerate. 457 4582015-12-26 Mike Frysinger <vapier@gentoo.org> 459 460 * interp.c (sim_write, sim_read): Delete. 461 (store_word): Delete call to AddressTranslation and set paddr=vaddr. 462 (load_word): Likewise. 463 * micromips.igen (cache): Likewise. 464 * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1, 465 do_swxc1, cache, do_load, do_load_left, do_load_right, do_store, 466 do_store_left, do_store_right, do_load_double, do_store_double): 467 Likewise. 468 (do_pref): Delete call to AddressTranslation and stub out Prefetch. 469 (do_prefx): Likewise. 470 * sim-main.c (address_translation, prefetch): Delete. 471 (ifetch32, ifetch16): Delete call to AddressTranslation and set 472 paddr=vaddr. 473 * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached, 474 address_translation, AddressTranslation, prefetch, Prefetch): Delete. 475 (LoadMemory, StoreMemory): Delete CCA arg. 476 4772015-12-24 Mike Frysinger <vapier@gentoo.org> 478 479 * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1. 480 * configure: Regenerated. 481 4822015-12-24 Mike Frysinger <vapier@gentoo.org> 483 484 * sim-main.h (SIM_QUIET_NAN_NEGATED): Move from tconfig.h. 485 * tconfig.h: Delete. 486 4872015-12-24 Mike Frysinger <vapier@gentoo.org> 488 489 * tconfig.h (SIM_HANDLES_LMA): Delete. 490 4912015-12-24 Mike Frysinger <vapier@gentoo.org> 492 493 * sim-main.h (WITH_WATCHPOINTS): Delete. 494 4952015-12-24 Mike Frysinger <vapier@gentoo.org> 496 497 * interp.c [SIM_HAVE_FLATMEM] (sim_open): Delete flatmem code. 498 4992015-12-24 Mike Frysinger <vapier@gentoo.org> 500 501 * tconfig.h (SIM_HAVE_SIMCACHE): Delete. 502 5032015-12-15 Dominik Vogt <vogt@linux.vnet.ibm.com> 504 505 * micromips.igen (process_isa_mode): Fix left shift of negative 506 value. 507 5082015-11-17 Mike Frysinger <vapier@gentoo.org> 509 510 * sim-main.h (WITH_MODULO_MEMORY): Delete. 511 5122015-11-15 Mike Frysinger <vapier@gentoo.org> 513 514 * Makefile.in (SIM_OBJS): Delete sim-reason.o and sim-stop.o. 515 5162015-11-14 Mike Frysinger <vapier@gentoo.org> 517 518 * interp.c (sim_close): Rename to ... 519 (mips_sim_close): ... this. Delete calls to sim_module_uninstall and 520 sim_io_shutdown. 521 * sim-main.h (mips_sim_close): Declare. 522 (SIM_CLOSE_HOOK): Define. 523 5242015-09-25 Andrew Bennett <andrew.bennett@imgtec.com> 525 Ali Lown <ali.lown@imgtec.com> 526 527 * Makefile.in (tmp-micromips): New rule. 528 (tmp-mach-multi): Add support for micromips. 529 * configure.ac (mips*-sde-elf* | mips*-mti-elf*): Made a multi sim 530 that works for both mips64 and micromips64. 531 (mipsisa32r2*-*-*): Made a multi sim that works for mips32 and 532 micromips32. 533 Add build support for micromips. 534 * dsp.igen (do_ph_s_absq, do_w_s_absq, do_qb_s_absq, do_addsc, 535 do_addwc, do_bitrev, do_extpv, do_extrv, do_extrv_s_h, do_insv, 536 do_lxx do_modsub, do_mthlip, do_mulsaq_s_w_ph, do_ph_packrl, do_qb_pick 537 do_ph_pick, do_qb_ph_precequ, do_qb_ph_preceu, do_w_preceq 538 do_w_ph_precrq, do_ph_qb_precrq, do_w_ph_rs_precrq do_qb_w_raddu, 539 do_rddsp, do_repl, do_shilov, do_ph_shl, do_qb_shl do_w_s_shllv, 540 do_ph_shrlv, do_w_r_shrav, do_wrdsp, do_qb_shrav, do_append, 541 do_balign, do_ph_w_mulsa, do_ph_qb_precr, do_prepend): New functions. 542 Refactored instruction code to use these functions. 543 * dsp2.igen: Refactored instruction code to use the new functions. 544 * interp.c (decode_coproc): Refactored to work with any instruction 545 encoding. 546 (isa_mode): New variable 547 (RSVD_INSTRUCTION): Changed to 0x00000039. 548 * m16.igen (BREAK16): Refactored instruction to use do_break16. 549 (JALX32): Add mips32, mips64, mips32r2 and mips64r2 models. 550 * micromips.dc: New file. 551 * micromips.igen: New file. 552 * micromips16.dc: New file. 553 * micromipsdsp.igen: New file. 554 * micromipsrun.c: New file. 555 * mips.igen (do_swc1): Changed to work with any instruction encoding. 556 (do_add do_addi do_andi do_dadd do_daddi do_dsll32 do_dsra32 557 do_dsrl32, do_dsub, do_break, do_break16, do_clo, do_clz, do_dclo, 558 do_dclz, do_lb, do_lh, do_lwr, do_lwl, do_lwc, do_lw, do_lwu, do_lhu, 559 do_ldc, do_lbu, do_ll, do_lld, do_lui, do_madd, do_dsp_madd, do_maddu, 560 do_dsp_maddu, do_dsp_mfhi, do_dsp_mflo, do_movn, do_movz, do_msub, 561 do_dsp_msub, do_msubu, do_dsp_msubu, do_mthi, do_dsp_mthi, do_mtlo, 562 do_dsp_mtlo, do_mul, do_dsp_mult, do_dsp_multu, do_pref, do_sc, 563 do_scd, do_sub, do_sw, do_teq, do_teqi, do_tge, do_tgei, do_tgeiu, 564 do_tgeu, do_tlt do_tlti, do_tltiu, do_tltu, do_tne, do_tnei, do_abs_fmt, 565 do_add_fmt, do_alnv_ps, do_c_cond_fmt, do_ceil_fmt, do_cfc1, do_ctc1, 566 do_cvt_d_fmt, do_cvt_l_fmt, do_cvt_ps_s, do_cvt_s_fmt, do_cvt_s_pl, 567 do_cvt_s_pu, do_cvt_w_fmt, do_div_fmt, do_dmfc1b, do_dmtc1b, do_floor_fmt, 568 do_luxc1_32, do_luxc1_64, do_lwc1, do_lwxc1, do_madd_fmt, do_mfc1b, 569 do_mov_fmt, do_movtf, do_movtf_fmt, do_movn_fmt, do_movz_fmt, do_msub_fmt, 570 do_mtc1b, do_mul_fmt, do_neg_fmt, do_nmadd_fmt, do_nmsub_fmt, do_pll_ps, 571 do_plu_ps, do_pul_ps, do_puu_ps, do_recip_fmt, do_round_fmt, do_rsqrt_fmt, 572 do_prefx, do_sdc1, do_suxc1_32, do_suxc1_64, do_sqrt_fmt, do_sub_fmt, 573 do_swc1, do_swxc1, do_trunc_fmt): New functions, refactored from existing 574 instructions. 575 Refactored instruction code to use these functions. 576 (RSVD): Changed to use new reserved instruction. 577 (loadstore_ea, not_word_value, unpredictable, check_mt_hilo, 578 check_mf_hilo, check_mult_hilo, check_div_hilo, check_u64, do_luxc1_32, 579 do_sdc1, do_suxc1_32, check_fmt_p, check_fpu, do_load_double, 580 do_store_double): Added micromips32 and micromips64 models. 581 Added include for micromips.igen and micromipsdsp.igen 582 Add micromips32 and micromips64 models. 583 (DecodeCoproc): Updated to use new macro definition. 584 * mips3264r2.igen (do_dsbh, do_dshd, do_dext, do_dextm, do_dextu, do_di, 585 do_dins, do_dinsm, do_ei, do_ext, do_mfhc1, do_mthc1, do_ins, do_dinsu, 586 do_seb, do_seh do_rdhwr, do_wsbh): New functions. 587 Refactored instruction code to use these functions. 588 * sim-main.h (CP0_operation): New enum. 589 (DecodeCoproc): Updated macro. 590 (IMEM32_MICROMIPS, IMEM16_MICROMIPS, MICROMIPS_MINOR_OPCODE, 591 MICROMIPS_DELAYSLOT_SIZE_ANY, MICROMIPS_DELAYSLOT_SIZE_16, 592 MICROMIPS_DELAYSLOT_SIZE_32, ISA_MODE_MIPS32 and 593 ISA_MODE_MICROMIPS): New defines. 594 (sim_state): Add isa_mode field. 595 5962015-06-23 Mike Frysinger <vapier@gentoo.org> 597 598 * configure: Regenerate. 599 6002015-06-12 Mike Frysinger <vapier@gentoo.org> 601 602 * configure.ac: Change configure.in to configure.ac. 603 * configure: Regenerate. 604 6052015-06-12 Mike Frysinger <vapier@gentoo.org> 606 607 * configure: Regenerate. 608 6092015-06-12 Mike Frysinger <vapier@gentoo.org> 610 611 * interp.c [TRACE]: Delete. 612 (TRACE): Change to WITH_TRACE_ANY_P. 613 [!WITH_TRACE_ANY_P] (open_trace): Define. 614 (mips_option_handler, open_trace, sim_close, dotrace): 615 Change defined(TRACE) to WITH_TRACE_ANY_P. 616 (sim_open): Delete TRACE ifdef check. 617 * sim-main.c (load_memory): Delete TRACE ifdef check. 618 (store_memory): Likewise. 619 * sim-main.h [WITH_TRACE_ANY_P] (dotrace, tracefh): Protect decls. 620 [!WITH_TRACE_ANY_P] (dotrace): Define. 621 6222015-04-18 Mike Frysinger <vapier@gentoo.org> 623 624 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESTART_HOOK): Delete 625 comments. 626 6272015-04-18 Mike Frysinger <vapier@gentoo.org> 628 629 * sim-main.h (SIM_CPU): Delete. 630 6312015-04-18 Mike Frysinger <vapier@gentoo.org> 632 633 * sim-main.h (sim_cia): Delete. 634 6352015-04-17 Mike Frysinger <vapier@gentoo.org> 636 637 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Change CIA_GET to 638 PU_PC_GET. 639 * interp.c (interrupt_event): Change CIA_GET to CPU_PC_GET. 640 (sim_create_inferior): Change CIA_SET to CPU_PC_SET. 641 * m16run.c (sim_engine_run): Change CIA_GET to CPU_PC_GET and 642 CIA_SET to CPU_PC_SET. 643 * sim-main.h (CIA_GET, CIA_SET): Delete. 644 6452015-04-15 Mike Frysinger <vapier@gentoo.org> 646 647 * Makefile.in (SIM_OBJS): Delete sim-cpu.o. 648 * sim-main.h (STATE_CPU): Delete. 649 6502015-04-13 Mike Frysinger <vapier@gentoo.org> 651 652 * configure: Regenerate. 653 6542015-04-13 Mike Frysinger <vapier@gentoo.org> 655 656 * Makefile.in (SIM_OBJS): Add sim-cpu.o. 657 * interp.c (mips_pc_get, mips_pc_set): New functions. 658 (sim_open): Declare new local var i. Call sim_cpu_alloc_all. 659 Call CPU_PC_FETCH & CPU_PC_STORE for all cpus. 660 (sim_pc_get): Delete. 661 * sim-main.h (SIM_CPU): Define. 662 (struct sim_state): Change cpu to an array of pointers. 663 (STATE_CPU): Drop &. 664 6652015-04-13 Mike Frysinger <vapier@gentoo.org> 666 667 * interp.c (mips_option_handler, open_trace, sim_close, 668 sim_write, sim_read, sim_store_register, sim_fetch_register, 669 sim_create_inferior, pr_addr, pr_uword64): Convert old style 670 prototypes. 671 (sim_open): Convert old style prototype. Change casts with 672 sim_write to unsigned char *. 673 (fetch_str): Change null to unsigned char, and change cast to 674 unsigned char *. 675 (sim_monitor): Change c & ch to unsigned char. Change cast to 676 unsigned char *. 677 6782015-04-12 Mike Frysinger <vapier@gentoo.org> 679 680 * Makefile.in (SIM_OBJS): Move interp.o to the start of the list. 681 6822015-04-06 Mike Frysinger <vapier@gentoo.org> 683 684 * Makefile.in (SIM_OBJS): Delete sim-engine.o. 685 6862015-04-01 Mike Frysinger <vapier@gentoo.org> 687 688 * tconfig.h (SIM_HAVE_PROFILE): Delete. 689 6902015-03-31 Mike Frysinger <vapier@gentoo.org> 691 692 * config.in, configure: Regenerate. 693 6942015-03-24 Mike Frysinger <vapier@gentoo.org> 695 696 * interp.c (sim_pc_get): New function. 697 6982015-03-24 Mike Frysinger <vapier@gentoo.org> 699 700 * sim-main.h (SIM_HAVE_BIENDIAN): Delete. 701 * tconfig.h (SIM_HAVE_BIENDIAN): Delete. 702 7032015-03-24 Mike Frysinger <vapier@gentoo.org> 704 705 * configure: Regenerate. 706 7072015-03-23 Mike Frysinger <vapier@gentoo.org> 708 709 * configure: Regenerate. 710 7112015-03-23 Mike Frysinger <vapier@gentoo.org> 712 713 * configure: Regenerate. 714 * configure.ac (mips_extra_objs): Delete. 715 * Makefile.in (MIPS_EXTRA_OBJS): Delete. 716 (SIM_OBJS): Delete MIPS_EXTRA_OBJS. 717 7182015-03-23 Mike Frysinger <vapier@gentoo.org> 719 720 * configure: Regenerate. 721 * configure.ac: Delete sim_hw checks for dv-sockser. 722 7232015-03-16 Mike Frysinger <vapier@gentoo.org> 724 725 * config.in, configure: Regenerate. 726 * tconfig.in: Rename file ... 727 * tconfig.h: ... here. 728 7292015-03-15 Mike Frysinger <vapier@gentoo.org> 730 731 * tconfig.in: Delete includes. 732 [HAVE_DV_SOCKSER]: Delete. 733 7342015-03-14 Mike Frysinger <vapier@gentoo.org> 735 736 * Makefile.in (SIM_RUN_OBJS): Delete. 737 7382015-03-14 Mike Frysinger <vapier@gentoo.org> 739 740 * configure.ac (AC_CHECK_HEADERS): Delete. 741 * aclocal.m4, configure: Regenerate. 742 7432014-08-19 Alan Modra <amodra@gmail.com> 744 745 * configure: Regenerate. 746 7472014-08-15 Roland McGrath <mcgrathr@google.com> 748 749 * configure: Regenerate. 750 * config.in: Regenerate. 751 7522014-03-04 Mike Frysinger <vapier@gentoo.org> 753 754 * configure: Regenerate. 755 7562013-09-23 Alan Modra <amodra@gmail.com> 757 758 * configure: Regenerate. 759 7602013-06-03 Mike Frysinger <vapier@gentoo.org> 761 762 * aclocal.m4, configure: Regenerate. 763 7642013-05-10 Freddie Chopin <freddie_chopin@op.pl> 765 766 * configure: Rebuild. 767 7682013-03-26 Mike Frysinger <vapier@gentoo.org> 769 770 * configure: Regenerate. 771 7722013-03-23 Joel Sherrill <joel.sherrill@oarcorp.com> 773 774 * configure.ac: Address use of dv-sockser.o. 775 * tconfig.in: Conditionalize use of dv_sockser_install. 776 * configure: Regenerated. 777 * config.in: Regenerated. 778 7792012-10-04 Chao-ying Fu <fu@mips.com> 780 Steve Ellcey <sellcey@mips.com> 781 782 * mips/mips3264r2.igen (rdhwr): New. 783 7842012-09-03 Joel Sherrill <joel.sherrill@oarcorp.com> 785 786 * configure.ac: Always link against dv-sockser.o. 787 * configure: Regenerate. 788 7892012-06-15 Joel Brobecker <brobecker@adacore.com> 790 791 * config.in, configure: Regenerate. 792 7932012-05-18 Nick Clifton <nickc@redhat.com> 794 795 PR 14072 796 * interp.c: Include config.h before system header files. 797 7982012-03-24 Mike Frysinger <vapier@gentoo.org> 799 800 * aclocal.m4, config.in, configure: Regenerate. 801 8022011-12-03 Mike Frysinger <vapier@gentoo.org> 803 804 * aclocal.m4: New file. 805 * configure: Regenerate. 806 8072011-10-19 Mike Frysinger <vapier@gentoo.org> 808 809 * configure: Regenerate after common/acinclude.m4 update. 810 8112011-10-17 Mike Frysinger <vapier@gentoo.org> 812 813 * configure.ac: Change include to common/acinclude.m4. 814 8152011-10-17 Mike Frysinger <vapier@gentoo.org> 816 817 * configure.ac: Change AC_PREREQ to 2.64. Delete AC_CONFIG_HEADER 818 call. Replace common.m4 include with SIM_AC_COMMON. 819 * configure: Regenerate. 820 8212011-07-08 Hans-Peter Nilsson <hp@axis.com> 822 823 * Makefile.in ($(SIM_MULTI_OBJ)): Depend on sim-main.h 824 $(SIM_EXTRA_DEPS). 825 (tmp-mach-multi): Exit early when igen fails. 826 8272011-07-05 Mike Frysinger <vapier@gentoo.org> 828 829 * interp.c (sim_do_command): Delete. 830 8312011-02-14 Mike Frysinger <vapier@gentoo.org> 832 833 * dv-tx3904sio.c (tx3904sio_fifo_push): Change zfree to free. 834 (tx3904sio_fifo_reset): Likewise. 835 * interp.c (sim_monitor): Likewise. 836 8372010-04-14 Mike Frysinger <vapier@gentoo.org> 838 839 * interp.c (sim_write): Add const to buffer arg. 840 8412010-01-18 Masaki Muranaka <monaka@monami-software.com> (tiny change) 842 843 * interp.c: Don't include sysdep.h 844 8452010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 846 847 * configure: Regenerate. 848 8492009-08-22 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> 850 851 * config.in: Regenerate. 852 * configure: Likewise. 853 854 * configure: Regenerate. 855 8562008-07-11 Hans-Peter Nilsson <hp@axis.com> 857 858 * configure: Regenerate to track ../common/common.m4 changes. 859 * config.in: Ditto. 860 8612008-06-06 Vladimir Prus <vladimir@codesourcery.com> 862 Daniel Jacobowitz <dan@codesourcery.com> 863 Joseph Myers <joseph@codesourcery.com> 864 865 * configure: Regenerate. 866 8672007-10-22 Richard Sandiford <rsandifo@nildram.co.uk> 868 869 * mips.igen (check_fmt_p): Provide a separate mips32r2 definition 870 that unconditionally allows fmt_ps. 871 (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU) 872 (FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt) 873 (PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change 874 filter from 64,f to 32,f. 875 (PREFX): Change filter from 64 to 32. 876 (LDXC1, LUXC1): Provide separate mips32r2 implementations 877 that use do_load_double instead of do_load. Make both LUXC1 878 versions unpredictable if SizeFGR () != 64. 879 (SDXC1, SUXC1): Extend to mips32r2, using do_store_double 880 instead of do_store. Remove unused variable. Make both SUXC1 881 versions unpredictable if SizeFGR () != 64. 882 8832007-10-07 Richard Sandiford <rsandifo@nildram.co.uk> 884 885 * mips.igen (ll): Fix mask for WITH_TARGET_WORD_BITSIZE == 32. 886 (sc, swxc1): Likewise. Also fix big-endian and reverse-endian 887 shifts for that case. 888 8892007-09-04 Nick Clifton <nickc@redhat.com> 890 891 * interp.c (options enum): Add OPTION_INFO_MEMORY. 892 (display_mem_info): New static variable. 893 (mips_option_handler): Handle OPTION_INFO_MEMORY. 894 (mips_options): Add info-memory and memory-info. 895 (sim_open): After processing the command line and board 896 specification, check display_mem_info. If it is set then 897 call the real handler for the --memory-info command line 898 switch. 899 9002007-08-24 Joel Brobecker <brobecker@adacore.com> 901 902 * configure.ac: Change license of multi-run.c to GPL version 3. 903 * configure: Regenerate. 904 9052007-06-28 Richard Sandiford <richard@codesourcery.com> 906 907 * configure.ac, configure: Revert last patch. 908 9092007-06-26 Richard Sandiford <richard@codesourcery.com> 910 911 * configure.ac (sim_mipsisa3264_configs): New variable. 912 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make 913 every configuration support all four targets, using the triplet to 914 determine the default. 915 * configure: Regenerate. 916 9172007-06-25 Richard Sandiford <richard@codesourcery.com> 918 919 * Makefile.in (m16run.o): New rule. 920 9212007-05-15 Thiemo Seufer <ths@mips.com> 922 923 * mips3264r2.igen (DSHD): Fix compile warning. 924 9252007-05-14 Thiemo Seufer <ths@mips.com> 926 927 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, 928 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, 929 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, 930 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support 931 for mips32r2. 932 9332007-03-01 Thiemo Seufer <ths@mips.com> 934 935 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32 936 and mips64. 937 9382007-02-20 Thiemo Seufer <ths@mips.com> 939 940 * dsp.igen: Update copyright notice. 941 * dsp2.igen: Fix copyright notice. 942 9432007-02-20 Thiemo Seufer <ths@mips.com> 944 Chao-Ying Fu <fu@mips.com> 945 946 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. 947 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): 948 Add dsp2 to sim_igen_machine. 949 * configure: Regenerate. 950 * dsp.igen (do_ph_op): Add MUL support when op = 2. 951 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. 952 (mulq_rs.ph): Use do_ph_mulq. 953 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. 954 * mips.igen: Add dsp2 model and include dsp2.igen. 955 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for 956 for *mips32r2, *mips64r2, *dsp. 957 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions 958 for *mips32r2, *mips64r2, *dsp2. 959 * dsp2.igen: New file for MIPS DSP REV 2 ASE. 960 9612007-02-19 Thiemo Seufer <ths@mips.com> 962 Nigel Stephens <nigel@mips.com> 963 964 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 965 jumps with hazard barrier. 966 9672007-02-19 Thiemo Seufer <ths@mips.com> 968 Nigel Stephens <nigel@mips.com> 969 970 * interp.c (sim_monitor): Flush stdout and stderr file descriptors 971 after each call to sim_io_write. 972 9732007-02-19 Thiemo Seufer <ths@mips.com> 974 Nigel Stephens <nigel@mips.com> 975 976 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size 977 supported by this simulator. 978 (decode_coproc): Recognise additional CP0 Config registers 979 correctly. 980 9812007-02-19 Thiemo Seufer <ths@mips.com> 982 Nigel Stephens <nigel@mips.com> 983 David Ung <davidu@mips.com> 984 985 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for 986 uninterpreted formats. If fmt is one of the uninterpreted types 987 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like 988 fmt_word, and fmt_uninterpreted_64 like fmt_long. 989 (store_fpr): When writing an invalid odd register, set the 990 matching even register to fmt_unknown, not the following register. 991 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to 992 the the memory window at offset 0 set by --memory-size command 993 line option. 994 (sim_store_register): Handle storing 4 bytes to an 8 byte floating 995 point register. 996 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte 997 register. 998 (sim_monitor): When returning the memory size to the MIPS 999 application, use the value in STATE_MEM_SIZE, not an arbitrary 1000 hardcoded value. 1001 (cop_lw): Don' mess around with FPR_STATE, just pass 1002 fmt_uninterpreted_32 to StoreFPR. 1003 (cop_sw): Similarly. 1004 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. 1005 (cop_sd): Similarly. 1006 * mips.igen (not_word_value): Single version for mips32, mips64 1007 and mips16. 1008 10092007-02-19 Thiemo Seufer <ths@mips.com> 1010 Nigel Stephens <nigel@mips.com> 1011 1012 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8 1013 MBytes. 1014 10152007-02-17 Thiemo Seufer <ths@mips.com> 1016 1017 * configure.ac (mips*-sde-elf*): Move in front of generic machine 1018 configuration. 1019 * configure: Regenerate. 1020 10212007-02-17 Thiemo Seufer <ths@mips.com> 1022 1023 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): 1024 Add mdmx to sim_igen_machine. 1025 (mipsisa64*-*-*): Likewise. Remove dsp. 1026 (mipsisa32*-*-*): Remove dsp. 1027 * configure: Regenerate. 1028 10292007-02-13 Thiemo Seufer <ths@mips.com> 1030 1031 * configure.ac: Add mips*-sde-elf* target. 1032 * configure: Regenerate. 1033 10342006-12-21 Hans-Peter Nilsson <hp@axis.com> 1035 1036 * acconfig.h: Remove. 1037 * config.in, configure: Regenerate. 1038 10392006-11-07 Thiemo Seufer <ths@mips.com> 1040 1041 * dsp.igen (do_w_op): Fix compiler warning. 1042 10432006-08-29 Thiemo Seufer <ths@mips.com> 1044 David Ung <davidu@mips.com> 1045 1046 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to 1047 sim_igen_machine. 1048 * configure: Regenerate. 1049 * mips.igen (model): Add smartmips. 1050 (MADDU): Increment ACX if carry. 1051 (do_mult): Clear ACX. 1052 (ROR,RORV): Add smartmips. 1053 (include): Include smartmips.igen. 1054 * sim-main.h (ACX): Set to REGISTERS[89]. 1055 * smartmips.igen: New file. 1056 10572006-08-29 Thiemo Seufer <ths@mips.com> 1058 David Ung <davidu@mips.com> 1059 1060 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and 1061 mips3264r2.igen. Add missing dependency rules. 1062 * m16e.igen: Support for mips16e save/restore instructions. 1063 10642006-06-13 Richard Earnshaw <rearnsha@arm.com> 1065 1066 * configure: Regenerated. 1067 10682006-06-05 Daniel Jacobowitz <dan@codesourcery.com> 1069 1070 * configure: Regenerated. 1071 10722006-05-31 Daniel Jacobowitz <dan@codesourcery.com> 1073 1074 * configure: Regenerated. 1075 10762006-05-15 Chao-ying Fu <fu@mips.com> 1077 1078 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions. 1079 10802006-04-18 Nick Clifton <nickc@redhat.com> 1081 1082 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break 1083 statement. 1084 10852006-03-29 Hans-Peter Nilsson <hp@axis.com> 1086 1087 * configure: Regenerate. 1088 10892005-12-14 Chao-ying Fu <fu@mips.com> 1090 1091 * Makefile.in (SIM_OBJS): Add dsp.o. 1092 (dsp.o): New dependency. 1093 (IGEN_INCLUDE): Add dsp.igen. 1094 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, 1095 mipsisa64*-*-*): Add dsp to sim_igen_machine. 1096 * configure: Regenerate. 1097 * mips.igen: Add dsp model and include dsp.igen. 1098 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, 1099 because these instructions are extended in DSP ASE. 1100 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of 1101 adding 6 DSP accumulator registers and 1 DSP control register. 1102 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, 1103 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, 1104 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, 1105 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, 1106 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, 1107 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, 1108 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, 1109 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, 1110 DSPCR_CCOND_SMASK): New define. 1111 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. 1112 * dsp.c, dsp.igen: New files for MIPS DSP ASE. 1113 11142005-07-08 Ian Lance Taylor <ian@airs.com> 1115 1116 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define. 1117 11182005-06-16 David Ung <davidu@mips.com> 1119 Nigel Stephens <nigel@mips.com> 1120 1121 * mips.igen: New mips16e model and include m16e.igen. 1122 (check_u64): Add mips16e tag. 1123 * m16e.igen: New file for MIPS16e instructions. 1124 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, 1125 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e 1126 models. 1127 * configure: Regenerate. 1128 11292005-05-26 David Ung <davidu@mips.com> 1130 1131 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model 1132 tags to all instructions which are applicable to the new ISAs. 1133 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from 1134 vr.igen. 1135 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific 1136 instructions. 1137 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move 1138 to mips.igen. 1139 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. 1140 * configure: Regenerate. 1141 11422005-03-23 Mark Kettenis <kettenis@gnu.org> 1143 1144 * configure: Regenerate. 1145 11462005-01-14 Andrew Cagney <cagney@gnu.org> 1147 1148 * configure.ac: Sinclude aclocal.m4 before common.m4. Add 1149 explicit call to AC_CONFIG_HEADER. 1150 * configure: Regenerate. 1151 11522005-01-12 Andrew Cagney <cagney@gnu.org> 1153 1154 * configure.ac: Update to use ../common/common.m4. 1155 * configure: Re-generate. 1156 11572005-01-11 Andrew Cagney <cagney@localhost.localdomain> 1158 1159 * configure: Regenerated to track ../common/aclocal.m4 changes. 1160 11612005-01-07 Andrew Cagney <cagney@gnu.org> 1162 1163 * configure.ac: Rename configure.in, require autoconf 2.59. 1164 * configure: Re-generate. 1165 11662004-12-08 Hans-Peter Nilsson <hp@axis.com> 1167 1168 * configure: Regenerate for ../common/aclocal.m4 update. 1169 11702004-09-24 Monika Chaddha <monika@acmet.com> 1171 1172 Committed by Andrew Cagney. 1173 * m16.igen (CMP, CMPI): Fix assembler. 1174 11752004-08-18 Chris Demetriou <cgd@broadcom.com> 1176 1177 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine. 1178 * configure: Regenerate. 1179 11802004-06-25 Chris Demetriou <cgd@broadcom.com> 1181 1182 * configure.in (sim_m16_machine): Include mipsIII. 1183 * configure: Regenerate. 1184 11852004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> 1186 1187 * mips/interp.c (decode_coproc): Sign-extend the address retrieved 1188 from COP0_BADVADDR. 1189 * mips/sim-main.h (COP0_BADVADDR): Remove a cast. 1190 11912004-04-10 Chris Demetriou <cgd@broadcom.com> 1192 1193 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. 1194 11952004-04-09 Chris Demetriou <cgd@broadcom.com> 1196 1197 * mips.igen (check_fmt): Remove. 1198 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) 1199 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) 1200 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) 1201 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) 1202 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) 1203 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. 1204 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) 1205 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) 1206 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. 1207 (C.cnd.fmta): Remove incorrect call to check_fmt_p. 1208 12092004-04-09 Chris Demetriou <cgd@broadcom.com> 1210 1211 * sb1.igen (check_sbx): New function. 1212 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx. 1213 12142004-03-29 Chris Demetriou <cgd@broadcom.com> 1215 Richard Sandiford <rsandifo@redhat.com> 1216 1217 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD) 1218 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. 1219 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide 1220 separate implementations for mipsIV and mipsV. Use new macros to 1221 determine whether the restrictions apply. 1222 12232004-01-19 Chris Demetriou <cgd@broadcom.com> 1224 1225 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) 1226 (check_mult_hilo): Improve comments. 1227 (check_div_hilo): Likewise. Also, fork off a new version 1228 to handle mips32/mips64 (since there are no hazards to check 1229 in MIPS32/MIPS64). 1230 12312003-06-17 Richard Sandiford <rsandifo@redhat.com> 1232 1233 * mips.igen (do_dmultx): Fix check for negative operands. 1234 12352003-05-16 Ian Lance Taylor <ian@airs.com> 1236 1237 * Makefile.in (SHELL): Make sure this is defined. 1238 (various): Use $(SHELL) whenever we invoke move-if-change. 1239 12402003-05-03 Chris Demetriou <cgd@broadcom.com> 1241 1242 * cp1.c: Tweak attribution slightly. 1243 * cp1.h: Likewise. 1244 * mdmx.c: Likewise. 1245 * mdmx.igen: Likewise. 1246 * mips3d.igen: Likewise. 1247 * sb1.igen: Likewise. 1248 12492003-04-15 Richard Sandiford <rsandifo@redhat.com> 1250 1251 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of 1252 unsigned operands. 1253 12542003-02-27 Andrew Cagney <cagney@redhat.com> 1255 1256 * interp.c (sim_open): Rename _bfd to bfd. 1257 (sim_create_inferior): Ditto. 1258 12592003-01-14 Chris Demetriou <cgd@broadcom.com> 1260 1261 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64. 1262 12632003-01-14 Chris Demetriou <cgd@broadcom.com> 1264 1265 * mips.igen (EI, DI): Remove. 1266 12672003-01-05 Richard Sandiford <rsandifo@redhat.com> 1268 1269 * Makefile.in (tmp-run-multi): Fix mips16 filter. 1270 12712003-01-04 Richard Sandiford <rsandifo@redhat.com> 1272 Andrew Cagney <ac131313@redhat.com> 1273 Gavin Romig-Koch <gavin@redhat.com> 1274 Graydon Hoare <graydon@redhat.com> 1275 Aldy Hernandez <aldyh@redhat.com> 1276 Dave Brolley <brolley@redhat.com> 1277 Chris Demetriou <cgd@broadcom.com> 1278 1279 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. 1280 (sim_mach_default): New variable. 1281 (mips64vr-*-*, mips64vrel-*-*): New configurations. 1282 Add a new simulator generator, MULTI. 1283 * configure: Regenerate. 1284 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. 1285 (multi-run.o): New dependency. 1286 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. 1287 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. 1288 (tmp-multi): Combine them. 1289 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. 1290 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. 1291 (distclean-extra): New rule. 1292 * sim-main.h: Include bfd.h. 1293 (MIPS_MACH): New macro. 1294 * mips.igen (vr4120, vr5400, vr5500): New models. 1295 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. 1296 * vr.igen: Replace with new version. 1297 12982003-01-04 Chris Demetriou <cgd@broadcom.com> 1299 1300 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). 1301 * configure: Regenerate. 1302 13032002-12-31 Chris Demetriou <cgd@broadcom.com> 1304 1305 * sim-main.h (check_branch_bug, mark_branch_bug): Remove. 1306 * mips.igen: Remove all invocations of check_branch_bug and 1307 mark_branch_bug. 1308 13092002-12-16 Chris Demetriou <cgd@broadcom.com> 1310 1311 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h". 1312 13132002-07-30 Chris Demetriou <cgd@broadcom.com> 1314 1315 * mips.igen (do_load_double, do_store_double): New functions. 1316 (LDC1, SDC1): Rename to... 1317 (LDC1b, SDC1b): respectively. 1318 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support. 1319 13202002-07-29 Michael Snyder <msnyder@redhat.com> 1321 1322 * cp1.c (fp_recip2): Modify initialization expression so that 1323 GCC will recognize it as constant. 1324 13252002-06-18 Chris Demetriou <cgd@broadcom.com> 1326 1327 * mdmx.c (SD_): Delete. 1328 (Unpredictable): Re-define, for now, to directly invoke 1329 unpredictable_action(). 1330 (mdmx_acc_op): Fix error in .ob immediate handling. 1331 13322002-06-18 Andrew Cagney <cagney@redhat.com> 1333 1334 * interp.c (sim_firmware_command): Initialize `address'. 1335 13362002-06-16 Andrew Cagney <ac131313@redhat.com> 1337 1338 * configure: Regenerated to track ../common/aclocal.m4 changes. 1339 13402002-06-14 Chris Demetriou <cgd@broadcom.com> 1341 Ed Satterthwaite <ehs@broadcom.com> 1342 1343 * mips3d.igen: New file which contains MIPS-3D ASE instructions. 1344 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. 1345 * mips.igen: Include mips3d.igen. 1346 (mips3d): New model name for MIPS-3D ASE instructions. 1347 (CVT.W.fmt): Don't use this instruction for word (source) format 1348 instructions. 1349 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) 1350 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) 1351 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. 1352 (NR_FRAC_GUARD, IMPLICIT_1): New macros. 1353 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) 1354 (RSquareRoot1, RSquareRoot2): New macros. 1355 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) 1356 (fp_rsqrt2): New functions. 1357 * configure.in: Add MIPS-3D support to mipsisa64 simulator. 1358 * configure: Regenerate. 1359 13602002-06-13 Chris Demetriou <cgd@broadcom.com> 1361 Ed Satterthwaite <ehs@broadcom.com> 1362 1363 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. 1364 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) 1365 (fp_inv_sqrt, fpu_format_name): Add paired-single support. 1366 (convert): Note that this function is not used for paired-single 1367 format conversions. 1368 (ps_lower, ps_upper, pack_ps, convert_ps): New functions. 1369 * mips.igen (FMT, MOVtf.fmt): Add paired-single support. 1370 (check_fmt_p): Enable paired-single support. 1371 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) 1372 (PUU.PS): New instructions. 1373 (CVT.S.fmt): Don't use this instruction for paired-single format 1374 destinations. 1375 * sim-main.h (FP_formats): New value 'fmt_ps.' 1376 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. 1377 (PSLower, PSUpper, PackPS, ConvertPS): New macros. 1378 13792002-06-12 Chris Demetriou <cgd@broadcom.com> 1380 1381 * mips.igen: Fix formatting of function calls in 1382 many FP operations. 1383 13842002-06-12 Chris Demetriou <cgd@broadcom.com> 1385 1386 * mips.igen (MOVN, MOVZ): Trace result. 1387 (TNEI): Print "tnei" as the opcode name in traces. 1388 (CEIL.W): Add disassembly string for traces. 1389 (RSQRT.fmt): Make location of disassembly string consistent 1390 with other instructions. 1391 13922002-06-12 Chris Demetriou <cgd@broadcom.com> 1393 1394 * mips.igen (X): Delete unused function. 1395 13962002-06-08 Andrew Cagney <cagney@redhat.com> 1397 1398 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". 1399 14002002-06-07 Chris Demetriou <cgd@broadcom.com> 1401 Ed Satterthwaite <ehs@broadcom.com> 1402 1403 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) 1404 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. 1405 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) 1406 (fp_nmsub): New prototypes. 1407 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) 1408 (NegMultiplySub): New defines. 1409 * mips.igen (RSQRT.fmt): Use RSquareRoot(). 1410 (MADD.D, MADD.S): Replace with... 1411 (MADD.fmt): New instruction. 1412 (MSUB.D, MSUB.S): Replace with... 1413 (MSUB.fmt): New instruction. 1414 (NMADD.D, NMADD.S): Replace with... 1415 (NMADD.fmt): New instruction. 1416 (NMSUB.D, MSUB.S): Replace with... 1417 (NMSUB.fmt): New instruction. 1418 14192002-06-07 Chris Demetriou <cgd@broadcom.com> 1420 Ed Satterthwaite <ehs@broadcom.com> 1421 1422 * cp1.c: Fix more comment spelling and formatting. 1423 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. 1424 (denorm_mode): New function. 1425 (fpu_unary, fpu_binary): Round results after operation, collect 1426 status from rounding operations, and update the FCSR. 1427 (convert): Collect status from integer conversions and rounding 1428 operations, and update the FCSR. Adjust NaN values that result 1429 from conversions. Convert to use sim_io_eprintf rather than 1430 fprintf, and remove some debugging code. 1431 * cp1.h (fenr_FS): New define. 1432 14332002-06-07 Chris Demetriou <cgd@broadcom.com> 1434 1435 * cp1.c (convert): Remove unusable debugging code, and move MIPS 1436 rounding mode to sim FP rounding mode flag conversion code into... 1437 (rounding_mode): New function. 1438 14392002-06-07 Chris Demetriou <cgd@broadcom.com> 1440 1441 * cp1.c: Clean up formatting of a few comments. 1442 (value_fpr): Reformat switch statement. 1443 14442002-06-06 Chris Demetriou <cgd@broadcom.com> 1445 Ed Satterthwaite <ehs@broadcom.com> 1446 1447 * cp1.h: New file. 1448 * sim-main.h: Include cp1.h. 1449 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) 1450 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) 1451 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. 1452 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. 1453 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. 1454 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. 1455 * cp1.c: Don't include sim-fpu.h; already included by 1456 sim-main.h. Clean up formatting of some comments. 1457 (NaN, Equal, Less): Remove. 1458 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) 1459 (fp_cmp): New functions. 1460 * mips.igen (do_c_cond_fmt): Remove. 1461 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with 1462 Compare. Add result tracing. 1463 (CxC1): Remove, replace with... 1464 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. 1465 (DMxC1): Remove, replace with... 1466 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. 1467 (MxC1): Remove, replace with... 1468 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions. 1469 14702002-06-04 Chris Demetriou <cgd@broadcom.com> 1471 1472 * sim-main.h (FGRIDX): Remove, replace all uses with... 1473 (FGR_BASE): New macro. 1474 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. 1475 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. 1476 (NR_FGR, FGR): Likewise. 1477 * interp.c: Replace all uses of FGRIDX with FGR_BASE. 1478 * mips.igen: Likewise. 1479 14802002-06-04 Chris Demetriou <cgd@broadcom.com> 1481 1482 * cp1.c: Add an FSF Copyright notice to this file. 1483 14842002-06-04 Chris Demetriou <cgd@broadcom.com> 1485 Ed Satterthwaite <ehs@broadcom.com> 1486 1487 * cp1.c (Infinity): Remove. 1488 * sim-main.h (Infinity): Likewise. 1489 1490 * cp1.c (fp_unary, fp_binary): New functions. 1491 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) 1492 (fp_sqrt): New functions, implemented in terms of the above. 1493 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) 1494 (Recip, SquareRoot): Remove (replaced by functions above). 1495 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) 1496 (fp_recip, fp_sqrt): New prototypes. 1497 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) 1498 (Recip, SquareRoot): Replace prototypes with #defines which 1499 invoke the functions above. 1500 15012002-06-03 Chris Demetriou <cgd@broadcom.com> 1502 1503 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) 1504 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in 1505 file, remove PARAMS from prototypes. 1506 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide 1507 simulator state arguments. 1508 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to 1509 pass simulator state arguments. 1510 * cp1.c (SD): Redefine as CPU_STATE(cpu). 1511 (store_fpr, convert): Remove 'sd' argument. 1512 (value_fpr): Likewise. Convert to use 'SD' instead. 1513 15142002-06-03 Chris Demetriou <cgd@broadcom.com> 1515 1516 * cp1.c (Min, Max): Remove #if 0'd functions. 1517 * sim-main.h (Min, Max): Remove. 1518 15192002-06-03 Chris Demetriou <cgd@broadcom.com> 1520 1521 * cp1.c: fix formatting of switch case and default labels. 1522 * interp.c: Likewise. 1523 * sim-main.c: Likewise. 1524 15252002-06-03 Chris Demetriou <cgd@broadcom.com> 1526 1527 * cp1.c: Clean up comments which describe FP formats. 1528 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64. 1529 15302002-06-03 Chris Demetriou <cgd@broadcom.com> 1531 Ed Satterthwaite <ehs@broadcom.com> 1532 1533 * configure.in (mipsisa64sb1*-*-*): New target for supporting 1534 Broadcom SiByte SB-1 processor configurations. 1535 * configure: Regenerate. 1536 * sb1.igen: New file. 1537 * mips.igen: Include sb1.igen. 1538 (sb1): New model. 1539 * Makefile.in (IGEN_INCLUDE): Add sb1.igen. 1540 * mdmx.igen: Add "sb1" model to all appropriate functions and 1541 instructions. 1542 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. 1543 (ob_func, ob_acc): Reference the above. 1544 (qh_acc): Adjust to keep the same size as ob_acc. 1545 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) 1546 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros. 1547 15482002-06-03 Chris Demetriou <cgd@broadcom.com> 1549 1550 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. 1551 15522002-06-02 Chris Demetriou <cgd@broadcom.com> 1553 Ed Satterthwaite <ehs@broadcom.com> 1554 1555 * mips.igen (mdmx): New (pseudo-)model. 1556 * mdmx.c, mdmx.igen: New files. 1557 * Makefile.in (SIM_OBJS): Add mdmx.o. 1558 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): 1559 New typedefs. 1560 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) 1561 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) 1562 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) 1563 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) 1564 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) 1565 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) 1566 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) 1567 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) 1568 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) 1569 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) 1570 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) 1571 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) 1572 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) 1573 (qh_fmtsel): New macros. 1574 (_sim_cpu): New member "acc". 1575 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) 1576 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions. 1577 15782002-05-01 Chris Demetriou <cgd@broadcom.com> 1579 1580 * interp.c: Use 'deprecated' rather than 'depreciated.' 1581 * sim-main.h: Likewise. 1582 15832002-05-01 Chris Demetriou <cgd@broadcom.com> 1584 1585 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult 1586 which wouldn't compile anyway. 1587 * sim-main.h (unpredictable_action): New function prototype. 1588 (Unpredictable): Define to call igen function unpredictable(). 1589 (NotWordValue): New macro to call igen function not_word_value(). 1590 (UndefinedResult): Remove. 1591 * interp.c (undefined_result): Remove. 1592 (unpredictable_action): New function. 1593 * mips.igen (not_word_value, unpredictable): New functions. 1594 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) 1595 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) 1596 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke 1597 NotWordValue() to check for unpredictable inputs, then 1598 Unpredictable() to handle them. 1599 16002002-02-24 Chris Demetriou <cgd@broadcom.com> 1601 1602 * mips.igen: Fix formatting of calls to Unpredictable(). 1603 16042002-04-20 Andrew Cagney <ac131313@redhat.com> 1605 1606 * interp.c (sim_open): Revert previous change. 1607 16082002-04-18 Alexandre Oliva <aoliva@redhat.com> 1609 1610 * interp.c (sim_open): Disable chunk of code that wrote code in 1611 vector table entries. 1612 16132002-03-19 Chris Demetriou <cgd@broadcom.com> 1614 1615 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f) 1616 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove 1617 unused definitions. 1618 16192002-03-19 Chris Demetriou <cgd@broadcom.com> 1620 1621 * cp1.c: Fix many formatting issues. 1622 16232002-03-19 Chris G. Demetriou <cgd@broadcom.com> 1624 1625 * cp1.c (fpu_format_name): New function to replace... 1626 (DOFMT): This. Delete, and update all callers. 1627 (fpu_rounding_mode_name): New function to replace... 1628 (RMMODE): This. Delete, and update all callers. 1629 16302002-03-19 Chris G. Demetriou <cgd@broadcom.com> 1631 1632 * interp.c: Move FPU support routines from here to... 1633 * cp1.c: Here. New file. 1634 * Makefile.in (SIM_OBJS): Add cp1.o to object list. 1635 (cp1.o): New target. 1636 16372002-03-12 Chris Demetriou <cgd@broadcom.com> 1638 1639 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. 1640 * mips.igen (mips32, mips64): New models, add to all instructions 1641 and functions as appropriate. 1642 (loadstore_ea, check_u64): New variant for model mips64. 1643 (check_fmt_p): New variant for models mipsV and mips64, remove 1644 mipsV model marking fro other variant. 1645 (SLL) Rename to... 1646 (SLLa) this. 1647 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions 1648 for mips32 and mips64. 1649 (DCLO, DCLZ): New instructions for mips64. 1650 16512002-03-07 Chris Demetriou <cgd@broadcom.com> 1652 1653 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print 1654 immediate or code as a hex value with the "%#lx" format. 1655 (ANDI): Likewise, and fix printed instruction name. 1656 16572002-03-05 Chris Demetriou <cgd@broadcom.com> 1658 1659 * sim-main.h (UndefinedResult, Unpredictable): New macros 1660 which currently do nothing. 1661 16622002-03-05 Chris Demetriou <cgd@broadcom.com> 1663 1664 * sim-main.h (status_UX, status_SX, status_KX, status_TS) 1665 (status_PX, status_MX, status_CU0, status_CU1, status_CU2) 1666 (status_CU3): New definitions. 1667 1668 * sim-main.h (ExceptionCause): Add new values for MIPS32 1669 and MIPS64: MDMX, MCheck, CacheErr. Update comments 1670 for DebugBreakPoint and NMIReset to note their status in 1671 MIPS32 and MIPS64. 1672 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) 1673 (SignalExceptionCacheErr): New exception macros. 1674 16752002-03-05 Chris Demetriou <cgd@broadcom.com> 1676 1677 * mips.igen (check_fpu): Enable check for coprocessor 1 usability. 1678 * sim-main.h (COP_Usable): Define, but for now coprocessor 1 1679 is always enabled. 1680 (SignalExceptionCoProcessorUnusable): Take as argument the 1681 unusable coprocessor number. 1682 16832002-03-05 Chris Demetriou <cgd@broadcom.com> 1684 1685 * mips.igen: Fix formatting of all SignalException calls. 1686 16872002-03-05 Chris Demetriou <cgd@broadcom.com> 1688 1689 * sim-main.h (SIGNEXTEND): Remove. 1690 16912002-03-04 Chris Demetriou <cgd@broadcom.com> 1692 1693 * mips.igen: Remove gencode comment from top of file, fix 1694 spelling in another comment. 1695 16962002-03-04 Chris Demetriou <cgd@broadcom.com> 1697 1698 * mips.igen (check_fmt, check_fmt_p): New functions to check 1699 whether specific floating point formats are usable. 1700 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) 1701 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) 1702 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): 1703 Use the new functions. 1704 (do_c_cond_fmt): Remove format checks... 1705 (C.cond.fmta, C.cond.fmtb): And move them into all callers. 1706 17072002-03-03 Chris Demetriou <cgd@broadcom.com> 1708 1709 * mips.igen: Fix formatting of check_fpu calls. 1710 17112002-03-03 Chris Demetriou <cgd@broadcom.com> 1712 1713 * mips.igen (FLOOR.L.fmt): Store correct destination register. 1714 17152002-03-03 Chris Demetriou <cgd@broadcom.com> 1716 1717 * mips.igen: Remove whitespace at end of lines. 1718 17192002-03-02 Chris Demetriou <cgd@broadcom.com> 1720 1721 * mips.igen (loadstore_ea): New function to do effective 1722 address calculations. 1723 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, 1724 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, 1725 CACHE): Use loadstore_ea to do effective address computations. 1726 17272002-03-02 Chris Demetriou <cgd@broadcom.com> 1728 1729 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. 1730 * mips.igen (LL, CxC1, MxC1): Likewise. 1731 17322002-03-02 Chris Demetriou <cgd@broadcom.com> 1733 1734 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, 1735 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, 1736 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, 1737 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, 1738 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, 1739 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): 1740 Don't split opcode fields by hand, use the opcode field values 1741 provided by igen. 1742 17432002-03-01 Chris Demetriou <cgd@broadcom.com> 1744 1745 * mips.igen (do_divu): Fix spacing. 1746 1747 * mips.igen (do_dsllv): Move to be right before DSLLV, 1748 to match the rest of the do_<shift> functions. 1749 17502002-03-01 Chris Demetriou <cgd@broadcom.com> 1751 1752 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, 1753 DSRL32, do_dsrlv): Trace inputs and results. 1754 17552002-03-01 Chris Demetriou <cgd@broadcom.com> 1756 1757 * mips.igen (CACHE): Provide instruction-printing string. 1758 1759 * interp.c (signal_exception): Comment tokens after #endif. 1760 17612002-02-28 Chris Demetriou <cgd@broadcom.com> 1762 1763 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32". 1764 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, 1765 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, 1766 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, 1767 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, 1768 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, 1769 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, 1770 LWC1, SWC1): Add "f" to filter, since these are FP instructions. 1771 17722002-02-28 Chris Demetriou <cgd@broadcom.com> 1773 1774 * mips.igen (DSRA32, DSRAV): Fix order of arguments in 1775 instruction-printing string. 1776 (LWU): Use '64' as the filter flag. 1777 17782002-02-28 Chris Demetriou <cgd@broadcom.com> 1779 1780 * mips.igen (SDXC1): Fix instruction-printing string. 1781 17822002-02-28 Chris Demetriou <cgd@broadcom.com> 1783 1784 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with 1785 filter flags "32,f". 1786 17872002-02-27 Chris Demetriou <cgd@broadcom.com> 1788 1789 * mips.igen (PREFX): This is a 64-bit instruction, use '64' 1790 as the filter flag. 1791 17922002-02-27 Chris Demetriou <cgd@broadcom.com> 1793 1794 * mips.igen (PREFX): Tweak instruction opcode fields (i.e., 1795 add a comma) so that it more closely match the MIPS ISA 1796 documentation opcode partitioning. 1797 (PREF): Put useful names on opcode fields, and include 1798 instruction-printing string. 1799 18002002-02-27 Chris Demetriou <cgd@broadcom.com> 1801 1802 * mips.igen (check_u64): New function which in the future will 1803 check whether 64-bit instructions are usable and signal an 1804 exception if not. Currently a no-op. 1805 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, 1806 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, 1807 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, 1808 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. 1809 1810 * mips.igen (check_fpu): New function which in the future will 1811 check whether FPU instructions are usable and signal an exception 1812 if not. Currently a no-op. 1813 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, 1814 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, 1815 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, 1816 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, 1817 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, 1818 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, 1819 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, 1820 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu. 1821 18222002-02-27 Chris Demetriou <cgd@broadcom.com> 1823 1824 * mips.igen (do_load_left, do_load_right): Move to be immediately 1825 following do_load. 1826 (do_store_left, do_store_right): Move to be immediately following 1827 do_store. 1828 18292002-02-27 Chris Demetriou <cgd@broadcom.com> 1830 1831 * mips.igen (mipsV): New model name. Also, add it to 1832 all instructions and functions where it is appropriate. 1833 18342002-02-18 Chris Demetriou <cgd@broadcom.com> 1835 1836 * mips.igen: For all functions and instructions, list model 1837 names that support that instruction one per line. 1838 18392002-02-11 Chris Demetriou <cgd@broadcom.com> 1840 1841 * mips.igen: Add some additional comments about supported 1842 models, and about which instructions go where. 1843 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same 1844 order as is used in the rest of the file. 1845 18462002-02-11 Chris Demetriou <cgd@broadcom.com> 1847 1848 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment 1849 indicating that ALU32_END or ALU64_END are there to check 1850 for overflow. 1851 (DADD): Likewise, but also remove previous comment about 1852 overflow checking. 1853 18542002-02-10 Chris Demetriou <cgd@broadcom.com> 1855 1856 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, 1857 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, 1858 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, 1859 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, 1860 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode 1861 fields (i.e., add and move commas) so that they more closely 1862 match the MIPS ISA documentation opcode partitioning. 1863 18642002-02-10 Chris Demetriou <cgd@broadcom.com> 1865 1866 * mips.igen (ADDI): Print immediate value. 1867 (BREAK): Print code. 1868 (DADDIU, DSRAV, DSRLV): Print correct instruction name. 1869 (SLL): Print "nop" specially, and don't run the code 1870 that does the shift for the "nop" case. 1871 18722001-11-17 Fred Fish <fnf@redhat.com> 1873 1874 * sim-main.h (float_operation): Move enum declaration outside 1875 of _sim_cpu struct declaration. 1876 18772001-04-12 Jim Blandy <jimb@redhat.com> 1878 1879 * mips.igen (CFC1, CTC1): Pass the correct register numbers to 1880 PENDING_FILL. Use PENDING_SCHED directly to handle the pending 1881 set of the FCSR. 1882 * sim-main.h (COCIDX): Remove definition; this isn't supported by 1883 PENDING_FILL, and you can get the intended effect gracefully by 1884 calling PENDING_SCHED directly. 1885 18862001-02-23 Ben Elliston <bje@redhat.com> 1887 1888 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not 1889 already defined elsewhere. 1890 18912001-02-19 Ben Elliston <bje@redhat.com> 1892 1893 * sim-main.h (sim_monitor): Return an int. 1894 * interp.c (sim_monitor): Add return values. 1895 (signal_exception): Handle error conditions from sim_monitor. 1896 18972001-02-08 Ben Elliston <bje@redhat.com> 1898 1899 * sim-main.c (load_memory): Pass cia to sim_core_read* functions. 1900 (store_memory): Likewise, pass cia to sim_core_write*. 1901 19022000-10-19 Frank Ch. Eigler <fche@redhat.com> 1903 1904 On advice from Chris G. Demetriou <cgd@sibyte.com>: 1905 * sim-main.h (GPR_CLEAR): Remove unused alternative macro. 1906 1907Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com> 1908 1909 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>: 1910 * Makefile.in: Don't delete *.igen when cleaning directory. 1911 1912Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com> 1913 1914 * m16.igen (break): Call SignalException not sim_engine_halt. 1915 1916Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com> 1917 1918 From Jason Eckhardt: 1919 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT]. 1920 1921Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com> 1922 1923 * mips.igen (MxC1, DMxC1): Fix printf formatting. 1924 19252000-05-24 Michael Hayes <mhayes@cygnus.com> 1926 1927 * mips.igen (do_dmultx): Fix typo. 1928 1929Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> 1930 1931 * configure: Regenerated to track ../common/aclocal.m4 changes. 1932 1933Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com> 1934 1935 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. 1936 19372000-04-12 Frank Ch. Eigler <fche@redhat.com> 1938 1939 * sim-main.h (GPR_CLEAR): Define macro. 1940 1941Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com> 1942 1943 * interp.c (decode_coproc): Output long using %lx and not %s. 1944 19452000-03-21 Frank Ch. Eigler <fche@redhat.com> 1946 1947 * interp.c (sim_open): Sort & extend dummy memory regions for 1948 --board=jmr3904 for eCos. 1949 19502000-03-02 Frank Ch. Eigler <fche@redhat.com> 1951 1952 * configure: Regenerated. 1953 1954Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> 1955 1956 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf 1957 calls, conditional on the simulator being in verbose mode. 1958 1959Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com> 1960 1961 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary 1962 cache don't get ReservedInstruction traps. 1963 19641999-11-29 Mark Salter <msalter@cygnus.com> 1965 1966 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask 1967 to clear status bits in sdisr register. This is how the hardware works. 1968 1969 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware 1970 being used by cygmon. 1971 19721999-11-11 Andrew Haley <aph@cygnus.com> 1973 1974 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 1975 instructions. 1976 1977Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com> 1978 1979 * mips.igen (MULT): Correct previous mis-applied patch. 1980 1981Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com> 1982 1983 * mips.igen (delayslot32): Handle sequence like 1984 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12 1985 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue. 1986 (MULT): Actually pass the third register... 1987 19881999-09-03 Mark Salter <msalter@cygnus.com> 1989 1990 * interp.c (sim_open): Added more memory aliases for additional 1991 hardware being touched by cygmon on jmr3904 board. 1992 1993Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> 1994 1995 * configure: Regenerated to track ../common/aclocal.m4 changes. 1996 1997Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com> 1998 1999 * interp.c (sim_store_register): Handle case where client - GDB - 2000 specifies that a 4 byte register is 8 bytes in size. 2001 (sim_fetch_register): Ditto. 2002 20031999-07-14 Frank Ch. Eigler <fche@cygnus.com> 2004 2005 Implement "sim firmware" option, inspired by jimb's version of 1998-01. 2006 * interp.c (firmware_option_p): New global flag: "sim firmware" given. 2007 (idt_monitor_base): Base address for IDT monitor traps. 2008 (pmon_monitor_base): Ditto for PMON. 2009 (lsipmon_monitor_base): Ditto for LSI PMON. 2010 (MONITOR_BASE, MONITOR_SIZE): Removed macros. 2011 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key. 2012 (sim_firmware_command): New function. 2013 (mips_option_handler): Call it for OPTION_FIRMWARE. 2014 (sim_open): Allocate memory for idt_monitor region. If "--board" 2015 option was given, add no monitor by default. Add BREAK hooks only if 2016 monitors are also there. 2017 2018Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com> 2019 2020 * interp.c (sim_monitor): Flush output before reading input. 2021 2022Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com> 2023 2024 * tconfig.in (SIM_HANDLES_LMA): Always define. 2025 2026Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com> 2027 2028 From Mark Salter <msalter@cygnus.com>: 2029 * interp.c (BOARD_BSP): Define. Add to list of possible boards. 2030 (sim_open): Add setup for BSP board. 2031 2032Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com> 2033 2034 * mips.igen (MULT, MULTU): Add syntax for two operand version. 2035 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report 2036 them as unimplemented. 2037 20381999-05-08 Felix Lee <flee@cygnus.com> 2039 2040 * configure: Regenerated to track ../common/aclocal.m4 changes. 2041 20421999-04-21 Frank Ch. Eigler <fche@cygnus.com> 2043 2044 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. 2045 2046Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com> 2047 2048 * configure.in: Any mips64vr5*-*-* target should have 2049 -DTARGET_ENABLE_FR=1. 2050 (default_endian): Any mips64vr*el-*-* target should default to 2051 LITTLE_ENDIAN. 2052 * configure: Re-generate. 2053 20541999-02-19 Gavin Romig-Koch <gavin@cygnus.com> 2055 2056 * mips.igen (ldl): Extend from _16_, not 32. 2057 2058Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com> 2059 2060 * interp.c (sim_store_register): Force registers written to by GDB 2061 into an un-interpreted state. 2062 20631999-02-05 Frank Ch. Eigler <fche@cygnus.com> 2064 2065 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the 2066 CPU, start periodic background I/O polls. 2067 (tx3904sio_poll): New function: periodic I/O poller. 2068 20691998-12-30 Frank Ch. Eigler <fche@cygnus.com> 2070 2071 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. 2072 2073Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> 2074 2075 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in 2076 case statement. 2077 20781998-12-29 Frank Ch. Eigler <fche@cygnus.com> 2079 2080 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. 2081 (load_word): Call SIM_CORE_SIGNAL hook on error. 2082 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before 2083 starting. For exception dispatching, pass PC instead of NULL_CIA. 2084 (decode_coproc): Use COP0_BADVADDR to store faulting address. 2085 * sim-main.h (COP0_BADVADDR): Define. 2086 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. 2087 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). 2088 (_sim_cpu): Add exc_* fields to store register value snapshots. 2089 * mips.igen (*): Replace memory-related SignalException* calls 2090 with references to SIM_CORE_SIGNAL hook. 2091 2092 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning 2093 fix. 2094 * sim-main.c (*): Minor warning cleanups. 2095 20961998-12-24 Gavin Romig-Koch <gavin@cygnus.com> 2097 2098 * m16.igen (DADDIU5): Correct type-o. 2099 2100Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook> 2101 2102 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp 2103 variables. 2104 2105Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook> 2106 2107 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib 2108 to include path. 2109 (interp.o): Add dependency on itable.h 2110 (oengine.c, gencode): Delete remaining references. 2111 (BUILT_SRC_FROM_GEN): Clean up. 2112 21131998-12-16 Gavin Romig-Koch <gavin@cygnus.com> 2114 2115 * vr4run.c: New. 2116 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, 2117 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, 2118 tmp-run-hack) : New. 2119 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, 2120 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): 2121 Drop the "64" qualifier to get the HACK generator working. 2122 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. 2123 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only 2124 qualifier to get the hack generator working. 2125 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. 2126 (DSLL): Use do_dsll. 2127 (DSLLV): Use do_dsllv. 2128 (DSRA): Use do_dsra. 2129 (DSRL): Use do_dsrl. 2130 (DSRLV): Use do_dsrlv. 2131 (BC1): Move *vr4100 to get the HACK generator working. 2132 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to 2133 get the HACK generator working. 2134 (MACC) Rename to get the HACK generator working. 2135 (DMACC,MACCS,DMACCS): Add the 64. 2136 21371998-12-12 Gavin Romig-Koch <gavin@cygnus.com> 2138 2139 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. 2140 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. 2141 21421998-12-11 Gavin Romig-Koch <gavin@cygnus.com> 2143 2144 * mips/interp.c (DEBUG): Cleanups. 2145 21461998-12-10 Frank Ch. Eigler <fche@cygnus.com> 2147 2148 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. 2149 (tx3904sio_tickle): fflush after a stdout character output. 2150 21511998-12-03 Frank Ch. Eigler <fche@cygnus.com> 2152 2153 * interp.c (sim_close): Uninstall modules. 2154 2155Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com> 2156 2157 * sim-main.h, interp.c (sim_monitor): Change to global 2158 function. 2159 2160Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com> 2161 2162 * configure.in (vr4100): Only include vr4100 instructions in 2163 simulator. 2164 * configure: Re-generate. 2165 * m16.igen (*): Tag all mips16 instructions as also being vr4100. 2166 2167Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com> 2168 2169 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. 2170 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping 2171 true alternative. 2172 2173 * configure.in (sim_default_gen, sim_use_gen): Replace with 2174 sim_gen. 2175 (--enable-sim-igen): Delete config option. Always using IGEN. 2176 * configure: Re-generate. 2177 2178 * Makefile.in (gencode): Kill, kill, kill. 2179 * gencode.c: Ditto. 2180 2181Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com> 2182 2183 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 2184 bit mips16 igen simulator. 2185 * configure: Re-generate. 2186 2187 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark 2188 as part of vr4100 ISA. 2189 * vr.igen: Mark all instructions as 64 bit only. 2190 2191Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 2192 2193 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): 2194 Pacify GCC. 2195 2196Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com> 2197 2198 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a 2199 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. 2200 * configure: Re-generate. 2201 2202 * m16.igen (BREAK): Define breakpoint instruction. 2203 (JALX32): Mark instruction as mips16 and not r3900. 2204 * mips.igen (C.cond.fmt): Fix typo in instruction format. 2205 2206 * sim-main.h (PENDING_FILL): Wrap C statements in do/while. 2207 2208Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> 2209 2210 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK 2211 insn as a debug breakpoint. 2212 2213 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as 2214 pending.slot_size. 2215 (PENDING_SCHED): Clean up trace statement. 2216 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. 2217 (PENDING_FILL): Delay write by only one cycle. 2218 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. 2219 2220 * sim-main.c (pending_tick): Clean up trace statements. Add trace 2221 of pending writes. 2222 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of 2223 32 & 64. 2224 (pending_tick): Move incrementing of index to FOR statement. 2225 (pending_tick): Only update PENDING_OUT after a write has occured. 2226 2227 * configure.in: Add explicit mips-lsi-* target. Use gencode to 2228 build simulator. 2229 * configure: Re-generate. 2230 2231 * interp.c (sim_engine_run OLD): Delete explicit call to 2232 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. 2233 2234Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> 2235 2236 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy 2237 interrupt level number to match changed SignalExceptionInterrupt 2238 macro. 2239 2240Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> 2241 2242 * interp.c: #include "itable.h" if WITH_IGEN. 2243 (get_insn_name): New function. 2244 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. 2245 * sim-main.h (MAX_INSNS,INSN_NAME): Delete. 2246 2247Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> 2248 2249 * configure: Rebuilt to inhale new common/aclocal.m4. 2250 2251Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> 2252 2253 * dv-tx3904sio.c: Include sim-assert.h. 2254 2255Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> 2256 2257 * dv-tx3904sio.c: New file: tx3904 serial I/O module. 2258 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. 2259 Reorganize target-specific sim-hardware checks. 2260 * configure: rebuilt. 2261 * interp.c (sim_open): For tx39 target boards, set 2262 OPERATING_ENVIRONMENT, add tx3904sio devices. 2263 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading 2264 ROM executables. Install dv-sockser into sim-modules list. 2265 2266 * dv-tx3904irc.c: Compiler warning clean-up. 2267 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly 2268 frequent hw-trace messages. 2269 2270Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> 2271 2272 * vr.igen (MulAcc): Identify as a vr4100 specific function. 2273 2274Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> 2275 2276 * Makefile.in (IGEN_INCLUDE): Add vr.igen. 2277 2278 * vr.igen: New file. 2279 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. 2280 * mips.igen: Define vr4100 model. Include vr.igen. 2281Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> 2282 2283 * mips.igen (check_mf_hilo): Correct check. 2284 2285Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> 2286 2287 * sim-main.h (interrupt_event): Add prototype. 2288 2289 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused 2290 register_ptr, register_value. 2291 (deliver_tx3904tmr_tick): Fix types passed to printf fmt. 2292 2293 * sim-main.h (tracefh): Make extern. 2294 2295Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> 2296 2297 * dv-tx3904tmr.c: Deschedule timer event after dispatching. 2298 Reduce unnecessarily high timer event frequency. 2299 * dv-tx3904cpu.c: Ditto for interrupt event. 2300 2301Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> 2302 2303 * interp.c (decode_coproc): For TX39, add stub COP0 register #7, 2304 to allay warnings. 2305 (interrupt_event): Made non-static. 2306 2307 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental 2308 interchange of configuration values for external vs. internal 2309 clock dividers. 2310 2311Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> 2312 2313 * mips.igen (BREAK): Moved code to here for 2314 simulator-reserved break instructions. 2315 * gencode.c (build_instruction): Ditto. 2316 * interp.c (signal_exception): Code moved from here. Non- 2317 reserved instructions now use exception vector, rather 2318 than halting sim. 2319 * sim-main.h: Moved magic constants to here. 2320 2321Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> 2322 2323 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE 2324 register upon non-zero interrupt event level, clear upon zero 2325 event value. 2326 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal 2327 by passing zero event value. 2328 (*_io_{read,write}_buffer): Endianness fixes. 2329 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. 2330 (deliver_*_tick): Reduce sim event interval to 75% of count interval. 2331 2332 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based 2333 serial I/O and timer module at base address 0xFFFF0000. 2334 2335Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> 2336 2337 * mips.igen (SWC1) : Correct the handling of ReverseEndian 2338 and BigEndianCPU. 2339 2340Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> 2341 2342 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips 2343 parts. 2344 * configure: Update. 2345 2346Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> 2347 2348 * dv-tx3904tmr.c: New file - implements tx3904 timer. 2349 * dv-tx3904{irc,cpu}.c: Mild reformatting. 2350 * configure.in: Include tx3904tmr in hw_device list. 2351 * configure: Rebuilt. 2352 * interp.c (sim_open): Instantiate three timer instances. 2353 Fix address typo of tx3904irc instance. 2354 2355Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> 2356 2357 * interp.c (signal_exception): SystemCall exception now uses 2358 the exception vector. 2359 2360Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> 2361 2362 * interp.c (decode_coproc): For TX39, add stub COP0 register #3, 2363 to allay warnings. 2364 2365Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> 2366 2367 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. 2368 2369Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> 2370 2371 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. 2372 2373 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and 2374 sim-main.h. Declare a struct hw_descriptor instead of struct 2375 hw_device_descriptor. 2376 2377Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> 2378 2379 * mips.igen (do_store_left, do_load_left): Compute nr of left and 2380 right bits and then re-align left hand bytes to correct byte 2381 lanes. Fix incorrect computation in do_store_left when loading 2382 bytes from second word. 2383 2384Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> 2385 2386 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. 2387 * interp.c (sim_open): Only create a device tree when HW is 2388 enabled. 2389 2390 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. 2391 * interp.c (signal_exception): Ditto. 2392 2393Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> 2394 2395 * gencode.c: Mark BEGEZALL as LIKELY. 2396 2397Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> 2398 2399 * sim-main.h (ALU32_END): Sign extend 32 bit results. 2400 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. 2401 2402Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> 2403 2404 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware 2405 modules. Recognize TX39 target with "mips*tx39" pattern. 2406 * configure: Rebuilt. 2407 * sim-main.h (*): Added many macros defining bits in 2408 TX39 control registers. 2409 (SignalInterrupt): Send actual PC instead of NULL. 2410 (SignalNMIReset): New exception type. 2411 * interp.c (board): New variable for future use to identify 2412 a particular board being simulated. 2413 (mips_option_handler,mips_options): Added "--board" option. 2414 (interrupt_event): Send actual PC. 2415 (sim_open): Make memory layout conditional on board setting. 2416 (signal_exception): Initial implementation of hardware interrupt 2417 handling. Accept another break instruction variant for simulator 2418 exit. 2419 (decode_coproc): Implement RFE instruction for TX39. 2420 (mips.igen): Decode RFE instruction as such. 2421 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. 2422 * interp.c: Define "jmr3904" and "jmr3904debug" board types and 2423 bbegin to implement memory map. 2424 * dv-tx3904cpu.c: New file. 2425 * dv-tx3904irc.c: New file. 2426 2427Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> 2428 2429 * mips.igen (check_mt_hilo): Create a separate r3900 version. 2430 2431Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> 2432 2433 * tx.igen (madd,maddu): Replace calls to check_op_hilo 2434 with calls to check_div_hilo. 2435 2436Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> 2437 2438 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): 2439 Replace check_op_hilo with check_mult_hilo and check_div_hilo. 2440 Add special r3900 version of do_mult_hilo. 2441 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo 2442 with calls to check_mult_hilo. 2443 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo 2444 with calls to check_div_hilo. 2445 2446Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> 2447 2448 * configure.in (SUBTARGET_R3900): Define for mipstx39 target. 2449 Document a replacement. 2450 2451Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> 2452 2453 * interp.c (sim_monitor): Make mon_printf work. 2454 2455Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> 2456 2457 * sim-main.h (INSN_NAME): New arg `cpu'. 2458 2459Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> 2460 2461 * configure: Regenerated to track ../common/aclocal.m4 changes. 2462 2463Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> 2464 2465 * configure: Regenerated to track ../common/aclocal.m4 changes. 2466 * config.in: Ditto. 2467 2468Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> 2469 2470 * acconfig.h: New file. 2471 * configure.in: Reverted change of Apr 24; use sinclude again. 2472 2473Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> 2474 2475 * configure: Regenerated to track ../common/aclocal.m4 changes. 2476 * config.in: Ditto. 2477 2478Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> 2479 2480 * configure.in: Don't call sinclude. 2481 2482Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> 2483 2484 * mips.igen (do_store_left): Pass 0 not NULL to store_memory. 2485 2486Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 2487 2488 * mips.igen (ERET): Implement. 2489 2490 * interp.c (decode_coproc): Return sign-extended EPC. 2491 2492 * mips.igen (ANDI, LUI, MFC0): Add tracing code. 2493 2494 * interp.c (signal_exception): Do not ignore Trap. 2495 (signal_exception): On TRAP, restart at exception address. 2496 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. 2497 (signal_exception): Update. 2498 (sim_open): Patch V_COMMON interrupt vector with an abort sequence 2499 so that TRAP instructions are caught. 2500 2501Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> 2502 2503 * sim-main.h (struct hilo_access, struct hilo_history): Define, 2504 contains HI/LO access history. 2505 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. 2506 (HIACCESS, LOACCESS): Delete, replace with 2507 (HIHISTORY, LOHISTORY): New macros. 2508 (CHECKHILO): Delete all, moved to mips.igen 2509 2510 * gencode.c (build_instruction): Do not generate checks for 2511 correct HI/LO register usage. 2512 2513 * interp.c (old_engine_run): Delete checks for correct HI/LO 2514 register usage. 2515 2516 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, 2517 check_mf_cycles): New functions. 2518 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, 2519 do_divu, domultx, do_mult, do_multu): Use. 2520 2521 * tx.igen ("madd", "maddu"): Use. 2522 2523Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> 2524 2525 * mips.igen (DSRAV): Use function do_dsrav. 2526 (SRAV): Use new function do_srav. 2527 2528 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. 2529 (B): Sign extend 11 bit immediate. 2530 (EXT-B*): Shift 16 bit immediate left by 1. 2531 (ADDIU*): Don't sign extend immediate value. 2532 2533Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> 2534 2535 * m16run.c (sim_engine_run): Restore CIA after handling an event. 2536 2537 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use 2538 functions. 2539 2540 * mips.igen (delayslot32, nullify_next_insn): New functions. 2541 (m16.igen): Always include. 2542 (do_*): Add more tracing. 2543 2544 * m16.igen (delayslot16): Add NIA argument, could be called by a 2545 32 bit MIPS16 instruction. 2546 2547 * interp.c (ifetch16): Move function from here. 2548 * sim-main.c (ifetch16): To here. 2549 2550 * sim-main.c (ifetch16, ifetch32): Update to match current 2551 implementations of LH, LW. 2552 (signal_exception): Don't print out incorrect hex value of illegal 2553 instruction. 2554 2555Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> 2556 2557 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an 2558 instruction. 2559 2560 * m16.igen: Implement MIPS16 instructions. 2561 2562 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, 2563 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, 2564 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, 2565 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, 2566 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move 2567 bodies of corresponding code from 32 bit insn to these. Also used 2568 by MIPS16 versions of functions. 2569 2570 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. 2571 (IMEM16): Drop NR argument from macro. 2572 2573Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 2574 2575 * Makefile.in (SIM_OBJS): Add sim-main.o. 2576 2577 * sim-main.h (address_translation, load_memory, store_memory, 2578 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark 2579 as INLINE_SIM_MAIN. 2580 (pr_addr, pr_uword64): Declare. 2581 (sim-main.c): Include when H_REVEALS_MODULE_P. 2582 2583 * interp.c (address_translation, load_memory, store_memory, 2584 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move 2585 from here. 2586 * sim-main.c: To here. Fix compilation problems. 2587 2588 * configure.in: Enable inlining. 2589 * configure: Re-config. 2590 2591Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> 2592 2593 * configure: Regenerated to track ../common/aclocal.m4 changes. 2594 2595Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> 2596 2597 * mips.igen: Include tx.igen. 2598 * Makefile.in (IGEN_INCLUDE): Add tx.igen. 2599 * tx.igen: New file, contains MADD and MADDU. 2600 2601 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not 2602 the hardwired constant `7'. 2603 (store_memory): Ditto. 2604 (LOADDRMASK): Move definition to sim-main.h. 2605 2606 mips.igen (MTC0): Enable for r3900. 2607 (ADDU): Add trace. 2608 2609 mips.igen (do_load_byte): Delete. 2610 (do_load, do_store, do_load_left, do_load_write, do_store_left, 2611 do_store_right): New functions. 2612 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. 2613 2614 configure.in: Let the tx39 use igen again. 2615 configure: Update. 2616 2617Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> 2618 2619 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, 2620 not an address sized quantity. Return zero for cache sizes. 2621 2622Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> 2623 2624 * mips.igen (r3900): r3900 does not support 64 bit integer 2625 operations. 2626 2627Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> 2628 2629 * configure.in (mipstx39*-*-*): Use gencode simulator rather 2630 than igen one. 2631 * configure : Rebuild. 2632 2633Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> 2634 2635 * configure: Regenerated to track ../common/aclocal.m4 changes. 2636 2637Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 2638 2639 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. 2640 2641Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> 2642 2643 * configure: Regenerated to track ../common/aclocal.m4 changes. 2644 * config.in: Regenerated to track ../common/aclocal.m4 changes. 2645 2646Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> 2647 2648 * configure: Regenerated to track ../common/aclocal.m4 changes. 2649 2650Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> 2651 2652 * interp.c (Max, Min): Comment out functions. Not yet used. 2653 2654Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> 2655 2656 * configure: Regenerated to track ../common/aclocal.m4 changes. 2657 2658Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> 2659 2660 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added 2661 configurable settings for stand-alone simulator. 2662 2663 * configure.in: Added X11 search, just in case. 2664 2665 * configure: Regenerated. 2666 2667Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> 2668 2669 * interp.c (sim_write, sim_read, load_memory, store_memory): 2670 Replace sim_core_*_map with read_map, write_map, exec_map resp. 2671 2672Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> 2673 2674 * sim-main.h (GETFCC): Return an unsigned value. 2675 2676Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 2677 2678 * mips.igen (DIV): Fix check for -1 / MIN_INT. 2679 (DADD): Result destination is RD not RT. 2680 2681Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> 2682 2683 * sim-main.h (HIACCESS, LOACCESS): Always define. 2684 2685 * mdmx.igen (Maxi, Mini): Rename Max, Min. 2686 2687 * interp.c (sim_info): Delete. 2688 2689Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> 2690 2691 * interp.c (DECLARE_OPTION_HANDLER): Use it. 2692 (mips_option_handler): New argument `cpu'. 2693 (sim_open): Update call to sim_add_option_table. 2694 2695Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> 2696 2697 * mips.igen (CxC1): Add tracing. 2698 2699Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> 2700 2701 * sim-main.h (Max, Min): Declare. 2702 2703 * interp.c (Max, Min): New functions. 2704 2705 * mips.igen (BC1): Add tracing. 2706 2707Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> 2708 2709 * interp.c Added memory map for stack in vr4100 2710 2711Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> 2712 2713 * interp.c (load_memory): Add missing "break"'s. 2714 2715Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> 2716 2717 * interp.c (sim_store_register, sim_fetch_register): Pass in 2718 length parameter. Return -1. 2719 2720Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> 2721 2722 * interp.c: Added hardware init hook, fixed warnings. 2723 2724Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> 2725 2726 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. 2727 2728Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> 2729 2730 * interp.c (ifetch16): New function. 2731 2732 * sim-main.h (IMEM32): Rename IMEM. 2733 (IMEM16_IMMED): Define. 2734 (IMEM16): Define. 2735 (DELAY_SLOT): Update. 2736 2737 * m16run.c (sim_engine_run): New file. 2738 2739 * m16.igen: All instructions except LB. 2740 (LB): Call do_load_byte. 2741 * mips.igen (do_load_byte): New function. 2742 (LB): Call do_load_byte. 2743 2744 * mips.igen: Move spec for insn bit size and high bit from here. 2745 * Makefile.in (tmp-igen, tmp-m16): To here. 2746 2747 * m16.dc: New file, decode mips16 instructions. 2748 2749 * Makefile.in (SIM_NO_ALL): Define. 2750 (tmp-m16): Generate both 16 bit and 32 bit simulator engines. 2751 2752Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> 2753 2754 * configure.in (mips_fpu_bitsize): For tx39, restrict floating 2755 point unit to 32 bit registers. 2756 * configure: Re-generate. 2757 2758Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> 2759 2760 * configure.in (sim_use_gen): Make IGEN the default simulator 2761 generator for generic 32 and 64 bit mips targets. 2762 * configure: Re-generate. 2763 2764Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 2765 2766 * sim-main.h (SizeFGR): Determine from floating-point and not gpr 2767 bitsize. 2768 2769 * interp.c (sim_fetch_register, sim_store_register): Read/write 2770 FGR from correct location. 2771 (sim_open): Set size of FGR's according to 2772 WITH_TARGET_FLOATING_POINT_BITSIZE. 2773 2774 * sim-main.h (FGR): Store floating point registers in a separate 2775 array. 2776 2777Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> 2778 2779 * configure: Regenerated to track ../common/aclocal.m4 changes. 2780 2781Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 2782 2783 * interp.c (ColdReset): Call PENDING_INVALIDATE. 2784 2785 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. 2786 2787 * interp.c (pending_tick): New function. Deliver pending writes. 2788 2789 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, 2790 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that 2791 it can handle mixed sized quantites and single bits. 2792 2793Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> 2794 2795 * interp.c (oengine.h): Do not include when building with IGEN. 2796 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. 2797 (sim_info): Ditto for PROCESSOR_64BIT. 2798 (sim_monitor): Replace ut_reg with unsigned_word. 2799 (*): Ditto for t_reg. 2800 (LOADDRMASK): Define. 2801 (sim_open): Remove defunct check that host FP is IEEE compliant, 2802 using software to emulate floating point. 2803 (value_fpr, ...): Always compile, was conditional on HASFPU. 2804 2805Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> 2806 2807 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in 2808 size. 2809 2810 * interp.c (SD, CPU): Define. 2811 (mips_option_handler): Set flags in each CPU. 2812 (interrupt_event): Assume CPU 0 is the one being iterrupted. 2813 (sim_close): Do not clear STATE, deleted anyway. 2814 (sim_write, sim_read): Assume CPU zero's vm should be used for 2815 data transfers. 2816 (sim_create_inferior): Set the PC for all processors. 2817 (sim_monitor, store_word, load_word, mips16_entry): Add cpu 2818 argument. 2819 (mips16_entry): Pass correct nr of args to store_word, load_word. 2820 (ColdReset): Cold reset all cpu's. 2821 (signal_exception): Pass cpu to sim_monitor & mips16_entry. 2822 (sim_monitor, load_memory, store_memory, signal_exception): Use 2823 `CPU' instead of STATE_CPU. 2824 2825 2826 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with 2827 SD or CPU_. 2828 2829 * sim-main.h (signal_exception): Add sim_cpu arg. 2830 (SignalException*): Pass both SD and CPU to signal_exception. 2831 * interp.c (signal_exception): Update. 2832 2833 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: 2834 Ditto 2835 (sync_operation, prefetch, cache_op, store_memory, load_memory, 2836 address_translation): Ditto 2837 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. 2838 2839Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> 2840 2841 * configure: Regenerated to track ../common/aclocal.m4 changes. 2842 2843Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> 2844 2845 * interp.c (sim_engine_run): Add `nr_cpus' argument. 2846 2847 * mips.igen (model): Map processor names onto BFD name. 2848 2849 * sim-main.h (CPU_CIA): Delete. 2850 (SET_CIA, GET_CIA): Define 2851 2852Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> 2853 2854 * sim-main.h (GPR_SET): Define, used by igen when zeroing a 2855 regiser. 2856 2857 * configure.in (default_endian): Configure a big-endian simulator 2858 by default. 2859 * configure: Re-generate. 2860 2861Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> 2862 2863 * configure: Regenerated to track ../common/aclocal.m4 changes. 2864 2865Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> 2866 2867 * interp.c (sim_monitor): Handle Densan monitor outbyte 2868 and inbyte functions. 2869 28701997-12-29 Felix Lee <flee@cygnus.com> 2871 2872 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). 2873 2874Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) 2875 2876 * Makefile.in (tmp-igen): Arrange for $zero to always be 2877 reset to zero after every instruction. 2878 2879Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> 2880 2881 * configure: Regenerated to track ../common/aclocal.m4 changes. 2882 * config.in: Ditto. 2883 2884Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) 2885 2886 * mips.igen (MSUB): Fix to work like MADD. 2887 * gencode.c (MSUB): Similarly. 2888 2889Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> 2890 2891 * configure: Regenerated to track ../common/aclocal.m4 changes. 2892 2893Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2894 2895 * mips.igen (LWC1): Correct assembler - lwc1 not swc1. 2896 2897Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2898 2899 * sim-main.h (sim-fpu.h): Include. 2900 2901 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, 2902 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite 2903 using host independant sim_fpu module. 2904 2905Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 2906 2907 * interp.c (signal_exception): Report internal errors with SIGABRT 2908 not SIGQUIT. 2909 2910 * sim-main.h (C0_CONFIG): New register. 2911 (signal.h): No longer include. 2912 2913 * interp.c (decode_coproc): Allow access C0_CONFIG to register. 2914 2915Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> 2916 2917 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). 2918 2919Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2920 2921 * mips.igen: Tag vr5000 instructions. 2922 (ANDI): Was missing mipsIV model, fix assembler syntax. 2923 (do_c_cond_fmt): New function. 2924 (C.cond.fmt): Handle mips I-III which do not support CC field 2925 separatly. 2926 (bc1): Handle mips IV which do not have a delaed FCC separatly. 2927 (SDR): Mask paddr when BigEndianMem, not the converse as specified 2928 in IV3.2 spec. 2929 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle 2930 vr5000 which saves LO in a GPR separatly. 2931 2932 * configure.in (enable-sim-igen): For vr5000, select vr5000 2933 specific instructions. 2934 * configure: Re-generate. 2935 2936Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> 2937 2938 * Makefile.in (SIM_OBJS): Add sim-fpu module. 2939 2940 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and 2941 fmt_uninterpreted_64 bit cases to switch. Convert to 2942 fmt_formatted, 2943 2944 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, 2945 2946 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse 2947 as specified in IV3.2 spec. 2948 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. 2949 2950Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2951 2952 * mips.igen: Delay slot branches add OFFSET to NIA not CIA. 2953 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. 2954 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non 2955 PENDING_FILL versions of instructions. Simplify. 2956 (X): New function. 2957 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of 2958 instructions. 2959 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to 2960 a signed value. 2961 (MTHI, MFHI): Disable code checking HI-LO. 2962 2963 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh 2964 global. 2965 (NULLIFY_NEXT_INSTRUCTION): Call dotrace. 2966 2967Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> 2968 2969 * gencode.c (build_mips16_operands): Replace IPC with cia. 2970 2971 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, 2972 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace 2973 IPC to `cia'. 2974 (UndefinedResult): Replace function with macro/function 2975 combination. 2976 (sim_engine_run): Don't save PC in IPC. 2977 2978 * sim-main.h (IPC): Delete. 2979 2980 2981 * interp.c (signal_exception, store_word, load_word, 2982 address_translation, load_memory, store_memory, cache_op, 2983 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, 2984 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add 2985 current instruction address - cia - argument. 2986 (sim_read, sim_write): Call address_translation directly. 2987 (sim_engine_run): Rename variable vaddr to cia. 2988 (signal_exception): Pass cia to sim_monitor 2989 2990 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, 2991 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, 2992 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. 2993 2994 * sim-main.h (SignalExceptionSimulatorFault): Delete definition. 2995 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with 2996 SIM_ASSERT. 2997 2998 * interp.c (signal_exception): Pass restart address to 2999 sim_engine_restart. 3000 3001 * Makefile.in (semantics.o, engine.o, support.o, itable.o, 3002 idecode.o): Add dependency. 3003 3004 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): 3005 Delete definitions 3006 (DELAY_SLOT): Update NIA not PC with branch address. 3007 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. 3008 3009 * mips.igen: Use CIA not PC in branch calculations. 3010 (illegal): Call SignalException. 3011 (BEQ, ADDIU): Fix assembler. 3012 3013Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 3014 3015 * m16.igen (JALX): Was missing. 3016 3017 * configure.in (enable-sim-igen): New configuration option. 3018 * configure: Re-generate. 3019 3020 * sim-main.h (MAX_INSNS, INSN_NAME): Define. 3021 3022 * interp.c (load_memory, store_memory): Delete parameter RAW. 3023 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly 3024 bypassing {load,store}_memory. 3025 3026 * sim-main.h (ByteSwapMem): Delete definition. 3027 3028 * Makefile.in (SIM_OBJS): Add sim-memopt module. 3029 3030 * interp.c (sim_do_command, sim_commands): Delete mips specific 3031 commands. Handled by module sim-options. 3032 3033 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. 3034 (WITH_MODULO_MEMORY): Define. 3035 3036 * interp.c (sim_info): Delete code printing memory size. 3037 3038 * interp.c (mips_size): Nee sim_size, delete function. 3039 (power2): Delete. 3040 (monitor, monitor_base, monitor_size): Delete global variables. 3041 (sim_open, sim_close): Delete code creating monitor and other 3042 memory regions. Use sim-memopts module, via sim_do_commandf, to 3043 manage memory regions. 3044 (load_memory, store_memory): Use sim-core for memory model. 3045 3046 * interp.c (address_translation): Delete all memory map code 3047 except line forcing 32 bit addresses. 3048 3049Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> 3050 3051 * sim-main.h (WITH_TRACE): Delete definition. Enables common 3052 trace options. 3053 3054 * interp.c (logfh, logfile): Delete globals. 3055 (sim_open, sim_close): Delete code opening & closing log file. 3056 (mips_option_handler): Delete -l and -n options. 3057 (OPTION mips_options): Ditto. 3058 3059 * interp.c (OPTION mips_options): Rename option trace to dinero. 3060 (mips_option_handler): Update. 3061 3062Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 3063 3064 * interp.c (fetch_str): New function. 3065 (sim_monitor): Rewrite using sim_read & sim_write. 3066 (sim_open): Check magic number. 3067 (sim_open): Write monitor vectors into memory using sim_write. 3068 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. 3069 (sim_read, sim_write): Simplify - transfer data one byte at a 3070 time. 3071 (load_memory, store_memory): Clarify meaning of parameter RAW. 3072 3073 * sim-main.h (isHOST): Defete definition. 3074 (isTARGET): Mark as depreciated. 3075 (address_translation): Delete parameter HOST. 3076 3077 * interp.c (address_translation): Delete parameter HOST. 3078 3079Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 3080 3081 * mips.igen: 3082 3083 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. 3084 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. 3085 3086Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> 3087 3088 * mips.igen: Add model filter field to records. 3089 3090Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 3091 3092 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. 3093 3094 interp.c (sim_engine_run): Do not compile function sim_engine_run 3095 when WITH_IGEN == 1. 3096 3097 * configure.in (sim_igen_flags, sim_m16_flags): Set according to 3098 target architecture. 3099 3100 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to 3101 igen. Replace with configuration variables sim_igen_flags / 3102 sim_m16_flags. 3103 3104 * m16.igen: New file. Copy mips16 insns here. 3105 * mips.igen: From here. 3106 3107Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 3108 3109 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ 3110 to top. 3111 (tmp-igen, tmp-m16): Pass -I srcdir to igen. 3112 3113Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> 3114 3115 * gencode.c (build_instruction): Follow sim_write's lead in using 3116 BigEndianMem instead of !ByteSwapMem. 3117 3118Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> 3119 3120 * configure.in (sim_gen): Dependent on target, select type of 3121 generator. Always select old style generator. 3122 3123 configure: Re-generate. 3124 3125 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New 3126 targets. 3127 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, 3128 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, 3129 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define 3130 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member 3131 SIM_@sim_gen@_*, set by autoconf. 3132 3133Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> 3134 3135 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. 3136 3137 * interp.c (ColdReset): Remove #ifdef HASFPU, check 3138 CURRENT_FLOATING_POINT instead. 3139 3140 * interp.c (ifetch32): New function. Fetch 32 bit instruction. 3141 (address_translation): Raise exception InstructionFetch when 3142 translation fails and isINSTRUCTION. 3143 3144 * interp.c (sim_open, sim_write, sim_monitor, store_word, 3145 sim_engine_run): Change type of of vaddr and paddr to 3146 address_word. 3147 (address_translation, prefetch, load_memory, store_memory, 3148 cache_op): Change type of vAddr and pAddr to address_word. 3149 3150 * gencode.c (build_instruction): Change type of vaddr and paddr to 3151 address_word. 3152 3153Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> 3154 3155 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT 3156 macro to obtain result of ALU op. 3157 3158Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> 3159 3160 * interp.c (sim_info): Call profile_print. 3161 3162Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 3163 3164 * Makefile.in (SIM_OBJS): Add sim-profile.o module. 3165 3166 * sim-main.h (WITH_PROFILE): Do not define, defined in 3167 common/sim-config.h. Use sim-profile module. 3168 (simPROFILE): Delete defintion. 3169 3170 * interp.c (PROFILE): Delete definition. 3171 (mips_option_handler): Delete 'p', 'y' and 'x' profile options. 3172 (sim_close): Delete code writing profile histogram. 3173 (mips_set_profile, mips_set_profile_size, writeout16, writeout32): 3174 Delete. 3175 (sim_engine_run): Delete code profiling the PC. 3176 3177Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 3178 3179 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. 3180 3181 * interp.c (sim_monitor): Make register pointers of type 3182 unsigned_word*. 3183 3184 * sim-main.h: Make registers of type unsigned_word not 3185 signed_word. 3186 3187Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 3188 3189 * interp.c (sync_operation): Rename from SyncOperation, make 3190 global, add SD argument. 3191 (prefetch): Rename from Prefetch, make global, add SD argument. 3192 (decode_coproc): Make global. 3193 3194 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. 3195 3196 * gencode.c (build_instruction): Generate DecodeCoproc not 3197 decode_coproc calls. 3198 3199 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h 3200 (SizeFGR): Move to sim-main.h 3201 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, 3202 simSIGINT, simJALDELAYSLOT): Move to sim-main.h 3203 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to 3204 sim-main.h. 3205 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, 3206 FP_RM_TOMINF, GETRM): Move to sim-main.h. 3207 (Uncached, CachedNoncoherent, CachedCoherent, Cached, 3208 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. 3209 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, 3210 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h 3211 3212 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise 3213 exception. 3214 (sim-alu.h): Include. 3215 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. 3216 (sim_cia): Typedef to instruction_address. 3217 3218Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> 3219 3220 * Makefile.in (interp.o): Rename generated file engine.c to 3221 oengine.c. 3222 3223 * interp.c: Update. 3224 3225Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> 3226 3227 * gencode.c (build_instruction): Use FPR_STATE not fpr_state. 3228 3229Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 3230 3231 * gencode.c (build_instruction): For "FPSQRT", output correct 3232 number of arguments to Recip. 3233 3234Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> 3235 3236 * Makefile.in (interp.o): Depends on sim-main.h 3237 3238 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. 3239 3240 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, 3241 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. 3242 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, 3243 STATE, DSSTATE): Define 3244 (GPR, FGRIDX, ..): Define. 3245 3246 * interp.c (registers, register_widths, fpr_state, ipc, dspc, 3247 pending_*, hiaccess, loaccess, state, dsstate): Delete globals. 3248 (GPR, FGRIDX, ...): Delete macros. 3249 3250 * interp.c: Update names to match defines from sim-main.h 3251 3252Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> 3253 3254 * interp.c (sim_monitor): Add SD argument. 3255 (sim_warning): Delete. Replace calls with calls to 3256 sim_io_eprintf. 3257 (sim_error): Delete. Replace calls with sim_io_error. 3258 (open_trace, writeout32, writeout16, getnum): Add SD argument. 3259 (mips_set_profile): Rename from sim_set_profile. Add SD argument. 3260 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD 3261 argument. 3262 (mips_size): Rename from sim_size. Add SD argument. 3263 3264 * interp.c (simulator): Delete global variable. 3265 (callback): Delete global variable. 3266 (mips_option_handler, sim_open, sim_write, sim_read, 3267 sim_store_register, sim_fetch_register, sim_info, sim_do_command, 3268 sim_size,sim_monitor): Use sim_io_* not callback->*. 3269 (sim_open): ZALLOC simulator struct. 3270 (PROFILE): Do not define. 3271 3272Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 3273 3274 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in 3275 support.h with corresponding code. 3276 3277 * sim-main.h (word64, uword64), support.h: Move definition to 3278 sim-main.h. 3279 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. 3280 3281 * support.h: Delete 3282 * Makefile.in: Update dependencies 3283 * interp.c: Do not include. 3284 3285Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 3286 3287 * interp.c (address_translation, load_memory, store_memory, 3288 cache_op): Rename to from AddressTranslation et.al., make global, 3289 add SD argument 3290 3291 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, 3292 CacheOp): Define. 3293 3294 * interp.c (SignalException): Rename to signal_exception, make 3295 global. 3296 3297 * interp.c (Interrupt, ...): Move definitions to sim-main.h. 3298 3299 * sim-main.h (SignalException, SignalExceptionInterrupt, 3300 SignalExceptionInstructionFetch, SignalExceptionAddressStore, 3301 SignalExceptionAddressLoad, SignalExceptionSimulatorFault, 3302 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): 3303 Define. 3304 3305 * interp.c, support.h: Use. 3306 3307Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 3308 3309 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename 3310 to value_fpr / store_fpr. Add SD argument. 3311 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, 3312 Multiply, Divide, Recip, SquareRoot, Convert): Make global. 3313 3314 * sim-main.h (ValueFPR, StoreFPR): Define. 3315 3316Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> 3317 3318 * interp.c (sim_engine_run): Check consistency between configure 3319 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN 3320 and HASFPU. 3321 3322 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. 3323 (mips_fpu): Configure WITH_FLOATING_POINT. 3324 (mips_endian): Configure WITH_TARGET_ENDIAN. 3325 * configure: Update. 3326 3327Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> 3328 3329 * configure: Regenerated to track ../common/aclocal.m4 changes. 3330 3331Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> 3332 3333 * configure: Regenerated. 3334 3335Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> 3336 3337 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 3338 3339Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 3340 3341 * gencode.c (print_igen_insn_models): Assume certain architectures 3342 include all mips* instructions. 3343 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 3344 instruction. 3345 3346 * Makefile.in (tmp.igen): Add target. Generate igen input from 3347 gencode file. 3348 3349 * gencode.c (FEATURE_IGEN): Define. 3350 (main): Add --igen option. Generate output in igen format. 3351 (process_instructions): Format output according to igen option. 3352 (print_igen_insn_format): New function. 3353 (print_igen_insn_models): New function. 3354 (process_instructions): Only issue warnings and ignore 3355 instructions when no FEATURE_IGEN. 3356 3357Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> 3358 3359 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some 3360 MIPS targets. 3361 3362Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> 3363 3364 * configure: Regenerated to track ../common/aclocal.m4 changes. 3365 3366Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> 3367 3368 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, 3369 SIM_RESERVED_BITS): Delete, moved to common. 3370 (SIM_EXTRA_CFLAGS): Update. 3371 3372Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 3373 3374 * configure.in: Configure non-strict memory alignment. 3375 * configure: Regenerated to track ../common/aclocal.m4 changes. 3376 3377Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> 3378 3379 * configure: Regenerated to track ../common/aclocal.m4 changes. 3380 3381Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> 3382 3383 * gencode.c (SDBBP,DERET): Added (3900) insns. 3384 (RFE): Turn on for 3900. 3385 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. 3386 (dsstate): Made global. 3387 (SUBTARGET_R3900): Added. 3388 (CANCELDELAYSLOT): New. 3389 (SignalException): Ignore SystemCall rather than ignore and 3390 terminate. Add DebugBreakPoint handling. 3391 (decode_coproc): New insns RFE, DERET; and new registers Debug 3392 and DEPC protected by SUBTARGET_R3900. 3393 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing 3394 bits explicitly. 3395 * Makefile.in,configure.in: Add mips subtarget option. 3396 * configure: Update. 3397 3398Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> 3399 3400 * gencode.c: Add r3900 (tx39). 3401 3402 3403Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> 3404 3405 * gencode.c (build_instruction): Don't need to subtract 4 for 3406 JALR, just 2. 3407 3408Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> 3409 3410 * interp.c: Correct some HASFPU problems. 3411 3412Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> 3413 3414 * configure: Regenerated to track ../common/aclocal.m4 changes. 3415 3416Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 3417 3418 * interp.c (mips_options): Fix samples option short form, should 3419 be `x'. 3420 3421Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> 3422 3423 * interp.c (sim_info): Enable info code. Was just returning. 3424 3425Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> 3426 3427 * interp.c (decode_coproc): Clarify warning about unsuported MTC0, 3428 MFC0. 3429 3430Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> 3431 3432 * gencode.c (build_instruction): Use SIGNED64 for 64 bit 3433 constants. 3434 (build_instruction): Ditto for LL. 3435 3436Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> 3437 3438 * configure: Regenerated to track ../common/aclocal.m4 changes. 3439 3440Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 3441 3442 * configure: Regenerated to track ../common/aclocal.m4 changes. 3443 * config.in: Ditto. 3444 3445Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> 3446 3447 * interp.c (sim_open): Add call to sim_analyze_program, update 3448 call to sim_config. 3449 3450Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> 3451 3452 * interp.c (sim_kill): Delete. 3453 (sim_create_inferior): Add ABFD argument. Set PC from same. 3454 (sim_load): Move code initializing trap handlers from here. 3455 (sim_open): To here. 3456 (sim_load): Delete, use sim-hload.c. 3457 3458 * Makefile.in (SIM_OBJS): Add sim-hload.o module. 3459 3460Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 3461 3462 * configure: Regenerated to track ../common/aclocal.m4 changes. 3463 * config.in: Ditto. 3464 3465Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 3466 3467 * interp.c (sim_open): Add ABFD argument. 3468 (sim_load): Move call to sim_config from here. 3469 (sim_open): To here. Check return status. 3470 3471Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> 3472 3473 * gencode.c (build_instruction): Two arg MADD should 3474 not assign result to $0. 3475 3476Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) 3477 3478 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) 3479 * sim/mips/configure.in: Regenerate. 3480 3481Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> 3482 3483 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit 3484 signed8, unsigned8 et.al. types. 3485 3486 * interp.c (SUB_REG_FETCH): Handle both little and big endian 3487 hosts when selecting subreg. 3488 3489Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) 3490 3491 * interp.c (sim_engine_run): Reset the ZERO register to zero 3492 regardless of FEATURE_WARN_ZERO. 3493 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. 3494 3495Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> 3496 3497 * interp.c (decode_coproc): Implement MTC0 N, CAUSE. 3498 (SignalException): For BreakPoints ignore any mode bits and just 3499 save the PC. 3500 (SignalException): Always set the CAUSE register. 3501 3502Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> 3503 3504 * interp.c (SignalException): Clear the simDELAYSLOT flag when an 3505 exception has been taken. 3506 3507 * interp.c: Implement the ERET and mt/f sr instructions. 3508 3509Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> 3510 3511 * interp.c (SignalException): Don't bother restarting an 3512 interrupt. 3513 3514Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 3515 3516 * interp.c (SignalException): Really take an interrupt. 3517 (interrupt_event): Only deliver interrupts when enabled. 3518 3519Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> 3520 3521 * interp.c (sim_info): Only print info when verbose. 3522 (sim_info) Use sim_io_printf for output. 3523 3524Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 3525 3526 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all 3527 mips architectures. 3528 3529Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 3530 3531 * interp.c (sim_do_command): Check for common commands if a 3532 simulator specific command fails. 3533 3534Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> 3535 3536 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP 3537 and simBE when DEBUG is defined. 3538 3539Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> 3540 3541 * interp.c (interrupt_event): New function. Pass exception event 3542 onto exception handler. 3543 3544 * configure.in: Check for stdlib.h. 3545 * configure: Regenerate. 3546 3547 * gencode.c (build_instruction): Add UNUSED attribute to tempS 3548 variable declaration. 3549 (build_instruction): Initialize memval1. 3550 (build_instruction): Add UNUSED attribute to byte, bigend, 3551 reverse. 3552 (build_operands): Ditto. 3553 3554 * interp.c: Fix GCC warnings. 3555 (sim_get_quit_code): Delete. 3556 3557 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. 3558 * Makefile.in: Ditto. 3559 * configure: Re-generate. 3560 3561 * Makefile.in (SIM_OBJS): Add sim-watch.o module. 3562 3563Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 3564 3565 * interp.c (mips_option_handler): New function parse argumes using 3566 sim-options. 3567 (myname): Replace with STATE_MY_NAME. 3568 (sim_open): Delete check for host endianness - performed by 3569 sim_config. 3570 (simHOSTBE, simBE): Delete, replaced by sim-endian flags. 3571 (sim_open): Move much of the initialization from here. 3572 (sim_load): To here. After the image has been loaded and 3573 endianness set. 3574 (sim_open): Move ColdReset from here. 3575 (sim_create_inferior): To here. 3576 (sim_open): Make FP check less dependant on host endianness. 3577 3578 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or 3579 run. 3580 * interp.c (sim_set_callbacks): Delete. 3581 3582 * interp.c (membank, membank_base, membank_size): Replace with 3583 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. 3584 (sim_open): Remove call to callback->init. gdb/run do this. 3585 3586 * interp.c: Update 3587 3588 * sim-main.h (SIM_HAVE_FLATMEM): Define. 3589 3590 * interp.c (big_endian_p): Delete, replaced by 3591 current_target_byte_order. 3592 3593Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> 3594 3595 * interp.c (host_read_long, host_read_word, host_swap_word, 3596 host_swap_long): Delete. Using common sim-endian. 3597 (sim_fetch_register, sim_store_register): Use H2T. 3598 (pipeline_ticks): Delete. Handled by sim-events. 3599 (sim_info): Update. 3600 (sim_engine_run): Update. 3601 3602Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> 3603 3604 * interp.c (sim_stop_reason): Move code determining simEXCEPTION 3605 reason from here. 3606 (SignalException): To here. Signal using sim_engine_halt. 3607 (sim_stop_reason): Delete, moved to common. 3608 3609Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> 3610 3611 * interp.c (sim_open): Add callback argument. 3612 (sim_set_callbacks): Delete SIM_DESC argument. 3613 (sim_size): Ditto. 3614 3615Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> 3616 3617 * Makefile.in (SIM_OBJS): Add common modules. 3618 3619 * interp.c (sim_set_callbacks): Also set SD callback. 3620 (set_endianness, xfer_*, swap_*): Delete. 3621 (host_read_word, host_read_long, host_swap_word, host_swap_long): 3622 Change to functions using sim-endian macros. 3623 (control_c, sim_stop): Delete, use common version. 3624 (simulate): Convert into. 3625 (sim_engine_run): This function. 3626 (sim_resume): Delete. 3627 3628 * interp.c (simulation): New variable - the simulator object. 3629 (sim_kind): Delete global - merged into simulation. 3630 (sim_load): Cleanup. Move PC assignment from here. 3631 (sim_create_inferior): To here. 3632 3633 * sim-main.h: New file. 3634 * interp.c (sim-main.h): Include. 3635 3636Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> 3637 3638 * configure: Regenerated to track ../common/aclocal.m4 changes. 3639 3640Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> 3641 3642 * tconfig.in (SIM_HAVE_BIENDIAN): Define. 3643 3644Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> 3645 3646 * gencode.c (build_instruction): DIV instructions: check 3647 for division by zero and integer overflow before using 3648 host's division operation. 3649 3650Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> 3651 3652 * Makefile.in (SIM_OBJS): Add sim-load.o. 3653 * interp.c: #include bfd.h. 3654 (target_byte_order): Delete. 3655 (sim_kind, myname, big_endian_p): New static locals. 3656 (sim_open): Set sim_kind, myname. Move call to set_endianness to 3657 after argument parsing. Recognize -E arg, set endianness accordingly. 3658 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to 3659 load file into simulator. Set PC from bfd. 3660 (sim_create_inferior): Return SIM_RC. Delete arg start_address. 3661 (set_endianness): Use big_endian_p instead of target_byte_order. 3662 3663Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> 3664 3665 * interp.c (sim_size): Delete prototype - conflicts with 3666 definition in remote-sim.h. Correct definition. 3667 3668Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 3669 3670 * configure: Regenerated to track ../common/aclocal.m4 changes. 3671 * config.in: Ditto. 3672 3673Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> 3674 3675 * interp.c (sim_open): New arg `kind'. 3676 3677 * configure: Regenerated to track ../common/aclocal.m4 changes. 3678 3679Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 3680 3681 * configure: Regenerated to track ../common/aclocal.m4 changes. 3682 3683Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> 3684 3685 * interp.c (sim_open): Set optind to 0 before calling getopt. 3686 3687Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 3688 3689 * configure: Regenerated to track ../common/aclocal.m4 changes. 3690 3691Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> 3692 3693 * interp.c : Replace uses of pr_addr with pr_uword64 3694 where the bit length is always 64 independent of SIM_ADDR. 3695 (pr_uword64) : added. 3696 3697Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 3698 3699 * configure: Re-generate. 3700 3701Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> 3702 3703 * configure: Regenerate to track ../common/aclocal.m4 changes. 3704 3705Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> 3706 3707 * interp.c (sim_open): New SIM_DESC result. Argument is now 3708 in argv form. 3709 (other sim_*): New SIM_DESC argument. 3710 3711Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> 3712 3713 * interp.c: Fix printing of addresses for non-64-bit targets. 3714 (pr_addr): Add function to print address based on size. 3715 3716Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> 3717 3718 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. 3719 3720Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> 3721 3722 * gencode.c (build_mips16_operands): Correct computation of base 3723 address for extended PC relative instruction. 3724 3725Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> 3726 3727 * interp.c (mips16_entry): Add support for floating point cases. 3728 (SignalException): Pass floating point cases to mips16_entry. 3729 (ValueFPR): Don't restrict fmt_single and fmt_word to even 3730 registers. 3731 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single 3732 or fmt_word. 3733 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, 3734 and then set the state to fmt_uninterpreted. 3735 (COP_SW): Temporarily set the state to fmt_word while calling 3736 ValueFPR. 3737 3738Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> 3739 3740 * gencode.c (build_instruction): The high order may be set in the 3741 comparison flags at any ISA level, not just ISA 4. 3742 3743Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> 3744 3745 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use 3746 COMMON_{PRE,POST}_CONFIG_FRAG instead. 3747 * configure.in: sinclude ../common/aclocal.m4. 3748 * configure: Regenerated. 3749 3750Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> 3751 3752 * configure: Rebuild after change to aclocal.m4. 3753 3754Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) 3755 3756 * configure configure.in Makefile.in: Update to new configure 3757 scheme which is more compatible with WinGDB builds. 3758 * configure.in: Improve comment on how to run autoconf. 3759 * configure: Re-run autoconf to get new ../common/aclocal.m4. 3760 * Makefile.in: Use autoconf substitution to install common 3761 makefile fragment. 3762 3763Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> 3764 3765 * gencode.c (build_instruction): Use BigEndianCPU instead of 3766 ByteSwapMem. 3767 3768Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> 3769 3770 * interp.c (sim_monitor): Make output to stdout visible in 3771 wingdb's I/O log window. 3772 3773Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> 3774 3775 * support.h: Undo previous change to SIGTRAP 3776 and SIGQUIT values. 3777 3778Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> 3779 3780 * interp.c (store_word, load_word): New static functions. 3781 (mips16_entry): New static function. 3782 (SignalException): Look for mips16 entry and exit instructions. 3783 (simulate): Use the correct index when setting fpr_state after 3784 doing a pending move. 3785 3786Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> 3787 3788 * interp.c: Fix byte-swapping code throughout to work on 3789 both little- and big-endian hosts. 3790 3791Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> 3792 3793 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent 3794 with gdb/config/i386/xm-windows.h. 3795 3796Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> 3797 3798 * gencode.c (build_instruction): Work around MSVC++ code gen bug 3799 that messes up arithmetic shifts. 3800 3801Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) 3802 3803 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for 3804 SIGTRAP and SIGQUIT for _WIN32. 3805 3806Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> 3807 3808 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to 3809 force a 64 bit multiplication. 3810 (build_instruction) [OR]: In mips16 mode, don't do anything if the 3811 destination register is 0, since that is the default mips16 nop 3812 instruction. 3813 3814Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> 3815 3816 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. 3817 (build_endian_shift): Don't check proc64. 3818 (build_instruction): Always set memval to uword64. Cast op2 to 3819 uword64 when shifting it left in memory instructions. Always use 3820 the same code for stores--don't special case proc64. 3821 3822 * gencode.c (build_mips16_operands): Fix base PC value for PC 3823 relative operands. 3824 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a 3825 jal instruction. 3826 * interp.c (simJALDELAYSLOT): Define. 3827 (JALDELAYSLOT): Define. 3828 (INDELAYSLOT, INJALDELAYSLOT): Define. 3829 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. 3830 3831Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) 3832 3833 * interp.c (sim_open): add flush_cache as a PMON routine 3834 (sim_monitor): handle flush_cache by ignoring it 3835 3836Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> 3837 3838 * gencode.c (build_instruction): Use !ByteSwapMem instead of 3839 BigEndianMem. 3840 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. 3841 (BigEndianMem): Rename to ByteSwapMem and change sense. 3842 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change 3843 BigEndianMem references to !ByteSwapMem. 3844 (set_endianness): New function, with prototype. 3845 (sim_open): Call set_endianness. 3846 (sim_info): Use simBE instead of BigEndianMem. 3847 (xfer_direct_word, xfer_direct_long, swap_direct_word, 3848 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, 3849 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER 3850 ifdefs, keeping the prototype declaration. 3851 (swap_word): Rewrite correctly. 3852 (ColdReset): Delete references to CONFIG. Delete endianness related 3853 code; moved to set_endianness. 3854 3855Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> 3856 3857 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. 3858 * interp.c (CHECKHILO): Define away. 3859 (simSIGINT): New macro. 3860 (membank_size): Increase from 1MB to 2MB. 3861 (control_c): New function. 3862 (sim_resume): Rename parameter signal to signal_number. Add local 3863 variable prev. Call signal before and after simulate. 3864 (sim_stop_reason): Add simSIGINT support. 3865 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg 3866 functions always. 3867 (sim_warning): Delete call to SignalException. Do call printf_filtered 3868 if logfh is NULL. 3869 (AddressTranslation): Add #ifdef DEBUG around debugging message and 3870 a call to sim_warning. 3871 3872Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> 3873 3874 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD 3875 16 bit instructions. 3876 3877Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> 3878 3879 Add support for mips16 (16 bit MIPS implementation): 3880 * gencode.c (inst_type): Add mips16 instruction encoding types. 3881 (GETDATASIZEINSN): Define. 3882 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add 3883 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and 3884 mtlo. 3885 (MIPS16_DECODE): New table, for mips16 instructions. 3886 (bitmap_val): New static function. 3887 (struct mips16_op): Define. 3888 (mips16_op_table): New table, for mips16 operands. 3889 (build_mips16_operands): New static function. 3890 (process_instructions): If PC is odd, decode a mips16 3891 instruction. Break out instruction handling into new 3892 build_instruction function. 3893 (build_instruction): New static function, broken out of 3894 process_instructions. Check modifiers rather than flags for SHIFT 3895 bit count and m[ft]{hi,lo} direction. 3896 (usage): Pass program name to fprintf. 3897 (main): Remove unused variable this_option_optind. Change 3898 ``*loptarg++'' to ``loptarg++''. 3899 (my_strtoul): Parenthesize && within ||. 3900 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. 3901 (simulate): If PC is odd, fetch a 16 bit instruction, and 3902 increment PC by 2 rather than 4. 3903 * configure.in: Add case for mips16*-*-*. 3904 * configure: Rebuild. 3905 3906Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> 3907 3908 * interp.c: Allow -t to enable tracing in standalone simulator. 3909 Fix garbage output in trace file and error messages. 3910 3911Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> 3912 3913 * Makefile.in: Delete stuff moved to ../common/Make-common.in. 3914 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. 3915 * configure.in: Simplify using macros in ../common/aclocal.m4. 3916 * configure: Regenerated. 3917 * tconfig.in: New file. 3918 3919Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> 3920 3921 * interp.c: Fix bugs in 64-bit port. 3922 Use ansi function declarations for msvc compiler. 3923 Initialize and test file pointer in trace code. 3924 Prevent duplicate definition of LAST_EMED_REGNUM. 3925 3926Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> 3927 3928 * interp.c (xfer_big_long): Prevent unwanted sign extension. 3929 3930Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> 3931 3932 * interp.c (SignalException): Check for explicit terminating 3933 breakpoint value. 3934 * gencode.c: Pass instruction value through SignalException() 3935 calls for Trap, Breakpoint and Syscall. 3936 3937Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> 3938 3939 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is 3940 only used on those hosts that provide it. 3941 * configure.in: Add sqrt() to list of functions to be checked for. 3942 * config.in: Re-generated. 3943 * configure: Re-generated. 3944 3945Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> 3946 3947 * gencode.c (process_instructions): Call build_endian_shift when 3948 expanding STORE RIGHT, to fix swr. 3949 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly 3950 clear the high bits. 3951 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. 3952 Fix float to int conversions to produce signed values. 3953 3954Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> 3955 3956 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. 3957 (process_instructions): Correct handling of nor instruction. 3958 Correct shift count for 32 bit shift instructions. Correct sign 3959 extension for arithmetic shifts to not shift the number of bits in 3960 the type. Fix 64 bit multiply high word calculation. Fix 32 bit 3961 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. 3962 Fix madd. 3963 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. 3964 It's OK to have a mult follow a mult. What's not OK is to have a 3965 mult follow an mfhi. 3966 (Convert): Comment out incorrect rounding code. 3967 3968Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> 3969 3970 * interp.c (sim_monitor): Improved monitor printf 3971 simulation. Tidied up simulator warnings, and added "--log" option 3972 for directing warning message output. 3973 * gencode.c: Use sim_warning() rather than WARNING macro. 3974 3975Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> 3976 3977 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and 3978 getopt1.o, rather than on gencode.c. Link objects together. 3979 Don't link against -liberty. 3980 (gencode.o, getopt.o, getopt1.o): New targets. 3981 * gencode.c: Include <ctype.h> and "ansidecl.h". 3982 (AND): Undefine after including "ansidecl.h". 3983 (ULONG_MAX): Define if not defined. 3984 (OP_*): Don't define macros; now defined in opcode/mips.h. 3985 (main): Call my_strtoul rather than strtoul. 3986 (my_strtoul): New static function. 3987 3988Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) 3989 3990 * gencode.c (process_instructions): Generate word64 and uword64 3991 instead of `long long' and `unsigned long long' data types. 3992 * interp.c: #include sysdep.h to get signals, and define default 3993 for SIGBUS. 3994 * (Convert): Work around for Visual-C++ compiler bug with type 3995 conversion. 3996 * support.h: Make things compile under Visual-C++ by using 3997 __int64 instead of `long long'. Change many refs to long long 3998 into word64/uword64 typedefs. 3999 4000Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) 4001 4002 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, 4003 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. 4004 (docdir): Removed. 4005 * configure.in (AC_PREREQ): autoconf 2.5 or higher. 4006 (AC_PROG_INSTALL): Added. 4007 (AC_PROG_CC): Moved to before configure.host call. 4008 * configure: Rebuilt. 4009 4010Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> 4011 4012 * configure.in: Define @SIMCONF@ depending on mips target. 4013 * configure: Rebuild. 4014 * Makefile.in (run): Add @SIMCONF@ to control simulator 4015 construction. 4016 * gencode.c: Change LOADDRMASK to 64bit memory model only. 4017 * interp.c: Remove some debugging, provide more detailed error 4018 messages, update memory accesses to use LOADDRMASK. 4019 4020Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> 4021 4022 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, 4023 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set 4024 stamp-h. 4025 * configure: Rebuild. 4026 * config.in: New file, generated by autoheader. 4027 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, 4028 and <strings.h> if they exist. Replace #ifdef sun with #ifdef 4029 HAVE_ANINT and HAVE_AINT, as appropriate. 4030 * Makefile.in (run): Use @LIBS@ rather than -lm. 4031 (interp.o): Depend upon config.h. 4032 (Makefile): Just rebuild Makefile. 4033 (clean): Remove stamp-h. 4034 (mostlyclean): Make the same as clean, not as distclean. 4035 (config.h, stamp-h): New targets. 4036 4037Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> 4038 4039 * interp.c (ColdReset): Fix boolean test. Make all simulator 4040 globals static. 4041 4042Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> 4043 4044 * interp.c (xfer_direct_word, xfer_direct_long, 4045 swap_direct_word, swap_direct_long, xfer_big_word, 4046 xfer_big_long, xfer_little_word, xfer_little_long, 4047 swap_word,swap_long): Added. 4048 * interp.c (ColdReset): Provide function indirection to 4049 host<->simulated_target transfer routines. 4050 * interp.c (sim_store_register, sim_fetch_register): Updated to 4051 make use of indirected transfer routines. 4052 4053Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> 4054 4055 * gencode.c (process_instructions): Ensure FP ABS instruction 4056 recognised. 4057 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON 4058 system call support. 4059 4060Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> 4061 4062 * interp.c (sim_do_command): Complain if callback structure not 4063 initialised. 4064 4065Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> 4066 4067 * interp.c (Convert): Provide round-to-nearest and round-to-zero 4068 support for Sun hosts. 4069 * Makefile.in (gencode): Ensure the host compiler and libraries 4070 used for cross-hosted build. 4071 4072Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> 4073 4074 * interp.c, gencode.c: Some more (TODO) tidying. 4075 4076Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> 4077 4078 * gencode.c, interp.c: Replaced explicit long long references with 4079 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. 4080 * support.h (SET64LO, SET64HI): Macros added. 4081 4082Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> 4083 4084 * configure: Regenerate with autoconf 2.7. 4085 4086Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> 4087 4088 * interp.c (LoadMemory): Enclose text following #endif in /* */. 4089 * support.h: Remove superfluous "1" from #if. 4090 * support.h (CHECKSIM): Remove stray 'a' at end of line. 4091 4092Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> 4093 4094 * interp.c (StoreFPR): Control UndefinedResult() call on 4095 WARN_RESULT manifest. 4096 4097Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> 4098 4099 * gencode.c: Tidied instruction decoding, and added FP instruction 4100 support. 4101 4102 * interp.c: Added dineroIII, and BSD profiling support. Also 4103 run-time FP handling. 4104 4105Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> 4106 4107 * Changelog, Makefile.in, README.Cygnus, configure, configure.in, 4108 gencode.c, interp.c, support.h: created. 4109