1 /* gdb.c --- sim interface to GDB. 2 3 Copyright (C) 2005-2024 Free Software Foundation, Inc. 4 Contributed by Red Hat, Inc. 5 6 This file is part of the GNU simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include <stdio.h> 25 #include <assert.h> 26 #include <signal.h> 27 #include <stdlib.h> 28 #include <string.h> 29 #include <ctype.h> 30 31 #include "ansidecl.h" 32 #include "libiberty.h" 33 #include "sim/callback.h" 34 #include "sim/sim.h" 35 #include "gdb/signals.h" 36 #include "sim/sim-m32c.h" 37 38 #include "cpu.h" 39 #include "mem.h" 40 #include "load.h" 41 #include "syscalls.h" 42 #ifdef TIMER_A 43 #include "timer_a.h" 44 #endif 45 46 /* I don't want to wrap up all the minisim's data structures in an 47 object and pass that around. That'd be a big change, and neither 48 GDB nor run needs that ability. 49 50 So we just have one instance, that lives in global variables, and 51 each time we open it, we re-initialize it. */ 52 struct sim_state 53 { 54 const char *message; 55 }; 56 57 static struct sim_state the_minisim = { 58 "This is the sole m32c minisim instance. See libsim.a's global variables." 59 }; 60 61 static int is_open; 62 63 SIM_DESC 64 sim_open (SIM_OPEN_KIND kind, 65 struct host_callback_struct *callback, 66 struct bfd *abfd, char * const *argv) 67 { 68 setbuf (stdout, 0); 69 if (is_open) 70 fprintf (stderr, "m32c minisim: re-opened sim\n"); 71 72 /* The 'run' interface doesn't use this function, so we don't care 73 about KIND; it's always SIM_OPEN_DEBUG. */ 74 if (kind != SIM_OPEN_DEBUG) 75 fprintf (stderr, "m32c minisim: sim_open KIND != SIM_OPEN_DEBUG: %d\n", 76 kind); 77 78 if (abfd) 79 m32c_set_mach (bfd_get_mach (abfd)); 80 81 /* We can use ABFD, if non-NULL to select the appropriate 82 architecture. But we only support the r8c right now. */ 83 84 set_callbacks (callback); 85 86 /* We don't expect any command-line arguments. */ 87 88 init_mem (); 89 init_regs (); 90 91 is_open = 1; 92 return &the_minisim; 93 } 94 95 static void 96 check_desc (SIM_DESC sd) 97 { 98 if (sd != &the_minisim) 99 fprintf (stderr, "m32c minisim: desc != &the_minisim\n"); 100 } 101 102 void 103 sim_close (SIM_DESC sd, int quitting) 104 { 105 check_desc (sd); 106 107 /* Not much to do. At least free up our memory. */ 108 init_mem (); 109 110 is_open = 0; 111 } 112 113 static bfd * 114 open_objfile (const char *filename) 115 { 116 bfd *prog = bfd_openr (filename, 0); 117 118 if (!prog) 119 { 120 fprintf (stderr, "Can't read %s\n", filename); 121 return 0; 122 } 123 124 if (!bfd_check_format (prog, bfd_object)) 125 { 126 fprintf (stderr, "%s not a m32c program\n", filename); 127 return 0; 128 } 129 130 return prog; 131 } 132 133 134 SIM_RC 135 sim_load (SIM_DESC sd, const char *prog, struct bfd * abfd, int from_tty) 136 { 137 check_desc (sd); 138 139 if (!abfd) 140 abfd = open_objfile (prog); 141 if (!abfd) 142 return SIM_RC_FAIL; 143 144 m32c_load (abfd); 145 146 return SIM_RC_OK; 147 } 148 149 SIM_RC 150 sim_create_inferior (SIM_DESC sd, struct bfd * abfd, 151 char * const *argv, char * const *env) 152 { 153 check_desc (sd); 154 155 if (abfd) 156 m32c_load (abfd); 157 158 return SIM_RC_OK; 159 } 160 161 uint64_t 162 sim_read (SIM_DESC sd, uint64_t addr, void *buf, uint64_t length) 163 { 164 check_desc (sd); 165 166 if (addr == 0) 167 return 0; 168 169 mem_get_blk ((int) addr, buf, length); 170 171 return length; 172 } 173 174 uint64_t 175 sim_write (SIM_DESC sd, uint64_t addr, const void *buf, uint64_t length) 176 { 177 check_desc (sd); 178 179 mem_put_blk ((int) addr, buf, length); 180 181 return length; 182 } 183 184 185 /* Read the LENGTH bytes at BUF as an little-endian value. */ 186 static DI 187 get_le (const unsigned char *buf, int length) 188 { 189 DI acc = 0; 190 while (--length >= 0) 191 acc = (acc << 8) + buf[length]; 192 193 return acc; 194 } 195 196 /* Store VAL as a little-endian value in the LENGTH bytes at BUF. */ 197 static void 198 put_le (unsigned char *buf, int length, DI val) 199 { 200 int i; 201 202 for (i = 0; i < length; i++) 203 { 204 buf[i] = val & 0xff; 205 val >>= 8; 206 } 207 } 208 209 static int 210 check_regno (enum m32c_sim_reg regno) 211 { 212 return 0 <= regno && regno < m32c_sim_reg_num_regs; 213 } 214 215 static size_t 216 mask_size (int addr_mask) 217 { 218 switch (addr_mask) 219 { 220 case 0xffff: 221 return 2; 222 case 0xfffff: 223 case 0xffffff: 224 return 3; 225 default: 226 fprintf (stderr, 227 "m32c minisim: addr_mask_size: unexpected mask 0x%x\n", 228 addr_mask); 229 return sizeof (addr_mask); 230 } 231 } 232 233 static size_t 234 reg_size (enum m32c_sim_reg regno) 235 { 236 switch (regno) 237 { 238 case m32c_sim_reg_r0_bank0: 239 case m32c_sim_reg_r1_bank0: 240 case m32c_sim_reg_r2_bank0: 241 case m32c_sim_reg_r3_bank0: 242 case m32c_sim_reg_r0_bank1: 243 case m32c_sim_reg_r1_bank1: 244 case m32c_sim_reg_r2_bank1: 245 case m32c_sim_reg_r3_bank1: 246 case m32c_sim_reg_flg: 247 case m32c_sim_reg_svf: 248 return 2; 249 250 case m32c_sim_reg_a0_bank0: 251 case m32c_sim_reg_a1_bank0: 252 case m32c_sim_reg_fb_bank0: 253 case m32c_sim_reg_sb_bank0: 254 case m32c_sim_reg_a0_bank1: 255 case m32c_sim_reg_a1_bank1: 256 case m32c_sim_reg_fb_bank1: 257 case m32c_sim_reg_sb_bank1: 258 case m32c_sim_reg_usp: 259 case m32c_sim_reg_isp: 260 return mask_size (addr_mask); 261 262 case m32c_sim_reg_pc: 263 case m32c_sim_reg_intb: 264 case m32c_sim_reg_svp: 265 case m32c_sim_reg_vct: 266 return mask_size (membus_mask); 267 268 case m32c_sim_reg_dmd0: 269 case m32c_sim_reg_dmd1: 270 return 1; 271 272 case m32c_sim_reg_dct0: 273 case m32c_sim_reg_dct1: 274 case m32c_sim_reg_drc0: 275 case m32c_sim_reg_drc1: 276 return 2; 277 278 case m32c_sim_reg_dma0: 279 case m32c_sim_reg_dma1: 280 case m32c_sim_reg_dsa0: 281 case m32c_sim_reg_dsa1: 282 case m32c_sim_reg_dra0: 283 case m32c_sim_reg_dra1: 284 return 3; 285 286 default: 287 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 288 regno); 289 return -1; 290 } 291 } 292 293 int 294 sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length) 295 { 296 size_t size; 297 298 check_desc (sd); 299 300 if (!check_regno (regno)) 301 return 0; 302 303 size = reg_size (regno); 304 if (length == size) 305 { 306 DI val; 307 308 switch (regno) 309 { 310 case m32c_sim_reg_r0_bank0: 311 val = regs.r[0].r_r0; 312 break; 313 case m32c_sim_reg_r1_bank0: 314 val = regs.r[0].r_r1; 315 break; 316 case m32c_sim_reg_r2_bank0: 317 val = regs.r[0].r_r2; 318 break; 319 case m32c_sim_reg_r3_bank0: 320 val = regs.r[0].r_r3; 321 break; 322 case m32c_sim_reg_a0_bank0: 323 val = regs.r[0].r_a0; 324 break; 325 case m32c_sim_reg_a1_bank0: 326 val = regs.r[0].r_a1; 327 break; 328 case m32c_sim_reg_fb_bank0: 329 val = regs.r[0].r_fb; 330 break; 331 case m32c_sim_reg_sb_bank0: 332 val = regs.r[0].r_sb; 333 break; 334 case m32c_sim_reg_r0_bank1: 335 val = regs.r[1].r_r0; 336 break; 337 case m32c_sim_reg_r1_bank1: 338 val = regs.r[1].r_r1; 339 break; 340 case m32c_sim_reg_r2_bank1: 341 val = regs.r[1].r_r2; 342 break; 343 case m32c_sim_reg_r3_bank1: 344 val = regs.r[1].r_r3; 345 break; 346 case m32c_sim_reg_a0_bank1: 347 val = regs.r[1].r_a0; 348 break; 349 case m32c_sim_reg_a1_bank1: 350 val = regs.r[1].r_a1; 351 break; 352 case m32c_sim_reg_fb_bank1: 353 val = regs.r[1].r_fb; 354 break; 355 case m32c_sim_reg_sb_bank1: 356 val = regs.r[1].r_sb; 357 break; 358 359 case m32c_sim_reg_usp: 360 val = regs.r_usp; 361 break; 362 case m32c_sim_reg_isp: 363 val = regs.r_isp; 364 break; 365 case m32c_sim_reg_pc: 366 val = regs.r_pc; 367 break; 368 case m32c_sim_reg_intb: 369 val = regs.r_intbl * 65536 + regs.r_intbl; 370 break; 371 case m32c_sim_reg_flg: 372 val = regs.r_flags; 373 break; 374 375 /* These registers aren't implemented by the minisim. */ 376 case m32c_sim_reg_svf: 377 case m32c_sim_reg_svp: 378 case m32c_sim_reg_vct: 379 case m32c_sim_reg_dmd0: 380 case m32c_sim_reg_dmd1: 381 case m32c_sim_reg_dct0: 382 case m32c_sim_reg_dct1: 383 case m32c_sim_reg_drc0: 384 case m32c_sim_reg_drc1: 385 case m32c_sim_reg_dma0: 386 case m32c_sim_reg_dma1: 387 case m32c_sim_reg_dsa0: 388 case m32c_sim_reg_dsa1: 389 case m32c_sim_reg_dra0: 390 case m32c_sim_reg_dra1: 391 return 0; 392 393 default: 394 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 395 regno); 396 return -1; 397 } 398 399 put_le (buf, length, val); 400 } 401 402 return size; 403 } 404 405 int 406 sim_store_register (SIM_DESC sd, int regno, const void *buf, int length) 407 { 408 size_t size; 409 410 check_desc (sd); 411 412 if (!check_regno (regno)) 413 return -1; 414 415 size = reg_size (regno); 416 417 if (length == size) 418 { 419 DI val = get_le (buf, length); 420 421 switch (regno) 422 { 423 case m32c_sim_reg_r0_bank0: 424 regs.r[0].r_r0 = val & 0xffff; 425 break; 426 case m32c_sim_reg_r1_bank0: 427 regs.r[0].r_r1 = val & 0xffff; 428 break; 429 case m32c_sim_reg_r2_bank0: 430 regs.r[0].r_r2 = val & 0xffff; 431 break; 432 case m32c_sim_reg_r3_bank0: 433 regs.r[0].r_r3 = val & 0xffff; 434 break; 435 case m32c_sim_reg_a0_bank0: 436 regs.r[0].r_a0 = val & addr_mask; 437 break; 438 case m32c_sim_reg_a1_bank0: 439 regs.r[0].r_a1 = val & addr_mask; 440 break; 441 case m32c_sim_reg_fb_bank0: 442 regs.r[0].r_fb = val & addr_mask; 443 break; 444 case m32c_sim_reg_sb_bank0: 445 regs.r[0].r_sb = val & addr_mask; 446 break; 447 case m32c_sim_reg_r0_bank1: 448 regs.r[1].r_r0 = val & 0xffff; 449 break; 450 case m32c_sim_reg_r1_bank1: 451 regs.r[1].r_r1 = val & 0xffff; 452 break; 453 case m32c_sim_reg_r2_bank1: 454 regs.r[1].r_r2 = val & 0xffff; 455 break; 456 case m32c_sim_reg_r3_bank1: 457 regs.r[1].r_r3 = val & 0xffff; 458 break; 459 case m32c_sim_reg_a0_bank1: 460 regs.r[1].r_a0 = val & addr_mask; 461 break; 462 case m32c_sim_reg_a1_bank1: 463 regs.r[1].r_a1 = val & addr_mask; 464 break; 465 case m32c_sim_reg_fb_bank1: 466 regs.r[1].r_fb = val & addr_mask; 467 break; 468 case m32c_sim_reg_sb_bank1: 469 regs.r[1].r_sb = val & addr_mask; 470 break; 471 472 case m32c_sim_reg_usp: 473 regs.r_usp = val & addr_mask; 474 break; 475 case m32c_sim_reg_isp: 476 regs.r_isp = val & addr_mask; 477 break; 478 case m32c_sim_reg_pc: 479 regs.r_pc = val & membus_mask; 480 break; 481 case m32c_sim_reg_intb: 482 regs.r_intbl = (val & membus_mask) & 0xffff; 483 regs.r_intbh = (val & membus_mask) >> 16; 484 break; 485 case m32c_sim_reg_flg: 486 regs.r_flags = val & 0xffff; 487 break; 488 489 /* These registers aren't implemented by the minisim. */ 490 case m32c_sim_reg_svf: 491 case m32c_sim_reg_svp: 492 case m32c_sim_reg_vct: 493 case m32c_sim_reg_dmd0: 494 case m32c_sim_reg_dmd1: 495 case m32c_sim_reg_dct0: 496 case m32c_sim_reg_dct1: 497 case m32c_sim_reg_drc0: 498 case m32c_sim_reg_drc1: 499 case m32c_sim_reg_dma0: 500 case m32c_sim_reg_dma1: 501 case m32c_sim_reg_dsa0: 502 case m32c_sim_reg_dsa1: 503 case m32c_sim_reg_dra0: 504 case m32c_sim_reg_dra1: 505 return 0; 506 507 default: 508 fprintf (stderr, "m32c minisim: unrecognized register number: %d\n", 509 regno); 510 return 0; 511 } 512 } 513 514 return size; 515 } 516 517 static volatile int stop; 518 static enum sim_stop reason; 519 static int siggnal; 520 521 522 /* Given a signal number used by the M32C bsp (that is, newlib), 523 return a target signal number used by GDB. */ 524 static int 525 m32c_signal_to_target (int m32c) 526 { 527 switch (m32c) 528 { 529 case 4: 530 return GDB_SIGNAL_ILL; 531 532 case 5: 533 return GDB_SIGNAL_TRAP; 534 535 case 10: 536 return GDB_SIGNAL_BUS; 537 538 case 11: 539 return GDB_SIGNAL_SEGV; 540 541 case 24: 542 return GDB_SIGNAL_XCPU; 543 544 case 2: 545 return GDB_SIGNAL_INT; 546 547 case 8: 548 return GDB_SIGNAL_FPE; 549 550 case 6: 551 return GDB_SIGNAL_ABRT; 552 } 553 554 return 0; 555 } 556 557 558 /* Take a step return code RC and set up the variables consulted by 559 sim_stop_reason appropriately. */ 560 static void 561 handle_step (int rc) 562 { 563 if (M32C_STEPPED (rc) || M32C_HIT_BREAK (rc)) 564 { 565 reason = sim_stopped; 566 siggnal = GDB_SIGNAL_TRAP; 567 } 568 else if (M32C_STOPPED (rc)) 569 { 570 reason = sim_stopped; 571 siggnal = m32c_signal_to_target (M32C_STOP_SIG (rc)); 572 } 573 else 574 { 575 assert (M32C_EXITED (rc)); 576 reason = sim_exited; 577 siggnal = M32C_EXIT_STATUS (rc); 578 } 579 } 580 581 582 void 583 sim_resume (SIM_DESC sd, int step, int sig_to_deliver) 584 { 585 check_desc (sd); 586 587 if (sig_to_deliver != 0) 588 { 589 fprintf (stderr, 590 "Warning: the m32c minisim does not implement " 591 "signal delivery yet.\n" "Resuming with no signal.\n"); 592 } 593 594 if (step) 595 { 596 handle_step (decode_opcode ()); 597 #ifdef TIMER_A 598 update_timer_a (); 599 #endif 600 } 601 else 602 { 603 /* We don't clear 'stop' here, because then we would miss 604 interrupts that arrived on the way here. Instead, we clear 605 the flag in sim_stop_reason, after GDB has disabled the 606 interrupt signal handler. */ 607 for (;;) 608 { 609 int rc; 610 611 if (stop) 612 { 613 stop = 0; 614 reason = sim_stopped; 615 siggnal = GDB_SIGNAL_INT; 616 break; 617 } 618 619 rc = decode_opcode (); 620 #ifdef TIMER_A 621 update_timer_a (); 622 #endif 623 624 if (!M32C_STEPPED (rc)) 625 { 626 handle_step (rc); 627 break; 628 } 629 } 630 } 631 m32c_sim_restore_console (); 632 } 633 634 int 635 sim_stop (SIM_DESC sd) 636 { 637 stop = 1; 638 639 return 1; 640 } 641 642 void 643 sim_stop_reason (SIM_DESC sd, enum sim_stop *reason_p, int *sigrc_p) 644 { 645 check_desc (sd); 646 647 *reason_p = reason; 648 *sigrc_p = siggnal; 649 } 650 651 void 652 sim_do_command (SIM_DESC sd, const char *cmd) 653 { 654 const char *arg; 655 char **argv = buildargv (cmd); 656 657 check_desc (sd); 658 659 cmd = arg = ""; 660 if (argv != NULL) 661 { 662 if (argv[0] != NULL) 663 cmd = argv[0]; 664 if (argv[1] != NULL) 665 arg = argv[1]; 666 } 667 668 if (strcmp (cmd, "trace") == 0) 669 { 670 if (strcmp (arg, "on") == 0) 671 trace = 1; 672 else if (strcmp (arg, "off") == 0) 673 trace = 0; 674 else 675 printf ("The 'sim trace' command expects 'on' or 'off' " 676 "as an argument.\n"); 677 } 678 else if (strcmp (cmd, "verbose") == 0) 679 { 680 if (strcmp (arg, "on") == 0) 681 verbose = 1; 682 else if (strcmp (arg, "off") == 0) 683 verbose = 0; 684 else 685 printf ("The 'sim verbose' command expects 'on' or 'off'" 686 " as an argument.\n"); 687 } 688 else 689 printf ("The 'sim' command expects either 'trace' or 'verbose'" 690 " as a subcommand.\n"); 691 692 freeargv (argv); 693 } 694 695 char ** 696 sim_complete_command (SIM_DESC sd, const char *text, const char *word) 697 { 698 return NULL; 699 } 700 701 char * 702 sim_memory_map (SIM_DESC sd) 703 { 704 return NULL; 705 } 706 707 void 708 sim_info (SIM_DESC sd, bool verbose) 709 { 710 printf ("The m32c minisim doesn't collect any statistics.\n"); 711 } 712