1 /* Simulator cache routines for CGEN simulators (and maybe others). 2 Copyright (C) 1996-2023 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This must come before any other includes. */ 21 #include "defs.h" 22 23 #define SCACHE_DEFINE_INLINE 24 25 #include <stdlib.h> 26 27 #include "libiberty.h" 28 29 #include "sim-main.h" 30 #include "sim-options.h" 31 #include "sim-io.h" 32 33 /* Unused address. */ 34 #define UNUSED_ADDR 0xffffffff 35 36 /* Scache configuration parameters. 37 ??? Experiments to determine reasonable values is wip. 38 These are just guesses. */ 39 40 /* Default number of scache elements. 41 The size of an element is typically 32-64 bytes, so the size of the 42 default scache will be between 512K and 1M bytes. */ 43 #ifdef CONFIG_SIM_CACHE_SIZE 44 #define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE 45 #else 46 #define SCACHE_DEFAULT_CACHE_SIZE 16384 47 #endif 48 49 /* Minimum cache size. 50 The m32r port assumes a cache size of at least 2 so it can decode both 16 51 bit insns. When compiling we need an extra for the chain entry. And this 52 must be a multiple of 2. Hence 4 is the minimum (though, for those with 53 featuritis or itchy pedantic bits, we could make this conditional on 54 WITH_SCACHE_PBB). */ 55 #define MIN_SCACHE_SIZE 4 56 57 /* Ratio of size of text section to size of scache. 58 When compiling, we don't want to flush the scache more than we have to 59 but we also don't want it to be exorbitantly(sp?) large. So we pick a high 60 default value, then reduce it by the size of the program being simulated, 61 but we don't override any value specified on the command line. 62 If not specified on the command line, the size to use is computed as 63 max (MIN_SCACHE_SIZE, 64 min (DEFAULT_SCACHE_SIZE, 65 text_size / (base_insn_size * INSN_SCACHE_RATIO))). */ 66 /* ??? Interesting idea but not currently used. */ 67 #define INSN_SCACHE_RATIO 4 68 69 /* Default maximum insn chain length. 70 The only reason for a maximum is so we can place a maximum size on the 71 profiling table. Chain lengths are determined by cti's. 72 32 is a more reasonable number, but when profiling, the before/after 73 handlers take up that much more space. The scache is filled from front to 74 back so all this determines is when the scache needs to be flushed. */ 75 #define MAX_CHAIN_LENGTH 64 76 77 /* Default maximum hash list length. */ 78 #define MAX_HASH_CHAIN_LENGTH 4 79 80 /* Minimum hash table size. */ 81 #define MIN_HASH_CHAINS 32 82 83 /* Ratio of number of scache elements to number of hash lists. 84 Since the user can only specify the size of the scache, we compute the 85 size of the hash table as 86 max (MIN_HASH_CHAINS, scache_size / SCACHE_HASH_RATIO). */ 87 #define SCACHE_HASH_RATIO 8 88 89 /* Hash a PC value. 90 FIXME: May wish to make the hashing architecture specific. 91 FIXME: revisit */ 92 #define HASH_PC(pc) (((pc) >> 2) + ((pc) >> 5)) 93 94 static MODULE_INIT_FN scache_init; 95 static MODULE_UNINSTALL_FN scache_uninstall; 96 97 static DECLARE_OPTION_HANDLER (scache_option_handler); 98 99 #define OPTION_PROFILE_SCACHE (OPTION_START + 0) 100 101 static const OPTION scache_options[] = { 102 { {"scache-size", optional_argument, NULL, 'c'}, 103 'c', "[SIZE]", "Specify size of simulator execution cache", 104 scache_option_handler }, 105 #if WITH_SCACHE_PBB 106 /* ??? It might be nice to allow the user to specify the size of the hash 107 table, the maximum hash list length, and the maximum chain length, but 108 for now that might be more akin to featuritis. */ 109 #endif 110 { {"profile-scache", optional_argument, NULL, OPTION_PROFILE_SCACHE}, 111 '\0', "on|off", "Perform simulator execution cache profiling", 112 scache_option_handler }, 113 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } 114 }; 115 116 static SIM_RC 117 scache_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, 118 char *arg, int is_command) 119 { 120 switch (opt) 121 { 122 case 'c' : 123 if (WITH_SCACHE) 124 { 125 if (arg != NULL) 126 { 127 unsigned int n = (unsigned int) strtoul (arg, NULL, 0); 128 if (n < MIN_SCACHE_SIZE) 129 { 130 sim_io_eprintf (sd, "invalid scache size `%u', must be at least %u", 131 n, MIN_SCACHE_SIZE); 132 return SIM_RC_FAIL; 133 } 134 /* Ensure it's a multiple of 2. */ 135 if ((n & (n - 1)) != 0) 136 { 137 unsigned int i; 138 sim_io_eprintf (sd, "scache size `%u' not a multiple of 2\n", n); 139 /* Round up to nearest multiple of 2. */ 140 for (i = 1; i && i < n; i <<= 1) 141 continue; 142 if (i) 143 { 144 n = i; 145 sim_io_eprintf (sd, "rounding scache size up to %u\n", n); 146 } 147 } 148 if (cpu == NULL) 149 STATE_SCACHE_SIZE (sd) = n; 150 else 151 CPU_SCACHE_SIZE (cpu) = n; 152 } 153 else 154 { 155 if (cpu == NULL) 156 STATE_SCACHE_SIZE (sd) = SCACHE_DEFAULT_CACHE_SIZE; 157 else 158 CPU_SCACHE_SIZE (cpu) = SCACHE_DEFAULT_CACHE_SIZE; 159 } 160 } 161 else 162 sim_io_eprintf (sd, "Simulator execution cache not enabled, `--scache-size' ignored\n"); 163 break; 164 165 case OPTION_PROFILE_SCACHE : 166 if (WITH_SCACHE && WITH_PROFILE_SCACHE_P) 167 { 168 /* FIXME: handle cpu != NULL. */ 169 return sim_profile_set_option (sd, "-scache", PROFILE_SCACHE_IDX, 170 arg); 171 } 172 else 173 sim_io_eprintf (sd, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n"); 174 break; 175 } 176 177 return SIM_RC_OK; 178 } 179 180 /* Provide a prototype to silence -Wmissing-prototypes. */ 181 SIM_RC sim_install_scache (SIM_DESC sd); 182 183 /* Install the simulator cache into the simulator. */ 184 SIM_RC 185 sim_install_scache (SIM_DESC sd) 186 { 187 sim_add_option_table (sd, NULL, scache_options); 188 sim_module_add_init_fn (sd, scache_init); 189 sim_module_add_uninstall_fn (sd, scache_uninstall); 190 191 /* This is the default, it may be overridden on the command line. */ 192 STATE_SCACHE_SIZE (sd) = WITH_SCACHE; 193 194 return SIM_RC_OK; 195 } 196 197 static SIM_RC 198 scache_init (SIM_DESC sd) 199 { 200 int c; 201 202 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 203 { 204 SIM_CPU *cpu = STATE_CPU (sd, c); 205 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 206 207 /* elm_size is 0 if the cpu doesn't not have scache support */ 208 if (elm_size == 0) 209 { 210 CPU_SCACHE_SIZE (cpu) = 0; 211 CPU_SCACHE_CACHE (cpu) = NULL; 212 } 213 else 214 { 215 if (CPU_SCACHE_SIZE (cpu) == 0) 216 CPU_SCACHE_SIZE (cpu) = STATE_SCACHE_SIZE (sd); 217 CPU_SCACHE_CACHE (cpu) = 218 (SCACHE *) xmalloc (CPU_SCACHE_SIZE (cpu) * elm_size); 219 #if WITH_SCACHE_PBB 220 CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) = MAX_CHAIN_LENGTH; 221 CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) = MAX_HASH_CHAIN_LENGTH; 222 CPU_SCACHE_NUM_HASH_CHAINS (cpu) = max (MIN_HASH_CHAINS, 223 CPU_SCACHE_SIZE (cpu) 224 / SCACHE_HASH_RATIO); 225 CPU_SCACHE_HASH_TABLE (cpu) = 226 (SCACHE_MAP *) xmalloc (CPU_SCACHE_NUM_HASH_CHAINS (cpu) 227 * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) 228 * sizeof (SCACHE_MAP)); 229 CPU_SCACHE_PBB_BEGIN (cpu) = (SCACHE *) zalloc (elm_size); 230 CPU_SCACHE_CHAIN_LENGTHS (cpu) = 231 (unsigned long *) zalloc ((CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) + 1) 232 * sizeof (long)); 233 #endif 234 } 235 } 236 237 scache_flush (sd); 238 239 return SIM_RC_OK; 240 } 241 242 static void 243 scache_uninstall (SIM_DESC sd) 244 { 245 int c; 246 247 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 248 { 249 SIM_CPU *cpu = STATE_CPU (sd, c); 250 251 if (CPU_SCACHE_CACHE (cpu) != NULL) 252 free (CPU_SCACHE_CACHE (cpu)); 253 #if WITH_SCACHE_PBB 254 if (CPU_SCACHE_HASH_TABLE (cpu) != NULL) 255 free (CPU_SCACHE_HASH_TABLE (cpu)); 256 if (CPU_SCACHE_PBB_BEGIN (cpu) != NULL) 257 free (CPU_SCACHE_PBB_BEGIN (cpu)); 258 if (CPU_SCACHE_CHAIN_LENGTHS (cpu) != NULL) 259 free (CPU_SCACHE_CHAIN_LENGTHS (cpu)); 260 #endif 261 } 262 } 263 264 void 265 scache_flush (SIM_DESC sd) 266 { 267 int c; 268 269 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 270 { 271 SIM_CPU *cpu = STATE_CPU (sd, c); 272 scache_flush_cpu (cpu); 273 } 274 } 275 276 void 277 scache_flush_cpu (SIM_CPU *cpu) 278 { 279 int i,n; 280 281 /* Don't bother if cache not in use. */ 282 if (CPU_SCACHE_SIZE (cpu) == 0) 283 return; 284 285 #if WITH_SCACHE_PBB 286 /* It's important that this be reasonably fast as this can be done when 287 the simulation is running. */ 288 CPU_SCACHE_NEXT_FREE (cpu) = CPU_SCACHE_CACHE (cpu); 289 n = CPU_SCACHE_NUM_HASH_CHAINS (cpu) * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 290 /* ??? Might be faster to just set the first entry, then update the 291 "last entry" marker during allocation. */ 292 for (i = 0; i < n; ++i) 293 CPU_SCACHE_HASH_TABLE (cpu) [i] . pc = UNUSED_ADDR; 294 #else 295 { 296 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 297 SCACHE *sc; 298 299 /* Technically, this may not be necessary, but it helps debugging. */ 300 memset (CPU_SCACHE_CACHE (cpu), 0, 301 CPU_SCACHE_SIZE (cpu) * elm_size); 302 303 for (i = 0, sc = CPU_SCACHE_CACHE (cpu); i < CPU_SCACHE_SIZE (cpu); 304 ++i, sc = (SCACHE *) ((char *) sc + elm_size)) 305 { 306 sc->argbuf.addr = UNUSED_ADDR; 307 } 308 } 309 #endif 310 } 311 312 #if WITH_SCACHE_PBB 313 314 /* Look up PC in the hash table of scache entry points. 315 Returns the entry or NULL if not found. */ 316 317 SCACHE * 318 scache_lookup (SIM_CPU *cpu, IADDR pc) 319 { 320 /* FIXME: hash computation is wrong, doesn't take into account 321 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ 322 unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); 323 int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 324 SCACHE_MAP *scm; 325 326 /* We don't update hit/miss statistics as this is only used when recording 327 branch target addresses. */ 328 329 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 330 for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) 331 { 332 if (scm->pc == pc) 333 return scm->sc; 334 } 335 return 0; 336 } 337 338 /* Look up PC and if not found create an entry for it. 339 If found the result is a pointer to the SCACHE entry. 340 If not found the result is NULL, and the address of a buffer of at least 341 N entries is stored in BUFP. 342 It's done this way so the caller can still distinguish found/not-found. 343 If the table is full, it is emptied to make room. 344 If the maximum length of a hash list is reached a random entry is thrown out 345 to make room. 346 ??? One might want to try to make this smarter, but let's see some 347 measurable benefit first. */ 348 349 SCACHE * 350 scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) 351 { 352 /* FIXME: hash computation is wrong, doesn't take into account 353 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ 354 unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); 355 int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 356 SCACHE_MAP *scm; 357 SCACHE *sc; 358 359 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 360 for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) 361 { 362 if (scm->pc == pc) 363 { 364 PROFILE_COUNT_SCACHE_HIT (cpu); 365 return scm->sc; 366 } 367 } 368 PROFILE_COUNT_SCACHE_MISS (cpu); 369 370 /* The address we want isn't cached. Bummer. 371 If the hash chain we have for this address is full, throw out an entry 372 to make room. */ 373 374 if (i == max_i) 375 { 376 /* Rather than do something sophisticated like LRU, we just throw out 377 a semi-random entry. Let someone else have the joy of saying how 378 wrong this is. NEXT_FREE is the entry to throw out and cycles 379 through all possibilities. */ 380 static int next_free = 0; 381 382 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 383 /* FIXME: This seems rather clumsy. */ 384 for (i = 0; i < next_free; ++i, ++scm) 385 continue; 386 ++next_free; 387 if (next_free == CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu)) 388 next_free = 0; 389 } 390 391 /* At this point SCM points to the hash table entry to use. 392 Now make sure there's room in the cache. */ 393 /* FIXME: Kinda weird to use a next_free adjusted scm when cache is 394 flushed. */ 395 396 { 397 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 398 int elms_used = (((char *) CPU_SCACHE_NEXT_FREE (cpu) 399 - (char *) CPU_SCACHE_CACHE (cpu)) 400 / elm_size); 401 int elms_left = CPU_SCACHE_SIZE (cpu) - elms_used; 402 403 if (elms_left < n) 404 { 405 PROFILE_COUNT_SCACHE_FULL_FLUSH (cpu); 406 scache_flush_cpu (cpu); 407 } 408 } 409 410 sc = CPU_SCACHE_NEXT_FREE (cpu); 411 scm->pc = pc; 412 scm->sc = sc; 413 414 *bufp = sc; 415 return NULL; 416 } 417 418 #endif /* WITH_SCACHE_PBB */ 419 420 /* Print cache access statics for CPU. */ 421 422 void 423 scache_print_profile (SIM_CPU *cpu, int verbose) 424 { 425 SIM_DESC sd = CPU_STATE (cpu); 426 unsigned long hits = CPU_SCACHE_HITS (cpu); 427 unsigned long misses = CPU_SCACHE_MISSES (cpu); 428 char buf[20]; 429 unsigned long max_val; 430 unsigned long *lengths; 431 int i; 432 433 if (CPU_SCACHE_SIZE (cpu) == 0) 434 return; 435 436 sim_io_printf (sd, "Simulator Cache Statistics\n\n"); 437 438 /* One could use PROFILE_LABEL_WIDTH here. I chose not to. */ 439 sim_io_printf (sd, " Cache size: %s\n", 440 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_SIZE (cpu))); 441 sim_io_printf (sd, " Hits: %s\n", 442 sim_add_commas (buf, sizeof (buf), hits)); 443 sim_io_printf (sd, " Misses: %s\n", 444 sim_add_commas (buf, sizeof (buf), misses)); 445 if (hits + misses != 0) 446 sim_io_printf (sd, " Hit rate: %.2f%%\n", 447 ((double) hits / ((double) hits + (double) misses)) * 100); 448 449 #if WITH_SCACHE_PBB 450 sim_io_printf (sd, "\n"); 451 sim_io_printf (sd, " Hash table size: %s\n", 452 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAINS (cpu))); 453 sim_io_printf (sd, " Max hash list length: %s\n", 454 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu))); 455 sim_io_printf (sd, " Max insn chain length: %s\n", 456 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_MAX_CHAIN_LENGTH (cpu))); 457 sim_io_printf (sd, " Cache full flushes: %s\n", 458 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_FULL_FLUSHES (cpu))); 459 sim_io_printf (sd, "\n"); 460 461 if (verbose) 462 { 463 sim_io_printf (sd, " Insn chain lengths:\n\n"); 464 max_val = 0; 465 lengths = CPU_SCACHE_CHAIN_LENGTHS (cpu); 466 for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) 467 if (lengths[i] > max_val) 468 max_val = lengths[i]; 469 for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) 470 { 471 sim_io_printf (sd, " %2d: %*s: ", 472 i, 473 max_val < 10000 ? 5 : 10, 474 sim_add_commas (buf, sizeof (buf), lengths[i])); 475 sim_profile_print_bar (sd, cpu, PROFILE_HISTOGRAM_WIDTH, 476 lengths[i], max_val); 477 sim_io_printf (sd, "\n"); 478 } 479 sim_io_printf (sd, "\n"); 480 } 481 #endif /* WITH_SCACHE_PBB */ 482 } 483