1 /* Simulator cache routines for CGEN simulators (and maybe others). 2 Copyright (C) 1996-2024 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This must come before any other includes. */ 21 #include "defs.h" 22 23 #define SCACHE_DEFINE_INLINE 24 25 #include <stdlib.h> 26 27 #include "libiberty.h" 28 29 #include "sim-main.h" 30 #include "sim-options.h" 31 #include "sim-io.h" 32 33 /* Unused address. */ 34 #define UNUSED_ADDR 0xffffffff 35 36 /* Scache configuration parameters. 37 ??? Experiments to determine reasonable values is wip. 38 These are just guesses. */ 39 40 /* Default number of scache elements. 41 The size of an element is typically 32-64 bytes, so the size of the 42 default scache will be between 512K and 1M bytes. */ 43 #ifdef CONFIG_SIM_CACHE_SIZE 44 #define SCACHE_DEFAULT_CACHE_SIZE CONFIG_SIM_CACHE_SIZE 45 #else 46 #define SCACHE_DEFAULT_CACHE_SIZE 16384 47 #endif 48 49 /* Minimum cache size. 50 The m32r port assumes a cache size of at least 2 so it can decode both 16 51 bit insns. When compiling we need an extra for the chain entry. And this 52 must be a multiple of 2. Hence 4 is the minimum (though, for those with 53 featuritis or itchy pedantic bits, we could make this conditional on 54 WITH_SCACHE_PBB). */ 55 #define MIN_SCACHE_SIZE 4 56 57 /* Ratio of size of text section to size of scache. 58 When compiling, we don't want to flush the scache more than we have to 59 but we also don't want it to be exorbitantly(sp?) large. So we pick a high 60 default value, then reduce it by the size of the program being simulated, 61 but we don't override any value specified on the command line. 62 If not specified on the command line, the size to use is computed as 63 max (MIN_SCACHE_SIZE, 64 min (DEFAULT_SCACHE_SIZE, 65 text_size / (base_insn_size * INSN_SCACHE_RATIO))). */ 66 /* ??? Interesting idea but not currently used. */ 67 #define INSN_SCACHE_RATIO 4 68 69 /* Default maximum insn chain length. 70 The only reason for a maximum is so we can place a maximum size on the 71 profiling table. Chain lengths are determined by cti's. 72 32 is a more reasonable number, but when profiling, the before/after 73 handlers take up that much more space. The scache is filled from front to 74 back so all this determines is when the scache needs to be flushed. */ 75 #define MAX_CHAIN_LENGTH 64 76 77 /* Default maximum hash list length. */ 78 #define MAX_HASH_CHAIN_LENGTH 4 79 80 /* Minimum hash table size. */ 81 #define MIN_HASH_CHAINS 32 82 83 /* Ratio of number of scache elements to number of hash lists. 84 Since the user can only specify the size of the scache, we compute the 85 size of the hash table as 86 max (MIN_HASH_CHAINS, scache_size / SCACHE_HASH_RATIO). */ 87 #define SCACHE_HASH_RATIO 8 88 89 /* Hash a PC value. 90 FIXME: May wish to make the hashing architecture specific. 91 FIXME: revisit */ 92 #define HASH_PC(pc) (((pc) >> 2) + ((pc) >> 5)) 93 94 static MODULE_INIT_FN scache_init; 95 static MODULE_UNINSTALL_FN scache_uninstall; 96 97 static DECLARE_OPTION_HANDLER (scache_option_handler); 98 99 #define OPTION_PROFILE_SCACHE (OPTION_START + 0) 100 101 static const OPTION scache_options[] = { 102 { {"scache-size", optional_argument, NULL, 'c'}, 103 'c', "[SIZE]", "Specify size of simulator execution cache", 104 scache_option_handler }, 105 #if WITH_SCACHE_PBB 106 /* ??? It might be nice to allow the user to specify the size of the hash 107 table, the maximum hash list length, and the maximum chain length, but 108 for now that might be more akin to featuritis. */ 109 #endif 110 { {"profile-scache", optional_argument, NULL, OPTION_PROFILE_SCACHE}, 111 '\0', "on|off", "Perform simulator execution cache profiling", 112 scache_option_handler }, 113 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL } 114 }; 115 116 static SIM_RC 117 scache_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, 118 char *arg, int is_command) 119 { 120 switch (opt) 121 { 122 case 'c' : 123 if (WITH_SCACHE) 124 { 125 if (arg != NULL) 126 { 127 unsigned int n = (unsigned int) strtoul (arg, NULL, 0); 128 if (n < MIN_SCACHE_SIZE) 129 { 130 sim_io_eprintf (sd, "invalid scache size `%u', must be at least %u", 131 n, MIN_SCACHE_SIZE); 132 return SIM_RC_FAIL; 133 } 134 /* Ensure it's a multiple of 2. */ 135 if ((n & (n - 1)) != 0) 136 { 137 unsigned int i; 138 sim_io_eprintf (sd, "scache size `%u' not a multiple of 2\n", n); 139 /* Round up to nearest multiple of 2. */ 140 for (i = 1; i && i < n; i <<= 1) 141 continue; 142 if (i) 143 { 144 n = i; 145 sim_io_eprintf (sd, "rounding scache size up to %u\n", n); 146 } 147 } 148 if (cpu == NULL) 149 STATE_SCACHE_SIZE (sd) = n; 150 else 151 CPU_SCACHE_SIZE (cpu) = n; 152 } 153 else 154 { 155 if (cpu == NULL) 156 STATE_SCACHE_SIZE (sd) = SCACHE_DEFAULT_CACHE_SIZE; 157 else 158 CPU_SCACHE_SIZE (cpu) = SCACHE_DEFAULT_CACHE_SIZE; 159 } 160 } 161 else 162 sim_io_eprintf (sd, "Simulator execution cache not enabled, `--scache-size' ignored\n"); 163 break; 164 165 case OPTION_PROFILE_SCACHE : 166 if (WITH_SCACHE && WITH_PROFILE_SCACHE_P) 167 { 168 /* FIXME: handle cpu != NULL. */ 169 return sim_profile_set_option (sd, "-scache", PROFILE_SCACHE_IDX, 170 arg); 171 } 172 else 173 sim_io_eprintf (sd, "Simulator cache profiling not compiled in, `--profile-scache' ignored\n"); 174 break; 175 } 176 177 return SIM_RC_OK; 178 } 179 180 /* Provide a prototype to silence -Wmissing-prototypes. */ 181 SIM_RC sim_install_scache (SIM_DESC sd); 182 183 /* Install the simulator cache into the simulator. */ 184 SIM_RC 185 sim_install_scache (SIM_DESC sd) 186 { 187 sim_add_option_table (sd, NULL, scache_options); 188 sim_module_add_init_fn (sd, scache_init); 189 sim_module_add_uninstall_fn (sd, scache_uninstall); 190 191 /* This is the default, it may be overridden on the command line. */ 192 STATE_SCACHE_SIZE (sd) = WITH_SCACHE; 193 194 return SIM_RC_OK; 195 } 196 197 static SIM_RC 198 scache_init (SIM_DESC sd) 199 { 200 int c; 201 202 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 203 { 204 SIM_CPU *cpu = STATE_CPU (sd, c); 205 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 206 207 /* elm_size is 0 if the cpu doesn't not have scache support */ 208 if (elm_size == 0) 209 { 210 CPU_SCACHE_SIZE (cpu) = 0; 211 CPU_SCACHE_CACHE (cpu) = NULL; 212 } 213 else 214 { 215 if (CPU_SCACHE_SIZE (cpu) == 0) 216 CPU_SCACHE_SIZE (cpu) = STATE_SCACHE_SIZE (sd); 217 CPU_SCACHE_CACHE (cpu) = 218 (SCACHE *) xmalloc (CPU_SCACHE_SIZE (cpu) * elm_size); 219 #if WITH_SCACHE_PBB 220 CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) = MAX_CHAIN_LENGTH; 221 CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) = MAX_HASH_CHAIN_LENGTH; 222 CPU_SCACHE_NUM_HASH_CHAINS (cpu) = max (MIN_HASH_CHAINS, 223 CPU_SCACHE_SIZE (cpu) 224 / SCACHE_HASH_RATIO); 225 CPU_SCACHE_HASH_TABLE (cpu) = 226 (SCACHE_MAP *) xmalloc (CPU_SCACHE_NUM_HASH_CHAINS (cpu) 227 * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu) 228 * sizeof (SCACHE_MAP)); 229 CPU_SCACHE_PBB_BEGIN (cpu) = (SCACHE *) zalloc (elm_size); 230 CPU_SCACHE_CHAIN_LENGTHS (cpu) = 231 (unsigned long *) zalloc ((CPU_SCACHE_MAX_CHAIN_LENGTH (cpu) + 1) 232 * sizeof (long)); 233 #endif 234 } 235 } 236 237 scache_flush (sd); 238 239 return SIM_RC_OK; 240 } 241 242 static void 243 scache_uninstall (SIM_DESC sd) 244 { 245 int c; 246 247 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 248 { 249 SIM_CPU *cpu = STATE_CPU (sd, c); 250 251 if (CPU_SCACHE_CACHE (cpu) != NULL) 252 free (CPU_SCACHE_CACHE (cpu)); 253 #if WITH_SCACHE_PBB 254 if (CPU_SCACHE_HASH_TABLE (cpu) != NULL) 255 free (CPU_SCACHE_HASH_TABLE (cpu)); 256 if (CPU_SCACHE_PBB_BEGIN (cpu) != NULL) 257 free (CPU_SCACHE_PBB_BEGIN (cpu)); 258 if (CPU_SCACHE_CHAIN_LENGTHS (cpu) != NULL) 259 free (CPU_SCACHE_CHAIN_LENGTHS (cpu)); 260 #endif 261 } 262 } 263 264 void 265 scache_flush (SIM_DESC sd) 266 { 267 int c; 268 269 for (c = 0; c < MAX_NR_PROCESSORS; ++c) 270 { 271 SIM_CPU *cpu = STATE_CPU (sd, c); 272 scache_flush_cpu (cpu); 273 } 274 } 275 276 void 277 scache_flush_cpu (SIM_CPU *cpu) 278 { 279 int i; 280 #if WITH_SCACHE_PBB 281 int n; 282 #endif 283 284 /* Don't bother if cache not in use. */ 285 if (CPU_SCACHE_SIZE (cpu) == 0) 286 return; 287 288 #if WITH_SCACHE_PBB 289 /* It's important that this be reasonably fast as this can be done when 290 the simulation is running. */ 291 CPU_SCACHE_NEXT_FREE (cpu) = CPU_SCACHE_CACHE (cpu); 292 n = CPU_SCACHE_NUM_HASH_CHAINS (cpu) * CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 293 /* ??? Might be faster to just set the first entry, then update the 294 "last entry" marker during allocation. */ 295 for (i = 0; i < n; ++i) 296 CPU_SCACHE_HASH_TABLE (cpu) [i] . pc = UNUSED_ADDR; 297 #else 298 { 299 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 300 SCACHE *sc; 301 302 /* Technically, this may not be necessary, but it helps debugging. */ 303 memset (CPU_SCACHE_CACHE (cpu), 0, 304 CPU_SCACHE_SIZE (cpu) * elm_size); 305 306 for (i = 0, sc = CPU_SCACHE_CACHE (cpu); i < CPU_SCACHE_SIZE (cpu); 307 ++i, sc = (SCACHE *) ((char *) sc + elm_size)) 308 { 309 sc->argbuf.addr = UNUSED_ADDR; 310 } 311 } 312 #endif 313 } 314 315 #if WITH_SCACHE_PBB 316 317 /* Look up PC in the hash table of scache entry points. 318 Returns the entry or NULL if not found. */ 319 320 SCACHE * 321 scache_lookup (SIM_CPU *cpu, IADDR pc) 322 { 323 /* FIXME: hash computation is wrong, doesn't take into account 324 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ 325 unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); 326 int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 327 SCACHE_MAP *scm; 328 329 /* We don't update hit/miss statistics as this is only used when recording 330 branch target addresses. */ 331 332 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 333 for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) 334 { 335 if (scm->pc == pc) 336 return scm->sc; 337 } 338 return 0; 339 } 340 341 /* Look up PC and if not found create an entry for it. 342 If found the result is a pointer to the SCACHE entry. 343 If not found the result is NULL, and the address of a buffer of at least 344 N entries is stored in BUFP. 345 It's done this way so the caller can still distinguish found/not-found. 346 If the table is full, it is emptied to make room. 347 If the maximum length of a hash list is reached a random entry is thrown out 348 to make room. 349 ??? One might want to try to make this smarter, but let's see some 350 measurable benefit first. */ 351 352 SCACHE * 353 scache_lookup_or_alloc (SIM_CPU *cpu, IADDR pc, int n, SCACHE **bufp) 354 { 355 /* FIXME: hash computation is wrong, doesn't take into account 356 NUM_HASH_CHAIN_ENTRIES. A lot of the hash table will be unused! */ 357 unsigned int slot = HASH_PC (pc) & (CPU_SCACHE_NUM_HASH_CHAINS (cpu) - 1); 358 int i, max_i = CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu); 359 SCACHE_MAP *scm; 360 SCACHE *sc; 361 362 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 363 for (i = 0; i < max_i && scm->pc != UNUSED_ADDR; ++i, ++scm) 364 { 365 if (scm->pc == pc) 366 { 367 PROFILE_COUNT_SCACHE_HIT (cpu); 368 return scm->sc; 369 } 370 } 371 PROFILE_COUNT_SCACHE_MISS (cpu); 372 373 /* The address we want isn't cached. Bummer. 374 If the hash chain we have for this address is full, throw out an entry 375 to make room. */ 376 377 if (i == max_i) 378 { 379 /* Rather than do something sophisticated like LRU, we just throw out 380 a semi-random entry. Let someone else have the joy of saying how 381 wrong this is. NEXT_FREE is the entry to throw out and cycles 382 through all possibilities. */ 383 static int next_free = 0; 384 385 scm = & CPU_SCACHE_HASH_TABLE (cpu) [slot]; 386 /* FIXME: This seems rather clumsy. */ 387 for (i = 0; i < next_free; ++i, ++scm) 388 continue; 389 ++next_free; 390 if (next_free == CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu)) 391 next_free = 0; 392 } 393 394 /* At this point SCM points to the hash table entry to use. 395 Now make sure there's room in the cache. */ 396 /* FIXME: Kinda weird to use a next_free adjusted scm when cache is 397 flushed. */ 398 399 { 400 int elm_size = IMP_PROPS_SCACHE_ELM_SIZE (MACH_IMP_PROPS (CPU_MACH (cpu))); 401 int elms_used = (((char *) CPU_SCACHE_NEXT_FREE (cpu) 402 - (char *) CPU_SCACHE_CACHE (cpu)) 403 / elm_size); 404 int elms_left = CPU_SCACHE_SIZE (cpu) - elms_used; 405 406 if (elms_left < n) 407 { 408 PROFILE_COUNT_SCACHE_FULL_FLUSH (cpu); 409 scache_flush_cpu (cpu); 410 } 411 } 412 413 sc = CPU_SCACHE_NEXT_FREE (cpu); 414 scm->pc = pc; 415 scm->sc = sc; 416 417 *bufp = sc; 418 return NULL; 419 } 420 421 #endif /* WITH_SCACHE_PBB */ 422 423 /* Print cache access statics for CPU. */ 424 425 void 426 scache_print_profile (SIM_CPU *cpu, bool verbose) 427 { 428 SIM_DESC sd = CPU_STATE (cpu); 429 unsigned long hits = CPU_SCACHE_HITS (cpu); 430 unsigned long misses = CPU_SCACHE_MISSES (cpu); 431 char buf[20]; 432 433 if (CPU_SCACHE_SIZE (cpu) == 0) 434 return; 435 436 sim_io_printf (sd, "Simulator Cache Statistics\n\n"); 437 438 /* One could use PROFILE_LABEL_WIDTH here. I chose not to. */ 439 sim_io_printf (sd, " Cache size: %s\n", 440 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_SIZE (cpu))); 441 sim_io_printf (sd, " Hits: %s\n", 442 sim_add_commas (buf, sizeof (buf), hits)); 443 sim_io_printf (sd, " Misses: %s\n", 444 sim_add_commas (buf, sizeof (buf), misses)); 445 if (hits + misses != 0) 446 sim_io_printf (sd, " Hit rate: %.2f%%\n", 447 ((double) hits / ((double) hits + (double) misses)) * 100); 448 449 #if WITH_SCACHE_PBB 450 sim_io_printf (sd, "\n"); 451 sim_io_printf (sd, " Hash table size: %s\n", 452 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAINS (cpu))); 453 sim_io_printf (sd, " Max hash list length: %s\n", 454 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_NUM_HASH_CHAIN_ENTRIES (cpu))); 455 sim_io_printf (sd, " Max insn chain length: %s\n", 456 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_MAX_CHAIN_LENGTH (cpu))); 457 sim_io_printf (sd, " Cache full flushes: %s\n", 458 sim_add_commas (buf, sizeof (buf), CPU_SCACHE_FULL_FLUSHES (cpu))); 459 sim_io_printf (sd, "\n"); 460 461 if (verbose) 462 { 463 unsigned long max_val; 464 unsigned long *lengths; 465 int i; 466 467 sim_io_printf (sd, " Insn chain lengths:\n\n"); 468 max_val = 0; 469 lengths = CPU_SCACHE_CHAIN_LENGTHS (cpu); 470 for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) 471 if (lengths[i] > max_val) 472 max_val = lengths[i]; 473 for (i = 1; i < CPU_SCACHE_MAX_CHAIN_LENGTH (cpu); ++i) 474 { 475 sim_io_printf (sd, " %2d: %*s: ", 476 i, 477 max_val < 10000 ? 5 : 10, 478 sim_add_commas (buf, sizeof (buf), lengths[i])); 479 sim_profile_print_bar (sd, cpu, PROFILE_HISTOGRAM_WIDTH, 480 lengths[i], max_val); 481 sim_io_printf (sd, "\n"); 482 } 483 sim_io_printf (sd, "\n"); 484 } 485 #endif /* WITH_SCACHE_PBB */ 486 } 487