1 /* Blackfin Watchpoint (WP) model. 2 3 Copyright (C) 2010-2024 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include "sim-main.h" 25 #include "devices.h" 26 #include "dv-bfin_wp.h" 27 28 /* XXX: This is mostly a stub. */ 29 30 #define WPI_NUM 6 /* 6 instruction watchpoints. */ 31 #define WPD_NUM 2 /* 2 data watchpoints. */ 32 33 struct bfin_wp 34 { 35 bu32 base; 36 37 /* Order after here is important -- matches hardware MMR layout. */ 38 bu32 iactl; 39 bu32 _pad0[15]; 40 bu32 ia[WPI_NUM]; 41 bu32 _pad1[16 - WPI_NUM]; 42 bu32 iacnt[WPI_NUM]; 43 bu32 _pad2[32 - WPI_NUM]; 44 45 bu32 dactl; 46 bu32 _pad3[15]; 47 bu32 da[WPD_NUM]; 48 bu32 _pad4[16 - WPD_NUM]; 49 bu32 dacnt[WPD_NUM]; 50 bu32 _pad5[32 - WPD_NUM]; 51 52 bu32 stat; 53 }; 54 #define mmr_base() offsetof(struct bfin_wp, iactl) 55 #define mmr_offset(mmr) (offsetof(struct bfin_wp, mmr) - mmr_base()) 56 #define mmr_idx(mmr) (mmr_offset (mmr) / 4) 57 58 static const char * const mmr_names[] = 59 { 60 [mmr_idx (iactl)] = "WPIACTL", 61 [mmr_idx (ia)] = "WPIA0", "WPIA1", "WPIA2", "WPIA3", "WPIA4", "WPIA5", 62 [mmr_idx (iacnt)] = "WPIACNT0", "WPIACNT1", "WPIACNT2", 63 "WPIACNT3", "WPIACNT4", "WPIACNT5", 64 [mmr_idx (dactl)] = "WPDACTL", 65 [mmr_idx (da)] = "WPDA0", "WPDA1", "WPDA2", "WPDA3", "WPDA4", "WPDA5", 66 [mmr_idx (dacnt)] = "WPDACNT0", "WPDACNT1", "WPDACNT2", 67 "WPDACNT3", "WPDACNT4", "WPDACNT5", 68 [mmr_idx (stat)] = "WPSTAT", 69 }; 70 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") 71 72 static unsigned 73 bfin_wp_io_write_buffer (struct hw *me, const void *source, int space, 74 address_word addr, unsigned nr_bytes) 75 { 76 struct bfin_wp *wp = hw_data (me); 77 bu32 mmr_off; 78 bu32 value; 79 bu32 *valuep; 80 81 /* Invalid access mode is higher priority than missing register. */ 82 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true)) 83 return 0; 84 85 value = dv_load_4 (source); 86 mmr_off = addr - wp->base; 87 valuep = (void *)((uintptr_t)wp + mmr_base() + mmr_off); 88 89 HW_TRACE_WRITE (); 90 91 switch (mmr_off) 92 { 93 case mmr_offset(iactl): 94 case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): 95 case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): 96 case mmr_offset(dactl): 97 case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): 98 case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): 99 *valuep = value; 100 break; 101 case mmr_offset(stat): 102 /* Yes, the hardware is this dumb -- clear all bits on any write. */ 103 *valuep = 0; 104 break; 105 default: 106 dv_bfin_mmr_invalid (me, addr, nr_bytes, true); 107 return 0; 108 } 109 110 return nr_bytes; 111 } 112 113 static unsigned 114 bfin_wp_io_read_buffer (struct hw *me, void *dest, int space, 115 address_word addr, unsigned nr_bytes) 116 { 117 struct bfin_wp *wp = hw_data (me); 118 bu32 mmr_off; 119 bu32 value; 120 bu32 *valuep; 121 122 /* Invalid access mode is higher priority than missing register. */ 123 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false)) 124 return 0; 125 126 mmr_off = addr - wp->base; 127 valuep = (void *)((uintptr_t)wp + mmr_base() + mmr_off); 128 129 HW_TRACE_READ (); 130 131 switch (mmr_off) 132 { 133 case mmr_offset(iactl): 134 case mmr_offset(ia[0]) ... mmr_offset(ia[WPI_NUM - 1]): 135 case mmr_offset(iacnt[0]) ... mmr_offset(iacnt[WPI_NUM - 1]): 136 case mmr_offset(dactl): 137 case mmr_offset(da[0]) ... mmr_offset(da[WPD_NUM - 1]): 138 case mmr_offset(dacnt[0]) ... mmr_offset(dacnt[WPD_NUM - 1]): 139 case mmr_offset(stat): 140 value = *valuep; 141 break; 142 default: 143 dv_bfin_mmr_invalid (me, addr, nr_bytes, false); 144 return 0; 145 } 146 147 dv_store_4 (dest, value); 148 149 return nr_bytes; 150 } 151 152 static void 153 attach_bfin_wp_regs (struct hw *me, struct bfin_wp *wp) 154 { 155 address_word attach_address; 156 int attach_space; 157 unsigned attach_size; 158 reg_property_spec reg; 159 160 if (hw_find_property (me, "reg") == NULL) 161 hw_abort (me, "Missing \"reg\" property"); 162 163 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 164 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 165 166 hw_unit_address_to_attach_address (hw_parent (me), 167 ®.address, 168 &attach_space, &attach_address, me); 169 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 170 171 if (attach_size != BFIN_COREMMR_WP_SIZE) 172 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_WP_SIZE); 173 174 hw_attach_address (hw_parent (me), 175 0, attach_space, attach_address, attach_size, me); 176 177 wp->base = attach_address; 178 } 179 180 static void 181 bfin_wp_finish (struct hw *me) 182 { 183 struct bfin_wp *wp; 184 185 wp = HW_ZALLOC (me, struct bfin_wp); 186 187 set_hw_data (me, wp); 188 set_hw_io_read_buffer (me, bfin_wp_io_read_buffer); 189 set_hw_io_write_buffer (me, bfin_wp_io_write_buffer); 190 191 attach_bfin_wp_regs (me, wp); 192 } 193 194 const struct hw_descriptor dv_bfin_wp_descriptor[] = 195 { 196 {"bfin_wp", bfin_wp_finish,}, 197 {NULL, NULL}, 198 }; 199