1 /* Blackfin Trace (TBUF) model. 2 3 Copyright (C) 2010-2024 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #include "sim-main.h" 25 #include "devices.h" 26 #include "dv-bfin_cec.h" 27 #include "dv-bfin_trace.h" 28 29 /* Note: The circular buffering here might look a little buggy wrt mid-reads 30 and consuming the top entry, but this is simulating hardware behavior. 31 The hardware is simple, dumb, and fast. Don't write dumb Blackfin 32 software and you won't have a problem. */ 33 34 /* The hardware is limited to 16 entries and defines TBUFCTL. Let's extend it ;). */ 35 #ifndef SIM_BFIN_TRACE_DEPTH 36 #define SIM_BFIN_TRACE_DEPTH 6 37 #endif 38 #define SIM_BFIN_TRACE_LEN (1 << SIM_BFIN_TRACE_DEPTH) 39 #define SIM_BFIN_TRACE_LEN_MASK (SIM_BFIN_TRACE_LEN - 1) 40 41 struct bfin_trace_entry 42 { 43 bu32 src, dst; 44 }; 45 struct bfin_trace 46 { 47 bu32 base; 48 struct bfin_trace_entry buffer[SIM_BFIN_TRACE_LEN]; 49 int top, bottom; 50 bool mid; 51 52 /* Order after here is important -- matches hardware MMR layout. */ 53 bu32 tbufctl, tbufstat; 54 char _pad[0x100 - 0x8]; 55 bu32 tbuf; 56 }; 57 #define mmr_base() offsetof(struct bfin_trace, tbufctl) 58 #define mmr_offset(mmr) (offsetof(struct bfin_trace, mmr) - mmr_base()) 59 60 static const char * const mmr_names[] = 61 { 62 "TBUFCTL", "TBUFSTAT", [mmr_offset (tbuf) / 4] = "TBUF", 63 }; 64 #define mmr_name(off) (mmr_names[(off) / 4] ? : "<INV>") 65 66 /* Ugh, circular buffers. */ 67 #define TBUF_LEN(t) ((t)->top - (t)->bottom) 68 #define TBUF_IDX(i) ((i) & SIM_BFIN_TRACE_LEN_MASK) 69 /* TOP is the next slot to fill. */ 70 #define TBUF_TOP(t) (&(t)->buffer[TBUF_IDX ((t)->top)]) 71 /* LAST is the latest valid slot. */ 72 #define TBUF_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 1)]) 73 /* LAST_LAST is the second-to-last valid slot. */ 74 #define TBUF_LAST_LAST(t) (&(t)->buffer[TBUF_IDX ((t)->top - 2)]) 75 76 static unsigned 77 bfin_trace_io_write_buffer (struct hw *me, const void *source, 78 int space, address_word addr, unsigned nr_bytes) 79 { 80 struct bfin_trace *trace = hw_data (me); 81 bu32 mmr_off; 82 bu32 value; 83 84 /* Invalid access mode is higher priority than missing register. */ 85 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true)) 86 return 0; 87 88 value = dv_load_4 (source); 89 mmr_off = addr - trace->base; 90 91 HW_TRACE_WRITE (); 92 93 switch (mmr_off) 94 { 95 case mmr_offset(tbufctl): 96 trace->tbufctl = value; 97 break; 98 case mmr_offset(tbufstat): 99 case mmr_offset(tbuf): 100 /* Discard writes to these. */ 101 break; 102 default: 103 dv_bfin_mmr_invalid (me, addr, nr_bytes, true); 104 return 0; 105 } 106 107 return nr_bytes; 108 } 109 110 static unsigned 111 bfin_trace_io_read_buffer (struct hw *me, void *dest, 112 int space, address_word addr, unsigned nr_bytes) 113 { 114 struct bfin_trace *trace = hw_data (me); 115 bu32 mmr_off; 116 bu32 value; 117 118 /* Invalid access mode is higher priority than missing register. */ 119 if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false)) 120 return 0; 121 122 mmr_off = addr - trace->base; 123 124 HW_TRACE_READ (); 125 126 switch (mmr_off) 127 { 128 case mmr_offset(tbufctl): 129 value = trace->tbufctl; 130 break; 131 case mmr_offset(tbufstat): 132 /* Hardware is limited to 16 entries, so to stay compatible with 133 software, limit the value to 16. For software algorithms that 134 keep reading while (TBUFSTAT != 0), they'll get all of it. */ 135 value = min (TBUF_LEN (trace), 16); 136 break; 137 case mmr_offset(tbuf): 138 { 139 struct bfin_trace_entry *e; 140 141 if (TBUF_LEN (trace) == 0) 142 { 143 value = 0; 144 break; 145 } 146 147 e = TBUF_LAST (trace); 148 if (trace->mid) 149 { 150 value = e->src; 151 --trace->top; 152 } 153 else 154 value = e->dst; 155 trace->mid = !trace->mid; 156 157 break; 158 } 159 default: 160 dv_bfin_mmr_invalid (me, addr, nr_bytes, false); 161 return 0; 162 } 163 164 dv_store_4 (dest, value); 165 166 return nr_bytes; 167 } 168 169 static void 170 attach_bfin_trace_regs (struct hw *me, struct bfin_trace *trace) 171 { 172 address_word attach_address; 173 int attach_space; 174 unsigned attach_size; 175 reg_property_spec reg; 176 177 if (hw_find_property (me, "reg") == NULL) 178 hw_abort (me, "Missing \"reg\" property"); 179 180 if (!hw_find_reg_array_property (me, "reg", 0, ®)) 181 hw_abort (me, "\"reg\" property must contain three addr/size entries"); 182 183 hw_unit_address_to_attach_address (hw_parent (me), 184 ®.address, 185 &attach_space, &attach_address, me); 186 hw_unit_size_to_attach_size (hw_parent (me), ®.size, &attach_size, me); 187 188 if (attach_size != BFIN_COREMMR_TRACE_SIZE) 189 hw_abort (me, "\"reg\" size must be %#x", BFIN_COREMMR_TRACE_SIZE); 190 191 hw_attach_address (hw_parent (me), 192 0, attach_space, attach_address, attach_size, me); 193 194 trace->base = attach_address; 195 } 196 197 static void 198 bfin_trace_finish (struct hw *me) 199 { 200 struct bfin_trace *trace; 201 202 trace = HW_ZALLOC (me, struct bfin_trace); 203 204 set_hw_data (me, trace); 205 set_hw_io_read_buffer (me, bfin_trace_io_read_buffer); 206 set_hw_io_write_buffer (me, bfin_trace_io_write_buffer); 207 208 attach_bfin_trace_regs (me, trace); 209 } 210 211 const struct hw_descriptor dv_bfin_trace_descriptor[] = 212 { 213 {"bfin_trace", bfin_trace_finish,}, 214 {NULL, NULL}, 215 }; 216 217 #define TRACE_STATE(cpu) DV_STATE_CACHED (cpu, trace) 218 219 /* This is not re-entrant, but neither is the cpu state, so this shouldn't 220 be a big deal ... */ 221 void bfin_trace_queue (SIM_CPU *cpu, bu32 src_pc, bu32 dst_pc, int hwloop) 222 { 223 struct bfin_trace *trace = TRACE_STATE (cpu); 224 struct bfin_trace_entry *e; 225 int len, ivg; 226 227 /* Only queue if powered. */ 228 if (!(trace->tbufctl & TBUFPWR)) 229 return; 230 231 /* Only queue if enabled. */ 232 if (!(trace->tbufctl & TBUFEN)) 233 return; 234 235 /* Ignore hardware loops. 236 XXX: This is what the hardware does, but an option to ignore 237 could be useful for debugging ... */ 238 if (hwloop >= 0) 239 return; 240 241 /* Only queue if at right level. */ 242 ivg = cec_get_ivg (cpu); 243 if (ivg == IVG_RST) 244 /* XXX: This is what the hardware does, but an option to ignore 245 could be useful for debugging ... */ 246 return; 247 if (ivg <= IVG_EVX && (trace->tbufctl & TBUFOVF)) 248 /* XXX: This is what the hardware does, but an option to ignore 249 could be useful for debugging ... just don't throw an 250 exception when full and in EVT{0..3}. */ 251 return; 252 253 /* Are we full ? */ 254 len = TBUF_LEN (trace); 255 if (len == SIM_BFIN_TRACE_LEN) 256 { 257 if (trace->tbufctl & TBUFOVF) 258 { 259 cec_exception (cpu, VEC_OVFLOW); 260 return; 261 } 262 263 /* Overwrite next entry. */ 264 ++trace->bottom; 265 } 266 267 /* One level compression. */ 268 if (len >= 1 && (trace->tbufctl & TBUFCMPLP)) 269 { 270 e = TBUF_LAST (trace); 271 if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) 272 { 273 /* Hardware sets LSB when level is compressed. */ 274 e->dst |= 1; 275 return; 276 } 277 } 278 279 /* Two level compression. */ 280 if (len >= 2 && (trace->tbufctl & TBUFCMPLP_DOUBLE)) 281 { 282 e = TBUF_LAST_LAST (trace); 283 if (src_pc == (e->src & ~1) && dst_pc == (e->dst & ~1)) 284 { 285 /* Hardware sets LSB when level is compressed. */ 286 e->src |= 1; 287 return; 288 } 289 } 290 291 e = TBUF_TOP (trace); 292 e->dst = dst_pc; 293 e->src = src_pc; 294 ++trace->top; 295 } 296