1 /* Blackfin Core Event Controller (CEC) model. 2 3 Copyright (C) 2010-2024 Free Software Foundation, Inc. 4 Contributed by Analog Devices, Inc. 5 6 This file is part of simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef DV_BFIN_CEC_H 22 #define DV_BFIN_CEC_H 23 24 #include "sim-main.h" 25 26 /* 0xFFE02100 ... 0xFFE02110 */ 27 #define BFIN_COREMMR_EVT_OVERRIDE (BFIN_COREMMR_CEC_BASE + (4 * 0)) 28 #define BFIN_COREMMR_IMASK (BFIN_COREMMR_CEC_BASE + (4 * 1)) 29 #define BFIN_COREMMR_IPEND (BFIN_COREMMR_CEC_BASE + (4 * 2)) 30 #define BFIN_COREMMR_ILAT (BFIN_COREMMR_CEC_BASE + (4 * 3)) 31 #define BFIN_COREMMR_IPRIO (BFIN_COREMMR_CEC_BASE + (4 * 4)) 32 33 #define IVG_EMU 0 34 #define IVG_RST 1 35 #define IVG_NMI 2 36 #define IVG_EVX 3 37 #define IVG_IRPTEN 4 /* Global is Reserved */ 38 #define IVG_IVHW 5 39 #define IVG_IVTMR 6 40 #define IVG7 7 41 #define IVG8 8 42 #define IVG9 9 43 #define IVG10 10 44 #define IVG11 11 45 #define IVG12 12 46 #define IVG13 13 47 #define IVG14 14 48 #define IVG15 15 49 #define IVG_USER 16 /* Not real; for internal use */ 50 51 #define IVG_EMU_B (1 << IVG_EMU) 52 #define IVG_RST_B (1 << IVG_RST) 53 #define IVG_NMI_B (1 << IVG_NMI) 54 #define IVG_EVX_B (1 << IVG_EVX) 55 #define IVG_IRPTEN_B (1 << IVG_IRPTEN) 56 #define IVG_IVHW_B (1 << IVG_IVHW) 57 #define IVG_IVTMR_B (1 << IVG_IVTMR) 58 #define IVG7_B (1 << IVG7) 59 #define IVG8_B (1 << IVG8) 60 #define IVG9_B (1 << IVG9) 61 #define IVG10_B (1 << IVG10) 62 #define IVG11_B (1 << IVG11) 63 #define IVG12_B (1 << IVG12) 64 #define IVG13_B (1 << IVG13) 65 #define IVG14_B (1 << IVG14) 66 #define IVG15_B (1 << IVG15) 67 #define IVG_UNMASKABLE_B \ 68 (IVG_EMU_B | IVG_RST_B | IVG_NMI_B | IVG_EVX_B | IVG_IRPTEN_B) 69 #define IVG_MASKABLE_B \ 70 (IVG_IVHW_B | IVG_IVTMR_B | IVG7_B | IVG8_B | IVG9_B | \ 71 IVG10_B | IVG11_B | IVG12_B | IVG13_B | IVG14_B | IVG15_B) 72 73 #define VEC_SYS 0x0 74 #define VEC_EXCPT01 0x1 75 #define VEC_EXCPT02 0x2 76 #define VEC_EXCPT03 0x3 77 #define VEC_EXCPT04 0x4 78 #define VEC_EXCPT05 0x5 79 #define VEC_EXCPT06 0x6 80 #define VEC_EXCPT07 0x7 81 #define VEC_EXCPT08 0x8 82 #define VEC_EXCPT09 0x9 83 #define VEC_EXCPT10 0xa 84 #define VEC_EXCPT11 0xb 85 #define VEC_EXCPT12 0xc 86 #define VEC_EXCPT13 0xd 87 #define VEC_EXCPT14 0xe 88 #define VEC_EXCPT15 0xf 89 #define VEC_STEP 0x10 /* single step */ 90 #define VEC_OVFLOW 0x11 /* trace buffer overflow */ 91 #define VEC_UNDEF_I 0x21 /* undefined instruction */ 92 #define VEC_ILGAL_I 0x22 /* illegal instruction combo (multi-issue) */ 93 #define VEC_CPLB_VL 0x23 /* DCPLB protection violation */ 94 #define VEC_MISALI_D 0x24 /* unaligned data access */ 95 #define VEC_UNCOV 0x25 /* unrecoverable event (double fault) */ 96 #define VEC_CPLB_M 0x26 /* DCPLB miss */ 97 #define VEC_CPLB_MHIT 0x27 /* multiple DCPLB hit */ 98 #define VEC_WATCH 0x28 /* watchpoint match */ 99 #define VEC_ISTRU_VL 0x29 /* ADSP-BF535 only */ 100 #define VEC_MISALI_I 0x2a /* unaligned instruction access */ 101 #define VEC_CPLB_I_VL 0x2b /* ICPLB protection violation */ 102 #define VEC_CPLB_I_M 0x2c /* ICPLB miss */ 103 #define VEC_CPLB_I_MHIT 0x2d /* multiple ICPLB hit */ 104 #define VEC_ILL_RES 0x2e /* illegal supervisor resource */ 105 /* 106 * The hardware reserves 63+ for future use - we use it to tell our 107 * normal exception handling code we have a hardware error 108 */ 109 #define VEC_HWERR 63 110 #define VEC_SIM_BASE 64 111 #define VEC_SIM_HLT (VEC_SIM_BASE + 1) 112 #define VEC_SIM_ABORT (VEC_SIM_BASE + 2) 113 #define VEC_SIM_TRAP (VEC_SIM_BASE + 3) 114 #define VEC_SIM_DBGA (VEC_SIM_BASE + 4) 115 extern void cec_exception (SIM_CPU *, int vec_excp); 116 117 #define HWERR_SYSTEM_MMR 0x02 118 #define HWERR_EXTERN_ADDR 0x03 119 #define HWERR_PERF_FLOW 0x12 120 #define HWERR_RAISE_5 0x18 121 extern void cec_hwerr (SIM_CPU *, int hwerr); 122 extern void cec_latch (SIM_CPU *, int ivg); 123 extern void cec_return (SIM_CPU *, int ivg); 124 125 extern int cec_get_ivg (SIM_CPU *); 126 extern bool cec_is_supervisor_mode (SIM_CPU *); 127 extern bool cec_is_user_mode (SIM_CPU *); 128 extern void cec_require_supervisor (SIM_CPU *); 129 130 extern bu32 cec_cli (SIM_CPU *); 131 extern void cec_sti (SIM_CPU *, bu32 ints); 132 133 extern void cec_push_reti (SIM_CPU *); 134 extern void cec_pop_reti (SIM_CPU *); 135 136 #endif 137