1# Makefile.in generated by automake 1.15.1 from Makefile.am. 2# @configure_input@ 3 4# Copyright (C) 1994-2017 Free Software Foundation, Inc. 5 6# This Makefile.in is free software; the Free Software Foundation 7# gives unlimited permission to copy and/or distribute it, 8# with or without modifications, as long as this notice is preserved. 9 10# This program is distributed in the hope that it will be useful, 11# but WITHOUT ANY WARRANTY, to the extent permitted by law; without 12# even the implied warranty of MERCHANTABILITY or FITNESS FOR A 13# PARTICULAR PURPOSE. 14 15@SET_MAKE@ 16 17# Copyright (C) 1993-2024 Free Software Foundation, Inc. 18# 19# This program is free software; you can redistribute it and/or modify 20# it under the terms of the GNU General Public License as published by 21# the Free Software Foundation; either version 3 of the License, or 22# (at your option) any later version. 23# 24# This program is distributed in the hope that it will be useful, 25# but WITHOUT ANY WARRANTY; without even the implied warranty of 26# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 27# GNU General Public License for more details. 28# 29# You should have received a copy of the GNU General Public License 30# along with this program. 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@AS_FOR_TARGET_LM32@ 1591AS_FOR_TARGET_M32C = @AS_FOR_TARGET_M32C@ 1592AS_FOR_TARGET_M32R = @AS_FOR_TARGET_M32R@ 1593AS_FOR_TARGET_M68HC11 = @AS_FOR_TARGET_M68HC11@ 1594AS_FOR_TARGET_MCORE = @AS_FOR_TARGET_MCORE@ 1595AS_FOR_TARGET_MICROBLAZE = @AS_FOR_TARGET_MICROBLAZE@ 1596AS_FOR_TARGET_MIPS = @AS_FOR_TARGET_MIPS@ 1597AS_FOR_TARGET_MN10300 = @AS_FOR_TARGET_MN10300@ 1598AS_FOR_TARGET_MOXIE = @AS_FOR_TARGET_MOXIE@ 1599AS_FOR_TARGET_MSP430 = @AS_FOR_TARGET_MSP430@ 1600AS_FOR_TARGET_OR1K = @AS_FOR_TARGET_OR1K@ 1601AS_FOR_TARGET_PPC = @AS_FOR_TARGET_PPC@ 1602AS_FOR_TARGET_PRU = @AS_FOR_TARGET_PRU@ 1603AS_FOR_TARGET_RISCV = @AS_FOR_TARGET_RISCV@ 1604AS_FOR_TARGET_RL78 = @AS_FOR_TARGET_RL78@ 1605AS_FOR_TARGET_RX = @AS_FOR_TARGET_RX@ 1606AS_FOR_TARGET_SH = @AS_FOR_TARGET_SH@ 1607AS_FOR_TARGET_V850 = @AS_FOR_TARGET_V850@ 1608AUTOCONF = @AUTOCONF@ 1609AUTOHEADER = @AUTOHEADER@ 1610AUTOMAKE = @AUTOMAKE@ 1611AWK = @AWK@ 1612BUILD_WARN_CFLAGS = @BUILD_WARN_CFLAGS@ 1613BUILD_WERROR_CFLAGS = @BUILD_WERROR_CFLAGS@ 1614CC = @CC@ 1615CCDEPMODE = @CCDEPMODE@ 1616CC_FOR_BUILD = @CC_FOR_BUILD@ 1617CC_FOR_TARGET = @CC_FOR_TARGET@ 1618CC_FOR_TARGET_AARCH64 = @CC_FOR_TARGET_AARCH64@ 1619CC_FOR_TARGET_ARM = @CC_FOR_TARGET_ARM@ 1620CC_FOR_TARGET_AVR = @CC_FOR_TARGET_AVR@ 1621CC_FOR_TARGET_BFIN = @CC_FOR_TARGET_BFIN@ 1622CC_FOR_TARGET_BPF = @CC_FOR_TARGET_BPF@ 1623CC_FOR_TARGET_CR16 = @CC_FOR_TARGET_CR16@ 1624CC_FOR_TARGET_CRIS = @CC_FOR_TARGET_CRIS@ 1625CC_FOR_TARGET_D10V = @CC_FOR_TARGET_D10V@ 1626CC_FOR_TARGET_ERC32 = @CC_FOR_TARGET_ERC32@ 1627CC_FOR_TARGET_EXAMPLE_SYNACOR = @CC_FOR_TARGET_EXAMPLE_SYNACOR@ 1628CC_FOR_TARGET_FRV = @CC_FOR_TARGET_FRV@ 1629CC_FOR_TARGET_FT32 = @CC_FOR_TARGET_FT32@ 1630CC_FOR_TARGET_H8300 = @CC_FOR_TARGET_H8300@ 1631CC_FOR_TARGET_IQ2000 = @CC_FOR_TARGET_IQ2000@ 1632CC_FOR_TARGET_LM32 = @CC_FOR_TARGET_LM32@ 1633CC_FOR_TARGET_M32C = @CC_FOR_TARGET_M32C@ 1634CC_FOR_TARGET_M32R = @CC_FOR_TARGET_M32R@ 1635CC_FOR_TARGET_M68HC11 = @CC_FOR_TARGET_M68HC11@ 1636CC_FOR_TARGET_MCORE = @CC_FOR_TARGET_MCORE@ 1637CC_FOR_TARGET_MICROBLAZE = @CC_FOR_TARGET_MICROBLAZE@ 1638CC_FOR_TARGET_MIPS = @CC_FOR_TARGET_MIPS@ 1639CC_FOR_TARGET_MN10300 = @CC_FOR_TARGET_MN10300@ 1640CC_FOR_TARGET_MOXIE = @CC_FOR_TARGET_MOXIE@ 1641CC_FOR_TARGET_MSP430 = @CC_FOR_TARGET_MSP430@ 1642CC_FOR_TARGET_OR1K = @CC_FOR_TARGET_OR1K@ 1643CC_FOR_TARGET_PPC = @CC_FOR_TARGET_PPC@ 1644CC_FOR_TARGET_PRU = @CC_FOR_TARGET_PRU@ 1645CC_FOR_TARGET_RISCV = @CC_FOR_TARGET_RISCV@ 1646CC_FOR_TARGET_RL78 = @CC_FOR_TARGET_RL78@ 1647CC_FOR_TARGET_RX = @CC_FOR_TARGET_RX@ 1648CC_FOR_TARGET_SH = @CC_FOR_TARGET_SH@ 1649CC_FOR_TARGET_V850 = @CC_FOR_TARGET_V850@ 1650CFLAGS = @CFLAGS@ 1651CFLAGS_FOR_BUILD = @CFLAGS_FOR_BUILD@ 1652CGEN_MAINT = @CGEN_MAINT@ 1653CPP = @CPP@ 1654CPPFLAGS = @CPPFLAGS@ 1655CPPFLAGS_FOR_BUILD = @CPPFLAGS_FOR_BUILD@ 1656CYGPATH_W = @CYGPATH_W@ 1657C_DIALECT = @C_DIALECT@ 1658DEFS = @DEFS@ 1659DEPDIR = @DEPDIR@ 1660DSYMUTIL = @DSYMUTIL@ 1661DTC = @DTC@ 1662DUMPBIN = @DUMPBIN@ 1663ECHO_C = @ECHO_C@ 1664ECHO_N = @ECHO_N@ 1665ECHO_T = @ECHO_T@ 1666EGREP = @EGREP@ 1667EXEEXT = @EXEEXT@ 1668FGREP = @FGREP@ 1669GREP = @GREP@ 1670IGEN_FLAGS_SMP = @IGEN_FLAGS_SMP@ 1671INSTALL = @INSTALL@ 1672INSTALL_DATA = @INSTALL_DATA@ 1673INSTALL_PROGRAM = @INSTALL_PROGRAM@ 1674INSTALL_SCRIPT = @INSTALL_SCRIPT@ 1675INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ 1676LD = @LD@ 1677LDFLAGS = @LDFLAGS@ 1678LDFLAGS_FOR_BUILD = @LDFLAGS_FOR_BUILD@ 1679LD_FOR_TARGET = @LD_FOR_TARGET@ 1680LD_FOR_TARGET_AARCH64 = @LD_FOR_TARGET_AARCH64@ 1681LD_FOR_TARGET_ARM = @LD_FOR_TARGET_ARM@ 1682LD_FOR_TARGET_AVR = @LD_FOR_TARGET_AVR@ 1683LD_FOR_TARGET_BFIN = @LD_FOR_TARGET_BFIN@ 1684LD_FOR_TARGET_BPF = @LD_FOR_TARGET_BPF@ 1685LD_FOR_TARGET_CR16 = @LD_FOR_TARGET_CR16@ 1686LD_FOR_TARGET_CRIS = @LD_FOR_TARGET_CRIS@ 1687LD_FOR_TARGET_D10V = @LD_FOR_TARGET_D10V@ 1688LD_FOR_TARGET_ERC32 = @LD_FOR_TARGET_ERC32@ 1689LD_FOR_TARGET_EXAMPLE_SYNACOR = @LD_FOR_TARGET_EXAMPLE_SYNACOR@ 1690LD_FOR_TARGET_FRV = @LD_FOR_TARGET_FRV@ 1691LD_FOR_TARGET_FT32 = @LD_FOR_TARGET_FT32@ 1692LD_FOR_TARGET_H8300 = @LD_FOR_TARGET_H8300@ 1693LD_FOR_TARGET_IQ2000 = @LD_FOR_TARGET_IQ2000@ 1694LD_FOR_TARGET_LM32 = @LD_FOR_TARGET_LM32@ 1695LD_FOR_TARGET_M32C = @LD_FOR_TARGET_M32C@ 1696LD_FOR_TARGET_M32R = @LD_FOR_TARGET_M32R@ 1697LD_FOR_TARGET_M68HC11 = @LD_FOR_TARGET_M68HC11@ 1698LD_FOR_TARGET_MCORE = @LD_FOR_TARGET_MCORE@ 1699LD_FOR_TARGET_MICROBLAZE = @LD_FOR_TARGET_MICROBLAZE@ 1700LD_FOR_TARGET_MIPS = @LD_FOR_TARGET_MIPS@ 1701LD_FOR_TARGET_MN10300 = @LD_FOR_TARGET_MN10300@ 1702LD_FOR_TARGET_MOXIE = @LD_FOR_TARGET_MOXIE@ 1703LD_FOR_TARGET_MSP430 = @LD_FOR_TARGET_MSP430@ 1704LD_FOR_TARGET_OR1K = @LD_FOR_TARGET_OR1K@ 1705LD_FOR_TARGET_PPC = @LD_FOR_TARGET_PPC@ 1706LD_FOR_TARGET_PRU = @LD_FOR_TARGET_PRU@ 1707LD_FOR_TARGET_RISCV = @LD_FOR_TARGET_RISCV@ 1708LD_FOR_TARGET_RL78 = @LD_FOR_TARGET_RL78@ 1709LD_FOR_TARGET_RX = @LD_FOR_TARGET_RX@ 1710LD_FOR_TARGET_SH = @LD_FOR_TARGET_SH@ 1711LD_FOR_TARGET_V850 = @LD_FOR_TARGET_V850@ 1712LIBOBJS = @LIBOBJS@ 1713LIBS = @LIBS@ 1714LIBTOOL = @LIBTOOL@ 1715LIPO = @LIPO@ 1716LN_S = @LN_S@ 1717LTLIBOBJS = @LTLIBOBJS@ 1718MAINT = @MAINT@ 1719MAKEINFO = @MAKEINFO@ 1720MKDIR_P = @MKDIR_P@ 1721NM = @NM@ 1722NMEDIT = @NMEDIT@ 1723OBJDUMP = @OBJDUMP@ 1724OBJEXT = @OBJEXT@ 1725OTOOL = @OTOOL@ 1726OTOOL64 = @OTOOL64@ 1727PACKAGE = @PACKAGE@ 1728PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ 1729PACKAGE_NAME = @PACKAGE_NAME@ 1730PACKAGE_STRING = @PACKAGE_STRING@ 1731PACKAGE_TARNAME = @PACKAGE_TARNAME@ 1732PACKAGE_URL = @PACKAGE_URL@ 1733PACKAGE_VERSION = @PACKAGE_VERSION@ 1734PATH_SEPARATOR = @PATH_SEPARATOR@ 1735PKGVERSION = @PKGVERSION@ 1736PKG_CONFIG = @PKG_CONFIG@ 1737PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@ 1738PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ 1739RANLIB = @RANLIB@ 1740RANLIB_FOR_BUILD = @RANLIB_FOR_BUILD@ 1741READLINE_CFLAGS = @READLINE_CFLAGS@ 1742READLINE_LIB = @READLINE_LIB@ 1743REPORT_BUGS_TEXI = @REPORT_BUGS_TEXI@ 1744REPORT_BUGS_TO = @REPORT_BUGS_TO@ 1745SDL_CFLAGS = @SDL_CFLAGS@ 1746SDL_LIBS = @SDL_LIBS@ 1747SED = @SED@ 1748SET_MAKE = @SET_MAKE@ 1749SHELL = @SHELL@ 1750SIM_CFLAG_WNO_SHADOW_LOCAL = @SIM_CFLAG_WNO_SHADOW_LOCAL@ 1751SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE = @SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE@ 1752SIM_ENABLED_ARCHES = @SIM_ENABLED_ARCHES@ 1753SIM_FRV_TRAPDUMP_FLAGS = @SIM_FRV_TRAPDUMP_FLAGS@ 1754SIM_HW_CFLAGS = @SIM_HW_CFLAGS@ 1755SIM_HW_SOCKSER = @SIM_HW_SOCKSER@ 1756SIM_INLINE = @SIM_INLINE@ 1757SIM_MIPS_BITSIZE = @SIM_MIPS_BITSIZE@ 1758SIM_MIPS_FPU_BITSIZE = @SIM_MIPS_FPU_BITSIZE@ 1759SIM_MIPS_GEN = @SIM_MIPS_GEN@ 1760SIM_MIPS_IGEN_ITABLE_FLAGS = @SIM_MIPS_IGEN_ITABLE_FLAGS@ 1761SIM_MIPS_M16_FLAGS = @SIM_MIPS_M16_FLAGS@ 1762SIM_MIPS_MULTI_IGEN_CONFIGS = @SIM_MIPS_MULTI_IGEN_CONFIGS@ 1763SIM_MIPS_MULTI_OBJ = @SIM_MIPS_MULTI_OBJ@ 1764SIM_MIPS_MULTI_SRC = @SIM_MIPS_MULTI_SRC@ 1765SIM_MIPS_SINGLE_FLAGS = @SIM_MIPS_SINGLE_FLAGS@ 1766SIM_MIPS_SUBTARGET = @SIM_MIPS_SUBTARGET@ 1767SIM_PRIMARY_TARGET = @SIM_PRIMARY_TARGET@ 1768SIM_RISCV_BITSIZE = @SIM_RISCV_BITSIZE@ 1769SIM_RX_CYCLE_ACCURATE_FLAGS = @SIM_RX_CYCLE_ACCURATE_FLAGS@ 1770SIM_TOOLCHAIN_VARS = @SIM_TOOLCHAIN_VARS@ 1771STRIP = @STRIP@ 1772TERMCAP_LIB = @TERMCAP_LIB@ 1773VERSION = @VERSION@ 1774WARN_CFLAGS = @WARN_CFLAGS@ 1775WERROR_CFLAGS = @WERROR_CFLAGS@ 1776abs_builddir = @abs_builddir@ 1777abs_srcdir = @abs_srcdir@ 1778abs_top_builddir = @abs_top_builddir@ 1779abs_top_srcdir = @abs_top_srcdir@ 1780ac_ct_CC = @ac_ct_CC@ 1781ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ 1782am__include = @am__include@ 1783am__leading_dot = @am__leading_dot@ 1784am__quote = @am__quote@ 1785am__tar = @am__tar@ 1786am__untar = @am__untar@ 1787bindir = @bindir@ 1788build = @build@ 1789build_alias = @build_alias@ 1790build_cpu = @build_cpu@ 1791build_os = @build_os@ 1792build_vendor = @build_vendor@ 1793builddir = @builddir@ 1794cgen = @cgen@ 1795cgendir = @cgendir@ 1796datadir = @datadir@ 1797datarootdir = @datarootdir@ 1798docdir = @docdir@ 1799dvidir = @dvidir@ 1800exec_prefix = @exec_prefix@ 1801host = @host@ 1802host_alias = @host_alias@ 1803host_cpu = @host_cpu@ 1804host_os = @host_os@ 1805host_vendor = @host_vendor@ 1806htmldir = @htmldir@ 1807includedir = @includedir@ 1808infodir = @infodir@ 1809install_sh = @install_sh@ 1810libdir = @libdir@ 1811libexecdir = @libexecdir@ 1812localedir = @localedir@ 1813localstatedir = @localstatedir@ 1814mandir = @mandir@ 1815mkdir_p = @mkdir_p@ 1816oldincludedir = @oldincludedir@ 1817pdfdir = @pdfdir@ 1818prefix = @prefix@ 1819program_transform_name = @program_transform_name@ 1820psdir = @psdir@ 1821sbindir = @sbindir@ 1822sharedstatedir = @sharedstatedir@ 1823sim_ppc_bitsize = @sim_ppc_bitsize@ 1824sim_ppc_decode_mechanism = @sim_ppc_decode_mechanism@ 1825sim_ppc_default_model = @sim_ppc_default_model@ 1826sim_ppc_dup = @sim_ppc_dup@ 1827sim_ppc_filter = @sim_ppc_filter@ 1828sim_ppc_float = @sim_ppc_float@ 1829sim_ppc_hw_obj = @sim_ppc_hw_obj@ 1830sim_ppc_hw_src = @sim_ppc_hw_src@ 1831sim_ppc_icache = @sim_ppc_icache@ 1832sim_ppc_igen_smp = @sim_ppc_igen_smp@ 1833sim_ppc_jump = @sim_ppc_jump@ 1834sim_ppc_line_nr = @sim_ppc_line_nr@ 1835sim_ppc_model = @sim_ppc_model@ 1836sim_ppc_model_issue = @sim_ppc_model_issue@ 1837sim_ppc_monitor = @sim_ppc_monitor@ 1838sim_ppc_opcode = @sim_ppc_opcode@ 1839sim_ppc_smp = @sim_ppc_smp@ 1840sim_ppc_switch = @sim_ppc_switch@ 1841sim_ppc_timebase = @sim_ppc_timebase@ 1842sim_ppc_xor_endian = @sim_ppc_xor_endian@ 1843srcdir = @srcdir@ 1844sysconfdir = @sysconfdir@ 1845target = @target@ 1846target_alias = @target_alias@ 1847target_cpu = @target_cpu@ 1848target_os = @target_os@ 1849target_vendor = @target_vendor@ 1850top_build_prefix = @top_build_prefix@ 1851top_builddir = @top_builddir@ 1852top_srcdir = @top_srcdir@ 1853AUTOMAKE_OPTIONS = dejagnu foreign no-dist subdir-objects 1854ACLOCAL_AMFLAGS = -Im4 -I.. -I../config 1855GNULIB_PARENT_DIR = .. 1856srccom = $(srcdir)/common 1857srcroot = $(srcdir)/.. 1858pkginclude_HEADERS = $(am__append_1) 1859EXTRA_LIBRARIES = igen/libigen.a $(am__append_101) 1860noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \ 1861 $(am__append_7) $(am__append_9) $(am__append_11) \ 1862 $(am__append_13) $(am__append_19) $(am__append_25) \ 1863 $(am__append_31) $(am__append_35) $(am__append_37) \ 1864 $(am__append_42) $(am__append_44) $(am__append_46) \ 1865 $(am__append_51) $(am__append_56) $(am__append_60) \ 1866 $(am__append_65) $(am__append_69) $(am__append_71) \ 1867 $(am__append_76) $(am__append_84) $(am__append_88) \ 1868 $(am__append_90) $(am__append_92) $(am__append_97) \ 1869 $(am__append_103) $(am__append_105) $(am__append_107) \ 1870 $(am__append_109) $(am__append_111) $(am__append_116) 1871BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \ 1872 $(am__append_39) $(am__append_48) $(am__append_53) \ 1873 $(am__append_62) $(am__append_78) $(am__append_86) \ 1874 $(am__append_94) $(am__append_99) $(am__append_113) \ 1875 $(am__append_118) 1876CLEANFILES = common/version.c common/version.c-stamp \ 1877 testsuite/common/bits-gen testsuite/common/bits32m0.c \ 1878 testsuite/common/bits32m31.c testsuite/common/bits64m0.c \ 1879 testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \ 1880 $(am__append_29) $(am__append_40) $(am__append_49) \ 1881 $(am__append_54) $(am__append_63) $(am__append_95) 1882DISTCLEANFILES = $(am__append_83) 1883MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \ 1884 $(SIM_ENABLED_ARCHES:%=%/hw-config.h) \ 1885 $(SIM_ENABLED_ARCHES:%=%/stamp-hw) \ 1886 $(SIM_ENABLED_ARCHES:%=%/modules.c) \ 1887 $(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \ 1888 igen/libigen.a site-sim-config.exp testrun.log testrun.sum \ 1889 $(am__append_18) $(am__append_24) $(am__append_30) \ 1890 $(am__append_41) $(am__append_50) $(am__append_55) \ 1891 $(am__append_59) $(am__append_64) $(am__append_68) \ 1892 $(am__append_82) $(am__append_87) $(am__append_96) \ 1893 $(am__append_100) $(am__append_115) $(am__append_119) 1894CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh 1895AM_CFLAGS = \ 1896 $(WERROR_CFLAGS) \ 1897 $(WARN_CFLAGS) \ 1898 $(AM_CFLAGS_$(subst -,_,$(@D))) \ 1899 $(AM_CFLAGS_$(subst -,_,$(@D)_$(@F))) 1900 1901AM_CPPFLAGS = $(INCGNU) -I$(srcroot) -I$(srcroot)/include -I../bfd \ 1902 -I.. -I$(@D) -I$(srcdir)/$(@D) $(SIM_HW_CFLAGS) $(SIM_INLINE) \ 1903 $(AM_CPPFLAGS_$(subst -,_,$(@D))) $(AM_CPPFLAGS_$(subst \ 1904 -,_,$(@D)_$(@F))) -I$(srcdir)/common -DSIM_TOPDIR_BUILD 1905AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \ 1906 $(SIM_INLINE) -I$(srcdir)/common 1907COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS) 1908LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@ 1909SIM_INSTALL_DATA_LOCAL_DEPS = 1910SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33) 1911SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34) 1912SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=) 1913SIM_COMPILE = \ 1914 $(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \ 1915 $(am__mv) $(SIM_DEPBASE).Tpo $(SIM_DEPBASE).Po 1916 1917AM_CPPFLAGS_common = -DSIM_COMMON_BUILD 1918common_libcommon_a_SOURCES = \ 1919 common/callback.c \ 1920 common/portability.c \ 1921 common/sim-load.c \ 1922 common/sim-signal.c \ 1923 common/syscall.c \ 1924 common/target-newlib-errno.c \ 1925 common/target-newlib-open.c \ 1926 common/target-newlib-signal.c \ 1927 common/target-newlib-syscall.c \ 1928 common/version.c 1929 1930SIM_COMMON_HW_OBJS = \ 1931 hw-alloc.o \ 1932 hw-base.o \ 1933 hw-device.o \ 1934 hw-events.o \ 1935 hw-handles.o \ 1936 hw-instances.o \ 1937 hw-ports.o \ 1938 hw-properties.o \ 1939 hw-tree.o \ 1940 sim-hw.o 1941 1942SIM_NEW_COMMON_OBJS = sim-arange.o sim-bits.o sim-close.o \ 1943 sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \ 1944 sim-engine.o sim-events.o sim-fpu.o sim-hload.o sim-hrw.o \ 1945 sim-io.o sim-info.o sim-memopt.o sim-model.o sim-module.o \ 1946 sim-options.o sim-profile.o sim-reason.o sim-reg.o sim-stop.o \ 1947 sim-syscall.o sim-trace.o sim-utils.o sim-watch.o \ 1948 $(am__append_2) 1949SIM_HW_DEVICES = cfi core pal glue 1950am_arch_d = $(subst -,_,$(@D)) 1951GEN_MODULES_C_SRCS = \ 1952 $(wildcard \ 1953 $(patsubst %,$(srcdir)/%,$($(am_arch_d)_libsim_a_SOURCES)) \ 1954 $(patsubst %.o,$(srcdir)/%.c,$($(am_arch_d)_libsim_a_OBJECTS) $($(am_arch_d)_libsim_a_LIBADD)) \ 1955 $(filter-out %.o,$(patsubst $(@D)/%.o,$(srcdir)/common/%.c,$($(am_arch_d)_libsim_a_LIBADD)))) 1956 1957LIBIBERTY_LIB = ../libiberty/libiberty.a 1958BFD_LIB = ../bfd/libbfd.la 1959OPCODES_LIB = ../opcodes/libopcodes.la 1960SIM_COMMON_LIBS = \ 1961 $(BFD_LIB) \ 1962 $(OPCODES_LIB) \ 1963 $(LIBIBERTY_LIB) \ 1964 $(LIBGNU) \ 1965 $(LIBGNU_EXTRA_LIBS) 1966 1967GUILE = guile 1968CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s" 1969CGENFLAGS = -v 1970CGEN_CPU_DIR = $(cgendir)/cpu 1971CPU_DIR = $(srcroot)/cpu 1972CGEN_ARCHFILE = $(CPU_DIR)/$(@D).cpu 1973CGEN_READ_SCM = $(cgendir)/sim.scm 1974CGEN_ARCH_SCM = $(cgendir)/sim-arch.scm 1975CGEN_CPU_SCM = $(cgendir)/sim-cpu.scm $(cgendir)/sim-model.scm 1976CGEN_DECODE_SCM = $(cgendir)/sim-decode.scm 1977CGEN_DESC_SCM = $(cgendir)/desc.scm $(cgendir)/desc-cpu.scm 1978CGEN_CPU_EXTR = /extr/ 1979CGEN_CPU_READ = /read/ 1980CGEN_CPU_WRITE = /write/ 1981CGEN_CPU_SEM = /sem/ 1982CGEN_CPU_SEMSW = /semsw/ 1983CGEN_WRAPPER = $(srccom)/cgen.sh 1984CGEN_GEN_ARCH = \ 1985 $(SHELL) $(CGEN_WRAPPER) arch $(srcdir)/$(@D) \ 1986 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 1987 $(@D) "$$FLAGS" ignored "$$isa" $$mach ignored \ 1988 $(CGEN_ARCHFILE) ignored 1989 1990CGEN_GEN_CPU = \ 1991 $(SHELL) $(CGEN_WRAPPER) cpu $(srcdir)/$(@D) \ 1992 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 1993 $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ 1994 $(CGEN_ARCHFILE) "$$EXTRAFILES" 1995 1996CGEN_GEN_DEFS = \ 1997 $(SHELL) $(CGEN_WRAPPER) defs $(srcdir)/$(@D) \ 1998 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 1999 $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ 2000 $(CGEN_ARCHFILE) ignored 2001 2002CGEN_GEN_DECODE = \ 2003 $(SHELL) $(CGEN_WRAPPER) decode $(srcdir)/$(@D) \ 2004 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 2005 $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ 2006 $(CGEN_ARCHFILE) "$$EXTRAFILES" 2007 2008CGEN_GEN_CPU_DECODE = \ 2009 $(SHELL) $(CGEN_WRAPPER) cpu-decode $(srcdir)/$(@D) \ 2010 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 2011 $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ 2012 $(CGEN_ARCHFILE) "$$EXTRAFILES" 2013 2014CGEN_GEN_CPU_DESC = \ 2015 $(SHELL) $(CGEN_WRAPPER) desc $(srcdir)/$(@D) \ 2016 $(CGEN) $(cgendir) "$(CGENFLAGS)" \ 2017 $(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \ 2018 $(CGEN_ARCHFILE) ignored $$opcfile 2019 2020CGEN_GEN_MLOOP = \ 2021 $(SHELL) $(srccom)/lineno.sh \ 2022 $(srccom)/genmloop.sh \ 2023 $@.lineno.sh \ 2024 -shell $(SHELL) -awk $(AWK) -lineno $(srccom)/lineno.sh \ 2025 -infile $< -outfile-prefix $(@D)/ 2026 2027 2028# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable 2029# leak detection while running it. 2030IGEN = igen/igen$(EXEEXT) 2031IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP) 2032igen_libigen_a_SOURCES = \ 2033 igen/table.c \ 2034 igen/lf.c \ 2035 igen/misc.c \ 2036 igen/filter_host.c \ 2037 igen/ld-decode.c \ 2038 igen/ld-cache.c \ 2039 igen/filter.c \ 2040 igen/ld-insn.c \ 2041 igen/gen-model.c \ 2042 igen/gen-itable.c \ 2043 igen/gen-icache.c \ 2044 igen/gen-semantics.c \ 2045 igen/gen-idecode.c \ 2046 igen/gen-support.c \ 2047 igen/gen-engine.c \ 2048 igen/gen.c 2049 2050igen_igen_SOURCES = igen/igen.c 2051igen_igen_LDADD = igen/libigen.a 2052igen_filter_SOURCES = 2053igen_filter_LDADD = igen/filter-main.o igen/libigen.a 2054igen_gen_SOURCES = 2055igen_gen_LDADD = igen/gen-main.o igen/libigen.a 2056igen_ld_cache_SOURCES = 2057igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a 2058igen_ld_decode_SOURCES = 2059igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a 2060igen_ld_insn_SOURCES = 2061igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a 2062igen_table_SOURCES = 2063igen_table_LDADD = igen/table-main.o igen/libigen.a 2064igen_IGEN_TOOLS = \ 2065 $(IGEN) \ 2066 igen/filter \ 2067 igen/gen \ 2068 igen/ld-cache \ 2069 igen/ld-decode \ 2070 igen/ld-insn \ 2071 igen/table 2072 2073EXTRA_DEJAGNU_SITE_CONFIG = site-sim-config.exp 2074 2075# Custom verbose test variables that automake doesn't provide (yet?). 2076AM_V_RUNTEST = $(AM_V_RUNTEST_@AM_V@) 2077AM_V_RUNTEST_ = $(AM_V_RUNTEST_@AM_DEFAULT_V@) 2078AM_V_RUNTEST_0 = @echo " RUNTEST $(RUNTESTFLAGS) $*"; 2079AM_V_RUNTEST_1 = 2080DO_RUNTEST = \ 2081 LC_ALL=C; export LC_ALL; \ 2082 EXPECT=${EXPECT} ; export EXPECT ; \ 2083 runtest=$(RUNTEST); \ 2084 $$runtest $(RUNTESTFLAGS) 2085 2086testsuite_common_CPPFLAGS = \ 2087 -I$(srcdir)/common \ 2088 -I$(srcroot)/include \ 2089 -I../bfd 2090 2091@SIM_ENABLE_ARCH_aarch64_TRUE@nodist_aarch64_libsim_a_SOURCES = \ 2092@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/modules.c 2093 2094@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_SOURCES = \ 2095@SIM_ENABLE_ARCH_aarch64_TRUE@ $(common_libcommon_a_SOURCES) 2096 2097@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_libsim_a_LIBADD = \ 2098@SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/%,$(SIM_NEW_COMMON_OBJS)) \ 2099@SIM_ENABLE_ARCH_aarch64_TRUE@ $(patsubst %,aarch64/dv-%.o,$(SIM_HW_DEVICES)) \ 2100@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/cpustate.o \ 2101@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/interp.o \ 2102@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/memory.o \ 2103@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/sim-resume.o \ 2104@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/simulator.o 2105 2106@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_SOURCES = 2107@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64_run_LDADD = \ 2108@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/nrun.o \ 2109@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/libsim.a \ 2110@SIM_ENABLE_ARCH_aarch64_TRUE@ $(SIM_COMMON_LIBS) 2111 2112@SIM_ENABLE_ARCH_arm_TRUE@AM_CPPFLAGS_arm = -DMODET 2113@SIM_ENABLE_ARCH_arm_TRUE@nodist_arm_libsim_a_SOURCES = \ 2114@SIM_ENABLE_ARCH_arm_TRUE@ arm/modules.c 2115 2116@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_SOURCES = \ 2117@SIM_ENABLE_ARCH_arm_TRUE@ $(common_libcommon_a_SOURCES) 2118 2119@SIM_ENABLE_ARCH_arm_TRUE@arm_libsim_a_LIBADD = \ 2120@SIM_ENABLE_ARCH_arm_TRUE@ arm/wrapper.o \ 2121@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/%,$(SIM_NEW_COMMON_OBJS)) \ 2122@SIM_ENABLE_ARCH_arm_TRUE@ $(patsubst %,arm/dv-%.o,$(SIM_HW_DEVICES)) \ 2123@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu.o \ 2124@SIM_ENABLE_ARCH_arm_TRUE@ arm/armemu32.o arm/arminit.o arm/armos.o arm/armsupp.o \ 2125@SIM_ENABLE_ARCH_arm_TRUE@ arm/armvirt.o arm/thumbemu.o \ 2126@SIM_ENABLE_ARCH_arm_TRUE@ arm/armcopro.o arm/maverick.o arm/iwmmxt.o 2127 2128@SIM_ENABLE_ARCH_arm_TRUE@arm_run_SOURCES = 2129@SIM_ENABLE_ARCH_arm_TRUE@arm_run_LDADD = \ 2130@SIM_ENABLE_ARCH_arm_TRUE@ arm/nrun.o \ 2131@SIM_ENABLE_ARCH_arm_TRUE@ arm/libsim.a \ 2132@SIM_ENABLE_ARCH_arm_TRUE@ $(SIM_COMMON_LIBS) 2133 2134@SIM_ENABLE_ARCH_arm_TRUE@armdocdir = $(docdir)/arm 2135@SIM_ENABLE_ARCH_arm_TRUE@armdoc_DATA = arm/README 2136@SIM_ENABLE_ARCH_avr_TRUE@nodist_avr_libsim_a_SOURCES = \ 2137@SIM_ENABLE_ARCH_avr_TRUE@ avr/modules.c 2138 2139@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_SOURCES = \ 2140@SIM_ENABLE_ARCH_avr_TRUE@ $(common_libcommon_a_SOURCES) 2141 2142@SIM_ENABLE_ARCH_avr_TRUE@avr_libsim_a_LIBADD = \ 2143@SIM_ENABLE_ARCH_avr_TRUE@ avr/interp.o \ 2144@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/%,$(SIM_NEW_COMMON_OBJS)) \ 2145@SIM_ENABLE_ARCH_avr_TRUE@ $(patsubst %,avr/dv-%.o,$(SIM_HW_DEVICES)) \ 2146@SIM_ENABLE_ARCH_avr_TRUE@ avr/sim-resume.o 2147 2148@SIM_ENABLE_ARCH_avr_TRUE@avr_run_SOURCES = 2149@SIM_ENABLE_ARCH_avr_TRUE@avr_run_LDADD = \ 2150@SIM_ENABLE_ARCH_avr_TRUE@ avr/nrun.o \ 2151@SIM_ENABLE_ARCH_avr_TRUE@ avr/libsim.a \ 2152@SIM_ENABLE_ARCH_avr_TRUE@ $(SIM_COMMON_LIBS) 2153 2154@SIM_ENABLE_ARCH_bfin_TRUE@AM_CPPFLAGS_bfin = $(SDL_CFLAGS) 2155@SIM_ENABLE_ARCH_bfin_TRUE@nodist_bfin_libsim_a_SOURCES = \ 2156@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/modules.c 2157 2158@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_SOURCES = \ 2159@SIM_ENABLE_ARCH_bfin_TRUE@ $(common_libcommon_a_SOURCES) 2160 2161@SIM_ENABLE_ARCH_bfin_TRUE@bfin_libsim_a_LIBADD = \ 2162@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/%,$(SIM_NEW_COMMON_OBJS)) \ 2163@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(SIM_HW_DEVICES)) \ 2164@SIM_ENABLE_ARCH_bfin_TRUE@ $(patsubst %,bfin/dv-%.o,$(bfin_SIM_EXTRA_HW_DEVICES)) \ 2165@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/bfin-sim.o \ 2166@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/devices.o \ 2167@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/gui.o \ 2168@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/interp.o \ 2169@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/machs.o \ 2170@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/sim-resume.o 2171 2172@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_SOURCES = 2173@SIM_ENABLE_ARCH_bfin_TRUE@bfin_run_LDADD = \ 2174@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/nrun.o \ 2175@SIM_ENABLE_ARCH_bfin_TRUE@ bfin/libsim.a \ 2176@SIM_ENABLE_ARCH_bfin_TRUE@ $(SIM_COMMON_LIBS) 2177 2178@SIM_ENABLE_ARCH_bfin_TRUE@bfin_SIM_EXTRA_HW_DEVICES = \ 2179@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_cec \ 2180@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ctimer \ 2181@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dma \ 2182@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_dmac \ 2183@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_amc \ 2184@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_ddrc \ 2185@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ebiu_sdc \ 2186@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_emac \ 2187@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_eppi \ 2188@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_evt \ 2189@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio \ 2190@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gpio2 \ 2191@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_gptimer \ 2192@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_jtag \ 2193@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_mmu \ 2194@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_nfc \ 2195@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_otp \ 2196@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pfmon \ 2197@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pint \ 2198@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_pll \ 2199@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_ppi \ 2200@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_rtc \ 2201@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_sic \ 2202@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_spi \ 2203@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_trace \ 2204@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_twi \ 2205@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart \ 2206@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_uart2 \ 2207@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wdog \ 2208@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \ 2209@SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy 2210 2211@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \ 2212@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c 2213 2214@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_SOURCES = \ 2215@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES) 2216 2217@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \ 2218@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \ 2219@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \ 2220@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \ 2221@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o 2222 2223@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES = 2224@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \ 2225@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/nrun.o \ 2226@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \ 2227@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS) 2228 2229@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \ 2230@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c 2231 2232@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_SOURCES = \ 2233@SIM_ENABLE_ARCH_cr16_TRUE@ $(common_libcommon_a_SOURCES) 2234 2235@SIM_ENABLE_ARCH_cr16_TRUE@cr16_libsim_a_LIBADD = \ 2236@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/%,$(SIM_NEW_COMMON_OBJS)) \ 2237@SIM_ENABLE_ARCH_cr16_TRUE@ $(patsubst %,cr16/dv-%.o,$(SIM_HW_DEVICES)) \ 2238@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/interp.o \ 2239@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/sim-resume.o \ 2240@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/simops.o \ 2241@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.o 2242 2243@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_SOURCES = 2244@SIM_ENABLE_ARCH_cr16_TRUE@cr16_run_LDADD = \ 2245@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/nrun.o \ 2246@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/libsim.a \ 2247@SIM_ENABLE_ARCH_cr16_TRUE@ $(SIM_COMMON_LIBS) 2248 2249@SIM_ENABLE_ARCH_cr16_TRUE@cr16_BUILD_OUTPUTS = \ 2250@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/gencode$(EXEEXT) \ 2251@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/table.c 2252 2253@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c 2254@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o 2255@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) \ 2256@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_CFLAG_WNO_SHADOW_LOCAL) 2257@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) 2258@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \ 2259@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.c 2260 2261@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_SOURCES = \ 2262@SIM_ENABLE_ARCH_cris_TRUE@ $(common_libcommon_a_SOURCES) 2263 2264@SIM_ENABLE_ARCH_cris_TRUE@cris_libsim_a_LIBADD = \ 2265@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/%,$(SIM_NEW_COMMON_OBJS)) \ 2266@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(SIM_HW_DEVICES)) \ 2267@SIM_ENABLE_ARCH_cris_TRUE@ $(patsubst %,cris/dv-%.o,$(cris_SIM_EXTRA_HW_DEVICES)) \ 2268@SIM_ENABLE_ARCH_cris_TRUE@ \ 2269@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-run.o \ 2270@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-scache.o \ 2271@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-trace.o \ 2272@SIM_ENABLE_ARCH_cris_TRUE@ cris/cgen-utils.o \ 2273@SIM_ENABLE_ARCH_cris_TRUE@ \ 2274@SIM_ENABLE_ARCH_cris_TRUE@ cris/arch.o \ 2275@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv10f.o \ 2276@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv10.o \ 2277@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev10.o \ 2278@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv10.o \ 2279@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.o \ 2280@SIM_ENABLE_ARCH_cris_TRUE@ cris/crisv32f.o \ 2281@SIM_ENABLE_ARCH_cris_TRUE@ cris/cpuv32.o \ 2282@SIM_ENABLE_ARCH_cris_TRUE@ cris/decodev32.o \ 2283@SIM_ENABLE_ARCH_cris_TRUE@ cris/modelv32.o \ 2284@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.o \ 2285@SIM_ENABLE_ARCH_cris_TRUE@ \ 2286@SIM_ENABLE_ARCH_cris_TRUE@ cris/sim-if.o \ 2287@SIM_ENABLE_ARCH_cris_TRUE@ cris/traps.o 2288 2289@SIM_ENABLE_ARCH_cris_TRUE@cris_run_SOURCES = 2290@SIM_ENABLE_ARCH_cris_TRUE@cris_run_LDADD = \ 2291@SIM_ENABLE_ARCH_cris_TRUE@ cris/nrun.o \ 2292@SIM_ENABLE_ARCH_cris_TRUE@ cris/libsim.a \ 2293@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_COMMON_LIBS) 2294 2295@SIM_ENABLE_ARCH_cris_TRUE@cris_SIM_EXTRA_HW_DEVICES = rv cris cris_900000xx 2296@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_SOURCES = cris/rvdummy.c 2297@SIM_ENABLE_ARCH_cris_TRUE@cris_rvdummy_LDADD = $(LIBIBERTY_LIB) 2298@SIM_ENABLE_ARCH_cris_TRUE@cris_BUILD_OUTPUTS = \ 2299@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv10f.c \ 2300@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v10f \ 2301@SIM_ENABLE_ARCH_cris_TRUE@ cris/mloopv32f.c \ 2302@SIM_ENABLE_ARCH_cris_TRUE@ cris/stamp-mloop-v32f 2303 2304@SIM_ENABLE_ARCH_d10v_TRUE@nodist_d10v_libsim_a_SOURCES = \ 2305@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/modules.c 2306 2307@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_SOURCES = \ 2308@SIM_ENABLE_ARCH_d10v_TRUE@ $(common_libcommon_a_SOURCES) 2309 2310@SIM_ENABLE_ARCH_d10v_TRUE@d10v_libsim_a_LIBADD = \ 2311@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/interp.o \ 2312@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/%,$(SIM_NEW_COMMON_OBJS)) \ 2313@SIM_ENABLE_ARCH_d10v_TRUE@ $(patsubst %,d10v/dv-%.o,$(SIM_HW_DEVICES)) \ 2314@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/endian.o \ 2315@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/sim-resume.o \ 2316@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/simops.o \ 2317@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.o 2318 2319@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_SOURCES = 2320@SIM_ENABLE_ARCH_d10v_TRUE@d10v_run_LDADD = \ 2321@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/nrun.o \ 2322@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/libsim.a \ 2323@SIM_ENABLE_ARCH_d10v_TRUE@ $(SIM_COMMON_LIBS) 2324 2325@SIM_ENABLE_ARCH_d10v_TRUE@d10v_BUILD_OUTPUTS = \ 2326@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/gencode$(EXEEXT) \ 2327@SIM_ENABLE_ARCH_d10v_TRUE@ d10v/table.c 2328 2329@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_SOURCES = d10v/gencode.c 2330@SIM_ENABLE_ARCH_d10v_TRUE@d10v_gencode_LDADD = d10v/d10v-opc.o 2331@SIM_ENABLE_ARCH_erc32_TRUE@READLINE_SRC = $(srcroot)/readline/readline 2332@SIM_ENABLE_ARCH_erc32_TRUE@AM_CPPFLAGS_erc32 = $(READLINE_CFLAGS) \ 2333@SIM_ENABLE_ARCH_erc32_TRUE@ -DFAST_UART 2334@SIM_ENABLE_ARCH_erc32_TRUE@nodist_erc32_libsim_a_SOURCES = \ 2335@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/modules.c 2336 2337@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_SOURCES = \ 2338@SIM_ENABLE_ARCH_erc32_TRUE@ $(common_libcommon_a_SOURCES) 2339 2340@SIM_ENABLE_ARCH_erc32_TRUE@erc32_libsim_a_LIBADD = \ 2341@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/erc32.o \ 2342@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/exec.o \ 2343@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/float.o \ 2344@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/func.o \ 2345@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/help.o \ 2346@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/interf.o 2347 2348@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_SOURCES = 2349@SIM_ENABLE_ARCH_erc32_TRUE@erc32_run_LDADD = \ 2350@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis.o \ 2351@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/libsim.a \ 2352@SIM_ENABLE_ARCH_erc32_TRUE@ $(SIM_COMMON_LIBS) $(READLINE_LIB) $(TERMCAP_LIB) 2353 2354@SIM_ENABLE_ARCH_erc32_TRUE@erc32docdir = $(docdir)/erc32 2355@SIM_ENABLE_ARCH_erc32_TRUE@erc32doc_DATA = erc32/README.erc32 erc32/README.gdb erc32/README.sis 2356@SIM_ENABLE_ARCH_examples_TRUE@nodist_example_synacor_libsim_a_SOURCES = \ 2357@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/modules.c 2358 2359@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_SOURCES = \ 2360@SIM_ENABLE_ARCH_examples_TRUE@ $(common_libcommon_a_SOURCES) 2361 2362@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_libsim_a_LIBADD = \ 2363@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/%,$(SIM_NEW_COMMON_OBJS)) \ 2364@SIM_ENABLE_ARCH_examples_TRUE@ $(patsubst %,example-synacor/dv-%.o,$(SIM_HW_DEVICES)) \ 2365@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/interp.o \ 2366@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-main.o \ 2367@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/sim-resume.o 2368 2369@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_SOURCES = 2370@SIM_ENABLE_ARCH_examples_TRUE@example_synacor_run_LDADD = \ 2371@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/nrun.o \ 2372@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/libsim.a \ 2373@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS) 2374 2375@SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS) 2376@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \ 2377@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.c 2378 2379@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_SOURCES = \ 2380@SIM_ENABLE_ARCH_frv_TRUE@ $(common_libcommon_a_SOURCES) 2381 2382@SIM_ENABLE_ARCH_frv_TRUE@frv_libsim_a_LIBADD = \ 2383@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/%,$(SIM_NEW_COMMON_OBJS)) \ 2384@SIM_ENABLE_ARCH_frv_TRUE@ $(patsubst %,frv/dv-%.o,$(SIM_HW_DEVICES)) \ 2385@SIM_ENABLE_ARCH_frv_TRUE@ \ 2386@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-accfp.o \ 2387@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-fpu.o \ 2388@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-run.o \ 2389@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-scache.o \ 2390@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-trace.o \ 2391@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-utils.o \ 2392@SIM_ENABLE_ARCH_frv_TRUE@ \ 2393@SIM_ENABLE_ARCH_frv_TRUE@ frv/arch.o \ 2394@SIM_ENABLE_ARCH_frv_TRUE@ frv/cgen-par.o \ 2395@SIM_ENABLE_ARCH_frv_TRUE@ frv/cpu.o \ 2396@SIM_ENABLE_ARCH_frv_TRUE@ frv/decode.o \ 2397@SIM_ENABLE_ARCH_frv_TRUE@ frv/frv.o \ 2398@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.o \ 2399@SIM_ENABLE_ARCH_frv_TRUE@ frv/model.o \ 2400@SIM_ENABLE_ARCH_frv_TRUE@ frv/sem.o \ 2401@SIM_ENABLE_ARCH_frv_TRUE@ \ 2402@SIM_ENABLE_ARCH_frv_TRUE@ frv/cache.o \ 2403@SIM_ENABLE_ARCH_frv_TRUE@ frv/interrupts.o \ 2404@SIM_ENABLE_ARCH_frv_TRUE@ frv/memory.o \ 2405@SIM_ENABLE_ARCH_frv_TRUE@ frv/options.o \ 2406@SIM_ENABLE_ARCH_frv_TRUE@ frv/pipeline.o \ 2407@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile.o \ 2408@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr400.o \ 2409@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr450.o \ 2410@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr500.o \ 2411@SIM_ENABLE_ARCH_frv_TRUE@ frv/profile-fr550.o \ 2412@SIM_ENABLE_ARCH_frv_TRUE@ frv/registers.o \ 2413@SIM_ENABLE_ARCH_frv_TRUE@ frv/reset.o \ 2414@SIM_ENABLE_ARCH_frv_TRUE@ frv/sim-if.o \ 2415@SIM_ENABLE_ARCH_frv_TRUE@ frv/traps.o 2416 2417@SIM_ENABLE_ARCH_frv_TRUE@frv_run_SOURCES = 2418@SIM_ENABLE_ARCH_frv_TRUE@frv_run_LDADD = \ 2419@SIM_ENABLE_ARCH_frv_TRUE@ frv/nrun.o \ 2420@SIM_ENABLE_ARCH_frv_TRUE@ frv/libsim.a \ 2421@SIM_ENABLE_ARCH_frv_TRUE@ $(SIM_COMMON_LIBS) 2422 2423@SIM_ENABLE_ARCH_frv_TRUE@frvdocdir = $(docdir)/frv 2424@SIM_ENABLE_ARCH_frv_TRUE@frvdoc_DATA = frv/README 2425@SIM_ENABLE_ARCH_frv_TRUE@frv_BUILD_OUTPUTS = \ 2426@SIM_ENABLE_ARCH_frv_TRUE@ frv/mloop.c \ 2427@SIM_ENABLE_ARCH_frv_TRUE@ frv/stamp-mloop 2428 2429@SIM_ENABLE_ARCH_ft32_TRUE@nodist_ft32_libsim_a_SOURCES = \ 2430@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/modules.c 2431 2432@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_SOURCES = \ 2433@SIM_ENABLE_ARCH_ft32_TRUE@ $(common_libcommon_a_SOURCES) 2434 2435@SIM_ENABLE_ARCH_ft32_TRUE@ft32_libsim_a_LIBADD = \ 2436@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/%,$(SIM_NEW_COMMON_OBJS)) \ 2437@SIM_ENABLE_ARCH_ft32_TRUE@ $(patsubst %,ft32/dv-%.o,$(SIM_HW_DEVICES)) \ 2438@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/interp.o \ 2439@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/sim-resume.o 2440 2441@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_SOURCES = 2442@SIM_ENABLE_ARCH_ft32_TRUE@ft32_run_LDADD = \ 2443@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/nrun.o \ 2444@SIM_ENABLE_ARCH_ft32_TRUE@ ft32/libsim.a \ 2445@SIM_ENABLE_ARCH_ft32_TRUE@ $(SIM_COMMON_LIBS) 2446 2447@SIM_ENABLE_ARCH_h8300_TRUE@nodist_h8300_libsim_a_SOURCES = \ 2448@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/modules.c 2449 2450@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_SOURCES = \ 2451@SIM_ENABLE_ARCH_h8300_TRUE@ $(common_libcommon_a_SOURCES) 2452 2453@SIM_ENABLE_ARCH_h8300_TRUE@h8300_libsim_a_LIBADD = \ 2454@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/compile.o \ 2455@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/%,$(SIM_NEW_COMMON_OBJS)) \ 2456@SIM_ENABLE_ARCH_h8300_TRUE@ $(patsubst %,h8300/dv-%.o,$(SIM_HW_DEVICES)) \ 2457@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/sim-resume.o 2458 2459@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_SOURCES = 2460@SIM_ENABLE_ARCH_h8300_TRUE@h8300_run_LDADD = \ 2461@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/nrun.o \ 2462@SIM_ENABLE_ARCH_h8300_TRUE@ h8300/libsim.a \ 2463@SIM_ENABLE_ARCH_h8300_TRUE@ $(SIM_COMMON_LIBS) 2464 2465@SIM_ENABLE_ARCH_iq2000_TRUE@nodist_iq2000_libsim_a_SOURCES = \ 2466@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/modules.c 2467 2468@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_SOURCES = \ 2469@SIM_ENABLE_ARCH_iq2000_TRUE@ $(common_libcommon_a_SOURCES) 2470 2471@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_LIBADD = \ 2472@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/%,$(SIM_NEW_COMMON_OBJS)) \ 2473@SIM_ENABLE_ARCH_iq2000_TRUE@ $(patsubst %,iq2000/dv-%.o,$(SIM_HW_DEVICES)) \ 2474@SIM_ENABLE_ARCH_iq2000_TRUE@ \ 2475@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-run.o \ 2476@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-scache.o \ 2477@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-trace.o \ 2478@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cgen-utils.o \ 2479@SIM_ENABLE_ARCH_iq2000_TRUE@ \ 2480@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/arch.o \ 2481@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/cpu.o \ 2482@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/decode.o \ 2483@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/iq2000.o \ 2484@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sem.o \ 2485@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.o \ 2486@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/model.o \ 2487@SIM_ENABLE_ARCH_iq2000_TRUE@ \ 2488@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/sim-if.o 2489 2490@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_SOURCES = 2491@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_run_LDADD = \ 2492@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/nrun.o \ 2493@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/libsim.a \ 2494@SIM_ENABLE_ARCH_iq2000_TRUE@ $(SIM_COMMON_LIBS) 2495 2496@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_BUILD_OUTPUTS = \ 2497@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/mloop.c \ 2498@SIM_ENABLE_ARCH_iq2000_TRUE@ iq2000/stamp-mloop 2499 2500@SIM_ENABLE_ARCH_lm32_TRUE@nodist_lm32_libsim_a_SOURCES = \ 2501@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/modules.c 2502 2503@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_SOURCES = \ 2504@SIM_ENABLE_ARCH_lm32_TRUE@ $(common_libcommon_a_SOURCES) 2505 2506@SIM_ENABLE_ARCH_lm32_TRUE@lm32_libsim_a_LIBADD = \ 2507@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/%,$(SIM_NEW_COMMON_OBJS)) \ 2508@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(SIM_HW_DEVICES)) \ 2509@SIM_ENABLE_ARCH_lm32_TRUE@ $(patsubst %,lm32/dv-%.o,$(lm32_SIM_EXTRA_HW_DEVICES)) \ 2510@SIM_ENABLE_ARCH_lm32_TRUE@ \ 2511@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-run.o \ 2512@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-scache.o \ 2513@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-trace.o \ 2514@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cgen-utils.o \ 2515@SIM_ENABLE_ARCH_lm32_TRUE@ \ 2516@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/arch.o \ 2517@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/cpu.o \ 2518@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/decode.o \ 2519@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sem.o \ 2520@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.o \ 2521@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/model.o \ 2522@SIM_ENABLE_ARCH_lm32_TRUE@ \ 2523@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/lm32.o \ 2524@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/sim-if.o \ 2525@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/traps.o \ 2526@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/user.o 2527 2528@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_SOURCES = 2529@SIM_ENABLE_ARCH_lm32_TRUE@lm32_run_LDADD = \ 2530@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/nrun.o \ 2531@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/libsim.a \ 2532@SIM_ENABLE_ARCH_lm32_TRUE@ $(SIM_COMMON_LIBS) 2533 2534@SIM_ENABLE_ARCH_lm32_TRUE@lm32_SIM_EXTRA_HW_DEVICES = lm32cpu lm32timer lm32uart 2535@SIM_ENABLE_ARCH_lm32_TRUE@lm32_BUILD_OUTPUTS = \ 2536@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/mloop.c \ 2537@SIM_ENABLE_ARCH_lm32_TRUE@ lm32/stamp-mloop 2538 2539@SIM_ENABLE_ARCH_m32c_TRUE@AM_CPPFLAGS_m32c = -DTIMER_A 2540@SIM_ENABLE_ARCH_m32c_TRUE@nodist_m32c_libsim_a_SOURCES = \ 2541@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/modules.c 2542 2543@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_SOURCES = \ 2544@SIM_ENABLE_ARCH_m32c_TRUE@ $(common_libcommon_a_SOURCES) 2545 2546@SIM_ENABLE_ARCH_m32c_TRUE@m32c_libsim_a_LIBADD = \ 2547@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/gdb-if.o \ 2548@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/int.o \ 2549@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/load.o \ 2550@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.o \ 2551@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/mem.o \ 2552@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/misc.o \ 2553@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.o \ 2554@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/reg.o \ 2555@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/srcdest.o \ 2556@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/syscalls.o \ 2557@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/trace.o 2558 2559@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_SOURCES = 2560@SIM_ENABLE_ARCH_m32c_TRUE@m32c_run_LDADD = \ 2561@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/main.o \ 2562@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/libsim.a \ 2563@SIM_ENABLE_ARCH_m32c_TRUE@ $(SIM_COMMON_LIBS) 2564 2565@SIM_ENABLE_ARCH_m32c_TRUE@m32c_BUILD_OUTPUTS = \ 2566@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/opc2c$(EXEEXT) \ 2567@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c \ 2568@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c 2569 2570@SIM_ENABLE_ARCH_m32c_TRUE@m32c_opc2c_SOURCES = m32c/opc2c.c 2571 2572# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable 2573# leak detection while running it. 2574@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT) 2575@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \ 2576@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c 2577 2578@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_SOURCES = \ 2579@SIM_ENABLE_ARCH_m32r_TRUE@ $(common_libcommon_a_SOURCES) 2580 2581@SIM_ENABLE_ARCH_m32r_TRUE@m32r_libsim_a_LIBADD = \ 2582@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/%,$(SIM_NEW_COMMON_OBJS)) \ 2583@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(SIM_HW_DEVICES)) \ 2584@SIM_ENABLE_ARCH_m32r_TRUE@ $(patsubst %,m32r/dv-%.o,$(m32r_SIM_EXTRA_HW_DEVICES)) \ 2585@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2586@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-run.o \ 2587@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-scache.o \ 2588@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-trace.o \ 2589@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cgen-utils.o \ 2590@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2591@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/arch.o \ 2592@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2593@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r.o \ 2594@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu.o \ 2595@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode.o \ 2596@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sem.o \ 2597@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model.o \ 2598@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.o \ 2599@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2600@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32rx.o \ 2601@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpux.o \ 2602@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decodex.o \ 2603@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modelx.o \ 2604@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.o \ 2605@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2606@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/m32r2.o \ 2607@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/cpu2.o \ 2608@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/decode2.o \ 2609@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/model2.o \ 2610@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.o \ 2611@SIM_ENABLE_ARCH_m32r_TRUE@ \ 2612@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/sim-if.o \ 2613@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/traps.o 2614 2615@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_SOURCES = 2616@SIM_ENABLE_ARCH_m32r_TRUE@m32r_run_LDADD = \ 2617@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/nrun.o \ 2618@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/libsim.a \ 2619@SIM_ENABLE_ARCH_m32r_TRUE@ $(SIM_COMMON_LIBS) 2620 2621@SIM_ENABLE_ARCH_m32r_TRUE@m32r_SIM_EXTRA_HW_DEVICES = m32r_cache m32r_uart 2622@SIM_ENABLE_ARCH_m32r_TRUE@m32r_BUILD_OUTPUTS = \ 2623@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop.c \ 2624@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop \ 2625@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloopx.c \ 2626@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-x \ 2627@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/mloop2.c \ 2628@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/stamp-mloop-2 2629 2630@SIM_ENABLE_ARCH_m68hc11_TRUE@AM_CPPFLAGS_m68hc11 = \ 2631@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 \ 2632@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_CELL_BITSIZE=32 \ 2633@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_ADDRESS_BITSIZE=32 \ 2634@SIM_ENABLE_ARCH_m68hc11_TRUE@ -DWITH_TARGET_WORD_MSB=31 2635 2636@SIM_ENABLE_ARCH_m68hc11_TRUE@nodist_m68hc11_libsim_a_SOURCES = \ 2637@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/modules.c 2638 2639@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_SOURCES = \ 2640@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(common_libcommon_a_SOURCES) 2641 2642@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_libsim_a_LIBADD = \ 2643@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interp.o \ 2644@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.o \ 2645@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.o \ 2646@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/emulos.o \ 2647@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/interrupts.o \ 2648@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11_sim.o \ 2649@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/%,$(SIM_NEW_COMMON_OBJS)) \ 2650@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(SIM_HW_DEVICES)) \ 2651@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(patsubst %,m68hc11/dv-%.o,$(m68hc11_SIM_EXTRA_HW_DEVICES)) \ 2652@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/sim-resume.o 2653 2654@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_SOURCES = 2655@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_run_LDADD = \ 2656@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/nrun.o \ 2657@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/libsim.a \ 2658@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(SIM_COMMON_LIBS) 2659 2660@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_SIM_EXTRA_HW_DEVICES = m68hc11 m68hc11sio m68hc11eepr m68hc11tim m68hc11spi nvram 2661@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_BUILD_OUTPUTS = \ 2662@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/gencode$(EXEEXT) \ 2663@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc11int.c \ 2664@SIM_ENABLE_ARCH_m68hc11_TRUE@ m68hc11/m68hc12int.c 2665 2666@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11_gencode_SOURCES = m68hc11/gencode.c 2667@SIM_ENABLE_ARCH_mcore_TRUE@nodist_mcore_libsim_a_SOURCES = \ 2668@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/modules.c 2669 2670@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_SOURCES = \ 2671@SIM_ENABLE_ARCH_mcore_TRUE@ $(common_libcommon_a_SOURCES) 2672 2673@SIM_ENABLE_ARCH_mcore_TRUE@mcore_libsim_a_LIBADD = \ 2674@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/interp.o \ 2675@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/%,$(SIM_NEW_COMMON_OBJS)) \ 2676@SIM_ENABLE_ARCH_mcore_TRUE@ $(patsubst %,mcore/dv-%.o,$(SIM_HW_DEVICES)) \ 2677@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/sim-resume.o 2678 2679@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_SOURCES = 2680@SIM_ENABLE_ARCH_mcore_TRUE@mcore_run_LDADD = \ 2681@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/nrun.o \ 2682@SIM_ENABLE_ARCH_mcore_TRUE@ mcore/libsim.a \ 2683@SIM_ENABLE_ARCH_mcore_TRUE@ $(SIM_COMMON_LIBS) 2684 2685@SIM_ENABLE_ARCH_microblaze_TRUE@nodist_microblaze_libsim_a_SOURCES = \ 2686@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/modules.c 2687 2688@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_SOURCES = \ 2689@SIM_ENABLE_ARCH_microblaze_TRUE@ $(common_libcommon_a_SOURCES) 2690 2691@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_libsim_a_LIBADD = \ 2692@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/interp.o \ 2693@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/%,$(SIM_NEW_COMMON_OBJS)) \ 2694@SIM_ENABLE_ARCH_microblaze_TRUE@ $(patsubst %,microblaze/dv-%.o,$(SIM_HW_DEVICES)) \ 2695@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/sim-resume.o 2696 2697@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_SOURCES = 2698@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze_run_LDADD = \ 2699@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/nrun.o \ 2700@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/libsim.a \ 2701@SIM_ENABLE_ARCH_microblaze_TRUE@ $(SIM_COMMON_LIBS) 2702 2703@SIM_ENABLE_ARCH_mips_TRUE@AM_CPPFLAGS_mips = \ 2704@SIM_ENABLE_ARCH_mips_TRUE@ @SIM_MIPS_SUBTARGET@ \ 2705@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \ 2706@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@ 2707 2708@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \ 2709@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75) 2710@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \ 2711@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c 2712 2713@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_SOURCES = \ 2714@SIM_ENABLE_ARCH_mips_TRUE@ $(common_libcommon_a_SOURCES) 2715 2716@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_LIBADD = \ 2717@SIM_ENABLE_ARCH_mips_TRUE@ mips/interp.o \ 2718@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_GEN_OBJ) \ 2719@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/%,$(SIM_NEW_COMMON_OBJS)) \ 2720@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(SIM_HW_DEVICES)) \ 2721@SIM_ENABLE_ARCH_mips_TRUE@ $(patsubst %,mips/dv-%.o,$(mips_SIM_EXTRA_HW_DEVICES)) \ 2722@SIM_ENABLE_ARCH_mips_TRUE@ mips/cp1.o \ 2723@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.o \ 2724@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.o \ 2725@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-main.o \ 2726@SIM_ENABLE_ARCH_mips_TRUE@ mips/sim-resume.o 2727 2728@SIM_ENABLE_ARCH_mips_TRUE@EXTRA_mips_libsim_a_DEPENDENCIES = $(SIM_MIPS_MULTI_OBJ) 2729@SIM_ENABLE_ARCH_mips_TRUE@mips_run_SOURCES = 2730@SIM_ENABLE_ARCH_mips_TRUE@mips_run_LDADD = \ 2731@SIM_ENABLE_ARCH_mips_TRUE@ mips/nrun.o \ 2732@SIM_ENABLE_ARCH_mips_TRUE@ mips/libsim.a \ 2733@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_COMMON_LIBS) 2734 2735@SIM_ENABLE_ARCH_mips_TRUE@mips_SIM_EXTRA_HW_DEVICES = tx3904cpu tx3904irc tx3904tmr tx3904sio 2736@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_IGEN_ITABLE = \ 2737@SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.h \ 2738@SIM_ENABLE_ARCH_mips_TRUE@ mips/itable.c 2739 2740@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_SINGLE = \ 2741@SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.h \ 2742@SIM_ENABLE_ARCH_mips_TRUE@ mips/icache.c \ 2743@SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.h \ 2744@SIM_ENABLE_ARCH_mips_TRUE@ mips/idecode.c \ 2745@SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.h \ 2746@SIM_ENABLE_ARCH_mips_TRUE@ mips/semantics.c \ 2747@SIM_ENABLE_ARCH_mips_TRUE@ mips/model.h \ 2748@SIM_ENABLE_ARCH_mips_TRUE@ mips/model.c \ 2749@SIM_ENABLE_ARCH_mips_TRUE@ mips/support.h \ 2750@SIM_ENABLE_ARCH_mips_TRUE@ mips/support.c \ 2751@SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.h \ 2752@SIM_ENABLE_ARCH_mips_TRUE@ mips/engine.c \ 2753@SIM_ENABLE_ARCH_mips_TRUE@ mips/irun.c 2754 2755@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M16 = \ 2756@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.h \ 2757@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_icache.c \ 2758@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.h \ 2759@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_idecode.c \ 2760@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.h \ 2761@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_semantics.c \ 2762@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.h \ 2763@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_model.c \ 2764@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.h \ 2765@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16_support.c \ 2766@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILT_SRC_FROM_GEN_MODE_M16_M32 = \ 2767@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.h \ 2768@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_icache.c \ 2769@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.h \ 2770@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_idecode.c \ 2771@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.h \ 2772@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_semantics.c \ 2773@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.h \ 2774@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_model.c \ 2775@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.h \ 2776@SIM_ENABLE_ARCH_mips_TRUE@ mips/m32_support.c 2777 2778@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \ 2779@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \ 2780@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \ 2781@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \ 2782@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81) 2783@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all 2784@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen 2785@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \ 2786@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp.igen \ 2787@SIM_ENABLE_ARCH_mips_TRUE@ mips/dsp2.igen \ 2788@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16.igen \ 2789@SIM_ENABLE_ARCH_mips_TRUE@ mips/m16e.igen \ 2790@SIM_ENABLE_ARCH_mips_TRUE@ mips/mdmx.igen \ 2791@SIM_ENABLE_ARCH_mips_TRUE@ mips/micromipsdsp.igen \ 2792@SIM_ENABLE_ARCH_mips_TRUE@ mips/micromips.igen \ 2793@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r2.igen \ 2794@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3264r6.igen \ 2795@SIM_ENABLE_ARCH_mips_TRUE@ mips/mips3d.igen \ 2796@SIM_ENABLE_ARCH_mips_TRUE@ mips/sb1.igen \ 2797@SIM_ENABLE_ARCH_mips_TRUE@ mips/tx.igen \ 2798@SIM_ENABLE_ARCH_mips_TRUE@ mips/vr.igen 2799 2800@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_DC = $(srcdir)/mips/mips.dc 2801@SIM_ENABLE_ARCH_mips_TRUE@mips_M16_DC = $(srcdir)/mips/m16.dc 2802@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS32_DC = $(srcdir)/mips/micromips.dc 2803@SIM_ENABLE_ARCH_mips_TRUE@mips_MICROMIPS16_DC = $(srcdir)/mips/micromips16.dc 2804@SIM_ENABLE_ARCH_mn10300_TRUE@AM_CPPFLAGS_mn10300 = \ 2805@SIM_ENABLE_ARCH_mn10300_TRUE@ -DPOLL_QUIT_INTERVAL=0x20 \ 2806@SIM_ENABLE_ARCH_mn10300_TRUE@ -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 2807 2808@SIM_ENABLE_ARCH_mn10300_TRUE@nodist_mn10300_libsim_a_SOURCES = \ 2809@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/modules.c 2810 2811@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_SOURCES = \ 2812@SIM_ENABLE_ARCH_mn10300_TRUE@ $(common_libcommon_a_SOURCES) 2813 2814@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_libsim_a_LIBADD = \ 2815@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.o \ 2816@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.o \ 2817@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.o \ 2818@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.o \ 2819@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.o \ 2820@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.o \ 2821@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.o \ 2822@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/%,$(SIM_NEW_COMMON_OBJS)) \ 2823@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(SIM_HW_DEVICES)) \ 2824@SIM_ENABLE_ARCH_mn10300_TRUE@ $(patsubst %,mn10300/dv-%.o,$(mn10300_SIM_EXTRA_HW_DEVICES)) \ 2825@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/interp.o \ 2826@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/op_utils.o \ 2827@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/sim-resume.o 2828 2829@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_SOURCES = 2830@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_run_LDADD = \ 2831@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/nrun.o \ 2832@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/libsim.a \ 2833@SIM_ENABLE_ARCH_mn10300_TRUE@ $(SIM_COMMON_LIBS) 2834 2835@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_SIM_EXTRA_HW_DEVICES = mn103cpu mn103int mn103tim mn103ser mn103iop 2836@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILT_SRC_FROM_IGEN = \ 2837@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \ 2838@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.c \ 2839@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \ 2840@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.c \ 2841@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \ 2842@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.c \ 2843@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.h \ 2844@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/model.c \ 2845@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.h \ 2846@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/support.c \ 2847@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \ 2848@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.c \ 2849@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h \ 2850@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.c \ 2851@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/irun.c 2852 2853@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_BUILD_OUTPUTS = \ 2854@SIM_ENABLE_ARCH_mn10300_TRUE@ $(mn10300_BUILT_SRC_FROM_IGEN) \ 2855@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/stamp-igen 2856 2857@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries 2858@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN = $(srcdir)/mn10300/mn10300.igen 2859@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_INSN_INC = mn10300/am33.igen mn10300/am33-2.igen 2860@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300_IGEN_DC = $(srcdir)/mn10300/mn10300.dc 2861@SIM_ENABLE_ARCH_moxie_TRUE@AM_CPPFLAGS_moxie = -DDTB="\"$(dtbdir)/moxie-gdb.dtb\"" 2862@SIM_ENABLE_ARCH_moxie_TRUE@nodist_moxie_libsim_a_SOURCES = \ 2863@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/modules.c 2864 2865@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_SOURCES = \ 2866@SIM_ENABLE_ARCH_moxie_TRUE@ $(common_libcommon_a_SOURCES) 2867 2868@SIM_ENABLE_ARCH_moxie_TRUE@moxie_libsim_a_LIBADD = \ 2869@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/%,$(SIM_NEW_COMMON_OBJS)) \ 2870@SIM_ENABLE_ARCH_moxie_TRUE@ $(patsubst %,moxie/dv-%.o,$(SIM_HW_DEVICES)) \ 2871@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/interp.o \ 2872@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/sim-resume.o 2873 2874@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_SOURCES = 2875@SIM_ENABLE_ARCH_moxie_TRUE@moxie_run_LDADD = \ 2876@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/nrun.o \ 2877@SIM_ENABLE_ARCH_moxie_TRUE@ moxie/libsim.a \ 2878@SIM_ENABLE_ARCH_moxie_TRUE@ $(SIM_COMMON_LIBS) 2879 2880@SIM_ENABLE_ARCH_moxie_TRUE@dtbdir = $(datadir)/gdb/dtb 2881@SIM_ENABLE_ARCH_moxie_TRUE@dtb_DATA = moxie/moxie-gdb.dtb 2882@SIM_ENABLE_ARCH_msp430_TRUE@nodist_msp430_libsim_a_SOURCES = \ 2883@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/modules.c 2884 2885@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_SOURCES = \ 2886@SIM_ENABLE_ARCH_msp430_TRUE@ $(common_libcommon_a_SOURCES) 2887 2888@SIM_ENABLE_ARCH_msp430_TRUE@msp430_libsim_a_LIBADD = \ 2889@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/%,$(SIM_NEW_COMMON_OBJS)) \ 2890@SIM_ENABLE_ARCH_msp430_TRUE@ $(patsubst %,msp430/dv-%.o,$(SIM_HW_DEVICES)) \ 2891@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/msp430-sim.o \ 2892@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/sim-resume.o 2893 2894@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_SOURCES = 2895@SIM_ENABLE_ARCH_msp430_TRUE@msp430_run_LDADD = \ 2896@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/nrun.o \ 2897@SIM_ENABLE_ARCH_msp430_TRUE@ msp430/libsim.a \ 2898@SIM_ENABLE_ARCH_msp430_TRUE@ $(SIM_COMMON_LIBS) 2899 2900@SIM_ENABLE_ARCH_or1k_TRUE@AM_CPPFLAGS_or1k = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 2901@SIM_ENABLE_ARCH_or1k_TRUE@nodist_or1k_libsim_a_SOURCES = \ 2902@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.c 2903 2904@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_SOURCES = \ 2905@SIM_ENABLE_ARCH_or1k_TRUE@ $(common_libcommon_a_SOURCES) 2906 2907@SIM_ENABLE_ARCH_or1k_TRUE@or1k_libsim_a_LIBADD = \ 2908@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/%,$(SIM_NEW_COMMON_OBJS)) \ 2909@SIM_ENABLE_ARCH_or1k_TRUE@ $(patsubst %,or1k/dv-%.o,$(SIM_HW_DEVICES)) \ 2910@SIM_ENABLE_ARCH_or1k_TRUE@ \ 2911@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-accfp.o \ 2912@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-fpu.o \ 2913@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-run.o \ 2914@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-scache.o \ 2915@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-trace.o \ 2916@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cgen-utils.o \ 2917@SIM_ENABLE_ARCH_or1k_TRUE@ \ 2918@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/arch.o \ 2919@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/cpu.o \ 2920@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/decode.o \ 2921@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.o \ 2922@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/model.o \ 2923@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sem.o \ 2924@SIM_ENABLE_ARCH_or1k_TRUE@ \ 2925@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/or1k.o \ 2926@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/sim-if.o \ 2927@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/traps.o 2928 2929@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_SOURCES = 2930@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_LDADD = \ 2931@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/nrun.o \ 2932@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/libsim.a \ 2933@SIM_ENABLE_ARCH_or1k_TRUE@ $(SIM_COMMON_LIBS) 2934 2935@SIM_ENABLE_ARCH_or1k_TRUE@or1kdocdir = $(docdir)/or1k 2936@SIM_ENABLE_ARCH_or1k_TRUE@or1kdoc_DATA = or1k/README 2937@SIM_ENABLE_ARCH_or1k_TRUE@or1k_BUILD_OUTPUTS = \ 2938@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.c \ 2939@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/stamp-mloop 2940 2941@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc = \ 2942@SIM_ENABLE_ARCH_ppc_TRUE@ -DHAVE_COMMON_FPU \ 2943@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_smp) \ 2944@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_xor_endian) \ 2945@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_bitsize) \ 2946@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_timebase) \ 2947@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_float) \ 2948@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_monitor) \ 2949@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_model) $(sim_ppc_default_model) $(sim_ppc_model_issue) \ 2950@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_switch) 2951 2952@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc_options.o = '-DOPCODE_RULES="$(IGEN_OPCODE_RULES)"' '-DIGEN_FLAGS="$(ppc_IGEN_FLAGS)"' 2953@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_SOURCES = \ 2954@SIM_ENABLE_ARCH_ppc_TRUE@ $(common_libcommon_a_SOURCES) 2955 2956@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_LIBADD = \ 2957@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/debug.o \ 2958@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o \ 2959@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-endian.o \ 2960@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o \ 2961@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_generic.o \ 2962@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o \ 2963@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_chirp.o \ 2964@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o \ 2965@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_unix.o \ 2966@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o \ 2967@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/vm.o \ 2968@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o \ 2969@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.o \ 2970@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o \ 2971@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cpu.o \ 2972@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o \ 2973@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/events.o \ 2974@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o \ 2975@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device.o \ 2976@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/tree.o \ 2977@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o \ 2978@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.o \ 2979@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o \ 2980@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.o \ 2981@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o \ 2982@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.o \ 2983@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o \ 2984@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-fpu.o \ 2985@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o \ 2986@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/pk_disklabel.o \ 2987@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst %,ppc/%,$(sim_ppc_hw_obj)) \ 2988@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o \ 2989@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gdb-sim.o \ 2990@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o 2991 2992@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = \ 2993@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.c 2994 2995@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \ 2996@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a \ 2997@SIM_ENABLE_ARCH_ppc_TRUE@ $(SIM_COMMON_LIBS) 2998 2999@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_SOURCES = \ 3000@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.c \ 3001@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.c \ 3002@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.c \ 3003@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.c \ 3004@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.c \ 3005@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.c \ 3006@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.c \ 3007@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.c \ 3008@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.c \ 3009@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.c \ 3010@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.c \ 3011@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.c \ 3012@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.c 3013 3014@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_LIBADD = \ 3015@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter.o \ 3016@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o \ 3017@SIM_ENABLE_ARCH_ppc_TRUE@ igen/lf.o \ 3018@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o 3019 3020@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_SOURCES = ppc/igen.c 3021@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_LDADD = ppc/libigen.a 3022 3023# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable 3024# leak detection while running it. 3025@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN = ppc/igen$(EXEEXT) 3026@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(PPC_IGEN) $(ppc_IGEN_FLAGS) 3027@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_FLAGS = \ 3028@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_decode_mechanism@ \ 3029@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_dup@ \ 3030@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_jump@ \ 3031@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_filter@ \ 3032@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_icache@ \ 3033@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_igen_smp@ \ 3034@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_line_nr@ 3035 3036@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILT_SRC_FROM_IGEN = \ 3037@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.h \ 3038@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.c \ 3039@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h \ 3040@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.c \ 3041@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.h \ 3042@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.c \ 3043@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h \ 3044@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.c \ 3045@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.h \ 3046@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.c \ 3047@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h \ 3048@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.c 3049 3050@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILD_OUTPUTS = \ 3051@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILT_SRC_FROM_IGEN) \ 3052@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-igen ppc/hw.c ppc/hw.h \ 3053@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-hw ppc/stamp-pk 3054@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_OPCODE_RULES = ppc/@sim_ppc_opcode@ 3055@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_SOURCES = 3056@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_LDADD = ppc/ld-cache-main.o ppc/libigen.a 3057@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_SOURCES = 3058@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_LDADD = ppc/ld-decode-main.o ppc/libigen.a 3059@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_SOURCES = 3060@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_LDADD = ppc/ld-insn-main.o ppc/libigen.a 3061@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_TOOLS = \ 3062@SIM_ENABLE_ARCH_ppc_TRUE@ $(PPC_IGEN) \ 3063@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache \ 3064@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode \ 3065@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn 3066 3067@SIM_ENABLE_ARCH_ppc_TRUE@IGEN_OPCODE_RULES = @sim_ppc_opcode@ 3068@SIM_ENABLE_ARCH_ppc_TRUE@ppc_HW_SRC = $(sim_ppc_hw_src:%=ppc/%) 3069@SIM_ENABLE_ARCH_ppc_TRUE@ppc_PACKAGE_SRC = ppc/pk_disklabel.c 3070@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc 3071@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN 3072@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_SOURCES = \ 3073@SIM_ENABLE_ARCH_pru_TRUE@ pru/modules.c 3074 3075@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_SOURCES = \ 3076@SIM_ENABLE_ARCH_pru_TRUE@ $(common_libcommon_a_SOURCES) 3077 3078@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_LIBADD = \ 3079@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/%,$(SIM_NEW_COMMON_OBJS)) \ 3080@SIM_ENABLE_ARCH_pru_TRUE@ $(patsubst %,pru/dv-%.o,$(SIM_HW_DEVICES)) \ 3081@SIM_ENABLE_ARCH_pru_TRUE@ pru/interp.o \ 3082@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o 3083 3084@SIM_ENABLE_ARCH_pru_TRUE@pru_run_SOURCES = 3085@SIM_ENABLE_ARCH_pru_TRUE@pru_run_LDADD = \ 3086@SIM_ENABLE_ARCH_pru_TRUE@ pru/nrun.o \ 3087@SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a \ 3088@SIM_ENABLE_ARCH_pru_TRUE@ $(SIM_COMMON_LIBS) 3089 3090@SIM_ENABLE_ARCH_riscv_TRUE@AM_CPPFLAGS_riscv = -DWITH_TARGET_WORD_BITSIZE=$(SIM_RISCV_BITSIZE) 3091@SIM_ENABLE_ARCH_riscv_TRUE@nodist_riscv_libsim_a_SOURCES = \ 3092@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.c 3093 3094@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES = \ 3095@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_SOURCES) 3096 3097@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \ 3098@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \ 3099@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \ 3100@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o \ 3101@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/machs.o \ 3102@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \ 3103@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o 3104 3105@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES = 3106@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \ 3107@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/nrun.o \ 3108@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/libsim.a \ 3109@SIM_ENABLE_ARCH_riscv_TRUE@ $(SIM_COMMON_LIBS) 3110 3111@SIM_ENABLE_ARCH_rl78_TRUE@nodist_rl78_libsim_a_SOURCES = \ 3112@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/modules.c 3113 3114@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_SOURCES = \ 3115@SIM_ENABLE_ARCH_rl78_TRUE@ $(common_libcommon_a_SOURCES) 3116 3117@SIM_ENABLE_ARCH_rl78_TRUE@rl78_libsim_a_LIBADD = \ 3118@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/load.o \ 3119@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/mem.o \ 3120@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/cpu.o \ 3121@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/rl78.o \ 3122@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/gdb-if.o \ 3123@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/trace.o 3124 3125@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_SOURCES = 3126@SIM_ENABLE_ARCH_rl78_TRUE@rl78_run_LDADD = \ 3127@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/main.o \ 3128@SIM_ENABLE_ARCH_rl78_TRUE@ rl78/libsim.a \ 3129@SIM_ENABLE_ARCH_rl78_TRUE@ $(SIM_COMMON_LIBS) 3130 3131@SIM_ENABLE_ARCH_rx_TRUE@AM_CPPFLAGS_rx = $(SIM_RX_CYCLE_ACCURATE_FLAGS) 3132@SIM_ENABLE_ARCH_rx_TRUE@nodist_rx_libsim_a_SOURCES = \ 3133@SIM_ENABLE_ARCH_rx_TRUE@ rx/modules.c 3134 3135@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_SOURCES = \ 3136@SIM_ENABLE_ARCH_rx_TRUE@ $(common_libcommon_a_SOURCES) 3137 3138@SIM_ENABLE_ARCH_rx_TRUE@rx_libsim_a_LIBADD = \ 3139@SIM_ENABLE_ARCH_rx_TRUE@ rx/fpu.o \ 3140@SIM_ENABLE_ARCH_rx_TRUE@ rx/load.o \ 3141@SIM_ENABLE_ARCH_rx_TRUE@ rx/mem.o \ 3142@SIM_ENABLE_ARCH_rx_TRUE@ rx/misc.o \ 3143@SIM_ENABLE_ARCH_rx_TRUE@ rx/reg.o \ 3144@SIM_ENABLE_ARCH_rx_TRUE@ rx/rx.o \ 3145@SIM_ENABLE_ARCH_rx_TRUE@ rx/syscalls.o \ 3146@SIM_ENABLE_ARCH_rx_TRUE@ rx/trace.o \ 3147@SIM_ENABLE_ARCH_rx_TRUE@ rx/gdb-if.o \ 3148@SIM_ENABLE_ARCH_rx_TRUE@ rx/err.o 3149 3150@SIM_ENABLE_ARCH_rx_TRUE@rx_run_SOURCES = 3151@SIM_ENABLE_ARCH_rx_TRUE@rx_run_LDADD = \ 3152@SIM_ENABLE_ARCH_rx_TRUE@ rx/main.o \ 3153@SIM_ENABLE_ARCH_rx_TRUE@ rx/libsim.a \ 3154@SIM_ENABLE_ARCH_rx_TRUE@ $(SIM_COMMON_LIBS) 3155 3156@SIM_ENABLE_ARCH_rx_TRUE@rxdocdir = $(docdir)/rx 3157@SIM_ENABLE_ARCH_rx_TRUE@rxdoc_DATA = rx/README.txt 3158@SIM_ENABLE_ARCH_sh_TRUE@nodist_sh_libsim_a_SOURCES = \ 3159@SIM_ENABLE_ARCH_sh_TRUE@ sh/modules.c 3160 3161@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_SOURCES = \ 3162@SIM_ENABLE_ARCH_sh_TRUE@ $(common_libcommon_a_SOURCES) 3163 3164@SIM_ENABLE_ARCH_sh_TRUE@sh_libsim_a_LIBADD = \ 3165@SIM_ENABLE_ARCH_sh_TRUE@ sh/interp.o \ 3166@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/%,$(SIM_NEW_COMMON_OBJS)) \ 3167@SIM_ENABLE_ARCH_sh_TRUE@ $(patsubst %,sh/dv-%.o,$(SIM_HW_DEVICES)) \ 3168@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.o 3169 3170@SIM_ENABLE_ARCH_sh_TRUE@sh_run_SOURCES = 3171@SIM_ENABLE_ARCH_sh_TRUE@sh_run_LDADD = \ 3172@SIM_ENABLE_ARCH_sh_TRUE@ sh/nrun.o \ 3173@SIM_ENABLE_ARCH_sh_TRUE@ sh/libsim.a \ 3174@SIM_ENABLE_ARCH_sh_TRUE@ $(SIM_COMMON_LIBS) 3175 3176@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \ 3177@SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \ 3178@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \ 3179@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c \ 3180@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c 3181 3182@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c 3183@SIM_ENABLE_ARCH_v850_TRUE@AM_CPPFLAGS_v850 = -DWITH_TARGET_WORD_BITSIZE=32 -DWITH_TARGET_WORD_MSB=31 3184@SIM_ENABLE_ARCH_v850_TRUE@nodist_v850_libsim_a_SOURCES = \ 3185@SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.c 3186 3187@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_SOURCES = \ 3188@SIM_ENABLE_ARCH_v850_TRUE@ $(common_libcommon_a_SOURCES) 3189 3190@SIM_ENABLE_ARCH_v850_TRUE@v850_libsim_a_LIBADD = \ 3191@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/%,$(SIM_NEW_COMMON_OBJS)) \ 3192@SIM_ENABLE_ARCH_v850_TRUE@ $(patsubst %,v850/dv-%.o,$(SIM_HW_DEVICES)) \ 3193@SIM_ENABLE_ARCH_v850_TRUE@ v850/simops.o \ 3194@SIM_ENABLE_ARCH_v850_TRUE@ v850/interp.o \ 3195@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.o \ 3196@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.o \ 3197@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.o \ 3198@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.o \ 3199@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.o \ 3200@SIM_ENABLE_ARCH_v850_TRUE@ v850/irun.o \ 3201@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.o \ 3202@SIM_ENABLE_ARCH_v850_TRUE@ v850/sim-resume.o 3203 3204@SIM_ENABLE_ARCH_v850_TRUE@v850_run_SOURCES = 3205@SIM_ENABLE_ARCH_v850_TRUE@v850_run_LDADD = \ 3206@SIM_ENABLE_ARCH_v850_TRUE@ v850/nrun.o \ 3207@SIM_ENABLE_ARCH_v850_TRUE@ v850/libsim.a \ 3208@SIM_ENABLE_ARCH_v850_TRUE@ $(SIM_COMMON_LIBS) 3209 3210@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILT_SRC_FROM_IGEN = \ 3211@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \ 3212@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.c \ 3213@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \ 3214@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.c \ 3215@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \ 3216@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.c \ 3217@SIM_ENABLE_ARCH_v850_TRUE@ v850/model.h \ 3218@SIM_ENABLE_ARCH_v850_TRUE@ v850/model.c \ 3219@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.h \ 3220@SIM_ENABLE_ARCH_v850_TRUE@ v850/support.c \ 3221@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \ 3222@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.c \ 3223@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h \ 3224@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.c \ 3225@SIM_ENABLE_ARCH_v850_TRUE@ v850/irun.c 3226 3227@SIM_ENABLE_ARCH_v850_TRUE@v850_BUILD_OUTPUTS = \ 3228@SIM_ENABLE_ARCH_v850_TRUE@ $(v850_BUILT_SRC_FROM_IGEN) \ 3229@SIM_ENABLE_ARCH_v850_TRUE@ v850/stamp-igen 3230 3231@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries 3232@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen 3233@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc 3234all: $(BUILT_SOURCES) config.h 3235 $(MAKE) $(AM_MAKEFLAGS) all-am 3236 3237.SUFFIXES: 3238.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs 3239am--refresh: Makefile 3240 @: 3241$(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__configure_deps) 3242 @for dep in $?; do \ 3243 case '$(am__configure_deps)' in \ 3244 *$$dep*) \ 3245 echo ' cd $(srcdir) && $(AUTOMAKE) --foreign'; \ 3246 $(am__cd) $(srcdir) && $(AUTOMAKE) --foreign \ 3247 && exit 0; \ 3248 exit 1;; \ 3249 esac; \ 3250 done; \ 3251 echo ' cd $(top_srcdir) && $(AUTOMAKE) --foreign Makefile'; \ 3252 $(am__cd) $(top_srcdir) && \ 3253 $(AUTOMAKE) --foreign Makefile 3254Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status 3255 @case '$?' in \ 3256 *config.status*) \ 3257 echo ' $(SHELL) ./config.status'; \ 3258 $(SHELL) ./config.status;; \ 3259 *) \ 3260 echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \ 3261 cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \ 3262 esac; 3263$(srcdir)/common/local.mk $(srcdir)/igen/local.mk $(srcdir)/testsuite/local.mk $(srcdir)/testsuite/common/local.mk $(srcdir)/aarch64/local.mk $(srcdir)/arm/local.mk $(srcdir)/avr/local.mk $(srcdir)/bfin/local.mk $(srcdir)/bpf/local.mk $(srcdir)/cr16/local.mk $(srcdir)/cris/local.mk $(srcdir)/d10v/local.mk $(srcdir)/erc32/local.mk $(srcdir)/example-synacor/local.mk $(srcdir)/frv/local.mk $(srcdir)/ft32/local.mk $(srcdir)/h8300/local.mk $(srcdir)/iq2000/local.mk $(srcdir)/lm32/local.mk $(srcdir)/m32c/local.mk $(srcdir)/m32r/local.mk $(srcdir)/m68hc11/local.mk $(srcdir)/mcore/local.mk $(srcdir)/microblaze/local.mk $(srcdir)/mips/local.mk $(srcdir)/mn10300/local.mk $(srcdir)/moxie/local.mk $(srcdir)/msp430/local.mk $(srcdir)/or1k/local.mk $(srcdir)/ppc/local.mk $(srcdir)/pru/local.mk $(srcdir)/riscv/local.mk $(srcdir)/rl78/local.mk $(srcdir)/rx/local.mk $(srcdir)/sh/local.mk $(srcdir)/v850/local.mk $(am__empty): 3264 3265$(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) 3266 $(SHELL) ./config.status --recheck 3267 3268$(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) 3269 $(am__cd) $(srcdir) && $(AUTOCONF) 3270$(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) 3271 $(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS) 3272$(am__aclocal_m4_deps): 3273 3274config.h: stamp-h1 3275 @test -f $@ || rm -f stamp-h1 3276 @test -f $@ || $(MAKE) $(AM_MAKEFLAGS) stamp-h1 3277 3278stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status 3279 @rm -f stamp-h1 3280 cd $(top_builddir) && $(SHELL) ./config.status config.h 3281$(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) 3282 ($(am__cd) $(top_srcdir) && $(AUTOHEADER)) 3283 rm -f stamp-h1 3284 touch $@ 3285 3286distclean-hdr: 3287 -rm -f config.h stamp-h1 3288aarch64/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3289 cd $(top_builddir) && $(SHELL) ./config.status $@ 3290arm/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3291 cd $(top_builddir) && $(SHELL) ./config.status $@ 3292avr/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3293 cd $(top_builddir) && $(SHELL) ./config.status $@ 3294bfin/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3295 cd $(top_builddir) && $(SHELL) ./config.status $@ 3296bpf/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3297 cd $(top_builddir) && $(SHELL) ./config.status $@ 3298cr16/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3299 cd $(top_builddir) && $(SHELL) ./config.status $@ 3300cris/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3301 cd $(top_builddir) && $(SHELL) ./config.status $@ 3302d10v/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3303 cd $(top_builddir) && $(SHELL) ./config.status $@ 3304frv/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3305 cd $(top_builddir) && $(SHELL) ./config.status $@ 3306ft32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3307 cd $(top_builddir) && $(SHELL) ./config.status $@ 3308h8300/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3309 cd $(top_builddir) && $(SHELL) ./config.status $@ 3310iq2000/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3311 cd $(top_builddir) && $(SHELL) ./config.status $@ 3312lm32/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3313 cd $(top_builddir) && $(SHELL) ./config.status $@ 3314m32c/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3315 cd $(top_builddir) && $(SHELL) ./config.status $@ 3316m32r/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3317 cd $(top_builddir) && $(SHELL) ./config.status $@ 3318m68hc11/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in 3319 cd $(top_builddir) && $(SHELL) ./config.status $@ 3320mcore/.gdbinit: $(top_builddir)/config.status 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4963.MAKE: all check check-am install install-am install-strip 4964 4965.PHONY: CTAGS GTAGS TAGS all all-am am--refresh check check-DEJAGNU \ 4966 check-TESTS check-am clean clean-checkPROGRAMS clean-cscope \ 4967 clean-generic clean-libtool clean-noinstLIBRARIES \ 4968 clean-noinstPROGRAMS cscope cscopelist-am ctags ctags-am \ 4969 distclean distclean-DEJAGNU distclean-compile \ 4970 distclean-generic distclean-hdr distclean-libtool \ 4971 distclean-tags dvi dvi-am html html-am info info-am install \ 4972 install-am install-armdocDATA install-data install-data-am \ 4973 install-data-local install-dtbDATA install-dvi install-dvi-am \ 4974 install-erc32docDATA install-exec install-exec-am \ 4975 install-exec-local install-frvdocDATA install-html \ 4976 install-html-am install-info install-info-am install-man \ 4977 install-or1kdocDATA install-pdf install-pdf-am \ 4978 install-pkgincludeHEADERS install-ppcdocDATA install-ps \ 4979 install-ps-am install-rxdocDATA install-strip installcheck \ 4980 installcheck-am installdirs maintainer-clean \ 4981 maintainer-clean-generic mostlyclean mostlyclean-compile \ 4982 mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ 4983 recheck tags tags-am uninstall uninstall-am \ 4984 uninstall-armdocDATA uninstall-dtbDATA uninstall-erc32docDATA \ 4985 uninstall-frvdocDATA uninstall-local uninstall-or1kdocDATA \ 4986 uninstall-pkgincludeHEADERS uninstall-ppcdocDATA \ 4987 uninstall-rxdocDATA 4988 4989.PRECIOUS: Makefile 4990 4991@am__include@ @am__quote@$(GNULIB_PARENT_DIR)/gnulib/Makefile.gnulib.inc@am__quote@ 4992 4993# Generate target constants for newlib/libgloss from its source tree. 4994# This file is shipped with distributions so we build in the source dir. 4995# Use `make nltvals' to rebuild. 4996.PHONY: nltvals 4997nltvals: 4998 $(srccom)/gennltvals.py --cpp "$(CPP)" 4999 5000common/version.c: common/version.c-stamp ; @true 5001common/version.c-stamp: $(srcroot)/gdb/version.in $(srcroot)/bfd/version.h $(srcdir)/common/create-version.sh 5002 $(AM_V_GEN)$(SHELL) $(srcdir)/common/create-version.sh $(srcroot)/gdb $@.tmp 5003 $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(@:-stamp=) 5004 $(AM_V_at)touch $@ 5005 5006.PRECIOUS: %/test-hw-events.o 5007%/test-hw-events.o: common/hw-events.c 5008 $(AM_V_CC)$(COMPILE) -DMAIN -c -o $@ $< 5009%/test-hw-events: %/test-hw-events.o %/libsim.a 5010 $(AM_V_CCLD)$(LINK) -o $@ $^ $(SIM_COMMON_LIBS) $(LIBS) 5011 5012# FIXME This is one very simple-minded way of generating the file hw-config.h. 5013%/hw-config.h: %/stamp-hw ; @true 5014%/stamp-hw: Makefile 5015 $(AM_V_GEN)set -e; \ 5016 ( \ 5017 sim_hw="$(SIM_HW_DEVICES) $($(@D)_SIM_EXTRA_HW_DEVICES)" ; \ 5018 echo "/* generated by Makefile */" ; \ 5019 printf "extern const struct hw_descriptor dv_%s_descriptor[];\n" $$sim_hw ; \ 5020 echo "const struct hw_descriptor * const hw_descriptors[] = {" ; \ 5021 printf " dv_%s_descriptor,\n" $$sim_hw ; \ 5022 echo " NULL," ; \ 5023 echo "};" \ 5024 ) > $@.tmp; \ 5025 $(SHELL) $(srcroot)/move-if-change $@.tmp $(@D)/hw-config.h; \ 5026 touch $@ 5027.PRECIOUS: %/stamp-hw 5028%/modules.c: %/stamp-modules ; @true 5029%/stamp-modules: Makefile 5030 $(AM_V_GEN)set -e; \ 5031 LANG=C ; export LANG; \ 5032 LC_ALL=C ; export LC_ALL; \ 5033 sed -n -e '/^sim_install_/{s/^\(sim_install_[a-z_0-9A-Z]*\).*/\1/;p}' $(GEN_MODULES_C_SRCS) | sort >$@.l-tmp; \ 5034 ( \ 5035 echo '/* Do not modify this file. */'; \ 5036 echo '/* It is created automatically by the Makefile. */'; \ 5037 echo '#include "libiberty.h"'; \ 5038 echo '#include "sim-module.h"'; \ 5039 sed -e 's:\(.*\):extern MODULE_INIT_FN \1;:' $@.l-tmp; \ 5040 echo 'MODULE_INSTALL_FN * const sim_modules_detected[] = {'; \ 5041 sed -e 's:\(.*\): \1,:' $@.l-tmp; \ 5042 echo '};'; \ 5043 echo 'const int sim_modules_detected_len = ARRAY_SIZE (sim_modules_detected);'; \ 5044 ) >$@.tmp; \ 5045 $(SHELL) $(srcroot)/move-if-change $@.tmp $(@D)/modules.c; \ 5046 rm -f $@.l-tmp; \ 5047 touch $@ 5048.PRECIOUS: %/stamp-modules 5049 5050# Alias for developers. 5051igen: $(IGEN) 5052 5053# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5054igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_libigen_a_DEPENDENCIES) $(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirstamp) 5055 $(AM_V_at)-rm -f $@ 5056 $(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(igen_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD) 5057 $(AM_V_at)$(RANLIB_FOR_BUILD) $@ 5058 5059igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_igen_DEPENDENCIES) igen/$(am__dirstamp) 5060 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(igen_igen_OBJECTS) $(igen_igen_LDADD) 5061 5062# igen is a build-time only tool. Override the default rules for it. 5063igen/%.o: igen/%.c 5064 $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5065 5066# Build some of the files in standalone mode for developers of igen itself. 5067igen/%-main.o: igen/%.c 5068 $(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@ 5069 5070site-sim-config.exp: Makefile 5071 $(AM_V_GEN)( \ 5072 echo "set SIM_PRIMARY_TARGET \"$(SIM_PRIMARY_TARGET)\""; \ 5073 echo "set builddir \"$(builddir)\""; \ 5074 echo "set srcdir \"$(srcdir)/testsuite\""; \ 5075 $(foreach V,$(SIM_TOOLCHAIN_VARS),echo "set $(V) \"$($(V))\"";) \ 5076 ) > $@ 5077 5078# Ignore dirs that only contain configuration settings. 5079check/./config/%.exp: ; @true 5080check/config/%.exp: ; @true 5081check/./lib/%.exp: ; @true 5082check/lib/%.exp: ; @true 5083 5084check/%.exp: 5085 $(AM_V_at)mkdir -p testsuite/$* 5086 $(AM_V_RUNTEST)$(DO_RUNTEST) --objdir testsuite/$* --outdir testsuite/$* $*.exp 5087 5088check-DEJAGNU-parallel: 5089 $(AM_V_at)( \ 5090 set -- `cd $(srcdir)/testsuite && find . -name '*.exp' -printf '%P\n' | sed 's:[.]exp$$::'`; \ 5091 $(MAKE) -k `printf 'check/%s.exp ' $$@`; \ 5092 ret=$$?; \ 5093 set -- `printf 'testsuite/%s/ ' $$@`; \ 5094 $(SHELL) $(srcroot)/contrib/dg-extract-results.sh \ 5095 `find $$@ -maxdepth 1 -name testrun.sum 2>/dev/null | sort` > testrun.sum; \ 5096 $(SHELL) $(srcroot)/contrib/dg-extract-results.sh -L \ 5097 `find $$@ -maxdepth 1 -name testrun.log 2>/dev/null | sort` > testrun.log; \ 5098 echo; \ 5099 $(SED) -n '/^.*===.*Summary.*===/,$$p' testrun.sum; \ 5100 exit $$ret) 5101 5102check-DEJAGNU-single: 5103 $(AM_V_RUNTEST)$(DO_RUNTEST) 5104 5105# If running a single job, invoking runtest once is faster & has nicer output. 5106check-DEJAGNU: site.exp 5107 $(AM_V_at)(set -e; \ 5108 EXPECT=${EXPECT} ; export EXPECT ; \ 5109 runtest=$(RUNTEST); \ 5110 if $(SHELL) -c "$$runtest --version" > /dev/null 2>&1; then \ 5111 case "$(MAKEFLAGS)" in \ 5112 *-j*) $(MAKE) check-DEJAGNU-parallel;; \ 5113 *) $(MAKE) check-DEJAGNU-single;; \ 5114 esac; \ 5115 else \ 5116 echo "WARNING: could not find \`runtest'" 1>&2; :;\ 5117 fi) 5118 5119# These tests are build-time only tools. Override the default rules for them. 5120testsuite/common/%.o: testsuite/common/%.c 5121 $(AM_V_CC)$(COMPILE_FOR_BUILD) $(testsuite_common_CPPFLAGS) -c $< -o $@ 5122 5123testsuite/common/alu-tst$(EXEEXT): $(testsuite_common_alu_tst_OBJECTS) $(testsuite_common_alu_tst_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5124 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_alu_tst_OBJECTS) $(testsuite_common_alu_tst_LDADD) 5125 5126testsuite/common/fpu-tst$(EXEEXT): $(testsuite_common_fpu_tst_OBJECTS) $(testsuite_common_fpu_tst_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5127 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_fpu_tst_OBJECTS) $(testsuite_common_fpu_tst_LDADD) 5128 5129testsuite/common/bits-gen$(EXEEXT): $(testsuite_common_bits_gen_OBJECTS) $(testsuite_common_bits_gen_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5130 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits_gen_OBJECTS) $(testsuite_common_bits_gen_LDADD) 5131 5132testsuite/common/bits32m0$(EXEEXT): $(testsuite_common_bits32m0_OBJECTS) $(testsuite_common_bits32m0_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5133 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits32m0_OBJECTS) $(testsuite_common_bits32m0_LDADD) 5134 5135testsuite/common/bits32m0.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c 5136 $(AM_V_GEN)$< 32 0 big > $@.tmp 5137 $(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp 5138 $(AM_V_at)mv $@.tmp $@ 5139 5140testsuite/common/bits32m31$(EXEEXT): $(testsuite_common_bits32m31_OBJECTS) $(testsuite_common_bits32m31_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5141 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits32m31_OBJECTS) $(testsuite_common_bits32m31_LDADD) 5142 5143testsuite/common/bits32m31.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c 5144 $(AM_V_GEN)$< 32 31 little > $@.tmp 5145 $(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp 5146 $(AM_V_at)mv $@.tmp $@ 5147 5148testsuite/common/bits64m0$(EXEEXT): $(testsuite_common_bits64m0_OBJECTS) $(testsuite_common_bits64m0_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5149 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits64m0_OBJECTS) $(testsuite_common_bits64m0_LDADD) 5150 5151testsuite/common/bits64m0.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c 5152 $(AM_V_GEN)$< 64 0 big > $@.tmp 5153 $(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp 5154 $(AM_V_at)mv $@.tmp $@ 5155 5156testsuite/common/bits64m63$(EXEEXT): $(testsuite_common_bits64m63_OBJECTS) $(testsuite_common_bits64m63_DEPENDENCIES) testsuite/common/$(am__dirstamp) 5157 $(AM_V_CCLD)$(LINK_FOR_BUILD) $(testsuite_common_bits64m63_OBJECTS) $(testsuite_common_bits64m63_LDADD) 5158 5159testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/common/bits-tst.c 5160 $(AM_V_GEN)$< 64 63 little > $@.tmp 5161 $(AM_V_at)cat $(srcdir)/testsuite/common/bits-tst.c >> $@.tmp 5162 $(AM_V_at)mv $@.tmp $@ 5163@SIM_ENABLE_ARCH_aarch64_TRUE@$(aarch64_libsim_a_OBJECTS) $(aarch64_libsim_a_LIBADD): aarch64/hw-config.h 5164 5165@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/modules.o: aarch64/modules.c 5166 5167@SIM_ENABLE_ARCH_aarch64_TRUE@aarch64/%.o: common/%.c ; $(SIM_COMPILE) 5168@SIM_ENABLE_ARCH_aarch64_TRUE@-@am__include@ aarch64/$(DEPDIR)/*.Po 5169@SIM_ENABLE_ARCH_arm_TRUE@$(arm_libsim_a_OBJECTS) $(arm_libsim_a_LIBADD): arm/hw-config.h 5170 5171@SIM_ENABLE_ARCH_arm_TRUE@arm/modules.o: arm/modules.c 5172 5173@SIM_ENABLE_ARCH_arm_TRUE@arm/%.o: common/%.c ; $(SIM_COMPILE) 5174@SIM_ENABLE_ARCH_arm_TRUE@-@am__include@ arm/$(DEPDIR)/*.Po 5175@SIM_ENABLE_ARCH_avr_TRUE@$(avr_libsim_a_OBJECTS) $(avr_libsim_a_LIBADD): avr/hw-config.h 5176 5177@SIM_ENABLE_ARCH_avr_TRUE@avr/modules.o: avr/modules.c 5178 5179@SIM_ENABLE_ARCH_avr_TRUE@avr/%.o: common/%.c ; $(SIM_COMPILE) 5180@SIM_ENABLE_ARCH_avr_TRUE@-@am__include@ avr/$(DEPDIR)/*.Po 5181@SIM_ENABLE_ARCH_bfin_TRUE@$(bfin_libsim_a_OBJECTS) $(bfin_libsim_a_LIBADD): bfin/hw-config.h 5182 5183@SIM_ENABLE_ARCH_bfin_TRUE@bfin/modules.o: bfin/modules.c 5184 5185@SIM_ENABLE_ARCH_bfin_TRUE@bfin/%.o: common/%.c ; $(SIM_COMPILE) 5186@SIM_ENABLE_ARCH_bfin_TRUE@-@am__include@ bfin/$(DEPDIR)/*.Po 5187 5188@SIM_ENABLE_ARCH_bfin_TRUE@bfin/linux-fixed-code.h: @MAINT@ $(srcdir)/bfin/linux-fixed-code.s bfin/local.mk bfin/$(am__dirstamp) 5189@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_GEN)$(AS_FOR_TARGET_BFIN) $(srcdir)/bfin/linux-fixed-code.s -o bfin/linux-fixed-code.o 5190@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)(\ 5191@SIM_ENABLE_ARCH_bfin_TRUE@ set -e; \ 5192@SIM_ENABLE_ARCH_bfin_TRUE@ echo "/* DO NOT EDIT: Autogenerated from linux-fixed-code.s. */"; \ 5193@SIM_ENABLE_ARCH_bfin_TRUE@ echo "static const unsigned char bfin_linux_fixed_code[] ="; \ 5194@SIM_ENABLE_ARCH_bfin_TRUE@ echo "{"; \ 5195@SIM_ENABLE_ARCH_bfin_TRUE@ $(OBJDUMP_FOR_TARGET_BFIN) -d -z bfin/linux-fixed-code.o > $@.dis; \ 5196@SIM_ENABLE_ARCH_bfin_TRUE@ sed -n \ 5197@SIM_ENABLE_ARCH_bfin_TRUE@ -e 's:^[^ ]* :0x:' \ 5198@SIM_ENABLE_ARCH_bfin_TRUE@ -e '/^0x/{s: .*::;s: *$$:,:;s: :, 0x:g;p;}' \ 5199@SIM_ENABLE_ARCH_bfin_TRUE@ $@.dis; \ 5200@SIM_ENABLE_ARCH_bfin_TRUE@ rm -f $@.dis; \ 5201@SIM_ENABLE_ARCH_bfin_TRUE@ echo "};" \ 5202@SIM_ENABLE_ARCH_bfin_TRUE@ ) > $@.tmp 5203@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/bfin/linux-fixed-code.h 5204@SIM_ENABLE_ARCH_bfin_TRUE@ $(AM_V_at)touch $(srcdir)/bfin/linux-fixed-code.h 5205@SIM_ENABLE_ARCH_bpf_TRUE@$(bpf_libsim_a_OBJECTS) $(bpf_libsim_a_LIBADD): bpf/hw-config.h 5206 5207@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.o: bpf/modules.c 5208 5209@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c ; $(SIM_COMPILE) 5210@SIM_ENABLE_ARCH_bpf_TRUE@-@am__include@ bpf/$(DEPDIR)/*.Po 5211@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h 5212 5213@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.o: cr16/modules.c 5214 5215@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c ; $(SIM_COMPILE) 5216@SIM_ENABLE_ARCH_cr16_TRUE@-@am__include@ cr16/$(DEPDIR)/*.Po 5217 5218@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.c: | $(cr16_BUILD_OUTPUTS) 5219 5220# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5221@SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode$(EXEEXT): $(cr16_gencode_OBJECTS) $(cr16_gencode_DEPENDENCIES) cr16/$(am__dirstamp) 5222@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(cr16_gencode_OBJECTS) $(cr16_gencode_LDADD) 5223 5224# gencode is a build-time only tool. Override the default rules for it. 5225@SIM_ENABLE_ARCH_cr16_TRUE@cr16/gencode.o: cr16/gencode.c 5226@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5227@SIM_ENABLE_ARCH_cr16_TRUE@cr16/cr16-opc.o: ../opcodes/cr16-opc.c 5228@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5229 5230@SIM_ENABLE_ARCH_cr16_TRUE@cr16/simops.h: cr16/gencode$(EXEEXT) 5231@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< -h >$@ 5232 5233@SIM_ENABLE_ARCH_cr16_TRUE@cr16/table.c: cr16/gencode$(EXEEXT) 5234@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@ 5235@SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h 5236 5237@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.o: cris/modules.c 5238 5239@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c ; $(SIM_COMPILE) 5240@SIM_ENABLE_ARCH_cris_TRUE@-@am__include@ cris/$(DEPDIR)/*.Po 5241 5242@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS) 5243 5244@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h: cris/stamp-mloop-v10f ; @true 5245@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: cris/mloop.in $(srccom)/genmloop.sh 5246@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5247@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv10f-switch.c \ 5248@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv10f -outfile-suffix -v10f 5249@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v10f.hin cris/engv10.h 5250@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v10f.cin cris/mloopv10f.c 5251@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@ 5252 5253@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv32f.c cris/engv32.h: cris/stamp-mloop-v32f ; @true 5254@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: cris/mloop.in $(srccom)/genmloop.sh 5255@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5256@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv32f-switch.c \ 5257@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv32f -outfile-suffix -v32f 5258@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v32f.hin cris/engv32.h 5259@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v32f.cin cris/mloopv32f.c 5260@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@ 5261 5262@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen: cris/cgen-arch cris/cgen-cpu-decode-v10f cris/cgen-cpu-decode-v32f 5263 5264@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-arch: 5265@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)mach=crisv10,crisv32 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) 5266@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/arch.h $(srcdir)/cris/arch.c $(srcdir)/cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch 5267 5268@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v10f: 5269@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5270@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv10-switch.c $(srcdir)/cris/semcrisv10f-switch.c 5271@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv10.h $(srcdir)/cris/cpuv10.c $(srcdir)/cris/semcrisv10f-switch.c $(srcdir)/cris/modelv10.c $(srcdir)/cris/decodev10.c $(srcdir)/cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f 5272 5273@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v32f: 5274@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5275@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv32-switch.c $(srcdir)/cris/semcrisv32f-switch.c 5276@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv32.h $(srcdir)/cris/cpuv32.c $(srcdir)/cris/semcrisv32f-switch.c $(srcdir)/cris/modelv32.c $(srcdir)/cris/decodev32.c $(srcdir)/cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f 5277@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD): d10v/hw-config.h 5278 5279@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.o: d10v/modules.c 5280 5281@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c ; $(SIM_COMPILE) 5282@SIM_ENABLE_ARCH_d10v_TRUE@-@am__include@ d10v/$(DEPDIR)/*.Po 5283 5284@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.c: | $(d10v_BUILD_OUTPUTS) 5285 5286# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5287@SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode$(EXEEXT): $(d10v_gencode_OBJECTS) $(d10v_gencode_DEPENDENCIES) d10v/$(am__dirstamp) 5288@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(d10v_gencode_OBJECTS) $(d10v_gencode_LDADD) 5289 5290# gencode is a build-time only tool. Override the default rules for it. 5291@SIM_ENABLE_ARCH_d10v_TRUE@d10v/gencode.o: d10v/gencode.c 5292@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5293@SIM_ENABLE_ARCH_d10v_TRUE@d10v/d10v-opc.o: ../opcodes/d10v-opc.c 5294@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5295 5296@SIM_ENABLE_ARCH_d10v_TRUE@d10v/simops.h: d10v/gencode$(EXEEXT) 5297@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< -h >$@ 5298 5299@SIM_ENABLE_ARCH_d10v_TRUE@d10v/table.c: d10v/gencode$(EXEEXT) 5300@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< >$@ 5301@SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD): erc32/hw-config.h 5302 5303@SIM_ENABLE_ARCH_erc32_TRUE@erc32/modules.o: erc32/modules.c 5304 5305@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c ; $(SIM_COMPILE) 5306@SIM_ENABLE_ARCH_erc32_TRUE@-@am__include@ erc32/$(DEPDIR)/*.Po 5307 5308@SIM_ENABLE_ARCH_erc32_TRUE@erc32/sis$(EXEEXT): erc32/run$(EXEEXT) 5309@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $< $@ 2>/dev/null || cp -p $< $@ 5310@SIM_ENABLE_ARCH_erc32_TRUE@sim-%D-install-exec-local: installdirs 5311@SIM_ENABLE_ARCH_erc32_TRUE@ $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir) 5312@SIM_ENABLE_ARCH_erc32_TRUE@ n=`echo sis | sed '$(program_transform_name)'`; \ 5313@SIM_ENABLE_ARCH_erc32_TRUE@ $(LIBTOOL) --mode=install $(INSTALL_PROGRAM) erc32/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT) 5314@SIM_ENABLE_ARCH_erc32_TRUE@sim-erc32-uninstall-local: 5315@SIM_ENABLE_ARCH_erc32_TRUE@ rm -f $(DESTDIR)$(bindir)/sis 5316@SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD): example-synacor/hw-config.h 5317 5318@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/modules.o: example-synacor/modules.c 5319 5320@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c ; $(SIM_COMPILE) 5321@SIM_ENABLE_ARCH_examples_TRUE@-@am__include@ example-synacor/$(DEPDIR)/*.Po 5322@SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): frv/hw-config.h 5323 5324@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.o: frv/modules.c 5325 5326@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c ; $(SIM_COMPILE) 5327@SIM_ENABLE_ARCH_frv_TRUE@-@am__include@ frv/$(DEPDIR)/*.Po 5328 5329@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS) 5330 5331@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true 5332@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: frv/mloop.in $(srccom)/genmloop.sh 5333@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5334@SIM_ENABLE_ARCH_frv_TRUE@ -mono -scache -parallel-generic-write -parallel-only \ 5335@SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf 5336@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/eng.hin frv/eng.h 5337@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c 5338@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@ 5339 5340@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen: frv/cgen-arch frv/cgen-cpu-decode 5341 5342@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch: 5343@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH) 5344@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/arch.h $(srcdir)/frv/arch.c $(srcdir)/frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch 5345 5346@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode: 5347@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE) 5348@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/cpu.h $(srcdir)/frv/sem.c $(srcdir)/frv/model.c $(srcdir)/frv/decode.c $(srcdir)/frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode 5349@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h 5350 5351@SIM_ENABLE_ARCH_ft32_TRUE@ft32/modules.o: ft32/modules.c 5352 5353@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c ; $(SIM_COMPILE) 5354@SIM_ENABLE_ARCH_ft32_TRUE@-@am__include@ ft32/$(DEPDIR)/*.Po 5355@SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h 5356 5357@SIM_ENABLE_ARCH_h8300_TRUE@h8300/modules.o: h8300/modules.c 5358 5359@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c ; $(SIM_COMPILE) 5360@SIM_ENABLE_ARCH_h8300_TRUE@-@am__include@ h8300/$(DEPDIR)/*.Po 5361@SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h 5362 5363@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.o: iq2000/modules.c 5364 5365@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c ; $(SIM_COMPILE) 5366@SIM_ENABLE_ARCH_iq2000_TRUE@-@am__include@ iq2000/$(DEPDIR)/*.Po 5367 5368@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS) 5369 5370@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true 5371@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: iq2000/mloop.in $(srccom)/genmloop.sh 5372@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5373@SIM_ENABLE_ARCH_iq2000_TRUE@ -mono -fast -pbb -switch sem-switch.c \ 5374@SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf 5375@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/eng.hin iq2000/eng.h 5376@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/mloop.cin iq2000/mloop.c 5377@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)touch $@ 5378 5379@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen: iq2000/cgen-arch iq2000/cgen-cpu-decode 5380 5381@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-arch: 5382@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)mach=iq2000 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) 5383@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/arch.h $(srcdir)/iq2000/arch.c $(srcdir)/iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch 5384 5385@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode: 5386@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5387@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/cpu.h $(srcdir)/iq2000/sem.c $(srcdir)/iq2000/sem-switch.c $(srcdir)/iq2000/model.c $(srcdir)/iq2000/decode.c $(srcdir)/iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode 5388@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h 5389 5390@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.o: lm32/modules.c 5391 5392@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c ; $(SIM_COMPILE) 5393@SIM_ENABLE_ARCH_lm32_TRUE@-@am__include@ lm32/$(DEPDIR)/*.Po 5394 5395@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS) 5396 5397@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true 5398@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: lm32/mloop.in $(srccom)/genmloop.sh 5399@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5400@SIM_ENABLE_ARCH_lm32_TRUE@ -mono -fast -pbb -switch sem-switch.c \ 5401@SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf 5402@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/eng.hin lm32/eng.h 5403@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/mloop.cin lm32/mloop.c 5404@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)touch $@ 5405 5406@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen: lm32/cgen-arch lm32/cgen-cpu-decode 5407 5408@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-arch: 5409@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) 5410@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/arch.h $(srcdir)/lm32/arch.c $(srcdir)/lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch 5411 5412@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode: 5413@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5414@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/cpu.h $(srcdir)/lm32/sem.c $(srcdir)/lm32/sem-switch.c $(srcdir)/lm32/model.c $(srcdir)/lm32/decode.c $(srcdir)/lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode 5415@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h 5416 5417@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.o: m32c/modules.c 5418 5419@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c ; $(SIM_COMPILE) 5420@SIM_ENABLE_ARCH_m32c_TRUE@-@am__include@ m32c/$(DEPDIR)/*.Po 5421 5422@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.c: | $(m32c_BUILD_OUTPUTS) 5423 5424# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5425@SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c$(EXEEXT): $(m32c_opc2c_OBJECTS) $(m32c_opc2c_DEPENDENCIES) m32c/$(am__dirstamp) 5426@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(m32c_opc2c_OBJECTS) $(m32c_opc2c_LDADD) 5427 5428# opc2c is a build-time only tool. Override the default rules for it. 5429@SIM_ENABLE_ARCH_m32c_TRUE@m32c/opc2c.o: m32c/opc2c.c 5430@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5431 5432@SIM_ENABLE_ARCH_m32c_TRUE@m32c/m32c.c: m32c/m32c.opc m32c/opc2c$(EXEEXT) 5433@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp 5434@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ 5435 5436@SIM_ENABLE_ARCH_m32c_TRUE@m32c/r8c.c: m32c/r8c.opc m32c/opc2c$(EXEEXT) 5437@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_GEN)$(m32c_OPC2C_RUN) -l $@.log $< > $@.tmp 5438@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@ 5439@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h 5440 5441@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.o: m32r/modules.c 5442 5443@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c ; $(SIM_COMPILE) 5444@SIM_ENABLE_ARCH_m32r_TRUE@-@am__include@ m32r/$(DEPDIR)/*.Po 5445 5446@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS) 5447 5448@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true 5449@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: m32r/mloop.in $(srccom)/genmloop.sh 5450@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5451@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -fast -pbb -switch sem-switch.c \ 5452@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf 5453@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng.hin m32r/eng.h 5454@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop.cin m32r/mloop.c 5455@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ 5456 5457@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop-x ; @true 5458@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: m32r/mloopx.in $(srccom)/genmloop.sh 5459@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5460@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch semx-switch.c \ 5461@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf -outfile-suffix x 5462@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/engx.hin m32r/engx.h 5463@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloopx.cin m32r/mloopx.c 5464@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ 5465 5466@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop-2 ; @true 5467@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: m32r/mloop2.in $(srccom)/genmloop.sh 5468@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5469@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \ 5470@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f -outfile-suffix 2 5471@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng2.hin m32r/eng2.h 5472@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop2.cin m32r/mloop2.c 5473@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@ 5474 5475@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen: m32r/cgen-arch m32r/cgen-cpu-decode m32r/cgen-cpu-decode-x m32r/cgen-cpu-decode-2 5476 5477@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-arch: 5478@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH) 5479@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/arch.h $(srcdir)/m32r/arch.c $(srcdir)/m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch 5480 5481@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode: 5482@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rbf mach=m32r FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5483@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu.h $(srcdir)/m32r/sem.c $(srcdir)/m32r/sem-switch.c $(srcdir)/m32r/model.c $(srcdir)/m32r/decode.c $(srcdir)/m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode 5484 5485@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-x: 5486@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5487@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpux.h $(srcdir)/m32r/semx-switch.c $(srcdir)/m32r/modelx.c $(srcdir)/m32r/decodex.c $(srcdir)/m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x 5488 5489@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2: 5490@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5491@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu2.h $(srcdir)/m32r/sem2-switch.c $(srcdir)/m32r/model2.c $(srcdir)/m32r/decode2.c $(srcdir)/m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2 5492@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h 5493 5494@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.o: m68hc11/modules.c 5495 5496@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c ; $(SIM_COMPILE) 5497@SIM_ENABLE_ARCH_m68hc11_TRUE@-@am__include@ m68hc11/$(DEPDIR)/*.Po 5498 5499@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.c: | $(m68hc11_BUILD_OUTPUTS) 5500 5501# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5502@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode$(EXEEXT): $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_DEPENDENCIES) m68hc11/$(am__dirstamp) 5503@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(m68hc11_gencode_OBJECTS) $(m68hc11_gencode_LDADD) 5504 5505# gencode is a build-time only tool. Override the default rules for it. 5506@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/gencode.o: m68hc11/gencode.c 5507@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5508 5509@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc11int.c: m68hc11/gencode$(EXEEXT) 5510@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6811 >$@ 5511 5512@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/m68hc12int.c: m68hc11/gencode$(EXEEXT) 5513@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@ 5514@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h 5515 5516@SIM_ENABLE_ARCH_mcore_TRUE@mcore/modules.o: mcore/modules.c 5517 5518@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c ; $(SIM_COMPILE) 5519@SIM_ENABLE_ARCH_mcore_TRUE@-@am__include@ mcore/$(DEPDIR)/*.Po 5520@SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h 5521 5522@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/modules.o: microblaze/modules.c 5523 5524@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c ; $(SIM_COMPILE) 5525@SIM_ENABLE_ARCH_microblaze_TRUE@-@am__include@ microblaze/$(DEPDIR)/*.Po 5526@SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h 5527 5528@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.o: mips/modules.c 5529 5530@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c ; $(SIM_COMPILE) 5531@SIM_ENABLE_ARCH_mips_TRUE@-@am__include@ mips/$(DEPDIR)/*.Po 5532 5533@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.c: | $(mips_BUILD_OUTPUTS) 5534 5535@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_IGEN_ITABLE): mips/stamp-igen-itable 5536@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE): mips/stamp-gen-mode-single 5537@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16): mips/stamp-gen-mode-m16-m16 5538@SIM_ENABLE_ARCH_mips_TRUE@$(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32): mips/stamp-gen-mode-m16-m32 5539@SIM_ENABLE_ARCH_mips_TRUE@$(SIM_MIPS_MULTI_SRC): mips/stamp-gen-mode-multi-igen mips/stamp-gen-mode-multi-run 5540 5541@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-igen-itable: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(IGEN) 5542@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5543@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ 5544@SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ 5545@SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ 5546@SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ 5547@SIM_ENABLE_ARCH_mips_TRUE@ -Wnowidth \ 5548@SIM_ENABLE_ARCH_mips_TRUE@ -Wnounimplemented \ 5549@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_IGEN_ITABLE_FLAGS) \ 5550@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ 5551@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ 5552@SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ 5553@SIM_ENABLE_ARCH_mips_TRUE@ -n itable.h -ht mips/itable.h \ 5554@SIM_ENABLE_ARCH_mips_TRUE@ -n itable.c -t mips/itable.c 5555@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5556 5557@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-single: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN) 5558@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5559@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ 5560@SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ 5561@SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ 5562@SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ 5563@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_SINGLE_FLAGS) \ 5564@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ 5565@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ 5566@SIM_ENABLE_ARCH_mips_TRUE@ -B 32 \ 5567@SIM_ENABLE_ARCH_mips_TRUE@ -H 31 \ 5568@SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ 5569@SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_IGEN_DC) \ 5570@SIM_ENABLE_ARCH_mips_TRUE@ -x \ 5571@SIM_ENABLE_ARCH_mips_TRUE@ -n icache.h -hc mips/icache.h \ 5572@SIM_ENABLE_ARCH_mips_TRUE@ -n icache.c -c mips/icache.c \ 5573@SIM_ENABLE_ARCH_mips_TRUE@ -n semantics.h -hs mips/semantics.h \ 5574@SIM_ENABLE_ARCH_mips_TRUE@ -n semantics.c -s mips/semantics.c \ 5575@SIM_ENABLE_ARCH_mips_TRUE@ -n idecode.h -hd mips/idecode.h \ 5576@SIM_ENABLE_ARCH_mips_TRUE@ -n idecode.c -d mips/idecode.c \ 5577@SIM_ENABLE_ARCH_mips_TRUE@ -n model.h -hm mips/model.h \ 5578@SIM_ENABLE_ARCH_mips_TRUE@ -n model.c -m mips/model.c \ 5579@SIM_ENABLE_ARCH_mips_TRUE@ -n support.h -hf mips/support.h \ 5580@SIM_ENABLE_ARCH_mips_TRUE@ -n support.c -f mips/support.c \ 5581@SIM_ENABLE_ARCH_mips_TRUE@ -n engine.h -he mips/engine.h \ 5582@SIM_ENABLE_ARCH_mips_TRUE@ -n engine.c -e mips/engine.c \ 5583@SIM_ENABLE_ARCH_mips_TRUE@ -n irun.c -r mips/irun.c 5584@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5585 5586@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m16: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_M16_DC) $(IGEN) 5587@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5588@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ 5589@SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ 5590@SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ 5591@SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ 5592@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_M16_FLAGS) \ 5593@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ 5594@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ 5595@SIM_ENABLE_ARCH_mips_TRUE@ -B 16 \ 5596@SIM_ENABLE_ARCH_mips_TRUE@ -H 15 \ 5597@SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ 5598@SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_M16_DC) \ 5599@SIM_ENABLE_ARCH_mips_TRUE@ -P m16_ \ 5600@SIM_ENABLE_ARCH_mips_TRUE@ -x \ 5601@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_icache.h -hc mips/m16_icache.h \ 5602@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_icache.c -c mips/m16_icache.c \ 5603@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_semantics.h -hs mips/m16_semantics.h \ 5604@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_semantics.c -s mips/m16_semantics.c \ 5605@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_idecode.h -hd mips/m16_idecode.h \ 5606@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_idecode.c -d mips/m16_idecode.c \ 5607@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_model.h -hm mips/m16_model.h \ 5608@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_model.c -m mips/m16_model.c \ 5609@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_support.h -hf mips/m16_support.h \ 5610@SIM_ENABLE_ARCH_mips_TRUE@ -n m16_support.c -f mips/m16_support.c 5611@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5612 5613@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-m16-m32: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(IGEN) 5614@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5615@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ 5616@SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ 5617@SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ 5618@SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ 5619@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_SINGLE_FLAGS) \ 5620@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ 5621@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ 5622@SIM_ENABLE_ARCH_mips_TRUE@ -B 32 \ 5623@SIM_ENABLE_ARCH_mips_TRUE@ -H 31 \ 5624@SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ 5625@SIM_ENABLE_ARCH_mips_TRUE@ -o $(mips_IGEN_DC) \ 5626@SIM_ENABLE_ARCH_mips_TRUE@ -P m32_ \ 5627@SIM_ENABLE_ARCH_mips_TRUE@ -x \ 5628@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_icache.h -hc mips/m32_icache.h \ 5629@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_icache.c -c mips/m32_icache.c \ 5630@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_semantics.h -hs mips/m32_semantics.h \ 5631@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_semantics.c -s mips/m32_semantics.c \ 5632@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_idecode.h -hd mips/m32_idecode.h \ 5633@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_idecode.c -d mips/m32_idecode.c \ 5634@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_model.h -hm mips/m32_model.h \ 5635@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_model.c -m mips/m32_model.c \ 5636@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_support.h -hf mips/m32_support.h \ 5637@SIM_ENABLE_ARCH_mips_TRUE@ -n m32_support.c -f mips/m32_support.c 5638@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5639 5640@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-igen: $(mips_IGEN_INSN) $(mips_IGEN_INSN_INC) $(mips_IGEN_DC) $(mips_M16_DC) $(mips_MICROMIPS32_DC) $(mips_MICROMIPS16_DC) $(IGEN) 5641@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)\ 5642@SIM_ENABLE_ARCH_mips_TRUE@ for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ 5643@SIM_ENABLE_ARCH_mips_TRUE@ p=`echo $${t} | sed -e 's/:.*//'` ; \ 5644@SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \ 5645@SIM_ENABLE_ARCH_mips_TRUE@ f=`echo $${t} | sed -e 's/.*://'` ; \ 5646@SIM_ENABLE_ARCH_mips_TRUE@ case $${p} in \ 5647@SIM_ENABLE_ARCH_mips_TRUE@ micromips16*) \ 5648@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 16 -H 15 -o $(mips_MICROMIPS16_DC) -F 16" ;; \ 5649@SIM_ENABLE_ARCH_mips_TRUE@ micromips32* | micromips64*) \ 5650@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_MICROMIPS32_DC) -F $${f}" ;; \ 5651@SIM_ENABLE_ARCH_mips_TRUE@ micromips_m32*) \ 5652@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \ 5653@SIM_ENABLE_ARCH_mips_TRUE@ m="mips32r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \ 5654@SIM_ENABLE_ARCH_mips_TRUE@ micromips_m64*) \ 5655@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}"; \ 5656@SIM_ENABLE_ARCH_mips_TRUE@ m="mips64r2,mips3d,mdmx,dsp,dsp2,smartmips" ;; \ 5657@SIM_ENABLE_ARCH_mips_TRUE@ m16*) \ 5658@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 16 -H 15 -o $(mips_M16_DC) -F 16" ;; \ 5659@SIM_ENABLE_ARCH_mips_TRUE@ *) \ 5660@SIM_ENABLE_ARCH_mips_TRUE@ e="-B 32 -H 31 -o $(mips_IGEN_DC) -F $${f}" ;; \ 5661@SIM_ENABLE_ARCH_mips_TRUE@ esac; \ 5662@SIM_ENABLE_ARCH_mips_TRUE@ $(IGEN_RUN) \ 5663@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_IGEN_TRACE) \ 5664@SIM_ENABLE_ARCH_mips_TRUE@ $${e} \ 5665@SIM_ENABLE_ARCH_mips_TRUE@ -I $(srcdir)/mips \ 5666@SIM_ENABLE_ARCH_mips_TRUE@ -Werror \ 5667@SIM_ENABLE_ARCH_mips_TRUE@ -Wnodiscard \ 5668@SIM_ENABLE_ARCH_mips_TRUE@ -M $${m} \ 5669@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-direct-access \ 5670@SIM_ENABLE_ARCH_mips_TRUE@ -G gen-zero-r0 \ 5671@SIM_ENABLE_ARCH_mips_TRUE@ -i $(mips_IGEN_INSN) \ 5672@SIM_ENABLE_ARCH_mips_TRUE@ -P $${p}_ \ 5673@SIM_ENABLE_ARCH_mips_TRUE@ -x \ 5674@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_icache.h -hc mips/$${p}_icache.h \ 5675@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_icache.c -c mips/$${p}_icache.c \ 5676@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_semantics.h -hs mips/$${p}_semantics.h \ 5677@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_semantics.c -s mips/$${p}_semantics.c \ 5678@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_idecode.h -hd mips/$${p}_idecode.h \ 5679@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_idecode.c -d mips/$${p}_idecode.c \ 5680@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_model.h -hm mips/$${p}_model.h \ 5681@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_model.c -m mips/$${p}_model.c \ 5682@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_support.h -hf mips/$${p}_support.h \ 5683@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_support.c -f mips/$${p}_support.c \ 5684@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_engine.h -he mips/$${p}_engine.h \ 5685@SIM_ENABLE_ARCH_mips_TRUE@ -n $${p}_engine.c -e mips/$${p}_engine.c \ 5686@SIM_ENABLE_ARCH_mips_TRUE@ || exit; \ 5687@SIM_ENABLE_ARCH_mips_TRUE@ done 5688@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5689 5690@SIM_ENABLE_ARCH_mips_TRUE@mips/stamp-gen-mode-multi-run: mips/m16run.c mips/micromipsrun.c 5691@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_GEN)\ 5692@SIM_ENABLE_ARCH_mips_TRUE@ for t in $(SIM_MIPS_MULTI_IGEN_CONFIGS); do \ 5693@SIM_ENABLE_ARCH_mips_TRUE@ case $${t} in \ 5694@SIM_ENABLE_ARCH_mips_TRUE@ m16*) \ 5695@SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \ 5696@SIM_ENABLE_ARCH_mips_TRUE@ o=mips/m16$${m}_run.c; \ 5697@SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/m16run.c > $$o.tmp \ 5698@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/m16$${m}_/" \ 5699@SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/m16$${m}_engine/" \ 5700@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m16_/m16$${m}_/" \ 5701@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m32$${m}_/" \ 5702@SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ 5703@SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ 5704@SIM_ENABLE_ARCH_mips_TRUE@ ;;\ 5705@SIM_ENABLE_ARCH_mips_TRUE@ micromips32*) \ 5706@SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^micromips32//' -e 's/:.*//'`; \ 5707@SIM_ENABLE_ARCH_mips_TRUE@ o=mips/micromips$${m}_run.c; \ 5708@SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \ 5709@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/micromips32$${m}_/" \ 5710@SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/micromips32$${m}_engine/" \ 5711@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips16_/micromips16$${m}_/" \ 5712@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips32_/micromips32$${m}_/" \ 5713@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m32$${m}_/" \ 5714@SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ 5715@SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ 5716@SIM_ENABLE_ARCH_mips_TRUE@ ;;\ 5717@SIM_ENABLE_ARCH_mips_TRUE@ micromips64*) \ 5718@SIM_ENABLE_ARCH_mips_TRUE@ m=`echo $${t} | sed -e 's/^micromips64//' -e 's/:.*//'`; \ 5719@SIM_ENABLE_ARCH_mips_TRUE@ o=mips/micromips$${m}_run.c; \ 5720@SIM_ENABLE_ARCH_mips_TRUE@ sed < $(srcdir)/mips/micromipsrun.c > $$o.tmp \ 5721@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/^sim_/micromips64$${m}_/" \ 5722@SIM_ENABLE_ARCH_mips_TRUE@ -e "/include/s/sim-engine/micromips64$${m}_engine/" \ 5723@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips16_/micromips16$${m}_/" \ 5724@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/micromips32_/micromips64$${m}_/" \ 5725@SIM_ENABLE_ARCH_mips_TRUE@ -e "s/m32_/m64$${m}_/" \ 5726@SIM_ENABLE_ARCH_mips_TRUE@ || exit 1; \ 5727@SIM_ENABLE_ARCH_mips_TRUE@ $(SHELL) $(srcroot)/move-if-change $$o.tmp $$o; \ 5728@SIM_ENABLE_ARCH_mips_TRUE@ ;;\ 5729@SIM_ENABLE_ARCH_mips_TRUE@ esac \ 5730@SIM_ENABLE_ARCH_mips_TRUE@ done 5731@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@ 5732@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD): mn10300/hw-config.h 5733 5734@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.o: mn10300/modules.c 5735 5736@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c ; $(SIM_COMPILE) 5737@SIM_ENABLE_ARCH_mn10300_TRUE@-@am__include@ mn10300/$(DEPDIR)/*.Po 5738 5739@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.c: | $(mn10300_BUILD_OUTPUTS) 5740 5741@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_BUILT_SRC_FROM_IGEN): mn10300/stamp-igen 5742@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/stamp-igen: $(mn10300_IGEN_INSN) $(mn10300_IGEN_INSN_INC) $(mn10300_IGEN_DC) $(IGEN) 5743@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5744@SIM_ENABLE_ARCH_mn10300_TRUE@ $(mn10300_IGEN_TRACE) \ 5745@SIM_ENABLE_ARCH_mn10300_TRUE@ -G gen-direct-access \ 5746@SIM_ENABLE_ARCH_mn10300_TRUE@ -M mn10300,am33 -G gen-multi-sim=am33 \ 5747@SIM_ENABLE_ARCH_mn10300_TRUE@ -M am33_2 \ 5748@SIM_ENABLE_ARCH_mn10300_TRUE@ -I $(srcdir)/mn10300 \ 5749@SIM_ENABLE_ARCH_mn10300_TRUE@ -i $(mn10300_IGEN_INSN) \ 5750@SIM_ENABLE_ARCH_mn10300_TRUE@ -o $(mn10300_IGEN_DC) \ 5751@SIM_ENABLE_ARCH_mn10300_TRUE@ -x \ 5752@SIM_ENABLE_ARCH_mn10300_TRUE@ -n icache.h -hc mn10300/icache.h \ 5753@SIM_ENABLE_ARCH_mn10300_TRUE@ -n icache.c -c mn10300/icache.c \ 5754@SIM_ENABLE_ARCH_mn10300_TRUE@ -n semantics.h -hs mn10300/semantics.h \ 5755@SIM_ENABLE_ARCH_mn10300_TRUE@ -n semantics.c -s mn10300/semantics.c \ 5756@SIM_ENABLE_ARCH_mn10300_TRUE@ -n idecode.h -hd mn10300/idecode.h \ 5757@SIM_ENABLE_ARCH_mn10300_TRUE@ -n idecode.c -d mn10300/idecode.c \ 5758@SIM_ENABLE_ARCH_mn10300_TRUE@ -n model.h -hm mn10300/model.h \ 5759@SIM_ENABLE_ARCH_mn10300_TRUE@ -n model.c -m mn10300/model.c \ 5760@SIM_ENABLE_ARCH_mn10300_TRUE@ -n support.h -hf mn10300/support.h \ 5761@SIM_ENABLE_ARCH_mn10300_TRUE@ -n support.c -f mn10300/support.c \ 5762@SIM_ENABLE_ARCH_mn10300_TRUE@ -n itable.h -ht mn10300/itable.h \ 5763@SIM_ENABLE_ARCH_mn10300_TRUE@ -n itable.c -t mn10300/itable.c \ 5764@SIM_ENABLE_ARCH_mn10300_TRUE@ -n engine.h -he mn10300/engine.h \ 5765@SIM_ENABLE_ARCH_mn10300_TRUE@ -n engine.c -e mn10300/engine.c \ 5766@SIM_ENABLE_ARCH_mn10300_TRUE@ -n irun.c -r mn10300/irun.c 5767@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)touch $@ 5768@SIM_ENABLE_ARCH_moxie_TRUE@$(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD): moxie/hw-config.h 5769 5770@SIM_ENABLE_ARCH_moxie_TRUE@moxie/modules.o: moxie/modules.c 5771 5772@SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: common/%.c ; $(SIM_COMPILE) 5773@SIM_ENABLE_ARCH_moxie_TRUE@-@am__include@ moxie/$(DEPDIR)/*.Po 5774 5775@SIM_ENABLE_ARCH_moxie_TRUE@moxie/moxie-gdb.dtb: @MAINT@ moxie/moxie-gdb.dts moxie/$(am__dirstamp) 5776@SIM_ENABLE_ARCH_moxie_TRUE@ $(AM_V_GEN) \ 5777@SIM_ENABLE_ARCH_moxie_TRUE@ if test "x$(DTC)" != x; then \ 5778@SIM_ENABLE_ARCH_moxie_TRUE@ $(DTC) -O dtb -o $@.tmp ${srcdir}/moxie/moxie-gdb.dts || exit 1; \ 5779@SIM_ENABLE_ARCH_moxie_TRUE@ $(SHELL) $(srcroot)/move-if-change $@.tmp ${srcdir}/moxie/moxie-gdb.dtb || exit 1; \ 5780@SIM_ENABLE_ARCH_moxie_TRUE@ touch ${srcdir}/moxie/moxie-gdb.dtb; \ 5781@SIM_ENABLE_ARCH_moxie_TRUE@ else \ 5782@SIM_ENABLE_ARCH_moxie_TRUE@ echo "Could not update the moxie-gdb.dtb file because the device "; \ 5783@SIM_ENABLE_ARCH_moxie_TRUE@ echo "tree compiler tool (dtc) is missing. Install the tool to "; \ 5784@SIM_ENABLE_ARCH_moxie_TRUE@ echo "update the device tree blob."; \ 5785@SIM_ENABLE_ARCH_moxie_TRUE@ fi 5786@SIM_ENABLE_ARCH_msp430_TRUE@$(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD): msp430/hw-config.h 5787 5788@SIM_ENABLE_ARCH_msp430_TRUE@msp430/modules.o: msp430/modules.c 5789 5790@SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: common/%.c ; $(SIM_COMPILE) 5791@SIM_ENABLE_ARCH_msp430_TRUE@-@am__include@ msp430/$(DEPDIR)/*.Po 5792@SIM_ENABLE_ARCH_or1k_TRUE@$(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD): or1k/hw-config.h 5793 5794@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.o: or1k/modules.c 5795 5796@SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c ; $(SIM_COMPILE) 5797@SIM_ENABLE_ARCH_or1k_TRUE@-@am__include@ or1k/$(DEPDIR)/*.Po 5798 5799@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS) 5800 5801@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true 5802@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: or1k/mloop.in $(srccom)/genmloop.sh 5803@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \ 5804@SIM_ENABLE_ARCH_or1k_TRUE@ -mono -fast -pbb -switch sem-switch.c \ 5805@SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf 5806@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/eng.hin or1k/eng.h 5807@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/mloop.cin or1k/mloop.c 5808@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)touch $@ 5809 5810@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen: or1k/cgen-arch or1k/cgen-cpu-decode 5811 5812@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-arch: 5813@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)mach=or32,or32nd FLAGS="with-scache"; $(CGEN_GEN_ARCH) 5814@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/arch.h $(srcdir)/or1k/arch.c $(srcdir)/or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch 5815 5816@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-cpu-decode: 5817@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)cpu=or1k32bf mach=or32,or32nd FLAGS="with-scache" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE) 5818@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/cpu.h $(srcdir)/or1k/cpu.c $(srcdir)/or1k/model.c $(srcdir)/or1k/sem.c $(srcdir)/or1k/sem-switch.c $(srcdir)/or1k/decode.c $(srcdir)/or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode 5819 5820@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: common/%.c ; $(SIM_COMPILE) 5821@SIM_ENABLE_ARCH_ppc_TRUE@-@am__include@ ppc/$(DEPDIR)/*.Po 5822 5823@SIM_ENABLE_ARCH_ppc_TRUE@ppc/defines.h: ppc/stamp-defines ; @true 5824@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-defines: config.h Makefile 5825@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(SED) -n -e '/^#define HAVE_.*1$$/{ s/ 1$$/",/; s/.* HAVE_/"HAVE_/; p }' < config.h > ppc/defines.hin 5826@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/defines.hin ppc/defines.h 5827@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@ 5828 5829@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.c: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp) 5830@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --source $@.tmp 5831@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.c 5832@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.c 5833 5834@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.h: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp) 5835@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp 5836@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h 5837@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h 5838 5839@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_BUILT_SRC_FROM_IGEN): ppc/stamp-igen 5840@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-igen: ppc/powerpc.igen ppc/altivec.igen ppc/e500.igen $(ppc_IGEN_OPCODE_RULES) $(PPC_IGEN) 5841@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(PPC_IGEN_RUN) \ 5842@SIM_ENABLE_ARCH_ppc_TRUE@ -o $(srcdir)/$(ppc_IGEN_OPCODE_RULES) \ 5843@SIM_ENABLE_ARCH_ppc_TRUE@ -I $(srcdir)/ppc -i $(srcdir)/ppc/powerpc.igen \ 5844@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.h -hc ppc/icache.h \ 5845@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.c -c ppc/icache.c \ 5846@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.h -hs ppc/semantics.h \ 5847@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.c -s ppc/semantics.c \ 5848@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.h -hd ppc/idecode.h \ 5849@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.c -d ppc/idecode.c \ 5850@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.h -ht ppc/itable.h \ 5851@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.c -t ppc/itable.c \ 5852@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.h -hm ppc/model.h \ 5853@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.c -m ppc/model.c \ 5854@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.h -hf ppc/support.h \ 5855@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.c -f ppc/support.c 5856@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@ 5857 5858@SIM_ENABLE_ARCH_ppc_TRUE@ppc/libigen.a: $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_DEPENDENCIES) $(EXTRA_ppc_libigen_a_DEPENDENCIES) ppc/$(am__dirstamp) 5859@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)-rm -f $@ 5860@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_LIBADD) 5861@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(RANLIB_FOR_BUILD) $@ 5862 5863@SIM_ENABLE_ARCH_ppc_TRUE@ppc/igen$(EXEEXT): $(ppc_igen_OBJECTS) $(ppc_igen_DEPENDENCIES) ppc/$(am__dirstamp) 5864@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(ppc_igen_OBJECTS) $(ppc_igen_LDADD) 5865 5866@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_libigen_a_OBJECTS) $(ppc_igen_OBJECTS): ppc/%.o: ppc/%.c 5867@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -I$(srcdir)/igen -I$(srcdir)/ppc -c $< -o $@ 5868 5869@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%-main.o: ppc/%.c 5870@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@ 5871@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-hw ; @true 5872@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-hw: Makefile $(ppc_HW_SRC) $(srcroot)/move-if-change 5873@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)\ 5874@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \ 5875@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \ 5876@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \ 5877@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \ 5878@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \ 5879@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \ 5880@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \ 5881@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \ 5882@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \ 5883@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern const device_descriptor /' \ 5884@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor\[\];/' \ 5885@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.hin; \ 5886@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \ 5887@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \ 5888@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \ 5889@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \ 5890@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \ 5891@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \ 5892@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \ 5893@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \ 5894@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \ 5895@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/ /' \ 5896@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor,/' \ 5897@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.cin 5898@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.hin ppc/hw.h 5899@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.cin ppc/hw.c 5900@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@ 5901@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-igen 5902@SIM_ENABLE_ARCH_ppc_TRUE@$(srcdir)/ppc/pk.h: @MAINT@ ppc/stamp-pk ; @true 5903@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-pk: $(srcdir)/ppc/local.mk $(ppc_PACKAGE_SRC) $(srcroot)/move-if-change 5904@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)echo "/* Generated file by local.mk; do not edit. */" > ppc/pk.hin; \ 5905@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \ 5906@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_PACKAGE_SRC) ; do \ 5907@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \ 5908@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \ 5909@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \ 5910@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \ 5911@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \ 5912@SIM_ENABLE_ARCH_ppc_TRUE@ for pk in $$f ; do echo $$pk ; done \ 5913@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*pk_\(.*\)\.c/\1/' \ 5914@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern package_create_instance_callback pk_/' \ 5915@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_create_instance;/' \ 5916@SIM_ENABLE_ARCH_ppc_TRUE@ >> ppc/pk.hin 5917@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/pk.hin $(srcdir)/ppc/pk.h 5918@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@ 5919@SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): pru/hw-config.h 5920 5921@SIM_ENABLE_ARCH_pru_TRUE@pru/modules.o: pru/modules.c 5922 5923@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c ; $(SIM_COMPILE) 5924@SIM_ENABLE_ARCH_pru_TRUE@-@am__include@ pru/$(DEPDIR)/*.Po 5925@SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD): riscv/hw-config.h 5926 5927@SIM_ENABLE_ARCH_riscv_TRUE@riscv/modules.o: riscv/modules.c 5928 5929@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c ; $(SIM_COMPILE) 5930@SIM_ENABLE_ARCH_riscv_TRUE@-@am__include@ riscv/$(DEPDIR)/*.Po 5931@SIM_ENABLE_ARCH_rl78_TRUE@$(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD): rl78/hw-config.h 5932 5933@SIM_ENABLE_ARCH_rl78_TRUE@rl78/modules.o: rl78/modules.c 5934 5935@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: common/%.c ; $(SIM_COMPILE) 5936@SIM_ENABLE_ARCH_rl78_TRUE@-@am__include@ rl78/$(DEPDIR)/*.Po 5937@SIM_ENABLE_ARCH_rx_TRUE@$(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD): rx/hw-config.h 5938 5939@SIM_ENABLE_ARCH_rx_TRUE@rx/modules.o: rx/modules.c 5940 5941@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: common/%.c ; $(SIM_COMPILE) 5942@SIM_ENABLE_ARCH_rx_TRUE@-@am__include@ rx/$(DEPDIR)/*.Po 5943@SIM_ENABLE_ARCH_sh_TRUE@$(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD): sh/hw-config.h 5944 5945@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.o: sh/modules.c 5946 5947@SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c ; $(SIM_COMPILE) 5948@SIM_ENABLE_ARCH_sh_TRUE@-@am__include@ sh/$(DEPDIR)/*.Po 5949 5950@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.c: | $(sh_BUILD_OUTPUTS) 5951 5952# These rules are copied from automake, but tweaked to use FOR_BUILD variables. 5953@SIM_ENABLE_ARCH_sh_TRUE@sh/gencode$(EXEEXT): $(sh_gencode_OBJECTS) $(sh_gencode_DEPENDENCIES) sh/$(am__dirstamp) 5954@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(sh_gencode_OBJECTS) $(sh_gencode_LDADD) 5955 5956# gencode is a build-time only tool. Override the default rules for it. 5957@SIM_ENABLE_ARCH_sh_TRUE@sh/gencode.o: sh/gencode.c 5958@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -c $< -o $@ 5959 5960@SIM_ENABLE_ARCH_sh_TRUE@sh/code.c: sh/gencode$(EXEEXT) 5961@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -x >$@ 5962 5963@SIM_ENABLE_ARCH_sh_TRUE@sh/ppi.c: sh/gencode$(EXEEXT) 5964@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -p >$@ 5965 5966@SIM_ENABLE_ARCH_sh_TRUE@sh/table.c: sh/gencode$(EXEEXT) 5967@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -s >$@ 5968@SIM_ENABLE_ARCH_v850_TRUE@$(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD): v850/hw-config.h 5969 5970@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.o: v850/modules.c 5971 5972@SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c ; $(SIM_COMPILE) 5973@SIM_ENABLE_ARCH_v850_TRUE@-@am__include@ v850/$(DEPDIR)/*.Po 5974 5975@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.c: | $(v850_BUILD_OUTPUTS) 5976 5977@SIM_ENABLE_ARCH_v850_TRUE@$(v850_BUILT_SRC_FROM_IGEN): v850/stamp-igen 5978@SIM_ENABLE_ARCH_v850_TRUE@v850/stamp-igen: $(v850_IGEN_INSN) $(v850_IGEN_DC) $(IGEN) 5979@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_GEN)$(IGEN_RUN) \ 5980@SIM_ENABLE_ARCH_v850_TRUE@ $(v850_IGEN_TRACE) \ 5981@SIM_ENABLE_ARCH_v850_TRUE@ -G gen-direct-access \ 5982@SIM_ENABLE_ARCH_v850_TRUE@ -G gen-zero-r0 \ 5983@SIM_ENABLE_ARCH_v850_TRUE@ -i $(v850_IGEN_INSN) \ 5984@SIM_ENABLE_ARCH_v850_TRUE@ -o $(v850_IGEN_DC) \ 5985@SIM_ENABLE_ARCH_v850_TRUE@ -x \ 5986@SIM_ENABLE_ARCH_v850_TRUE@ -n icache.h -hc v850/icache.h \ 5987@SIM_ENABLE_ARCH_v850_TRUE@ -n icache.c -c v850/icache.c \ 5988@SIM_ENABLE_ARCH_v850_TRUE@ -n semantics.h -hs v850/semantics.h \ 5989@SIM_ENABLE_ARCH_v850_TRUE@ -n semantics.c -s v850/semantics.c \ 5990@SIM_ENABLE_ARCH_v850_TRUE@ -n idecode.h -hd v850/idecode.h \ 5991@SIM_ENABLE_ARCH_v850_TRUE@ -n idecode.c -d v850/idecode.c \ 5992@SIM_ENABLE_ARCH_v850_TRUE@ -n model.h -hm v850/model.h \ 5993@SIM_ENABLE_ARCH_v850_TRUE@ -n model.c -m v850/model.c \ 5994@SIM_ENABLE_ARCH_v850_TRUE@ -n support.h -hf v850/support.h \ 5995@SIM_ENABLE_ARCH_v850_TRUE@ -n support.c -f v850/support.c \ 5996@SIM_ENABLE_ARCH_v850_TRUE@ -n itable.h -ht v850/itable.h \ 5997@SIM_ENABLE_ARCH_v850_TRUE@ -n itable.c -t v850/itable.c \ 5998@SIM_ENABLE_ARCH_v850_TRUE@ -n engine.h -he v850/engine.h \ 5999@SIM_ENABLE_ARCH_v850_TRUE@ -n engine.c -e v850/engine.c \ 6000@SIM_ENABLE_ARCH_v850_TRUE@ -n irun.c -r v850/irun.c 6001@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)touch $@ 6002 6003install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS) 6004 $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(libdir) 6005 lib=`echo sim | sed '$(program_transform_name)'`; \ 6006 for d in $(SIM_ENABLED_ARCHES); do \ 6007 n="$$lib"; \ 6008 [ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \ 6009 n="lib$$n.a"; \ 6010 $(INSTALL_DATA) $$d/libsim.a $(DESTDIR)$(libdir)/$$n || exit 1; \ 6011 done 6012 6013install-exec-local: installdirs $(SIM_INSTALL_EXEC_LOCAL_DEPS) 6014 $(AM_V_at)$(MKDIR_P) $(DESTDIR)$(bindir) 6015 run=`echo run | sed '$(program_transform_name)'`; \ 6016 for d in $(SIM_ENABLED_ARCHES); do \ 6017 n="$$run"; \ 6018 [ "$(SIM_PRIMARY_TARGET)" = "$$d" ] || n="$$n-$$d"; \ 6019 $(LIBTOOL) --mode=install \ 6020 $(INSTALL_PROGRAM) $$d/run$(EXEEXT) $(DESTDIR)$(bindir)/$$n$(EXEEXT) || exit 1; \ 6021 done 6022 6023uninstall-local: $(SIM_UNINSTALL_LOCAL_DEPS) 6024 rm -f $(DESTDIR)$(bindir)/run $(DESTDIR)$(libdir)/libsim.a 6025 for d in $(SIM_ENABLED_ARCHES); do \ 6026 rm -f $(DESTDIR)$(bindir)/run-$$d $(DESTDIR)$(libdir)/libsim-$$d.a; \ 6027 done 6028 6029# Tell versions [3.59,3.63) of GNU make to not export all variables. 6030# Otherwise a system limit (for SysV at least) may be exceeded. 6031.NOEXPORT: 6032