xref: /netbsd-src/external/gpl3/gdb/dist/opcodes/sparc-opc.c (revision 413d532bcc3f62d122e56d92e13ac64825a40baf)
1 /* Table of opcodes for the sparc.
2    Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3    2000, 2002, 2004, 2005, 2006, 2007, 2008, 2011, 2012
4    Free Software Foundation, Inc.
5 
6    This file is part of the GNU opcodes library.
7 
8    This library is free software; you can redistribute it and/or modify
9    it under the terms of the GNU General Public License as published by
10    the Free Software Foundation; either version 3, or (at your option)
11    any later version.
12 
13    It is distributed in the hope that it will be useful, but WITHOUT
14    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
16    License for more details.
17 
18    You should have received a copy of the GNU General Public License
19    along with this file; see the file COPYING.  If not, write to the
20    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
21    MA 02110-1301, USA.  */
22 
23 
24 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
25    instruction's name rather than the args.  This would make gas faster, pinsn
26    slower, but would mess up some macros a bit.  xoxorich. */
27 
28 #include "sysdep.h"
29 #include <stdio.h>
30 #include "opcode/sparc.h"
31 
32 /* Some defines to make life easy.  */
33 #define MASK_V6		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
34 #define MASK_V7		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
35 #define MASK_V8		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
36 #define MASK_SPARCLET	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
37 #define MASK_SPARCLITE	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
38 #define MASK_V9		SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
39 #define MASK_V9A	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
40 #define MASK_V9B	SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
41 
42 /* Bit masks of architectures supporting the insn.  */
43 
44 #define v6		(MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
45 			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
46 /* v6 insns not supported on the sparclet.  */
47 #define v6notlet	(MASK_V6 | MASK_V7 | MASK_V8 \
48 			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
49 #define v7		(MASK_V7 | MASK_V8 | MASK_SPARCLET \
50 			 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
51 /* Although not all insns are implemented in hardware, sparclite is defined
52    to be a superset of v8.  Unimplemented insns trap and are then theoretically
53    implemented in software.
54    It's not clear that the same is true for sparclet, although the docs
55    suggest it is.  Rather than complicating things, the sparclet assembler
56    recognizes all v8 insns.  */
57 #define v8		(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
58 			 | MASK_V9 | MASK_V9A | MASK_V9B)
59 #define sparclet	(MASK_SPARCLET)
60 #define sparclite	(MASK_SPARCLITE)
61 #define v9		(MASK_V9 | MASK_V9A | MASK_V9B)
62 #define v9a		(MASK_V9A | MASK_V9B)
63 #define v9b		(MASK_V9B)
64 /* v6 insns not supported by v9.  */
65 #define v6notv9		(MASK_V6 | MASK_V7 | MASK_V8 \
66 			 | MASK_SPARCLET | MASK_SPARCLITE)
67 /* v9a instructions which would appear to be aliases to v9's impdep's
68    otherwise.  */
69 #define v9notv9a	(MASK_V9)
70 
71 /* Table of opcode architectures.
72    The order is defined in opcode/sparc.h.  */
73 
74 const struct sparc_opcode_arch sparc_opcode_archs[] =
75 {
76   { "v6", MASK_V6 },
77   { "v7", MASK_V6 | MASK_V7 },
78   { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
79   { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
80   { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
81   /* ??? Don't some v8 priviledged insns conflict with v9?  */
82   { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
83   /* v9 with ultrasparc additions */
84   { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
85   /* v9 with cheetah additions */
86   { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
87   { NULL, 0 }
88 };
89 
90 /* Given NAME, return it's architecture entry.  */
91 
92 enum sparc_opcode_arch_val
93 sparc_opcode_lookup_arch (const char *name)
94 {
95   const struct sparc_opcode_arch *p;
96 
97   for (p = &sparc_opcode_archs[0]; p->name; ++p)
98     if (strcmp (name, p->name) == 0)
99       return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]);
100 
101   return SPARC_OPCODE_ARCH_BAD;
102 }
103 
104 /* Branch condition field.  */
105 #define COND(x)		(((x) & 0xf) << 25)
106 
107 /* Compare And Branch condition field.  */
108 #define CBCOND(x)	(((x) & 0x1f) << 25)
109 
110 /* v9: Move (MOVcc and FMOVcc) condition field.  */
111 #define MCOND(x,i_or_f)	((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
112 
113 /* v9: Move register (MOVRcc and FMOVRcc) condition field.  */
114 #define RCOND(x)	(((x) & 0x7) << 10)	/* v9 */
115 
116 #define CONDA	(COND (0x8))
117 #define CONDCC	(COND (0xd))
118 #define CONDCS	(COND (0x5))
119 #define CONDE	(COND (0x1))
120 #define CONDG	(COND (0xa))
121 #define CONDGE	(COND (0xb))
122 #define CONDGU	(COND (0xc))
123 #define CONDL	(COND (0x3))
124 #define CONDLE	(COND (0x2))
125 #define CONDLEU	(COND (0x4))
126 #define CONDN	(COND (0x0))
127 #define CONDNE	(COND (0x9))
128 #define CONDNEG	(COND (0x6))
129 #define CONDPOS	(COND (0xe))
130 #define CONDVC	(COND (0xf))
131 #define CONDVS	(COND (0x7))
132 
133 #define CONDNZ	CONDNE
134 #define CONDZ	CONDE
135 #define CONDGEU	CONDCC
136 #define CONDLU	CONDCS
137 
138 #define FCONDA		(COND (0x8))
139 #define FCONDE		(COND (0x9))
140 #define FCONDG		(COND (0x6))
141 #define FCONDGE		(COND (0xb))
142 #define FCONDL		(COND (0x4))
143 #define FCONDLE		(COND (0xd))
144 #define FCONDLG		(COND (0x2))
145 #define FCONDN		(COND (0x0))
146 #define FCONDNE		(COND (0x1))
147 #define FCONDO		(COND (0xf))
148 #define FCONDU		(COND (0x7))
149 #define FCONDUE		(COND (0xa))
150 #define FCONDUG		(COND (0x5))
151 #define FCONDUGE	(COND (0xc))
152 #define FCONDUL		(COND (0x3))
153 #define FCONDULE	(COND (0xe))
154 
155 #define FCONDNZ	FCONDNE
156 #define FCONDZ	FCONDE
157 
158 #define ICC 		(0)	/* v9 */
159 #define XCC 		(1 << 12) /* v9 */
160 #define CBCOND_XCC	(1 << 21)
161 #define FCC(x)		(((x) & 0x3) << 11) /* v9 */
162 #define FBFCC(x)	(((x) & 0x3) << 20)	/* v9 */
163 
164 /* The order of the opcodes in the table is significant:
165 
166 	* The assembler requires that all instances of the same mnemonic must
167 	be consecutive.	If they aren't, the assembler will bomb at runtime.
168 
169 	* The disassembler should not care about the order of the opcodes.  */
170 
171 /* Entries for commutative arithmetic operations.  */
172 /* ??? More entries can make use of this.  */
173 #define COMMUTEOP(opcode, op3, arch_mask) \
174 { opcode,	F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0),	"1,2,d", 0, 0, arch_mask }, \
175 { opcode,	F3(2, op3, 1), F3(~2, ~op3, ~1),		"1,i,d", 0, 0, arch_mask }, \
176 { opcode,	F3(2, op3, 1), F3(~2, ~op3, ~1),		"i,1,d", 0, 0, arch_mask }
177 
178 const struct sparc_opcode sparc_opcodes[] = {
179 
180 { "ld",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0),		"[1+2],d", 0, 0, v6 },
181 { "ld",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,	"[1],d", 0, 0, v6 }, /* ld [rs1+%g0],d */
182 { "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[1+i],d", 0, 0, v6 },
183 { "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[i+1],d", 0, 0, v6 },
184 { "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
185 { "ld",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ld [rs1+0],d */
186 { "ld",	F3(3, 0x20, 0), F3(~3, ~0x20, ~0),		"[1+2],g", 0, 0, v6 },
187 { "ld",	F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0,	"[1],g", 0, 0, v6 }, /* ld [rs1+%g0],d */
188 { "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1),		"[1+i],g", 0, 0, v6 },
189 { "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1),		"[i+1],g", 0, 0, v6 },
190 { "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0,	"[i],g", 0, 0, v6 },
191 { "ld",	F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0),	"[1],g", 0, 0, v6 }, /* ld [rs1+0],d */
192 
193 { "ld",	F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0),	"[1+2],F", 0, 0, v6 },
194 { "ld",	F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+%g0],d */
195 { "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),	"[1+i],F", 0, 0, v6 },
196 { "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0),	"[i+1],F", 0, 0, v6 },
197 { "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, v6 },
198 { "ld",	F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, v6 }, /* ld [rs1+0],d */
199 
200 { "ld",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0),		"[1+2],D", 0, 0, v6notv9 },
201 { "ld",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,	"[1],D", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
202 { "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[1+i],D", 0, 0, v6notv9 },
203 { "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[i+1],D", 0, 0, v6notv9 },
204 { "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,	"[i],D", 0, 0, v6notv9 },
205 { "ld",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),	"[1],D", 0, 0, v6notv9 }, /* ld [rs1+0],d */
206 { "ld",	F3(3, 0x31, 0), F3(~3, ~0x31, ~0),		"[1+2],C", 0, 0, v6notv9 },
207 { "ld",	F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0,	"[1],C", 0, 0, v6notv9 }, /* ld [rs1+%g0],d */
208 { "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1),		"[1+i],C", 0, 0, v6notv9 },
209 { "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1),		"[i+1],C", 0, 0, v6notv9 },
210 { "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0,	"[i],C", 0, 0, v6notv9 },
211 { "ld",	F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0),	"[1],C", 0, 0, v6notv9 }, /* ld [rs1+0],d */
212 
213 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
214    'ld' pseudo-op in v9.  */
215 { "lduw",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0),		"[1+2],d", F_ALIAS, 0, v9 },
216 { "lduw",	F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0,	"[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+%g0],d */
217 { "lduw",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[1+i],d", F_ALIAS, 0, v9 },
218 { "lduw",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1),		"[i+1],d", F_ALIAS, 0, v9 },
219 { "lduw",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0,	"[i],d", F_ALIAS, 0, v9 },
220 { "lduw",	F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0),	"[1],d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
221 
222 { "ldd",	F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
223 { "ldd",	F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* ldd [rs1+%g0],d */
224 { "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1),		"[1+i],d", 0, 0, v6 },
225 { "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1),		"[i+1],d", 0, 0, v6 },
226 { "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
227 { "ldd",	F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ldd [rs1+0],d */
228 { "ldd",	F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0),	"[1+2],H", 0, 0, v6 },
229 { "ldd",	F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0),	"[1],H", 0, 0, v6 }, /* ldd [rs1+%g0],d */
230 { "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1),		"[1+i],H", 0, 0, v6 },
231 { "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1),		"[i+1],H", 0, 0, v6 },
232 { "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0,	"[i],H", 0, 0, v6 },
233 { "ldd",	F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0),	"[1],H", 0, 0, v6 }, /* ldd [rs1+0],d */
234 
235 { "ldd",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0),	"[1+2],D", 0, 0, v6notv9 },
236 { "ldd",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0),	"[1],D", 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */
237 { "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[1+i],D", 0, 0, v6notv9 },
238 { "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[i+1],D", 0, 0, v6notv9 },
239 { "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,	"[i],D", 0, 0, v6notv9 },
240 { "ldd",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),	"[1],D", 0, 0, v6notv9 }, /* ldd [rs1+0],d */
241 
242 { "ldq",	F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0),	"[1+2],J", 0, 0, v9 },
243 { "ldq",	F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0),	"[1],J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
244 { "ldq",	F3(3, 0x22, 1), F3(~3, ~0x22, ~1),		"[1+i],J", 0, 0, v9 },
245 { "ldq",	F3(3, 0x22, 1), F3(~3, ~0x22, ~1),		"[i+1],J", 0, 0, v9 },
246 { "ldq",	F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0,	"[i],J", 0, 0, v9 },
247 { "ldq",	F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0),	"[1],J", 0, 0, v9 }, /* ldd [rs1+0],d */
248 
249 { "ldsb",	F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
250 { "ldsb",	F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* ldsb [rs1+%g0],d */
251 { "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1),		"[1+i],d", 0, 0, v6 },
252 { "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1),		"[i+1],d", 0, 0, v6 },
253 { "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
254 { "ldsb",	F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ldsb [rs1+0],d */
255 
256 { "ldsh",	F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* ldsh [rs1+%g0],d */
257 { "ldsh",	F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
258 { "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),		"[1+i],d", 0, 0, v6 },
259 { "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1),		"[i+1],d", 0, 0, v6 },
260 { "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
261 { "ldsh",	F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ldsh [rs1+0],d */
262 
263 { "ldstub",	F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
264 { "ldstub",	F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* ldstub [rs1+%g0],d */
265 { "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),		"[1+i],d", 0, 0, v6 },
266 { "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1),		"[i+1],d", 0, 0, v6 },
267 { "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
268 { "ldstub",	F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ldstub [rs1+0],d */
269 
270 { "ldsw",	F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0),	"[1+2],d", 0, 0, v9 },
271 { "ldsw",	F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v9 }, /* ldsw [rs1+%g0],d */
272 { "ldsw",	F3(3, 0x08, 1), F3(~3, ~0x08, ~1),		"[1+i],d", 0, 0, v9 },
273 { "ldsw",	F3(3, 0x08, 1), F3(~3, ~0x08, ~1),		"[i+1],d", 0, 0, v9 },
274 { "ldsw",	F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0,	"[i],d", 0, 0, v9 },
275 { "ldsw",	F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0),	"[1],d", 0, 0, v9 }, /* ldsw [rs1+0],d */
276 
277 { "ldub",	F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
278 { "ldub",	F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* ldub [rs1+%g0],d */
279 { "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1),		"[1+i],d", 0, 0, v6 },
280 { "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1),		"[i+1],d", 0, 0, v6 },
281 { "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
282 { "ldub",	F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* ldub [rs1+0],d */
283 
284 { "lduh",	F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0),	"[1+2],d", 0, 0, v6 },
285 { "lduh",	F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v6 }, /* lduh [rs1+%g0],d */
286 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1),		"[1+i],d", 0, 0, v6 },
287 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1),		"[i+1],d", 0, 0, v6 },
288 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0,	"[i],d", 0, 0, v6 },
289 { "lduh",	F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0),	"[1],d", 0, 0, v6 }, /* lduh [rs1+0],d */
290 
291 { "ldx",	F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0),	"[1+2],d", 0, 0, v9 },
292 { "ldx",	F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v9 }, /* ldx [rs1+%g0],d */
293 { "ldx",	F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),		"[1+i],d", 0, 0, v9 },
294 { "ldx",	F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1),		"[i+1],d", 0, 0, v9 },
295 { "ldx",	F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0,	"[i],d", 0, 0, v9 },
296 { "ldx",	F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0),	"[1],d", 0, 0, v9 }, /* ldx [rs1+0],d */
297 
298 { "ldx",	F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1),	"[1+2],F", 0, 0, v9 },
299 { "ldx",	F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1),	"[1],F", 0, 0, v9 }, /* ld [rs1+%g0],d */
300 { "ldx",	F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1),	"[1+i],F", 0, 0, v9 },
301 { "ldx",	F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1),	"[i+1],F", 0, 0, v9 },
302 { "ldx",	F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1),	"[i],F", 0, 0, v9 },
303 { "ldx",	F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, v9 }, /* ld [rs1+0],d */
304 
305 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, 0, v9b },
306 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, 0, v9b },
307 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, 0, v9b },
308 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, 0, v9b },
309 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, 0, v9b },
310 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, 0, v9b },
311 
312 { "lda",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0),		"[1+2]A,d", 0, 0, v6 },
313 { "lda",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* lda [rs1+%g0],d */
314 { "lda",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1),		"[1+i]o,d", 0, 0, v9 },
315 { "lda",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1),		"[i+1]o,d", 0, 0, v9 },
316 { "lda",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
317 { "lda",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
318 { "lda",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0),		"[1+2]A,g", 0, 0, v9 },
319 { "lda",	F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0,	"[1]A,g", 0, 0, v9 }, /* lda [rs1+%g0],d */
320 { "lda",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[1+i]o,g", 0, 0, v9 },
321 { "lda",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1),		"[i+1]o,g", 0, 0, v9 },
322 { "lda",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0,	"[i]o,g", 0, 0, v9 },
323 { "lda",	F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0),	"[1]o,g", 0, 0, v9 }, /* ld [rs1+0],d */
324 
325 { "ldda",	F3(3, 0x13, 0), F3(~3, ~0x13, ~0),		"[1+2]A,d", 0, 0, v6 },
326 { "ldda",	F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* ldda [rs1+%g0],d */
327 { "ldda",	F3(3, 0x13, 1), F3(~3, ~0x13, ~1),		"[1+i]o,d", 0, 0, v9 },
328 { "ldda",	F3(3, 0x13, 1), F3(~3, ~0x13, ~1),		"[i+1]o,d", 0, 0, v9 },
329 { "ldda",	F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
330 { "ldda",	F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
331 
332 { "ldda",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0),		"[1+2]A,H", 0, 0, v9 },
333 { "ldda",	F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0,	"[1]A,H", 0, 0, v9 }, /* ldda [rs1+%g0],d */
334 { "ldda",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[1+i]o,H", 0, 0, v9 },
335 { "ldda",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1),		"[i+1]o,H", 0, 0, v9 },
336 { "ldda",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0,	"[i]o,H", 0, 0, v9 },
337 { "ldda",	F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0),	"[1]o,H", 0, 0, v9 }, /* ld [rs1+0],d */
338 
339 { "ldqa",	F3(3, 0x32, 0), F3(~3, ~0x32, ~0),		"[1+2]A,J", 0, 0, v9 },
340 { "ldqa",	F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0,	"[1]A,J", 0, 0, v9 }, /* ldd [rs1+%g0],d */
341 { "ldqa",	F3(3, 0x32, 1), F3(~3, ~0x32, ~1),		"[1+i]o,J", 0, 0, v9 },
342 { "ldqa",	F3(3, 0x32, 1), F3(~3, ~0x32, ~1),		"[i+1]o,J", 0, 0, v9 },
343 { "ldqa",	F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0,	"[i]o,J", 0, 0, v9 },
344 { "ldqa",	F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0),	"[1]o,J", 0, 0, v9 }, /* ldd [rs1+0],d */
345 
346 { "ldsba",	F3(3, 0x19, 0), F3(~3, ~0x19, ~0),		"[1+2]A,d", 0, 0, v6 },
347 { "ldsba",	F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* ldsba [rs1+%g0],d */
348 { "ldsba",	F3(3, 0x19, 1), F3(~3, ~0x19, ~1),		"[1+i]o,d", 0, 0, v9 },
349 { "ldsba",	F3(3, 0x19, 1), F3(~3, ~0x19, ~1),		"[i+1]o,d", 0, 0, v9 },
350 { "ldsba",	F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
351 { "ldsba",	F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
352 
353 { "ldsha",	F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0),		"[1+2]A,d", 0, 0, v6 },
354 { "ldsha",	F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* ldsha [rs1+%g0],d */
355 { "ldsha",	F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),		"[1+i]o,d", 0, 0, v9 },
356 { "ldsha",	F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1),		"[i+1]o,d", 0, 0, v9 },
357 { "ldsha",	F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
358 { "ldsha",	F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
359 
360 { "ldstuba",	F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0),		"[1+2]A,d", 0, 0, v6 },
361 { "ldstuba",	F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* ldstuba [rs1+%g0],d */
362 { "ldstuba",	F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),		"[1+i]o,d", 0, 0, v9 },
363 { "ldstuba",	F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1),		"[i+1]o,d", 0, 0, v9 },
364 { "ldstuba",	F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
365 { "ldstuba",	F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
366 
367 { "ldswa",	F3(3, 0x18, 0), F3(~3, ~0x18, ~0),		"[1+2]A,d", 0, 0, v9 },
368 { "ldswa",	F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0,	"[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
369 { "ldswa",	F3(3, 0x18, 1), F3(~3, ~0x18, ~1),		"[1+i]o,d", 0, 0, v9 },
370 { "ldswa",	F3(3, 0x18, 1), F3(~3, ~0x18, ~1),		"[i+1]o,d", 0, 0, v9 },
371 { "ldswa",	F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
372 { "ldswa",	F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
373 
374 { "lduba",	F3(3, 0x11, 0), F3(~3, ~0x11, ~0),		"[1+2]A,d", 0, 0, v6 },
375 { "lduba",	F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* lduba [rs1+%g0],d */
376 { "lduba",	F3(3, 0x11, 1), F3(~3, ~0x11, ~1),		"[1+i]o,d", 0, 0, v9 },
377 { "lduba",	F3(3, 0x11, 1), F3(~3, ~0x11, ~1),		"[i+1]o,d", 0, 0, v9 },
378 { "lduba",	F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
379 { "lduba",	F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
380 
381 { "lduha",	F3(3, 0x12, 0), F3(~3, ~0x12, ~0),		"[1+2]A,d", 0, 0, v6 },
382 { "lduha",	F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0,	"[1]A,d", 0, 0, v6 }, /* lduha [rs1+%g0],d */
383 { "lduha",	F3(3, 0x12, 1), F3(~3, ~0x12, ~1),		"[1+i]o,d", 0, 0, v9 },
384 { "lduha",	F3(3, 0x12, 1), F3(~3, ~0x12, ~1),		"[i+1]o,d", 0, 0, v9 },
385 { "lduha",	F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
386 { "lduha",	F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
387 
388 { "lduwa",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0),		"[1+2]A,d", F_ALIAS, 0, v9 }, /* lduwa === lda */
389 { "lduwa",	F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0,	"[1]A,d", F_ALIAS, 0, v9 }, /* lda [rs1+%g0],d */
390 { "lduwa",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1),		"[1+i]o,d", F_ALIAS, 0, v9 },
391 { "lduwa",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1),		"[i+1]o,d", F_ALIAS, 0, v9 },
392 { "lduwa",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0,	"[i]o,d", F_ALIAS, 0, v9 },
393 { "lduwa",	F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0),	"[1]o,d", F_ALIAS, 0, v9 }, /* ld [rs1+0],d */
394 
395 { "ldxa",	F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0),		"[1+2]A,d", 0, 0, v9 },
396 { "ldxa",	F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0,	"[1]A,d", 0, 0, v9 }, /* lda [rs1+%g0],d */
397 { "ldxa",	F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),		"[1+i]o,d", 0, 0, v9 },
398 { "ldxa",	F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1),		"[i+1]o,d", 0, 0, v9 },
399 { "ldxa",	F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
400 { "ldxa",	F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* ld [rs1+0],d */
401 
402 { "st",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),		"d,[1+2]", 0, 0, v6 },
403 { "st",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),		"d,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
404 { "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),			"d,[1+i]", 0, 0, v6 },
405 { "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),			"d,[i+1]", 0, 0, v6 },
406 { "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,		"d,[i]", 0, 0, v6 },
407 { "st",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),		"d,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
408 { "st",	F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0),		"g,[1+2]", 0, 0, v6 },
409 { "st",	F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0),		"g,[1]", 0, 0, v6 }, /* st d[rs1+%g0] */
410 { "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1),			"g,[1+i]", 0, 0, v6 },
411 { "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1),			"g,[i+1]", 0, 0, v6 },
412 { "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0,		"g,[i]", 0, 0, v6 },
413 { "st",	F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0),		"g,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
414 
415 { "st",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0),		"D,[1+2]", 0, 0, v6notv9 },
416 { "st",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0),		"D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
417 { "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),			"D,[1+i]", 0, 0, v6notv9 },
418 { "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),			"D,[i+1]", 0, 0, v6notv9 },
419 { "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,		"D,[i]", 0, 0, v6notv9 },
420 { "st",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),		"D,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
421 { "st",	F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0),		"C,[1+2]", 0, 0, v6notv9 },
422 { "st",	F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0),		"C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+%g0] */
423 { "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1),			"C,[1+i]", 0, 0, v6notv9 },
424 { "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1),			"C,[i+1]", 0, 0, v6notv9 },
425 { "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0,		"C,[i]", 0, 0, v6notv9 },
426 { "st",	F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0),		"C,[1]", 0, 0, v6notv9 }, /* st d,[rs1+0] */
427 
428 { "st",	F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0),	"F,[1+2]", 0, 0, v6 },
429 { "st",	F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0),	"F,[1]", 0, 0, v6 }, /* st d,[rs1+%g0] */
430 { "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,		"F,[1+i]", 0, 0, v6 },
431 { "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0,		"F,[i+1]", 0, 0, v6 },
432 { "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0,		"F,[i]", 0, 0, v6 },
433 { "st",	F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0),	"F,[1]", 0, 0, v6 }, /* st d,[rs1+0] */
434 
435 { "stw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v9 },
436 { "stw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
437 { "stw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[1+i]", F_ALIAS, 0, v9 },
438 { "stw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[i+1]", F_ALIAS, 0, v9 },
439 { "stw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v9 },
440 { "stw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
441 { "stsw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v9 },
442 { "stsw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
443 { "stsw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[1+i]", F_ALIAS, 0, v9 },
444 { "stsw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[i+1]", F_ALIAS, 0, v9 },
445 { "stsw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v9 },
446 { "stsw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
447 { "stuw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v9 },
448 { "stuw",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+%g0] */
449 { "stuw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[1+i]", F_ALIAS, 0, v9 },
450 { "stuw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[i+1]", F_ALIAS, 0, v9 },
451 { "stuw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v9 },
452 { "stuw",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
453 
454 { "spill",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
455 { "spill",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+%g0] */
456 { "spill",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
457 { "spill",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
458 { "spill",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
459 { "spill",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* st d,[rs1+0] */
460 
461 { "sta",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0),		"d,[1+2]A", 0, 0, v6 },
462 { "sta",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),	"d,[1]A", 0, 0, v6 }, /* sta d,[rs1+%g0] */
463 { "sta",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[1+i]o", 0, 0, v9 },
464 { "sta",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[i+1]o", 0, 0, v9 },
465 { "sta",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,	"d,[i]o", 0, 0, v9 },
466 { "sta",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),	"d,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
467 
468 { "sta",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0),		"g,[1+2]A", 0, 0, v9 },
469 { "sta",	F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0),	"g,[1]A", 0, 0, v9 }, /* sta d,[rs1+%g0] */
470 { "sta",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),		"g,[1+i]o", 0, 0, v9 },
471 { "sta",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1),		"g,[i+1]o", 0, 0, v9 },
472 { "sta",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0,	"g,[i]o", 0, 0, v9 },
473 { "sta",	F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0),	"g,[1]o", 0, 0, v9 }, /* st d,[rs1+0] */
474 
475 { "stwa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0),		"d,[1+2]A", F_ALIAS, 0, v9 },
476 { "stwa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
477 { "stwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
478 { "stwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
479 { "stwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
480 { "stwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
481 { "stswa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0),		"d,[1+2]A", F_ALIAS, 0, v9 },
482 { "stswa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
483 { "stswa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
484 { "stswa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
485 { "stswa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
486 { "stswa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
487 { "stuwa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0),		"d,[1+2]A", F_ALIAS, 0, v9 },
488 { "stuwa",	F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v9 }, /* sta d,[rs1+%g0] */
489 { "stuwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
490 { "stuwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
491 { "stuwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
492 { "stuwa",	F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* st d,[rs1+0] */
493 
494 { "stb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),	"d,[1+2]", 0, 0, v6 },
495 { "stb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),	"d,[1]", 0, 0, v6 }, /* stb d,[rs1+%g0] */
496 { "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[1+i]", 0, 0, v6 },
497 { "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[i+1]", 0, 0, v6 },
498 { "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,	"d,[i]", 0, 0, v6 },
499 { "stb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),	"d,[1]", 0, 0, v6 }, /* stb d,[rs1+0] */
500 
501 { "stsb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
502 { "stsb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
503 { "stsb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
504 { "stsb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
505 { "stsb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
506 { "stsb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
507 { "stub",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
508 { "stub",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+%g0] */
509 { "stub",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
510 { "stub",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
511 { "stub",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
512 { "stub",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* stb d,[rs1+0] */
513 
514 { "stba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0),		"d,[1+2]A", 0, 0, v6 },
515 { "stba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),	"d,[1]A", 0, 0, v6 }, /* stba d,[rs1+%g0] */
516 { "stba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[1+i]o", 0, 0, v9 },
517 { "stba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[i+1]o", 0, 0, v9 },
518 { "stba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,	"d,[i]o", 0, 0, v9 },
519 { "stba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),	"d,[1]o", 0, 0, v9 }, /* stb d,[rs1+0] */
520 
521 { "stsba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0),		"d,[1+2]A", F_ALIAS, 0, v6 },
522 { "stsba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
523 { "stsba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
524 { "stsba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
525 { "stsba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
526 { "stsba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
527 { "stuba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0),		"d,[1+2]A", F_ALIAS, 0, v6 },
528 { "stuba",	F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v6 }, /* stba d,[rs1+%g0] */
529 { "stuba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
530 { "stuba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
531 { "stuba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
532 { "stuba",	F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* stb d,[rs1+0] */
533 
534 { "std",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),	"d,[1+2]", 0, 0, v6 },
535 { "std",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),	"d,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */
536 { "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[1+i]", 0, 0, v6 },
537 { "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[i+1]", 0, 0, v6 },
538 { "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,	"d,[i]", 0, 0, v6 },
539 { "std",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),	"d,[1]", 0, 0, v6 }, /* std d,[rs1+0] */
540 
541 { "std",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),	"q,[1+2]", 0, 0, v6notv9 },
542 { "std",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),	"q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
543 { "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"q,[1+i]", 0, 0, v6notv9 },
544 { "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"q,[i+1]", 0, 0, v6notv9 },
545 { "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,	"q,[i]", 0, 0, v6notv9 },
546 { "std",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),	"q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
547 { "std",	F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0),	"H,[1+2]", 0, 0, v6 },
548 { "std",	F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0),	"H,[1]", 0, 0, v6 }, /* std d,[rs1+%g0] */
549 { "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1),		"H,[1+i]", 0, 0, v6 },
550 { "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1),		"H,[i+1]", 0, 0, v6 },
551 { "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0,	"H,[i]", 0, 0, v6 },
552 { "std",	F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0),	"H,[1]", 0, 0, v6 }, /* std d,[rs1+0] */
553 
554 { "std",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),	"Q,[1+2]", 0, 0, v6notv9 },
555 { "std",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),	"Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
556 { "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"Q,[1+i]", 0, 0, v6notv9 },
557 { "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"Q,[i+1]", 0, 0, v6notv9 },
558 { "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,	"Q,[i]", 0, 0, v6notv9 },
559 { "std",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),	"Q,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
560 { "std",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0),	"D,[1+2]", 0, 0, v6notv9 },
561 { "std",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0),	"D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+%g0] */
562 { "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"D,[1+i]", 0, 0, v6notv9 },
563 { "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"D,[i+1]", 0, 0, v6notv9 },
564 { "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,	"D,[i]", 0, 0, v6notv9 },
565 { "std",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),	"D,[1]", 0, 0, v6notv9 }, /* std d,[rs1+0] */
566 
567 { "spilld",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
568 { "spilld",	F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+%g0] */
569 { "spilld",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
570 { "spilld",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
571 { "spilld",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
572 { "spilld",	F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* std d,[rs1+0] */
573 
574 { "stda",	F3(3, 0x17, 0), F3(~3, ~0x17, ~0),		"d,[1+2]A", 0, 0, v6 },
575 { "stda",	F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0),	"d,[1]A", 0, 0, v6 }, /* stda d,[rs1+%g0] */
576 { "stda",	F3(3, 0x17, 1), F3(~3, ~0x17, ~1),		"d,[1+i]o", 0, 0, v9 },
577 { "stda",	F3(3, 0x17, 1), F3(~3, ~0x17, ~1),		"d,[i+1]o", 0, 0, v9 },
578 { "stda",	F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0,	"d,[i]o", 0, 0, v9 },
579 { "stda",	F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0),	"d,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
580 { "stda",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0),		"H,[1+2]A", 0, 0, v9 },
581 { "stda",	F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0),	"H,[1]A", 0, 0, v9 }, /* stda d,[rs1+%g0] */
582 { "stda",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"H,[1+i]o", 0, 0, v9 },
583 { "stda",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1),		"H,[i+1]o", 0, 0, v9 },
584 { "stda",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0,	"H,[i]o", 0, 0, v9 },
585 { "stda",	F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0),	"H,[1]o", 0, 0, v9 }, /* std d,[rs1+0] */
586 
587 { "sth",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),	"d,[1+2]", 0, 0, v6 },
588 { "sth",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),	"d,[1]", 0, 0, v6 }, /* sth d,[rs1+%g0] */
589 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[1+i]", 0, 0, v6 },
590 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[i+1]", 0, 0, v6 },
591 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,	"d,[i]", 0, 0, v6 },
592 { "sth",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),	"d,[1]", 0, 0, v6 }, /* sth d,[rs1+0] */
593 
594 { "stsh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
595 { "stsh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
596 { "stsh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
597 { "stsh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
598 { "stsh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
599 { "stsh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
600 { "stuh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0),	"d,[1+2]", F_ALIAS, 0, v6 },
601 { "stuh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+%g0] */
602 { "stuh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[1+i]", F_ALIAS, 0, v6 },
603 { "stuh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1),		"d,[i+1]", F_ALIAS, 0, v6 },
604 { "stuh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0,	"d,[i]", F_ALIAS, 0, v6 },
605 { "stuh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0),	"d,[1]", F_ALIAS, 0, v6 }, /* sth d,[rs1+0] */
606 
607 { "stha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0),		"d,[1+2]A", 0, 0, v6 },
608 { "stha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),	"d,[1]A", 0, 0, v6 }, /* stha ,[rs1+%g0] */
609 { "stha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[1+i]o", 0, 0, v9 },
610 { "stha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[i+1]o", 0, 0, v9 },
611 { "stha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,	"d,[i]o", 0, 0, v9 },
612 { "stha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),	"d,[1]o", 0, 0, v9 }, /* sth d,[rs1+0] */
613 
614 { "stsha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0),		"d,[1+2]A", F_ALIAS, 0, v6 },
615 { "stsha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
616 { "stsha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
617 { "stsha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
618 { "stsha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
619 { "stsha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
620 { "stuha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0),		"d,[1+2]A", F_ALIAS, 0, v6 },
621 { "stuha",	F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0),	"d,[1]A", F_ALIAS, 0, v6 }, /* stha ,[rs1+%g0] */
622 { "stuha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[1+i]o", F_ALIAS, 0, v9 },
623 { "stuha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1),		"d,[i+1]o", F_ALIAS, 0, v9 },
624 { "stuha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0,	"d,[i]o", F_ALIAS, 0, v9 },
625 { "stuha",	F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0),	"d,[1]o", F_ALIAS, 0, v9 }, /* sth d,[rs1+0] */
626 
627 { "stx",	F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0),	"d,[1+2]", 0, 0, v9 },
628 { "stx",	F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0),	"d,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
629 { "stx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),		"d,[1+i]", 0, 0, v9 },
630 { "stx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1),		"d,[i+1]", 0, 0, v9 },
631 { "stx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0,	"d,[i]", 0, 0, v9 },
632 { "stx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0),	"d,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
633 
634 { "stx",	F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1),	"F,[1+2]", 0, 0, v9 },
635 { "stx",	F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+%g0] */
636 { "stx",	F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),		"F,[1+i]", 0, 0, v9 },
637 { "stx",	F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1),		"F,[i+1]", 0, 0, v9 },
638 { "stx",	F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1),	"F,[i]", 0, 0, v9 },
639 { "stx",	F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, v9 }, /* stx d,[rs1+0] */
640 
641 { "stxa",	F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0),		"d,[1+2]A", 0, 0, v9 },
642 { "stxa",	F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0),	"d,[1]A", 0, 0, v9 }, /* stxa d,[rs1+%g0] */
643 { "stxa",	F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),		"d,[1+i]o", 0, 0, v9 },
644 { "stxa",	F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1),		"d,[i+1]o", 0, 0, v9 },
645 { "stxa",	F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0,	"d,[i]o", 0, 0, v9 },
646 { "stxa",	F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0),	"d,[1]o", 0, 0, v9 }, /* stx d,[rs1+0] */
647 
648 { "stq",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0),	"J,[1+2]", 0, 0, v9 },
649 { "stq",	F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0),	"J,[1]", 0, 0, v9 }, /* stq [rs1+%g0] */
650 { "stq",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"J,[1+i]", 0, 0, v9 },
651 { "stq",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1),		"J,[i+1]", 0, 0, v9 },
652 { "stq",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0,	"J,[i]", 0, 0, v9 },
653 { "stq",	F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0),	"J,[1]", 0, 0, v9 }, /* stq [rs1+0] */
654 
655 { "stqa",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0),	"J,[1+2]A", 0, 0, v9 },
656 { "stqa",	F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0),	"J,[1]A", 0, 0, v9 }, /* stqa [rs1+%g0] */
657 { "stqa",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"J,[1+i]o", 0, 0, v9 },
658 { "stqa",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1),		"J,[i+1]o", 0, 0, v9 },
659 { "stqa",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0,	"J,[i]o", 0, 0, v9 },
660 { "stqa",	F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0),	"J,[1]o", 0, 0, v9 }, /* stqa [rs1+0] */
661 
662 { "swap",	F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0),	"[1+2],d", 0, 0, v7 },
663 { "swap",	F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0),	"[1],d", 0, 0, v7 }, /* swap [rs1+%g0],d */
664 { "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),		"[1+i],d", 0, 0, v7 },
665 { "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1),		"[i+1],d", 0, 0, v7 },
666 { "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0,	"[i],d", 0, 0, v7 },
667 { "swap",	F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0),	"[1],d", 0, 0, v7 }, /* swap [rs1+0],d */
668 
669 { "swapa",	F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0),		"[1+2]A,d", 0, 0, v7 },
670 { "swapa",	F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0),	"[1]A,d", 0, 0, v7 }, /* swapa [rs1+%g0],d */
671 { "swapa",	F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),		"[1+i]o,d", 0, 0, v9 },
672 { "swapa",	F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1),		"[i+1]o,d", 0, 0, v9 },
673 { "swapa",	F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0,	"[i]o,d", 0, 0, v9 },
674 { "swapa",	F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0),	"[1]o,d", 0, 0, v9 }, /* swap [rs1+0],d */
675 
676 { "restore",	F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0),			"1,2,d", 0, 0, v6 },
677 { "restore",	F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"", 0, 0, v6 }, /* restore %g0,%g0,%g0 */
678 { "restore",	F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1),				"1,i,d", 0, 0, v6 },
679 { "restore",	F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0),	"", 0, 0, v6 }, /* restore %g0,0,%g0 */
680 
681 { "rett",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0),	"1+2", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+rs2 */
682 { "rett",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0),	"1", F_UNBR|F_DELAYED, 0, v6 },	/* rett rs1,%g0 */
683 { "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,		"1+i", F_UNBR|F_DELAYED, 0, v6 }, /* rett rs1+X */
684 { "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0,		"i+1", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
685 { "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,		"i", F_UNBR|F_DELAYED, 0, v6 }, /* rett X+rs1 */
686 { "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0,		"i", F_UNBR|F_DELAYED, 0, v6 },	/* rett X */
687 { "rett",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0),	"1", F_UNBR|F_DELAYED, 0, v6 },	/* rett rs1+0 */
688 
689 { "save",	F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
690 { "save",	F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),		"1,i,d", 0, 0, v6 },
691 { "save",	F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1),		"i,1,d", 0, 0, v6 }, /* Sun assembler compatibility */
692 { "save",	0x81e00000,	~0x81e00000,			"", F_ALIAS, 0, v6 },
693 
694 { "ret",  F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8),	       "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %i7+8,%g0 */
695 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %o7+8,%g0 */
696 
697 { "jmpl",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0),	"1+2,d", F_JSR|F_DELAYED, 0, v6 },
698 { "jmpl",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0),	"1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,d */
699 { "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0),	"1,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,d */
700 { "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0,	"i,d", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,d */
701 { "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1),		"1+i,d", F_JSR|F_DELAYED, 0, v6 },
702 { "jmpl",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1),		"i+1,d", F_JSR|F_DELAYED, 0, v6 },
703 
704 { "done",	F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
705 { "retry",	F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
706 { "saved",	F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
707 { "restored",	F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
708 { "allclean",	F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
709 { "otherw",	F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
710 { "normalw",	F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
711 { "invalw",	F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0),	"", 0, 0, v9 },
712 { "sir",	F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0,		"i", 0, 0, v9 },
713 
714 { "flush",	F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),	"1+2", 0, 0, v8 },
715 { "flush",	F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),	"1", 0, 0, v8 }, /* flush rs1+%g0 */
716 { "flush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),	"1", 0, 0, v8 }, /* flush rs1+0 */
717 { "flush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,	"i", 0, 0, v8 }, /* flush %g0+i */
718 { "flush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"1+i", 0, 0, v8 },
719 { "flush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"i+1", 0, 0, v8 },
720 
721 /* IFLUSH was renamed to FLUSH in v8.  */
722 { "iflush",	F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0),	"1+2", F_ALIAS, 0, v6 },
723 { "iflush",	F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0),	"1", F_ALIAS, 0, v6 }, /* flush rs1+%g0 */
724 { "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0),	"1", F_ALIAS, 0, v6 }, /* flush rs1+0 */
725 { "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0,	"i", F_ALIAS, 0, v6 },
726 { "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"1+i", F_ALIAS, 0, v6 },
727 { "iflush",	F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1),		"i+1", F_ALIAS, 0, v6 },
728 
729 { "return",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0),	"1+2", 0, 0, v9 },
730 { "return",	F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0),	"1", 0, 0, v9 }, /* return rs1+%g0 */
731 { "return",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0),	"1", 0, 0, v9 }, /* return rs1+0 */
732 { "return",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0,	"i", 0, 0, v9 }, /* return %g0+i */
733 { "return",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1),		"1+i", 0, 0, v9 },
734 { "return",	F3(2, 0x39, 1), F3(~2, ~0x39, ~1),		"i+1", 0, 0, v9 },
735 
736 { "flushw",	F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"", 0, 0, v9 },
737 
738 { "membar",	F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, v9 },
739 { "stbar",	F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, v8 },
740 
741 { "prefetch",	F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0),		"[1+2],*", 0, 0, v9 },
742 { "prefetch",	F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0,	"[1],*", 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
743 { "prefetch",	F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),		"[1+i],*", 0, 0, v9 },
744 { "prefetch",	F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1),		"[i+1],*", 0, 0, v9 },
745 { "prefetch",	F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0,	"[i],*", 0, 0, v9 },
746 { "prefetch",	F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0),	"[1],*", 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
747 { "prefetcha",	F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0),		"[1+2]A,*", 0, 0, v9 },
748 { "prefetcha",	F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0,	"[1]A,*", 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
749 { "prefetcha",	F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),		"[1+i]o,*", 0, 0, v9 },
750 { "prefetcha",	F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1),		"[i+1]o,*", 0, 0, v9 },
751 { "prefetcha",	F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0,	"[i]o,*", 0, 0, v9 },
752 { "prefetcha",	F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0),	"[1]o,*", 0, 0, v9 }, /* prefetcha [rs1+0],d */
753 
754 { "sll",	F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5),	"1,2,d", 0, 0, v6 },
755 { "sll",	F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5),	"1,X,d", 0, 0, v6 },
756 { "sra",	F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5),	"1,2,d", 0, 0, v6 },
757 { "sra",	F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5),	"1,X,d", 0, 0, v6 },
758 { "srl",	F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5),	"1,2,d", 0, 0, v6 },
759 { "srl",	F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5),	"1,X,d", 0, 0, v6 },
760 
761 { "sllx",	F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5),	"1,2,d", 0, 0, v9 },
762 { "sllx",	F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6),	"1,Y,d", 0, 0, v9 },
763 { "srax",	F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5),	"1,2,d", 0, 0, v9 },
764 { "srax",	F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6),	"1,Y,d", 0, 0, v9 },
765 { "srlx",	F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5),	"1,2,d", 0, 0, v9 },
766 { "srlx",	F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6),	"1,Y,d", 0, 0, v9 },
767 
768 { "mulscc",	F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
769 { "mulscc",	F3(2, 0x24, 1), F3(~2, ~0x24, ~1),		"1,i,d", 0, 0, v6 },
770 
771 { "divscc",	F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0),	"1,2,d", 0, 0, sparclite },
772 { "divscc",	F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1),		"1,i,d", 0, 0, sparclite },
773 
774 { "scan",	F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0),	"1,2,d", 0, 0, sparclet|sparclite },
775 { "scan",	F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1),		"1,i,d", 0, 0, sparclet|sparclite },
776 
777 { "popc",	F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, v9 },
778 { "popc",	F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0,	"i,d", 0, HWCAP_POPC, v9 },
779 
780 { "clr",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0),	"d", F_ALIAS, 0, v6 }, /* or %g0,%g0,d */
781 { "clr",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0),		"d", F_ALIAS, 0, v6 }, /* or %g0,0,d	*/
782 { "clr",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0),		"[1+2]", F_ALIAS, 0, v6 },
783 { "clr",	F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0),		"[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+%g0] */
784 { "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,			"[1+i]", F_ALIAS, 0, v6 },
785 { "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0,			"[i+1]", F_ALIAS, 0, v6 },
786 { "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0,			"[i]", F_ALIAS, 0, v6 },
787 { "clr",	F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0),		"[1]", F_ALIAS, 0, v6 }, /* st %g0,[rs1+0] */
788 
789 { "clrb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0),	"[1+2]", F_ALIAS, 0, v6 },
790 { "clrb",	F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0),	"[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+%g0] */
791 { "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,		"[1+i]", F_ALIAS, 0, v6 },
792 { "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0,		"[i+1]", F_ALIAS, 0, v6 },
793 { "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0,		"[i]", F_ALIAS, 0, v6 },
794 { "clrb",	F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0),	"[1]", F_ALIAS, 0, v6 }, /* stb %g0,[rs1+0] */
795 
796 { "clrh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0),	"[1+2]", F_ALIAS, 0, v6 },
797 { "clrh",	F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0),	"[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+%g0] */
798 { "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,		"[1+i]", F_ALIAS, 0, v6 },
799 { "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0,		"[i+1]", F_ALIAS, 0, v6 },
800 { "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0,		"[i]", F_ALIAS, 0, v6 },
801 { "clrh",	F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0),	"[1]", F_ALIAS, 0, v6 }, /* sth %g0,[rs1+0] */
802 
803 { "clrx",	F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0),	"[1+2]", F_ALIAS, 0, v9 },
804 { "clrx",	F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0),	"[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+%g0] */
805 { "clrx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,		"[1+i]", F_ALIAS, 0, v9 },
806 { "clrx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0,		"[i+1]", F_ALIAS, 0, v9 },
807 { "clrx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0,		"[i]", F_ALIAS, 0, v9 },
808 { "clrx",	F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0),	"[1]", F_ALIAS, 0, v9 }, /* stx %g0,[rs1+0] */
809 
810 { "orcc",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
811 { "orcc",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1),		"1,i,d", 0, 0, v6 },
812 { "orcc",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1),		"i,1,d", 0, 0, v6 },
813 
814 /* This is not a commutative instruction.  */
815 { "orncc",	F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
816 { "orncc",	F3(2, 0x16, 1), F3(~2, ~0x16, ~1),		"1,i,d", 0, 0, v6 },
817 
818 /* This is not a commutative instruction.  */
819 { "orn",	F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
820 { "orn",	F3(2, 0x06, 1), F3(~2, ~0x06, ~1),		"1,i,d", 0, 0, v6 },
821 
822 { "tst",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0),	"1", 0, 0, v6 }, /* orcc rs1, %g0, %g0 */
823 { "tst",	F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0),	"2", 0, 0, v6 }, /* orcc %g0, rs2, %g0 */
824 { "tst",	F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0),	"1", 0, 0, v6 }, /* orcc rs1, 0, %g0 */
825 
826 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|ASI(~0),		"1,2,m", 0, 0, v8 }, /* wr r,r,%asrX */
827 { "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1),			"1,i,m", 0, 0, v8 }, /* wr r,i,%asrX */
828 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),	"2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
829 { "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1)|RS1_G0,		"i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
830 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|ASI_RS2(~0),		"1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
831 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),	"1,2,y", 0, 0, v6 }, /* wr r,r,%y */
832 { "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1)|RD_G0,		"1,i,y", 0, 0, v6 }, /* wr r,i,%y */
833 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
834 { "wr",	F3(2, 0x30, 1),		F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,		"i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
835 { "wr",	F3(2, 0x30, 0),		F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),	"1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
836 { "wr",	F3(2, 0x31, 0),		F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),	"1,2,p", 0, 0, v6notv9 }, /* wr r,r,%psr */
837 { "wr",	F3(2, 0x31, 1),		F3(~2, ~0x31, ~1)|RD_G0,		"1,i,p", 0, 0, v6notv9 }, /* wr r,i,%psr */
838 { "wr",	F3(2, 0x31, 0),		F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
839 { "wr",	F3(2, 0x31, 1),		F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,		"i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
840 { "wr",	F3(2, 0x31, 0),		F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),	"1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
841 { "wr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),	"1,2,w", 0, 0, v6notv9 }, /* wr r,r,%wim */
842 { "wr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1)|RD_G0,		"1,i,w", 0, 0, v6notv9 }, /* wr r,i,%wim */
843 { "wr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
844 { "wr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,		"i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
845 { "wr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),	"1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
846 { "wr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),	"1,2,t", 0, 0, v6notv9 }, /* wr r,r,%tbr */
847 { "wr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1)|RD_G0,		"1,i,t", 0, 0, v6notv9 }, /* wr r,i,%tbr */
848 { "wr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
849 { "wr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,		"i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
850 { "wr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),	"1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
851 
852 { "wr", F3(2, 0x30, 0)|RD(2),	F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0),	"1,2,E", 0, 0, v9 }, /* wr r,r,%ccr */
853 { "wr", F3(2, 0x30, 1)|RD(2),	F3(~2, ~0x30, ~1)|RD(~2),		"1,i,E", 0, 0, v9 }, /* wr r,i,%ccr */
854 { "wr", F3(2, 0x30, 0)|RD(3),	F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0),	"1,2,o", 0, 0, v9 }, /* wr r,r,%asi */
855 { "wr", F3(2, 0x30, 1)|RD(3),	F3(~2, ~0x30, ~1)|RD(~3),		"1,i,o", 0, 0, v9 }, /* wr r,i,%asi */
856 { "wr", F3(2, 0x30, 0)|RD(6),	F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0),	"1,2,s", 0, 0, v9 }, /* wr r,r,%fprs */
857 { "wr", F3(2, 0x30, 1)|RD(6),	F3(~2, ~0x30, ~1)|RD(~6),		"1,i,s", 0, 0, v9 }, /* wr r,i,%fprs */
858 
859 { "wr", F3(2, 0x30, 0)|RD(16),	F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pcr */
860 { "wr", F3(2, 0x30, 1)|RD(16),	F3(~2, ~0x30, ~1)|RD(~16),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pcr */
861 { "wr", F3(2, 0x30, 0)|RD(17),	F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%pic */
862 { "wr", F3(2, 0x30, 1)|RD(17),	F3(~2, ~0x30, ~1)|RD(~17),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%pic */
863 { "wr", F3(2, 0x30, 0)|RD(18),	F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%dcr */
864 { "wr", F3(2, 0x30, 1)|RD(18),	F3(~2, ~0x30, ~1)|RD(~18),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%dcr */
865 { "wr", F3(2, 0x30, 0)|RD(19),	F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%gsr */
866 { "wr", F3(2, 0x30, 1)|RD(19),	F3(~2, ~0x30, ~1)|RD(~19),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%gsr */
867 { "wr", F3(2, 0x30, 0)|RD(20),	F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%set_softint */
868 { "wr", F3(2, 0x30, 1)|RD(20),	F3(~2, ~0x30, ~1)|RD(~20),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%set_softint */
869 { "wr", F3(2, 0x30, 0)|RD(21),	F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%clear_softint */
870 { "wr", F3(2, 0x30, 1)|RD(21),	F3(~2, ~0x30, ~1)|RD(~21),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%clear_softint */
871 { "wr", F3(2, 0x30, 0)|RD(22),	F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%softint */
872 { "wr", F3(2, 0x30, 1)|RD(22),	F3(~2, ~0x30, ~1)|RD(~22),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%softint */
873 { "wr", F3(2, 0x30, 0)|RD(23),	F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0),	"1,2,_", 0, HWCAP_VIS, v9a }, /* wr r,r,%tick_cmpr */
874 { "wr", F3(2, 0x30, 1)|RD(23),	F3(~2, ~0x30, ~1)|RD(~23),		"1,i,_", 0, HWCAP_VIS, v9a }, /* wr r,i,%tick_cmpr */
875 { "wr", F3(2, 0x30, 0)|RD(24),	F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0),	"1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick */
876 { "wr", F3(2, 0x30, 1)|RD(24),	F3(~2, ~0x30, ~1)|RD(~24),		"1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick */
877 { "wr", F3(2, 0x30, 0)|RD(25),	F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0),	"1,2,_", HWCAP_VIS2, 0, v9b }, /* wr r,r,%sys_tick_cmpr */
878 { "wr", F3(2, 0x30, 1)|RD(25),	F3(~2, ~0x30, ~1)|RD(~25),		"1,i,_", HWCAP_VIS2, 0, v9b }, /* wr r,i,%sys_tick_cmpr */
879 { "wr", F3(2, 0x30, 0)|RD(26),	F3(~2, ~0x30, ~0)|RD(~26)|ASI(~0),	"1,2,_", 0, HWCAP_CBCOND, v9b }, /* wr r,r,%cfr */
880 { "wr", F3(2, 0x30, 1)|RD(26),	F3(~2, ~0x30, ~1)|RD(~26),		"1,i,_", 0, HWCAP_CBCOND, v9b }, /* wr r,i,%cfr */
881 { "wr", F3(2, 0x30, 0)|RD(27),	F3(~2, ~0x30, ~0)|RD(~27)|ASI(~0),	"1,2,_", 0, HWCAP_PAUSE, v9b }, /* wr r,r,%pause */
882 { "wr", F3(2, 0x30, 1)|RD(27),	F3(~2, ~0x30, ~1)|RD(~27),		"1,i,_", 0, HWCAP_PAUSE, v9b }, /* wr r,i,%pause */
883 { "wr", F3(2, 0x30, 0)|RD(28),	F3(~2, ~0x30, ~0)|RD(~28)|ASI(~0),	"1,2,_", 0, HWCAP_VIS3, v9b }, /* wr r,r,%cps */
884 { "wr", F3(2, 0x30, 1)|RD(28),	F3(~2, ~0x30, ~1)|RD(~28),		"1,i,_", 0, HWCAP_VIS3, v9b }, /* wr r,i,%cps */
885 
886 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, v9b }, /* wr %g0,i,%pause */
887 
888 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|SIMM13(~0),		"M,d", 0, 0, v8 }, /* rd %asrX,r */
889 { "rd",	F3(2, 0x28, 0),			F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),	"y,d", 0, 0, v6 }, /* rd %y,r */
890 { "rd",	F3(2, 0x29, 0),			F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),	"p,d", 0, 0, v6notv9 }, /* rd %psr,r */
891 { "rd",	F3(2, 0x2a, 0),			F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),	"w,d", 0, 0, v6notv9 }, /* rd %wim,r */
892 { "rd",	F3(2, 0x2b, 0),			F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),	"t,d", 0, 0, v6notv9 }, /* rd %tbr,r */
893 
894 { "rd",	F3(2, 0x28, 0)|RS1(2),		F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0),	"E,d", 0, 0, v9 }, /* rd %ccr,r */
895 { "rd",	F3(2, 0x28, 0)|RS1(3),		F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0),	"o,d", 0, 0, v9 }, /* rd %asi,r */
896 { "rd",	F3(2, 0x28, 0)|RS1(4),		F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0),	"W,d", 0, 0, v9 }, /* rd %tick,r */
897 { "rd",	F3(2, 0x28, 0)|RS1(5),		F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0),	"P,d", 0, 0, v9 }, /* rd %pc,r */
898 { "rd",	F3(2, 0x28, 0)|RS1(6),		F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0),	"s,d", 0, 0, v9 }, /* rd %fprs,r */
899 
900 { "rd",	F3(2, 0x28, 0)|RS1(16),		F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %pcr,r */
901 { "rd",	F3(2, 0x28, 0)|RS1(17),		F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %pic,r */
902 { "rd",	F3(2, 0x28, 0)|RS1(18),		F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %dcr,r */
903 { "rd",	F3(2, 0x28, 0)|RS1(19),		F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %gsr,r */
904 { "rd",	F3(2, 0x28, 0)|RS1(22),		F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %softint,r */
905 { "rd",	F3(2, 0x28, 0)|RS1(23),		F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0),	"/,d", 0, HWCAP_VIS, v9a }, /* rd %tick_cmpr,r */
906 { "rd",	F3(2, 0x28, 0)|RS1(24),		F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0),	"/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick,r */
907 { "rd",	F3(2, 0x28, 0)|RS1(25),		F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0),	"/,d", HWCAP_VIS2, 0, v9b }, /* rd %sys_tick_cmpr,r */
908 { "rd",	F3(2, 0x28, 0)|RS1(26),		F3(~2, ~0x28, ~0)|RS1(~26)|SIMM13(~0),	"/,d", HWCAP_CBCOND, 0, v9b }, /* rd %cfr,r */
909 { "rd",	F3(2, 0x28, 0)|RS1(28),		F3(~2, ~0x28, ~0)|RS1(~28)|SIMM13(~0),	"/,d", 0, HWCAP_VIS3, v9b }, /* rd %cps,r */
910 
911 { "rdpr",	F3(2, 0x2a, 0),		F3(~2, ~0x2a, ~0)|SIMM13(~0),	"?,d", 0, 0, v9 },   /* rdpr %priv,r */
912 { "wrpr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0),		"1,2,!", 0, 0, v9 }, /* wrpr r1,r2,%priv */
913 { "wrpr",	F3(2, 0x32, 0),		F3(~2, ~0x32, ~0)|SIMM13(~0),	"1,!", 0, 0, v9 },   /* wrpr r1,%priv */
914 { "wrpr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1),		"1,i,!", 0, 0, v9 }, /* wrpr r1,i,%priv */
915 { "wrpr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1),		"i,1,!", F_ALIAS, 0, v9 }, /* wrpr i,r1,%priv */
916 { "wrpr",	F3(2, 0x32, 1),		F3(~2, ~0x32, ~1)|RS1(~0),	"i,!", 0, 0, v9 },   /* wrpr i,%priv */
917 
918 { "rdhpr",	F3(2, 0x29, 0),		F3(~2, ~0x29, ~0)|SIMM13(~0),	"$,d", 0, 0, v9 },   /* rdhpr %hpriv,r */
919 { "wrhpr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0),		"1,2,%", 0, 0, v9 }, /* wrhpr r1,r2,%hpriv */
920 { "wrhpr",	F3(2, 0x33, 0),		F3(~2, ~0x33, ~0)|SIMM13(~0),	"1,%", 0, 0, v9 },   /* wrhpr r1,%hpriv */
921 { "wrhpr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1),		"1,i,%", 0, 0, v9 }, /* wrhpr r1,i,%hpriv */
922 { "wrhpr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1),		"i,1,%", F_ALIAS, 0, v9 }, /* wrhpr i,r1,%hpriv */
923 { "wrhpr",	F3(2, 0x33, 1),		F3(~2, ~0x33, ~1)|RS1(~0),	"i,%", 0, 0, v9 },   /* wrhpr i,%hpriv */
924 
925 /* ??? This group seems wrong.  A three operand move?  */
926 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0),		"1,2,m", F_ALIAS, 0, v8 }, /* wr r,r,%asrX */
927 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1),			"1,i,m", F_ALIAS, 0, v8 }, /* wr r,i,%asrX */
928 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0),	"1,2,y", F_ALIAS, 0, v6 }, /* wr r,r,%y */
929 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0,		"1,i,y", F_ALIAS, 0, v6 }, /* wr r,i,%y */
930 { "mov",	F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0),	"1,2,p", F_ALIAS, 0, v6notv9 }, /* wr r,r,%psr */
931 { "mov",	F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0,		"1,i,p", F_ALIAS, 0, v6notv9 }, /* wr r,i,%psr */
932 { "mov",	F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0),	"1,2,w", F_ALIAS, 0, v6notv9 }, /* wr r,r,%wim */
933 { "mov",	F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0,		"1,i,w", F_ALIAS, 0, v6notv9 }, /* wr r,i,%wim */
934 { "mov",	F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0),	"1,2,t", F_ALIAS, 0, v6notv9 }, /* wr r,r,%tbr */
935 { "mov",	F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0,		"1,i,t", F_ALIAS, 0, v6notv9 }, /* wr r,i,%tbr */
936 
937 { "mov",	F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0),		"M,d", F_ALIAS, 0, v8 }, /* rd %asr1,r */
938 { "mov",	F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0),	"y,d", F_ALIAS, 0, v6 }, /* rd %y,r */
939 { "mov",	F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0),	"p,d", F_ALIAS, 0, v6notv9 }, /* rd %psr,r */
940 { "mov",	F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0),	"w,d", F_ALIAS, 0, v6notv9 }, /* rd %wim,r */
941 { "mov",	F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0),	"t,d", F_ALIAS, 0, v6notv9 }, /* rd %tbr,r */
942 
943 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0),	"2,m", F_ALIAS, 0, v8 }, /* wr %g0,rs2,%asrX */
944 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0,		"i,m", F_ALIAS, 0, v8 }, /* wr %g0,i,%asrX */
945 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0),		"1,m", F_ALIAS, 0, v8 }, /* wr rs1,%g0,%asrX */
946 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0),		"1,m", F_ALIAS, 0, v8 }, /* wr rs1,0,%asrX */
947 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,y", F_ALIAS, 0, v6 }, /* wr %g0,rs2,%y */
948 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0,		"i,y", F_ALIAS, 0, v6 }, /* wr %g0,i,%y */
949 { "mov",	F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0),	"1,y", F_ALIAS, 0, v6 }, /* wr rs1,%g0,%y */
950 { "mov",	F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0),	"1,y", F_ALIAS, 0, v6 }, /* wr rs1,0,%y */
951 { "mov",	F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%psr */
952 { "mov",	F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0,		"i,p", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%psr */
953 { "mov",	F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0),	"1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%psr */
954 { "mov",	F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0),	"1,p", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%psr */
955 { "mov",	F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%wim */
956 { "mov",	F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0,		"i,w", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%wim */
957 { "mov",	F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0),	"1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%wim */
958 { "mov",	F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0),	"1,w", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%wim */
959 { "mov",	F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0),	"2,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,rs2,%tbr */
960 { "mov",	F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0,		"i,t", F_ALIAS, 0, v6notv9 }, /* wr %g0,i,%tbr */
961 { "mov",	F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0),	"1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,%g0,%tbr */
962 { "mov",	F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0),	"1,t", F_ALIAS, 0, v6notv9 }, /* wr rs1,0,%tbr */
963 
964 { "mov",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0),	"2,d", 0, 0, v6 }, /* or %g0,rs2,d */
965 { "mov",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0,		"i,d", 0, 0, v6 }, /* or %g0,i,d	*/
966 { "mov",        F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0),		"1,d", 0, 0, v6 }, /* or rs1,%g0,d   */
967 { "mov",        F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0),		"1,d", 0, 0, v6 }, /* or rs1,0,d */
968 
969 { "or",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
970 { "or",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"1,i,d", 0, 0, v6 },
971 { "or",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"i,1,d", 0, 0, v6 },
972 
973 { "bset",	F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0),	"2,r", F_ALIAS, 0, v6 },	/* or rd,rs2,rd */
974 { "bset",	F3(2, 0x02, 1), F3(~2, ~0x02, ~1),		"i,r", F_ALIAS, 0, v6 },	/* or rd,i,rd */
975 
976 /* This is not a commutative instruction.  */
977 { "andn",	F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
978 { "andn",	F3(2, 0x05, 1), F3(~2, ~0x05, ~1),		"1,i,d", 0, 0, v6 },
979 
980 /* This is not a commutative instruction.  */
981 { "andncc",	F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
982 { "andncc",	F3(2, 0x15, 1), F3(~2, ~0x15, ~1),		"1,i,d", 0, 0, v6 },
983 
984 { "bclr",	F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0),	"2,r", F_ALIAS, 0, v6 },	/* andn rd,rs2,rd */
985 { "bclr",	F3(2, 0x05, 1), F3(~2, ~0x05, ~1),		"i,r", F_ALIAS, 0, v6 },	/* andn rd,i,rd */
986 
987 { "cmp",	F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0),	"1,2", 0, 0, v6 },	/* subcc rs1,rs2,%g0 */
988 { "cmp",	F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0,		"1,i", 0, 0, v6 },	/* subcc rs1,i,%g0 */
989 
990 { "sub",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
991 { "sub",	F3(2, 0x04, 1), F3(~2, ~0x04, ~1),		"1,i,d", 0, 0, v6 },
992 
993 { "subcc",	F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
994 { "subcc",	F3(2, 0x14, 1), F3(~2, ~0x14, ~1),		"1,i,d", 0, 0, v6 },
995 
996 { "subx",	F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),	"1,2,d", 0, 0, v6notv9 },
997 { "subx",	F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),		"1,i,d", 0, 0, v6notv9 },
998 { "subc",	F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
999 { "subc",	F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1),		"1,i,d", 0, 0, v9 },
1000 
1001 { "subxcc",	F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),	"1,2,d", 0, 0, v6notv9 },
1002 { "subxcc",	F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),		"1,i,d", 0, 0, v6notv9 },
1003 { "subccc",	F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1004 { "subccc",	F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1),		"1,i,d", 0, 0, v9 },
1005 
1006 { "and",	F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1007 { "and",	F3(2, 0x01, 1), F3(~2, ~0x01, ~1),		"1,i,d", 0, 0, v6 },
1008 { "and",	F3(2, 0x01, 1), F3(~2, ~0x01, ~1),		"i,1,d", 0, 0, v6 },
1009 
1010 { "andcc",	F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1011 { "andcc",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1),		"1,i,d", 0, 0, v6 },
1012 { "andcc",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1),		"i,1,d", 0, 0, v6 },
1013 
1014 { "dec",	F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },	/* sub rd,1,rd */
1015 { "dec",	F3(2, 0x04, 1),		    F3(~2, ~0x04, ~1),		       "i,r", F_ALIAS, 0, v8 },	/* sub rd,imm,rd */
1016 { "deccc",	F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },	/* subcc rd,1,rd */
1017 { "deccc",	F3(2, 0x14, 1),		    F3(~2, ~0x14, ~1),		       "i,r", F_ALIAS, 0, v8 },	/* subcc rd,imm,rd */
1018 { "inc",	F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },	/* add rd,1,rd */
1019 { "inc",	F3(2, 0x00, 1),		    F3(~2, ~0x00, ~1),		       "i,r", F_ALIAS, 0, v8 },	/* add rd,imm,rd */
1020 { "inccc",	F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, v6 },	/* addcc rd,1,rd */
1021 { "inccc",	F3(2, 0x10, 1),		    F3(~2, ~0x10, ~1),		       "i,r", F_ALIAS, 0, v8 },	/* addcc rd,imm,rd */
1022 
1023 { "btst",	F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, v6 },	/* andcc rs1,rs2,%g0 */
1024 { "btst",	F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, v6 },	/* andcc rs1,i,%g0 */
1025 
1026 { "neg",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, v6 }, /* sub %g0,rs2,rd */
1027 { "neg",	F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, v6 }, /* sub %g0,rd,rd */
1028 
1029 { "add",	F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1030 { "add",	F3(2, 0x00, 1), F3(~2, ~0x00, ~1),		"1,i,d", 0, 0, v6 },
1031 { "add",	F3(2, 0x00, 1), F3(~2, ~0x00, ~1),		"i,1,d", 0, 0, v6 },
1032 { "addcc",	F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1033 { "addcc",	F3(2, 0x10, 1), F3(~2, ~0x10, ~1),		"1,i,d", 0, 0, v6 },
1034 { "addcc",	F3(2, 0x10, 1), F3(~2, ~0x10, ~1),		"i,1,d", 0, 0, v6 },
1035 
1036 { "addx",	F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),	"1,2,d", 0, 0, v6notv9 },
1037 { "addx",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"1,i,d", 0, 0, v6notv9 },
1038 { "addx",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"i,1,d", 0, 0, v6notv9 },
1039 { "addc",	F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1040 { "addc",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"1,i,d", 0, 0, v9 },
1041 { "addc",	F3(2, 0x08, 1), F3(~2, ~0x08, ~1),		"i,1,d", 0, 0, v9 },
1042 
1043 { "addxcc",	F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),	"1,2,d", 0, 0, v6notv9 },
1044 { "addxcc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"1,i,d", 0, 0, v6notv9 },
1045 { "addxcc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"i,1,d", 0, 0, v6notv9 },
1046 { "addccc",	F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1047 { "addccc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"1,i,d", 0, 0, v9 },
1048 { "addccc",	F3(2, 0x18, 1), F3(~2, ~0x18, ~1),		"i,1,d", 0, 0, v9 },
1049 
1050 { "smul",	F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_MUL32, v8 },
1051 { "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"1,i,d", 0, HWCAP_MUL32, v8 },
1052 { "smul",	F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1),		"i,1,d", 0, HWCAP_MUL32, v8 },
1053 { "smulcc",	F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_MUL32, v8 },
1054 { "smulcc",	F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),		"1,i,d", 0, HWCAP_MUL32, v8 },
1055 { "smulcc",	F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1),		"i,1,d", 0, HWCAP_MUL32, v8 },
1056 { "umul",	F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_MUL32, v8 },
1057 { "umul",	F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),		"1,i,d", 0, HWCAP_MUL32, v8 },
1058 { "umul",	F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1),		"i,1,d", 0, HWCAP_MUL32, v8 },
1059 { "umulcc",	F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_MUL32, v8 },
1060 { "umulcc",	F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),		"1,i,d", 0, HWCAP_MUL32, v8 },
1061 { "umulcc",	F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1),		"i,1,d", 0, HWCAP_MUL32, v8 },
1062 { "sdiv",	F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_DIV32, v8 },
1063 { "sdiv",	F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),		"1,i,d", 0, HWCAP_DIV32, v8 },
1064 { "sdiv",	F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1),		"i,1,d", 0, HWCAP_DIV32, v8 },
1065 { "sdivcc",	F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_DIV32, v8 },
1066 { "sdivcc",	F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),		"1,i,d", 0, HWCAP_DIV32, v8 },
1067 { "sdivcc",	F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1),		"i,1,d", 0, HWCAP_DIV32, v8 },
1068 { "udiv",	F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_DIV32, v8 },
1069 { "udiv",	F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),		"1,i,d", 0, HWCAP_DIV32, v8 },
1070 { "udiv",	F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1),		"i,1,d", 0, HWCAP_DIV32, v8 },
1071 { "udivcc",	F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0),	"1,2,d", 0, HWCAP_DIV32, v8 },
1072 { "udivcc",	F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),		"1,i,d", 0, HWCAP_DIV32, v8 },
1073 { "udivcc",	F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1),		"i,1,d", 0, HWCAP_DIV32, v8 },
1074 
1075 { "mulx",	F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1076 { "mulx",	F3(2, 0x09, 1), F3(~2, ~0x09, ~1),		"1,i,d", 0, 0, v9 },
1077 { "sdivx",	F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1078 { "sdivx",	F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),		"1,i,d", 0, 0, v9 },
1079 { "udivx",	F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0),	"1,2,d", 0, 0, v9 },
1080 { "udivx",	F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1),		"1,i,d", 0, 0, v9 },
1081 
1082 { "call",	F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, v6 },
1083 { "call",	F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, v6 },
1084 
1085 { "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),	"1+2", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%o7 */
1086 { "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0),	"1+2,#", F_JSR|F_DELAYED, 0, v6 },
1087 { "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),	"1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%o7 */
1088 { "call",	F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0),	"1,#", F_JSR|F_DELAYED, 0, v6 },
1089 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),		"1+i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%o7 */
1090 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),		"1+i,#", F_JSR|F_DELAYED, 0, v6 },
1091 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),		"i+1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%o7 */
1092 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf),		"i+1,#", F_JSR|F_DELAYED, 0, v6 },
1093 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,	"i", F_JSR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%o7 */
1094 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0,	"i,#", F_JSR|F_DELAYED, 0, v6 },
1095 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),	"1", F_JSR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%o7 */
1096 { "call",	F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0),	"1,#", F_JSR|F_DELAYED, 0, v6 },
1097 
1098 { "chkpt",	F2(0, 1)|CONDA|ANNUL|(1<<20), F2(~0, ~1)|((~CONDA)&COND(~0)), "G", 0, HWCAP_TRANS, v9b },
1099 
1100 /* Conditional instructions.
1101 
1102    Because this part of the table was such a mess earlier, I have
1103    macrofied it so that all the branches and traps are generated from
1104    a single-line description of each condition value.  John Gilmore. */
1105 
1106 /* Define branches -- one annulled, one without, etc. */
1107 #define br(opcode, mask, lose, flags) \
1108  { opcode, (mask)|ANNUL, (lose),       ",a l",   (flags), 0, v6 }, \
1109  { opcode, (mask)      , (lose)|ANNUL, "l",     (flags), 0, v6 }
1110 
1111 #define brx(opcode, mask, lose, flags) /* v9 */ \
1112  { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G",      (flags), 0, v9 }, \
1113  { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G",   (flags), 0, v9 }, \
1114  { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G",   (flags), 0, v9 }, \
1115  { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, v9 }, \
1116  { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G",   (flags), 0, v9 }, \
1117  { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, v9 }, \
1118  { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G",      (flags), 0, v9 }, \
1119  { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G",   (flags), 0, v9 }, \
1120  { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G",   (flags), 0, v9 }, \
1121  { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, v9 }, \
1122  { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G",   (flags), 0, v9 }, \
1123  { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, v9 }
1124 
1125 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1126 #define tr(opcode, mask, lose, flags) \
1127  { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0,	"Z,i",   (flags), 0, v9 }, /* %g0 + imm */ \
1128  { opcode, (mask)|(2<<11)|IMMED, (lose),	"Z,1+i", (flags), 0, v9 }, /* rs1 + imm */ \
1129  { opcode, (mask)|(2<<11), IMMED|(lose),	"Z,1+2", (flags), 0, v9 }, /* rs1 + rs2 */ \
1130  { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0,	"Z,1",   (flags), 0, v9 }, /* rs1 + %g0 */ \
1131  { opcode, (mask)|IMMED, (lose)|RS1_G0,	"z,i",   (flags)|F_ALIAS, 0, v9 }, /* %g0 + imm */ \
1132  { opcode, (mask)|IMMED, (lose),	"z,1+i", (flags)|F_ALIAS, 0, v9 }, /* rs1 + imm */ \
1133  { opcode, (mask), IMMED|(lose),	"z,1+2", (flags)|F_ALIAS, 0, v9 }, /* rs1 + rs2 */ \
1134  { opcode, (mask), IMMED|(lose)|RS2_G0,	"z,1",   (flags)|F_ALIAS, 0, v9 }, /* rs1 + %g0 */ \
1135  { opcode, (mask)|IMMED, (lose)|RS1_G0,		"i",     (flags), 0, v6 }, /* %g0 + imm */ \
1136  { opcode, (mask)|IMMED, (lose),		"1+i",   (flags), 0, v6 }, /* rs1 + imm */ \
1137  { opcode, (mask)|IMMED, (lose),		"i+1",   (flags), 0, v6 }, /* imm + rs1 */ \
1138  { opcode, (mask), IMMED|(lose),		"1+2",   (flags), 0, v6 }, /* rs1 + rs2 */ \
1139  { opcode, (mask), IMMED|(lose)|RS2_G0,		"1",     (flags), 0, v6 } /* rs1 + %g0 */
1140 
1141 /* v9: We must put `brx' before `br', to ensure that we never match something
1142    v9: against an expression unless it is an expression.  Otherwise, we end
1143    v9: up with undefined symbol tables entries, because they get added, but
1144    v9: are not deleted if the pattern fails to match.  */
1145 
1146 /* Define both branches and traps based on condition mask */
1147 #define cond(bop, top, mask, flags) \
1148   brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1149   br(bop,  F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1150   tr(top,  F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1151 
1152 /* Define all the conditions, all the branches, all the traps.  */
1153 
1154 /* Standard branch, trap mnemonics */
1155 cond ("b",	"ta",   CONDA, F_UNBR),
1156 /* Alternative form (just for assembly, not for disassembly) */
1157 cond ("ba",	"t",    CONDA, F_UNBR|F_ALIAS),
1158 
1159 cond ("bcc",	"tcc",  CONDCC, F_CONDBR),
1160 cond ("bcs",	"tcs",  CONDCS, F_CONDBR),
1161 cond ("be",	"te",   CONDE, F_CONDBR),
1162 cond ("beq",	"teq",  CONDE, F_CONDBR|F_ALIAS),
1163 cond ("bg",	"tg",   CONDG, F_CONDBR),
1164 cond ("bgt",	"tgt",  CONDG, F_CONDBR|F_ALIAS),
1165 cond ("bge",	"tge",  CONDGE, F_CONDBR),
1166 cond ("bgeu",	"tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1167 cond ("bgu",	"tgu",  CONDGU, F_CONDBR),
1168 cond ("bl",	"tl",   CONDL, F_CONDBR),
1169 cond ("blt",	"tlt",  CONDL, F_CONDBR|F_ALIAS),
1170 cond ("ble",	"tle",  CONDLE, F_CONDBR),
1171 cond ("bleu",	"tleu", CONDLEU, F_CONDBR),
1172 cond ("blu",	"tlu",  CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1173 cond ("bn",	"tn",   CONDN, F_CONDBR),
1174 cond ("bne",	"tne",  CONDNE, F_CONDBR),
1175 cond ("bneg",	"tneg", CONDNEG, F_CONDBR),
1176 cond ("bnz",	"tnz",  CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1177 cond ("bpos",	"tpos", CONDPOS, F_CONDBR),
1178 cond ("bvc",	"tvc",  CONDVC, F_CONDBR),
1179 cond ("bvs",	"tvs",  CONDVS, F_CONDBR),
1180 cond ("bz",	"tz",   CONDZ, F_CONDBR|F_ALIAS), /* for e */
1181 
1182 #undef cond
1183 #undef br
1184 #undef brr /* v9 */
1185 #undef tr
1186 
1187 #define brr(opcode, mask, lose, flags) /* v9 */ \
1188  { opcode, (mask)|BPRED, ANNUL|(lose), "1,k",      F_DELAYED|(flags), 0, v9 }, \
1189  { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k",   F_DELAYED|(flags), 0, v9 }, \
1190  { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k",   F_DELAYED|(flags), 0, v9 }, \
1191  { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, v9 }, \
1192  { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k",   F_DELAYED|(flags), 0, v9 }, \
1193  { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, v9 }
1194 
1195 #define condr(bop, mask, flags) /* v9 */ \
1196   brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1197 
1198 /* v9 */ condr("brnz", 0x5, F_CONDBR),
1199 /* v9 */ condr("brz", 0x1, F_CONDBR),
1200 /* v9 */ condr("brgez", 0x7, F_CONDBR),
1201 /* v9 */ condr("brlz", 0x3, F_CONDBR),
1202 /* v9 */ condr("brlez", 0x2, F_CONDBR),
1203 /* v9 */ condr("brgz", 0x6, F_CONDBR),
1204 
1205 #define cbcond(cop, cmask) \
1206   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \
1207     "1,2,=", F_CONDBR, HWCAP_CBCOND, v9}, \
1208   { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \
1209     "1,X,=", F_CONDBR, HWCAP_CBCOND, v9}, \
1210   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \
1211     "1,2,=", F_CONDBR, HWCAP_CBCOND, v9}, \
1212   { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \
1213     "1,X,=", F_CONDBR, HWCAP_CBCOND, v9},
1214 
1215 cbcond("be",   0x09)
1216 cbcond("ble",  0x0a)
1217 cbcond("bl",   0x0b)
1218 cbcond("bleu", 0x0c)
1219 cbcond("bcs",  0x0d)
1220 cbcond("bneg", 0x0e)
1221 cbcond("bvs",  0x0f)
1222 cbcond("bne",  0x19)
1223 cbcond("bg",   0x1a)
1224 cbcond("bge",  0x1b)
1225 cbcond("bgu",  0x1c)
1226 cbcond("bcc",  0x1d)
1227 cbcond("bpos", 0x1e)
1228 cbcond("bvc",  0x1f)
1229 
1230 #undef cbcond
1231 #undef condr /* v9 */
1232 #undef brr /* v9 */
1233 
1234 #define movr(opcode, mask, flags) /* v9 */ \
1235  { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, v9 }, \
1236  { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, v9 }
1237 
1238 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1239  { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, v9 }
1240 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1241  { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, v9 }
1242 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1243  { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, v9 }
1244 
1245 #define fmovrs(mop, mask, flags) /* v9 */ \
1246   fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1247 #define fmovrd(mop, mask, flags) /* v9 */ \
1248   fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1249 #define fmovrq(mop, mask, flags) /* v9 */ \
1250   fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1251 
1252 /* v9 */ movr("movrne", 0x5, 0),
1253 /* v9 */ movr("movre", 0x1, 0),
1254 /* v9 */ movr("movrgez", 0x7, 0),
1255 /* v9 */ movr("movrlz", 0x3, 0),
1256 /* v9 */ movr("movrlez", 0x2, 0),
1257 /* v9 */ movr("movrgz", 0x6, 0),
1258 /* v9 */ movr("movrnz", 0x5, F_ALIAS),
1259 /* v9 */ movr("movrz", 0x1, F_ALIAS),
1260 
1261 /* v9 */ fmovrs("fmovrsne", 0x5, 0),
1262 /* v9 */ fmovrs("fmovrse", 0x1, 0),
1263 /* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1264 /* v9 */ fmovrs("fmovrslz", 0x3, 0),
1265 /* v9 */ fmovrs("fmovrslez", 0x2, 0),
1266 /* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1267 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1268 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1269 
1270 /* v9 */ fmovrd("fmovrdne", 0x5, 0),
1271 /* v9 */ fmovrd("fmovrde", 0x1, 0),
1272 /* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1273 /* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1274 /* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1275 /* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1276 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1277 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1278 
1279 /* v9 */ fmovrq("fmovrqne", 0x5, 0),
1280 /* v9 */ fmovrq("fmovrqe", 0x1, 0),
1281 /* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1282 /* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1283 /* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1284 /* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1285 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1286 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1287 
1288 #undef movr /* v9 */
1289 #undef fmovr /* v9 */
1290 #undef fmrr /* v9 */
1291 
1292 #define movicc(opcode, cond, flags) /* v9 */ \
1293   { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, v9 }, \
1294   { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, v9 }, \
1295   { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11),     "Z,2,d", flags, 0, v9 }, \
1296   { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11),     "Z,I,d", flags, 0, v9 }
1297 
1298 #define movfcc(opcode, fcond, flags) /* v9 */ \
1299   { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, v9 }, \
1300   { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, v9 }, \
1301   { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, v9 }, \
1302   { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, v9 }, \
1303   { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, v9 }, \
1304   { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, v9 }, \
1305   { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, v9 }, \
1306   { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, v9 }
1307 
1308 #define movcc(opcode, cond, fcond, flags) /* v9 */ \
1309   movfcc (opcode, fcond, flags), /* v9 */ \
1310   movicc (opcode, cond, flags) /* v9 */
1311 
1312 /* v9 */ movcc  ("mova",	CONDA, FCONDA, 0),
1313 /* v9 */ movicc ("movcc",	CONDCC, 0),
1314 /* v9 */ movicc ("movgeu",	CONDGEU, F_ALIAS),
1315 /* v9 */ movicc ("movcs",	CONDCS, 0),
1316 /* v9 */ movicc ("movlu",	CONDLU, F_ALIAS),
1317 /* v9 */ movcc  ("move",	CONDE, FCONDE, 0),
1318 /* v9 */ movcc  ("movg",	CONDG, FCONDG, 0),
1319 /* v9 */ movcc  ("movge",	CONDGE, FCONDGE, 0),
1320 /* v9 */ movicc ("movgu",	CONDGU, 0),
1321 /* v9 */ movcc  ("movl",	CONDL, FCONDL, 0),
1322 /* v9 */ movcc  ("movle",	CONDLE, FCONDLE, 0),
1323 /* v9 */ movicc ("movleu",	CONDLEU, 0),
1324 /* v9 */ movfcc ("movlg",	FCONDLG, 0),
1325 /* v9 */ movcc  ("movn",	CONDN, FCONDN, 0),
1326 /* v9 */ movcc  ("movne",	CONDNE, FCONDNE, 0),
1327 /* v9 */ movicc ("movneg",	CONDNEG, 0),
1328 /* v9 */ movcc  ("movnz",	CONDNZ, FCONDNZ, F_ALIAS),
1329 /* v9 */ movfcc ("movo",	FCONDO, 0),
1330 /* v9 */ movicc ("movpos",	CONDPOS, 0),
1331 /* v9 */ movfcc ("movu",	FCONDU, 0),
1332 /* v9 */ movfcc ("movue",	FCONDUE, 0),
1333 /* v9 */ movfcc ("movug",	FCONDUG, 0),
1334 /* v9 */ movfcc ("movuge",	FCONDUGE, 0),
1335 /* v9 */ movfcc ("movul",	FCONDUL, 0),
1336 /* v9 */ movfcc ("movule",	FCONDULE, 0),
1337 /* v9 */ movicc ("movvc",	CONDVC, 0),
1338 /* v9 */ movicc ("movvs",	CONDVS, 0),
1339 /* v9 */ movcc  ("movz",	CONDZ, FCONDZ, F_ALIAS),
1340 
1341 #undef movicc /* v9 */
1342 #undef movfcc /* v9 */
1343 #undef movcc /* v9 */
1344 
1345 #define FM_SF 1		/* v9 - values for fpsize */
1346 #define FM_DF 2		/* v9 */
1347 #define FM_QF 3		/* v9 */
1348 
1349 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1350 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags, 0, v9 }, \
1351 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags, 0, v9 }
1352 
1353 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1354 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, v9 }, \
1355 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, v9 }, \
1356 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, v9 }, \
1357 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, v9 }
1358 
1359 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */
1360 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1361 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0),  "z," args, flags | F_FLOAT, 0, v9 }, \
1362 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, v9 }, \
1363 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0),  F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0),  "Z," args, flags | F_FLOAT, 0, v9 }, \
1364 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, v9 }, \
1365 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, v9 }, \
1366 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, v9 }
1367 
1368 #define fmovicc(suffix, cond, flags) /* v9 */ \
1369 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags),		\
1370 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags),		\
1371 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1372 
1373 #define fmovfcc(suffix, fcond, flags) /* v9 */ \
1374 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags),		\
1375 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags),		\
1376 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1377 
1378 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1379 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags),	\
1380 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags),	\
1381 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1382 
1383 /* v9 */ fmovcc  ("a", CONDA, FCONDA, 0),
1384 /* v9 */ fmovicc ("cc", CONDCC, 0),
1385 /* v9 */ fmovicc ("cs", CONDCS, 0),
1386 /* v9 */ fmovcc  ("e", CONDE, FCONDE, 0),
1387 /* v9 */ fmovcc  ("g", CONDG, FCONDG, 0),
1388 /* v9 */ fmovcc  ("ge", CONDGE, FCONDGE, 0),
1389 /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
1390 /* v9 */ fmovicc ("gu", CONDGU, 0),
1391 /* v9 */ fmovcc  ("l", CONDL, FCONDL, 0),
1392 /* v9 */ fmovcc  ("le", CONDLE, FCONDLE, 0),
1393 /* v9 */ fmovicc ("leu", CONDLEU, 0),
1394 /* v9 */ fmovfcc ("lg", FCONDLG, 0),
1395 /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
1396 /* v9 */ fmovcc  ("n", CONDN, FCONDN, 0),
1397 /* v9 */ fmovcc  ("ne", CONDNE, FCONDNE, 0),
1398 /* v9 */ fmovicc ("neg", CONDNEG, 0),
1399 /* v9 */ fmovcc  ("nz", CONDNZ, FCONDNZ, F_ALIAS),
1400 /* v9 */ fmovfcc ("o", FCONDO, 0),
1401 /* v9 */ fmovicc ("pos", CONDPOS, 0),
1402 /* v9 */ fmovfcc ("u", FCONDU, 0),
1403 /* v9 */ fmovfcc ("ue", FCONDUE, 0),
1404 /* v9 */ fmovfcc ("ug", FCONDUG, 0),
1405 /* v9 */ fmovfcc ("uge", FCONDUGE, 0),
1406 /* v9 */ fmovfcc ("ul", FCONDUL, 0),
1407 /* v9 */ fmovfcc ("ule", FCONDULE, 0),
1408 /* v9 */ fmovicc ("vc", CONDVC, 0),
1409 /* v9 */ fmovicc ("vs", CONDVS, 0),
1410 /* v9 */ fmovcc  ("z", CONDZ, FCONDZ, F_ALIAS),
1411 
1412 #undef fmoviccx /* v9 */
1413 #undef fmovfccx /* v9 */
1414 #undef fmovccx /* v9 */
1415 #undef fmovicc /* v9 */
1416 #undef fmovfcc /* v9 */
1417 #undef fmovcc /* v9 */
1418 #undef FM_DF /* v9 */
1419 #undef FM_QF /* v9 */
1420 #undef FM_SF /* v9 */
1421 
1422 /* Coprocessor branches.  */
1423 #define CBR(opcode, mask, lose, flags, arch) \
1424  { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED, 0, arch }, \
1425  { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, arch }
1426 
1427 /* Floating point branches.  */
1428 #define FBR(opcode, mask, lose, flags) \
1429  { opcode, (mask), ANNUL | (lose), "l",    flags | F_DELAYED | F_FBR, 0, v6 }, \
1430  { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, v6 }
1431 
1432 /* V9 extended floating point branches.  */
1433 #define FBRX(opcode, mask, lose, flags) /* v9 */ \
1434  { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
1435  { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1436  { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1437  { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1438  { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1439  { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1440  { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
1441  { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1442  { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1443  { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1444  { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1445  { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1446  { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
1447  { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1448  { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1449  { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1450  { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1451  { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1452  { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G",      flags|F_DELAYED|F_FBR, 0, v9 }, \
1453  { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1454  { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1455  { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, v9 }, \
1456  { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G",   flags|F_DELAYED|F_FBR, 0, v9 }, \
1457  { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, v9 }
1458 
1459 /* v9: We must put `FBRX' before `FBR', to ensure that we never match
1460    v9: something against an expression unless it is an expression.  Otherwise,
1461    v9: we end up with undefined symbol tables entries, because they get added,
1462    v9: but are not deleted if the pattern fails to match.  */
1463 
1464 #define CONDFC(fop, cop, mask, flags) \
1465   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1466   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1467   CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1468 
1469 #define CONDFCL(fop, cop, mask, flags) \
1470   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1471   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1472   CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1473 
1474 #define CONDF(fop, mask, flags) \
1475   FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1476   FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1477 
1478 CONDFC  ("fb",    "cb",    0x8, F_UNBR),
1479 CONDFCL ("fba",	  "cba",   0x8, F_UNBR|F_ALIAS),
1480 CONDFC  ("fbe",	  "cb0",   0x9, F_CONDBR),
1481 CONDF   ("fbz",            0x9, F_CONDBR|F_ALIAS),
1482 CONDFC  ("fbg",	  "cb2",   0x6, F_CONDBR),
1483 CONDFC  ("fbge",  "cb02",  0xb, F_CONDBR),
1484 CONDFC  ("fbl",	  "cb1",   0x4, F_CONDBR),
1485 CONDFC  ("fble",  "cb01",  0xd, F_CONDBR),
1486 CONDFC  ("fblg",  "cb12",  0x2, F_CONDBR),
1487 CONDFCL ("fbn",	  "cbn",   0x0, F_UNBR),
1488 CONDFC  ("fbne",  "cb123", 0x1, F_CONDBR),
1489 CONDF   ("fbnz",           0x1, F_CONDBR|F_ALIAS),
1490 CONDFC  ("fbo",	  "cb012", 0xf, F_CONDBR),
1491 CONDFC  ("fbu",	  "cb3",   0x7, F_CONDBR),
1492 CONDFC  ("fbue",  "cb03",  0xa, F_CONDBR),
1493 CONDFC  ("fbug",  "cb23",  0x5, F_CONDBR),
1494 CONDFC  ("fbuge", "cb023", 0xc, F_CONDBR),
1495 CONDFC  ("fbul",  "cb13",  0x3, F_CONDBR),
1496 CONDFC  ("fbule", "cb013", 0xe, F_CONDBR),
1497 
1498 #undef CONDFC
1499 #undef CONDFCL
1500 #undef CONDF
1501 #undef CBR
1502 #undef FBR
1503 #undef FBRX	/* v9 */
1504 
1505 { "jmp",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0),	"1+2", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+rs2,%g0 */
1506 { "jmp",	F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0),	"1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+%g0,%g0 */
1507 { "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,		"1+i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+i,%g0 */
1508 { "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0,		"i+1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl i+rs1,%g0 */
1509 { "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0,		"i", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl %g0+i,%g0 */
1510 { "jmp",	F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0),	"1", F_UNBR|F_DELAYED, 0, v6 }, /* jmpl rs1+0,%g0 */
1511 
1512 { "nop",	F2(0, 4), 0xfeffffff, "", 0, 0, v6 }, /* sethi 0, %g0 */
1513 
1514 { "set",	F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v6 },
1515 { "setuw",	F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
1516 { "setsw",	F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, v9 },
1517 { "setx",	F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, v9 },
1518 
1519 { "sethi",	F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, v6 },
1520 
1521 { "taddcc",	F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1522 { "taddcc",	F3(2, 0x20, 1), F3(~2, ~0x20, ~1),		"1,i,d", 0, 0, v6 },
1523 { "taddcc",	F3(2, 0x20, 1), F3(~2, ~0x20, ~1),		"i,1,d", 0, 0, v6 },
1524 { "taddcctv",	F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1525 { "taddcctv",	F3(2, 0x22, 1), F3(~2, ~0x22, ~1),		"1,i,d", 0, 0, v6 },
1526 { "taddcctv",	F3(2, 0x22, 1), F3(~2, ~0x22, ~1),		"i,1,d", 0, 0, v6 },
1527 
1528 { "tsubcc",	F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1529 { "tsubcc",	F3(2, 0x21, 1), F3(~2, ~0x21, ~1),		"1,i,d", 0, 0, v6 },
1530 { "tsubcctv",	F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1531 { "tsubcctv",	F3(2, 0x23, 1), F3(~2, ~0x23, ~1),		"1,i,d", 0, 0, v6 },
1532 
1533 { "unimp",	F2(0x0, 0x0), 0xffc00000, "n", 0, 0, v6notv9 },
1534 { "illtrap",	F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, v9 },
1535 
1536 /* This *is* a commutative instruction.  */
1537 { "xnor",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1538 { "xnor",	F3(2, 0x07, 1), F3(~2, ~0x07, ~1),		"1,i,d", 0, 0, v6 },
1539 { "xnor",	F3(2, 0x07, 1), F3(~2, ~0x07, ~1),		"i,1,d", 0, 0, v6 },
1540 /* This *is* a commutative instruction.  */
1541 { "xnorcc",	F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1542 { "xnorcc",	F3(2, 0x17, 1), F3(~2, ~0x17, ~1),		"1,i,d", 0, 0, v6 },
1543 { "xnorcc",	F3(2, 0x17, 1), F3(~2, ~0x17, ~1),		"i,1,d", 0, 0, v6 },
1544 { "xor",	F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1545 { "xor",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"1,i,d", 0, 0, v6 },
1546 { "xor",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"i,1,d", 0, 0, v6 },
1547 { "xorcc",	F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0),	"1,2,d", 0, 0, v6 },
1548 { "xorcc",	F3(2, 0x13, 1), F3(~2, ~0x13, ~1),		"1,i,d", 0, 0, v6 },
1549 { "xorcc",	F3(2, 0x13, 1), F3(~2, ~0x13, ~1),		"i,1,d", 0, 0, v6 },
1550 
1551 { "not",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, v6 }, /* xnor rs1,%0,rd */
1552 { "not",	F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, v6 }, /* xnor rd,%0,rd */
1553 
1554 { "btog",	F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0),	"2,r", F_ALIAS, 0, v6 }, /* xor rd,rs2,rd */
1555 { "btog",	F3(2, 0x03, 1), F3(~2, ~0x03, ~1),		"i,r", F_ALIAS, 0, v6 }, /* xor rd,i,rd */
1556 
1557 /* FPop1 and FPop2 are not instructions.  Don't accept them.  */
1558 
1559 { "fdtoi",	F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
1560 { "fstoi",	F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
1561 { "fqtoi",	F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
1562 
1563 { "fdtox",	F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
1564 { "fstox",	F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, v9 },
1565 { "fqtox",	F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, v9 },
1566 
1567 { "fitod",	F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
1568 { "fitos",	F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
1569 { "fitoq",	F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
1570 
1571 { "fxtod",	F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
1572 { "fxtos",	F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, v9 },
1573 { "fxtoq",	F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, v9 },
1574 
1575 { "fdtoq",	F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, v8 },
1576 { "fdtos",	F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, v6 },
1577 { "fqtod",	F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, v8 },
1578 { "fqtos",	F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, v8 },
1579 { "fstod",	F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, v6 },
1580 { "fstoq",	F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, v8 },
1581 
1582 { "fdivd",	F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, v6 },
1583 { "fdivq",	F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, v8 },
1584 { "fdivx",	F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
1585 { "fdivs",	F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, v6 },
1586 { "fmuld",	F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, v6 },
1587 { "fmulq",	F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, v8 },
1588 { "fmulx",	F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
1589 { "fmuls",	F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, v6 },
1590 
1591 { "fdmulq",	F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, v8 },
1592 { "fdmulx",	F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, v8 },
1593 { "fsmuld",	F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, v8 },
1594 
1595 { "fsqrtd",	F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, v7 },
1596 { "fsqrtq",	F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, v8 },
1597 { "fsqrtx",	F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v8 },
1598 { "fsqrts",	F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, v7 },
1599 
1600 { "fabsd",	F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
1601 { "fabsq",	F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
1602 { "fabsx",	F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
1603 { "fabss",	F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
1604 { "fmovd",	F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
1605 { "fmovq",	F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
1606 { "fmovx",	F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
1607 { "fmovs",	F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
1608 { "fnegd",	F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, v9 },
1609 { "fnegq",	F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, v9 },
1610 { "fnegx",	F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, v9 },
1611 { "fnegs",	F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, v6 },
1612 
1613 { "faddd",	F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, v6 },
1614 { "faddq",	F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, v8 },
1615 { "faddx",	F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
1616 { "fadds",	F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, v6 },
1617 { "fsubd",	F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, v6 },
1618 { "fsubq",	F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, v8 },
1619 { "fsubx",	F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, v8 },
1620 { "fsubs",	F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, v6 },
1621 
1622 #define CMPFCC(x)	(((x)&0x3)<<25)
1623 
1624 { "fcmpd",	          F3F(2, 0x35, 0x052),            F3F(~2, ~0x35, ~0x052)|RD_G0,  "v,B",   F_FLOAT, 0, v6 },
1625 { "fcmpd",	CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052),	 "6,v,B", F_FLOAT, 0, v9 },
1626 { "fcmpd",	CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052),	 "7,v,B", F_FLOAT, 0, v9 },
1627 { "fcmpd",	CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052),	 "8,v,B", F_FLOAT, 0, v9 },
1628 { "fcmpd",	CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052),	 "9,v,B", F_FLOAT, 0, v9 },
1629 { "fcmped",	          F3F(2, 0x35, 0x056),            F3F(~2, ~0x35, ~0x056)|RD_G0,  "v,B",   F_FLOAT, 0, v6 },
1630 { "fcmped",	CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056),	 "6,v,B", F_FLOAT, 0, v9 },
1631 { "fcmped",	CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056),	 "7,v,B", F_FLOAT, 0, v9 },
1632 { "fcmped",	CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056),	 "8,v,B", F_FLOAT, 0, v9 },
1633 { "fcmped",	CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056),	 "9,v,B", F_FLOAT, 0, v9 },
1634 { "fcmpq",	          F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,	 "V,R", F_FLOAT, 0, v8 },
1635 { "fcmpq",	CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),	 "6,V,R", F_FLOAT, 0, v9 },
1636 { "fcmpq",	CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),	 "7,V,R", F_FLOAT, 0, v9 },
1637 { "fcmpq",	CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),	 "8,V,R", F_FLOAT, 0, v9 },
1638 { "fcmpq",	CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),	 "9,V,R", F_FLOAT, 0, v9 },
1639 { "fcmpeq",	          F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,	 "V,R", F_FLOAT, 0, v8 },
1640 { "fcmpeq",	CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),	 "6,V,R", F_FLOAT, 0, v9 },
1641 { "fcmpeq",	CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),	 "7,V,R", F_FLOAT, 0, v9 },
1642 { "fcmpeq",	CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),	 "8,V,R", F_FLOAT, 0, v9 },
1643 { "fcmpeq",	CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),	 "9,V,R", F_FLOAT, 0, v9 },
1644 { "fcmpx",	          F3F(2, 0x35, 0x053),            F3F(~2, ~0x35, ~0x053)|RD_G0,	 "V,R", F_FLOAT|F_ALIAS, 0, v8 },
1645 { "fcmpx",	CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053),	 "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1646 { "fcmpx",	CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053),	 "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1647 { "fcmpx",	CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053),	 "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1648 { "fcmpx",	CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053),	 "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1649 { "fcmpex",	          F3F(2, 0x35, 0x057),            F3F(~2, ~0x35, ~0x057)|RD_G0,	 "V,R", F_FLOAT|F_ALIAS, 0, v8 },
1650 { "fcmpex",	CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057),	 "6,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1651 { "fcmpex",	CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057),	 "7,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1652 { "fcmpex",	CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057),	 "8,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1653 { "fcmpex",	CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057),	 "9,V,R", F_FLOAT|F_ALIAS, 0, v9 },
1654 { "fcmps",	          F3F(2, 0x35, 0x051),            F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f",   F_FLOAT, 0, v6 },
1655 { "fcmps",	CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051),	 "6,e,f", F_FLOAT, 0, v9 },
1656 { "fcmps",	CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051),	 "7,e,f", F_FLOAT, 0, v9 },
1657 { "fcmps",	CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051),	 "8,e,f", F_FLOAT, 0, v9 },
1658 { "fcmps",	CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051),	 "9,e,f", F_FLOAT, 0, v9 },
1659 { "fcmpes",	          F3F(2, 0x35, 0x055),            F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f",   F_FLOAT, 0, v6 },
1660 { "fcmpes",	CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055),	 "6,e,f", F_FLOAT, 0, v9 },
1661 { "fcmpes",	CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055),	 "7,e,f", F_FLOAT, 0, v9 },
1662 { "fcmpes",	CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055),	 "8,e,f", F_FLOAT, 0, v9 },
1663 { "fcmpes",	CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055),	 "9,e,f", F_FLOAT, 0, v9 },
1664 
1665 /* These Extended FPop (FIFO) instructions are new in the Fujitsu
1666    MB86934, replacing the CPop instructions from v6 and later
1667    processors.  */
1668 
1669 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, sparclite }
1670 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op),        args, 0, 0, sparclite }
1671 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0,  args, 0, 0, sparclite }
1672 
1673 EFPOP1_2 ("efitod",	0x0c8, "f,H"),
1674 EFPOP1_2 ("efitos",	0x0c4, "f,g"),
1675 EFPOP1_2 ("efdtoi",	0x0d2, "B,g"),
1676 EFPOP1_2 ("efstoi",	0x0d1, "f,g"),
1677 EFPOP1_2 ("efstod",	0x0c9, "f,H"),
1678 EFPOP1_2 ("efdtos",	0x0c6, "B,g"),
1679 EFPOP1_2 ("efmovs",	0x001, "f,g"),
1680 EFPOP1_2 ("efnegs",	0x005, "f,g"),
1681 EFPOP1_2 ("efabss",	0x009, "f,g"),
1682 EFPOP1_2 ("efsqrtd",	0x02a, "B,H"),
1683 EFPOP1_2 ("efsqrts",	0x029, "f,g"),
1684 EFPOP1_3 ("efaddd",	0x042, "v,B,H"),
1685 EFPOP1_3 ("efadds",	0x041, "e,f,g"),
1686 EFPOP1_3 ("efsubd",	0x046, "v,B,H"),
1687 EFPOP1_3 ("efsubs",	0x045, "e,f,g"),
1688 EFPOP1_3 ("efdivd",	0x04e, "v,B,H"),
1689 EFPOP1_3 ("efdivs",	0x04d, "e,f,g"),
1690 EFPOP1_3 ("efmuld",	0x04a, "v,B,H"),
1691 EFPOP1_3 ("efmuls",	0x049, "e,f,g"),
1692 EFPOP1_3 ("efsmuld",	0x069, "e,f,H"),
1693 EFPOP2_2 ("efcmpd",	0x052, "v,B"),
1694 EFPOP2_2 ("efcmped",	0x056, "v,B"),
1695 EFPOP2_2 ("efcmps",	0x051, "e,f"),
1696 EFPOP2_2 ("efcmpes",	0x055, "e,f"),
1697 
1698 #undef EFPOP1_2
1699 #undef EFPOP1_3
1700 #undef EFPOP2_2
1701 
1702 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1703    present.  Otherwise, the F_ALIAS flag is ignored.  */
1704 { "cpop1",	F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
1705 { "cpop2",	F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, v6notv9 },
1706 
1707 /* sparclet specific insns */
1708 
1709 COMMUTEOP ("umac", 0x3e, sparclet),
1710 COMMUTEOP ("smac", 0x3f, sparclet),
1711 COMMUTEOP ("umacd", 0x2e, sparclet),
1712 COMMUTEOP ("smacd", 0x2f, sparclet),
1713 COMMUTEOP ("umuld", 0x09, sparclet),
1714 COMMUTEOP ("smuld", 0x0d, sparclet),
1715 
1716 { "shuffle",	F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0),	"1,2,d", 0, 0, sparclet },
1717 { "shuffle",	F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1),		"1,i,d", 0, 0, sparclet },
1718 
1719 /* The manual isn't completely accurate on these insns.  The `rs2' field is
1720    treated as being 6 bits to account for 6 bit immediates to cpush.  It is
1721    assumed that it is intended that bit 5 is 0 when rs2 contains a reg.  */
1722 #define BIT5 (1<<5)
1723 { "crdcxt",	F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0),	"U,d", 0, 0, sparclet },
1724 { "cwrcxt",	F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0),	"1,u", 0, 0, sparclet },
1725 { "cpush",	F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0),	"1,2", 0, 0, sparclet },
1726 { "cpush",	F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0),		"1,Y", 0, 0, sparclet },
1727 { "cpusha",	F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0),	"1,2", 0, 0, sparclet },
1728 { "cpusha",	F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0),		"1,Y", 0, 0, sparclet },
1729 { "cpull",	F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, sparclet },
1730 #undef BIT5
1731 
1732 /* sparclet coprocessor branch insns */
1733 #define SLCBCC2(opcode, mask, lose) \
1734  { opcode, (mask), ANNUL|(lose), "l",    F_DELAYED|F_CONDBR, 0, sparclet }, \
1735  { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, sparclet }
1736 #define SLCBCC(opcode, mask) \
1737   SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1738 
1739 /* cbn,cba can't be defined here because they're defined elsewhere and GAS
1740    requires all mnemonics of the same name to be consecutive.  */
1741 /*SLCBCC("cbn", 0), - already defined */
1742 SLCBCC("cbe", 1),
1743 SLCBCC("cbf", 2),
1744 SLCBCC("cbef", 3),
1745 SLCBCC("cbr", 4),
1746 SLCBCC("cber", 5),
1747 SLCBCC("cbfr", 6),
1748 SLCBCC("cbefr", 7),
1749 /*SLCBCC("cba", 8), - already defined */
1750 SLCBCC("cbne", 9),
1751 SLCBCC("cbnf", 10),
1752 SLCBCC("cbnef", 11),
1753 SLCBCC("cbnr", 12),
1754 SLCBCC("cbner", 13),
1755 SLCBCC("cbnfr", 14),
1756 SLCBCC("cbnefr", 15),
1757 
1758 #undef SLCBCC2
1759 #undef SLCBCC
1760 
1761 { "casa",	F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, v9 },
1762 { "casa",	F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, v9 },
1763 { "casxa",	F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, v9 },
1764 { "casxa",	F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, v9 },
1765 
1766 /* v9 synthetic insns */
1767 { "iprefetch",	F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, v9 }, /* bn,a,pt %xcc,label */
1768 { "signx",	F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* sra rs1,%g0,rd */
1769 { "signx",	F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* sra rd,%g0,rd */
1770 { "clruw",	F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, v9 }, /* srl rs1,%g0,rd */
1771 { "clruw",	F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, v9 }, /* srl rd,%g0,rd */
1772 { "cas",	F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1773 { "casl",	F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1774 { "casx",	F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1775 { "casxl",	F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
1776 
1777 /* Ultrasparc extensions */
1778 { "shutdown",	F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, v9a },
1779 
1780 /* FIXME: Do we want to mark these as F_FLOAT, or something similar?  */
1781 { "fpadd16",	F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, v9a },
1782 { "fpadd16s",	F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, v9a },
1783 { "fpadd32",	F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, v9a },
1784 { "fpadd32s",	F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, v9a },
1785 { "fpsub16",	F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, v9a },
1786 { "fpsub16s",	F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, v9a },
1787 { "fpsub32",	F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, v9a },
1788 { "fpsub32s",	F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, v9a },
1789 
1790 { "fpack32",	F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, v9a },
1791 { "fpack16",	F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
1792 { "fpackfix",	F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, v9a },
1793 { "fexpand",	F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, v9a },
1794 { "fpmerge",	F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, v9a },
1795 
1796 /* Note that the mixing of 32/64 bit regs is intentional.  */
1797 { "fmul8x16",		F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, v9a },
1798 { "fmul8x16au",		F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, v9a },
1799 { "fmul8x16al",		F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, v9a },
1800 { "fmul8sux16",		F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, v9a },
1801 { "fmul8ulx16",		F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, v9a },
1802 { "fmuld8sux16",	F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, v9a },
1803 { "fmuld8ulx16",	F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, v9a },
1804 
1805 { "alignaddr",	F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, v9a },
1806 { "alignaddrl",	F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, v9a },
1807 { "faligndata",	F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, v9a },
1808 
1809 { "fzero",	F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, v9a },
1810 { "fzeros",	F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, v9a },
1811 { "fone",	F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, v9a },
1812 { "fones",	F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, v9a },
1813 { "fsrc1",	F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, v9a },
1814 { "fsrc1s",	F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, v9a },
1815 { "fsrc2",	F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, v9a },
1816 { "fsrc2s",	F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, v9a },
1817 { "fnot1",	F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, v9a },
1818 { "fnot1s",	F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, v9a },
1819 { "fnot2",	F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, v9a },
1820 { "fnot2s",	F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, v9a },
1821 { "for",	F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, v9a },
1822 { "fors",	F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, v9a },
1823 { "fnor",	F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, v9a },
1824 { "fnors",	F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, v9a },
1825 { "fand",	F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, v9a },
1826 { "fands",	F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, v9a },
1827 { "fnand",	F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, v9a },
1828 { "fnands",	F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, v9a },
1829 { "fxor",	F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, v9a },
1830 { "fxors",	F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, v9a },
1831 { "fxnor",	F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, v9a },
1832 { "fxnors",	F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, v9a },
1833 { "fornot1",	F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, v9a },
1834 { "fornot1s",	F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, v9a },
1835 { "fornot2",	F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, v9a },
1836 { "fornot2s",	F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, v9a },
1837 { "fandnot1",	F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, v9a },
1838 { "fandnot1s",	F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, v9a },
1839 { "fandnot2",	F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, v9a },
1840 { "fandnot2s",	F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, v9a },
1841 
1842 { "fcmpgt16",	F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, v9a },
1843 { "fcmpgt32",	F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, v9a },
1844 { "fcmple16",	F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, v9a },
1845 { "fcmple32",	F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, v9a },
1846 { "fcmpne16",	F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, v9a },
1847 { "fcmpne32",	F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, v9a },
1848 { "fcmpeq16",	F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, v9a },
1849 { "fcmpeq32",	F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, v9a },
1850 
1851 { "edge8",	F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, v9a },
1852 { "edge8l",	F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, v9a },
1853 { "edge16",	F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, v9a },
1854 { "edge16l",	F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, v9a },
1855 { "edge32",	F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, v9a },
1856 { "edge32l",	F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, v9a },
1857 
1858 { "pdist",	F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, v9a },
1859 
1860 { "array8",	F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, v9a },
1861 { "array16",	F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, v9a },
1862 { "array32",	F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, v9a },
1863 
1864 /* Cheetah instructions */
1865 { "edge8n",    F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", HWCAP_VIS2, 0, v9b },
1866 { "edge8ln",   F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", HWCAP_VIS2, 0, v9b },
1867 { "edge16n",   F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", HWCAP_VIS2, 0, v9b },
1868 { "edge16ln",  F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", HWCAP_VIS2, 0, v9b },
1869 { "edge32n",   F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", HWCAP_VIS2, 0, v9b },
1870 { "edge32ln",  F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", HWCAP_VIS2, 0, v9b },
1871 
1872 { "bmask",     F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", HWCAP_VIS2, 0, v9b },
1873 { "bshuffle",  F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", HWCAP_VIS2, 0, v9b },
1874 
1875 { "siam",      F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", HWCAP_VIS2, 0, v9b },
1876 
1877 { "commit",	F3(2, 0x3e, 0)|RD(30), F3(~2, ~0x3e, ~0)|RD(~30)|RS1_G0|SIMM13(~0), "", 0, HWCAP_TRANS, v9b },
1878 { "fnadds",	F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
1879 { "fnaddd",	F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
1880 { "fnmuls",	F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
1881 { "fnmuld",	F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
1882 { "fhadds",	F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
1883 { "fhaddd",	F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
1884 { "fhsubs",	F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
1885 { "fhsubd",	F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
1886 { "fnhadds",	F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, v9b },
1887 { "fnhaddd",	F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, v9b },
1888 { "fnsmuld",	F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, v9b },
1889 { "fpmaddx",	F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
1890 { "fmadds",	F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
1891 { "fmaddd",	F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
1892 { "fpmaddxhi",	F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, v9b },
1893 { "fmsubs",	F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
1894 { "fmsubd",	F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
1895 { "fnmsubs",	F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
1896 { "fnmsubd",	F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
1897 { "fnmadds",	F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, v9b },
1898 { "fnmaddd",	F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, v9b },
1899 { "fumadds",	F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
1900 { "fumaddd",	F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
1901 { "fumsubs",	F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
1902 { "fumsubd",	F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
1903 { "fnumsubs",	F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
1904 { "fnumsubd",	F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
1905 { "fnumadds",	F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, v9b },
1906 { "fnumaddd",	F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, v9b },
1907 { "addxc",	F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, v9b },
1908 { "addxccc",	F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, v9b },
1909 { "random",	F3F(2, 0x36, 0x015), F3F(~2, ~0x36, ~0x015), "H", F_FLOAT, HWCAP_RANDOM, v9b },
1910 { "umulxhi",	F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, v9b },
1911 { "lzd",	F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, v9b },
1912 { "cmask8",	F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, v9b },
1913 { "cmask16",	F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, v9b },
1914 { "cmask32",	F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, v9b },
1915 { "fsll16",	F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, v9b },
1916 { "fsrl16",	F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, v9b },
1917 { "fsll32",	F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, v9b },
1918 { "fsrl32",	F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, v9b },
1919 { "fslas16",	F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, v9b },
1920 { "fsra16",	F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, v9b },
1921 { "fslas32",	F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, v9b },
1922 { "fsra32",	F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, v9b },
1923 { "pdistn",	F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, v9b },
1924 { "fmean16",	F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, v9b },
1925 { "fpadd64",	F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, v9b },
1926 { "fchksm16",	F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, v9b },
1927 { "fpsub64",	F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, v9b },
1928 { "fpadds16",	F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, v9b },
1929 { "fpadds16s",	F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, v9b },
1930 { "fpadds32",	F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, v9b },
1931 { "fpadds32s",	F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, v9b },
1932 { "fpsubs16",	F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, v9b },
1933 { "fpsubs16s",	F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, v9b },
1934 { "fpsubs32",	F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, v9b },
1935 { "fpsubs32s",	F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, v9b },
1936 { "movdtox",	F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, v9b },
1937 { "movstouw",	F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
1938 { "movstosw",	F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, v9b },
1939 { "movxtod",	F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, v9b },
1940 { "movwtos",	F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, v9b },
1941 { "xmulx",	F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, v9b },
1942 { "xmulxhi",	F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, v9b },
1943 { "fucmple8",	F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, v9b },
1944 { "fucmpne8",	F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, v9b },
1945 { "fucmpgt8",	F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, v9b },
1946 { "fucmpeq8",	F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, v9b },
1947 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
1948 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, v9b },
1949 { "des_ip",     F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, v9b },
1950 { "des_iip",    F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, v9b },
1951 { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, v9b },
1952 {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, v9b },
1953 { "camellia_fi",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
1954 {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
1955 { "md5",        F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, v9b },
1956 { "sha1",       F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, v9b },
1957 { "sha256",     F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, v9b },
1958 { "sha512",     F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, v9b },
1959 { "crc32c",     F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, v9b },
1960 { "mpmul",      F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, v9b },
1961 { "montmul",    F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, v9b },
1962 { "montsqr",    F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, v9b },
1963 {"aes_eround01",  F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1964 {"aes_eround23",  F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1965 {"aes_dround01",  F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1966 {"aes_dround23",  F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1967 {"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1968 {"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1969 {"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1970 {"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, v9b },
1971 {"aes_kexpand1",  F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, v9b },
1972 {"des_round",     F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, v9b },
1973 {"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
1974 {"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, v9b },
1975 {"camellia_f",    F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, v9b },
1976 { "flcmps",	CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, v9b },
1977 { "flcmps",	CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, v9b },
1978 { "flcmps",	CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, v9b },
1979 { "flcmps",	CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, v9b },
1980 { "flcmpd",	CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, v9b },
1981 { "flcmpd",	CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, v9b },
1982 { "flcmpd",	CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, v9b },
1983 { "flcmpd",	CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, v9b },
1984 
1985 /* More v9 specific insns, these need to come last so they do not clash
1986    with v9a instructions such as "edge8" which looks like impdep1. */
1987 
1988 #define IMPDEP(name, code) \
1989 { name,	F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, v9notv9a }, \
1990 { name,	F3(2, code, 1), F3(~2, ~code, ~1),	   "1,i,d", 0, 0, v9notv9a }, \
1991 { name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,1,2,d", 0, 0, v9notv9a }, \
1992 { name, F3(2, code, 0), F3(~2, ~code, ~0),         "x,e,f,g", 0, 0, v9notv9a }
1993 
1994 IMPDEP ("impdep1", 0x36),
1995 IMPDEP ("impdep2", 0x37),
1996 
1997 #undef IMPDEP
1998 
1999 };
2000 
2001 const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
2002 
2003 /* Utilities for argument parsing.  */
2004 
2005 typedef struct
2006 {
2007   int value;
2008   const char *name;
2009 } arg;
2010 
2011 /* Look up NAME in TABLE.  */
2012 
2013 static int
2014 lookup_name (const arg *table, const char *name)
2015 {
2016   const arg *p;
2017 
2018   for (p = table; p->name; ++p)
2019     if (strcmp (name, p->name) == 0)
2020       return p->value;
2021 
2022   return -1;
2023 }
2024 
2025 /* Look up VALUE in TABLE.  */
2026 
2027 static const char *
2028 lookup_value (const arg *table, int value)
2029 {
2030   const arg *p;
2031 
2032   for (p = table; p->name; ++p)
2033     if (value == p->value)
2034       return p->name;
2035 
2036   return NULL;
2037 }
2038 
2039 /* Handle ASI's.  */
2040 
2041 static arg asi_table[] =
2042 {
2043   /* These are in the v9 architecture manual.  */
2044   /* The shorter versions appear first, they're here because Sun's as has them.
2045      Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2046      UltraSPARC architecture manual).  */
2047   { 0x04, "#ASI_N" },
2048   { 0x0c, "#ASI_N_L" },
2049   { 0x10, "#ASI_AIUP" },
2050   { 0x11, "#ASI_AIUS" },
2051   { 0x18, "#ASI_AIUP_L" },
2052   { 0x19, "#ASI_AIUS_L" },
2053   { 0x80, "#ASI_P" },
2054   { 0x81, "#ASI_S" },
2055   { 0x82, "#ASI_PNF" },
2056   { 0x83, "#ASI_SNF" },
2057   { 0x88, "#ASI_P_L" },
2058   { 0x89, "#ASI_S_L" },
2059   { 0x8a, "#ASI_PNF_L" },
2060   { 0x8b, "#ASI_SNF_L" },
2061   { 0x04, "#ASI_NUCLEUS" },
2062   { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2063   { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2064   { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2065   { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2066   { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2067   { 0x80, "#ASI_PRIMARY" },
2068   { 0x81, "#ASI_SECONDARY" },
2069   { 0x82, "#ASI_PRIMARY_NOFAULT" },
2070   { 0x83, "#ASI_SECONDARY_NOFAULT" },
2071   { 0x88, "#ASI_PRIMARY_LITTLE" },
2072   { 0x89, "#ASI_SECONDARY_LITTLE" },
2073   { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2074   { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2075   /* These are UltraSPARC and Niagara extensions.  */
2076   { 0x14, "#ASI_PHYS_USE_EC" },
2077   { 0x15, "#ASI_PHYS_BYPASS_EC_E" },
2078   { 0x16, "#ASI_BLK_AIUP_4V" },
2079   { 0x17, "#ASI_BLK_AIUS_4V" },
2080   { 0x1c, "#ASI_PHYS_USE_EC_L" },
2081   { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L" },
2082   { 0x1e, "#ASI_BLK_AIUP_L_4V" },
2083   { 0x1f, "#ASI_BLK_AIUS_L_4V" },
2084   { 0x20, "#ASI_SCRATCHPAD" },
2085   { 0x21, "#ASI_MMU" },
2086   { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS" },
2087   { 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
2088   { 0x25, "#ASI_QUEUE" },
2089   { 0x26, "#ASI_QUAD_LDD_PHYS_4V" },
2090   { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L" },
2091   { 0x30, "#ASI_PCACHE_DATA_STATUS" },
2092   { 0x31, "#ASI_PCACHE_DATA" },
2093   { 0x32, "#ASI_PCACHE_TAG" },
2094   { 0x33, "#ASI_PCACHE_SNOOP_TAG" },
2095   { 0x34, "#ASI_QUAD_LDD_PHYS" },
2096   { 0x38, "#ASI_WCACHE_VALID_BITS" },
2097   { 0x39, "#ASI_WCACHE_DATA" },
2098   { 0x3a, "#ASI_WCACHE_TAG" },
2099   { 0x3b, "#ASI_WCACHE_SNOOP_TAG" },
2100   { 0x3c, "#ASI_QUAD_LDD_PHYS_L" },
2101   { 0x40, "#ASI_SRAM_FAST_INIT" },
2102   { 0x41, "#ASI_CORE_AVAILABLE" },
2103   { 0x41, "#ASI_CORE_ENABLE_STAT" },
2104   { 0x41, "#ASI_CORE_ENABLE" },
2105   { 0x41, "#ASI_XIR_STEERING" },
2106   { 0x41, "#ASI_CORE_RUNNING_RW" },
2107   { 0x41, "#ASI_CORE_RUNNING_W1S" },
2108   { 0x41, "#ASI_CORE_RUNNING_W1C" },
2109   { 0x41, "#ASI_CORE_RUNNING_STAT" },
2110   { 0x41, "#ASI_CMT_ERROR_STEERING" },
2111   { 0x41, "#ASI_DCACHE_INVALIDATE" },
2112   { 0x41, "#ASI_DCACHE_UTAG" },
2113   { 0x41, "#ASI_DCACHE_SNOOP_TAG" },
2114   { 0x42, "#ASI_DCACHE_INVALIDATE" },
2115   { 0x43, "#ASI_DCACHE_UTAG" },
2116   { 0x44, "#ASI_DCACHE_SNOOP_TAG" },
2117   { 0x45, "#ASI_LSU_CONTROL_REG" },
2118   { 0x45, "#ASI_DCU_CONTROL_REG" },
2119   { 0x46, "#ASI_DCACHE_DATA" },
2120   { 0x47, "#ASI_DCACHE_TAG" },
2121   { 0x48, "#ASI_INTR_DISPATCH_STAT" },
2122   { 0x49, "#ASI_INTR_RECEIVE" },
2123   { 0x4a, "#ASI_UPA_CONFIG" },
2124   { 0x4a, "#ASI_JBUS_CONFIG" },
2125   { 0x4a, "#ASI_SAFARI_CONFIG" },
2126   { 0x4a, "#ASI_SAFARI_ADDRESS" },
2127   { 0x4b, "#ASI_ESTATE_ERROR_EN" },
2128   { 0x4c, "#ASI_AFSR" },
2129   { 0x4d, "#ASI_AFAR" },
2130   { 0x4e, "#ASI_EC_TAG_DATA" },
2131   { 0x50, "#ASI_IMMU" },
2132   { 0x51, "#ASI_IMMU_TSB_8KB_PTR" },
2133   { 0x52, "#ASI_IMMU_TSB_16KB_PTR" },
2134   { 0x54, "#ASI_ITLB_DATA_IN" },
2135   { 0x55, "#ASI_ITLB_DATA_ACCESS" },
2136   { 0x56, "#ASI_ITLB_TAG_READ" },
2137   { 0x57, "#ASI_IMMU_DEMAP" },
2138   { 0x58, "#ASI_DMMU" },
2139   { 0x59, "#ASI_DMMU_TSB_8KB_PTR" },
2140   { 0x5a, "#ASI_DMMU_TSB_64KB_PTR" },
2141   { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR" },
2142   { 0x5c, "#ASI_DTLB_DATA_IN" },
2143   { 0x5d, "#ASI_DTLB_DATA_ACCESS" },
2144   { 0x5e, "#ASI_DTLB_TAG_READ" },
2145   { 0x5f, "#ASI_DMMU_DEMAP" },
2146   { 0x60, "#ASI_IIU_INST_TRAP" },
2147   { 0x63, "#ASI_INTR_ID" },
2148   { 0x63, "#ASI_CORE_ID" },
2149   { 0x63, "#ASI_CESR_ID" },
2150   { 0x66, "#ASI_IC_INSTR" },
2151   { 0x67, "#ASI_IC_TAG" },
2152   { 0x68, "#ASI_IC_STAG" },
2153   { 0x6e, "#ASI_IC_PRE_DECODE" },
2154   { 0x6f, "#ASI_IC_NEXT_FIELD" },
2155   { 0x6f, "#ASI_BRPRED_ARRAY" },
2156   { 0x70, "#ASI_BLK_AIUP" },
2157   { 0x71, "#ASI_BLK_AIUS" },
2158   { 0x72, "#ASI_MCU_CTRL_REG" },
2159   { 0x74, "#ASI_EC_DATA" },
2160   { 0x75, "#ASI_EC_CTRL" },
2161   { 0x76, "#ASI_EC_W" },
2162   { 0x77, "#ASI_UDB_ERROR_W" },
2163   { 0x77, "#ASI_UDB_CONTROL_W" },
2164   { 0x77, "#ASI_INTR_W" },
2165   { 0x77, "#ASI_INTR_DATAN_W" },
2166   { 0x77, "#ASI_INTR_DISPATCH_W" },
2167   { 0x78, "#ASI_BLK_AIUPL" },
2168   { 0x79, "#ASI_BLK_AIUSL" },
2169   { 0x7e, "#ASI_EC_R" },
2170   { 0x7f, "#ASI_UDBH_ERROR_R" },
2171   { 0x7f, "#ASI_UDBL_ERROR_R" },
2172   { 0x7f, "#ASI_UDBH_CONTROL_R" },
2173   { 0x7f, "#ASI_UDBL_CONTROL_R" },
2174   { 0x7f, "#ASI_INTR_R" },
2175   { 0x7f, "#ASI_INTR_DATAN_R" },
2176   { 0xc0, "#ASI_PST8_P" },
2177   { 0xc1, "#ASI_PST8_S" },
2178   { 0xc2, "#ASI_PST16_P" },
2179   { 0xc3, "#ASI_PST16_S" },
2180   { 0xc4, "#ASI_PST32_P" },
2181   { 0xc5, "#ASI_PST32_S" },
2182   { 0xc8, "#ASI_PST8_PL" },
2183   { 0xc9, "#ASI_PST8_SL" },
2184   { 0xca, "#ASI_PST16_PL" },
2185   { 0xcb, "#ASI_PST16_SL" },
2186   { 0xcc, "#ASI_PST32_PL" },
2187   { 0xcd, "#ASI_PST32_SL" },
2188   { 0xd0, "#ASI_FL8_P" },
2189   { 0xd1, "#ASI_FL8_S" },
2190   { 0xd2, "#ASI_FL16_P" },
2191   { 0xd3, "#ASI_FL16_S" },
2192   { 0xd8, "#ASI_FL8_PL" },
2193   { 0xd9, "#ASI_FL8_SL" },
2194   { 0xda, "#ASI_FL16_PL" },
2195   { 0xdb, "#ASI_FL16_SL" },
2196   { 0xe0, "#ASI_BLK_COMMIT_P", },
2197   { 0xe1, "#ASI_BLK_COMMIT_S", },
2198   { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P" },
2199   { 0xf0, "#ASI_BLK_P", },
2200   { 0xf1, "#ASI_BLK_S", },
2201   { 0xf8, "#ASI_BLK_PL", },
2202   { 0xf9, "#ASI_BLK_SL", },
2203   { 0, 0 }
2204 };
2205 
2206 /* Return the value for ASI NAME, or -1 if not found.  */
2207 
2208 int
2209 sparc_encode_asi (const char *name)
2210 {
2211   return lookup_name (asi_table, name);
2212 }
2213 
2214 /* Return the name for ASI value VALUE or NULL if not found.  */
2215 
2216 const char *
2217 sparc_decode_asi (int value)
2218 {
2219   return lookup_value (asi_table, value);
2220 }
2221 
2222 /* Handle membar masks.  */
2223 
2224 static arg membar_table[] =
2225 {
2226   { 0x40, "#Sync" },
2227   { 0x20, "#MemIssue" },
2228   { 0x10, "#Lookaside" },
2229   { 0x08, "#StoreStore" },
2230   { 0x04, "#LoadStore" },
2231   { 0x02, "#StoreLoad" },
2232   { 0x01, "#LoadLoad" },
2233   { 0, 0 }
2234 };
2235 
2236 /* Return the value for membar arg NAME, or -1 if not found.  */
2237 
2238 int
2239 sparc_encode_membar (const char *name)
2240 {
2241   return lookup_name (membar_table, name);
2242 }
2243 
2244 /* Return the name for membar value VALUE or NULL if not found.  */
2245 
2246 const char *
2247 sparc_decode_membar (int value)
2248 {
2249   return lookup_value (membar_table, value);
2250 }
2251 
2252 /* Handle prefetch args.  */
2253 
2254 static arg prefetch_table[] =
2255 {
2256   { 0, "#n_reads" },
2257   { 1, "#one_read" },
2258   { 2, "#n_writes" },
2259   { 3, "#one_write" },
2260   { 4, "#page" },
2261   { 16, "#invalidate" },
2262   { 17, "#unified", },
2263   { 20, "#n_reads_strong", },
2264   { 21, "#one_read_strong", },
2265   { 22, "#n_writes_strong", },
2266   { 23, "#one_write_strong", },
2267   { 0, 0 }
2268 };
2269 
2270 /* Return the value for prefetch arg NAME, or -1 if not found.  */
2271 
2272 int
2273 sparc_encode_prefetch (const char *name)
2274 {
2275   return lookup_name (prefetch_table, name);
2276 }
2277 
2278 /* Return the name for prefetch value VALUE or NULL if not found.  */
2279 
2280 const char *
2281 sparc_decode_prefetch (int value)
2282 {
2283   return lookup_value (prefetch_table, value);
2284 }
2285 
2286 /* Handle sparclet coprocessor registers.  */
2287 
2288 static arg sparclet_cpreg_table[] =
2289 {
2290   { 0, "%ccsr" },
2291   { 1, "%ccfr" },
2292   { 2, "%cccrcr" },
2293   { 3, "%ccpr" },
2294   { 4, "%ccsr2" },
2295   { 5, "%cccrr" },
2296   { 6, "%ccrstr" },
2297   { 0, 0 }
2298 };
2299 
2300 /* Return the value for sparclet cpreg arg NAME, or -1 if not found.  */
2301 
2302 int
2303 sparc_encode_sparclet_cpreg (const char *name)
2304 {
2305   return lookup_name (sparclet_cpreg_table, name);
2306 }
2307 
2308 /* Return the name for sparclet cpreg value VALUE or NULL if not found.  */
2309 
2310 const char *
2311 sparc_decode_sparclet_cpreg (int value)
2312 {
2313   return lookup_value (sparclet_cpreg_table, value);
2314 }
2315