1 /* Table of opcodes for the sparc. 2 Copyright (C) 1989-2024 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with this file; see the file COPYING. If not, write to the 18 Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, 19 MA 02110-1301, USA. */ 20 21 22 /* FIXME-someday: perhaps the ,a's and such should be embedded in the 23 instruction's name rather than the args. This would make gas faster, pinsn 24 slower, but would mess up some macros a bit. xoxorich. */ 25 26 #include "sysdep.h" 27 #include <stdio.h> 28 #include "opcode/sparc.h" 29 30 /* Some defines to make life easy. */ 31 #define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6) 32 #define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7) 33 #define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8) 34 #define MASK_LEON SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_LEON) 35 #define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET) 36 #define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE) 37 #define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) 38 #define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A) 39 #define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B) 40 #define MASK_V9C SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9C) 41 #define MASK_V9D SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9D) 42 #define MASK_V9E SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9E) 43 #define MASK_V9V SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9V) 44 #define MASK_V9M SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9M) 45 #define MASK_M8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_M8) 46 47 /* Bit masks of architectures supporting the insn. */ 48 49 #define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 50 | MASK_SPARCLET | MASK_SPARCLITE \ 51 | MASK_V9 | MASK_V9A | MASK_V9B \ 52 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 53 | MASK_M8) 54 /* v6 insns not supported on the sparclet. */ 55 #define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 56 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \ 57 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 58 | MASK_M8) 59 #define v7 (MASK_V7 | MASK_V8 | MASK_LEON | MASK_SPARCLET \ 60 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B \ 61 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 62 | MASK_M8) 63 /* Although not all insns are implemented in hardware, sparclite is defined 64 to be a superset of v8. Unimplemented insns trap and are then theoretically 65 implemented in software. 66 It's not clear that the same is true for sparclet, although the docs 67 suggest it is. Rather than complicating things, the sparclet assembler 68 recognizes all v8 insns. */ 69 #define v8 (MASK_V8 | MASK_LEON | MASK_SPARCLET | MASK_SPARCLITE \ 70 | MASK_V9 | MASK_V9A | MASK_V9B \ 71 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 72 | MASK_M8) 73 #define sparclet (MASK_SPARCLET) 74 #define leon (MASK_LEON) 75 /* sparclet insns supported by leon. */ 76 #define letandleon (MASK_SPARCLET | MASK_LEON) 77 #define sparclite (MASK_SPARCLITE) 78 #define v9 (MASK_V9 | MASK_V9A | MASK_V9B \ 79 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 80 | MASK_M8) 81 /* v9 insns supported by leon. */ 82 #define v9andleon (MASK_V9 | MASK_V9A | MASK_V9B \ 83 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 84 | MASK_M8 | MASK_LEON) 85 #define v9a (MASK_V9A | MASK_V9B \ 86 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 87 | MASK_M8) 88 #define v9b (MASK_V9B \ 89 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 90 | MASK_M8) 91 #define v9c (MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M \ 92 | MASK_M8) 93 #define v9d (MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8) 94 #define v9e (MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8) 95 #define v9v (MASK_V9V | MASK_V9M | MASK_M8) 96 #define v9m (MASK_V9M | MASK_M8) 97 #define m8 (MASK_M8) 98 99 /* v6 insns not supported by v9. */ 100 #define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON \ 101 | MASK_SPARCLET | MASK_SPARCLITE) 102 /* v9a instructions which would appear to be aliases to v9's impdep's 103 otherwise. */ 104 #define v9notv9a (MASK_V9) 105 106 /* Hardware capability sets, used to keep sparc_opcode_archs easy to 107 read. */ 108 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD 109 #define HWS_V9 HWS_V8 | HWCAP_POPC 110 #define HWS_VA HWS_V9 | HWCAP_VIS 111 #define HWS_VB HWS_VA | HWCAP_VIS2 112 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT 113 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC 114 #define HWS_VE HWS_VD \ 115 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ 116 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ 117 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE 118 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA 119 #define HWS_VM HWS_VV 120 #define HWS_VM8 HWS_VM 121 122 #define HWS2_VM \ 123 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ 124 | HWCAP2_XMPMUL | HWCAP2_XMONT 125 #define HWS2_VM8 HWS2_VM \ 126 | HWCAP2_SPARC6 | HWCAP2_ONADDSUB | HWCAP2_ONMUL | HWCAP2_ONDIV \ 127 | HWCAP2_DICTUNP | HWCAP2_FPCMPSHL | HWCAP2_RLE | HWCAP2_SHA3 128 129 130 /* Table of opcode architectures. 131 The order is defined in opcode/sparc.h. */ 132 133 const struct sparc_opcode_arch sparc_opcode_archs[] = 134 { 135 { "v6", MASK_V6, 0, 0 }, 136 { "v7", MASK_V6 | MASK_V7, 0, 0 }, 137 { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 }, 138 { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, 0 }, 139 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET, HWS_V8, 0 }, 140 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE, HWS_V8, 0 }, 141 /* ??? Don't some v8 priviledged insns conflict with v9? */ 142 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9, HWS_V9, 0 }, 143 /* v9 with ultrasparc additions */ 144 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A, HWS_VA, 0 }, 145 /* v9 with cheetah additions */ 146 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B, HWS_VB, 0 }, 147 /* v9 with UA2005 and T1 additions. */ 148 { "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 149 | MASK_V9C), HWS_VC, 0 }, 150 /* v9 with UA2007 and T3 additions. */ 151 { "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 152 | MASK_V9C | MASK_V9D), HWS_VD, 0 }, 153 /* v9 with OSA2011 and T4 additions modulus integer multiply-add. */ 154 { "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 155 | MASK_V9C | MASK_V9D | MASK_V9E), HWS_VE, 0 }, 156 /* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp 157 multiply-add. */ 158 { "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 159 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V), HWS_VV, 0 }, 160 /* v9 with OSA2015 and M7 additions. */ 161 { "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 162 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M), HWS_VM, HWS2_VM }, 163 /* v9 with OSA2017 and M8 additions. */ 164 { "m8", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B 165 | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M | MASK_M8), 166 HWS_VM8, HWS2_VM8 }, 167 { NULL, 0, 0, 0 } 168 }; 169 170 /* Given NAME, return it's architecture entry. */ 171 172 enum sparc_opcode_arch_val 173 sparc_opcode_lookup_arch (const char *name) 174 { 175 const struct sparc_opcode_arch *p; 176 177 for (p = &sparc_opcode_archs[0]; p->name; ++p) 178 if (strcmp (name, p->name) == 0) 179 return (enum sparc_opcode_arch_val) (p - &sparc_opcode_archs[0]); 180 181 return SPARC_OPCODE_ARCH_BAD; 182 } 183 184 /* Branch condition field. */ 185 #define COND(x) (((x) & 0xf) << 25) 186 187 /* Compare And Branch condition field. */ 188 #define CBCOND(x) (((x) & 0x1f) << 25) 189 190 /* v9: Move (MOVcc and FMOVcc) condition field. */ 191 #define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */ 192 193 /* v9: Move register (MOVRcc and FMOVRcc) condition field. */ 194 #define RCOND(x) (((x) & 0x7) << 10) /* v9 */ 195 196 #define CONDA (COND (0x8)) 197 #define CONDCC (COND (0xd)) 198 #define CONDCS (COND (0x5)) 199 #define CONDE (COND (0x1)) 200 #define CONDG (COND (0xa)) 201 #define CONDGE (COND (0xb)) 202 #define CONDGU (COND (0xc)) 203 #define CONDL (COND (0x3)) 204 #define CONDLE (COND (0x2)) 205 #define CONDLEU (COND (0x4)) 206 #define CONDN (COND (0x0)) 207 #define CONDNE (COND (0x9)) 208 #define CONDNEG (COND (0x6)) 209 #define CONDPOS (COND (0xe)) 210 #define CONDVC (COND (0xf)) 211 #define CONDVS (COND (0x7)) 212 213 #define CONDNZ CONDNE 214 #define CONDZ CONDE 215 #define CONDGEU CONDCC 216 #define CONDLU CONDCS 217 218 #define FCONDA (COND (0x8)) 219 #define FCONDE (COND (0x9)) 220 #define FCONDG (COND (0x6)) 221 #define FCONDGE (COND (0xb)) 222 #define FCONDL (COND (0x4)) 223 #define FCONDLE (COND (0xd)) 224 #define FCONDLG (COND (0x2)) 225 #define FCONDN (COND (0x0)) 226 #define FCONDNE (COND (0x1)) 227 #define FCONDO (COND (0xf)) 228 #define FCONDU (COND (0x7)) 229 #define FCONDUE (COND (0xa)) 230 #define FCONDUG (COND (0x5)) 231 #define FCONDUGE (COND (0xc)) 232 #define FCONDUL (COND (0x3)) 233 #define FCONDULE (COND (0xe)) 234 235 #define FCONDNZ FCONDNE 236 #define FCONDZ FCONDE 237 238 #define ICC (0) /* v9 */ 239 #define XCC (1 << 12) /* v9 */ 240 #define CBCOND_XCC (1 << 21) 241 #define FCC(x) (((x) & 0x3) << 11) /* v9 */ 242 #define FBFCC(x) (((x) & 0x3) << 20) /* v9 */ 243 244 /* The order of the opcodes in the table is significant: 245 246 * The assembler requires that all instances of the same mnemonic must 247 be consecutive. If they aren't, the assembler will bomb at runtime. 248 249 * The disassembler should not care about the order of the opcodes. */ 250 251 /* Entries for commutative arithmetic operations. */ 252 /* ??? More entries can make use of this. */ 253 #define COMMUTEOP(opcode, op3, arch_mask) \ 254 { opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, 0, 0, arch_mask }, \ 255 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, 0, 0, arch_mask }, \ 256 { opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, 0, 0, arch_mask } 257 258 const struct sparc_opcode sparc_opcodes[] = { 259 260 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, 0, 0, v6 }, 261 { "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 262 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, 0, 0, v6 }, 263 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, 0, 0, v6 }, 264 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 265 { "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 266 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, 0, 0, v6 }, 267 { "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 268 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, 0, 0, v6 }, 269 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, 0, 0, v6 }, 270 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, 0, 0, v6 }, 271 { "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 272 273 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, 0, 0, v6 }, 274 { "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+%g0],d */ 275 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, 0, 0, v6 }, 276 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, 0, 0, v6 }, 277 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, 0, 0, v6 }, 278 { "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, 0, 0, v6 }, /* ld [rs1+0],d */ 279 280 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, 0, 0, v6notv9 }, 281 { "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ 282 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, 0, 0, v6notv9 }, 283 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, 0, 0, v6notv9 }, 284 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 }, 285 { "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */ 286 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, 0, 0, v6notv9 }, 287 { "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+%g0],d */ 288 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, 0, 0, v6notv9 }, 289 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, 0, 0, v6notv9 }, 290 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, 0, 0, v6notv9 }, 291 { "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, 0, 0, v6notv9 }, /* ld [rs1+0],d */ 292 293 /* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the 294 'ld' pseudo-op in v9. */ 295 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, 0, 0, v9 }, 296 { "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+%g0],d */ 297 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, 0, 0, v9 }, 298 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, 0, 0, v9 }, 299 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v9 }, 300 { "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 301 302 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 303 { "ldtw", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 304 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, 0, 0, v9 }, 305 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, 0, 0, v9 }, 306 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 307 { "ldtw", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 308 309 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", F_ALIAS, 0, 0, v6 }, 310 { "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */ 311 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", F_ALIAS, 0, 0, v6 }, 312 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", F_ALIAS, 0, 0, v6 }, 313 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", F_ALIAS, 0, 0, v6 }, 314 { "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */ 315 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", F_ALIAS, 0, 0, v6 }, 316 { "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+%g0],d */ 317 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", F_ALIAS, 0, 0, v6 }, 318 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", F_ALIAS, 0, 0, v6 }, 319 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", F_ALIAS, 0, 0, v6 }, 320 { "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", F_ALIAS, 0, 0, v6 }, /* ldd [rs1+0],d */ 321 322 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, 0, 0, v6notv9 }, 323 { "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+%g0],d */ 324 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, 0, 0, v6notv9 }, 325 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, 0, 0, v6notv9 }, 326 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, 0, 0, v6notv9 }, 327 { "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, 0, 0, v6notv9 }, /* ldd [rs1+0],d */ 328 329 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, 0, 0, v9 }, 330 { "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 331 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, 0, 0, v9 }, 332 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, 0, 0, v9 }, 333 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, 0, 0, v9 }, 334 { "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 335 336 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 337 { "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+%g0],d */ 338 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, 0, 0, v6 }, 339 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, 0, 0, v6 }, 340 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 341 { "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsb [rs1+0],d */ 342 343 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+%g0],d */ 344 { "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 345 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, 0, 0, v6 }, 346 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, 0, 0, v6 }, 347 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 348 { "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldsh [rs1+0],d */ 349 350 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 351 { "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+%g0],d */ 352 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, 0, 0, v6 }, 353 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, 0, 0, v6 }, 354 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 355 { "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldstub [rs1+0],d */ 356 357 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 358 { "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+%g0],d */ 359 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, 0, 0, v9 }, 360 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, 0, 0, v9 }, 361 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 362 { "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldsw [rs1+0],d */ 363 364 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 365 { "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+%g0],d */ 366 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, 0, 0, v6 }, 367 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, 0, 0, v6 }, 368 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 369 { "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* ldub [rs1+0],d */ 370 371 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v6 }, 372 { "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+%g0],d */ 373 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, 0, 0, v6 }, 374 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, 0, 0, v6 }, 375 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, 0, 0, v6 }, 376 { "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v6 }, /* lduh [rs1+0],d */ 377 378 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v9 }, 379 { "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+%g0],d */ 380 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, 0, 0, v9 }, 381 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, 0, 0, v9 }, 382 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, 0, 0, v9 }, 383 { "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v9 }, /* ldx [rs1+0],d */ 384 385 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, 0, 0, v9 }, 386 { "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, 0, 0, v9 }, /* ld [rs1+%g0],d */ 387 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, 0, 0, v9 }, 388 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, 0, 0, v9 }, 389 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, 0, 0, v9 }, 390 { "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 391 392 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RD(~3), "[1+2],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1+rs2],%efsr */ 393 { "ldx", F3(3, 0x21, 0)|RD(3), F3(~3, ~0x21, ~0)|RS2_G0|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [rs1],%efsr */ 394 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[1+i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1+0],%efsr */ 395 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RD(~3), "[i+1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0+%rs1],%efsr */ 396 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|RS1_G0|RD(~3),"[i],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [0],%efsr */ 397 { "ldx", F3(3, 0x21, 1)|RD(3), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~3),"[1],(", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, /* ldx [%rs1], %efsr */ 398 399 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 400 { "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lda [rs1+%g0],d */ 401 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 402 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 403 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 404 { "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 405 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, 0, 0, v9 }, 406 { "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 407 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, 0, 0, v9 }, 408 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, 0, 0, v9 }, 409 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, 0, 0, v9 }, 410 { "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 411 412 /* Note that the LDTXA instructions share an opcode with the 413 (deprecated) LDTWA instructions below. They are differenciated by 414 the combination of the `i' instruction field and the ASI used in 415 the instruction. */ 416 417 #define ldtxa(asi) \ 418 { "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi)), "[1+2]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c }, \ 419 { "ldtxa", F3(3, 0x13, 0)|ASI((asi)), F3(~3, ~0x13, ~0)|ASI(~(asi))|RS2_G0, "[1]A,d", 0, HWCAP_ASI_BLK_INIT, 0, v9c } 420 421 ldtxa (0x22), /* #ASI_TWINX_AIUP */ 422 ldtxa (0x23), /* #ASI_TWINX_AIUS */ 423 ldtxa (0x26), /* #ASI_TWINX_REAL */ 424 ldtxa (0x27), /* #ASI_TWINX_N */ 425 ldtxa (0x2A), /* #ASI_TWINX_AIUP_L */ 426 ldtxa (0x2B), /* #ASI_TWINX_AIUS_L */ 427 ldtxa (0x2E), /* #ASI_TWINX_REAL_L */ 428 ldtxa (0x2F), /* #ASI_TWINX_NL */ 429 ldtxa (0xE2), /* #ASI_TWINX_P */ 430 ldtxa (0xE3), /* #ASI_TWINX_S */ 431 ldtxa (0xEA), /* #ASI_TWINX_PL */ 432 ldtxa (0xEB), /* #ASI_TWINX_SL */ 433 434 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 435 { "ldtwa", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */ 436 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 437 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 438 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 439 { "ldtwa", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 440 441 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v6 }, 442 { "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v6 }, /* ldda [rs1+%g0],d */ 443 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 }, 444 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 }, 445 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 }, 446 { "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 447 448 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, 0, 0, v9 }, 449 { "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, 0, 0, v9 }, /* ldda [rs1+%g0],d */ 450 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, 0, 0, v9 }, 451 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, 0, 0, v9 }, 452 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, 0, 0, v9 }, 453 { "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 454 455 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, 0, 0, v9 }, 456 { "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, 0, 0, v9 }, /* ldd [rs1+%g0],d */ 457 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, 0, 0, v9 }, 458 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, 0, 0, v9 }, 459 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, 0, 0, v9 }, 460 { "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, 0, 0, v9 }, /* ldd [rs1+0],d */ 461 462 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 463 { "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsba [rs1+%g0],d */ 464 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 465 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 466 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 467 { "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 468 469 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 470 { "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldsha [rs1+%g0],d */ 471 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 472 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 473 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 474 { "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 475 476 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 477 { "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* ldstuba [rs1+%g0],d */ 478 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 479 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 480 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 481 { "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 482 483 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 484 { "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 485 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 486 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 487 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 488 { "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 489 490 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 491 { "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduba [rs1+%g0],d */ 492 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 493 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 494 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 495 { "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 496 497 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, 0, 0, v6 }, 498 { "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v6 }, /* lduha [rs1+%g0],d */ 499 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 500 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 501 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 502 { "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 503 504 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, 0, 0, v9 }, /* lduwa === lda */ 505 { "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, 0, 0, v9 }, /* lda [rs1+%g0],d */ 506 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, 0, 0, v9 }, 507 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, 0, 0, v9 }, 508 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, 0, 0, v9 }, 509 { "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, 0, 0, v9 }, /* ld [rs1+0],d */ 510 511 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, 0, 0, v9 }, 512 { "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, 0, 0, v9 }, /* lda [rs1+%g0],d */ 513 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 514 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 515 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 516 { "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* ld [rs1+0],d */ 517 518 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 519 { "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */ 520 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, 0, 0, v6 }, 521 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, 0, 0, v6 }, 522 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 523 { "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 524 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, 0, 0, v6 }, 525 { "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, 0, 0, v6 }, /* st d[rs1+%g0] */ 526 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, 0, 0, v6 }, 527 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, 0, 0, v6 }, 528 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, 0, 0, v6 }, 529 { "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 530 531 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 }, 532 { "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ 533 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, 0, 0, v6notv9 }, 534 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, 0, 0, v6notv9 }, 535 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 }, 536 { "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */ 537 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, 0, 0, v6notv9 }, 538 { "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+%g0] */ 539 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, 0, 0, v6notv9 }, 540 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, 0, 0, v6notv9 }, 541 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, 0, 0, v6notv9 }, 542 { "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, 0, 0, v6notv9 }, /* st d,[rs1+0] */ 543 544 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, 0, 0, v6 }, 545 { "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+%g0] */ 546 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, 0, 0, v6 }, 547 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, 0, 0, v6 }, 548 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, 0, 0, v6 }, 549 { "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, 0, 0, v6 }, /* st d,[rs1+0] */ 550 551 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 552 { "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 553 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 554 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 555 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 556 { "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 557 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 558 { "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 559 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 560 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 561 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 562 { "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 563 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v9 }, 564 { "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+%g0] */ 565 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v9 }, 566 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v9 }, 567 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v9 }, 568 { "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 569 570 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 571 { "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+%g0] */ 572 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 573 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 574 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 575 { "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* st d,[rs1+0] */ 576 577 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 578 { "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* sta d,[rs1+%g0] */ 579 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 580 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 581 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 582 { "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */ 583 584 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, 0, 0, v9 }, 585 { "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 586 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, 0, 0, v9 }, 587 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, 0, 0, v9 }, 588 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, 0, 0, v9 }, 589 { "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, 0, 0, v9 }, /* st d,[rs1+0] */ 590 591 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 592 { "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 593 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 594 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 595 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 596 { "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 597 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 598 { "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 599 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 600 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 601 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 602 { "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 603 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v9 }, 604 { "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v9 }, /* sta d,[rs1+%g0] */ 605 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 606 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 607 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 608 { "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* st d,[rs1+0] */ 609 610 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 611 { "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 612 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, 0, 0, v6 }, 613 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, 0, 0, v6 }, 614 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 615 { "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* stb d,[rs1+0] */ 616 617 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 618 { "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 619 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 620 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 621 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 622 { "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */ 623 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 624 { "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+%g0] */ 625 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 626 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 627 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 628 { "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* stb d,[rs1+0] */ 629 630 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 631 { "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 632 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 633 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 634 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 635 { "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stb d,[rs1+0] */ 636 637 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 638 { "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 639 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 640 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 641 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 642 { "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */ 643 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 644 { "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stba d,[rs1+%g0] */ 645 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 646 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 647 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 648 { "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* stb d,[rs1+0] */ 649 650 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 }, 651 { "sttw", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+%g0] */ 652 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, 0, 0, v9 }, 653 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, 0, 0, v9 }, 654 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 }, 655 { "sttw", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 656 657 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_PREF_ALIAS, 0, 0, v6 }, 658 { "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */ 659 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_PREF_ALIAS, 0, 0, v6 }, 660 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_PREF_ALIAS, 0, 0, v6 }, 661 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_PREF_ALIAS, 0, 0, v6 }, 662 { "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_PREF_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */ 663 664 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, 0, 0, v6notv9 }, 665 { "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 666 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, 0, 0, v6notv9 }, 667 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, 0, 0, v6notv9 }, 668 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, 0, 0, v6notv9 }, 669 { "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 670 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, 0, 0, v6 }, 671 { "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+%g0] */ 672 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, 0, 0, v6 }, 673 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, 0, 0, v6 }, 674 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, 0, 0, v6 }, 675 { "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, 0, 0, v6 }, /* std d,[rs1+0] */ 676 677 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, 0, 0, v6notv9 }, 678 { "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 679 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, 0, 0, v6notv9 }, 680 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, 0, 0, v6notv9 }, 681 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, 0, 0, v6notv9 }, 682 { "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 683 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, 0, 0, v6notv9 }, 684 { "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+%g0] */ 685 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, 0, 0, v6notv9 }, 686 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, 0, 0, v6notv9 }, 687 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, 0, 0, v6notv9 }, 688 { "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, 0, 0, v6notv9 }, /* std d,[rs1+0] */ 689 690 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 691 { "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+%g0] */ 692 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 693 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 694 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 695 { "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* std d,[rs1+0] */ 696 697 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, 0, 0, v9 }, 698 { "sttwa", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */ 699 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 700 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 701 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 702 { "sttwa", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 703 704 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 705 { "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stda d,[rs1+%g0] */ 706 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 707 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 708 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 709 { "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* std d,[rs1+0] */ 710 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, 0, 0, v9 }, 711 { "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, 0, 0, v9 }, /* stda d,[rs1+%g0] */ 712 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, 0, 0, v9 }, 713 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, 0, 0, v9 }, 714 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, 0, 0, v9 }, 715 { "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, 0, 0, v9 }, /* std d,[rs1+0] */ 716 717 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v6 }, 718 { "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 719 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, 0, 0, v6 }, 720 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, 0, 0, v6 }, 721 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v6 }, 722 { "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v6 }, /* sth d,[rs1+0] */ 723 724 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 725 { "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 726 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 727 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 728 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 729 { "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */ 730 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, 0, 0, v6 }, 731 { "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+%g0] */ 732 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, 0, 0, v6 }, 733 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, 0, 0, v6 }, 734 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, 0, 0, v6 }, 735 { "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, 0, 0, v6 }, /* sth d,[rs1+0] */ 736 737 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, 0, 0, v6 }, 738 { "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 739 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 740 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 741 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 742 { "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* sth d,[rs1+0] */ 743 744 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 745 { "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 746 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 747 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 748 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 749 { "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */ 750 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, 0, 0, v6 }, 751 { "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, 0, 0, v6 }, /* stha ,[rs1+%g0] */ 752 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, 0, 0, v9 }, 753 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, 0, 0, v9 }, 754 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, 0, 0, v9 }, 755 { "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, 0, 0, v9 }, /* sth d,[rs1+0] */ 756 757 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, 0, 0, v9 }, 758 { "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */ 759 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, 0, 0, v9 }, 760 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, 0, 0, v9 }, 761 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, 0, 0, v9 }, 762 { "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 763 764 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, 0, 0, v9 }, 765 { "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+%g0] */ 766 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, 0, 0, v9 }, 767 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, 0, 0, v9 }, 768 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, 0, 0, v9 }, 769 { "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 770 771 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, 0, 0, v9 }, 772 { "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, 0, 0, v9 }, /* stxa d,[rs1+%g0] */ 773 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, 0, 0, v9 }, 774 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, 0, 0, v9 }, 775 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, 0, 0, v9 }, 776 { "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, 0, 0, v9 }, /* stx d,[rs1+0] */ 777 778 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, 0, 0, v9 }, 779 { "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+%g0] */ 780 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, 0, 0, v9 }, 781 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, 0, 0, v9 }, 782 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, 0, 0, v9 }, 783 { "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, 0, 0, v9 }, /* stq [rs1+0] */ 784 785 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, 0, 0, v9 }, 786 { "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, 0, 0, v9 }, /* stqa [rs1+%g0] */ 787 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, 0, 0, v9 }, 788 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, 0, 0, v9 }, 789 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, 0, 0, v9 }, 790 { "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, 0, 0, v9 }, /* stqa [rs1+0] */ 791 792 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, 0, 0, v7 }, 793 { "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+%g0],d */ 794 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, 0, 0, v7 }, 795 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, 0, 0, v7 }, 796 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, 0, 0, v7 }, 797 { "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, 0, 0, v7 }, /* swap [rs1+0],d */ 798 799 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, 0, 0, v7 }, 800 { "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, 0, 0, v7 }, /* swapa [rs1+%g0],d */ 801 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, 0, 0, v9 }, 802 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, 0, 0, v9 }, 803 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, 0, 0, v9 }, 804 { "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, 0, 0, v9 }, /* swap [rs1+0],d */ 805 806 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 807 { "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v6 }, /* restore %g0,%g0,%g0 */ 808 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, 0, 0, v6 }, 809 { "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, 0, 0, v6 }, /* restore %g0,0,%g0 */ 810 811 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+rs2 */ 812 { "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1,%g0 */ 813 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+X */ 814 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */ 815 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X+rs1 */ 816 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett X */ 817 { "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6notv9 }, /* rett rs1+0 */ 818 819 { "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 820 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, 0, 0, v6 }, 821 { "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "i,1,d", 0, 0, 0, v6 }, /* Sun assembler compatibility */ 822 { "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, 0, 0, v6 }, 823 824 { "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %i7+8,%g0 */ 825 { "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %o7+8,%g0 */ 826 827 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, 0, 0, v6 }, 828 { "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,d */ 829 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,d */ 830 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,d */ 831 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, 0, 0, v6 }, 832 { "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, 0, 0, v6 }, 833 834 { "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 835 { "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 836 { "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 837 { "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 838 { "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 839 { "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 840 { "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 841 { "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, 0, 0, v9 }, 842 { "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, 0, 0, v9 }, 843 844 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "[1+2]", 0, 0, 0, v9 }, 845 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+%g0 */ 846 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "[1]", 0, 0, 0, v9 }, /* flush rs1+0 */ 847 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "[i]", 0, 0, 0, v9 }, /* flush %g0+i */ 848 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[1+i]", 0, 0, 0, v9 }, 849 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "[i+1]", 0, 0, 0, v9 }, 850 851 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v8 }, 852 { "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+%g0 */ 853 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v8 }, /* flush rs1+0 */ 854 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v8 }, /* flush %g0+i */ 855 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v8 }, 856 { "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v8 }, 857 858 /* IFLUSH was renamed to FLUSH in v8. */ 859 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, 0, 0, v6 }, 860 { "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+%g0 */ 861 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, 0, 0, v6 }, /* flush rs1+0 */ 862 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, 0, 0, v6 }, 863 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, 0, 0, v6 }, 864 { "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, 0, 0, v6 }, 865 866 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, 0, 0, v9 }, 867 { "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, 0, 0, v9 }, /* return rs1+%g0 */ 868 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, 0, 0, v9 }, /* return rs1+0 */ 869 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, 0, 0, v9 }, /* return %g0+i */ 870 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, 0, 0, v9 }, 871 { "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, 0, 0, v9 }, 872 873 { "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, 0, 0, v9 }, 874 875 { "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, 0, 0, v9 }, 876 { "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, 0, 0, v8 }, 877 878 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, 0, 0, v9 }, 879 { "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */ 880 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, 0, 0, v9 }, 881 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, 0, 0, v9 }, 882 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, 0, 0, v9 }, 883 { "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, 0, 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */ 884 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, 0, 0, v9 }, 885 { "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, 0, 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */ 886 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, 0, 0, v9 }, 887 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, 0, 0, v9 }, 888 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, 0, 0, v9 }, 889 { "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, 0, 0, v9 }, /* prefetcha [rs1+0],d */ 890 891 { "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 892 { "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 893 { "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 894 { "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 895 { "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, 0, 0, v6 }, 896 { "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, 0, 0, v6 }, 897 898 { "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 899 { "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 900 { "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 901 { "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 902 { "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, 0, 0, v9 }, 903 { "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, 0, 0, v9 }, 904 905 { "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 906 { "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, 0, 0, v6 }, 907 908 { "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclite }, 909 { "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, 0, 0, sparclite }, 910 911 { "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet|sparclite }, 912 { "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, 0, 0, sparclet|sparclite }, 913 914 { "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, HWCAP_POPC, 0, v9 }, 915 { "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, HWCAP_POPC, 0, v9 }, 916 917 { "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,%g0,d */ 918 { "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, 0, 0, v6 }, /* or %g0,0,d */ 919 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 920 { "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+%g0] */ 921 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 922 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 923 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 924 { "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* st %g0,[rs1+0] */ 925 926 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 927 { "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+%g0] */ 928 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 929 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 930 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 931 { "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* stb %g0,[rs1+0] */ 932 933 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v6 }, 934 { "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+%g0] */ 935 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v6 }, 936 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v6 }, 937 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v6 }, 938 { "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v6 }, /* sth %g0,[rs1+0] */ 939 940 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, 0, 0, v9 }, 941 { "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+%g0] */ 942 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, 0, 0, v9 }, 943 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, 0, 0, v9 }, 944 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, 0, 0, v9 }, 945 { "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, 0, 0, v9 }, /* stx %g0,[rs1+0] */ 946 947 { "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 948 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, 0, 0, v6 }, 949 { "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, 0, 0, v6 }, 950 951 /* This is not a commutative instruction. */ 952 { "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 953 { "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, 0, 0, v6 }, 954 955 /* This is not a commutative instruction. */ 956 { "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 957 { "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, 0, 0, v6 }, 958 959 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, %g0, %g0 */ 960 { "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, 0, 0, v6 }, /* orcc %g0, rs2, %g0 */ 961 { "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, 0, 0, v6 }, /* orcc rs1, 0, %g0 */ 962 963 964 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, 0, 0, v8 }, /* wr r,r,%asrX */ 965 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, 0, 0, v8 }, /* wr r,i,%asrX */ 966 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */ 967 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */ 968 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%asrX */ 969 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_PREF_ALIAS, 0, 0, v8 }, /* wr rs1,%g0,%asrX */ 970 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, 0, 0, v6 }, /* wr r,r,%y */ 971 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, 0, 0, v6 }, /* wr r,i,%y */ 972 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */ 973 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */ 974 { "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,0,%y */ 975 { "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_PREF_ALIAS, 0, 0, v6 }, /* wr rs1,%g0,%y */ 976 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, 0, 0, v6notv9 }, /* wr r,r,%psr */ 977 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, 0, 0, v6notv9 }, /* wr r,i,%psr */ 978 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */ 979 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */ 980 { "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%psr */ 981 { "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%psr */ 982 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, 0, 0, v6notv9 }, /* wr r,r,%wim */ 983 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, 0, 0, v6notv9 }, /* wr r,i,%wim */ 984 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */ 985 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */ 986 { "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%wim */ 987 { "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%wim */ 988 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, 0, 0, v6notv9 }, /* wr r,r,%tbr */ 989 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, 0, 0, v6notv9 }, /* wr r,i,%tbr */ 990 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ 991 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */ 992 { "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,0,%tbr */ 993 { "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_PREF_ALIAS, 0, 0, v6notv9 }, /* wr rs1,%g0,%tbr */ 994 995 { "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, 0, 0, v9 }, /* wr r,r,%ccr */ 996 { "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, 0, 0, v9 }, /* wr r,i,%ccr */ 997 { "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, 0, 0, v9 }, /* wr r,r,%asi */ 998 { "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, 0, 0, v9 }, /* wr r,i,%asi */ 999 { "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, 0, 0, v9 }, /* wr r,r,%fprs */ 1000 { "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, 0, 0, v9 }, /* wr r,i,%fprs */ 1001 { "wr", F3(2, 0x30, 0)|RD(14), F3(~2, ~0x30, ~0)|RD(~14), "1,2,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,r,%mcdper */ 1002 { "wr", F3(2, 0x30, 1)|RD(14), F3(~2, ~0x30, ~1)|RD(~14), "1,i,{", 0, 0, HWCAP2_SPARC5, v9m }, /* wr r,i,%mcdper */ 1003 1004 /* Write to ASR registers 16..31, which is the range defined in SPARC 1005 V9 for implementation-dependent uses. Note that the read-only ASR 1006 registers can't be used in a `wr' instruction. */ 1007 1008 #define wrasr(asr,hwcap,hwcap2,arch) \ 1009 { "wr", F3(2, 0x30, 0)|RD((asr)), F3(~2, ~0x30, ~0)|RD(~(asr))|ASI(~0), "1,2,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,r,%asr */ \ 1010 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "1,i,_", 0, (hwcap), (hwcap2), (arch) }, /* wr r,i,%asr */ \ 1011 { "wr", F3(2, 0x30, 1)|RD((asr)), F3(~2, ~0x30, ~1)|RD(~(asr)), "i,1,_", F_ALIAS, (hwcap), (hwcap2), (arch) } /* wr i,r,%asr */ 1012 1013 wrasr (16, HWCAP_VIS, 0, v9a), /* wr ...,%pcr */ 1014 wrasr (17, HWCAP_VIS, 0, v9a), /* wr ...,%pic */ 1015 wrasr (18, HWCAP_VIS, 0, v9a), /* wr ...,%dcr */ 1016 wrasr (19, HWCAP_VIS, 0, v9a), /* wr ...,%gsr */ 1017 wrasr (20, HWCAP_VIS, 0, v9a), /* wr ...,%softint_set */ 1018 wrasr (21, HWCAP_VIS, 0, v9a), /* wr ...,%softint_clear */ 1019 wrasr (22, HWCAP_VIS, 0, v9a), /* wr ...,%softint */ 1020 wrasr (23, HWCAP_VIS, 0, v9a), /* wr ...,%tick_cmpr */ 1021 wrasr (24, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick */ 1022 wrasr (25, HWCAP_VIS2, 0, v9b), /* wr ...,%sys_tick_cmpr */ 1023 wrasr (26, HWCAP_CBCOND, 0, v9e), /* wr ...,%cfr */ 1024 wrasr (27, HWCAP_PAUSE, 0, v9e), /* wr ...,%pause */ 1025 wrasr (28, 0, HWCAP2_MWAIT, v9m), /* wr ...,%mwait */ 1026 1027 { "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI(~0), "1,2,p", 0, 0, 0, leon }, /* pwr r,r,%psr */ 1028 { "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1), "1,i,p", 0, 0, 0, leon }, /* pwr r,i,%psr */ 1029 { "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|ASI(~0), "2,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,rs2,%psr */ 1030 { "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|RS1_G0, "i,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr %g0,i,%psr */ 1031 { "pwr", F3(2, 0x31, 1)|RD(1), F3(~2, ~0x31, ~1)|RD(~1)|SIMM13(~0), "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,0,%psr */ 1032 { "pwr", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|ASI_RS2(~0), "1,p", F_PREF_ALIAS, 0, 0, leon }, /* pwr rs1,%g0,%psr */ 1033 1034 { "pause", F3(2, 0x30, 1)|RD(27)|RS1(0), F3(~2, ~0x30, ~1)|RD(~27)|RS1(~0), "i", 0, HWCAP_PAUSE, 0, v9e }, /* wr %g0,i,%pause */ 1035 1036 { "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, 0, 0, v9 }, /* rd %ccr,r */ 1037 { "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, 0, 0, v9 }, /* rd %asi,r */ 1038 { "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, 0, 0, v9 }, /* rd %tick,r */ 1039 { "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, 0, 0, v9 }, /* rd %pc,r */ 1040 { "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, 0, 0, v9 }, /* rd %fprs,r */ 1041 { "rd", F3(2, 0x28, 0)|RS1(13), F3(~2, ~0x28, ~0)|RS1(~13)|SIMM13(~0), "&,d", 0, 0, HWCAP2_SPARC6, m8 }, /* rd %entropy,r */ 1042 { "rd", F3(2, 0x28, 0)|RS1(14), F3(~2, ~0x28, ~0)|RS1(~14)|SIMM13(~0), "{,d", 0, 0, HWCAP2_SPARC5, v9m }, /* rd %mcdper,r */ 1043 1044 /* Read from ASR registers 16..31, which is the range defined in SPARC 1045 V9 for implementation-dependent uses. Note that the write-only ASR 1046 registers can't be used in a `rd' instruction. */ 1047 1048 #define rdasr(asr,hwcap,hwcap2,arch) \ 1049 { "rd", F3(2, 0x28, 0)|RS1((asr)), F3(~2, ~0x28, ~0)|RS1(~(asr))|SIMM13(~0), "/,d", 0, (hwcap), (hwcap2), (arch) } 1050 1051 rdasr (16, HWCAP_VIS, 0, v9a), /* rd %pcr,r */ 1052 rdasr (17, HWCAP_VIS, 0, v9a), /* rd %pic,r */ 1053 rdasr (18, HWCAP_VIS, 0, v9a), /* rd %dcr,r */ 1054 rdasr (19, HWCAP_VIS, 0, v9a), /* rd %gsr,r */ 1055 rdasr (22, HWCAP_VIS, 0, v9a), /* rd %softint,r */ 1056 rdasr (23, HWCAP_VIS, 0, v9a), /* rd %tick_cmpr,r */ 1057 rdasr (24, HWCAP_VIS2, 0, v9b), /* rd %sys_tick,r */ 1058 rdasr (25, HWCAP_VIS2, 0, v9b), /* rd %sys_tick_cmpr,r */ 1059 rdasr (26, HWCAP_CBCOND, 0, v9e), /* rd %cfr,r */ 1060 1061 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, 0, 0, v8 }, /* rd %asrX,r */ 1062 { "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, 0, 0, v6 }, /* rd %y,r */ 1063 { "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, 0, 0, v6notv9 }, /* rd %psr,r */ 1064 { "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, 0, 0, v6notv9 }, /* rd %wim,r */ 1065 { "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, 0, 0, v6notv9 }, /* rd %tbr,r */ 1066 1067 /* Instructions to read and write from/to privileged registers. */ 1068 1069 #define rdpr(reg,hwcap,hwcap2,arch) \ 1070 { "rdpr", F3(2, 0x2a, 0)|RS1((reg)), F3(~2, ~0x2a, ~0)|RS1(~(reg))|SIMM13(~0),"?,d", 0, (hwcap), (hwcap2), (arch) } /* rdpr %priv,r */ 1071 1072 rdpr (0, 0, 0, v9), /* rdpr %tpc,r */ 1073 rdpr (1, 0, 0, v9), /* rdpr %tnpc,r */ 1074 rdpr (2, 0, 0, v9), /* rdpr %tstate,r */ 1075 rdpr (3, 0, 0, v9), /* rdpr %tt,r */ 1076 rdpr (4, 0, 0, v9), /* rdpr %tick,r */ 1077 rdpr (5, 0, 0, v9), /* rdpr %tba,r */ 1078 rdpr (6, 0, 0, v9), /* rdpr %pstate,r */ 1079 rdpr (7, 0, 0, v9), /* rdpr %tl,r */ 1080 rdpr (8, 0, 0, v9), /* rdpr %pil,r */ 1081 rdpr (9, 0, 0, v9), /* rdpr %cwp,r */ 1082 rdpr (10, 0, 0, v9), /* rdpr %cansave,r */ 1083 rdpr (11, 0, 0, v9), /* rdpr %canrestore,r */ 1084 rdpr (12, 0, 0, v9), /* rdpr %cleanwin,r */ 1085 rdpr (13, 0, 0, v9), /* rdpr %otherwin,r */ 1086 rdpr (14, 0, 0, v9), /* rdpr %wstate,r */ 1087 rdpr (15, 0, 0, v9), /* rdpr %fq,r */ 1088 rdpr (16, 0, 0, v9), /* rdpr %gl,r */ 1089 rdpr (23, 0, HWCAP2_SPARC5, v9m), /* rdpr %pmcdper,r */ 1090 rdpr (31, 0, 0, v9), /* rdpr %ver,r */ 1091 1092 #define wrpr(reg,hwcap,hwcap2,arch) \ 1093 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg)), "1,2,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,r2,%priv */ \ 1094 { "wrpr", F3(2, 0x32, 0)|RD((reg)), F3(~2, ~0x32, ~0)|RD(~(reg))|SIMM13(~0), "1,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,%priv */ \ 1095 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "1,i,!", 0, (hwcap), (hwcap2), (arch) }, /* wrpr r1,i,%priv */ \ 1096 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg)), "i,1,!", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrpr i,r1,%priv */ \ 1097 { "wrpr", F3(2, 0x32, 1)|RD((reg)), F3(~2, ~0x32, ~1)|RD(~(reg))|RS1(~0), "i,!", 0, (hwcap), (hwcap2), (arch) } /* wrpr i,%priv */ 1098 1099 wrpr (0, 0, 0, v9), /* wrpr ...,%tpc */ 1100 wrpr (1, 0, 0, v9), /* wrpr ...,%tnpc */ 1101 wrpr (2, 0, 0, v9), /* wrpr ...,%tstate */ 1102 wrpr (3, 0, 0, v9), /* wrpr ...,%tt */ 1103 wrpr (4, 0, 0, v9), /* wrpr ...,%tick */ 1104 wrpr (5, 0, 0, v9), /* wrpr ...,%tba */ 1105 wrpr (6, 0, 0, v9), /* wrpr ...,%pstate */ 1106 wrpr (7, 0, 0, v9), /* wrpr ...,%tl */ 1107 wrpr (8, 0, 0, v9), /* wrpr ...,%pil */ 1108 wrpr (9, 0, 0, v9), /* wrpr ...,%cwp */ 1109 wrpr (10, 0, 0, v9), /* wrpr ...,%cansave */ 1110 wrpr (11, 0, 0, v9), /* wrpr ...,%canrestore */ 1111 wrpr (12, 0, 0, v9), /* wrpr ...,%cleanwin */ 1112 wrpr (13, 0, 0, v9), /* wrpr ...,%otherwin */ 1113 wrpr (14, 0, 0, v9), /* wrpr ...,%wstate */ 1114 wrpr (15, 0, 0, v9), /* wrpr ...,%fq */ 1115 wrpr (16, 0, 0, v9), /* wrpr ...,%gl */ 1116 wrpr (23, 0, HWCAP2_SPARC5, v9m), /* wdpr ...,%pmcdper */ 1117 wrpr (31, 0, 0, v9), /* wrpr ...,%ver */ 1118 1119 /* Instructions to read and write from/to hyperprivileged 1120 registers. */ 1121 1122 #define rdhpr(reg,hwcap,hwcap2,arch) \ 1123 { "rdhpr", F3(2, 0x29, 0)|RS1((reg)), F3(~2, ~0x29, ~0)|RS1(~(reg))|SIMM13(~0), "$,d", 0, (hwcap), (hwcap2), (arch) } 1124 1125 rdhpr (0, HWCAP_VIS, 0, v9a), /* rdhpr %hpstate,r */ 1126 rdhpr (1, HWCAP_VIS, 0, v9a), /* rdhpr %htstate,r */ 1127 rdhpr (3, HWCAP_VIS, 0, v9a), /* rdhpr %hintp,r */ 1128 rdhpr (5, HWCAP_VIS, 0, v9a), /* rdhpr %htba,r */ 1129 rdhpr (6, HWCAP_VIS, 0, v9a), /* rdhpr %hver,r */ 1130 rdhpr (23, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcdper,r */ 1131 rdhpr (24, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hmcddfr,r */ 1132 rdhpr (27, 0, HWCAP2_SPARC5, v9m), /* rdhpr %hva_mask_nz,r */ 1133 rdhpr (28, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_offset,r */ 1134 rdhpr (29, HWCAP_VIS, 0, v9a), /* rdhpar %hstick_enable,r */ 1135 rdhpr (31, HWCAP_VIS, 0, v9a), /* rdhpr %hstick_cmpr,r */ 1136 1137 #define wrhpr(reg,hwcap,hwcap2,arch) \ 1138 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg)),"1,2,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,r2,%hpriv */ \ 1139 { "wrhpr", F3(2, 0x33, 0)|RD((reg)), F3(~2, ~0x33, ~0)|RD(~(reg))|SIMM13(~0), "1,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,%hpriv */ \ 1140 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "1,i,%", 0, (hwcap), (hwcap2), (arch) }, /* wrhpr r1,i,%hpriv */ \ 1141 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg)), "i,1,%", F_ALIAS, (hwcap), (hwcap2), (arch) }, /* wrhpr i,r1,%hpriv */ \ 1142 { "wrhpr", F3(2, 0x33, 1)|RD((reg)), F3(~2, ~0x33, ~1)|RD(~(reg))|RS1(~0), "i,%", 0, (hwcap), (hwcap2), (arch) } /* wrhpr i,%hpriv */ 1143 1144 wrhpr (0, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hpstate */ 1145 wrhpr (1, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htstate */ 1146 wrhpr (3, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hintp */ 1147 wrhpr (5, HWCAP_VIS, 0, v9a), /* wrhpr ...,%htba */ 1148 wrhpr (23, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcdper */ 1149 wrhpr (24, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hmcddfr */ 1150 wrhpr (27, 0, HWCAP2_SPARC5, v9m), /* wrhpr ...,%hva_mask_nz */ 1151 wrhpr (28, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_offset */ 1152 wrhpr (29, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_enable */ 1153 wrhpr (31, HWCAP_VIS, 0, v9a), /* wrhpr ...,%hstick_cmpr */ 1154 1155 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, 0, 0, v8 }, /* rd %asr1,r */ 1156 { "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, 0, 0, v6 }, /* rd %y,r */ 1157 { "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %psr,r */ 1158 { "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %wim,r */ 1159 { "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, 0, 0, v6notv9 }, /* rd %tbr,r */ 1160 1161 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RS1_G0|ASI(~0), "2,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,rs2,%asrX */ 1162 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RS1_G0, "i,m", F_ALIAS, 0, 0, v8 }, /* wr %g0,i,%asrX */ 1163 { "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|RS1_G0|ASI(~0), "2,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,rs2,%y */ 1164 { "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|RS1_G0, "i,y", F_ALIAS, 0, 0, v6 }, /* wr %g0,i,%y */ 1165 { "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|RS1_G0|ASI(~0), "2,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%psr */ 1166 { "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|RS1_G0, "i,p", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%psr */ 1167 { "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|RS1_G0|ASI(~0), "2,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%wim */ 1168 { "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|RS1_G0, "i,w", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%wim */ 1169 { "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|RS1_G0|ASI(~0), "2,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,rs2,%tbr */ 1170 { "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|RS1_G0, "i,t", F_ALIAS, 0, 0, v6notv9 }, /* wr %g0,i,%tbr */ 1171 1172 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, 0, 0, v6 }, /* or %g0,rs2,d */ 1173 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, 0, 0, v6 }, /* or %g0,i,d */ 1174 { "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,%g0,d */ 1175 { "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, 0, 0, v6 }, /* or rs1,0,d */ 1176 1177 { "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1178 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, 0, 0, v6 }, 1179 { "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, 0, 0, v6 }, 1180 1181 { "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* or rd,rs2,rd */ 1182 { "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* or rd,i,rd */ 1183 1184 /* This is not a commutative instruction. */ 1185 { "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1186 { "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, 0, 0, v6 }, 1187 1188 /* This is not a commutative instruction. */ 1189 { "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1190 { "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, 0, 0, v6 }, 1191 1192 { "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* andn rd,rs2,rd */ 1193 { "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* andn rd,i,rd */ 1194 1195 { "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, 0, 0, v6 }, /* subcc rs1,rs2,%g0 */ 1196 { "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, 0, 0, v6 }, /* subcc rs1,i,%g0 */ 1197 1198 { "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1199 { "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, 0, 0, v6 }, 1200 1201 { "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1202 { "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, 0, 0, v6 }, 1203 1204 { "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1205 { "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1206 { "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1207 { "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, 0, 0, v9 }, 1208 1209 { "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1210 { "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1211 { "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1212 { "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, 0, 0, v9 }, 1213 1214 { "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1215 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, 0, 0, v6 }, 1216 { "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, 0, 0, v6 }, 1217 1218 { "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1219 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, 0, 0, v6 }, 1220 { "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, 0, 0, v6 }, 1221 1222 { "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* sub rd,1,rd */ 1223 { "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* sub rd,imm,rd */ 1224 { "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* subcc rd,1,rd */ 1225 { "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* subcc rd,imm,rd */ 1226 { "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* add rd,1,rd */ 1227 { "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* add rd,imm,rd */ 1228 { "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, 0, 0, v6 }, /* addcc rd,1,rd */ 1229 { "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, 0, 0, v8 }, /* addcc rd,imm,rd */ 1230 1231 { "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, 0, 0, v6 }, /* andcc rs1,rs2,%g0 */ 1232 { "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, 0, 0, v6 }, /* andcc rs1,i,%g0 */ 1233 1234 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, 0, 0, v6 }, /* sub %g0,rs2,rd */ 1235 { "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, 0, 0, v6 }, /* sub %g0,rd,rd */ 1236 1237 { "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1238 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, 0, 0, v6 }, 1239 { "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, 0, 0, v6 }, 1240 { "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1241 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, 0, 0, v6 }, 1242 { "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, 0, 0, v6 }, 1243 1244 { "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1245 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1246 { "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v6notv9 }, 1247 { "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1248 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, 0, 0, v9 }, 1249 { "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, 0, 0, v9 }, 1250 1251 { "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6notv9 }, 1252 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v6notv9 }, 1253 { "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v6notv9 }, 1254 { "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1255 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, 0, 0, v9 }, 1256 { "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, 0, 0, v9 }, 1257 1258 { "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1259 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1260 { "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1261 { "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1262 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1263 { "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1264 { "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1265 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1266 { "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1267 { "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, HWCAP_MUL32, 0, v8 }, 1268 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, HWCAP_MUL32, 0, v8 }, 1269 { "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, HWCAP_MUL32, 0, v8 }, 1270 { "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1271 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1272 { "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1273 { "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1274 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1275 { "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1276 { "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1277 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1278 { "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1279 { "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, HWCAP_DIV32, 0, v8 }, 1280 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, HWCAP_DIV32, 0, v8 }, 1281 { "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, HWCAP_DIV32, 0, v8 }, 1282 1283 { "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1284 { "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, 0, 0, v9 }, 1285 { "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1286 { "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, v9 }, 1287 { "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9 }, 1288 { "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, 0, 0, v9 }, 1289 1290 { "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, 0, 0, v6 }, 1291 { "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1292 1293 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%o7 */ 1294 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1295 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%o7 */ 1296 { "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1297 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%o7 */ 1298 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1299 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%o7 */ 1300 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1301 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%o7 */ 1302 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1303 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%o7 */ 1304 { "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, 0, 0, v6 }, 1305 1306 /* Conditional instructions. 1307 1308 Because this part of the table was such a mess earlier, I have 1309 macrofied it so that all the branches and traps are generated from 1310 a single-line description of each condition value. John Gilmore. */ 1311 1312 /* Define branches -- one annulled, one without, etc. */ 1313 #define br(opcode, mask, lose, flags) \ 1314 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), 0, 0, v6 }, \ 1315 { opcode, (mask) , (lose)|ANNUL, "l", (flags), 0, 0, v6 } 1316 1317 #define brx(opcode, mask, lose, flags) /* v9 */ \ 1318 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), 0, 0, v9 }, \ 1319 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), 0, 0, v9 }, \ 1320 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), 0, 0, v9 }, \ 1321 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), 0, 0, v9 }, \ 1322 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), 0, 0, v9 }, \ 1323 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), 0, 0, v9 }, \ 1324 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), 0, 0, v9 }, \ 1325 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), 0, 0, v9 }, \ 1326 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), 0, 0, v9 }, \ 1327 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), 0, 0, v9 }, \ 1328 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), 0, 0, v9 }, \ 1329 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), 0, 0, v9 } 1330 1331 /* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */ 1332 #define tr(opcode, mask, lose, flags) \ 1333 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), 0, 0, v9 }, /* %g0 + imm */ \ 1334 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), 0, 0, v9 }, /* rs1 + imm */ \ 1335 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), 0, 0, v9 }, /* rs1 + rs2 */ \ 1336 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), 0, 0, v9 }, /* rs1 + %g0 */ \ 1337 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, 0, 0, v9 }, /* %g0 + imm */ \ 1338 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + imm */ \ 1339 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + rs2 */ \ 1340 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, 0, 0, v9 }, /* rs1 + %g0 */ \ 1341 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), 0, 0, v6 }, /* %g0 + imm */ \ 1342 { opcode, (mask)|IMMED, (lose), "1+i", (flags), 0, 0, v6 }, /* rs1 + imm */ \ 1343 { opcode, (mask)|IMMED, (lose), "i+1", (flags), 0, 0, v6 }, /* imm + rs1 */ \ 1344 { opcode, (mask), IMMED|(lose), "1+2", (flags), 0, 0, v6 }, /* rs1 + rs2 */ \ 1345 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), 0, 0, v6 } /* rs1 + %g0 */ 1346 1347 /* v9: We must put `brx' before `br', to ensure that we never match something 1348 v9: against an expression unless it is an expression. Otherwise, we end 1349 v9: up with undefined symbol tables entries, because they get added, but 1350 v9: are not deleted if the pattern fails to match. */ 1351 1352 /* Define both branches and traps based on condition mask */ 1353 #define cond(bop, top, mask, flags) \ 1354 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \ 1355 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \ 1356 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR))) 1357 1358 /* Define all the conditions, all the branches, all the traps. */ 1359 1360 /* Standard branch, trap mnemonics */ 1361 cond ("b", "ta", CONDA, F_UNBR), 1362 /* Alternative form (just for assembly, not for disassembly) */ 1363 cond ("ba", "t", CONDA, F_UNBR|F_ALIAS), 1364 1365 cond ("bcc", "tcc", CONDCC, F_CONDBR), 1366 cond ("bcs", "tcs", CONDCS, F_CONDBR), 1367 cond ("be", "te", CONDE, F_CONDBR), 1368 cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS), 1369 cond ("bg", "tg", CONDG, F_CONDBR), 1370 cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS), 1371 cond ("bge", "tge", CONDGE, F_CONDBR), 1372 cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */ 1373 cond ("bgu", "tgu", CONDGU, F_CONDBR), 1374 cond ("bl", "tl", CONDL, F_CONDBR), 1375 cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS), 1376 cond ("ble", "tle", CONDLE, F_CONDBR), 1377 cond ("bleu", "tleu", CONDLEU, F_CONDBR), 1378 cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */ 1379 cond ("bn", "tn", CONDN, F_CONDBR), 1380 cond ("bne", "tne", CONDNE, F_CONDBR), 1381 cond ("bneg", "tneg", CONDNEG, F_CONDBR), 1382 cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */ 1383 cond ("bpos", "tpos", CONDPOS, F_CONDBR), 1384 cond ("bvc", "tvc", CONDVC, F_CONDBR), 1385 cond ("bvs", "tvs", CONDVS, F_CONDBR), 1386 cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */ 1387 1388 #undef cond 1389 #undef br 1390 #undef brr /* v9 */ 1391 #undef tr 1392 1393 #define brr(opcode, mask, lose, flags) /* v9 */ \ 1394 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1395 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1396 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1397 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1398 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), 0, 0, v9 }, \ 1399 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), 0, 0, v9 } 1400 1401 #define condr(bop, mask, flags) /* v9 */ \ 1402 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */ 1403 1404 /* v9 */ condr("brnz", 0x5, F_CONDBR), 1405 /* v9 */ condr("brz", 0x1, F_CONDBR), 1406 /* v9 */ condr("brgez", 0x7, F_CONDBR), 1407 /* v9 */ condr("brlz", 0x3, F_CONDBR), 1408 /* v9 */ condr("brlez", 0x2, F_CONDBR), 1409 /* v9 */ condr("brgz", 0x6, F_CONDBR), 1410 1411 #define cbcond(cop, cmask, flgs) \ 1412 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(0),F2(~0,~3)|CBCOND(~(cmask))|F3I(~0)|CBCOND_XCC, \ 1413 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1414 { "cw" cop, F2(0, 3)|CBCOND(cmask)|F3I(1),F2(~0,~3)|CBCOND(~(cmask))|F3I(~1)|CBCOND_XCC, \ 1415 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1416 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(0)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~0), \ 1417 "1,2,=", flgs, HWCAP_CBCOND, 0, v9e}, \ 1418 { "cx" cop, F2(0, 3)|CBCOND(cmask)|F3I(1)|CBCOND_XCC,F2(~0,~3)|CBCOND(~(cmask))|F3I(~1), \ 1419 "1,X,=", flgs, HWCAP_CBCOND, 0, v9e}, 1420 1421 cbcond("be", 0x09, F_CONDBR) 1422 cbcond("bz", 0x09, F_CONDBR|F_ALIAS) 1423 cbcond("ble", 0x0a, F_CONDBR) 1424 cbcond("bl", 0x0b, F_CONDBR) 1425 cbcond("bleu", 0x0c, F_CONDBR) 1426 cbcond("bcs", 0x0d, F_CONDBR) 1427 cbcond("blu", 0x0d, F_CONDBR|F_ALIAS) 1428 cbcond("bneg", 0x0e, F_CONDBR) 1429 cbcond("bvs", 0x0f, F_CONDBR) 1430 cbcond("bne", 0x19, F_CONDBR) 1431 cbcond("bnz", 0x19, F_CONDBR|F_ALIAS) 1432 cbcond("bg", 0x1a, F_CONDBR) 1433 cbcond("bge", 0x1b, F_CONDBR) 1434 cbcond("bgu", 0x1c, F_CONDBR) 1435 cbcond("bcc", 0x1d, F_CONDBR) 1436 cbcond("bgeu", 0x1d, F_CONDBR|F_ALIAS) 1437 cbcond("bpos", 0x1e, F_CONDBR) 1438 cbcond("bvc", 0x1f, F_CONDBR) 1439 1440 #undef cbcond 1441 #undef condr /* v9 */ 1442 #undef brr /* v9 */ 1443 1444 #define movr(opcode, mask, flags) /* v9 */ \ 1445 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), 0, 0, v9 }, \ 1446 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), 0, 0, v9 } 1447 1448 #define fmrrs(opcode, mask, lose, flags) /* v9 */ \ 1449 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, 0, 0, v9 } 1450 #define fmrrd(opcode, mask, lose, flags) /* v9 */ \ 1451 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, 0, 0, v9 } 1452 #define fmrrq(opcode, mask, lose, flags) /* v9 */ \ 1453 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, 0, 0, v9 } 1454 1455 #define fmovrs(mop, mask, flags) /* v9 */ \ 1456 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */ 1457 #define fmovrd(mop, mask, flags) /* v9 */ \ 1458 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */ 1459 #define fmovrq(mop, mask, flags) /* v9 */ \ 1460 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */ 1461 1462 /* v9 */ movr("movrne", 0x5, 0), 1463 /* v9 */ movr("movre", 0x1, 0), 1464 /* v9 */ movr("movrgez", 0x7, 0), 1465 /* v9 */ movr("movrlz", 0x3, 0), 1466 /* v9 */ movr("movrlez", 0x2, 0), 1467 /* v9 */ movr("movrgz", 0x6, 0), 1468 /* v9 */ movr("movrnz", 0x5, F_ALIAS), 1469 /* v9 */ movr("movrz", 0x1, F_ALIAS), 1470 1471 /* v9 */ fmovrs("fmovrsne", 0x5, 0), 1472 /* v9 */ fmovrs("fmovrse", 0x1, 0), 1473 /* v9 */ fmovrs("fmovrsgez", 0x7, 0), 1474 /* v9 */ fmovrs("fmovrslz", 0x3, 0), 1475 /* v9 */ fmovrs("fmovrslez", 0x2, 0), 1476 /* v9 */ fmovrs("fmovrsgz", 0x6, 0), 1477 /* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS), 1478 /* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS), 1479 1480 /* v9 */ fmovrd("fmovrdne", 0x5, 0), 1481 /* v9 */ fmovrd("fmovrde", 0x1, 0), 1482 /* v9 */ fmovrd("fmovrdgez", 0x7, 0), 1483 /* v9 */ fmovrd("fmovrdlz", 0x3, 0), 1484 /* v9 */ fmovrd("fmovrdlez", 0x2, 0), 1485 /* v9 */ fmovrd("fmovrdgz", 0x6, 0), 1486 /* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS), 1487 /* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS), 1488 1489 /* v9 */ fmovrq("fmovrqne", 0x5, 0), 1490 /* v9 */ fmovrq("fmovrqe", 0x1, 0), 1491 /* v9 */ fmovrq("fmovrqgez", 0x7, 0), 1492 /* v9 */ fmovrq("fmovrqlz", 0x3, 0), 1493 /* v9 */ fmovrq("fmovrqlez", 0x2, 0), 1494 /* v9 */ fmovrq("fmovrqgz", 0x6, 0), 1495 /* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS), 1496 /* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS), 1497 1498 #undef movr /* v9 */ 1499 #undef fmovr /* v9 */ 1500 #undef fmrr /* v9 */ 1501 1502 #define movicc(opcode, cond, flags) /* v9 */ \ 1503 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, 0, 0, v9 }, \ 1504 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, 0, 0, v9 }, \ 1505 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, 0, 0, v9 }, \ 1506 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, 0, 0, v9 } 1507 1508 #define movfcc(opcode, fcond, flags) /* v9 */ \ 1509 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, 0, 0, v9 }, \ 1510 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, 0, 0, v9 }, \ 1511 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, 0, 0, v9 }, \ 1512 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, 0, 0, v9 }, \ 1513 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, 0, 0, v9 }, \ 1514 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, 0, 0, v9 }, \ 1515 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, 0, 0, v9 }, \ 1516 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, 0, 0, v9 } 1517 1518 #define movcc(opcode, cond, fcond, flags) /* v9 */ \ 1519 movfcc (opcode, fcond, flags), /* v9 */ \ 1520 movicc (opcode, cond, flags) /* v9 */ 1521 1522 /* v9 */ movcc ("mova", CONDA, FCONDA, 0), 1523 /* v9 */ movicc ("movcc", CONDCC, 0), 1524 /* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS), 1525 /* v9 */ movicc ("movcs", CONDCS, 0), 1526 /* v9 */ movicc ("movlu", CONDLU, F_ALIAS), 1527 /* v9 */ movcc ("move", CONDE, FCONDE, 0), 1528 /* v9 */ movcc ("movg", CONDG, FCONDG, 0), 1529 /* v9 */ movcc ("movge", CONDGE, FCONDGE, 0), 1530 /* v9 */ movicc ("movgu", CONDGU, 0), 1531 /* v9 */ movcc ("movl", CONDL, FCONDL, 0), 1532 /* v9 */ movcc ("movle", CONDLE, FCONDLE, 0), 1533 /* v9 */ movicc ("movleu", CONDLEU, 0), 1534 /* v9 */ movfcc ("movlg", FCONDLG, 0), 1535 /* v9 */ movcc ("movn", CONDN, FCONDN, 0), 1536 /* v9 */ movcc ("movne", CONDNE, FCONDNE, 0), 1537 /* v9 */ movicc ("movneg", CONDNEG, 0), 1538 /* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS), 1539 /* v9 */ movfcc ("movo", FCONDO, 0), 1540 /* v9 */ movicc ("movpos", CONDPOS, 0), 1541 /* v9 */ movfcc ("movu", FCONDU, 0), 1542 /* v9 */ movfcc ("movue", FCONDUE, 0), 1543 /* v9 */ movfcc ("movug", FCONDUG, 0), 1544 /* v9 */ movfcc ("movuge", FCONDUGE, 0), 1545 /* v9 */ movfcc ("movul", FCONDUL, 0), 1546 /* v9 */ movfcc ("movule", FCONDULE, 0), 1547 /* v9 */ movicc ("movvc", CONDVC, 0), 1548 /* v9 */ movicc ("movvs", CONDVS, 0), 1549 /* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS), 1550 1551 #undef movicc /* v9 */ 1552 #undef movfcc /* v9 */ 1553 #undef movcc /* v9 */ 1554 1555 #define FM_SF 1 /* v9 - values for fpsize */ 1556 #define FM_DF 2 /* v9 */ 1557 #define FM_QF 3 /* v9 */ 1558 1559 #define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \ 1560 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, 0, 0, v9 }, \ 1561 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, 0, 0, v9 } 1562 1563 #define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \ 1564 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, 0, 0, v9 }, \ 1565 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, 0, 0, v9 }, \ 1566 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, 0, 0, v9 }, \ 1567 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, 0, 0, v9 } 1568 1569 /* FIXME: use fmovicc/fmovfcc? */ /* v9 */ 1570 #define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \ 1571 { opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, 0, 0, v9 }, \ 1572 { opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, 0, 0, v9 }, \ 1573 { opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, 0, 0, v9 }, \ 1574 { opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, 0, 0, v9 }, \ 1575 { opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, 0, 0, v9 }, \ 1576 { opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, 0, 0, v9 } 1577 1578 #define fmovicc(suffix, cond, flags) /* v9 */ \ 1579 fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \ 1580 fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \ 1581 fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags) 1582 1583 #define fmovfcc(suffix, fcond, flags) /* v9 */ \ 1584 fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \ 1585 fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \ 1586 fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags) 1587 1588 #define fmovcc(suffix, cond, fcond, flags) /* v9 */ \ 1589 fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \ 1590 fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \ 1591 fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags) 1592 1593 /* v9 */ fmovcc ("a", CONDA, FCONDA, 0), 1594 /* v9 */ fmovicc ("cc", CONDCC, 0), 1595 /* v9 */ fmovicc ("cs", CONDCS, 0), 1596 /* v9 */ fmovcc ("e", CONDE, FCONDE, 0), 1597 /* v9 */ fmovcc ("g", CONDG, FCONDG, 0), 1598 /* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0), 1599 /* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS), 1600 /* v9 */ fmovicc ("gu", CONDGU, 0), 1601 /* v9 */ fmovcc ("l", CONDL, FCONDL, 0), 1602 /* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0), 1603 /* v9 */ fmovicc ("leu", CONDLEU, 0), 1604 /* v9 */ fmovfcc ("lg", FCONDLG, 0), 1605 /* v9 */ fmovicc ("lu", CONDLU, F_ALIAS), 1606 /* v9 */ fmovcc ("n", CONDN, FCONDN, 0), 1607 /* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0), 1608 /* v9 */ fmovicc ("neg", CONDNEG, 0), 1609 /* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS), 1610 /* v9 */ fmovfcc ("o", FCONDO, 0), 1611 /* v9 */ fmovicc ("pos", CONDPOS, 0), 1612 /* v9 */ fmovfcc ("u", FCONDU, 0), 1613 /* v9 */ fmovfcc ("ue", FCONDUE, 0), 1614 /* v9 */ fmovfcc ("ug", FCONDUG, 0), 1615 /* v9 */ fmovfcc ("uge", FCONDUGE, 0), 1616 /* v9 */ fmovfcc ("ul", FCONDUL, 0), 1617 /* v9 */ fmovfcc ("ule", FCONDULE, 0), 1618 /* v9 */ fmovicc ("vc", CONDVC, 0), 1619 /* v9 */ fmovicc ("vs", CONDVS, 0), 1620 /* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS), 1621 1622 #undef fmoviccx /* v9 */ 1623 #undef fmovfccx /* v9 */ 1624 #undef fmovccx /* v9 */ 1625 #undef fmovicc /* v9 */ 1626 #undef fmovfcc /* v9 */ 1627 #undef fmovcc /* v9 */ 1628 #undef FM_DF /* v9 */ 1629 #undef FM_QF /* v9 */ 1630 #undef FM_SF /* v9 */ 1631 1632 /* Coprocessor branches. */ 1633 #define CBR(opcode, mask, lose, flags, arch) \ 1634 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, 0, 0, arch }, \ 1635 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, 0, 0, arch } 1636 1637 /* Floating point branches. */ 1638 #define FBR(opcode, mask, lose, flags) \ 1639 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, 0, 0, v6 }, \ 1640 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, 0, 0, v6 } 1641 1642 /* V9 extended floating point branches. */ 1643 #define FBRX(opcode, mask, lose, flags) /* v9 */ \ 1644 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1645 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1646 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1647 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1648 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1649 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1650 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1651 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1652 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1653 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1654 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1655 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1656 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1657 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1658 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1659 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1660 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1661 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1662 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1663 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1664 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1665 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1666 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 }, \ 1667 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, 0, 0, v9 } 1668 1669 /* v9: We must put `FBRX' before `FBR', to ensure that we never match 1670 v9: something against an expression unless it is an expression. Otherwise, 1671 v9: we end up with undefined symbol tables entries, because they get added, 1672 v9: but are not deleted if the pattern fails to match. */ 1673 1674 #define CONDFC(fop, cop, mask, flags) \ 1675 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1676 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ 1677 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet) 1678 1679 #define CONDFCL(fop, cop, mask, flags) \ 1680 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1681 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \ 1682 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6) 1683 1684 #define CONDF(fop, mask, flags) \ 1685 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \ 1686 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags) 1687 1688 CONDFC ("fb", "cb", 0x8, F_UNBR), 1689 CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS), 1690 CONDFC ("fbe", "cb0", 0x9, F_CONDBR), 1691 CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS), 1692 CONDFC ("fbg", "cb2", 0x6, F_CONDBR), 1693 CONDFC ("fbge", "cb02", 0xb, F_CONDBR), 1694 CONDFC ("fbl", "cb1", 0x4, F_CONDBR), 1695 CONDFC ("fble", "cb01", 0xd, F_CONDBR), 1696 CONDFC ("fblg", "cb12", 0x2, F_CONDBR), 1697 CONDFCL ("fbn", "cbn", 0x0, F_UNBR), 1698 CONDFC ("fbne", "cb123", 0x1, F_CONDBR), 1699 CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS), 1700 CONDFC ("fbo", "cb012", 0xf, F_CONDBR), 1701 CONDFC ("fbu", "cb3", 0x7, F_CONDBR), 1702 CONDFC ("fbue", "cb03", 0xa, F_CONDBR), 1703 CONDFC ("fbug", "cb23", 0x5, F_CONDBR), 1704 CONDFC ("fbuge", "cb023", 0xc, F_CONDBR), 1705 CONDFC ("fbul", "cb13", 0x3, F_CONDBR), 1706 CONDFC ("fbule", "cb013", 0xe, F_CONDBR), 1707 1708 #undef CONDFC 1709 #undef CONDFCL 1710 #undef CONDF 1711 #undef CBR 1712 #undef FBR 1713 #undef FBRX /* v9 */ 1714 1715 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+rs2,%g0 */ 1716 { "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+%g0,%g0 */ 1717 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+i,%g0 */ 1718 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl i+rs1,%g0 */ 1719 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl %g0+i,%g0 */ 1720 { "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, 0, 0, v6 }, /* jmpl rs1+0,%g0 */ 1721 1722 { "nop", F2(0, 4), 0xfeffffff, "", 0, 0, 0, v6 }, /* sethi 0, %g0 */ 1723 1724 { "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v6 }, 1725 { "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 }, 1726 { "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, 0, 0, v9 }, 1727 { "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, 0, 0, v9 }, 1728 1729 { "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, 0, 0, v6 }, 1730 1731 { "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1732 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, 0, 0, v6 }, 1733 { "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, 0, 0, v6 }, 1734 { "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1735 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, 0, 0, v6 }, 1736 { "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, 0, 0, v6 }, 1737 1738 { "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1739 { "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, 0, 0, v6 }, 1740 { "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1741 { "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, 0, 0, v6 }, 1742 1743 { "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, 0, 0, v6notv9 }, 1744 { "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, 0, 0, v9 }, 1745 1746 /* This *is* a commutative instruction. */ 1747 { "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1748 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, 0, 0, v6 }, 1749 { "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, 0, 0, v6 }, 1750 /* This *is* a commutative instruction. */ 1751 { "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1752 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, 0, 0, v6 }, 1753 { "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, 0, 0, v6 }, 1754 { "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1755 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, 0, 0, v6 }, 1756 { "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, 0, 0, v6 }, 1757 { "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v6 }, 1758 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, 0, 0, v6 }, 1759 { "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, 0, 0, v6 }, 1760 1761 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, 0, 0, v6 }, /* xnor rs1,%0,rd */ 1762 { "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, 0, 0, v6 }, /* xnor rd,%0,rd */ 1763 1764 { "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, 0, 0, v6 }, /* xor rd,rs2,rd */ 1765 { "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, 0, 0, v6 }, /* xor rd,i,rd */ 1766 1767 /* FPop1 and FPop2 are not instructions. Don't accept them. */ 1768 1769 { "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 }, 1770 { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1771 { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 }, 1772 1773 { "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1774 { "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, 0, 0, v9 }, 1775 { "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, 0, 0, v9 }, 1776 1777 { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 }, 1778 { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1779 { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 }, 1780 1781 { "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1782 { "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, 0, 0, v9 }, 1783 { "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, 0, 0, v9 }, 1784 1785 { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, 0, 0, v8 }, 1786 { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, 0, 0, v6 }, 1787 { "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, 0, 0, v8 }, 1788 { "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, 0, 0, v8 }, 1789 { "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, 0, 0, v6 }, 1790 { "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, 0, 0, v8 }, 1791 1792 { "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, 0, 0, v6 }, 1793 { "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, 0, 0, v8 }, 1794 { "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1795 { "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, 0, 0, v6 }, 1796 { "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, 0, 0, v6 }, 1797 { "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, 0, 0, v8 }, 1798 { "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1799 { "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, 0, 0, v6 }, 1800 1801 { "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, 0, 0, v8 }, 1802 { "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1803 { "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, HWCAP_FSMULD, 0, v8 }, 1804 1805 { "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v7 }, 1806 { "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v8 }, 1807 { "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1808 { "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, 0, 0, v7 }, 1809 1810 { "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1811 { "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1812 { "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1813 { "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1814 { "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1815 { "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1816 { "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1817 { "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1818 { "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, 0, 0, v9 }, 1819 { "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, 0, 0, v9 }, 1820 { "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1821 { "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, 0, 0, v6 }, 1822 1823 { "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, 0, 0, v6 }, 1824 { "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, 0, 0, v8 }, 1825 { "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1826 { "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, 0, 0, v6 }, 1827 { "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, 0, 0, v6 }, 1828 { "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, 0, 0, v8 }, 1829 { "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1830 { "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, 0, 0, v6 }, 1831 1832 #define CMPFCC(x) (((x)&0x3)<<25) 1833 1834 { "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 }, 1835 { "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, 0, 0, v9 }, 1836 { "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, 0, 0, v9 }, 1837 { "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, 0, 0, v9 }, 1838 { "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, 0, 0, v9 }, 1839 { "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, 0, 0, v6 }, 1840 { "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, 0, 0, v9 }, 1841 { "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, 0, 0, v9 }, 1842 { "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, 0, 0, v9 }, 1843 { "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, 0, 0, v9 }, 1844 { "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 }, 1845 { "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, 0, 0, v9 }, 1846 { "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, 0, 0, v9 }, 1847 { "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, 0, 0, v9 }, 1848 { "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, 0, 0, v9 }, 1849 { "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, 0, 0, v8 }, 1850 { "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, 0, 0, v9 }, 1851 { "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, 0, 0, v9 }, 1852 { "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, 0, 0, v9 }, 1853 { "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, 0, 0, v9 }, 1854 { "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1855 { "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1856 { "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1857 { "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1858 { "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1859 { "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, 0, 0, v8 }, 1860 { "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1861 { "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1862 { "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1863 { "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, 0, 0, v9 }, 1864 { "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 }, 1865 { "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, 0, 0, v9 }, 1866 { "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, 0, 0, v9 }, 1867 { "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, 0, 0, v9 }, 1868 { "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, 0, 0, v9 }, 1869 { "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, 0, 0, v6 }, 1870 { "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, 0, 0, v9 }, 1871 { "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, 0, 0, v9 }, 1872 { "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, 0, 0, v9 }, 1873 { "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, 0, 0, v9 }, 1874 1875 /* These Extended FPop (FIFO) instructions are new in the Fujitsu 1876 MB86934, replacing the CPop instructions from v6 and later 1877 processors. */ 1878 1879 #define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, 0, 0, sparclite } 1880 #define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, 0, 0, sparclite } 1881 #define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, 0, 0, sparclite } 1882 1883 EFPOP1_2 ("efitod", 0x0c8, "f,H"), 1884 EFPOP1_2 ("efitos", 0x0c4, "f,g"), 1885 EFPOP1_2 ("efdtoi", 0x0d2, "B,g"), 1886 EFPOP1_2 ("efstoi", 0x0d1, "f,g"), 1887 EFPOP1_2 ("efstod", 0x0c9, "f,H"), 1888 EFPOP1_2 ("efdtos", 0x0c6, "B,g"), 1889 EFPOP1_2 ("efmovs", 0x001, "f,g"), 1890 EFPOP1_2 ("efnegs", 0x005, "f,g"), 1891 EFPOP1_2 ("efabss", 0x009, "f,g"), 1892 EFPOP1_2 ("efsqrtd", 0x02a, "B,H"), 1893 EFPOP1_2 ("efsqrts", 0x029, "f,g"), 1894 EFPOP1_3 ("efaddd", 0x042, "v,B,H"), 1895 EFPOP1_3 ("efadds", 0x041, "e,f,g"), 1896 EFPOP1_3 ("efsubd", 0x046, "v,B,H"), 1897 EFPOP1_3 ("efsubs", 0x045, "e,f,g"), 1898 EFPOP1_3 ("efdivd", 0x04e, "v,B,H"), 1899 EFPOP1_3 ("efdivs", 0x04d, "e,f,g"), 1900 EFPOP1_3 ("efmuld", 0x04a, "v,B,H"), 1901 EFPOP1_3 ("efmuls", 0x049, "e,f,g"), 1902 EFPOP1_3 ("efsmuld", 0x069, "e,f,H"), 1903 EFPOP2_2 ("efcmpd", 0x052, "v,B"), 1904 EFPOP2_2 ("efcmped", 0x056, "v,B"), 1905 EFPOP2_2 ("efcmps", 0x051, "e,f"), 1906 EFPOP2_2 ("efcmpes", 0x055, "e,f"), 1907 1908 #undef EFPOP1_2 1909 #undef EFPOP1_3 1910 #undef EFPOP2_2 1911 1912 /* These are marked F_ALIAS, so that they won't conflict with sparclite insns 1913 present. Otherwise, the F_ALIAS flag is ignored. */ 1914 { "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 }, 1915 { "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, 0, 0, v6notv9 }, 1916 1917 /* sparclet specific insns */ 1918 1919 COMMUTEOP ("umac", 0x3e, letandleon), 1920 COMMUTEOP ("smac", 0x3f, letandleon), 1921 1922 COMMUTEOP ("umacd", 0x2e, sparclet), 1923 COMMUTEOP ("smacd", 0x2f, sparclet), 1924 COMMUTEOP ("umuld", 0x09, sparclet), 1925 COMMUTEOP ("smuld", 0x0d, sparclet), 1926 1927 { "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, 0, 0, sparclet }, 1928 { "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, 0, 0, sparclet }, 1929 1930 /* The manual isn't completely accurate on these insns. The `rs2' field is 1931 treated as being 6 bits to account for 6 bit immediates to cpush. It is 1932 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */ 1933 #define BIT5 (1<<5) 1934 { "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, 0, 0, sparclet }, 1935 { "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, 0, 0, sparclet }, 1936 { "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet }, 1937 { "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, 0, 0, sparclet }, 1938 { "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, 0, 0, sparclet }, 1939 { "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, 0, 0, sparclet }, 1940 { "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, 0, 0, sparclet }, 1941 #undef BIT5 1942 1943 /* sparclet coprocessor branch insns */ 1944 #define SLCBCC2(opcode, mask, lose) \ 1945 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, 0, 0, sparclet }, \ 1946 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, 0, 0, sparclet } 1947 #define SLCBCC(opcode, mask) \ 1948 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask))) 1949 1950 /* cbn,cba can't be defined here because they're defined elsewhere and GAS 1951 requires all mnemonics of the same name to be consecutive. */ 1952 /*SLCBCC("cbn", 0), - already defined */ 1953 SLCBCC("cbe", 1), 1954 SLCBCC("cbf", 2), 1955 SLCBCC("cbef", 3), 1956 SLCBCC("cbr", 4), 1957 SLCBCC("cber", 5), 1958 SLCBCC("cbfr", 6), 1959 SLCBCC("cbefr", 7), 1960 /*SLCBCC("cba", 8), - already defined */ 1961 SLCBCC("cbne", 9), 1962 SLCBCC("cbnf", 10), 1963 SLCBCC("cbnef", 11), 1964 SLCBCC("cbnr", 12), 1965 SLCBCC("cbner", 13), 1966 SLCBCC("cbnfr", 14), 1967 SLCBCC("cbnefr", 15), 1968 1969 #undef SLCBCC2 1970 #undef SLCBCC 1971 1972 { "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, 0, 0, v9andleon }, 1973 { "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, 0, 0, v9andleon }, 1974 { "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, 0, 0, v9 }, 1975 { "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, 0, 0, v9 }, 1976 1977 /* v9 synthetic insns */ 1978 { "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, 0, 0, v9 }, /* bn,a,pt %xcc,label */ 1979 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* sra rs1,%g0,rd */ 1980 { "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* sra rd,%g0,rd */ 1981 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, 0, 0, v9 }, /* srl rs1,%g0,rd */ 1982 { "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, 0, 0, v9 }, /* srl rd,%g0,rd */ 1983 { "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P,rs2,rd */ 1984 { "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */ 1985 { "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P,rs2,rd */ 1986 { "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, 0, 0, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */ 1987 1988 /* Ultrasparc extensions */ 1989 { "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, HWCAP_VIS, 0, v9a }, 1990 1991 /* FIXME: Do we want to mark these as F_FLOAT, or something similar? */ 1992 { "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1993 { "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1994 { "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1995 { "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1996 { "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1997 { "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 1998 { "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 1999 { "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2000 2001 { "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2002 { "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a }, 2003 { "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, HWCAP_VIS, 0, v9a }, 2004 { "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, HWCAP_VIS, 0, v9a }, 2005 { "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 2006 2007 /* Note that the mixing of 32/64 bit regs is intentional. */ 2008 { "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, HWCAP_VIS, 0, v9a }, 2009 { "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 2010 { "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 2011 { "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2012 { "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2013 { "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 2014 { "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, HWCAP_VIS, 0, v9a }, 2015 2016 { "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2017 { "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2018 { "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, HWCAP_VIS, 0, v9a }, /* faligndatag */ 2019 { "faligndata", F3F(2, 0x36, 0x049), F3F(~2, ~0x36, ~0x049), "v,B,5,}", 0, 0, HWCAP2_SPARC5, v9m }, /* faligndatai */ 2020 2021 { "fzerod", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, HWCAP_VIS, 0, v9a }, 2022 { "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2023 { "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, HWCAP_VIS, 0, v9a }, 2024 { "foned", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, HWCAP_VIS, 0, v9a }, 2025 { "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2026 { "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, HWCAP_VIS, 0, v9a }, 2027 { "fsrc1d", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, HWCAP_VIS, 0, v9a }, 2028 { "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2029 { "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, HWCAP_VIS, 0, v9a }, 2030 { "fsrc2d", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, HWCAP_VIS, 0, v9a }, 2031 { "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2032 { "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, HWCAP_VIS, 0, v9a }, 2033 { "fnot1d", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, HWCAP_VIS, 0, v9a }, 2034 { "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2035 { "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, HWCAP_VIS, 0, v9a }, 2036 { "fnot2d", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, HWCAP_VIS, 0, v9a }, 2037 { "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2038 { "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, HWCAP_VIS, 0, v9a }, 2039 { "ford", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2040 { "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2041 { "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2042 { "fnord", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2043 { "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2044 { "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2045 { "fandd", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2046 { "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2047 { "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2048 { "fnandd", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2049 { "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2050 { "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2051 { "fxord", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2052 { "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2053 { "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2054 { "fxnord", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2055 { "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2056 { "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2057 { "fornot1d", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2058 { "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2059 { "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2060 { "fornot2d", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2061 { "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2062 { "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2063 { "fandnot1d", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2064 { "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2065 { "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2066 { "fandnot2d", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2067 { "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", F_ALIAS, HWCAP_VIS, 0, v9a }, 2068 { "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, HWCAP_VIS, 0, v9a }, 2069 2070 { "fpcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2071 { "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2072 { "fpcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2073 { "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2074 { "fpcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2075 { "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2076 { "fpcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2077 { "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2078 { "fpcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2079 { "fpcmpune16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2080 { "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2081 { "fpcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2082 { "fpcmpune32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2083 { "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2084 { "fpcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2085 { "fpcmpueq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2086 { "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2087 { "fpcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, HWCAP_VIS, 0, v9a }, 2088 { "fpcmpueq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2089 { "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2090 2091 { "edge8cc", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2092 { "edge8lcc", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2093 { "edge16cc", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2094 { "edge16lcc", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2095 { "edge32cc", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2096 { "edge32lcc", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2097 2098 { "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2099 { "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2100 { "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2101 { "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2102 { "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2103 { "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", F_ALIAS, HWCAP_VIS, 0, v9a }, 2104 2105 { "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, HWCAP_VIS, 0, v9a }, 2106 2107 { "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2108 { "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2109 { "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, HWCAP_VIS, 0, v9a }, 2110 2111 /* Cheetah instructions */ 2112 { "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2113 { "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2114 { "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2115 { "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2116 { "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2117 { "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2118 2119 { "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, HWCAP_VIS2, 0, v9b }, 2120 { "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, HWCAP_VIS2, 0, v9b }, 2121 2122 { "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, HWCAP_VIS2, 0, v9b }, 2123 2124 { "fnadds", F3F(2, 0x34, 0x051), F3F(~2, ~0x34, ~0x051), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2125 { "fnaddd", F3F(2, 0x34, 0x052), F3F(~2, ~0x34, ~0x052), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2126 { "fnmuls", F3F(2, 0x34, 0x059), F3F(~2, ~0x34, ~0x059), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2127 { "fnmuld", F3F(2, 0x34, 0x05a), F3F(~2, ~0x34, ~0x05a), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2128 { "fhadds", F3F(2, 0x34, 0x061), F3F(~2, ~0x34, ~0x061), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2129 { "fhaddd", F3F(2, 0x34, 0x062), F3F(~2, ~0x34, ~0x062), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2130 { "fhsubs", F3F(2, 0x34, 0x065), F3F(~2, ~0x34, ~0x065), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2131 { "fhsubd", F3F(2, 0x34, 0x066), F3F(~2, ~0x34, ~0x066), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2132 { "fnhadds", F3F(2, 0x34, 0x071), F3F(~2, ~0x34, ~0x071), "e,f,g", F_FLOAT, HWCAP_HPC, 0, v9d }, 2133 { "fnhaddd", F3F(2, 0x34, 0x072), F3F(~2, ~0x34, ~0x072), "v,B,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2134 { "fnsmuld", F3F(2, 0x34, 0x079), F3F(~2, ~0x34, ~0x079), "e,f,H", F_FLOAT, HWCAP_HPC, 0, v9d }, 2135 { "fpmaddx", F3(2, 0x37, 0)|OPF_LOW4(0), F3(~2, ~0x37, 0)|OPF_LOW4(~0), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v }, 2136 { "fmadds", F3(2, 0x37, 0)|OPF_LOW4(1), F3(~2, ~0x37, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2137 { "fmaddd", F3(2, 0x37, 0)|OPF_LOW4(2), F3(~2, ~0x37, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2138 { "fpmaddxhi", F3(2, 0x37, 0)|OPF_LOW4(4), F3(~2, ~0x37, 0)|OPF_LOW4(~4), "v,B,5,H", F_FLOAT, HWCAP_IMA, 0, v9v }, 2139 { "fmsubs", F3(2, 0x37, 0)|OPF_LOW4(5), F3(~2, ~0x37, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2140 { "fmsubd", F3(2, 0x37, 0)|OPF_LOW4(6), F3(~2, ~0x37, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2141 { "fnmsubs", F3(2, 0x37, 0)|OPF_LOW4(9), F3(~2, ~0x37, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2142 { "fnmsubd", F3(2, 0x37, 0)|OPF_LOW4(10), F3(~2, ~0x37, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2143 { "fnmadds", F3(2, 0x37, 0)|OPF_LOW4(13), F3(~2, ~0x37, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2144 { "fnmaddd", F3(2, 0x37, 0)|OPF_LOW4(14), F3(~2, ~0x37, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FMAF, 0, v9d }, 2145 { "fumadds", F3(2, 0x3f, 0)|OPF_LOW4(1), F3(~2, ~0x3f, 0)|OPF_LOW4(~1), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2146 { "fumaddd", F3(2, 0x3f, 0)|OPF_LOW4(2), F3(~2, ~0x3f, 0)|OPF_LOW4(~2), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2147 { "fumsubs", F3(2, 0x3f, 0)|OPF_LOW4(5), F3(~2, ~0x3f, 0)|OPF_LOW4(~5), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2148 { "fumsubd", F3(2, 0x3f, 0)|OPF_LOW4(6), F3(~2, ~0x3f, 0)|OPF_LOW4(~6), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2149 { "fnumsubs", F3(2, 0x3f, 0)|OPF_LOW4(9), F3(~2, ~0x3f, 0)|OPF_LOW4(~9), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2150 { "fnumsubd", F3(2, 0x3f, 0)|OPF_LOW4(10), F3(~2, ~0x3f, 0)|OPF_LOW4(~10), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2151 { "fnumadds", F3(2, 0x3f, 0)|OPF_LOW4(13), F3(~2, ~0x3f, 0)|OPF_LOW4(~13), "e,f,4,g", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2152 { "fnumaddd", F3(2, 0x3f, 0)|OPF_LOW4(14), F3(~2, ~0x3f, 0)|OPF_LOW4(~14), "v,B,5,H", F_FLOAT, HWCAP_FJFMAU, 0, v9v }, 2153 { "addxc", F3F(2, 0x36, 0x011), F3F(~2, ~0x36, ~0x011), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2154 { "addxccc", F3F(2, 0x36, 0x013), F3F(~2, ~0x36, ~0x013), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2155 { "umulxhi", F3F(2, 0x36, 0x016), F3F(~2, ~0x36, ~0x016), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2156 { "lzcnt", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", 0, HWCAP_VIS3, 0, v9d }, 2157 { "lzd", F3F(2, 0x36, 0x017), F3F(~2, ~0x36, ~0x017), "2,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2158 { "cmask8", F3F(2, 0x36, 0x01b), F3F(~2, ~0x36, ~0x01b), "2", 0, HWCAP_VIS3, 0, v9d }, 2159 { "cmask16", F3F(2, 0x36, 0x01d), F3F(~2, ~0x36, ~0x01d), "2", 0, HWCAP_VIS3, 0, v9d }, 2160 { "cmask32", F3F(2, 0x36, 0x01f), F3F(~2, ~0x36, ~0x01f), "2", 0, HWCAP_VIS3, 0, v9d }, 2161 { "fsll16", F3F(2, 0x36, 0x021), F3F(~2, ~0x36, ~0x021), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2162 { "fsrl16", F3F(2, 0x36, 0x023), F3F(~2, ~0x36, ~0x023), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2163 { "fsll32", F3F(2, 0x36, 0x025), F3F(~2, ~0x36, ~0x025), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2164 { "fsrl32", F3F(2, 0x36, 0x027), F3F(~2, ~0x36, ~0x027), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2165 { "fslas16", F3F(2, 0x36, 0x029), F3F(~2, ~0x36, ~0x029), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2166 { "fsra16", F3F(2, 0x36, 0x02b), F3F(~2, ~0x36, ~0x02b), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2167 { "fslas32", F3F(2, 0x36, 0x02d), F3F(~2, ~0x36, ~0x02d), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2168 { "fsra32", F3F(2, 0x36, 0x02f), F3F(~2, ~0x36, ~0x02f), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2169 { "pdistn", F3F(2, 0x36, 0x03f), F3F(~2, ~0x36, ~0x03f), "v,B,d", 0, HWCAP_VIS3, 0, v9d }, 2170 { "fmean16", F3F(2, 0x36, 0x040), F3F(~2, ~0x36, ~0x040), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2171 { "fpadd64", F3F(2, 0x36, 0x042), F3F(~2, ~0x36, ~0x042), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2172 { "fchksm16", F3F(2, 0x36, 0x044), F3F(~2, ~0x36, ~0x044), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2173 { "fpsub64", F3F(2, 0x36, 0x046), F3F(~2, ~0x36, ~0x046), "v,B,H", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2174 { "fpadds16", F3F(2, 0x36, 0x058), F3F(~2, ~0x36, ~0x058), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2175 { "fpadds16s", F3F(2, 0x36, 0x059), F3F(~2, ~0x36, ~0x059), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2176 { "fpadds32", F3F(2, 0x36, 0x05a), F3F(~2, ~0x36, ~0x05a), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2177 { "fpadds32s", F3F(2, 0x36, 0x05b), F3F(~2, ~0x36, ~0x05b), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2178 { "fpsubs16", F3F(2, 0x36, 0x05c), F3F(~2, ~0x36, ~0x05c), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2179 { "fpsubs16s", F3F(2, 0x36, 0x05d), F3F(~2, ~0x36, ~0x05d), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2180 { "fpsubs32", F3F(2, 0x36, 0x05e), F3F(~2, ~0x36, ~0x05e), "v,B,H", 0, HWCAP_VIS3, 0, v9d }, 2181 { "fpsubs32s", F3F(2, 0x36, 0x05f), F3F(~2, ~0x36, ~0x05f), "e,f,g", 0, HWCAP_VIS3, 0, v9d }, 2182 { "movdtox", F3F(2, 0x36, 0x110), F3F(~2, ~0x36, ~0x110), "B,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2183 { "movstouw", F3F(2, 0x36, 0x111), F3F(~2, ~0x36, ~0x111), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2184 { "movstosw", F3F(2, 0x36, 0x113), F3F(~2, ~0x36, ~0x113), "f,d", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2185 { "movxtod", F3F(2, 0x36, 0x118), F3F(~2, ~0x36, ~0x118), "2,H", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2186 { "movwtos", F3F(2, 0x36, 0x119), F3F(~2, ~0x36, ~0x119), "2,g", F_FLOAT, HWCAP_VIS3, 0, v9d }, 2187 { "xmulx", F3F(2, 0x36, 0x115), F3F(~2, ~0x36, ~0x115), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2188 { "xmulxhi", F3F(2, 0x36, 0x116), F3F(~2, ~0x36, ~0x116), "1,2,d", 0, HWCAP_VIS3, 0, v9d }, 2189 { "fpcmpule8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2190 { "fucmple8", F3F(2, 0x36, 0x120), F3F(~2, ~0x36, ~0x120), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2191 { "fpcmpune8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2192 { "fpcmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d }, 2193 { "fucmpne8", F3F(2, 0x36, 0x122), F3F(~2, ~0x36, ~0x122), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2194 { "fpcmpugt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2195 { "fucmpgt8", F3F(2, 0x36, 0x128), F3F(~2, ~0x36, ~0x128), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2196 { "fpcmpueq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", 0, HWCAP_VIS3, HWCAP2_VIS3B, v9d }, 2197 { "fpcmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_PREF_ALIAS, HWCAP_VIS3, 0, v9d }, 2198 { "fucmpeq8", F3F(2, 0x36, 0x12a), F3F(~2, ~0x36, ~0x12a), "v,B,d", F_ALIAS, HWCAP_VIS3, 0, v9d }, 2199 {"aes_kexpand0",F3F(2, 0x36, 0x130), F3F(~2, ~0x36, ~0x130), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2200 {"aes_kexpand2",F3F(2, 0x36, 0x131), F3F(~2, ~0x36, ~0x131), "v,B,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2201 { "des_ip", F3F(2, 0x36, 0x134), F3F(~2, ~0x36, ~0x134), "v,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2202 { "des_iip", F3F(2, 0x36, 0x135), F3F(~2, ~0x36, ~0x135), "v,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2203 { "des_kexpand",F3F(2, 0x36, 0x136), F3F(~2, ~0x36, ~0x136), "v,X,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2204 {"kasumi_fi_fi",F3F(2, 0x36, 0x138), F3F(~2, ~0x36, ~0x138), "v,B,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2205 { "camellia_fl",F3F(2, 0x36, 0x13c), F3F(~2, ~0x36, ~0x13c), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2206 {"camellia_fli",F3F(2, 0x36, 0x13d), F3F(~2, ~0x36, ~0x13d), "v,B,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2207 { "md5", F3F(2, 0x36, 0x140), F3F(~2, ~0x36, ~0x140), "", F_FLOAT, HWCAP_MD5, 0, v9e }, 2208 { "sha1", F3F(2, 0x36, 0x141), F3F(~2, ~0x36, ~0x141), "", F_FLOAT, HWCAP_SHA1, 0, v9e }, 2209 { "sha256", F3F(2, 0x36, 0x142), F3F(~2, ~0x36, ~0x142), "", F_FLOAT, HWCAP_SHA256, 0, v9e }, 2210 { "sha512", F3F(2, 0x36, 0x143), F3F(~2, ~0x36, ~0x143), "", F_FLOAT, HWCAP_SHA512, 0, v9e }, 2211 { "sha3", F3F(2, 0x36, 0x144), F3F(~2, ~0x36, ~0x144), "", F_FLOAT, 0, HWCAP2_SHA3, m8 }, 2212 { "crc32c", F3F(2, 0x36, 0x147), F3F(~2, ~0x36, ~0x147), "v,B,H", F_FLOAT, HWCAP_CRC32C, 0, v9e }, 2213 { "xmpmul", F3F(2, 0x36, 0x148)|RD(1), F3F(~2, ~0x36, ~0x148)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMPMUL, v9m }, 2214 { "mpmul", F3F(2, 0x36, 0x148), F3F(~2, ~0x36, ~0x148), "X", F_FLOAT, HWCAP_MPMUL, 0, v9e }, 2215 { "xmontmul", F3F(2, 0x36, 0x149)|RD(1), F3F(~2, ~0x36, ~0x149)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m }, 2216 { "montmul", F3F(2, 0x36, 0x149), F3F(~2, ~0x36, ~0x149), "X", F_FLOAT, HWCAP_MONT, 0, v9e }, 2217 { "xmontsqr", F3F(2, 0x36, 0x14a)|RD(1), F3F(~2, ~0x36, ~0x14a)|RD(~1), "X", F_FLOAT, 0, HWCAP2_XMONT, v9m }, 2218 { "montsqr", F3F(2, 0x36, 0x14a), F3F(~2, ~0x36, ~0x14a), "X", F_FLOAT, HWCAP_MONT, 0, v9e }, 2219 {"aes_eround01", F3F4(2, 0x19, 0), F3F4(~2, ~0x19, ~0), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2220 {"aes_eround23", F3F4(2, 0x19, 1), F3F4(~2, ~0x19, ~1), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2221 {"aes_dround01", F3F4(2, 0x19, 2), F3F4(~2, ~0x19, ~2), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2222 {"aes_dround23", F3F4(2, 0x19, 3), F3F4(~2, ~0x19, ~3), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2223 {"aes_eround01_l",F3F4(2, 0x19, 4), F3F4(~2, ~0x19, ~4), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2224 {"aes_eround23_l",F3F4(2, 0x19, 5), F3F4(~2, ~0x19, ~5), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2225 {"aes_dround01_l",F3F4(2, 0x19, 6), F3F4(~2, ~0x19, ~6), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2226 {"aes_dround23_l",F3F4(2, 0x19, 7), F3F4(~2, ~0x19, ~7), "v,B,5,H", F_FLOAT, HWCAP_AES, 0, v9e }, 2227 {"aes_kexpand1", F3F4(2, 0x19, 8), F3F4(~2, ~0x19, ~8), "v,B,),H", F_FLOAT, HWCAP_AES, 0, v9e }, 2228 {"des_round", F3F4(2, 0x19, 9), F3F4(~2, ~0x19, ~9), "v,B,5,H", F_FLOAT, HWCAP_DES, 0, v9e }, 2229 {"kasumi_fl_xor", F3F4(2, 0x19, 10), F3F4(~2, ~0x19, ~10), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2230 {"kasumi_fi_xor", F3F4(2, 0x19, 11), F3F4(~2, ~0x19, ~11), "v,B,5,H", F_FLOAT, HWCAP_KASUMI, 0, v9e }, 2231 {"camellia_f", F3F4(2, 0x19, 12), F3F4(~2, ~0x19, ~12), "v,B,5,H", F_FLOAT, HWCAP_CAMELLIA, 0, v9e }, 2232 { "flcmps", CMPFCC(0)|F3F(2, 0x36, 0x151), CMPFCC(~0)|F3F(~2, ~0x36, ~0x151), "6,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2233 { "flcmps", CMPFCC(1)|F3F(2, 0x36, 0x151), CMPFCC(~1)|F3F(~2, ~0x36, ~0x151), "7,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2234 { "flcmps", CMPFCC(2)|F3F(2, 0x36, 0x151), CMPFCC(~2)|F3F(~2, ~0x36, ~0x151), "8,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2235 { "flcmps", CMPFCC(3)|F3F(2, 0x36, 0x151), CMPFCC(~3)|F3F(~2, ~0x36, ~0x151), "9,e,f", F_FLOAT, HWCAP_HPC, 0, v9d }, 2236 { "flcmpd", CMPFCC(0)|F3F(2, 0x36, 0x152), CMPFCC(~0)|F3F(~2, ~0x36, ~0x152), "6,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2237 { "flcmpd", CMPFCC(1)|F3F(2, 0x36, 0x152), CMPFCC(~1)|F3F(~2, ~0x36, ~0x152), "7,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2238 { "flcmpd", CMPFCC(2)|F3F(2, 0x36, 0x152), CMPFCC(~2)|F3F(~2, ~0x36, ~0x152), "8,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2239 { "flcmpd", CMPFCC(3)|F3F(2, 0x36, 0x152), CMPFCC(~3)|F3F(~2, ~0x36, ~0x152), "9,v,B", F_FLOAT, HWCAP_HPC, 0, v9d }, 2240 2241 { "mwait", F3(2, 0x30, 0)|RD(28), F3(~2, ~0x30, ~0)|RD(~28)|RS1_G0|ASI(~0), "2", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait r */ 2242 { "mwait", F3(2, 0x30, 1)|RD(28), F3(~2, ~0x30, ~1)|RD(~28)|RS1_G0, "i", 0, 0, HWCAP2_MWAIT, v9m }, /* mwait imm */ 2243 2244 /* Other SPARC5 and VIS4.0 instructions. */ 2245 2246 { "subxc", F3(2, 0x36, 0)|OPF(0x41), F3(~2, ~0x36, ~0)|OPF(~0x41), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m }, 2247 { "subxccc", F3(2, 0x36, 0)|OPF(0x43), F3(~2, ~0x36, ~0)|OPF(~0x43), "1,2,d", 0, 0, HWCAP2_SPARC5, v9m }, 2248 2249 { "fpadd8", F3F(2, 0x36, 0x124), F3F(~2, ~0x36, ~0x124), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2250 { "fpadds8", F3F(2, 0x36, 0x126), F3F(~2, ~0x36, ~0x126), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2251 { "fpaddus8", F3F(2, 0x36, 0x127), F3F(~2, ~0x36, ~0x127), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2252 { "fpaddus16", F3F(2, 0x36, 0x123), F3F(~2, ~0x36, ~0x123), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2253 { "fpcmple8", F3F(2, 0x36, 0x034), F3F(~2, ~0x36, ~0x034), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2254 { "fpcmpgt8", F3F(2, 0x36, 0x03c), F3F(~2, ~0x36, ~0x03c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2255 { "fpcmpule16", F3F(2, 0x36, 0x12e), F3F(~2, ~0x36, ~0x12e), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2256 { "fpcmpugt16", F3F(2, 0x36, 0x12b), F3F(~2, ~0x36, ~0x12b), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2257 { "fpcmpule32", F3F(2, 0x36, 0x12f), F3F(~2, ~0x36, ~0x12f), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2258 { "fpcmpugt32", F3F(2, 0x36, 0x12c), F3F(~2, ~0x36, ~0x12c), "v,B,d", 0, 0, HWCAP2_SPARC5, v9m }, 2259 { "fpmax8", F3F(2, 0x36, 0x11d), F3F(~2, ~0x36, ~0x11d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2260 { "fpmax16", F3F(2, 0x36, 0x11e), F3F(~2, ~0x36, ~0x11e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2261 { "fpmax32", F3F(2, 0x36, 0x11f), F3F(~2, ~0x36, ~0x11f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2262 { "fpmaxu8", F3F(2, 0x36, 0x15d), F3F(~2, ~0x36, ~0x15d), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2263 { "fpmaxu16", F3F(2, 0x36, 0x15e), F3F(~2, ~0x36, ~0x15e), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2264 { "fpmaxu32", F3F(2, 0x36, 0x15f), F3F(~2, ~0x36, ~0x15f), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2265 { "fpmin8", F3F(2, 0x36, 0x11a), F3F(~2, ~0x36, ~0x11a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2266 { "fpmin16", F3F(2, 0x36, 0x11b), F3F(~2, ~0x36, ~0x11b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2267 { "fpmin32", F3F(2, 0x36, 0x11c), F3F(~2, ~0x36, ~0x11c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2268 { "fpminu8", F3F(2, 0x36, 0x15a), F3F(~2, ~0x36, ~0x15a), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2269 { "fpminu16", F3F(2, 0x36, 0x15b), F3F(~2, ~0x36, ~0x15b), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2270 { "fpminu32", F3F(2, 0x36, 0x15c), F3F(~2, ~0x36, ~0x15c), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2271 { "fpsub8", F3F(2, 0x36, 0x154), F3F(~2, ~0x36, ~0x154), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2272 { "fpsubs8", F3F(2, 0x36, 0x156), F3F(~2, ~0x36, ~0x156), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2273 { "fpsubus8", F3F(2, 0x36, 0x157), F3F(~2, ~0x36, ~0x157), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2274 { "fpsubus16", F3F(2, 0x36, 0x153), F3F(~2, ~0x36, ~0x153), "v,B,H", 0, 0, HWCAP2_SPARC5, v9m }, 2275 2276 /* Other OSA2017 and M8 instructions. */ 2277 2278 { "dictunpack", F3F(2, 0x36, 0x1c), F3F(~2, ~0x36, ~0x1c), "v,X,H", 0, 0, HWCAP2_DICTUNP, m8 }, 2279 2280 #define fpcmpshl(cbits, opf) \ 2281 { "fpcmp" cbits "shl", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,',|,d", 0, 0, HWCAP2_FPCMPSHL, m8 } 2282 2283 fpcmpshl ("ule8", 0x190), 2284 fpcmpshl ("ugt8", 0x191), 2285 fpcmpshl ("eq8", 0x192), 2286 fpcmpshl ("ne8", 0x193), 2287 2288 fpcmpshl ("ule16", 0x194), 2289 fpcmpshl ("ugt16", 0x195), 2290 fpcmpshl ("eq16", 0x196), 2291 fpcmpshl ("ne16", 0x197), 2292 2293 fpcmpshl ("ule32", 0x198), 2294 fpcmpshl ("ugt32", 0x199), 2295 fpcmpshl ("eq32", 0x19a), 2296 fpcmpshl ("ne32", 0x19b), 2297 2298 fpcmpshl ("de8", 0x45), 2299 fpcmpshl ("de16", 0x47), 2300 fpcmpshl ("de32", 0x4a), 2301 2302 fpcmpshl ("ur8", 0x19c), 2303 fpcmpshl ("ur16", 0x19d), 2304 fpcmpshl ("ur32", 0x19e), 2305 2306 #undef fpcmpshl 2307 2308 #define fps64x(dir, opf) \ 2309 { "fps" dir "64x", F3F(2, 0x36, (opf)), F3F(~2, ~0x36, ~(opf)), "v,B,H", 0, 0, HWCAP2_SPARC6, m8 } 2310 2311 fps64x ("ll", 0x106), 2312 fps64x ("ra", 0x10f), 2313 fps64x ("rl", 0x107), 2314 2315 #undef fps64x 2316 2317 #define ldm(width,opm,flags) \ 2318 { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2],d", (flags), 0, HWCAP2_SPARC6, m8 }, \ 2319 { "ldm" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+%g0],d */ \ 2320 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \ 2321 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1],d", (flags), 0, HWCAP2_SPARC6, m8 }, /* ldm [rs1+j],d */ \ 2322 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j],d", (flags), 0, HWCAP2_SPARC6, m8 }, \ 2323 { "ldm" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1],d", (flags), 0, HWCAP2_SPARC6, m8 } /* ldm [rs1+0],d */ 2324 2325 ldm ("sh", 0x0, 0), 2326 ldm ("uh", 0x1, 0), 2327 ldm ("sw", 0x2, 0), 2328 ldm ("uw", 0x3, 0), 2329 /* Note that opm=0x4 is reserved. */ 2330 ldm ("x", 0x5, 0), 2331 ldm ("ux", 0x5, F_ALIAS), 2332 2333 #undef ldm 2334 2335 #define ldma(width,opm,flags) \ 2336 { "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o,d", (flags), 0, HWCAP2_SPARC6, m8 }, \ 2337 { "ldm" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o,d", (flags), 0, HWCAP2_SPARC6, m8 } 2338 2339 ldma ("sh", 0x0, 0), 2340 ldma ("uh", 0x1, 0), 2341 ldma ("sw", 0x2, 0), 2342 ldma ("uw", 0x3, 0), 2343 /* Note that opm=0x4 is reserved. */ 2344 ldma ("x", 0x5, 0), 2345 ldma ("ux", 0x5, F_ALIAS), 2346 2347 #undef ldma 2348 2349 #define ldmf(width,opm,rd) \ 2350 { "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0), "[1+2]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \ 2351 { "ldmf" width, F3(3, 0x31, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+%g0],rd */ \ 2352 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[1+j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \ 2353 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm)), "[j+1]," rd, 0, 0, HWCAP2_SPARC6, m8 }, /* ldmf [rs1+j],rd */ \ 2354 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|RS1_G0, "[j]," rd, 0, 0, HWCAP2_SPARC6, m8 }, \ 2355 { "ldmf" width, F3(3, 0x31, 1)|OPM((opm)), F3(~3, ~0x31, ~1)|OPM(~(opm))|SIMM10(~0), "[1]," rd, 0, 0, HWCAP2_SPARC6, m8 } /* ldmf [rs1+0],rd */ 2356 2357 ldmf ("s", 0x6, "g"), 2358 ldmf ("d", 0x7, "H"), 2359 2360 #undef ldmf 2361 2362 #define ldmfa(width,opm,rd) \ 2363 { "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1), "[1+2]o," rd, 0, 0, HWCAP2_SPARC6, m8 }, \ 2364 { "ldmf" width "a", F3(3, 0x31, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x31, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "[1]o," rd, 0, 0, HWCAP2_SPARC6, m8} 2365 2366 ldmfa ("s", 0x6, "g"), 2367 ldmfa ("d", 0x7, "H"), 2368 2369 #undef ldmfa 2370 2371 #define stm(width,opm) \ 2372 { "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), "d,[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2373 { "stm" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, "d,[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stm d,[rs1+%g0] */ \ 2374 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2375 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), "d,[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2376 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, "d,[j]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2377 { "stm" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), "d,[1]", 0, 0, HWCAP2_SPARC6, m8 } 2378 2379 stm ("h", 0x1), 2380 stm ("w", 0x3), 2381 stm ("x", 0x5), 2382 2383 #undef stm 2384 2385 #define stma(width,opm) \ 2386 { "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), "d,[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \ 2387 { "stm" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, "d,[1]o", 0, 0, HWCAP2_SPARC6, m8 } 2388 2389 stma ("h", 0x1), 2390 stma ("w", 0x3), 2391 stma ("x", 0x5), 2392 2393 #undef stma 2394 2395 #define stmf(width, opm, rd) \ 2396 { "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0), rd ",[1+2]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2397 { "stmf" width, F3(3, 0x35, 0)|OPM((opm))|OPMI(0), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~0)|RS2_G0, rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 }, /* stmf rd,[rs1+%g0] */ \ 2398 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[1+j]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2399 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm)), rd ",[j+1]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2400 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|RS1_G0, rd ",[j]", 0, 0, HWCAP2_SPARC6, m8 }, \ 2401 { "stmf" width, F3(3, 0x35, 1)|OPM((opm)), F3(~3, ~0x35, ~1)|OPM(~(opm))|SIMM10(~0), rd ",[1]", 0, 0, HWCAP2_SPARC6, m8 } 2402 2403 stmf ("s", 0x6, "g"), 2404 stmf ("d", 0x7, "H"), 2405 2406 #define stmfa(width, opm, rd) \ 2407 { "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1), rd ",[1+2]o", 0, 0, HWCAP2_SPARC6, m8 }, \ 2408 { "stmf" width "a", F3(3, 0x35, 0)|OPM((opm))|OPMI(1), F3(~3, ~0x35, ~0)|OPM(~(opm))|OPMI(~1)|RS2_G0, rd ",[1]o", 0, 0, HWCAP2_SPARC6, m8 } 2409 2410 stmfa ("s", 0x6, "g"), 2411 stmfa ("d", 0x7, "H"), 2412 2413 #undef stmfa 2414 2415 #define on(op,fcn,hwcaps2) \ 2416 { "on" op, F3F(2, 0x36, 0x15)|ONFCN((fcn)), F3F(~2, ~0x36, ~0x15)|ONFCN(~(fcn)), ";,:,^", 0, 0, (hwcaps2), m8 } 2417 2418 on ("add", 0x0, HWCAP2_ONADDSUB), 2419 on ("sub", 0x1, HWCAP2_ONADDSUB), 2420 on ("mul", 0x2, HWCAP2_ONMUL), 2421 on ("div", 0x3, HWCAP2_ONDIV), 2422 2423 #undef on 2424 2425 #define rev(what,width,fcn) \ 2426 { "rev" what width, F3F(2, 0x36, 0x1e)|REVFCN((fcn)), F3F(~2, ~0x36, ~0x1e)|REVFCN(~(fcn)), "1,d", 0, 0, HWCAP2_SPARC6, m8 } 2427 2428 rev ("bits", "b", 0x0), 2429 rev ("bytes", "h", 0x1), 2430 rev ("bytes", "w", 0x2), 2431 rev ("bytes", "x", 0x3), 2432 2433 #undef rev 2434 2435 { "rle_burst", F3F(2, 0x36, 0x30), F3F(~2, ~0x36, ~0x30), "1,2,d", 0, 0, HWCAP2_RLE, m8 }, 2436 { "rle_length", F3F(2, 0x36, 0x32)|RS1(0), F3F(~2, ~0x36, ~0x32)|RS1(~0), "2,d", 0, 0, HWCAP2_RLE, m8 }, 2437 2438 /* More v9 specific insns, these need to come last so they do not clash 2439 with v9a instructions such as "edge8" which looks like impdep1. */ 2440 2441 #define IMPDEP(name, code) \ 2442 { name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, 0, 0, v9notv9a }, \ 2443 { name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, 0, 0, v9notv9a }, \ 2444 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, 0, 0, v9notv9a }, \ 2445 { name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, 0, 0, v9notv9a } 2446 2447 IMPDEP ("impdep1", 0x36), 2448 IMPDEP ("impdep2", 0x37), 2449 2450 #undef IMPDEP 2451 2452 }; 2453 2454 const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0])); 2455 2456 /* Handle ASI's. */ 2457 2458 static sparc_asi asi_table[] = 2459 { 2460 /* These are in the v9 architecture manual. */ 2461 /* The shorter versions appear first, they're here because Sun's as has them. 2462 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the 2463 UltraSPARC architecture manual). */ 2464 { 0x04, "#ASI_N", v9 }, 2465 { 0x0c, "#ASI_N_L", v9 }, 2466 { 0x10, "#ASI_AIUP", v9 }, 2467 { 0x11, "#ASI_AIUS", v9 }, 2468 { 0x18, "#ASI_AIUP_L", v9 }, 2469 { 0x19, "#ASI_AIUS_L", v9 }, 2470 { 0x80, "#ASI_P", v9 }, 2471 { 0x81, "#ASI_S", v9 }, 2472 { 0x82, "#ASI_PNF", v9 }, 2473 { 0x83, "#ASI_SNF", v9 }, 2474 { 0x88, "#ASI_P_L", v9 }, 2475 { 0x89, "#ASI_S_L", v9 }, 2476 { 0x8a, "#ASI_PNF_L", v9 }, 2477 { 0x8b, "#ASI_SNF_L", v9 }, 2478 { 0x04, "#ASI_NUCLEUS", v9 }, 2479 { 0x0c, "#ASI_NUCLEUS_LITTLE", v9 }, 2480 { 0x10, "#ASI_AS_IF_USER_PRIMARY", v9 }, 2481 { 0x11, "#ASI_AS_IF_USER_SECONDARY", v9 }, 2482 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE", v9 }, 2483 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE", v9 }, 2484 { 0x80, "#ASI_PRIMARY", v9 }, 2485 { 0x81, "#ASI_SECONDARY", v9 }, 2486 { 0x82, "#ASI_PRIMARY_NOFAULT", v9 }, 2487 { 0x83, "#ASI_SECONDARY_NOFAULT", v9 }, 2488 { 0x88, "#ASI_PRIMARY_LITTLE", v9 }, 2489 { 0x89, "#ASI_SECONDARY_LITTLE", v9 }, 2490 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE", v9 }, 2491 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE", v9 }, 2492 /* These are UltraSPARC and Niagara extensions. */ 2493 { 0x14, "#ASI_PHYS_USE_EC", v9b }, 2494 { 0x15, "#ASI_PHYS_BYPASS_EC_E", v9b }, 2495 { 0x16, "#ASI_BLK_AIUP_4V", v9c }, 2496 { 0x17, "#ASI_BLK_AIUS_4V", v9c }, 2497 { 0x1c, "#ASI_PHYS_USE_EC_L", v9b }, 2498 { 0x1d, "#ASI_PHYS_BYPASS_EC_E_L", v9b }, 2499 { 0x1e, "#ASI_BLK_AIUP_L_4V", v9c }, 2500 { 0x1f, "#ASI_BLK_AIUS_L_4V", v9c }, 2501 { 0x20, "#ASI_SCRATCHPAD", v9c }, 2502 { 0x21, "#ASI_MMU", v9c }, 2503 { 0x23, "#ASI_BLK_INIT_QUAD_LDD_AIUS", v9c }, 2504 { 0x24, "#ASI_NUCLEUS_QUAD_LDD", v9b }, 2505 { 0x24, "#ASI_CORE_COMMIT_COUNT", m8 }, 2506 { 0x24, "#ASI_CORE_SELECT_COUNT", m8 }, 2507 { 0x25, "#ASI_QUEUE", v9c }, 2508 { 0x26, "#ASI_QUAD_LDD_PHYS_4V", v9c }, 2509 { 0x2c, "#ASI_NUCLEUS_QUAD_LDD_L", v9b }, 2510 { 0x30, "#ASI_PCACHE_DATA_STATUS", v9b }, 2511 { 0x31, "#ASI_PCACHE_DATA", v9b }, 2512 { 0x32, "#ASI_PCACHE_TAG", v9b }, 2513 { 0x33, "#ASI_PCACHE_SNOOP_TAG", v9b }, 2514 { 0x34, "#ASI_QUAD_LDD_PHYS", v9b }, 2515 { 0x38, "#ASI_WCACHE_VALID_BITS", v9b }, 2516 { 0x39, "#ASI_WCACHE_DATA", v9b }, 2517 { 0x3a, "#ASI_WCACHE_TAG", v9b }, 2518 { 0x3b, "#ASI_WCACHE_SNOOP_TAG", v9b }, 2519 { 0x3c, "#ASI_QUAD_LDD_PHYS_L", v9b }, 2520 { 0x40, "#ASI_SRAM_FAST_INIT", v9b }, 2521 { 0x41, "#ASI_CORE_AVAILABLE", v9b }, 2522 { 0x41, "#ASI_CORE_ENABLE_STAT", v9b }, 2523 { 0x41, "#ASI_CORE_ENABLE", v9b }, 2524 { 0x41, "#ASI_XIR_STEERING", v9b }, 2525 { 0x41, "#ASI_CORE_RUNNING_RW", v9b }, 2526 { 0x41, "#ASI_CORE_RUNNING_W1S", v9b }, 2527 { 0x41, "#ASI_CORE_RUNNING_W1C", v9b }, 2528 { 0x41, "#ASI_CORE_RUNNING_STAT", v9b }, 2529 { 0x41, "#ASI_CMT_ERROR_STEERING", v9b }, 2530 { 0x45, "#ASI_LSU_CONTROL_REG", v9b }, 2531 { 0x45, "#ASI_DCU_CONTROL_REG", v9b }, 2532 { 0x46, "#ASI_DCACHE_DATA", v9b }, 2533 { 0x47, "#ASI_DCACHE_TAG", v9b }, 2534 { 0x48, "#ASI_INTR_DISPATCH_STAT", v9b }, 2535 { 0x49, "#ASI_INTR_RECEIVE", v9b }, 2536 { 0x4b, "#ASI_ESTATE_ERROR_EN", v9b }, 2537 { 0x4c, "#ASI_AFSR", v9b }, 2538 { 0x4d, "#ASI_AFAR", v9b }, 2539 { 0x4e, "#ASI_EC_TAG_DATA", v9b }, 2540 { 0x48, "#ASI_ARF_ECC_REG", m8 }, 2541 { 0x50, "#ASI_IMMU", v9b }, 2542 { 0x51, "#ASI_IMMU_TSB_8KB_PTR", v9b }, 2543 { 0x52, "#ASI_IMMU_TSB_64KB_PTR", v9b }, 2544 { 0x53, "#ASI_ITLB_PROBE", m8 }, 2545 { 0x54, "#ASI_ITLB_DATA_IN", v9b }, 2546 { 0x55, "#ASI_ITLB_DATA_ACCESS", v9b }, 2547 { 0x56, "#ASI_ITLB_TAG_READ", v9b }, 2548 { 0x57, "#ASI_IMMU_DEMAP", v9b }, 2549 { 0x58, "#ASI_DMMU", v9b }, 2550 { 0x58, "#ASI_DSFAR", m8 }, 2551 { 0x59, "#ASI_DMMU_TSB_8KB_PTR", v9b }, 2552 { 0x5a, "#ASI_DMMU_TSB_64KB_PTR", v9b }, 2553 { 0x5a, "#ASI_DTLB_PROBE_PRIMARY", m8 }, 2554 { 0x5b, "#ASI_DMMU_TSB_DIRECT_PTR", v9b }, 2555 { 0x5b, "#ASI_DTLB_PROBE_REAL", m8 }, 2556 { 0x5c, "#ASI_DTLB_DATA_IN", v9b }, 2557 { 0x5d, "#ASI_DTLB_DATA_ACCESS", v9b }, 2558 { 0x5e, "#ASI_DTLB_TAG_READ", v9b }, 2559 { 0x5f, "#ASI_DMMU_DEMAP", v9b }, 2560 { 0x60, "#ASI_IIU_INST_TRAP", v9b }, 2561 { 0x63, "#ASI_INTR_ID", v9b }, 2562 { 0x63, "#ASI_CORE_ID", v9b }, 2563 { 0x63, "#ASI_CESR_ID", v9b }, 2564 { 0x64, "#ASI_CORE_SELECT_COMMIT_NHT", m8 }, 2565 { 0x66, "#ASI_IC_INSTR", v9b }, 2566 { 0x67, "#ASI_IC_TAG", v9b }, 2567 { 0x68, "#ASI_IC_STAG", v9b }, 2568 { 0x6f, "#ASI_BRPRED_ARRAY", v9b }, 2569 { 0x70, "#ASI_BLK_AIUP", v9b }, 2570 { 0x71, "#ASI_BLK_AIUS", v9b }, 2571 { 0x72, "#ASI_MCU_CTRL_REG", v9b }, 2572 { 0x74, "#ASI_EC_DATA", v9b }, 2573 { 0x75, "#ASI_EC_CTRL", v9b }, 2574 { 0x76, "#ASI_EC_W", v9b }, 2575 { 0x77, "#ASI_INTR_W", v9b }, 2576 { 0x77, "#ASI_INTR_DATAN_W", v9b }, 2577 { 0x77, "#ASI_INTR_DISPATCH_W", v9b }, 2578 { 0x78, "#ASI_BLK_AIUPL", v9b }, 2579 { 0x79, "#ASI_BLK_AIUSL", v9b }, 2580 { 0x7e, "#ASI_EC_R", v9b }, 2581 { 0x7f, "#ASI_INTR_R", v9b }, 2582 { 0x7f, "#ASI_INTR_DATAN_R", v9b }, 2583 { 0xc0, "#ASI_PST8_P", v9b }, 2584 { 0xc1, "#ASI_PST8_S", v9b }, 2585 { 0xc2, "#ASI_PST16_P", v9b }, 2586 { 0xc3, "#ASI_PST16_S", v9b }, 2587 { 0xc4, "#ASI_PST32_P", v9b }, 2588 { 0xc5, "#ASI_PST32_S", v9b }, 2589 { 0xc8, "#ASI_PST8_PL", v9b }, 2590 { 0xc9, "#ASI_PST8_SL", v9b }, 2591 { 0xca, "#ASI_PST16_PL", v9b }, 2592 { 0xcb, "#ASI_PST16_SL", v9b }, 2593 { 0xcc, "#ASI_PST32_PL", v9b }, 2594 { 0xcd, "#ASI_PST32_SL", v9b }, 2595 { 0xd0, "#ASI_FL8_P", v9b }, 2596 { 0xd1, "#ASI_FL8_S", v9b }, 2597 { 0xd2, "#ASI_FL16_P", v9b }, 2598 { 0xd3, "#ASI_FL16_S", v9b }, 2599 { 0xd8, "#ASI_FL8_PL", v9b }, 2600 { 0xd9, "#ASI_FL8_SL", v9b }, 2601 { 0xda, "#ASI_FL16_PL", v9b }, 2602 { 0xdb, "#ASI_FL16_SL", v9b }, 2603 { 0xe0, "#ASI_BLK_COMMIT_P", v9b }, 2604 { 0xe1, "#ASI_BLK_COMMIT_S", v9b }, 2605 { 0xe2, "#ASI_BLK_INIT_QUAD_LDD_P", v9b }, 2606 { 0xf0, "#ASI_BLK_P", v9b }, 2607 { 0xf1, "#ASI_BLK_S", v9b }, 2608 { 0xf8, "#ASI_BLK_PL", v9b }, 2609 { 0xf9, "#ASI_BLK_SL", v9b }, 2610 { 0x22, "#ASI_TWINX_AIUP", v9c }, 2611 { 0x23, "#ASI_TWINX_AIUS", v9c }, 2612 { 0x26, "#ASI_TWINX_REAL", v9c }, 2613 { 0x27, "#ASI_TWINX_N", v9c }, 2614 { 0x2A, "#ASI_TWINX_AIUP_L", v9c }, 2615 { 0x2B, "#ASI_TWINX_AIUS_L", v9c }, 2616 { 0x2E, "#ASI_TWINX_REAL_L", v9c }, 2617 { 0x2F, "#ASI_TWINX_NL", v9c }, 2618 { 0xE2, "#ASI_TWINX_P", v9c }, 2619 { 0xE3, "#ASI_TWINX_S", v9c }, 2620 { 0xEA, "#ASI_TWINX_PL", v9c }, 2621 { 0xEB, "#ASI_TWINX_SL", v9c }, 2622 /* These are ASIs from UA2005, UA2007, OSA2011, & OSA 2015 */ 2623 { 0x12, "#ASI_MAIUP", v9m }, 2624 { 0x13, "#ASI_MAIUS", v9m }, 2625 { 0x14, "#ASI_REAL", v9c }, 2626 { 0x15, "#ASI_REAL_IO", v9c }, 2627 { 0x1c, "#ASI_REAL_L", v9c }, 2628 { 0x1d, "#ASI_REAL_IO_L", v9c }, 2629 { 0x30, "#ASI_AIPP", v9d }, 2630 { 0x31, "#ASI_AIPS", v9d }, 2631 { 0x36, "#ASI_AIPN", v9d }, 2632 { 0x38, "#ASI_AIPP_L", v9d }, 2633 { 0x39, "#ASI_AIPS_L", v9d }, 2634 { 0x3e, "#ASI_AIPN_L", v9d }, 2635 { 0x42, "#ASI_INST_MASK_REG", v9d }, 2636 { 0x42, "#ASI_LSU_DIAG_REG", v9d }, 2637 { 0x43, "#ASI_ERROR_INJECT_REG", v9d }, 2638 { 0x48, "#ASI_IRF_ECC_REG", v9d }, 2639 { 0x49, "#ASI_FRF_ECC_REG", v9d }, 2640 { 0x4e, "#ASI_SPARC_PWR_MGMT", v9d }, 2641 { 0x4f, "#ASI_HYP_SCRATCHPAD", v9c }, 2642 { 0x59, "#ASI_SCRATCHPAD_ACCESS", v9d }, 2643 { 0x5a, "#ASI_TICK_ACCESS", v9d }, 2644 { 0x5b, "#ASI_TSA_ACCESS", v9d }, 2645 { 0xb0, "#ASI_PIC", v9e }, 2646 { 0xf2, "#ASI_STBI_PM", v9e }, 2647 { 0xf3, "#ASI_STBI_SM", v9e }, 2648 { 0xfa, "#ASI_STBI_PLM", v9e }, 2649 { 0xfb, "#ASI_STBI_SLM", v9e }, 2650 { 0, 0, 0 } 2651 }; 2652 2653 /* Return the a pointer to the matching sparc_asi struct, NULL if not found. */ 2654 2655 const sparc_asi * 2656 sparc_encode_asi (const char *name) 2657 { 2658 const sparc_asi *p; 2659 2660 for (p = asi_table; p->name; ++p) 2661 if (strcmp (name, p->name) == 0) 2662 return p; 2663 2664 return NULL; 2665 } 2666 2667 /* Return the name for ASI value VALUE or NULL if not found. */ 2668 2669 const char * 2670 sparc_decode_asi (int value) 2671 { 2672 const sparc_asi *p; 2673 2674 for (p = asi_table; p->name; ++p) 2675 if (value == p->value) 2676 return p->name; 2677 2678 return NULL; 2679 } 2680 2681 /* Utilities for argument parsing. */ 2682 2683 typedef struct 2684 { 2685 int value; 2686 const char *name; 2687 } arg; 2688 2689 /* Look up NAME in TABLE. */ 2690 2691 static int 2692 lookup_name (const arg *table, const char *name) 2693 { 2694 const arg *p; 2695 2696 for (p = table; p->name; ++p) 2697 if (strcmp (name, p->name) == 0) 2698 return p->value; 2699 2700 return -1; 2701 } 2702 2703 /* Look up VALUE in TABLE. */ 2704 2705 static const char * 2706 lookup_value (const arg *table, int value) 2707 { 2708 const arg *p; 2709 2710 for (p = table; p->name; ++p) 2711 if (value == p->value) 2712 return p->name; 2713 2714 return NULL; 2715 } 2716 2717 /* Handle membar masks. */ 2718 2719 static arg membar_table[] = 2720 { 2721 { 0x40, "#Sync" }, 2722 { 0x20, "#MemIssue" }, 2723 { 0x10, "#Lookaside" }, 2724 { 0x08, "#StoreStore" }, 2725 { 0x04, "#LoadStore" }, 2726 { 0x02, "#StoreLoad" }, 2727 { 0x01, "#LoadLoad" }, 2728 { 0, 0 } 2729 }; 2730 2731 /* Return the value for membar arg NAME, or -1 if not found. */ 2732 2733 int 2734 sparc_encode_membar (const char *name) 2735 { 2736 return lookup_name (membar_table, name); 2737 } 2738 2739 /* Return the name for membar value VALUE or NULL if not found. */ 2740 2741 const char * 2742 sparc_decode_membar (int value) 2743 { 2744 return lookup_value (membar_table, value); 2745 } 2746 2747 /* Handle prefetch args. */ 2748 2749 static arg prefetch_table[] = 2750 { 2751 { 0, "#n_reads" }, 2752 { 1, "#one_read" }, 2753 { 2, "#n_writes" }, 2754 { 3, "#one_write" }, 2755 { 4, "#page" }, 2756 { 16, "#invalidate" }, 2757 { 17, "#unified", }, 2758 { 20, "#n_reads_strong", }, 2759 { 21, "#one_read_strong", }, 2760 { 22, "#n_writes_strong", }, 2761 { 23, "#one_write_strong", }, 2762 { 0, 0 } 2763 }; 2764 2765 /* Return the value for prefetch arg NAME, or -1 if not found. */ 2766 2767 int 2768 sparc_encode_prefetch (const char *name) 2769 { 2770 return lookup_name (prefetch_table, name); 2771 } 2772 2773 /* Return the name for prefetch value VALUE or NULL if not found. */ 2774 2775 const char * 2776 sparc_decode_prefetch (int value) 2777 { 2778 return lookup_value (prefetch_table, value); 2779 } 2780 2781 /* Handle sparclet coprocessor registers. */ 2782 2783 static arg sparclet_cpreg_table[] = 2784 { 2785 { 0, "%ccsr" }, 2786 { 1, "%ccfr" }, 2787 { 2, "%cccrcr" }, 2788 { 3, "%ccpr" }, 2789 { 4, "%ccsr2" }, 2790 { 5, "%cccrr" }, 2791 { 6, "%ccrstr" }, 2792 { 0, 0 } 2793 }; 2794 2795 /* Return the value for sparclet cpreg arg NAME, or -1 if not found. */ 2796 2797 int 2798 sparc_encode_sparclet_cpreg (const char *name) 2799 { 2800 return lookup_name (sparclet_cpreg_table, name); 2801 } 2802 2803 /* Return the name for sparclet cpreg value VALUE or NULL if not found. */ 2804 2805 const char * 2806 sparc_decode_sparclet_cpreg (int value) 2807 { 2808 return lookup_value (sparclet_cpreg_table, value); 2809 } 2810