1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Instruction opcode table for mt. 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 6 Copyright (C) 1996-2024 Free Software Foundation, Inc. 7 8 This file is part of the GNU Binutils and/or GDB, the GNU debugger. 9 10 This file is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3, or (at your option) 13 any later version. 14 15 It is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License along 21 with this program; if not, write to the Free Software Foundation, Inc., 22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 23 24 */ 25 26 #include "sysdep.h" 27 #include "ansidecl.h" 28 #include "bfd.h" 29 #include "symcat.h" 30 #include "mt-desc.h" 31 #include "mt-opc.h" 32 #include "libiberty.h" 33 34 /* -- opc.c */ 35 #include "safe-ctype.h" 36 37 /* Special check to ensure that instruction exists for given machine. */ 38 39 int 40 mt_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) 41 { 42 int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); 43 44 /* No mach attribute? Assume it's supported for all machs. */ 45 if (machs == 0) 46 return 1; 47 48 return ((machs & cd->machs) != 0); 49 } 50 51 /* A better hash function for instruction mnemonics. */ 52 53 unsigned int 54 mt_asm_hash (const char* insn) 55 { 56 unsigned int hash; 57 const char* m = insn; 58 59 for (hash = 0; *m && ! ISSPACE (*m); m++) 60 hash = (hash * 23) ^ (0x1F & TOLOWER (*m)); 61 62 /* printf ("%s %d\n", insn, (hash % CGEN_ASM_HASH_SIZE)); */ 63 64 return hash % CGEN_ASM_HASH_SIZE; 65 } 66 67 68 /* -- asm.c */ 69 /* The hash functions are recorded here to help keep assembler code out of 70 the disassembler and vice versa. */ 71 72 static int asm_hash_insn_p (const CGEN_INSN *); 73 static unsigned int asm_hash_insn (const char *); 74 static int dis_hash_insn_p (const CGEN_INSN *); 75 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT); 76 77 /* Instruction formats. */ 78 79 #define F(f) & mt_cgen_ifld_table[MT_##f] 80 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED = { 81 0, 0, 0x0, { { 0 } } 82 }; 83 84 static const CGEN_IFMT ifmt_add ATTRIBUTE_UNUSED = { 85 32, 32, 0xff000fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } 86 }; 87 88 static const CGEN_IFMT ifmt_addi ATTRIBUTE_UNUSED = { 89 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16S) }, { 0 } } 90 }; 91 92 static const CGEN_IFMT ifmt_addui ATTRIBUTE_UNUSED = { 93 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } 94 }; 95 96 static const CGEN_IFMT ifmt_nop ATTRIBUTE_UNUSED = { 97 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU24) }, { 0 } } 98 }; 99 100 static const CGEN_IFMT ifmt_ldui ATTRIBUTE_UNUSED = { 101 32, 32, 0xfff00000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_DR) }, { F (F_IMM16U) }, { 0 } } 102 }; 103 104 static const CGEN_IFMT ifmt_brlt ATTRIBUTE_UNUSED = { 105 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } 106 }; 107 108 static const CGEN_IFMT ifmt_jmp ATTRIBUTE_UNUSED = { 109 32, 32, 0xffff0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } 110 }; 111 112 static const CGEN_IFMT ifmt_jal ATTRIBUTE_UNUSED = { 113 32, 32, 0xff0f0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } 114 }; 115 116 static const CGEN_IFMT ifmt_dbnz ATTRIBUTE_UNUSED = { 117 32, 32, 0xff0f0000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_IMM16S) }, { 0 } } 118 }; 119 120 static const CGEN_IFMT ifmt_ei ATTRIBUTE_UNUSED = { 121 32, 32, 0xffffffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } 122 }; 123 124 static const CGEN_IFMT ifmt_si ATTRIBUTE_UNUSED = { 125 32, 32, 0xffff0fff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_UU4B) }, { F (F_UU4A) }, { F (F_DRRR) }, { F (F_UU12) }, { 0 } } 126 }; 127 128 static const CGEN_IFMT ifmt_reti ATTRIBUTE_UNUSED = { 129 32, 32, 0xff0fffff, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU16) }, { 0 } } 130 }; 131 132 static const CGEN_IFMT ifmt_stw ATTRIBUTE_UNUSED = { 133 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16S) }, { 0 } } 134 }; 135 136 static const CGEN_IFMT ifmt_ldctxt ATTRIBUTE_UNUSED = { 137 32, 32, 0xff000e00, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_RC) }, { F (F_RCNUM) }, { F (F_UU_3_11) }, { F (F_CONTNUM) }, { 0 } } 138 }; 139 140 static const CGEN_IFMT ifmt_ldfb ATTRIBUTE_UNUSED = { 141 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_IMM16U) }, { 0 } } 142 }; 143 144 static const CGEN_IFMT ifmt_fbcb ATTRIBUTE_UNUSED = { 145 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_4_15) }, { F (F_RC) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 146 }; 147 148 static const CGEN_IFMT ifmt_mfbcb ATTRIBUTE_UNUSED = { 149 32, 32, 0xfc00f000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_4_15) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 150 }; 151 152 static const CGEN_IFMT ifmt_fbcci ATTRIBUTE_UNUSED = { 153 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 154 }; 155 156 static const CGEN_IFMT ifmt_mfbcci ATTRIBUTE_UNUSED = { 157 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 158 }; 159 160 static const CGEN_IFMT ifmt_fbcbdr ATTRIBUTE_UNUSED = { 161 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_BALL2) }, { F (F_BRC2) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 162 }; 163 164 static const CGEN_IFMT ifmt_rcfbcb ATTRIBUTE_UNUSED = { 165 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_BALL) }, { F (F_BRC) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 166 }; 167 168 static const CGEN_IFMT ifmt_mrcfbcb ATTRIBUTE_UNUSED = { 169 32, 32, 0xfcc08000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_UU_2_23) }, { F (F_TYPE) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ROWNUM) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 170 }; 171 172 static const CGEN_IFMT ifmt_cbcast ATTRIBUTE_UNUSED = { 173 32, 32, 0xfc000380, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_UU_3_9) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 174 }; 175 176 static const CGEN_IFMT ifmt_dupcbcast ATTRIBUTE_UNUSED = { 177 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MASK) }, { F (F_CELL) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 178 }; 179 180 static const CGEN_IFMT ifmt_wfbi ATTRIBUTE_UNUSED = { 181 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_BANKADDR) }, { F (F_ROWNUM1) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 182 }; 183 184 static const CGEN_IFMT ifmt_wfb ATTRIBUTE_UNUSED = { 185 32, 32, 0xff000040, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_UU_2_25) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_UU_1_6) }, { F (F_CTXDISP) }, { 0 } } 186 }; 187 188 static const CGEN_IFMT ifmt_rcrisc ATTRIBUTE_UNUSED = { 189 32, 32, 0xfc080000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_UU_1_19) }, { F (F_COLNUM) }, { F (F_DRRR) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 190 }; 191 192 static const CGEN_IFMT ifmt_fbcbinc ATTRIBUTE_UNUSED = { 193 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RBBC) }, { F (F_SR1) }, { F (F_INCAMT) }, { F (F_RC1) }, { F (F_CBRB) }, { F (F_CELL) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 194 }; 195 196 static const CGEN_IFMT ifmt_rcxmode ATTRIBUTE_UNUSED = { 197 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_XMODE) }, { F (F_MASK1) }, { F (F_SR2) }, { F (F_FBDISP) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 198 }; 199 200 static const CGEN_IFMT ifmt_interleaver ATTRIBUTE_UNUSED = { 201 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_MODE) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_ID) }, { F (F_SIZE) }, { 0 } } 202 }; 203 204 static const CGEN_IFMT ifmt_wfbinc ATTRIBUTE_UNUSED = { 205 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 206 }; 207 208 static const CGEN_IFMT ifmt_mwfbinc ATTRIBUTE_UNUSED = { 209 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_FBINCR) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 210 }; 211 212 static const CGEN_IFMT ifmt_wfbincr ATTRIBUTE_UNUSED = { 213 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 214 }; 215 216 static const CGEN_IFMT ifmt_mwfbincr ATTRIBUTE_UNUSED = { 217 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_RDA) }, { F (F_WR) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 218 }; 219 220 static const CGEN_IFMT ifmt_fbcbincs ATTRIBUTE_UNUSED = { 221 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_A23) }, { F (F_CR) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 222 }; 223 224 static const CGEN_IFMT ifmt_mfbcbincs ATTRIBUTE_UNUSED = { 225 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_CBS) }, { F (F_INCR) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 226 }; 227 228 static const CGEN_IFMT ifmt_fbcbincrs ATTRIBUTE_UNUSED = { 229 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_BALL) }, { F (F_COLNUM) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 230 }; 231 232 static const CGEN_IFMT ifmt_mfbcbincrs ATTRIBUTE_UNUSED = { 233 32, 32, 0xfc008000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_PERM) }, { F (F_SR1) }, { F (F_SR2) }, { F (F_UU_1_15) }, { F (F_CBX) }, { F (F_CCB) }, { F (F_CDB) }, { F (F_ROWNUM2) }, { F (F_DUP) }, { F (F_CTXDISP) }, { 0 } } 234 }; 235 236 static const CGEN_IFMT ifmt_loop ATTRIBUTE_UNUSED = { 237 32, 32, 0xff0fff00, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_SR1) }, { F (F_UU4A) }, { F (F_UU8) }, { F (F_LOOPO) }, { 0 } } 238 }; 239 240 static const CGEN_IFMT ifmt_loopi ATTRIBUTE_UNUSED = { 241 32, 32, 0xff000000, { { F (F_MSYS) }, { F (F_OPC) }, { F (F_IMM) }, { F (F_IMM16L) }, { F (F_LOOPO) }, { 0 } } 242 }; 243 244 static const CGEN_IFMT ifmt_dfbc ATTRIBUTE_UNUSED = { 245 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_RC3) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 246 }; 247 248 static const CGEN_IFMT ifmt_dwfb ATTRIBUTE_UNUSED = { 249 32, 32, 0xfc000080, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_CB1INCR) }, { F (F_CB2INCR) }, { F (F_UU1) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 250 }; 251 252 static const CGEN_IFMT ifmt_dfbr ATTRIBUTE_UNUSED = { 253 32, 32, 0xfc000000, { { F (F_MSYS) }, { F (F_MSOPC) }, { F (F_CB1SEL) }, { F (F_CB2SEL) }, { F (F_SR2) }, { F (F_LENGTH) }, { F (F_ROWNUM1) }, { F (F_ROWNUM2) }, { F (F_RC2) }, { F (F_CTXDISP) }, { 0 } } 254 }; 255 256 #undef F 257 258 #define A(a) (1 << CGEN_INSN_##a) 259 #define OPERAND(op) MT_OPERAND_##op 260 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 261 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 262 263 /* The instruction table. */ 264 265 static const CGEN_OPCODE mt_cgen_insn_opcode_table[MAX_INSNS] = 266 { 267 /* Special null first entry. 268 A `num' value of zero is thus invalid. 269 Also, the special `invalid' insn resides here. */ 270 { { 0, 0, 0, 0 }, {{0}}, 0, {0}}, 271 /* add $frdrrr,$frsr1,$frsr2 */ 272 { 273 { 0, 0, 0, 0 }, 274 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 275 & ifmt_add, { 0x0 } 276 }, 277 /* addu $frdrrr,$frsr1,$frsr2 */ 278 { 279 { 0, 0, 0, 0 }, 280 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 281 & ifmt_add, { 0x2000000 } 282 }, 283 /* addi $frdr,$frsr1,#$imm16 */ 284 { 285 { 0, 0, 0, 0 }, 286 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 287 & ifmt_addi, { 0x1000000 } 288 }, 289 /* addui $frdr,$frsr1,#$imm16z */ 290 { 291 { 0, 0, 0, 0 }, 292 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 293 & ifmt_addui, { 0x3000000 } 294 }, 295 /* sub $frdrrr,$frsr1,$frsr2 */ 296 { 297 { 0, 0, 0, 0 }, 298 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 299 & ifmt_add, { 0x4000000 } 300 }, 301 /* subu $frdrrr,$frsr1,$frsr2 */ 302 { 303 { 0, 0, 0, 0 }, 304 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 305 & ifmt_add, { 0x6000000 } 306 }, 307 /* subi $frdr,$frsr1,#$imm16 */ 308 { 309 { 0, 0, 0, 0 }, 310 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 311 & ifmt_addi, { 0x5000000 } 312 }, 313 /* subui $frdr,$frsr1,#$imm16z */ 314 { 315 { 0, 0, 0, 0 }, 316 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 317 & ifmt_addui, { 0x7000000 } 318 }, 319 /* mul $frdrrr,$frsr1,$frsr2 */ 320 { 321 { 0, 0, 0, 0 }, 322 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 323 & ifmt_add, { 0x8000000 } 324 }, 325 /* muli $frdr,$frsr1,#$imm16 */ 326 { 327 { 0, 0, 0, 0 }, 328 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 329 & ifmt_addi, { 0x9000000 } 330 }, 331 /* and $frdrrr,$frsr1,$frsr2 */ 332 { 333 { 0, 0, 0, 0 }, 334 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 335 & ifmt_add, { 0x10000000 } 336 }, 337 /* andi $frdr,$frsr1,#$imm16z */ 338 { 339 { 0, 0, 0, 0 }, 340 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 341 & ifmt_addui, { 0x11000000 } 342 }, 343 /* or $frdrrr,$frsr1,$frsr2 */ 344 { 345 { 0, 0, 0, 0 }, 346 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 347 & ifmt_add, { 0x12000000 } 348 }, 349 /* nop */ 350 { 351 { 0, 0, 0, 0 }, 352 { { MNEM, 0 } }, 353 & ifmt_nop, { 0x12000000 } 354 }, 355 /* ori $frdr,$frsr1,#$imm16z */ 356 { 357 { 0, 0, 0, 0 }, 358 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 359 & ifmt_addui, { 0x13000000 } 360 }, 361 /* xor $frdrrr,$frsr1,$frsr2 */ 362 { 363 { 0, 0, 0, 0 }, 364 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 365 & ifmt_add, { 0x14000000 } 366 }, 367 /* xori $frdr,$frsr1,#$imm16z */ 368 { 369 { 0, 0, 0, 0 }, 370 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 371 & ifmt_addui, { 0x15000000 } 372 }, 373 /* nand $frdrrr,$frsr1,$frsr2 */ 374 { 375 { 0, 0, 0, 0 }, 376 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 377 & ifmt_add, { 0x16000000 } 378 }, 379 /* nandi $frdr,$frsr1,#$imm16z */ 380 { 381 { 0, 0, 0, 0 }, 382 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 383 & ifmt_addui, { 0x17000000 } 384 }, 385 /* nor $frdrrr,$frsr1,$frsr2 */ 386 { 387 { 0, 0, 0, 0 }, 388 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 389 & ifmt_add, { 0x18000000 } 390 }, 391 /* nori $frdr,$frsr1,#$imm16z */ 392 { 393 { 0, 0, 0, 0 }, 394 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 395 & ifmt_addui, { 0x19000000 } 396 }, 397 /* xnor $frdrrr,$frsr1,$frsr2 */ 398 { 399 { 0, 0, 0, 0 }, 400 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 401 & ifmt_add, { 0x1a000000 } 402 }, 403 /* xnori $frdr,$frsr1,#$imm16z */ 404 { 405 { 0, 0, 0, 0 }, 406 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16Z), 0 } }, 407 & ifmt_addui, { 0x1b000000 } 408 }, 409 /* ldui $frdr,#$imm16z */ 410 { 411 { 0, 0, 0, 0 }, 412 { { MNEM, ' ', OP (FRDR), ',', '#', OP (IMM16Z), 0 } }, 413 & ifmt_ldui, { 0x1d000000 } 414 }, 415 /* lsl $frdrrr,$frsr1,$frsr2 */ 416 { 417 { 0, 0, 0, 0 }, 418 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 419 & ifmt_add, { 0x20000000 } 420 }, 421 /* lsli $frdr,$frsr1,#$imm16 */ 422 { 423 { 0, 0, 0, 0 }, 424 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 425 & ifmt_addi, { 0x21000000 } 426 }, 427 /* lsr $frdrrr,$frsr1,$frsr2 */ 428 { 429 { 0, 0, 0, 0 }, 430 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 431 & ifmt_add, { 0x22000000 } 432 }, 433 /* lsri $frdr,$frsr1,#$imm16 */ 434 { 435 { 0, 0, 0, 0 }, 436 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 437 & ifmt_addi, { 0x23000000 } 438 }, 439 /* asr $frdrrr,$frsr1,$frsr2 */ 440 { 441 { 0, 0, 0, 0 }, 442 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), ',', OP (FRSR2), 0 } }, 443 & ifmt_add, { 0x24000000 } 444 }, 445 /* asri $frdr,$frsr1,#$imm16 */ 446 { 447 { 0, 0, 0, 0 }, 448 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 449 & ifmt_addi, { 0x25000000 } 450 }, 451 /* brlt $frsr1,$frsr2,$imm16o */ 452 { 453 { 0, 0, 0, 0 }, 454 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, 455 & ifmt_brlt, { 0x31000000 } 456 }, 457 /* brle $frsr1,$frsr2,$imm16o */ 458 { 459 { 0, 0, 0, 0 }, 460 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, 461 & ifmt_brlt, { 0x33000000 } 462 }, 463 /* breq $frsr1,$frsr2,$imm16o */ 464 { 465 { 0, 0, 0, 0 }, 466 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, 467 & ifmt_brlt, { 0x35000000 } 468 }, 469 /* brne $frsr1,$frsr2,$imm16o */ 470 { 471 { 0, 0, 0, 0 }, 472 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', OP (IMM16O), 0 } }, 473 & ifmt_brlt, { 0x3b000000 } 474 }, 475 /* jmp $imm16o */ 476 { 477 { 0, 0, 0, 0 }, 478 { { MNEM, ' ', OP (IMM16O), 0 } }, 479 & ifmt_jmp, { 0x37000000 } 480 }, 481 /* jal $frdrrr,$frsr1 */ 482 { 483 { 0, 0, 0, 0 }, 484 { { MNEM, ' ', OP (FRDRRR), ',', OP (FRSR1), 0 } }, 485 & ifmt_jal, { 0x38000000 } 486 }, 487 /* dbnz $frsr1,$imm16o */ 488 { 489 { 0, 0, 0, 0 }, 490 { { MNEM, ' ', OP (FRSR1), ',', OP (IMM16O), 0 } }, 491 & ifmt_dbnz, { 0x3d000000 } 492 }, 493 /* ei */ 494 { 495 { 0, 0, 0, 0 }, 496 { { MNEM, 0 } }, 497 & ifmt_ei, { 0x60000000 } 498 }, 499 /* di */ 500 { 501 { 0, 0, 0, 0 }, 502 { { MNEM, 0 } }, 503 & ifmt_ei, { 0x62000000 } 504 }, 505 /* si $frdrrr */ 506 { 507 { 0, 0, 0, 0 }, 508 { { MNEM, ' ', OP (FRDRRR), 0 } }, 509 & ifmt_si, { 0x64000000 } 510 }, 511 /* reti $frsr1 */ 512 { 513 { 0, 0, 0, 0 }, 514 { { MNEM, ' ', OP (FRSR1), 0 } }, 515 & ifmt_reti, { 0x66000000 } 516 }, 517 /* ldw $frdr,$frsr1,#$imm16 */ 518 { 519 { 0, 0, 0, 0 }, 520 { { MNEM, ' ', OP (FRDR), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 521 & ifmt_addi, { 0x41000000 } 522 }, 523 /* stw $frsr2,$frsr1,#$imm16 */ 524 { 525 { 0, 0, 0, 0 }, 526 { { MNEM, ' ', OP (FRSR2), ',', OP (FRSR1), ',', '#', OP (IMM16), 0 } }, 527 & ifmt_stw, { 0x43000000 } 528 }, 529 /* break */ 530 { 531 { 0, 0, 0, 0 }, 532 { { MNEM, 0 } }, 533 & ifmt_nop, { 0x68000000 } 534 }, 535 /* iflush */ 536 { 537 { 0, 0, 0, 0 }, 538 { { MNEM, 0 } }, 539 & ifmt_nop, { 0x6a000000 } 540 }, 541 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */ 542 { 543 { 0, 0, 0, 0 }, 544 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RC), ',', '#', OP (RCNUM), ',', '#', OP (CONTNUM), 0 } }, 545 & ifmt_ldctxt, { 0x80000000 } 546 }, 547 /* ldfb $frsr1,$frsr2,#$imm16z */ 548 { 549 { 0, 0, 0, 0 }, 550 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, 551 & ifmt_ldfb, { 0x84000000 } 552 }, 553 /* stfb $frsr1,$frsr2,#$imm16z */ 554 { 555 { 0, 0, 0, 0 }, 556 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (IMM16Z), 0 } }, 557 & ifmt_ldfb, { 0x88000000 } 558 }, 559 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 560 { 561 { 0, 0, 0, 0 }, 562 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 563 & ifmt_fbcb, { 0x8c000000 } 564 }, 565 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 566 { 567 { 0, 0, 0, 0 }, 568 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 569 & ifmt_mfbcb, { 0x90000000 } 570 }, 571 /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 572 { 573 { 0, 0, 0, 0 }, 574 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 575 & ifmt_fbcci, { 0x94000000 } 576 }, 577 /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 578 { 579 { 0, 0, 0, 0 }, 580 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 581 & ifmt_fbcci, { 0x98000000 } 582 }, 583 /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 584 { 585 { 0, 0, 0, 0 }, 586 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 587 & ifmt_fbcci, { 0x9c000000 } 588 }, 589 /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 590 { 591 { 0, 0, 0, 0 }, 592 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 593 & ifmt_fbcci, { 0xa0000000 } 594 }, 595 /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 596 { 597 { 0, 0, 0, 0 }, 598 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 599 & ifmt_mfbcci, { 0xa4000000 } 600 }, 601 /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 602 { 603 { 0, 0, 0, 0 }, 604 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 605 & ifmt_mfbcci, { 0xa8000000 } 606 }, 607 /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 608 { 609 { 0, 0, 0, 0 }, 610 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 611 & ifmt_mfbcci, { 0xac000000 } 612 }, 613 /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */ 614 { 615 { 0, 0, 0, 0 }, 616 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 617 & ifmt_mfbcci, { 0xb0000000 } 618 }, 619 /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 620 { 621 { 0, 0, 0, 0 }, 622 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', OP (FRSR2), ',', '#', OP (BALL2), ',', '#', OP (BRC2), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 623 & ifmt_fbcbdr, { 0xb4000000 } 624 }, 625 /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 626 { 627 { 0, 0, 0, 0 }, 628 { { MNEM, ' ', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (BALL), ',', '#', OP (BRC), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 629 & ifmt_rcfbcb, { 0xb8000000 } 630 }, 631 /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 632 { 633 { 0, 0, 0, 0 }, 634 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RBBC), ',', '#', OP (TYPE), ',', '#', OP (ROWNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 635 & ifmt_mrcfbcb, { 0xbc000000 } 636 }, 637 /* cbcast #$mask,#$rc2,#$ctxdisp */ 638 { 639 { 0, 0, 0, 0 }, 640 { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 641 & ifmt_cbcast, { 0xc0000000 } 642 }, 643 /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */ 644 { 645 { 0, 0, 0, 0 }, 646 { { MNEM, ' ', '#', OP (MASK), ',', '#', OP (CELL), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 647 & ifmt_dupcbcast, { 0xc4000000 } 648 }, 649 /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */ 650 { 651 { 0, 0, 0, 0 }, 652 { { MNEM, ' ', '#', OP (BANKADDR), ',', '#', OP (ROWNUM1), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 653 & ifmt_wfbi, { 0xc8000000 } 654 }, 655 /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */ 656 { 657 { 0, 0, 0, 0 }, 658 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (CTXDISP), 0 } }, 659 & ifmt_wfb, { 0xcc000000 } 660 }, 661 /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 662 { 663 { 0, 0, 0, 0 }, 664 { { MNEM, ' ', OP (FRDRRR), ',', '#', OP (RBBC), ',', OP (FRSR1), ',', '#', OP (COLNUM), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 665 & ifmt_rcrisc, { 0xd0000000 } 666 }, 667 /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */ 668 { 669 { 0, 0, 0, 0 }, 670 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RBBC), ',', '#', OP (INCAMT), ',', '#', OP (RC1), ',', '#', OP (CBRB), ',', '#', OP (CELL), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 671 & ifmt_fbcbinc, { 0xd4000000 } 672 }, 673 /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */ 674 { 675 { 0, 0, 0, 0 }, 676 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (XMODE), ',', '#', OP (MASK1), ',', '#', OP (FBDISP), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 677 & ifmt_rcxmode, { 0xd8000000 } 678 }, 679 /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */ 680 { 681 { 0, 0, 0, 0 }, 682 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (MODE), ',', OP (FRSR2), ',', '#', OP (ID), ',', '#', OP (SIZE), 0 } }, 683 & ifmt_interleaver, { 0xdc000000 } 684 }, 685 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 686 { 687 { 0, 0, 0, 0 }, 688 { { MNEM, ' ', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 689 & ifmt_wfbinc, { 0xe0000000 } 690 }, 691 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 692 { 693 { 0, 0, 0, 0 }, 694 { { MNEM, ' ', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (FBINCR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 695 & ifmt_mwfbinc, { 0xe4000000 } 696 }, 697 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 698 { 699 { 0, 0, 0, 0 }, 700 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 701 & ifmt_wfbincr, { 0xe8000000 } 702 }, 703 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */ 704 { 705 { 0, 0, 0, 0 }, 706 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (RDA), ',', '#', OP (WR), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 707 & ifmt_mwfbincr, { 0xec000000 } 708 }, 709 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 710 { 711 { 0, 0, 0, 0 }, 712 { { MNEM, ' ', '#', OP (PERM), ',', '#', OP (A23), ',', '#', OP (CR), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 713 & ifmt_fbcbincs, { 0xf0000000 } 714 }, 715 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 716 { 717 { 0, 0, 0, 0 }, 718 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (CBS), ',', '#', OP (INCR), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 719 & ifmt_mfbcbincs, { 0xf4000000 } 720 }, 721 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 722 { 723 { 0, 0, 0, 0 }, 724 { { MNEM, ' ', OP (FRSR1), ',', '#', OP (PERM), ',', '#', OP (BALL), ',', '#', OP (COLNUM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 725 & ifmt_fbcbincrs, { 0xf8000000 } 726 }, 727 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */ 728 { 729 { 0, 0, 0, 0 }, 730 { { MNEM, ' ', OP (FRSR1), ',', OP (FRSR2), ',', '#', OP (PERM), ',', '#', OP (CBX), ',', '#', OP (CCB), ',', '#', OP (CDB), ',', '#', OP (ROWNUM2), ',', '#', OP (DUP), ',', '#', OP (CTXDISP), 0 } }, 731 & ifmt_mfbcbincrs, { 0xfc000000 } 732 }, 733 /* loop $frsr1,$loopsize */ 734 { 735 { 0, 0, 0, 0 }, 736 { { MNEM, ' ', OP (FRSR1), ',', OP (LOOPSIZE), 0 } }, 737 & ifmt_loop, { 0x3e000000 } 738 }, 739 /* loopi #$imm16l,$loopsize */ 740 { 741 { 0, 0, 0, 0 }, 742 { { MNEM, ' ', '#', OP (IMM16L), ',', OP (LOOPSIZE), 0 } }, 743 & ifmt_loopi, { 0x3f000000 } 744 }, 745 /* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ 746 { 747 { 0, 0, 0, 0 }, 748 { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 749 & ifmt_dfbc, { 0x80000000 } 750 }, 751 /* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */ 752 { 753 { 0, 0, 0, 0 }, 754 { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 755 & ifmt_dwfb, { 0x84000000 } 756 }, 757 /* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */ 758 { 759 { 0, 0, 0, 0 }, 760 { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', '#', OP (CB1INCR), ',', '#', OP (CB2INCR), ',', '#', OP (RC3), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 761 & ifmt_dfbc, { 0x88000000 } 762 }, 763 /* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */ 764 { 765 { 0, 0, 0, 0 }, 766 { { MNEM, ' ', '#', OP (CB1SEL), ',', '#', OP (CB2SEL), ',', OP (FRSR2), ',', '#', OP (LENGTH), ',', '#', OP (ROWNUM1), ',', '#', OP (ROWNUM2), ',', '#', OP (RC2), ',', '#', OP (CTXDISP), 0 } }, 767 & ifmt_dfbr, { 0x8c000000 } 768 }, 769 }; 770 771 #undef A 772 #undef OPERAND 773 #undef MNEM 774 #undef OP 775 776 /* Formats for ALIAS macro-insns. */ 777 778 #define F(f) & mt_cgen_ifld_table[MT_##f] 779 #undef F 780 781 /* Each non-simple macro entry points to an array of expansion possibilities. */ 782 783 #define A(a) (1 << CGEN_INSN_##a) 784 #define OPERAND(op) MT_OPERAND_##op 785 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */ 786 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field)) 787 788 /* The macro instruction table. */ 789 790 static const CGEN_IBASE mt_cgen_macro_insn_table[] = 791 { 792 }; 793 794 /* The macro instruction opcode table. */ 795 796 static const CGEN_OPCODE mt_cgen_macro_insn_opcode_table[] = 797 { 798 }; 799 800 #undef A 801 #undef OPERAND 802 #undef MNEM 803 #undef OP 804 805 #ifndef CGEN_ASM_HASH_P 806 #define CGEN_ASM_HASH_P(insn) 1 807 #endif 808 809 #ifndef CGEN_DIS_HASH_P 810 #define CGEN_DIS_HASH_P(insn) 1 811 #endif 812 813 /* Return non-zero if INSN is to be added to the hash table. 814 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */ 815 816 static int 817 asm_hash_insn_p (const CGEN_INSN *insn ATTRIBUTE_UNUSED) 818 { 819 return CGEN_ASM_HASH_P (insn); 820 } 821 822 static int 823 dis_hash_insn_p (const CGEN_INSN *insn) 824 { 825 /* If building the hash table and the NO-DIS attribute is present, 826 ignore. */ 827 if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_NO_DIS)) 828 return 0; 829 return CGEN_DIS_HASH_P (insn); 830 } 831 832 #ifndef CGEN_ASM_HASH 833 #define CGEN_ASM_HASH_SIZE 127 834 #ifdef CGEN_MNEMONIC_OPERANDS 835 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) 836 #else 837 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/ 838 #endif 839 #endif 840 841 /* It doesn't make much sense to provide a default here, 842 but while this is under development we do. 843 BUFFER is a pointer to the bytes of the insn, target order. 844 VALUE is the first base_insn_bitsize bits as an int in host order. */ 845 846 #ifndef CGEN_DIS_HASH 847 #define CGEN_DIS_HASH_SIZE 256 848 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf)) 849 #endif 850 851 /* The result is the hash value of the insn. 852 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */ 853 854 static unsigned int 855 asm_hash_insn (const char *mnem) 856 { 857 return CGEN_ASM_HASH (mnem); 858 } 859 860 /* BUF is a pointer to the bytes of the insn, target order. 861 VALUE is the first base_insn_bitsize bits as an int in host order. */ 862 863 static unsigned int 864 dis_hash_insn (const char *buf ATTRIBUTE_UNUSED, 865 CGEN_INSN_INT value ATTRIBUTE_UNUSED) 866 { 867 return CGEN_DIS_HASH (buf, value); 868 } 869 870 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */ 871 872 static void 873 set_fields_bitsize (CGEN_FIELDS *fields, int size) 874 { 875 CGEN_FIELDS_BITSIZE (fields) = size; 876 } 877 878 /* Function to call before using the operand instance table. 879 This plugs the opcode entries and macro instructions into the cpu table. */ 880 881 void 882 mt_cgen_init_opcode_table (CGEN_CPU_DESC cd) 883 { 884 int i; 885 int num_macros = (sizeof (mt_cgen_macro_insn_table) / 886 sizeof (mt_cgen_macro_insn_table[0])); 887 const CGEN_IBASE *ib = & mt_cgen_macro_insn_table[0]; 888 const CGEN_OPCODE *oc = & mt_cgen_macro_insn_opcode_table[0]; 889 CGEN_INSN *insns = xmalloc (num_macros * sizeof (CGEN_INSN)); 890 891 /* This test has been added to avoid a warning generated 892 if memset is called with a third argument of value zero. */ 893 if (num_macros >= 1) 894 memset (insns, 0, num_macros * sizeof (CGEN_INSN)); 895 for (i = 0; i < num_macros; ++i) 896 { 897 insns[i].base = &ib[i]; 898 insns[i].opcode = &oc[i]; 899 mt_cgen_build_insn_regex (& insns[i]); 900 } 901 cd->macro_insn_table.init_entries = insns; 902 cd->macro_insn_table.entry_size = sizeof (CGEN_IBASE); 903 cd->macro_insn_table.num_init_entries = num_macros; 904 905 oc = & mt_cgen_insn_opcode_table[0]; 906 insns = (CGEN_INSN *) cd->insn_table.init_entries; 907 for (i = 0; i < MAX_INSNS; ++i) 908 { 909 insns[i].opcode = &oc[i]; 910 mt_cgen_build_insn_regex (& insns[i]); 911 } 912 913 cd->sizeof_fields = sizeof (CGEN_FIELDS); 914 cd->set_fields_bitsize = set_fields_bitsize; 915 916 cd->asm_hash_p = asm_hash_insn_p; 917 cd->asm_hash = asm_hash_insn; 918 cd->asm_hash_size = CGEN_ASM_HASH_SIZE; 919 920 cd->dis_hash_p = dis_hash_insn_p; 921 cd->dis_hash = dis_hash_insn; 922 cd->dis_hash_size = CGEN_DIS_HASH_SIZE; 923 } 924