1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */ 2 /* Disassembler interface for targets using CGEN. -*- C -*- 3 CGEN: Cpu tools GENerator 4 5 THIS FILE IS MACHINE GENERATED WITH CGEN. 6 - the resultant file is machine generated, cgen-dis.in isn't 7 8 Copyright (C) 1996-2024 Free Software Foundation, Inc. 9 10 This file is part of libopcodes. 11 12 This library is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 3, or (at your option) 15 any later version. 16 17 It is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software Foundation, Inc., 24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 25 26 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 27 Keep that in mind. */ 28 29 #include "sysdep.h" 30 #include <stdio.h> 31 #include "ansidecl.h" 32 #include "disassemble.h" 33 #include "bfd.h" 34 #include "symcat.h" 35 #include "libiberty.h" 36 #include "mep-desc.h" 37 #include "mep-opc.h" 38 #include "opintl.h" 39 40 /* Default text to print if an instruction isn't recognized. */ 41 #define UNKNOWN_INSN_MSG _("*unknown*") 42 43 static void print_normal 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 45 static void print_address 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 47 static void print_keyword 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 49 static void print_insn_normal 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 51 static int print_insn 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 53 static int default_print_insn 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 55 static int read_insn 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 57 unsigned long *); 58 59 /* -- disassembler routines inserted here. */ 60 61 /* -- dis.c */ 62 63 #include "elf/mep.h" 64 #include "elf-bfd.h" 65 66 #define CGEN_VALIDATE_INSN_SUPPORTED 67 68 static void 69 print_tpreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info, 70 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, 71 unsigned int flags ATTRIBUTE_UNUSED) 72 { 73 disassemble_info *info = (disassemble_info *) dis_info; 74 75 (*info->fprintf_func) (info->stream, "$tp"); 76 } 77 78 static void 79 print_spreg (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, void *dis_info, 80 CGEN_KEYWORD *table ATTRIBUTE_UNUSED, long val ATTRIBUTE_UNUSED, 81 unsigned int flags ATTRIBUTE_UNUSED) 82 { 83 disassemble_info *info = (disassemble_info *) dis_info; 84 85 (*info->fprintf_func) (info->stream, "$sp"); 86 } 87 88 /* begin-cop-ip-print-handlers */ 89 static void 90 print_ivc2_cr (CGEN_CPU_DESC, 91 void *, 92 CGEN_KEYWORD *, 93 long, 94 unsigned int) ATTRIBUTE_UNUSED; 95 static void 96 print_ivc2_cr (CGEN_CPU_DESC cd, 97 void *dis_info, 98 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, 99 long value, 100 unsigned int attrs) 101 { 102 print_keyword (cd, dis_info, & mep_cgen_opval_h_cr_ivc2, value, attrs); 103 } 104 static void 105 print_ivc2_ccr (CGEN_CPU_DESC, 106 void *, 107 CGEN_KEYWORD *, 108 long, 109 unsigned int) ATTRIBUTE_UNUSED; 110 static void 111 print_ivc2_ccr (CGEN_CPU_DESC cd, 112 void *dis_info, 113 CGEN_KEYWORD *keyword_table ATTRIBUTE_UNUSED, 114 long value, 115 unsigned int attrs) 116 { 117 print_keyword (cd, dis_info, & mep_cgen_opval_h_ccr_ivc2, value, attrs); 118 } 119 /* end-cop-ip-print-handlers */ 120 121 /************************************************************\ 122 *********************** Experimental ************************* 123 \************************************************************/ 124 125 #undef CGEN_PRINT_INSN 126 #define CGEN_PRINT_INSN mep_print_insn 127 128 static int 129 mep_print_vliw_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info, 130 bfd_byte *buf, int corelength, int copro1length, 131 int copro2length ATTRIBUTE_UNUSED) 132 { 133 int i; 134 int status = 0; 135 /* char insnbuf[CGEN_MAX_INSN_SIZE]; */ 136 bfd_byte insnbuf[64]; 137 138 /* If corelength > 0 then there is a core insn present. It 139 will be at the beginning of the buffer. After printing 140 the core insn, we need to print the + on the next line. */ 141 if (corelength > 0) 142 { 143 int my_status = 0; 144 145 for (i = 0; i < corelength; i++ ) 146 insnbuf[i] = buf[i]; 147 cd->isas = & MEP_CORE_ISA; 148 149 my_status = print_insn (cd, pc, info, insnbuf, corelength); 150 if (my_status != corelength) 151 { 152 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 153 my_status = corelength; 154 } 155 status += my_status; 156 157 /* Print the + to indicate that the following copro insn is 158 part of a vliw group. */ 159 if (copro1length > 0) 160 (*info->fprintf_func) (info->stream, " + "); 161 } 162 163 /* Now all that is left to be processed is the coprocessor insns 164 In vliw mode, there will always be one. Its positioning will 165 be from byte corelength to byte corelength+copro1length -1. 166 No need to check for existence. Also, the first vliw insn, 167 will, as spec'd, always be at least as long as the core insn 168 so we don't need to flush the buffer. */ 169 if (copro1length > 0) 170 { 171 int my_status = 0; 172 173 for (i = corelength; i < corelength + copro1length; i++ ) 174 insnbuf[i - corelength] = buf[i]; 175 176 switch (copro1length) 177 { 178 case 0: 179 break; 180 case 2: 181 cd->isas = & MEP_COP16_ISA; 182 break; 183 case 4: 184 cd->isas = & MEP_COP32_ISA; 185 break; 186 case 6: 187 cd->isas = & MEP_COP48_ISA; 188 break; 189 case 8: 190 cd->isas = & MEP_COP64_ISA; 191 break; 192 default: 193 /* Shouldn't be anything but 16,32,48,64. */ 194 break; 195 } 196 197 my_status = print_insn (cd, pc, info, insnbuf, copro1length); 198 199 if (my_status != copro1length) 200 { 201 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 202 my_status = copro1length; 203 } 204 status += my_status; 205 } 206 207 #if 0 208 /* Now we need to process the second copro insn if it exists. We 209 have no guarantee that the second copro insn will be longer 210 than the first, so we have to flush the buffer if we are have 211 a second copro insn to process. If present, this insn will 212 be in the position from byte corelength+copro1length to byte 213 corelength+copro1length+copro2length-1 (which better equal 8 214 or else we're in big trouble. */ 215 if (copro2length > 0) 216 { 217 int my_status = 0; 218 219 for (i = 0; i < 64 ; i++) 220 insnbuf[i] = 0; 221 222 for (i = corelength + copro1length; i < 64; i++) 223 insnbuf[i - (corelength + copro1length)] = buf[i]; 224 225 switch (copro2length) 226 { 227 case 2: 228 cd->isas = 1 << ISA_EXT_COP1_16; 229 break; 230 case 4: 231 cd->isas = 1 << ISA_EXT_COP1_32; 232 break; 233 case 6: 234 cd->isas = 1 << ISA_EXT_COP1_48; 235 break; 236 case 8: 237 cd->isas = 1 << ISA_EXT_COP1_64; 238 break; 239 default: 240 /* Shouldn't be anything but 16,32,48,64. */ 241 break; 242 } 243 244 my_status = print_insn (cd, pc, info, insnbuf, copro2length); 245 246 if (my_status != copro2length) 247 { 248 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 249 my_status = copro2length; 250 } 251 252 status += my_status; 253 } 254 #endif 255 256 /* Status should now be the number of bytes that were printed 257 which should be 4 for VLIW32 mode and 64 for VLIW64 mode. */ 258 259 if ((!MEP_VLIW64 && (status != 4)) || (MEP_VLIW64 && (status != 8))) 260 return -1; 261 else 262 return status; 263 } 264 265 /* The two functions mep_examine_vliw[32,64]_insns are used find out 266 which vliw combinaion (16 bit core with 48 bit copro, 32 bit core 267 with 32 bit copro, etc.) is present. Later on, when internally 268 parallel coprocessors are handled, only these functions should 269 need to be changed. 270 271 At this time only the following combinations are supported: 272 273 VLIW32 Mode: 274 16 bit core insn (core) and 16 bit coprocessor insn (cop1) 275 32 bit core insn (core) 276 32 bit coprocessor insn (cop1) 277 Note: As of this time, I do not believe we have enough information 278 to distinguish a 32 bit core insn from a 32 bit cop insn. Also, 279 no 16 bit coprocessor insns have been specified. 280 281 VLIW64 Mode: 282 16 bit core insn (core) and 48 bit coprocessor insn (cop1) 283 32 bit core insn (core) and 32 bit coprocessor insn (cop1) 284 64 bit coprocessor insn (cop1) 285 286 The framework for an internally parallel coprocessor is also 287 present (2nd coprocessor insn is cop2), but at this time it 288 is not used. This only appears to be valid in VLIW64 mode. */ 289 290 static int 291 mep_examine_vliw32_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 292 { 293 int status; 294 int buflength; 295 int corebuflength; 296 int cop1buflength; 297 int cop2buflength; 298 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 299 char indicator16[1]; 300 char indicatorcop32[2]; 301 302 /* At this time we're not supporting internally parallel coprocessors, 303 so cop2buflength will always be 0. */ 304 cop2buflength = 0; 305 306 /* Read in 32 bits. */ 307 buflength = 4; /* VLIW insn spans 4 bytes. */ 308 status = (*info->read_memory_func) (pc, buf, buflength, info); 309 310 if (status != 0) 311 { 312 (*info->memory_error_func) (status, pc, info); 313 return -1; 314 } 315 316 /* Put the big endian representation of the bytes to be examined 317 in the temporary buffers for examination. */ 318 319 if (info->endian == BFD_ENDIAN_BIG) 320 { 321 indicator16[0] = buf[0]; 322 indicatorcop32[0] = buf[0]; 323 indicatorcop32[1] = buf[1]; 324 } 325 else 326 { 327 indicator16[0] = buf[1]; 328 indicatorcop32[0] = buf[1]; 329 indicatorcop32[1] = buf[0]; 330 } 331 332 /* If the two high order bits are 00, 01 or 10, we have a 16 bit 333 core insn and a 48 bit copro insn. */ 334 335 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) 336 { 337 if ((indicatorcop32[0] & 0xf0) == 0xf0 && (indicatorcop32[1] & 0x07) == 0x07) 338 { 339 /* We have a 32 bit copro insn. */ 340 corebuflength = 0; 341 /* All 4 4ytes are one copro insn. */ 342 cop1buflength = 4; 343 } 344 else 345 { 346 /* We have a 32 bit core. */ 347 corebuflength = 4; 348 cop1buflength = 0; 349 } 350 } 351 else 352 { 353 /* We have a 16 bit core insn and a 16 bit copro insn. */ 354 corebuflength = 2; 355 cop1buflength = 2; 356 } 357 358 /* Now we have the distrubution set. Print them out. */ 359 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, 360 cop1buflength, cop2buflength); 361 362 return status; 363 } 364 365 static int 366 mep_examine_vliw64_insns (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 367 { 368 int status; 369 int buflength; 370 int corebuflength; 371 int cop1buflength; 372 int cop2buflength; 373 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 374 char indicator16[1]; 375 char indicator64[4]; 376 377 /* At this time we're not supporting internally parallel 378 coprocessors, so cop2buflength will always be 0. */ 379 cop2buflength = 0; 380 381 /* Read in 64 bits. */ 382 buflength = 8; /* VLIW insn spans 8 bytes. */ 383 status = (*info->read_memory_func) (pc, buf, buflength, info); 384 385 if (status != 0) 386 { 387 (*info->memory_error_func) (status, pc, info); 388 return -1; 389 } 390 391 /* We have all 64 bits in the buffer now. We have to figure out 392 what combination of instruction sizes are present. The two 393 high order bits will indicate whether or not we have a 16 bit 394 core insn or not. If not, then we have to look at the 7,8th 395 bytes to tell whether we have 64 bit copro insn or a 32 bit 396 core insn with a 32 bit copro insn. Endianness will make a 397 difference here. */ 398 399 /* Put the big endian representation of the bytes to be examined 400 in the temporary buffers for examination. */ 401 402 /* indicator16[0] = buf[0]; */ 403 if (info->endian == BFD_ENDIAN_BIG) 404 { 405 indicator16[0] = buf[0]; 406 indicator64[0] = buf[0]; 407 indicator64[1] = buf[1]; 408 indicator64[2] = buf[2]; 409 indicator64[3] = buf[3]; 410 } 411 else 412 { 413 indicator16[0] = buf[1]; 414 indicator64[0] = buf[1]; 415 indicator64[1] = buf[0]; 416 indicator64[2] = buf[3]; 417 indicator64[3] = buf[2]; 418 } 419 420 /* If the two high order bits are 00, 01 or 10, we have a 16 bit 421 core insn and a 48 bit copro insn. */ 422 423 if ((indicator16[0] & 0x80) && (indicator16[0] & 0x40)) 424 { 425 if ((indicator64[0] & 0xf0) == 0xf0 && (indicator64[1] & 0x07) == 0x07 426 && ((indicator64[2] & 0xfe) != 0xf0 || (indicator64[3] & 0xf4) != 0)) 427 { 428 /* We have a 64 bit copro insn. */ 429 corebuflength = 0; 430 /* All 8 bytes are one copro insn. */ 431 cop1buflength = 8; 432 } 433 else 434 { 435 /* We have a 32 bit core insn and a 32 bit copro insn. */ 436 corebuflength = 4; 437 cop1buflength = 4; 438 } 439 } 440 else 441 { 442 /* We have a 16 bit core insn and a 48 bit copro insn. */ 443 corebuflength = 2; 444 cop1buflength = 6; 445 } 446 447 /* Now we have the distrubution set. Print them out. */ 448 status = mep_print_vliw_insns (cd, pc, info, buf, corebuflength, 449 cop1buflength, cop2buflength); 450 451 return status; 452 } 453 454 #ifdef MEP_IVC2_SUPPORTED 455 456 static int 457 print_slot_insn (CGEN_CPU_DESC cd, 458 bfd_vma pc, 459 disassemble_info *info, 460 SLOTS_ATTR slot, 461 bfd_byte *buf) 462 { 463 const CGEN_INSN_LIST *insn_list; 464 CGEN_INSN_INT insn_value; 465 CGEN_EXTRACT_INFO ex_info; 466 467 insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); 468 469 /* Fill in ex_info fields like read_insn would. Don't actually call 470 read_insn, since the incoming buffer is already read (and possibly 471 modified a la m32r). */ 472 ex_info.valid = (1 << 8) - 1; 473 ex_info.dis_info = info; 474 ex_info.insn_bytes = buf; 475 476 /* The instructions are stored in hash lists. 477 Pick the first one and keep trying until we find the right one. */ 478 479 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 480 while (insn_list != NULL) 481 { 482 const CGEN_INSN *insn = insn_list->insn; 483 CGEN_FIELDS fields; 484 int length; 485 486 if ((CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) 487 && CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_CONFIG) != MEP_CONFIG) 488 || ! (CGEN_ATTR_CGEN_INSN_SLOTS_VALUE (CGEN_INSN_ATTRS (insn)) & (1 << slot))) 489 { 490 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 491 continue; 492 } 493 494 if ((insn_value & CGEN_INSN_BASE_MASK (insn)) 495 == CGEN_INSN_BASE_VALUE (insn)) 496 { 497 /* Printing is handled in two passes. The first pass parses the 498 machine insn and extracts the fields. The second pass prints 499 them. */ 500 501 length = CGEN_EXTRACT_FN (cd, insn) 502 (cd, insn, &ex_info, insn_value, &fields, pc); 503 504 /* Length < 0 -> error. */ 505 if (length < 0) 506 return length; 507 if (length > 0) 508 { 509 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 510 /* Length is in bits, result is in bytes. */ 511 return length / 8; 512 } 513 } 514 515 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 516 } 517 518 if (slot == SLOTS_P0S) 519 (*info->fprintf_func) (info->stream, "*unknown-p0s*"); 520 else if (slot == SLOTS_P0) 521 (*info->fprintf_func) (info->stream, "*unknown-p0*"); 522 else if (slot == SLOTS_P1) 523 (*info->fprintf_func) (info->stream, "*unknown-p1*"); 524 else if (slot == SLOTS_C3) 525 (*info->fprintf_func) (info->stream, "*unknown-c3*"); 526 return 0; 527 } 528 529 static int 530 mep_examine_ivc2_insns (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, bfd_vma pc ATTRIBUTE_UNUSED, disassemble_info *info ATTRIBUTE_UNUSED) 531 { 532 int status; 533 int buflength; 534 bfd_byte buf[8]; 535 bfd_byte insn[8]; 536 int e; 537 538 /* Read in 64 bits. */ 539 buflength = 8; /* VLIW insn spans 8 bytes. */ 540 status = (*info->read_memory_func) (pc, buf, buflength, info); 541 542 if (status != 0) 543 { 544 (*info->memory_error_func) (status, pc, info); 545 return -1; 546 } 547 548 if (info->endian == BFD_ENDIAN_LITTLE) 549 e = 1; 550 else 551 e = 0; 552 553 if (((unsigned char)buf[0^e] & 0xf0) < 0xc0) 554 { 555 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ 556 /* V1 [-----core-----][--------p0s-------][------------p1------------] */ 557 558 print_insn (cd, pc, info, buf, 2); 559 560 insn[0^e] = 0; 561 insn[1^e] = buf[2^e]; 562 insn[2^e] = buf[3^e]; 563 insn[3^e] = buf[4^e] & 0xf0; 564 (*info->fprintf_func) (info->stream, " + "); 565 print_slot_insn (cd, pc, info, SLOTS_P0S, insn); 566 567 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; 568 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; 569 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; 570 insn[3^e] = buf[7^e] << 4; 571 (*info->fprintf_func) (info->stream, " + "); 572 print_slot_insn (cd, pc, info, SLOTS_P1, insn); 573 } 574 else if ((buf[0^e] & 0xf0) == 0xf0 && (buf[1^e] & 0x0f) == 0x07) 575 { 576 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ 577 /* V3 1111[--p0--]0111[--------p0--------][------------p1------------] */ 578 /* 00000000111111112222222233333333 */ 579 580 insn[0^e] = buf[0^e] << 4 | buf[1^e] >> 4; 581 insn[1^e] = buf[2^e]; 582 insn[2^e] = buf[3^e]; 583 insn[3^e] = buf[4^e] & 0xf0; 584 print_slot_insn (cd, pc, info, SLOTS_P0, insn); 585 586 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; 587 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; 588 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; 589 insn[3^e] = buf[7^e] << 4; 590 (*info->fprintf_func) (info->stream, " + "); 591 print_slot_insn (cd, pc, info, SLOTS_P1, insn); 592 } 593 else 594 { 595 /* <--00--><--11--><--22--><--33--><--44--><--55--><--66--><--77--> */ 596 /* V2 [-------------core-------------]xxxx[------------p1------------] */ 597 print_insn (cd, pc, info, buf, 4); 598 599 insn[0^e] = buf[4^e] << 4 | buf[5^e] >> 4; 600 insn[1^e] = buf[5^e] << 4 | buf[6^e] >> 4; 601 insn[2^e] = buf[6^e] << 4 | buf[7^e] >> 4; 602 insn[3^e] = buf[7^e] << 4; 603 (*info->fprintf_func) (info->stream, " + "); 604 print_slot_insn (cd, pc, info, SLOTS_P1, insn); 605 } 606 607 return 8; 608 } 609 610 #endif /* MEP_IVC2_SUPPORTED */ 611 612 /* This is a hack. SID calls this to update the disassembler as the 613 CPU changes modes. */ 614 static int mep_ivc2_disassemble_p = 0; 615 static int mep_ivc2_vliw_disassemble_p = 0; 616 617 void 618 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx); 619 void 620 mep_print_insn_set_ivc2_mode (int ivc2_p, int vliw_p, int cfg_idx) 621 { 622 mep_ivc2_disassemble_p = ivc2_p; 623 mep_ivc2_vliw_disassemble_p = vliw_p; 624 mep_config_index = cfg_idx; 625 } 626 627 static int 628 mep_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 629 { 630 int status; 631 int cop_type; 632 int ivc2 = 0; 633 static CGEN_ATTR_VALUE_BITSET_TYPE *ivc2_core_isa = NULL; 634 635 if (ivc2_core_isa == NULL) 636 { 637 /* IVC2 has some core-only coprocessor instructions. We 638 use COP32 to flag those, and COP64 for the VLIW ones, 639 since they have the same names. */ 640 ivc2_core_isa = cgen_bitset_create (MAX_ISAS); 641 } 642 643 /* Extract and adapt to configuration number, if available. */ 644 if (info->section && info->section->owner) 645 { 646 bfd *abfd = info->section->owner; 647 if (bfd_get_flavour (abfd) == bfd_target_elf_flavour) 648 { 649 mep_config_index = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_INDEX_MASK; 650 /* This instantly redefines MEP_CONFIG, MEP_OMASK, .... MEP_VLIW64 */ 651 652 /* mep_config_map is a variable sized array, so we do not know how big it is. 653 The only safe way to check the index therefore is to iterate over the array. 654 We do know that the last entry is all null. */ 655 int i; 656 for (i = 0; i <= mep_config_index; i++) 657 if (mep_config_map[i].name == NULL) 658 break; 659 660 if (i < mep_config_index) 661 { 662 opcodes_error_handler (_("illegal MEP INDEX setting '%x' in ELF header e_flags field"), mep_config_index); 663 mep_config_index = 0; 664 } 665 666 cop_type = abfd->tdata.elf_obj_data->elf_header->e_flags & EF_MEP_COP_MASK; 667 if (cop_type == EF_MEP_COP_IVC2) 668 ivc2 = 1; 669 } 670 } 671 672 /* Picking the right ISA bitmask for the current context is tricky. */ 673 if (info->section) 674 { 675 if (info->section->flags & SEC_MEP_VLIW) 676 { 677 #ifdef MEP_IVC2_SUPPORTED 678 if (ivc2) 679 { 680 /* ivc2 has its own way of selecting its functions. */ 681 cd->isas = & MEP_CORE_ISA; 682 status = mep_examine_ivc2_insns (cd, pc, info); 683 } 684 else 685 #endif 686 /* Are we in 32 or 64 bit vliw mode? */ 687 if (MEP_VLIW64) 688 status = mep_examine_vliw64_insns (cd, pc, info); 689 else 690 status = mep_examine_vliw32_insns (cd, pc, info); 691 /* Both the above branches set their own isa bitmasks. */ 692 } 693 else 694 { 695 if (ivc2) 696 { 697 cgen_bitset_clear (ivc2_core_isa); 698 cgen_bitset_union (ivc2_core_isa, &MEP_CORE_ISA, ivc2_core_isa); 699 cgen_bitset_union (ivc2_core_isa, &MEP_COP32_ISA, ivc2_core_isa); 700 cd->isas = ivc2_core_isa; 701 } 702 else 703 cd->isas = & MEP_CORE_ISA; 704 status = default_print_insn (cd, pc, info); 705 } 706 } 707 else /* sid or gdb */ 708 { 709 #ifdef MEP_IVC2_SUPPORTED 710 if (mep_ivc2_disassemble_p) 711 { 712 if (mep_ivc2_vliw_disassemble_p) 713 { 714 cd->isas = & MEP_CORE_ISA; 715 status = mep_examine_ivc2_insns (cd, pc, info); 716 return status; 717 } 718 else 719 { 720 if (ivc2) 721 cd->isas = ivc2_core_isa; 722 } 723 } 724 #endif 725 726 status = default_print_insn (cd, pc, info); 727 } 728 729 return status; 730 } 731 732 733 /* -- opc.c */ 734 735 void mep_cgen_print_operand 736 (CGEN_CPU_DESC, int, void *, CGEN_FIELDS *, void const *, bfd_vma, int); 737 738 /* Main entry point for printing operands. 739 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 740 of dis-asm.h on cgen.h. 741 742 This function is basically just a big switch statement. Earlier versions 743 used tables to look up the function to use, but 744 - if the table contains both assembler and disassembler functions then 745 the disassembler contains much of the assembler and vice-versa, 746 - there's a lot of inlining possibilities as things grow, 747 - using a switch statement avoids the function call overhead. 748 749 This function could be moved into `print_insn_normal', but keeping it 750 separate makes clear the interface between `print_insn_normal' and each of 751 the handlers. */ 752 753 void 754 mep_cgen_print_operand (CGEN_CPU_DESC cd, 755 int opindex, 756 void * xinfo, 757 CGEN_FIELDS *fields, 758 void const *attrs ATTRIBUTE_UNUSED, 759 bfd_vma pc, 760 int length) 761 { 762 disassemble_info *info = (disassemble_info *) xinfo; 763 764 switch (opindex) 765 { 766 case MEP_OPERAND_ADDR24A4 : 767 print_normal (cd, info, fields->f_24u8a4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 768 break; 769 case MEP_OPERAND_C5RMUIMM20 : 770 print_normal (cd, info, fields->f_c5_rmuimm20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 771 break; 772 case MEP_OPERAND_C5RNMUIMM24 : 773 print_normal (cd, info, fields->f_c5_rnmuimm24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 774 break; 775 case MEP_OPERAND_CALLNUM : 776 print_normal (cd, info, fields->f_callnum, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 777 break; 778 case MEP_OPERAND_CCCC : 779 print_normal (cd, info, fields->f_rm, 0, pc, length); 780 break; 781 case MEP_OPERAND_CCRN : 782 print_keyword (cd, info, & mep_cgen_opval_h_ccr, fields->f_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL)); 783 break; 784 case MEP_OPERAND_CDISP10 : 785 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 786 break; 787 case MEP_OPERAND_CDISP10A2 : 788 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 789 break; 790 case MEP_OPERAND_CDISP10A4 : 791 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 792 break; 793 case MEP_OPERAND_CDISP10A8 : 794 print_normal (cd, info, fields->f_cdisp10, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 795 break; 796 case MEP_OPERAND_CDISP12 : 797 print_normal (cd, info, fields->f_12s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 798 break; 799 case MEP_OPERAND_CIMM4 : 800 print_normal (cd, info, fields->f_rn, 0, pc, length); 801 break; 802 case MEP_OPERAND_CIMM5 : 803 print_normal (cd, info, fields->f_5u24, 0, pc, length); 804 break; 805 case MEP_OPERAND_CODE16 : 806 print_normal (cd, info, fields->f_16u16, 0, pc, length); 807 break; 808 case MEP_OPERAND_CODE24 : 809 print_normal (cd, info, fields->f_24u4n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 810 break; 811 case MEP_OPERAND_CP_FLAG : 812 print_keyword (cd, info, & mep_cgen_opval_h_ccr, 0, 0); 813 break; 814 case MEP_OPERAND_CRN : 815 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crn, 0); 816 break; 817 case MEP_OPERAND_CRN64 : 818 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crn, 0); 819 break; 820 case MEP_OPERAND_CRNX : 821 print_keyword (cd, info, & mep_cgen_opval_h_cr, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL)); 822 break; 823 case MEP_OPERAND_CRNX64 : 824 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL)); 825 break; 826 case MEP_OPERAND_CROC : 827 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u7, 0); 828 break; 829 case MEP_OPERAND_CROP : 830 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u23, 0); 831 break; 832 case MEP_OPERAND_CRPC : 833 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u26, 0); 834 break; 835 case MEP_OPERAND_CRPP : 836 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u18, 0); 837 break; 838 case MEP_OPERAND_CRQC : 839 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u21, 0); 840 break; 841 case MEP_OPERAND_CRQP : 842 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_5u13, 0); 843 break; 844 case MEP_OPERAND_CSRN : 845 print_keyword (cd, info, & mep_cgen_opval_h_csr, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL)); 846 break; 847 case MEP_OPERAND_CSRN_IDX : 848 print_normal (cd, info, fields->f_csrn, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 849 break; 850 case MEP_OPERAND_DBG : 851 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 852 break; 853 case MEP_OPERAND_DEPC : 854 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 855 break; 856 case MEP_OPERAND_EPC : 857 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 858 break; 859 case MEP_OPERAND_EXC : 860 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 861 break; 862 case MEP_OPERAND_HI : 863 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 864 break; 865 case MEP_OPERAND_IMM16P0 : 866 print_normal (cd, info, fields->f_ivc2_imm16p0, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 867 break; 868 case MEP_OPERAND_IMM3P12 : 869 print_normal (cd, info, fields->f_ivc2_3u12, 0, pc, length); 870 break; 871 case MEP_OPERAND_IMM3P25 : 872 print_normal (cd, info, fields->f_ivc2_3u25, 0, pc, length); 873 break; 874 case MEP_OPERAND_IMM3P4 : 875 print_normal (cd, info, fields->f_ivc2_3u4, 0, pc, length); 876 break; 877 case MEP_OPERAND_IMM3P5 : 878 print_normal (cd, info, fields->f_ivc2_3u5, 0, pc, length); 879 break; 880 case MEP_OPERAND_IMM3P9 : 881 print_normal (cd, info, fields->f_ivc2_3u9, 0, pc, length); 882 break; 883 case MEP_OPERAND_IMM4P10 : 884 print_normal (cd, info, fields->f_ivc2_4u10, 0, pc, length); 885 break; 886 case MEP_OPERAND_IMM4P4 : 887 print_normal (cd, info, fields->f_ivc2_4u4, 0, pc, length); 888 break; 889 case MEP_OPERAND_IMM4P8 : 890 print_normal (cd, info, fields->f_ivc2_4u8, 0, pc, length); 891 break; 892 case MEP_OPERAND_IMM5P23 : 893 print_normal (cd, info, fields->f_ivc2_5u23, 0, pc, length); 894 break; 895 case MEP_OPERAND_IMM5P3 : 896 print_normal (cd, info, fields->f_ivc2_5u3, 0, pc, length); 897 break; 898 case MEP_OPERAND_IMM5P7 : 899 print_normal (cd, info, fields->f_ivc2_5u7, 0, pc, length); 900 break; 901 case MEP_OPERAND_IMM5P8 : 902 print_normal (cd, info, fields->f_ivc2_5u8, 0, pc, length); 903 break; 904 case MEP_OPERAND_IMM6P2 : 905 print_normal (cd, info, fields->f_ivc2_6u2, 0, pc, length); 906 break; 907 case MEP_OPERAND_IMM6P6 : 908 print_normal (cd, info, fields->f_ivc2_6u6, 0, pc, length); 909 break; 910 case MEP_OPERAND_IMM8P0 : 911 print_normal (cd, info, fields->f_ivc2_8u0, 0, pc, length); 912 break; 913 case MEP_OPERAND_IMM8P20 : 914 print_normal (cd, info, fields->f_ivc2_8u20, 0, pc, length); 915 break; 916 case MEP_OPERAND_IMM8P4 : 917 print_normal (cd, info, fields->f_ivc2_8u4, 0, pc, length); 918 break; 919 case MEP_OPERAND_IVC_X_0_2 : 920 print_normal (cd, info, fields->f_ivc2_2u0, 0, pc, length); 921 break; 922 case MEP_OPERAND_IVC_X_0_3 : 923 print_normal (cd, info, fields->f_ivc2_3u0, 0, pc, length); 924 break; 925 case MEP_OPERAND_IVC_X_0_4 : 926 print_normal (cd, info, fields->f_ivc2_4u0, 0, pc, length); 927 break; 928 case MEP_OPERAND_IVC_X_0_5 : 929 print_normal (cd, info, fields->f_ivc2_5u0, 0, pc, length); 930 break; 931 case MEP_OPERAND_IVC_X_6_1 : 932 print_normal (cd, info, fields->f_ivc2_1u6, 0, pc, length); 933 break; 934 case MEP_OPERAND_IVC_X_6_2 : 935 print_normal (cd, info, fields->f_ivc2_2u6, 0, pc, length); 936 break; 937 case MEP_OPERAND_IVC_X_6_3 : 938 print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length); 939 break; 940 case MEP_OPERAND_IVC2_ACC0_0 : 941 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 942 break; 943 case MEP_OPERAND_IVC2_ACC0_1 : 944 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 945 break; 946 case MEP_OPERAND_IVC2_ACC0_2 : 947 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 948 break; 949 case MEP_OPERAND_IVC2_ACC0_3 : 950 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 951 break; 952 case MEP_OPERAND_IVC2_ACC0_4 : 953 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 954 break; 955 case MEP_OPERAND_IVC2_ACC0_5 : 956 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 957 break; 958 case MEP_OPERAND_IVC2_ACC0_6 : 959 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 960 break; 961 case MEP_OPERAND_IVC2_ACC0_7 : 962 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 963 break; 964 case MEP_OPERAND_IVC2_ACC1_0 : 965 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 966 break; 967 case MEP_OPERAND_IVC2_ACC1_1 : 968 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 969 break; 970 case MEP_OPERAND_IVC2_ACC1_2 : 971 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 972 break; 973 case MEP_OPERAND_IVC2_ACC1_3 : 974 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 975 break; 976 case MEP_OPERAND_IVC2_ACC1_4 : 977 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 978 break; 979 case MEP_OPERAND_IVC2_ACC1_5 : 980 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 981 break; 982 case MEP_OPERAND_IVC2_ACC1_6 : 983 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 984 break; 985 case MEP_OPERAND_IVC2_ACC1_7 : 986 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 987 break; 988 case MEP_OPERAND_IVC2_CC : 989 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 990 break; 991 case MEP_OPERAND_IVC2_COFA0 : 992 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 993 break; 994 case MEP_OPERAND_IVC2_COFA1 : 995 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 996 break; 997 case MEP_OPERAND_IVC2_COFR0 : 998 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 999 break; 1000 case MEP_OPERAND_IVC2_COFR1 : 1001 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 1002 break; 1003 case MEP_OPERAND_IVC2_CSAR0 : 1004 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 1005 break; 1006 case MEP_OPERAND_IVC2_CSAR1 : 1007 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0); 1008 break; 1009 case MEP_OPERAND_IVC2C3CCRN : 1010 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL)); 1011 break; 1012 case MEP_OPERAND_IVC2CCRN : 1013 print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn, 0|(1<<CGEN_OPERAND_VIRTUAL)); 1014 break; 1015 case MEP_OPERAND_IVC2CRN : 1016 print_keyword (cd, info, & mep_cgen_opval_h_cr64, fields->f_ivc2_crnx, 0|(1<<CGEN_OPERAND_VIRTUAL)); 1017 break; 1018 case MEP_OPERAND_IVC2RM : 1019 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_ivc2_crm, 0); 1020 break; 1021 case MEP_OPERAND_LO : 1022 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1023 break; 1024 case MEP_OPERAND_LP : 1025 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1026 break; 1027 case MEP_OPERAND_MB0 : 1028 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1029 break; 1030 case MEP_OPERAND_MB1 : 1031 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1032 break; 1033 case MEP_OPERAND_ME0 : 1034 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1035 break; 1036 case MEP_OPERAND_ME1 : 1037 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1038 break; 1039 case MEP_OPERAND_NPC : 1040 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1041 break; 1042 case MEP_OPERAND_OPT : 1043 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1044 break; 1045 case MEP_OPERAND_PCABS24A2 : 1046 print_address (cd, info, fields->f_24u5a2n, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 1047 break; 1048 case MEP_OPERAND_PCREL12A2 : 1049 print_address (cd, info, fields->f_12s4a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 1050 break; 1051 case MEP_OPERAND_PCREL17A2 : 1052 print_address (cd, info, fields->f_17s16a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 1053 break; 1054 case MEP_OPERAND_PCREL24A2 : 1055 print_address (cd, info, fields->f_24s5a2n, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 1056 break; 1057 case MEP_OPERAND_PCREL8A2 : 1058 print_address (cd, info, fields->f_8s8a2, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 1059 break; 1060 case MEP_OPERAND_PSW : 1061 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1062 break; 1063 case MEP_OPERAND_R0 : 1064 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1065 break; 1066 case MEP_OPERAND_R1 : 1067 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1068 break; 1069 case MEP_OPERAND_RL : 1070 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl, 0); 1071 break; 1072 case MEP_OPERAND_RL5 : 1073 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rl5, 0); 1074 break; 1075 case MEP_OPERAND_RM : 1076 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); 1077 break; 1078 case MEP_OPERAND_RMA : 1079 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rm, 0); 1080 break; 1081 case MEP_OPERAND_RN : 1082 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1083 break; 1084 case MEP_OPERAND_RN3 : 1085 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1086 break; 1087 case MEP_OPERAND_RN3C : 1088 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1089 break; 1090 case MEP_OPERAND_RN3L : 1091 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1092 break; 1093 case MEP_OPERAND_RN3S : 1094 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1095 break; 1096 case MEP_OPERAND_RN3UC : 1097 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1098 break; 1099 case MEP_OPERAND_RN3UL : 1100 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1101 break; 1102 case MEP_OPERAND_RN3US : 1103 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn3, 0); 1104 break; 1105 case MEP_OPERAND_RNC : 1106 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1107 break; 1108 case MEP_OPERAND_RNL : 1109 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1110 break; 1111 case MEP_OPERAND_RNS : 1112 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1113 break; 1114 case MEP_OPERAND_RNUC : 1115 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1116 break; 1117 case MEP_OPERAND_RNUL : 1118 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1119 break; 1120 case MEP_OPERAND_RNUS : 1121 print_keyword (cd, info, & mep_cgen_opval_h_gpr, fields->f_rn, 0); 1122 break; 1123 case MEP_OPERAND_SAR : 1124 print_keyword (cd, info, & mep_cgen_opval_h_csr, 0, 0); 1125 break; 1126 case MEP_OPERAND_SDISP16 : 1127 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1128 break; 1129 case MEP_OPERAND_SIMM16 : 1130 print_normal (cd, info, fields->f_16s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1131 break; 1132 case MEP_OPERAND_SIMM16P0 : 1133 print_normal (cd, info, fields->f_ivc2_simm16p0, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 1134 break; 1135 case MEP_OPERAND_SIMM6 : 1136 print_normal (cd, info, fields->f_6s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1137 break; 1138 case MEP_OPERAND_SIMM8 : 1139 print_normal (cd, info, fields->f_8s8, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_RELOC_IMPLIES_OVERFLOW), pc, length); 1140 break; 1141 case MEP_OPERAND_SIMM8P0 : 1142 print_normal (cd, info, fields->f_ivc2_8s0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1143 break; 1144 case MEP_OPERAND_SIMM8P20 : 1145 print_normal (cd, info, fields->f_ivc2_8s20, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1146 break; 1147 case MEP_OPERAND_SIMM8P4 : 1148 print_normal (cd, info, fields->f_ivc2_8s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1149 break; 1150 case MEP_OPERAND_SP : 1151 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1152 break; 1153 case MEP_OPERAND_SPR : 1154 print_spreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1155 break; 1156 case MEP_OPERAND_TP : 1157 print_keyword (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1158 break; 1159 case MEP_OPERAND_TPR : 1160 print_tpreg (cd, info, & mep_cgen_opval_h_gpr, 0, 0); 1161 break; 1162 case MEP_OPERAND_UDISP2 : 1163 print_normal (cd, info, fields->f_2u6, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1164 break; 1165 case MEP_OPERAND_UDISP7 : 1166 print_normal (cd, info, fields->f_7u9, 0, pc, length); 1167 break; 1168 case MEP_OPERAND_UDISP7A2 : 1169 print_normal (cd, info, fields->f_7u9a2, 0, pc, length); 1170 break; 1171 case MEP_OPERAND_UDISP7A4 : 1172 print_normal (cd, info, fields->f_7u9a4, 0, pc, length); 1173 break; 1174 case MEP_OPERAND_UIMM16 : 1175 print_normal (cd, info, fields->f_16u16, 0, pc, length); 1176 break; 1177 case MEP_OPERAND_UIMM2 : 1178 print_normal (cd, info, fields->f_2u10, 0, pc, length); 1179 break; 1180 case MEP_OPERAND_UIMM24 : 1181 print_normal (cd, info, fields->f_24u8n, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 1182 break; 1183 case MEP_OPERAND_UIMM3 : 1184 print_normal (cd, info, fields->f_3u5, 0, pc, length); 1185 break; 1186 case MEP_OPERAND_UIMM4 : 1187 print_normal (cd, info, fields->f_4u8, 0, pc, length); 1188 break; 1189 case MEP_OPERAND_UIMM5 : 1190 print_normal (cd, info, fields->f_5u8, 0, pc, length); 1191 break; 1192 case MEP_OPERAND_UIMM7A4 : 1193 print_normal (cd, info, fields->f_7u9a4, 0, pc, length); 1194 break; 1195 case MEP_OPERAND_ZERO : 1196 print_normal (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 1197 break; 1198 1199 default : 1200 /* xgettext:c-format */ 1201 opcodes_error_handler 1202 (_("internal error: unrecognized field %d while printing insn"), 1203 opindex); 1204 abort (); 1205 } 1206 } 1207 1208 cgen_print_fn * const mep_cgen_print_handlers[] = 1209 { 1210 print_insn_normal, 1211 }; 1212 1213 1214 void 1215 mep_cgen_init_dis (CGEN_CPU_DESC cd) 1216 { 1217 mep_cgen_init_opcode_table (cd); 1218 mep_cgen_init_ibld_table (cd); 1219 cd->print_handlers = & mep_cgen_print_handlers[0]; 1220 cd->print_operand = mep_cgen_print_operand; 1221 } 1222 1223 1224 /* Default print handler. */ 1225 1226 static void 1227 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1228 void *dis_info, 1229 long value, 1230 unsigned int attrs, 1231 bfd_vma pc ATTRIBUTE_UNUSED, 1232 int length ATTRIBUTE_UNUSED) 1233 { 1234 disassemble_info *info = (disassemble_info *) dis_info; 1235 1236 /* Print the operand as directed by the attributes. */ 1237 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 1238 ; /* nothing to do */ 1239 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 1240 (*info->fprintf_func) (info->stream, "%ld", value); 1241 else 1242 (*info->fprintf_func) (info->stream, "0x%lx", value); 1243 } 1244 1245 /* Default address handler. */ 1246 1247 static void 1248 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1249 void *dis_info, 1250 bfd_vma value, 1251 unsigned int attrs, 1252 bfd_vma pc ATTRIBUTE_UNUSED, 1253 int length ATTRIBUTE_UNUSED) 1254 { 1255 disassemble_info *info = (disassemble_info *) dis_info; 1256 1257 /* Print the operand as directed by the attributes. */ 1258 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 1259 ; /* Nothing to do. */ 1260 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 1261 (*info->print_address_func) (value, info); 1262 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 1263 (*info->print_address_func) (value, info); 1264 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 1265 (*info->fprintf_func) (info->stream, "%ld", (long) value); 1266 else 1267 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 1268 } 1269 1270 /* Keyword print handler. */ 1271 1272 static void 1273 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1274 void *dis_info, 1275 CGEN_KEYWORD *keyword_table, 1276 long value, 1277 unsigned int attrs ATTRIBUTE_UNUSED) 1278 { 1279 disassemble_info *info = (disassemble_info *) dis_info; 1280 const CGEN_KEYWORD_ENTRY *ke; 1281 1282 ke = cgen_keyword_lookup_value (keyword_table, value); 1283 if (ke != NULL) 1284 (*info->fprintf_func) (info->stream, "%s", ke->name); 1285 else 1286 (*info->fprintf_func) (info->stream, "???"); 1287 } 1288 1289 /* Default insn printer. 1290 1291 DIS_INFO is defined as `void *' so the disassembler needn't know anything 1292 about disassemble_info. */ 1293 1294 static void 1295 print_insn_normal (CGEN_CPU_DESC cd, 1296 void *dis_info, 1297 const CGEN_INSN *insn, 1298 CGEN_FIELDS *fields, 1299 bfd_vma pc, 1300 int length) 1301 { 1302 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 1303 disassemble_info *info = (disassemble_info *) dis_info; 1304 const CGEN_SYNTAX_CHAR_TYPE *syn; 1305 1306 CGEN_INIT_PRINT (cd); 1307 1308 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 1309 { 1310 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 1311 { 1312 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 1313 continue; 1314 } 1315 if (CGEN_SYNTAX_CHAR_P (*syn)) 1316 { 1317 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 1318 continue; 1319 } 1320 1321 /* We have an operand. */ 1322 mep_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 1323 fields, CGEN_INSN_ATTRS (insn), pc, length); 1324 } 1325 } 1326 1327 /* Subroutine of print_insn. Reads an insn into the given buffers and updates 1328 the extract info. 1329 Returns 0 if all is well, non-zero otherwise. */ 1330 1331 static int 1332 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1333 bfd_vma pc, 1334 disassemble_info *info, 1335 bfd_byte *buf, 1336 int buflen, 1337 CGEN_EXTRACT_INFO *ex_info, 1338 unsigned long *insn_value) 1339 { 1340 int status = (*info->read_memory_func) (pc, buf, buflen, info); 1341 1342 if (status != 0) 1343 { 1344 (*info->memory_error_func) (status, pc, info); 1345 return -1; 1346 } 1347 1348 ex_info->dis_info = info; 1349 ex_info->valid = (1 << buflen) - 1; 1350 ex_info->insn_bytes = buf; 1351 1352 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 1353 return 0; 1354 } 1355 1356 /* Utility to print an insn. 1357 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 1358 The result is the size of the insn in bytes or zero for an unknown insn 1359 or -1 if an error occurs fetching data (memory_error_func will have 1360 been called). */ 1361 1362 static int 1363 print_insn (CGEN_CPU_DESC cd, 1364 bfd_vma pc, 1365 disassemble_info *info, 1366 bfd_byte *buf, 1367 unsigned int buflen) 1368 { 1369 CGEN_INSN_INT insn_value; 1370 const CGEN_INSN_LIST *insn_list; 1371 CGEN_EXTRACT_INFO ex_info; 1372 int basesize; 1373 1374 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 1375 basesize = cd->base_insn_bitsize < buflen * 8 ? 1376 cd->base_insn_bitsize : buflen * 8; 1377 insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); 1378 1379 1380 /* Fill in ex_info fields like read_insn would. Don't actually call 1381 read_insn, since the incoming buffer is already read (and possibly 1382 modified a la m32r). */ 1383 ex_info.valid = (1 << buflen) - 1; 1384 ex_info.dis_info = info; 1385 ex_info.insn_bytes = buf; 1386 1387 /* The instructions are stored in hash lists. 1388 Pick the first one and keep trying until we find the right one. */ 1389 1390 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 1391 while (insn_list != NULL) 1392 { 1393 const CGEN_INSN *insn = insn_list->insn; 1394 CGEN_FIELDS fields; 1395 int length; 1396 unsigned long insn_value_cropped; 1397 1398 #ifdef CGEN_VALIDATE_INSN_SUPPORTED 1399 /* Not needed as insn shouldn't be in hash lists if not supported. */ 1400 /* Supported by this cpu? */ 1401 if (! mep_cgen_insn_supported (cd, insn)) 1402 { 1403 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 1404 continue; 1405 } 1406 #endif 1407 1408 /* Basic bit mask must be correct. */ 1409 /* ??? May wish to allow target to defer this check until the extract 1410 handler. */ 1411 1412 /* Base size may exceed this instruction's size. Extract the 1413 relevant part from the buffer. */ 1414 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 1415 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 1416 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 1417 info->endian == BFD_ENDIAN_BIG); 1418 else 1419 insn_value_cropped = insn_value; 1420 1421 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 1422 == CGEN_INSN_BASE_VALUE (insn)) 1423 { 1424 /* Printing is handled in two passes. The first pass parses the 1425 machine insn and extracts the fields. The second pass prints 1426 them. */ 1427 1428 /* Make sure the entire insn is loaded into insn_value, if it 1429 can fit. */ 1430 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 1431 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 1432 { 1433 unsigned long full_insn_value; 1434 int rc = read_insn (cd, pc, info, buf, 1435 CGEN_INSN_BITSIZE (insn) / 8, 1436 & ex_info, & full_insn_value); 1437 if (rc != 0) 1438 return rc; 1439 length = CGEN_EXTRACT_FN (cd, insn) 1440 (cd, insn, &ex_info, full_insn_value, &fields, pc); 1441 } 1442 else 1443 length = CGEN_EXTRACT_FN (cd, insn) 1444 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 1445 1446 /* Length < 0 -> error. */ 1447 if (length < 0) 1448 return length; 1449 if (length > 0) 1450 { 1451 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 1452 /* Length is in bits, result is in bytes. */ 1453 return length / 8; 1454 } 1455 } 1456 1457 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 1458 } 1459 1460 return 0; 1461 } 1462 1463 /* Default value for CGEN_PRINT_INSN. 1464 The result is the size of the insn in bytes or zero for an unknown insn 1465 or -1 if an error occured fetching bytes. */ 1466 1467 #ifndef CGEN_PRINT_INSN 1468 #define CGEN_PRINT_INSN default_print_insn 1469 #endif 1470 1471 static int 1472 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 1473 { 1474 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 1475 int buflen; 1476 int status; 1477 1478 /* Attempt to read the base part of the insn. */ 1479 buflen = cd->base_insn_bitsize / 8; 1480 status = (*info->read_memory_func) (pc, buf, buflen, info); 1481 1482 /* Try again with the minimum part, if min < base. */ 1483 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 1484 { 1485 buflen = cd->min_insn_bitsize / 8; 1486 status = (*info->read_memory_func) (pc, buf, buflen, info); 1487 } 1488 1489 if (status != 0) 1490 { 1491 (*info->memory_error_func) (status, pc, info); 1492 return -1; 1493 } 1494 1495 return print_insn (cd, pc, info, buf, buflen); 1496 } 1497 1498 /* Main entry point. 1499 Print one instruction from PC on INFO->STREAM. 1500 Return the size of the instruction (in bytes). */ 1501 1502 typedef struct cpu_desc_list 1503 { 1504 struct cpu_desc_list *next; 1505 CGEN_BITSET *isa; 1506 int mach; 1507 int endian; 1508 int insn_endian; 1509 CGEN_CPU_DESC cd; 1510 } cpu_desc_list; 1511 1512 int 1513 print_insn_mep (bfd_vma pc, disassemble_info *info) 1514 { 1515 static cpu_desc_list *cd_list = 0; 1516 cpu_desc_list *cl = 0; 1517 static CGEN_CPU_DESC cd = 0; 1518 static CGEN_BITSET *prev_isa; 1519 static int prev_mach; 1520 static int prev_endian; 1521 static int prev_insn_endian; 1522 int length; 1523 CGEN_BITSET *isa; 1524 int mach; 1525 int endian = (info->endian == BFD_ENDIAN_BIG 1526 ? CGEN_ENDIAN_BIG 1527 : CGEN_ENDIAN_LITTLE); 1528 int insn_endian = (info->endian_code == BFD_ENDIAN_BIG 1529 ? CGEN_ENDIAN_BIG 1530 : CGEN_ENDIAN_LITTLE); 1531 enum bfd_architecture arch; 1532 1533 /* ??? gdb will set mach but leave the architecture as "unknown" */ 1534 #ifndef CGEN_BFD_ARCH 1535 #define CGEN_BFD_ARCH bfd_arch_mep 1536 #endif 1537 arch = info->arch; 1538 if (arch == bfd_arch_unknown) 1539 arch = CGEN_BFD_ARCH; 1540 1541 /* There's no standard way to compute the machine or isa number 1542 so we leave it to the target. */ 1543 #ifdef CGEN_COMPUTE_MACH 1544 mach = CGEN_COMPUTE_MACH (info); 1545 #else 1546 mach = info->mach; 1547 #endif 1548 1549 #ifdef CGEN_COMPUTE_ISA 1550 { 1551 static CGEN_BITSET *permanent_isa; 1552 1553 if (!permanent_isa) 1554 permanent_isa = cgen_bitset_create (MAX_ISAS); 1555 isa = permanent_isa; 1556 cgen_bitset_clear (isa); 1557 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 1558 } 1559 #else 1560 isa = info->private_data; 1561 #endif 1562 1563 /* If we've switched cpu's, try to find a handle we've used before */ 1564 if (cd 1565 && (cgen_bitset_compare (isa, prev_isa) != 0 1566 || mach != prev_mach 1567 || endian != prev_endian)) 1568 { 1569 cd = 0; 1570 for (cl = cd_list; cl; cl = cl->next) 1571 { 1572 if (cgen_bitset_compare (cl->isa, isa) == 0 && 1573 cl->mach == mach && 1574 cl->endian == endian) 1575 { 1576 cd = cl->cd; 1577 prev_isa = cd->isas; 1578 break; 1579 } 1580 } 1581 } 1582 1583 /* If we haven't initialized yet, initialize the opcode table. */ 1584 if (! cd) 1585 { 1586 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 1587 const char *mach_name; 1588 1589 if (!arch_type) 1590 abort (); 1591 mach_name = arch_type->printable_name; 1592 1593 prev_isa = cgen_bitset_copy (isa); 1594 prev_mach = mach; 1595 prev_endian = endian; 1596 prev_insn_endian = insn_endian; 1597 cd = mep_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 1598 CGEN_CPU_OPEN_BFDMACH, mach_name, 1599 CGEN_CPU_OPEN_ENDIAN, prev_endian, 1600 CGEN_CPU_OPEN_INSN_ENDIAN, prev_insn_endian, 1601 CGEN_CPU_OPEN_END); 1602 if (!cd) 1603 abort (); 1604 1605 /* Save this away for future reference. */ 1606 cl = xmalloc (sizeof (struct cpu_desc_list)); 1607 cl->cd = cd; 1608 cl->isa = prev_isa; 1609 cl->mach = mach; 1610 cl->endian = endian; 1611 cl->next = cd_list; 1612 cd_list = cl; 1613 1614 mep_cgen_init_dis (cd); 1615 } 1616 1617 /* We try to have as much common code as possible. 1618 But at this point some targets need to take over. */ 1619 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 1620 but if not possible try to move this hook elsewhere rather than 1621 have two hooks. */ 1622 length = CGEN_PRINT_INSN (cd, pc, info); 1623 if (length > 0) 1624 return length; 1625 if (length < 0) 1626 return -1; 1627 1628 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 1629 return cd->default_insn_bitsize / 8; 1630 } 1631