1 /* Declarations for Intel 80386 opcode table 2 Copyright (C) 2007-2024 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "opcode/i386.h" 22 #include <limits.h> 23 #ifndef CHAR_BIT 24 #define CHAR_BIT 8 25 #endif 26 27 /* Position of cpu flags bitfiled. */ 28 29 enum i386_cpu 30 { 31 /* i186 or better required */ 32 Cpu186 = 0, 33 /* i286 or better required */ 34 Cpu286, 35 /* i386 or better required */ 36 Cpu386, 37 /* i486 or better required */ 38 Cpu486, 39 /* i585 or better required */ 40 Cpu586, 41 /* i686 or better required */ 42 Cpu686, 43 /* CMOV Instruction support required */ 44 CpuCMOV, 45 /* FXSR Instruction support required */ 46 CpuFXSR, 47 /* CLFLUSH Instruction support required */ 48 CpuClflush, 49 /* NOP Instruction support required */ 50 CpuNop, 51 /* SYSCALL Instructions support required */ 52 CpuSYSCALL, 53 /* Floating point support required */ 54 Cpu8087, 55 /* i686 and floating point support required */ 56 Cpu687, 57 /* SSE3 and floating point support required */ 58 CpuFISTTP, 59 /* MMX support required */ 60 CpuMMX, 61 /* SSE support required */ 62 CpuSSE, 63 /* SSE2 support required */ 64 CpuSSE2, 65 /* SSE3 support required */ 66 CpuSSE3, 67 /* VIA PadLock required */ 68 CpuPadLock, 69 /* AMD Secure Virtual Machine Ext-s required */ 70 CpuSVME, 71 /* VMX Instructions required */ 72 CpuVMX, 73 /* SMX Instructions required */ 74 CpuSMX, 75 /* SSSE3 support required */ 76 CpuSSSE3, 77 /* SSE4a support required */ 78 CpuSSE4a, 79 /* LZCNT support required */ 80 CpuLZCNT, 81 /* POPCNT support required */ 82 CpuPOPCNT, 83 /* MONITOR support required */ 84 CpuMONITOR, 85 /* SSE4.1 support required */ 86 CpuSSE4_1, 87 /* SSE4.2 support required */ 88 CpuSSE4_2, 89 /* AVX2 support required */ 90 CpuAVX2, 91 /* Intel AVX-512 Conflict Detection Instructions support required */ 92 CpuAVX512CD, 93 /* Intel AVX-512 Exponential and Reciprocal Instructions support 94 required */ 95 CpuAVX512ER, 96 /* Intel AVX-512 Prefetch Instructions support required */ 97 CpuAVX512PF, 98 /* Intel AVX-512 DQ Instructions support required. */ 99 CpuAVX512DQ, 100 /* Intel AVX-512 BW Instructions support required. */ 101 CpuAVX512BW, 102 /* Intel IAMCU support required */ 103 CpuIAMCU, 104 /* Xsave/xrstor New Instructions support required */ 105 CpuXsave, 106 /* Xsaveopt New Instructions support required */ 107 CpuXsaveopt, 108 /* AES support required */ 109 CpuAES, 110 /* PCLMULQDQ support required */ 111 CpuPCLMULQDQ, 112 /* FMA support required */ 113 CpuFMA, 114 /* FMA4 support required */ 115 CpuFMA4, 116 /* XOP support required */ 117 CpuXOP, 118 /* LWP support required */ 119 CpuLWP, 120 /* BMI support required */ 121 CpuBMI, 122 /* TBM support required */ 123 CpuTBM, 124 /* MOVBE Instruction support required */ 125 CpuMovbe, 126 /* CMPXCHG16B instruction support required. */ 127 CpuCX16, 128 /* LAHF/SAHF instruction support required (in 64-bit mode). */ 129 CpuLAHF_SAHF, 130 /* EPT Instructions required */ 131 CpuEPT, 132 /* RDTSCP Instruction support required */ 133 CpuRdtscp, 134 /* FSGSBASE Instructions required */ 135 CpuFSGSBase, 136 /* RDRND Instructions required */ 137 CpuRdRnd, 138 /* F16C Instructions required */ 139 CpuF16C, 140 /* Intel BMI2 support required */ 141 CpuBMI2, 142 /* RTM support required */ 143 CpuRTM, 144 /* INVPCID Instructions required */ 145 CpuINVPCID, 146 /* VMFUNC Instruction required */ 147 CpuVMFUNC, 148 /* Intel MPX Instructions required */ 149 CpuMPX, 150 /* RDRSEED instruction required. */ 151 CpuRDSEED, 152 /* Multi-presisionn add-carry instructions are required. */ 153 CpuADX, 154 /* Supports prefetchw and prefetch instructions. */ 155 CpuPRFCHW, 156 /* SMAP instructions required. */ 157 CpuSMAP, 158 /* SHA instructions required. */ 159 CpuSHA, 160 /* SHA512 instructions required. */ 161 CpuSHA512, 162 /* SM3 instructions required. */ 163 CpuSM3, 164 /* SM4 instructions required. */ 165 CpuSM4, 166 /* CLFLUSHOPT instruction required */ 167 CpuClflushOpt, 168 /* XSAVES/XRSTORS instruction required */ 169 CpuXSAVES, 170 /* XSAVEC instruction required */ 171 CpuXSAVEC, 172 /* PREFETCHWT1 instruction required */ 173 CpuPREFETCHWT1, 174 /* SE1 instruction required */ 175 CpuSE1, 176 /* CLWB instruction required */ 177 CpuCLWB, 178 /* Intel AVX-512 IFMA Instructions support required. */ 179 CpuAVX512IFMA, 180 /* Intel AVX-512 VBMI Instructions support required. */ 181 CpuAVX512VBMI, 182 /* Intel AVX-512 4FMAPS Instructions support required. */ 183 CpuAVX512_4FMAPS, 184 /* Intel AVX-512 4VNNIW Instructions support required. */ 185 CpuAVX512_4VNNIW, 186 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ 187 CpuAVX512_VPOPCNTDQ, 188 /* Intel AVX-512 VBMI2 Instructions support required. */ 189 CpuAVX512_VBMI2, 190 /* Intel AVX-512 VNNI Instructions support required. */ 191 CpuAVX512_VNNI, 192 /* Intel AVX-512 BITALG Instructions support required. */ 193 CpuAVX512_BITALG, 194 /* Intel AVX-512 BF16 Instructions support required. */ 195 CpuAVX512_BF16, 196 /* Intel AVX-512 VP2INTERSECT Instructions support required. */ 197 CpuAVX512_VP2INTERSECT, 198 /* TDX Instructions support required. */ 199 CpuTDX, 200 /* Intel AVX VNNI Instructions support required. */ 201 CpuAVX_VNNI, 202 /* Intel AVX-512 FP16 Instructions support required. */ 203 CpuAVX512_FP16, 204 /* PREFETCHI instruction required */ 205 CpuPREFETCHI, 206 /* Intel AVX IFMA Instructions support required. */ 207 CpuAVX_IFMA, 208 /* Intel AVX VNNI-INT8 Instructions support required. */ 209 CpuAVX_VNNI_INT8, 210 /* Intel AVX VNNI-INT16 Instructions support required. */ 211 CpuAVX_VNNI_INT16, 212 /* Intel CMPccXADD instructions support required. */ 213 CpuCMPCCXADD, 214 /* Intel WRMSRNS Instructions support required */ 215 CpuWRMSRNS, 216 /* Intel MSRLIST Instructions support required. */ 217 CpuMSRLIST, 218 /* Intel AVX NE CONVERT Instructions support required. */ 219 CpuAVX_NE_CONVERT, 220 /* Intel RAO INT Instructions support required. */ 221 CpuRAO_INT, 222 /* fred instruction required */ 223 CpuFRED, 224 /* lkgs instruction required */ 225 CpuLKGS, 226 /* Intel USER_MSR Instruction support required. */ 227 CpuUSER_MSR, 228 /* mwaitx instruction required */ 229 CpuMWAITX, 230 /* Clzero instruction required */ 231 CpuCLZERO, 232 /* OSPKE instruction required */ 233 CpuOSPKE, 234 /* RDPID instruction required */ 235 CpuRDPID, 236 /* PTWRITE instruction required */ 237 CpuPTWRITE, 238 /* CET instructions support required */ 239 CpuIBT, 240 CpuSHSTK, 241 /* AMX-INT8 instructions required */ 242 CpuAMX_INT8, 243 /* AMX-BF16 instructions required */ 244 CpuAMX_BF16, 245 /* AMX-FP16 instructions required */ 246 CpuAMX_FP16, 247 /* AMX-COMPLEX instructions required. */ 248 CpuAMX_COMPLEX, 249 /* AMX-TILE instructions required */ 250 CpuAMX_TILE, 251 /* GFNI instructions required */ 252 CpuGFNI, 253 /* VAES instructions required */ 254 CpuVAES, 255 /* VPCLMULQDQ instructions required */ 256 CpuVPCLMULQDQ, 257 /* WBNOINVD instructions required */ 258 CpuWBNOINVD, 259 /* PCONFIG instructions required */ 260 CpuPCONFIG, 261 /* PBNDKB instructions required. */ 262 CpuPBNDKB, 263 /* WAITPKG instructions required */ 264 CpuWAITPKG, 265 /* UINTR instructions required */ 266 CpuUINTR, 267 /* CLDEMOTE instruction required */ 268 CpuCLDEMOTE, 269 /* MOVDIRI instruction support required */ 270 CpuMOVDIRI, 271 /* MOVDIRR64B instruction required */ 272 CpuMOVDIR64B, 273 /* ENQCMD instruction required */ 274 CpuENQCMD, 275 /* SERIALIZE instruction required */ 276 CpuSERIALIZE, 277 /* RDPRU instruction required */ 278 CpuRDPRU, 279 /* MCOMMIT instruction required */ 280 CpuMCOMMIT, 281 /* SEV-ES instruction(s) required */ 282 CpuSEV_ES, 283 /* TSXLDTRK instruction required */ 284 CpuTSXLDTRK, 285 /* KL instruction support required */ 286 CpuKL, 287 /* WideKL instruction support required */ 288 CpuWideKL, 289 /* HRESET instruction required */ 290 CpuHRESET, 291 /* INVLPGB instructions required */ 292 CpuINVLPGB, 293 /* TLBSYNC instructions required */ 294 CpuTLBSYNC, 295 /* SNP instructions required */ 296 CpuSNP, 297 /* RMPQUERY instruction required */ 298 CpuRMPQUERY, 299 300 /* NOTE: These items, which can be combined with other ISA flags above, need 301 to remain second to last and in sync with CPU_FLAGS_COMMON. */ 302 303 /* i287 support required */ 304 Cpu287, 305 CpuAttrEnums = Cpu287, 306 /* i387 support required */ 307 Cpu387, 308 /* 3dnow! support required */ 309 Cpu3dnow, 310 /* 3dnow! Extensions support required */ 311 Cpu3dnowA, 312 /* 64bit support required */ 313 Cpu64, 314 /* AVX support required */ 315 CpuAVX, 316 /* HLE support required */ 317 CpuHLE, 318 /* Intel AVX-512 Foundation Instructions support required */ 319 CpuAVX512F, 320 /* Intel AVX-512 VL Instructions support required. */ 321 CpuAVX512VL, 322 /* Intel APX_F Instructions support required. */ 323 CpuAPX_F, 324 /* Not supported in the 64bit mode */ 325 CpuNo64, 326 327 /* NOTE: This item needs to remain last. */ 328 329 /* The last bitfield in i386_cpu_flags. */ 330 CpuMax = CpuNo64 331 }; 332 333 #define CpuNumOfUints \ 334 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 335 #define CpuNumOfBits \ 336 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 337 338 #define CpuIsaBits 8 339 #define CpuAttrNumOfUints \ 340 ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1) 341 #define CpuAttrNumOfBits \ 342 (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT) 343 344 /* If you get a compiler error for zero width of an unused field, 345 comment the respective one out. */ 346 #define CpuUnused (CpuMax + 1) 347 #define CpuAttrUnused (CpuIsaBits + CpuMax + 1 - CpuAttrEnums) 348 349 #define CPU_FLAGS_COMMON \ 350 unsigned int cpu287:1, \ 351 cpu387:1, \ 352 cpu3dnow:1, \ 353 cpu3dnowa:1, \ 354 cpu64:1, \ 355 cpuavx:1, \ 356 cpuhle:1, \ 357 cpuavx512f:1, \ 358 cpuavx512vl:1, \ 359 cpuapx_f:1, \ 360 /* NOTE: This field needs to remain last. */ \ 361 cpuno64:1 362 363 typedef union i386_cpu_attr 364 { 365 struct 366 { 367 unsigned int isa:CpuIsaBits; 368 CPU_FLAGS_COMMON; 369 #ifdef CpuAttrUnused 370 unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused); 371 #endif 372 } bitfield; 373 unsigned int array[CpuAttrNumOfUints]; 374 } i386_cpu_attr; 375 376 /* We can check if an instruction is available with array instead 377 of bitfield. */ 378 typedef union i386_cpu_flags 379 { 380 struct 381 { 382 unsigned int cpui186:1; 383 unsigned int cpui286:1; 384 unsigned int cpui386:1; 385 unsigned int cpui486:1; 386 unsigned int cpui586:1; 387 unsigned int cpui686:1; 388 unsigned int cpucmov:1; 389 unsigned int cpufxsr:1; 390 unsigned int cpuclflush:1; 391 unsigned int cpunop:1; 392 unsigned int cpusyscall:1; 393 unsigned int cpu8087:1; 394 unsigned int cpu687:1; 395 unsigned int cpufisttp:1; 396 unsigned int cpummx:1; 397 unsigned int cpusse:1; 398 unsigned int cpusse2:1; 399 unsigned int cpusse3:1; 400 unsigned int cpupadlock:1; 401 unsigned int cpusvme:1; 402 unsigned int cpuvmx:1; 403 unsigned int cpusmx:1; 404 unsigned int cpussse3:1; 405 unsigned int cpusse4a:1; 406 unsigned int cpulzcnt:1; 407 unsigned int cpupopcnt:1; 408 unsigned int cpumonitor:1; 409 unsigned int cpusse4_1:1; 410 unsigned int cpusse4_2:1; 411 unsigned int cpuavx2:1; 412 unsigned int cpuavx512cd:1; 413 unsigned int cpuavx512er:1; 414 unsigned int cpuavx512pf:1; 415 unsigned int cpuavx512dq:1; 416 unsigned int cpuavx512bw:1; 417 unsigned int cpuiamcu:1; 418 unsigned int cpuxsave:1; 419 unsigned int cpuxsaveopt:1; 420 unsigned int cpuaes:1; 421 unsigned int cpupclmulqdq:1; 422 unsigned int cpufma:1; 423 unsigned int cpufma4:1; 424 unsigned int cpuxop:1; 425 unsigned int cpulwp:1; 426 unsigned int cpubmi:1; 427 unsigned int cputbm:1; 428 unsigned int cpumovbe:1; 429 unsigned int cpucx16:1; 430 unsigned int cpulahf_sahf:1; 431 unsigned int cpuept:1; 432 unsigned int cpurdtscp:1; 433 unsigned int cpufsgsbase:1; 434 unsigned int cpurdrnd:1; 435 unsigned int cpuf16c:1; 436 unsigned int cpubmi2:1; 437 unsigned int cpurtm:1; 438 unsigned int cpuinvpcid:1; 439 unsigned int cpuvmfunc:1; 440 unsigned int cpumpx:1; 441 unsigned int cpurdseed:1; 442 unsigned int cpuadx:1; 443 unsigned int cpuprfchw:1; 444 unsigned int cpusmap:1; 445 unsigned int cpusha:1; 446 unsigned int cpusha512:1; 447 unsigned int cpusm3:1; 448 unsigned int cpusm4:1; 449 unsigned int cpuclflushopt:1; 450 unsigned int cpuxsaves:1; 451 unsigned int cpuxsavec:1; 452 unsigned int cpuprefetchwt1:1; 453 unsigned int cpuse1:1; 454 unsigned int cpuclwb:1; 455 unsigned int cpuavx512ifma:1; 456 unsigned int cpuavx512vbmi:1; 457 unsigned int cpuavx512_4fmaps:1; 458 unsigned int cpuavx512_4vnniw:1; 459 unsigned int cpuavx512_vpopcntdq:1; 460 unsigned int cpuavx512_vbmi2:1; 461 unsigned int cpuavx512_vnni:1; 462 unsigned int cpuavx512_bitalg:1; 463 unsigned int cpuavx512_bf16:1; 464 unsigned int cpuavx512_vp2intersect:1; 465 unsigned int cputdx:1; 466 unsigned int cpuavx_vnni:1; 467 unsigned int cpuavx512_fp16:1; 468 unsigned int cpuprefetchi:1; 469 unsigned int cpuavx_ifma:1; 470 unsigned int cpuavx_vnni_int8:1; 471 unsigned int cpuavx_vnni_int16:1; 472 unsigned int cpucmpccxadd:1; 473 unsigned int cpuwrmsrns:1; 474 unsigned int cpumsrlist:1; 475 unsigned int cpuavx_ne_convert:1; 476 unsigned int cpurao_int:1; 477 unsigned int cpufred:1; 478 unsigned int cpulkgs:1; 479 unsigned int cpuuser_msr:1; 480 unsigned int cpumwaitx:1; 481 unsigned int cpuclzero:1; 482 unsigned int cpuospke:1; 483 unsigned int cpurdpid:1; 484 unsigned int cpuptwrite:1; 485 unsigned int cpuibt:1; 486 unsigned int cpushstk:1; 487 unsigned int cpuamx_int8:1; 488 unsigned int cpuamx_bf16:1; 489 unsigned int cpuamx_fp16:1; 490 unsigned int cpuamx_complex:1; 491 unsigned int cpuamx_tile:1; 492 unsigned int cpugfni:1; 493 unsigned int cpuvaes:1; 494 unsigned int cpuvpclmulqdq:1; 495 unsigned int cpuwbnoinvd:1; 496 unsigned int cpupconfig:1; 497 unsigned int cpupbndkb:1; 498 unsigned int cpuwaitpkg:1; 499 unsigned int cpuuintr:1; 500 unsigned int cpucldemote:1; 501 unsigned int cpumovdiri:1; 502 unsigned int cpumovdir64b:1; 503 unsigned int cpuenqcmd:1; 504 unsigned int cpuserialize:1; 505 unsigned int cpurdpru:1; 506 unsigned int cpumcommit:1; 507 unsigned int cpusev_es:1; 508 unsigned int cputsxldtrk:1; 509 unsigned int cpukl:1; 510 unsigned int cpuwidekl:1; 511 unsigned int cpuhreset:1; 512 unsigned int cpuinvlpgb:1; 513 unsigned int cputlbsync:1; 514 unsigned int cpusnp:1; 515 unsigned int cpurmpquery:1; 516 CPU_FLAGS_COMMON; 517 #ifdef CpuUnused 518 unsigned int unused:(CpuNumOfBits - CpuUnused); 519 #endif 520 } bitfield; 521 unsigned int array[CpuNumOfUints]; 522 } i386_cpu_flags; 523 524 /* Position of opcode_modifier bits. */ 525 526 enum 527 { 528 /* has direction bit. */ 529 D = 0, 530 /* set if operands can be both bytes and words/dwords/qwords, encoded the 531 canonical way; the base_opcode field should hold the encoding for byte 532 operands */ 533 W, 534 /* load form instruction. Must be placed before store form. */ 535 Load, 536 /* insn has a modrm byte. */ 537 Modrm, 538 /* special case for jump insns; value has to be 1 */ 539 #define JUMP 1 540 /* call and jump */ 541 #define JUMP_DWORD 2 542 /* loop and jecxz */ 543 #define JUMP_BYTE 3 544 /* special case for intersegment leaps/calls */ 545 #define JUMP_INTERSEGMENT 4 546 /* absolute address for jump */ 547 #define JUMP_ABSOLUTE 5 548 Jump, 549 /* FP insn memory format bit, sized by 0x4 */ 550 FloatMF, 551 /* needs size prefix if in 32-bit mode */ 552 #define SIZE16 1 553 /* needs size prefix if in 16-bit mode */ 554 #define SIZE32 2 555 /* needs size prefix if in 64-bit mode */ 556 #define SIZE64 3 557 Size, 558 /* Check that operand sizes match. */ 559 CheckOperandSize, 560 /* any memory size */ 561 #define ANY_SIZE 1 562 /* fake an extra reg operand for clr, imul and special register 563 processing for some instructions. */ 564 #define REG_KLUDGE 2 565 /* deprecated fp insn, gets a warning */ 566 #define UGH 3 567 /* An implicit xmm0 as the first operand */ 568 #define IMPLICIT_1ST_XMM0 4 569 /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. 570 It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). 571 */ 572 #define IMPLICIT_QUAD_GROUP 5 573 /* Default mask isn't allowed. */ 574 #define NO_DEFAULT_MASK 6 575 /* Address prefix changes register operand */ 576 #define ADDR_PREFIX_OP_REG 7 577 /* Instrucion requires that destination must be distinct from source 578 registers. */ 579 #define DISTINCT_DEST 8 580 /* Instruction updates stack pointer implicitly. */ 581 #define IMPLICIT_STACK_OP 9 582 OperandConstraint, 583 /* instruction ignores operand size prefix and in Intel mode ignores 584 mnemonic size suffix check. */ 585 #define IGNORESIZE 1 586 /* default insn size depends on mode */ 587 #define DEFAULTSIZE 2 588 MnemonicSize, 589 /* b suffix on instruction illegal */ 590 No_bSuf, 591 /* w suffix on instruction illegal */ 592 No_wSuf, 593 /* l suffix on instruction illegal */ 594 No_lSuf, 595 /* s suffix on instruction illegal */ 596 No_sSuf, 597 /* q suffix on instruction illegal */ 598 No_qSuf, 599 /* instruction needs FWAIT */ 600 FWait, 601 /* IsString provides for a quick test for string instructions, and 602 its actual value also indicates which of the operands (if any) 603 requires use of the %es segment. */ 604 #define IS_STRING_ES_OP0 2 605 #define IS_STRING_ES_OP1 3 606 IsString, 607 /* RegMem is for instructions with a modrm byte where the register 608 destination operand should be encoded in the mod and regmem fields. 609 Normally, it will be encoded in the reg field. We add a RegMem 610 flag to indicate that it should be encoded in the regmem field. */ 611 RegMem, 612 /* quick test if branch instruction is MPX supported */ 613 BNDPrefixOk, 614 #define PrefixNone 0 615 #define PrefixRep 1 616 #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */ 617 #define PrefixNoTrack 3 618 /* Prefixes implying "LOCK okay" must come after Lock. All others have 619 to come before. */ 620 #define PrefixLock 4 621 #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ 622 #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */ 623 PrefixOk, 624 /* opcode is a prefix */ 625 IsPrefix, 626 /* instruction has extension in 8 bit imm */ 627 ImmExt, 628 /* instruction don't need Rex64 prefix. */ 629 NoRex64, 630 /* insn has VEX prefix: 631 1: 128bit VEX prefix (or operand dependent). 632 2: 256bit VEX prefix. 633 3: Scalar VEX prefix. 634 */ 635 #define VEX128 1 636 #define VEX256 2 637 #define VEXScalar 3 638 Vex, 639 /* How to encode VEX.vvvv: 640 1: VEX.vvvv encodes the src1 register operand. 641 2: VEX.vvvv encodes the src2 register operand. 642 3: VEX.vvvv encodes the dest register operand. 643 */ 644 #define VexVVVV_SRC1 1 645 #define VexVVVV_SRC2 2 646 #define VexVVVV_DST 3 647 648 VexVVVV, 649 /* How the VEX.W bit is used: 650 0: Set by the REX.W bit. 651 1: VEX.W0. Should always be 0. 652 2: VEX.W1. Should always be 1. 653 3: VEX.WIG. The VEX.W bit is ignored. 654 */ 655 #define VEXW0 1 656 #define VEXW1 2 657 #define VEXWIG 3 658 VexW, 659 /* Opcode prefix (values chosen to be usable directly in 660 VEX/XOP/EVEX pp fields): 661 0: None 662 1: Add 0x66 opcode prefix. 663 2: Add 0xf3 opcode prefix. 664 3: Add 0xf2 opcode prefix. 665 */ 666 #define PREFIX_NONE 0 667 #define PREFIX_0X66 1 668 #define PREFIX_0XF3 2 669 #define PREFIX_0XF2 3 670 OpcodePrefix, 671 /* Instruction with a mandatory SIB byte: 672 1: 128bit vector register. 673 2: 256bit vector register. 674 3: 512bit vector register. 675 */ 676 #define VECSIB128 1 677 #define VECSIB256 2 678 #define VECSIB512 3 679 #define SIBMEM 4 680 SIB, 681 682 /* SSE to AVX support required */ 683 SSE2AVX, 684 685 /* insn has EVEX prefix: 686 1: 512bit EVEX prefix. 687 2: 128bit EVEX prefix. 688 3: 256bit EVEX prefix. 689 4: Length-ignored (LIG) EVEX prefix. 690 5: Length determined from actual operands. 691 6: L'L = 3 (reserved, .insn only) 692 */ 693 #define EVEX512 1 694 #define EVEX128 2 695 #define EVEX256 3 696 #define EVEXLIG 4 697 #define EVEXDYN 5 698 #define EVEX_L3 6 699 EVex, 700 701 /* AVX512 masking support */ 702 Masking, 703 704 /* AVX512 broadcast support. The number of bytes to broadcast is 705 1 << (Broadcast - 1): 706 1: Byte broadcast. 707 2: Word broadcast. 708 3: Dword broadcast. 709 4: Qword broadcast. 710 */ 711 #define BYTE_BROADCAST 1 712 #define WORD_BROADCAST 2 713 #define DWORD_BROADCAST 3 714 #define QWORD_BROADCAST 4 715 Broadcast, 716 717 /* Static rounding control is supported. */ 718 StaticRounding, 719 720 /* Supress All Exceptions is supported. */ 721 SAE, 722 723 /* Compressed Disp8*N attribute. */ 724 #define DISP8_SHIFT_VL 7 725 Disp8MemShift, 726 727 /* Support encoding optimization. */ 728 Optimize, 729 730 /* Language dialect. NOTE: Order matters! */ 731 #define INTEL_SYNTAX 1 732 #define ATT_SYNTAX 2 733 #define ATT_MNEMONIC 3 734 Dialect, 735 736 /* ISA64: Don't change the order without other code adjustments. 737 0: Common to AMD64 and Intel64. 738 1: AMD64. 739 2: Intel64. 740 3: Only in Intel64. 741 */ 742 #define AMD64 1 743 #define INTEL64 2 744 #define INTEL64ONLY 3 745 ISA64, 746 747 /* egprs (r16-r31) on instruction illegal. We also use it to judge 748 whether the instruction supports pseudo-prefix {rex2}. */ 749 NoEgpr, 750 751 /* No CSPAZO flags update indication. */ 752 NF, 753 754 /* Instrucion requires REX2 prefix. */ 755 Rex2, 756 757 /* Support zero upper */ 758 ZU, 759 760 /* The last bitfield in i386_opcode_modifier. */ 761 Opcode_Modifier_Num 762 }; 763 764 typedef struct i386_opcode_modifier 765 { 766 unsigned int d:1; 767 unsigned int w:1; 768 unsigned int load:1; 769 unsigned int modrm:1; 770 unsigned int jump:3; 771 unsigned int floatmf:1; 772 unsigned int size:2; 773 unsigned int checkoperandsize:1; 774 unsigned int operandconstraint:4; 775 unsigned int mnemonicsize:2; 776 unsigned int no_bsuf:1; 777 unsigned int no_wsuf:1; 778 unsigned int no_lsuf:1; 779 unsigned int no_ssuf:1; 780 unsigned int no_qsuf:1; 781 unsigned int fwait:1; 782 unsigned int isstring:2; 783 unsigned int regmem:1; 784 unsigned int bndprefixok:1; 785 unsigned int prefixok:3; 786 unsigned int isprefix:1; 787 unsigned int immext:1; 788 unsigned int norex64:1; 789 unsigned int vex:2; 790 unsigned int vexvvvv:2; 791 unsigned int vexw:2; 792 unsigned int opcodeprefix:2; 793 unsigned int sib:3; 794 unsigned int sse2avx:1; 795 unsigned int evex:3; 796 unsigned int masking:1; 797 unsigned int broadcast:3; 798 unsigned int staticrounding:1; 799 unsigned int sae:1; 800 unsigned int disp8memshift:3; 801 unsigned int optimize:1; 802 unsigned int dialect:2; 803 unsigned int isa64:2; 804 unsigned int noegpr:1; 805 unsigned int nf:1; 806 unsigned int rex2:1; 807 unsigned int zu:1; 808 } i386_opcode_modifier; 809 810 /* Operand classes. */ 811 812 #define CLASS_WIDTH 4 813 enum operand_class 814 { 815 ClassNone, 816 Reg, /* GPRs and FP regs, distinguished by operand size */ 817 SReg, /* Segment register */ 818 RegCR, /* Control register */ 819 RegDR, /* Debug register */ 820 RegTR, /* Test register */ 821 RegMMX, /* MMX register */ 822 RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ 823 RegMask, /* Vector Mask register */ 824 RegBND, /* Bound register */ 825 }; 826 827 /* Special operand instances. */ 828 829 #define INSTANCE_WIDTH 3 830 enum operand_instance 831 { 832 InstanceNone, 833 Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ 834 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ 835 RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ 836 RegB, /* %bl / %bx / %ebx / %rbx */ 837 }; 838 839 /* Position of operand_type bits. */ 840 841 enum 842 { 843 /* Class and Instance */ 844 ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, 845 /* 1 bit immediate */ 846 Imm1, 847 /* 8 bit immediate */ 848 Imm8, 849 /* 8 bit immediate sign extended */ 850 Imm8S, 851 /* 16 bit immediate */ 852 Imm16, 853 /* 32 bit immediate */ 854 Imm32, 855 /* 32 bit immediate sign extended */ 856 Imm32S, 857 /* 64 bit immediate */ 858 Imm64, 859 /* 8bit/16bit/32bit displacements are used in different ways, 860 depending on the instruction. For jumps, they specify the 861 size of the PC relative displacement, for instructions with 862 memory operand, they specify the size of the offset relative 863 to the base register, and for instructions with memory offset 864 such as `mov 1234,%al' they specify the size of the offset 865 relative to the segment base. */ 866 /* 8 bit displacement */ 867 Disp8, 868 /* 16 bit displacement */ 869 Disp16, 870 /* 32 bit displacement (64-bit: sign-extended) */ 871 Disp32, 872 /* 64 bit displacement */ 873 Disp64, 874 /* Register which can be used for base or index in memory operand. */ 875 BaseIndex, 876 /* BYTE size. */ 877 Byte, 878 /* WORD size. 2 byte */ 879 Word, 880 /* DWORD size. 4 byte */ 881 Dword, 882 /* FWORD size. 6 byte */ 883 Fword, 884 /* QWORD size. 8 byte */ 885 Qword, 886 /* TBYTE size. 10 byte */ 887 Tbyte, 888 /* XMMWORD size. */ 889 Xmmword, 890 /* YMMWORD size. */ 891 Ymmword, 892 /* ZMMWORD size. */ 893 Zmmword, 894 /* TMMWORD size. */ 895 Tmmword, 896 /* Unspecified memory size. */ 897 Unspecified, 898 899 /* The number of bits in i386_operand_type. */ 900 OTNum 901 }; 902 903 #define OTNumOfUints \ 904 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) 905 #define OTNumOfBits \ 906 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 907 908 /* If you get a compiler error for zero width of the unused field, 909 comment it out. */ 910 #define OTUnused OTNum 911 912 typedef union i386_operand_type 913 { 914 struct 915 { 916 unsigned int class:CLASS_WIDTH; 917 unsigned int instance:INSTANCE_WIDTH; 918 unsigned int imm1:1; 919 unsigned int imm8:1; 920 unsigned int imm8s:1; 921 unsigned int imm16:1; 922 unsigned int imm32:1; 923 unsigned int imm32s:1; 924 unsigned int imm64:1; 925 unsigned int disp8:1; 926 unsigned int disp16:1; 927 unsigned int disp32:1; 928 unsigned int disp64:1; 929 unsigned int baseindex:1; 930 unsigned int byte:1; 931 unsigned int word:1; 932 unsigned int dword:1; 933 unsigned int fword:1; 934 unsigned int qword:1; 935 unsigned int tbyte:1; 936 unsigned int xmmword:1; 937 unsigned int ymmword:1; 938 unsigned int zmmword:1; 939 unsigned int tmmword:1; 940 unsigned int unspecified:1; 941 #ifdef OTUnused 942 unsigned int unused:(OTNumOfBits - OTUnused); 943 #endif 944 } bitfield; 945 unsigned int array[OTNumOfUints]; 946 } i386_operand_type; 947 948 typedef struct insn_template 949 { 950 /* instruction name sans width suffix ("mov" for movl insns) */ 951 unsigned int mnem_off; 952 953 /* Bitfield arrangement is such that individual fields can be easily 954 extracted (in native builds at least) - either by at most a masking 955 operation (base_opcode, operands), or by just a (signed) right shift 956 (extension_opcode). Please try to maintain this property. */ 957 958 /* base_opcode is the fundamental opcode byte without optional 959 prefix(es). */ 960 unsigned int base_opcode:16; 961 #define Opcode_D 0x2 /* Direction bit: 962 set if Reg --> Regmem; 963 unset if Regmem --> Reg. */ 964 #define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */ 965 #define Opcode_FloatD 0x4 /* Direction bit for float insns. */ 966 #define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */ 967 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ 968 /* The next value is arbitrary, as long as it's non-zero and distinct 969 from all other values above. */ 970 #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ 971 972 /* how many operands */ 973 unsigned int operands:3; 974 975 /* opcode space */ 976 unsigned int opcode_space:4; 977 /* Opcode encoding space (values chosen to be usable directly in 978 VEX/XOP mmmmm and EVEX mm fields): 979 0: Base opcode space. 980 1: 0F opcode prefix / space. 981 2: 0F38 opcode prefix / space. 982 3: 0F3A opcode prefix / space. 983 4: EVEXMAP4 opcode prefix / space. 984 5: EVEXMAP5 opcode prefix / space. 985 6: EVEXMAP6 opcode prefix / space. 986 7: VEXMAP7 opcode prefix / space. 987 8: XOP 08 opcode space. 988 9: XOP 09 opcode space. 989 A: XOP 0A opcode space. 990 */ 991 #define SPACE_BASE 0 992 #define SPACE_0F 1 993 #define SPACE_0F38 2 994 #define SPACE_0F3A 3 995 #define SPACE_EVEXMAP4 4 996 #define SPACE_EVEXMAP5 5 997 #define SPACE_EVEXMAP6 6 998 #define SPACE_VEXMAP7 7 999 #define SPACE_XOP08 8 1000 #define SPACE_XOP09 9 1001 #define SPACE_XOP0A 0xA 1002 1003 /* (Fake) base opcode value for pseudo prefixes. */ 1004 #define PSEUDO_PREFIX 0 1005 1006 /* extension_opcode is the 3 bit extension for group <n> insns. 1007 This field is also used to store the 8-bit opcode suffix for the 1008 AMD 3DNow! instructions. 1009 If this template has no extension opcode (the usual case) use None 1010 Instructions */ 1011 signed int extension_opcode:9; 1012 #define None (-1) /* If no extension_opcode is possible. */ 1013 1014 /* Pseudo prefixes. */ 1015 #define Prefix_Disp8 0 /* {disp8} */ 1016 #define Prefix_Disp16 1 /* {disp16} */ 1017 #define Prefix_Disp32 2 /* {disp32} */ 1018 #define Prefix_Load 3 /* {load} */ 1019 #define Prefix_Store 4 /* {store} */ 1020 #define Prefix_VEX 5 /* {vex} */ 1021 #define Prefix_VEX3 6 /* {vex3} */ 1022 #define Prefix_EVEX 7 /* {evex} */ 1023 #define Prefix_REX 8 /* {rex} */ 1024 #define Prefix_REX2 9 /* {rex2} */ 1025 #define Prefix_NoOptimize 10 /* {nooptimize} */ 1026 #define Prefix_NF 11 /* {nf} */ 1027 1028 /* the bits in opcode_modifier are used to generate the final opcode from 1029 the base_opcode. These bits also are used to detect alternate forms of 1030 the same instruction */ 1031 i386_opcode_modifier opcode_modifier; 1032 1033 /* cpu feature attributes */ 1034 i386_cpu_attr cpu, cpu_any; 1035 1036 /* operand_types[i] describes the type of operand i. This is made 1037 by OR'ing together all of the possible type masks. (e.g. 1038 'operand_types[i] = Reg|Imm' specifies that operand i can be 1039 either a register or an immediate operand. */ 1040 i386_operand_type operand_types[MAX_OPERANDS]; 1041 } 1042 insn_template; 1043 1044 /* these are for register name --> number & type hash lookup */ 1045 typedef struct 1046 { 1047 char reg_name[8]; 1048 i386_operand_type reg_type; 1049 unsigned char reg_flags; 1050 #define RegRex 0x1 /* Extended register. */ 1051 #define RegRex64 0x2 /* Extended 8 bit register. */ 1052 #define RegVRex 0x4 /* Extended vector register. */ 1053 #define RegRex2 0x8 /* Extended GPRs R16–R31 register. */ 1054 unsigned char reg_num; 1055 #define RegIP ((unsigned char ) ~0) 1056 /* EIZ and RIZ are fake index registers. */ 1057 #define RegIZ (RegIP - 1) 1058 /* FLAT is a fake segment register (Intel mode). */ 1059 #define RegFlat ((unsigned char) ~0) 1060 unsigned char dw2_regnum[2]; 1061 #define Dw2Inval 0xff 1062 } 1063 reg_entry; 1064