1 /* Declarations for C-SKY opcode table 2 Copyright (C) 2007-2024 Free Software Foundation, Inc. 3 Contributed by C-SKY Microsystems and Mentor Graphics. 4 5 This file is part of the GNU opcodes library. 6 7 This library is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 It is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GAS; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 20 02110-1301, USA. */ 21 22 #include "opcode/csky.h" 23 #include "safe-ctype.h" 24 25 #define OP_TABLE_NUM 2 26 #define MAX_OPRND_NUM 5 27 28 enum operand_type 29 { 30 OPRND_TYPE_NONE = 0, 31 /* Control register. */ 32 OPRND_TYPE_CTRLREG, 33 /* r0 - r7. */ 34 OPRND_TYPE_GREG0_7, 35 /* r0 - r15. */ 36 OPRND_TYPE_GREG0_15, 37 /* r16 - r31. */ 38 OPRND_TYPE_GREG16_31, 39 /* r0 - r31. */ 40 OPRND_TYPE_AREG, 41 /* (rx). */ 42 OPRND_TYPE_AREG_WITH_BRACKET, 43 OPRND_TYPE_AREG_WITH_LSHIFT, 44 OPRND_TYPE_AREG_WITH_LSHIFT_FPU, 45 46 OPRND_TYPE_FREG_WITH_INDEX, 47 OPRND_TYPE_VREG_WITH_INDEX, 48 /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ 49 OPRND_TYPE_REG_r1a, 50 /* r1 only, for divs/divu in csky v1 ISA. */ 51 OPRND_TYPE_REG_r1b, 52 /* r28. */ 53 OPRND_TYPE_REG_r28, 54 OPRND_TYPE_REGr4_r7, 55 /* sp register with bracket. */ 56 OPRND_TYPE_REGbsp, 57 /* sp register. */ 58 OPRND_TYPE_REGsp, 59 /* Register with bracket. */ 60 OPRND_TYPE_REGnr4_r7, 61 /* Not sp register. */ 62 OPRND_TYPE_REGnsp, 63 /* Not lr register. */ 64 OPRND_TYPE_REGnlr, 65 /* Not sp/lr register. */ 66 OPRND_TYPE_REGnsplr, 67 /* hi/lo register. */ 68 OPRND_TYPE_REGhilo, 69 /* VDSP register. */ 70 OPRND_TYPE_VREG, 71 72 /* cp index. */ 73 OPRND_TYPE_CPIDX, 74 /* cp regs. */ 75 OPRND_TYPE_CPREG, 76 /* cp cregs. */ 77 OPRND_TYPE_CPCREG, 78 /* fpu regs. */ 79 OPRND_TYPE_FREG, 80 /* fpu even regs. */ 81 OPRND_TYPE_FEREG, 82 /* Float round mode. */ 83 OPRND_TYPE_RM, 84 /* PSR bits. */ 85 OPRND_TYPE_PSR_BITS_LIST, 86 87 /* Constant. */ 88 OPRND_TYPE_CONSTANT, 89 /* Floating Constant. */ 90 OPRND_TYPE_FCONSTANT, 91 /* Extern lrw constant. */ 92 OPRND_TYPE_ELRW_CONSTANT, 93 /* [label]. */ 94 OPRND_TYPE_LABEL_WITH_BRACKET, 95 /* The operand is the same as first reg. It is a dummy reg that doesn't 96 appear in the binary code of the instruction. It is also used by 97 the disassembler. 98 For example: bclri rz, rz, imm5 -> bclri rz, imm5. */ 99 OPRND_TYPE_DUMMY_REG, 100 /* The type of the operand is same as the first operand. If the value 101 of the operand is same as the first operand, we can use a 16-bit 102 instruction to represent the opcode. 103 For example: addc r1, r1, r2 -> addc16 r1, r2. */ 104 OPRND_TYPE_2IN1_DUMMY, 105 /* Output a reg same as the first reg. 106 For example: addc r17, r1 -> addc32 r17, r17, r1. 107 The old "addc" cannot be represented by a 16-bit instruction because 108 16-bit "addc" only supports regs from r0 to r15. So we use "addc32" 109 which has 3 operands, and duplicate the first operand to the second. */ 110 OPRND_TYPE_DUP_GREG0_7, 111 OPRND_TYPE_DUP_GREG0_15, 112 OPRND_TYPE_DUP_AREG, 113 /* Immediate. */ 114 OPRND_TYPE_IMM1b, 115 OPRND_TYPE_IMM2b, 116 OPRND_TYPE_IMM3b, 117 OPRND_TYPE_IMM4b, 118 OPRND_TYPE_IMM5b, 119 OPRND_TYPE_IMM7b, 120 OPRND_TYPE_IMM8b, 121 OPRND_TYPE_IMM9b, 122 OPRND_TYPE_IMM12b, 123 OPRND_TYPE_IMM15b, 124 OPRND_TYPE_IMM16b, 125 OPRND_TYPE_IMM18b, 126 OPRND_TYPE_IMM32b, 127 /* Immediate left shift 2 bits. */ 128 OPRND_TYPE_IMM7b_LS2, 129 OPRND_TYPE_IMM8b_LS2, 130 /* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */ 131 OPRND_TYPE_IMM5b_1_31, 132 OPRND_TYPE_IMM5b_7_31, 133 /* OPRND_TYPE_IMM5b_LS means: Imm <= prev Imm. */ 134 OPRND_TYPE_IMM5b_LS, 135 /* Operand type for rori and rotri. */ 136 OPRND_TYPE_IMM5b_RORI, 137 OPRND_TYPE_IMM5b_VSH, 138 OPRND_TYPE_IMM5b_POWER, 139 OPRND_TYPE_IMM5b_7_31_POWER, 140 OPRND_TYPE_IMM5b_BMASKI, 141 OPRND_TYPE_IMM8b_BMASKI, 142 /* For v2 movih. */ 143 OPRND_TYPE_IMM16b_MOVIH, 144 /* For v2 ori. */ 145 OPRND_TYPE_IMM16b_ORI, 146 /* For v2 ld/st. */ 147 OPRND_TYPE_IMM_LDST, 148 OPRND_TYPE_IMM_FLDST, 149 OPRND_TYPE_IMM2b_JMPIX, 150 /* Offset for bloop. */ 151 OPRND_TYPE_BLOOP_OFF4b, 152 OPRND_TYPE_BLOOP_OFF12b, 153 /* Offset for jump. */ 154 OPRND_TYPE_OFF8b, 155 OPRND_TYPE_OFF10b, 156 OPRND_TYPE_OFF11b, 157 OPRND_TYPE_OFF16b, 158 OPRND_TYPE_OFF16b_LSL1, 159 OPRND_TYPE_OFF26b, 160 /* An immediate or label. */ 161 OPRND_TYPE_IMM_OFF18b, 162 /* Offset immediate. */ 163 OPRND_TYPE_OIMM3b, 164 OPRND_TYPE_OIMM4b, 165 OPRND_TYPE_OIMM5b, 166 OPRND_TYPE_OIMM8b, 167 OPRND_TYPE_OIMM12b, 168 OPRND_TYPE_OIMM16b, 169 OPRND_TYPE_OIMM18b, 170 /* For csky v2 idly. */ 171 OPRND_TYPE_OIMM5b_IDLY, 172 /* For v2 bmaski. */ 173 OPRND_TYPE_OIMM5b_BMASKI, 174 /* Constants. */ 175 OPRND_TYPE_CONST1, 176 /* PC relative offset. */ 177 OPRND_TYPE_PCR_OFFSET_16K, 178 OPRND_TYPE_PCR_OFFSET_64K, 179 OPRND_TYPE_PCR_OFFSET_64M, 180 OPRND_TYPE_CPFUNC, 181 OPRND_TYPE_GOT_PLT, 182 OPRND_TYPE_REGLIST_LDM, 183 OPRND_TYPE_REGLIST_DASH, 184 OPRND_TYPE_FREGLIST_DASH, 185 OPRND_TYPE_REGLIST_COMMA, 186 OPRND_TYPE_REGLIST_DASH_COMMA, 187 OPRND_TYPE_BRACKET, 188 OPRND_TYPE_ABRACKET, 189 OPRND_TYPE_JBTF, 190 OPRND_TYPE_JBR, 191 OPRND_TYPE_JBSR, 192 OPRND_TYPE_UNCOND10b, 193 OPRND_TYPE_UNCOND16b, 194 OPRND_TYPE_COND10b, 195 OPRND_TYPE_COND16b, 196 OPRND_TYPE_JCOMPZ, 197 OPRND_TYPE_LSB2SIZE, 198 OPRND_TYPE_MSB2SIZE, 199 OPRND_TYPE_LSB, 200 OPRND_TYPE_MSB, 201 /* Single float and double float. */ 202 OPRND_TYPE_SFLOAT, 203 OPRND_TYPE_DFLOAT, 204 OPRND_TYPE_HFLOAT_FMOVI, 205 OPRND_TYPE_SFLOAT_FMOVI, 206 OPRND_TYPE_DFLOAT_FMOVI, 207 }; 208 209 /* Operand descriptors. */ 210 struct operand 211 { 212 /* Mask for suboperand. */ 213 unsigned int mask; 214 /* Suboperand type. */ 215 enum operand_type type; 216 /* Operand shift. */ 217 int shift; 218 }; 219 220 struct soperand 221 { 222 /* Mask for operand. */ 223 unsigned int mask; 224 /* Operand type. */ 225 enum operand_type type; 226 /* Operand shift. */ 227 int shift; 228 /* Suboperand. */ 229 struct operand subs[3]; 230 }; 231 232 union csky_operand 233 { 234 struct operand oprnds[MAX_OPRND_NUM]; 235 struct suboperand1 236 { 237 struct operand oprnd; 238 struct soperand soprnd; 239 } soprnd1; 240 struct suboperand2 241 { 242 struct soperand soprnd; 243 struct operand oprnd; 244 } soprnd2; 245 }; 246 247 /* Describe a single instruction encoding. */ 248 struct csky_opcode_info 249 { 250 /* How many operands. */ 251 long operand_num; 252 /* The instruction opcode. */ 253 unsigned int opcode; 254 /* Operand information. */ 255 union csky_operand oprnd; 256 }; 257 258 /* C-SKY instruction description. Each mnemonic can have multiple 259 16-bit and 32-bit encodings. */ 260 struct csky_opcode 261 { 262 /* The instruction name. */ 263 const char *mnemonic; 264 /* Whether this is an unconditional control transfer instruction, 265 for the purposes of placing literal pools after it. 266 0 = no, 1 = within function, 2 = end of function. 267 See check_literals in gas/config/tc-csky.c. */ 268 int transfer; 269 /* Encodings for 16-bit opcodes. */ 270 struct csky_opcode_info op16[OP_TABLE_NUM]; 271 /* Encodings for 32-bit opcodes. */ 272 struct csky_opcode_info op32[OP_TABLE_NUM]; 273 /* Instruction set flag. */ 274 uint64_t isa_flag16; 275 uint64_t isa_flag32; 276 /* Whether this insn needs relocation, 0: no, !=0: yes. */ 277 signed int reloc16; 278 signed int reloc32; 279 /* Whether this insn needs relaxation, 0: no, != 0: yes. */ 280 signed int relax; 281 /* Worker function to call when this instruction needs special assembler 282 handling. */ 283 bool (*work) (void); 284 }; 285 286 /* The following are the opcodes used in relax/fix process. */ 287 #define CSKYV1_INST_JMPI 0x7000 288 #define CSKYV1_INST_ADDI 0x2000 289 #define CSKYV1_INST_SUBI 0x2400 290 #define CSKYV1_INST_LDW 0x8000 291 #define CSKYV1_INST_STW 0x9000 292 #define CSKYV1_INST_BSR 0xf800 293 #define CSKYV1_INST_LRW 0x7000 294 #define CSKYV1_INST_ADDU 0x1c00 295 #define CSKYV1_INST_JMP 0x00c0 296 #define CSKYV1_INST_MOV_R1_RX 0x1201 297 #define CSKYV1_INST_MOV_RX_R1 0x1210 298 299 #define CSKYV2_INST_BT16 0x0800 300 #define CSKYV2_INST_BF16 0x0c00 301 #define CSKYV2_INST_BT32 0xe8600000 302 #define CSKYV2_INST_BF32 0xe8400000 303 #define CSKYV2_INST_BR32 0xe8000000 304 #define CSKYV2_INST_NOP 0x6c03 305 #define CSKYV2_INST_MOVI16 0x3000 306 #define CSKYV2_INST_MOVI32 0xea000000 307 #define CSKYV2_INST_MOVIH 0xea200000 308 #define CSKYV2_INST_LRW16 0x1000 309 #define CSKYV2_INST_LRW32 0xea800000 310 #define CSKYV2_INST_BSR32 0xe0000000 311 #define CSKYV2_INST_BR32 0xe8000000 312 #define CSKYV2_INST_FLRW 0xf4003800 313 #define CSKYV2_INST_JMPI32 0xeac00000 314 #define CSKYV2_INST_JSRI32 0xeae00000 315 #define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000 316 #define CSKYV2_INST_JSR_R26 0xe8fa0000 317 #define CSKYV2_INST_MOV_R0_R0 0xc4004820 318 319 #define OPRND_SHIFT_0_BIT 0 320 #define OPRND_SHIFT_1_BIT 1 321 #define OPRND_SHIFT_2_BIT 2 322 #define OPRND_SHIFT_3_BIT 3 323 #define OPRND_SHIFT_4_BIT 4 324 325 #define OPRND_MASK_NONE 0x0 326 #define OPRND_MASK_0_1 0x3 327 #define OPRND_MASK_0_2 0x7 328 #define OPRND_MASK_0_3 0xf 329 #define OPRND_MASK_0_4 0x1f 330 #define OPRND_MASK_0_7 0xff 331 #define OPRND_MASK_0_8 0x1ff 332 #define OPRND_MASK_0_9 0x3ff 333 #define OPRND_MASK_0_10 0x7ff 334 #define OPRND_MASK_0_11 0xfff 335 #define OPRND_MASK_0_14 0x7fff 336 #define OPRND_MASK_0_15 0xffff 337 #define OPRND_MASK_0_17 0x3ffff 338 #define OPRND_MASK_0_25 0x3ffffff 339 #define OPRND_MASK_2_4 0x1c 340 #define OPRND_MASK_2_5 0x3c 341 #define OPRND_MASK_3_7 0xf8 342 #define OPRND_MASK_4 0x10 343 #define OPRND_MASK_4_5 0x30 344 #define OPRND_MASK_4_6 0x70 345 #define OPRND_MASK_4_7 0xf0 346 #define OPRND_MASK_4_8 0x1f0 347 #define OPRND_MASK_4_10 0x7f0 348 #define OPRND_MASK_5 0x20 349 #define OPRND_MASK_5_6 0x60 350 #define OPRND_MASK_5_7 0xe0 351 #define OPRND_MASK_5_8 0x1e0 352 #define OPRND_MASK_5_9 0x3e0 353 #define OPRND_MASK_6 0x40 354 #define OPRND_MASK_6_7 0xc0 355 #define OPRND_MASK_6_8 0x1c0 356 #define OPRND_MASK_6_9 0x3c0 357 #define OPRND_MASK_6_10 0x7c0 358 #define OPRND_MASK_7 0x80 359 #define OPRND_MASK_7_8 0x180 360 #define OPRND_MASK_8_9 0x300 361 #define OPRND_MASK_8_10 0x700 362 #define OPRND_MASK_8_11 0xf00 363 #define OPRND_MASK_9_10 0x600 364 #define OPRND_MASK_9_12 0x1e00 365 #define OPRND_MASK_10_11 0xc00 366 #define OPRND_MASK_10_14 0x7c00 367 #define OPRND_MASK_12_15 0xf000 368 #define OPRND_MASK_13_17 0x3e000 369 #define OPRND_MASK_16_19 0xf0000 370 #define OPRND_MASK_16_20 0x1f0000 371 #define OPRND_MASK_16_25 0x3ff0000 372 #define OPRND_MASK_17_24 0x1fe0000 373 #define OPRND_MASK_20 0x0100000 374 #define OPRND_MASK_20_21 0x0300000 375 #define OPRND_MASK_20_22 0x0700000 376 #define OPRND_MASK_20_23 0x0f00000 377 #define OPRND_MASK_20_24 0x1f00000 378 #define OPRND_MASK_20_25 0x3f00000 379 #define OPRND_MASK_21_24 0x1e00000 380 #define OPRND_MASK_21_25 0x3e00000 381 #define OPRND_MASK_25 0x2000000 382 #define OPRND_MASK_RSV 0xffffffff 383 #define OPRND_MASK_0_3or5_8 OPRND_MASK_0_3 | OPRND_MASK_5_8 384 #define OPRND_MASK_0_3or6_7 OPRND_MASK_0_3 | OPRND_MASK_6_7 385 #define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24 386 #define OPRND_MASK_0_3or25 OPRND_MASK_0_3 | OPRND_MASK_25 387 #define OPRND_MASK_0_4or21_24 OPRND_MASK_0_4 | OPRND_MASK_21_24 388 #define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25 389 #define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20 390 #define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10 391 #define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9 392 #define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20 393 #define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8 394 #define OPRND_MASK_5or20_21 OPRND_MASK_5 | OPRND_MASK_20_21 395 #define OPRND_MASK_5or20_22 OPRND_MASK_5 | OPRND_MASK_20_22 396 #define OPRND_MASK_5or20_23 OPRND_MASK_5 | OPRND_MASK_20_23 397 #define OPRND_MASK_5or20_24 OPRND_MASK_5 | OPRND_MASK_20_24 398 #define OPRND_MASK_5or20_25 OPRND_MASK_5 | OPRND_MASK_20_25 399 #define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24 400 #define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9 401 #define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25 402 #define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24 403 #define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25 404 #define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10 405 #define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25 406 #define OPRND_MASK_8_9or21_25 OPRND_MASK_8_9 | OPRND_MASK_21_25 407 #define OPRND_MASK_8_9or16_25 OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25 408 #define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24 409 #define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25 410 #define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25 411 #define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24 412 #define OPRND_MASK_4_6or20 OPRND_MASK_4_6 | OPRND_MASK_20 413 #define OPRND_MASK_5_7or20 OPRND_MASK_5_7 | OPRND_MASK_20 414 #define OPRND_MASK_4_5or20or25 OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25 415 #define OPRND_MASK_4_6or20or25 OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25 416 #define OPRND_MASK_4_7or20or25 OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25 417 #define OPRND_MASK_6_9or17_24 OPRND_MASK_6_9 | OPRND_MASK_17_24 418 #define OPRND_MASK_6_7or20 OPRND_MASK_6_7 | OPRND_MASK_20 419 #define OPRND_MASK_6or20 OPRND_MASK_6 | OPRND_MASK_20 420 #define OPRND_MASK_7or20 OPRND_MASK_7 | OPRND_MASK_20 421 #define OPRND_MASK_5or8_9or16_25 OPRND_MASK_5 | OPRND_MASK_8_9or16_25 422 #define OPRND_MASK_5or8_9or20_25 OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25 423 424 #define OPERAND_INFO(mask, type, shift) \ 425 {OPRND_MASK_##mask, OPRND_TYPE_##type, shift} 426 427 #define OPCODE_INFO_NONE() \ 428 {-2, 0, \ 429 {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 430 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 431 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 432 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 433 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 434 435 /* Here and in subsequent macros, the "oprnd" arguments are the 436 parenthesized arglist to the OPERAND_INFO macro above. */ 437 #define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ 438 {num, op, \ 439 {OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \ 440 OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}} 441 442 #define OPCODE_INFO0(op) \ 443 {0, op, \ 444 {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 445 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 446 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 447 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 448 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 449 #define OPCODE_INFO1(op, oprnd) \ 450 {1, op, \ 451 {{OPERAND_INFO oprnd, \ 452 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 453 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 454 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 455 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 456 #define OPCODE_INFO2(op, oprnd1, oprnd2) \ 457 {2, op, \ 458 {{OPERAND_INFO oprnd1, \ 459 OPERAND_INFO oprnd2, \ 460 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 461 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 462 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 463 #define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \ 464 {3, op, \ 465 {{OPERAND_INFO oprnd1, \ 466 OPERAND_INFO oprnd2, \ 467 OPERAND_INFO oprnd3, \ 468 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 469 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 470 #define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \ 471 {4, op, \ 472 {{OPERAND_INFO oprnd1, \ 473 OPERAND_INFO oprnd2, \ 474 OPERAND_INFO oprnd3, \ 475 OPERAND_INFO oprnd4, \ 476 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 477 #define OPCODE_INFO_LIST(op, oprnd) \ 478 {-1, op, \ 479 {{OPERAND_INFO oprnd, \ 480 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 481 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \ 482 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ 483 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 484 #define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ 485 {5, op, \ 486 {{OPERAND_INFO oprnd1, \ 487 OPERAND_INFO oprnd2, \ 488 OPERAND_INFO oprnd3, \ 489 OPERAND_INFO oprnd4, \ 490 OPERAND_INFO oprnd5}}} 491 492 #define BRACKET_OPRND(oprnd1, oprnd2) \ 493 OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \ 494 OPERAND_INFO oprnd1, \ 495 OPERAND_INFO oprnd2, \ 496 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) 497 #define ABRACKET_OPRND(oprnd1, oprnd2) \ 498 OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \ 499 OPERAND_INFO oprnd1, \ 500 OPERAND_INFO oprnd2, \ 501 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) 502 503 #define SOPCODE_INFO1(op, soprnd) \ 504 {1, op, \ 505 {{soprnd, \ 506 OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} 507 #define SOPCODE_INFO2(op, oprnd, soprnd) \ 508 {2, op, \ 509 {{OPERAND_INFO oprnd, soprnd}}} 510 511 512 /* Before using the opcode-defining macros, there need to be 513 #defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See 514 below. */ 515 /* FIXME: it is a wart that these parameters are not explicit. */ 516 517 #define OP16(mnem, opcode16, isa) \ 518 {mnem, _TRANSFER, \ 519 {opcode16, OPCODE_INFO_NONE ()}, \ 520 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 521 isa, 0, _RELOC16, 0, _RELAX, NULL} 522 523 #ifdef BUILD_AS 524 525 #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ 526 {mnem, _TRANSFER, \ 527 {opcode16, OPCODE_INFO_NONE ()}, \ 528 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 529 isa, 0, _RELOC16, 0, _RELAX, work} 530 #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ 531 {mnem, _TRANSFER, \ 532 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 533 {opcode32, OPCODE_INFO_NONE ()}, \ 534 0, isa, 0, _RELOC32, _RELAX, work} 535 #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ 536 {mnem, _TRANSFER, \ 537 {opcode16, OPCODE_INFO_NONE ()}, \ 538 {opcode32, OPCODE_INFO_NONE ()}, \ 539 isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} 540 #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ 541 {mnem, _TRANSFER, \ 542 {opcode16a, opcode16b}, \ 543 {opcode32, OPCODE_INFO_NONE ()}, \ 544 isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} 545 #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ 546 {mnem, _TRANSFER, \ 547 {opcode16a, opcode16b}, \ 548 {opcode32a, opcode32b}, \ 549 isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} 550 #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ 551 {mnem, _TRANSFER, \ 552 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 553 {opcode32a, opcode32b}, \ 554 0, isa, 0, _RELOC32, _RELAX, work} 555 556 #else /* ifdef BUILD_AS */ 557 558 #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ 559 {mnem, _TRANSFER, \ 560 {opcode16, OPCODE_INFO_NONE ()}, \ 561 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 562 isa, 0, _RELOC16, 0, _RELAX, NULL} 563 #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ 564 {mnem, _TRANSFER, \ 565 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 566 {opcode32, OPCODE_INFO_NONE ()}, \ 567 0, isa, 0, _RELOC32, _RELAX, NULL} 568 #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ 569 {mnem, _TRANSFER, \ 570 {opcode16, OPCODE_INFO_NONE ()}, \ 571 {opcode32, OPCODE_INFO_NONE ()}, \ 572 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 573 #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ 574 {mnem, _TRANSFER, \ 575 {opcode16a, opcode16b}, \ 576 {opcode32, OPCODE_INFO_NONE ()}, \ 577 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 578 #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ 579 {mnem, _TRANSFER, \ 580 {opcode16a, opcode16b}, \ 581 {opcode32a, opcode32b}, \ 582 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 583 #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ 584 {mnem, _TRANSFER, \ 585 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 586 {opcode32a, opcode32b}, \ 587 0, isa, 0, _RELOC32, _RELAX, NULL} 588 589 #endif /* ifdef BUILD_AS */ 590 591 #define DOP16(mnem, opcode16_1, opcode16_2, isa) \ 592 {mnem, _TRANSFER, \ 593 {opcode16_1, opcode16_2}, \ 594 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 595 isa, 0, _RELOC16, 0, _RELAX, NULL} 596 #define OP32(mnem, opcode32, isa) \ 597 {mnem, _TRANSFER, \ 598 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 599 {opcode32, OPCODE_INFO_NONE ()}, \ 600 0, isa, 0, _RELOC32, _RELAX, NULL} 601 #define DOP32(mnem, opcode32a, opcode32b, isa) \ 602 {mnem, _TRANSFER, \ 603 {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ 604 {opcode32a, opcode32b}, \ 605 0, isa, 0, _RELOC32, _RELAX, NULL} 606 #define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \ 607 {mnem, _TRANSFER, \ 608 {opcode16, OPCODE_INFO_NONE ()}, \ 609 {opcode32, OPCODE_INFO_NONE ()}, \ 610 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 611 #define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \ 612 {mnem, _TRANSFER, \ 613 {opcode16a, opcode16b}, \ 614 {opcode32, OPCODE_INFO_NONE ()}, \ 615 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 616 #define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \ 617 {mnem, _TRANSFER, \ 618 {opcode16, OPCODE_INFO_NONE ()}, \ 619 {opcode32a, opcode32b}, \ 620 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 621 #define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \ 622 {mnem, _TRANSFER, \ 623 {opcode16a, opcode16b}, \ 624 {opcode32a, opcode32b}, \ 625 isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} 626 627 628 /* Register names and numbers. */ 629 #define V1_REG_SP 0 630 #define V1_REG_LR 15 631 632 struct psrbit 633 { 634 int value; 635 int isa; 636 const char *name; 637 }; 638 639 const struct psrbit cskyv1_psr_bits[] = 640 { 641 {1, 0, "ie"}, 642 {2, 0, "fe"}, 643 {4, 0, "ee"}, 644 {8, 0, "af"}, 645 {0, 0, NULL}, 646 }; 647 648 const struct psrbit cskyv2_psr_bits[] = 649 { 650 {8, 0, "ee"}, 651 {4, 0, "ie"}, 652 {2, 0, "fe"}, 653 {1, 0, "af"}, 654 {0x10, CSKY_ISA_TRUST, "sie"}, 655 {0, 0, NULL}, 656 }; 657 658 #define GENERAL_REG_BANK 0x80000000 659 #define REG_SUPPORT_ALL 0xffffffff 660 661 /* CSKY register description. */ 662 struct csky_reg_def 663 { 664 /* The group number for control registers, 665 and set the bank of genaral registers to a special number. */ 666 int bank; 667 int regno; 668 /* The name displayed by serial number. */ 669 const char *name; 670 /* The name displayed by ABI infomation, 671 used when objdump add option -Mabi-names. */ 672 const char *abi_name; 673 /* The flags indicate which arches support the register. */ 674 int arch_flag; 675 /* Some registers depend on special features. */ 676 char *features; 677 }; 678 679 /* Arch flag. */ 680 #define ASH(a) (1 << CSKY_ARCH_##a) 681 682 /* All arches exclued 801. */ 683 #define REG_SUPPORT_A (REG_SUPPORT_ALL & ~ASH(801)) 684 685 /* All arches exclued 801 and 802. */ 686 #define REG_SUPPORT_B (REG_SUPPORT_ALL & ~(ASH(801) | ASH(802))) 687 688 /* All arches exclued 801, 802, 803, 805.*/ 689 #define REG_SUPPORT_C (REG_SUPPORT_ALL & ~(ASH(801) \ 690 | ASH(802) | ASH(803) | ASH(805))) 691 692 /* All arches exclued 801, 802, 803, 805, 807, 810. */ 693 #define REG_SUPPORT_D (REG_SUPPORT_C & ~(ASH(807) | ASH(810))) 694 695 /* All arches exclued 807, 810, 860. */ 696 #define REG_SUPPORT_E (REG_SUPPORT_ALL & ~(ASH(807) | ASH(810) | \ 697 ASH(860))) 698 699 /* C-SKY V1 general registers table. */ 700 static struct csky_reg_def csky_abiv1_general_regs[] = 701 { 702 #define DECLARE_REG(regno, abi_name, support) \ 703 {GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL} 704 705 DECLARE_REG (0, "sp", REG_SUPPORT_ALL), 706 DECLARE_REG (1, NULL, REG_SUPPORT_ALL), 707 DECLARE_REG (2, "a0", REG_SUPPORT_ALL), 708 DECLARE_REG (3, "a1", REG_SUPPORT_ALL), 709 DECLARE_REG (4, "a2", REG_SUPPORT_ALL), 710 DECLARE_REG (5, "a3", REG_SUPPORT_ALL), 711 DECLARE_REG (6, "a4", REG_SUPPORT_ALL), 712 DECLARE_REG (7, "a5", REG_SUPPORT_ALL), 713 DECLARE_REG (8, "fp", REG_SUPPORT_ALL), 714 DECLARE_REG (8, "l0", REG_SUPPORT_ALL), 715 DECLARE_REG (9, "l1", REG_SUPPORT_ALL), 716 DECLARE_REG (10, "l2", REG_SUPPORT_ALL), 717 DECLARE_REG (11, "l3", REG_SUPPORT_ALL), 718 DECLARE_REG (12, "l4", REG_SUPPORT_ALL), 719 DECLARE_REG (13, "l5", REG_SUPPORT_ALL), 720 DECLARE_REG (14, "gb", REG_SUPPORT_ALL), 721 DECLARE_REG (15, "lr", REG_SUPPORT_ALL), 722 #undef DECLARE_REG 723 {-1, -1, NULL, NULL, 0, NULL}, 724 }; 725 726 /* C-SKY V1 control registers table. */ 727 static struct csky_reg_def csky_abiv1_control_regs[] = 728 { 729 #define DECLARE_REG(regno, abi_name, support) \ 730 {0, regno, "cr"#regno, abi_name, support, NULL} 731 732 DECLARE_REG (0, "psr", REG_SUPPORT_ALL), 733 DECLARE_REG (1, "vbr", REG_SUPPORT_ALL), 734 DECLARE_REG (2, "epsr", REG_SUPPORT_ALL), 735 DECLARE_REG (3, "fpsr", REG_SUPPORT_ALL), 736 DECLARE_REG (4, "epc", REG_SUPPORT_ALL), 737 DECLARE_REG (5, "fpc", REG_SUPPORT_ALL), 738 DECLARE_REG (6, "ss0", REG_SUPPORT_ALL), 739 DECLARE_REG (7, "ss1", REG_SUPPORT_ALL), 740 DECLARE_REG (8, "ss2", REG_SUPPORT_ALL), 741 DECLARE_REG (9, "ss3", REG_SUPPORT_ALL), 742 DECLARE_REG (10, "ss4", REG_SUPPORT_ALL), 743 DECLARE_REG (11, "gcr", REG_SUPPORT_ALL), 744 DECLARE_REG (12, "gsr", REG_SUPPORT_ALL), 745 DECLARE_REG (13, "cpid", REG_SUPPORT_ALL), 746 DECLARE_REG (14, "dcsr", REG_SUPPORT_ALL), 747 DECLARE_REG (15, "cwr", REG_SUPPORT_ALL), 748 DECLARE_REG (16, NULL, REG_SUPPORT_ALL), 749 DECLARE_REG (17, "cfr", REG_SUPPORT_ALL), 750 DECLARE_REG (18, "ccr", REG_SUPPORT_ALL), 751 DECLARE_REG (19, "capr", REG_SUPPORT_ALL), 752 DECLARE_REG (20, "pacr", REG_SUPPORT_ALL), 753 DECLARE_REG (21, "prsr", REG_SUPPORT_ALL), 754 DECLARE_REG (22, "mir", REG_SUPPORT_ALL), 755 DECLARE_REG (23, "mrr", REG_SUPPORT_ALL), 756 DECLARE_REG (24, "mel0", REG_SUPPORT_ALL), 757 DECLARE_REG (25, "mel1", REG_SUPPORT_ALL), 758 DECLARE_REG (26, "meh", REG_SUPPORT_ALL), 759 DECLARE_REG (27, "mcr", REG_SUPPORT_ALL), 760 DECLARE_REG (28, "mpr", REG_SUPPORT_ALL), 761 DECLARE_REG (29, "mwr", REG_SUPPORT_ALL), 762 DECLARE_REG (30, "mcir", REG_SUPPORT_ALL), 763 #undef DECLARE_REG 764 {-1, -1, NULL, NULL, 0, NULL}, 765 }; 766 767 /* C-SKY V2 general registers table. */ 768 static struct csky_reg_def csky_abiv2_general_regs[] = 769 { 770 #ifdef DECLARE_REG 771 #undef DECLARE_REG 772 #endif 773 #define DECLARE_REG(regno, abi_name, support) \ 774 {GENERAL_REG_BANK, regno, "r"#regno, abi_name, support, NULL} 775 776 DECLARE_REG (0, "a0", REG_SUPPORT_ALL), 777 DECLARE_REG (1, "a1", REG_SUPPORT_ALL), 778 DECLARE_REG (2, "a2", REG_SUPPORT_ALL), 779 DECLARE_REG (3, "a3", REG_SUPPORT_ALL), 780 DECLARE_REG (4, "l0", REG_SUPPORT_ALL), 781 DECLARE_REG (5, "l1", REG_SUPPORT_ALL), 782 DECLARE_REG (6, "l2", REG_SUPPORT_ALL), 783 DECLARE_REG (7, "l3", REG_SUPPORT_ALL), 784 DECLARE_REG (8, "l4", REG_SUPPORT_ALL), 785 DECLARE_REG (9, "l5", REG_SUPPORT_A), 786 DECLARE_REG (10, "l6", REG_SUPPORT_A), 787 DECLARE_REG (11, "l7", REG_SUPPORT_A), 788 DECLARE_REG (12, "t0", REG_SUPPORT_A), 789 DECLARE_REG (13, "t1", REG_SUPPORT_ALL), 790 DECLARE_REG (14, "sp", REG_SUPPORT_ALL), 791 DECLARE_REG (15, "lr", REG_SUPPORT_ALL), 792 DECLARE_REG (16, "l8", REG_SUPPORT_B), 793 DECLARE_REG (17, "l9", REG_SUPPORT_B), 794 DECLARE_REG (18, "t2", REG_SUPPORT_B), 795 DECLARE_REG (19, "t3", REG_SUPPORT_B), 796 DECLARE_REG (20, "t4", REG_SUPPORT_B), 797 DECLARE_REG (21, "t5", REG_SUPPORT_B), 798 DECLARE_REG (22, "t6", REG_SUPPORT_B), 799 DECLARE_REG (23, "t7", REG_SUPPORT_B), 800 DECLARE_REG (24, "t8", REG_SUPPORT_B), 801 DECLARE_REG (25, "t9", REG_SUPPORT_B), 802 DECLARE_REG (26, NULL, REG_SUPPORT_B), 803 DECLARE_REG (27, NULL, REG_SUPPORT_B), 804 DECLARE_REG (28, "gb", REG_SUPPORT_B), 805 DECLARE_REG (28, "rgb", REG_SUPPORT_B), 806 DECLARE_REG (28, "rdb", REG_SUPPORT_B), 807 DECLARE_REG (29, "tb", REG_SUPPORT_B), 808 DECLARE_REG (29, "rtb", REG_SUPPORT_B), 809 DECLARE_REG (30, "svbr", REG_SUPPORT_A), 810 DECLARE_REG (31, "tls", REG_SUPPORT_B), 811 812 /* The followings JAVA/BCTM's features. */ 813 DECLARE_REG (23, "fp", REG_SUPPORT_ALL), 814 DECLARE_REG (24, "top", REG_SUPPORT_ALL), 815 DECLARE_REG (25, "bsp", REG_SUPPORT_ALL), 816 817 {-1, -1, NULL, NULL, 0, NULL}, 818 }; 819 820 /* C-SKY V2 control registers table. */ 821 static struct csky_reg_def csky_abiv2_control_regs[] = 822 { 823 824 #ifdef DECLARE_REG 825 #undef DECLARE_REG 826 #endif 827 /* Bank0. */ 828 #define DECLARE_REG(regno, abi_name) \ 829 {0, regno, "cr<"#regno", 0>", abi_name, REG_SUPPORT_ALL, NULL} 830 DECLARE_REG (0, "psr"), 831 DECLARE_REG (1, "vbr"), 832 DECLARE_REG (2, "epsr"), 833 DECLARE_REG (3, "fpsr"), 834 DECLARE_REG (4, "epc"), 835 DECLARE_REG (5, "fpc"), 836 DECLARE_REG (6, "ss0"), 837 DECLARE_REG (7, "ss1"), 838 DECLARE_REG (8, "ss2"), 839 DECLARE_REG (9, "ss3"), 840 DECLARE_REG (10, "ss4"), 841 DECLARE_REG (11, "gcr"), 842 DECLARE_REG (12, "gsr"), 843 DECLARE_REG (13, "cpid"), 844 DECLARE_REG (14, "dcsr"), 845 DECLARE_REG (15, NULL), 846 DECLARE_REG (16, NULL), 847 DECLARE_REG (17, "cfr"), 848 DECLARE_REG (18, "ccr"), 849 DECLARE_REG (19, "capr"), 850 DECLARE_REG (20, "pacr"), 851 DECLARE_REG (21, "prsr"), 852 DECLARE_REG (22, "cir"), 853 DECLARE_REG (23, "ccr2"), 854 DECLARE_REG (24, NULL), 855 DECLARE_REG (25, "cer2"), 856 DECLARE_REG (26, NULL), 857 DECLARE_REG (27, NULL), 858 DECLARE_REG (28, "rvbr"), 859 DECLARE_REG (29, "rmr"), 860 DECLARE_REG (30, "mpid"), 861 862 #undef DECLARE_REG 863 #define DECLARE_REG(regno, abi_name, support) \ 864 {0, regno, "cr<"#regno", 0>", abi_name, support, NULL} 865 DECLARE_REG (31, "chr", REG_SUPPORT_E), 866 DECLARE_REG (31, "hint", REG_SUPPORT_C), 867 868 /* Bank1. */ 869 #undef DECLARE_REG 870 #define DECLARE_REG(regno, abi_name) \ 871 {1, regno, "cr<"#regno", 1>", abi_name, REG_SUPPORT_ALL, NULL} 872 873 DECLARE_REG (14, "usp"), 874 DECLARE_REG (26, "cindex"), 875 DECLARE_REG (27, "cdata0"), 876 DECLARE_REG (28, "cdata1"), 877 DECLARE_REG (29, "cdata2"), 878 DECLARE_REG (30, "cdata3"), 879 DECLARE_REG (31, "cins"), 880 881 /* Bank2. */ 882 #undef DECLARE_REG 883 #define DECLARE_REG(regno, abi_name) \ 884 {2, regno, "cr<"#regno", 2>", abi_name, REG_SUPPORT_ALL, NULL} 885 886 DECLARE_REG (0, "fid"), 887 DECLARE_REG (1, "fcr"), 888 DECLARE_REG (2, "fesr"), 889 890 /* Bank3. */ 891 #undef DECLARE_REG 892 #define DECLARE_REG(regno, abi_name) \ 893 {3, regno, "cr<"#regno", 3>", abi_name, REG_SUPPORT_ALL, NULL} 894 DECLARE_REG (8, "dcr"), 895 DECLARE_REG (8, "sedcr"), 896 DECLARE_REG (9, "pcr"), 897 DECLARE_REG (9, "sepcr"), 898 899 /* Bank15. */ 900 #undef DECLARE_REG 901 #define DECLARE_REG(regno, abi_name) \ 902 {15, regno, "cr<"#regno", 15>", abi_name, REG_SUPPORT_ALL, NULL} 903 904 DECLARE_REG (0, "mir"), 905 DECLARE_REG (2, "mel0"), 906 DECLARE_REG (3, "mel1"), 907 DECLARE_REG (4, "meh"), 908 DECLARE_REG (6, "mpr"), 909 DECLARE_REG (8, "mcir"), 910 DECLARE_REG (28, "mpgd0"), 911 DECLARE_REG (29, "mpgd"), 912 DECLARE_REG (29, "mpgd1"), 913 DECLARE_REG (30, "msa0"), 914 DECLARE_REG (31, "msa1"), 915 #undef DECLARE_REG 916 {-1, -1, NULL, NULL, 0, NULL}, 917 }; 918 919 /* Get register name according to giving parameters, 920 IS_ABI controls whether is ABI name or not. */ 921 static inline const char * 922 get_register_name (struct csky_reg_def *reg_table, 923 int arch, int bank, int regno, int is_abi) 924 { 925 static char regname[64] = {0}; 926 unsigned int i = 0; 927 while (reg_table[i].name != NULL) 928 { 929 if (reg_table[i].bank == bank 930 && reg_table[i].regno == regno 931 && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK)))) 932 { 933 if (is_abi && reg_table[i].abi_name) 934 return reg_table[i].abi_name; 935 else 936 return reg_table[i].name; 937 } 938 i++; 939 } 940 941 if (bank & 0x80000000) 942 return "unkown register"; 943 944 sprintf (regname, "cr<%d, %d>", regno, bank); 945 946 return regname; 947 } 948 949 /* Get register number according to giving parameters. 950 If not found, return -1. */ 951 static inline int 952 get_register_number (struct csky_reg_def *reg_table, 953 int arch, char *s, char **end, int *bank) 954 { 955 unsigned int i = 0; 956 int len = 0; 957 while (reg_table[i].name != NULL) 958 { 959 len = strlen (reg_table[i].name); 960 if ((strncasecmp (reg_table[i].name, s, len) == 0) 961 && !(ISDIGIT (s[len])) 962 && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK)))) 963 { 964 *end = s + len; 965 *bank = reg_table[i].bank; 966 return reg_table[i].regno; 967 } 968 969 if (reg_table[i].abi_name == NULL) 970 { 971 i++; 972 continue; 973 } 974 975 len = strlen (reg_table[i].abi_name); 976 if ((strncasecmp (reg_table[i].abi_name, s, len) == 0) 977 && !(ISALNUM (s[len])) 978 && (reg_table[i].arch_flag & (1u << (arch & CSKY_ARCH_MASK)))) 979 { 980 *end = s + len; 981 *bank = reg_table[i].bank; 982 return reg_table[i].regno; 983 } 984 i++; 985 } 986 return -1; 987 } 988 989 /* Return general register's name. */ 990 static inline const char * 991 csky_get_general_reg_name (int arch, int regno, int is_abi) 992 { 993 struct csky_reg_def *reg_table; 994 995 if (IS_CSKY_ARCH_V1 (arch)) 996 reg_table = csky_abiv1_general_regs; 997 else 998 reg_table = csky_abiv2_general_regs; 999 1000 return get_register_name (reg_table, arch, GENERAL_REG_BANK, regno, is_abi); 1001 } 1002 1003 /* Return general register's number. */ 1004 static inline int 1005 csky_get_general_regno (int arch, char *s, char **end) 1006 { 1007 struct csky_reg_def *reg_table; 1008 int bank = 0; 1009 1010 if (IS_CSKY_ARCH_V1 (arch)) 1011 reg_table = csky_abiv1_general_regs; 1012 else 1013 reg_table = csky_abiv2_general_regs; 1014 1015 return get_register_number (reg_table, arch, s, end, &bank); 1016 } 1017 1018 /* Return control register's name. */ 1019 static inline const char * 1020 csky_get_control_reg_name (int arch, int bank, int regno, int is_abi) 1021 { 1022 struct csky_reg_def *reg_table; 1023 1024 if (IS_CSKY_ARCH_V1 (arch)) 1025 reg_table = csky_abiv1_control_regs; 1026 else 1027 reg_table = csky_abiv2_control_regs; 1028 1029 return get_register_name (reg_table, arch, bank, regno, is_abi); 1030 } 1031 1032 /* Return control register's number. */ 1033 static inline int 1034 csky_get_control_regno (int arch, char *s, char **end, int *bank) 1035 { 1036 struct csky_reg_def *reg_table; 1037 1038 if (IS_CSKY_ARCH_V1 (arch)) 1039 reg_table = csky_abiv1_control_regs; 1040 else 1041 reg_table = csky_abiv2_control_regs; 1042 1043 return get_register_number (reg_table, arch, s, end, bank); 1044 } 1045 1046 /* C-SKY V1 opcodes. */ 1047 const struct csky_opcode csky_v1_opcodes[] = 1048 { 1049 #define _TRANSFER 0 1050 #define _RELOC16 0 1051 #define _RELOC32 0 1052 #define _RELAX 0 1053 OP16 ("bkpt", 1054 OPCODE_INFO0 (0x0000), 1055 CSKYV1_ISA_E1), 1056 OP16 ("sync", 1057 OPCODE_INFO0 (0x0001), 1058 CSKYV1_ISA_E1), 1059 #undef _TRANSFER 1060 #define _TRANSFER 2 1061 OP16 ("rfi", 1062 OPCODE_INFO0 (0x0003), 1063 CSKYV1_ISA_E1), 1064 #undef _TRANSFER 1065 #define _TRANSFER 0 1066 OP16 ("stop", 1067 OPCODE_INFO0 (0x0004), 1068 CSKYV1_ISA_E1), 1069 OP16 ("wait", 1070 OPCODE_INFO0 (0x0005), 1071 CSKYV1_ISA_E1), 1072 OP16 ("doze", 1073 OPCODE_INFO0 (0x0006), 1074 CSKYV1_ISA_E1), 1075 OP16 ("idly4", 1076 OPCODE_INFO0 (0x0007), 1077 CSKYV1_ISA_E1), 1078 OP16 ("trap", 1079 OPCODE_INFO1 (0x0008, 1080 (0_1, IMM2b, OPRND_SHIFT_0_BIT)), 1081 CSKYV1_ISA_E1), 1082 OP16 ("mvtc", 1083 OPCODE_INFO0 (0x000c), 1084 CSKY_ISA_DSP), 1085 OP16 ("cprc", 1086 OPCODE_INFO0 (0x000d), 1087 CSKY_ISA_CP), 1088 OP16 ("cpseti", 1089 OPCODE_INFO1 (0x0010, 1090 (0_3, CPIDX, OPRND_SHIFT_0_BIT)), 1091 CSKY_ISA_CP), 1092 OP16 ("mvc", 1093 OPCODE_INFO1 (0x0020, 1094 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1095 CSKYV1_ISA_E1), 1096 OP16 ("mvcv", 1097 OPCODE_INFO1 (0x0030, 1098 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1099 CSKYV1_ISA_E1), 1100 OP16 ("ldq", 1101 OPCODE_INFO2 (0x0040, 1102 (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), 1103 (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), 1104 CSKYV1_ISA_E1), 1105 OP16 ("stq", 1106 OPCODE_INFO2 (0x0050, 1107 (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), 1108 (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), 1109 CSKYV1_ISA_E1), 1110 OP16 ("ldm", 1111 OPCODE_INFO2 (0x0060, 1112 (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), 1113 (NONE, REGbsp, OPRND_SHIFT_0_BIT)), 1114 CSKYV1_ISA_E1), 1115 OP16 ("stm", 1116 OPCODE_INFO2 (0x0070, 1117 (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), 1118 (NONE, REGbsp, OPRND_SHIFT_0_BIT)), 1119 CSKYV1_ISA_E1), 1120 DOP16 ("dect", 1121 OPCODE_INFO3 (0x0080, 1122 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1123 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1124 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1125 OPCODE_INFO1 (0x0080, 1126 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1127 CSKYV1_ISA_E1), 1128 DOP16 ("decf", 1129 OPCODE_INFO3 (0x0090, 1130 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1131 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1132 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1133 OPCODE_INFO1 (0x0090, 1134 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1135 CSKYV1_ISA_E1), 1136 DOP16 ("inct", 1137 OPCODE_INFO3 (0x00a0, 1138 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1139 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1140 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1141 OPCODE_INFO1 (0x00a0, 1142 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1143 CSKYV1_ISA_E1), 1144 DOP16 ("incf", 1145 OPCODE_INFO3 (0x00b0, 1146 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1147 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1148 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1149 OPCODE_INFO1 (0x00b0, 1150 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1151 CSKYV1_ISA_E1), 1152 #undef _TRANSFER 1153 #define _TRANSFER 2 1154 OP16 ("jmp", 1155 OPCODE_INFO1 (0x00c0, 1156 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1157 CSKYV1_ISA_E1), 1158 #undef _TRANSFER 1159 #define _TRANSFER 0 1160 OP16 ("jsr", 1161 OPCODE_INFO1 (0x00d0, 1162 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1163 CSKYV1_ISA_E1), 1164 DOP16 ("ff1", 1165 OPCODE_INFO2 (0x00e0, 1166 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1167 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1168 OPCODE_INFO1 (0x00e0, 1169 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1170 CSKYV1_ISA_E1), 1171 DOP16 ("brev", 1172 OPCODE_INFO2 (0x00f0, 1173 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1174 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1175 OPCODE_INFO1 (0x00f0, 1176 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1177 CSKYV1_ISA_E1), 1178 DOP16 ("xtrb3", 1179 OPCODE_INFO2 (0x0100, 1180 (NONE, REG_r1a, OPRND_SHIFT_0_BIT), 1181 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1182 OPCODE_INFO1 (0x0100, 1183 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1184 CSKYV1_ISA_E1), 1185 DOP16 ("xtrb2", 1186 OPCODE_INFO2 (0x0110, 1187 (NONE, REG_r1a, OPRND_SHIFT_0_BIT), 1188 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1189 OPCODE_INFO1 (0x0110, 1190 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1191 CSKYV1_ISA_E1), 1192 DOP16 ("xtrb1", 1193 OPCODE_INFO2 (0x0120, 1194 (NONE, REG_r1a, OPRND_SHIFT_0_BIT), 1195 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1196 OPCODE_INFO1 (0x0120, 1197 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1198 CSKYV1_ISA_E1), 1199 DOP16 ("xtrb0", 1200 OPCODE_INFO2 (0x0130, 1201 (NONE, REG_r1a, OPRND_SHIFT_0_BIT), 1202 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1203 OPCODE_INFO1 (0x0130, 1204 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1205 CSKYV1_ISA_E1), 1206 DOP16 ("zextb", 1207 OPCODE_INFO2 (0x0140, 1208 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1209 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1210 OPCODE_INFO1 (0x0140, 1211 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1212 CSKYV1_ISA_E1), 1213 DOP16 ("sextb", 1214 OPCODE_INFO2 (0x0150, 1215 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1216 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1217 OPCODE_INFO1 (0x0150, 1218 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1219 CSKYV1_ISA_E1), 1220 DOP16 ("zexth", 1221 OPCODE_INFO2 (0x0160, 1222 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1223 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1224 OPCODE_INFO1 (0x0160, 1225 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1226 CSKYV1_ISA_E1), 1227 DOP16 ("sexth", 1228 OPCODE_INFO2 (0x0170, 1229 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1230 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1231 OPCODE_INFO1 (0x0170, 1232 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1233 CSKYV1_ISA_E1), 1234 DOP16 ("declt", 1235 OPCODE_INFO3 (0x0180, 1236 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1237 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1238 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1239 OPCODE_INFO1 (0x0180, 1240 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1241 CSKYV1_ISA_E1), 1242 OP16 ("tstnbz", 1243 OPCODE_INFO1 (0x0190, 1244 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1245 CSKYV1_ISA_E1), 1246 DOP16 ("decgt", 1247 OPCODE_INFO3 (0x01a0, 1248 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1249 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1250 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1251 OPCODE_INFO1 (0x01a0, 1252 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1253 CSKYV1_ISA_E1), 1254 DOP16 ("decne", 1255 OPCODE_INFO3 (0x01b0, 1256 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1257 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1258 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1259 OPCODE_INFO1 (0x01b0, 1260 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1261 CSKYV1_ISA_E1), 1262 OP16 ("clrt", 1263 OPCODE_INFO1 (0x01c0, 1264 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1265 CSKYV1_ISA_E1), 1266 OP16 ("clrf", 1267 OPCODE_INFO1 (0x01d0, 1268 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1269 CSKYV1_ISA_E1), 1270 DOP16 ("abs", 1271 OPCODE_INFO2 (0x01e0, 1272 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1273 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1274 OPCODE_INFO1 (0x01e0, 1275 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1276 CSKYV1_ISA_E1), 1277 DOP16 ("not", 1278 OPCODE_INFO2 (0x01f0, 1279 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1280 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), 1281 OPCODE_INFO1 (0x01f0, 1282 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1283 CSKYV1_ISA_E1), 1284 OP16 ("movt", 1285 OPCODE_INFO2 (0x0200, 1286 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1287 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1288 CSKYV1_ISA_E1), 1289 DOP16 ("mult", 1290 OPCODE_INFO3 (0x0300, 1291 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1292 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1293 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1294 OPCODE_INFO2 (0x0300, 1295 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1296 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1297 CSKYV1_ISA_E1), 1298 OP16 ("mac", 1299 OPCODE_INFO2 (0x0400, 1300 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1301 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1302 CSKY_ISA_MAC), 1303 DOP16 ("subu", 1304 OPCODE_INFO3 (0x0500, 1305 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1306 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1307 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1308 OPCODE_INFO2 (0x0500, 1309 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1310 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1311 CSKYV1_ISA_E1), 1312 DOP16 ("sub", 1313 OPCODE_INFO3 (0x0500, 1314 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1315 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1316 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1317 OPCODE_INFO2 (0x0500, 1318 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1319 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1320 CSKYV1_ISA_E1), 1321 DOP16 ("addc", 1322 OPCODE_INFO3 (0x0600, 1323 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1324 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1325 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1326 OPCODE_INFO2 (0x0600, 1327 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1328 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1329 CSKYV1_ISA_E1), 1330 DOP16 ("subc", 1331 OPCODE_INFO3 (0x0700, 1332 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1333 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1334 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1335 OPCODE_INFO2 (0x0700, 1336 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1337 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1338 CSKYV1_ISA_E1), 1339 OP16 ("cprgr", 1340 OPCODE_INFO2 (0x0800, 1341 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1342 (4_8, CPREG, OPRND_SHIFT_0_BIT)), 1343 CSKY_ISA_CP), 1344 OP16 ("movf", 1345 OPCODE_INFO2 (0x0a00, 1346 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1347 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1348 CSKYV1_ISA_E1), 1349 DOP16 ("lsr", 1350 OPCODE_INFO3 (0x0b00, 1351 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1352 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1353 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1354 OPCODE_INFO2 (0x0b00, 1355 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1356 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1357 CSKYV1_ISA_E1), 1358 OP16 ("cmphs", 1359 OPCODE_INFO2 (0x0c00, 1360 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1361 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1362 CSKYV1_ISA_E1), 1363 OP16 ("cmplt", 1364 OPCODE_INFO2 (0x0d00, 1365 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1366 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1367 CSKYV1_ISA_E1), 1368 OP16 ("tst", 1369 OPCODE_INFO2 (0x0e00, 1370 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1371 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1372 CSKYV1_ISA_E1), 1373 OP16 ("cmpne", 1374 OPCODE_INFO2 (0x0f00, 1375 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1376 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1377 CSKYV1_ISA_E1), 1378 OP16 ("mfcr", 1379 OPCODE_INFO2 (0x1000, 1380 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1381 (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), 1382 CSKYV1_ISA_E1), 1383 OP16 ("psrclr", 1384 OPCODE_INFO_LIST (0x11f0, 1385 (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), 1386 CSKYV1_ISA_E1), 1387 OP16 ("psrset", 1388 OPCODE_INFO_LIST (0x11f8, 1389 (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), 1390 CSKYV1_ISA_E1), 1391 OP16 ("mov", 1392 OPCODE_INFO2 (0x1200, 1393 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1394 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1395 CSKYV1_ISA_E1), 1396 OP16 ("bgenr", 1397 OPCODE_INFO2 (0x1300, 1398 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1399 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1400 CSKYV1_ISA_E1), 1401 DOP16 ("rsub", 1402 OPCODE_INFO3 (0x1400, 1403 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1404 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1405 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1406 OPCODE_INFO2 (0x1400, 1407 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1408 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1409 CSKYV1_ISA_E1), 1410 DOP16 ("ixw", 1411 OPCODE_INFO3 (0x1500, 1412 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1413 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1414 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1415 OPCODE_INFO2 (0x1500, 1416 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1417 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1418 CSKYV1_ISA_E1), 1419 DOP16 ("and", 1420 OPCODE_INFO3 (0x1600, 1421 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1422 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1423 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1424 OPCODE_INFO2 (0x1600, 1425 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1426 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1427 CSKYV1_ISA_E1), 1428 DOP16 ("xor", 1429 OPCODE_INFO3 (0x1700, 1430 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1431 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1432 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1433 OPCODE_INFO2 (0x1700, 1434 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1435 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1436 CSKYV1_ISA_E1), 1437 OP16 ("mtcr", 1438 OPCODE_INFO2 (0x1800, 1439 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1440 (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), 1441 CSKYV1_ISA_E1), 1442 DOP16 ("asr", 1443 OPCODE_INFO3 (0x1a00, 1444 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1445 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1446 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1447 OPCODE_INFO2 (0x1a00, 1448 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1449 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1450 CSKYV1_ISA_E1), 1451 DOP16 ("lsl", 1452 OPCODE_INFO3 (0x1b00, 1453 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1454 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1455 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1456 OPCODE_INFO2 (0x1b00, 1457 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1458 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1459 CSKYV1_ISA_E1), 1460 DOP16 ("addu", 1461 OPCODE_INFO3 (0x1c00, 1462 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1463 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1464 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1465 OPCODE_INFO2 (0x1c00, 1466 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1467 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1468 CSKYV1_ISA_E1), 1469 OP16 ("add", 1470 OPCODE_INFO2 (0x1c00, 1471 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1472 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1473 CSKYV1_ISA_E1), 1474 DOP16 ("ixh", 1475 OPCODE_INFO3 (0x1d00, 1476 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1477 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1478 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1479 OPCODE_INFO2 (0x1d00, 1480 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1481 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1482 CSKYV1_ISA_E1), 1483 DOP16 ("or", 1484 OPCODE_INFO3 (0x1e00, 1485 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1486 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1487 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1488 OPCODE_INFO2 (0x1e00, 1489 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1490 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1491 CSKYV1_ISA_E1), 1492 DOP16 ("andn", 1493 OPCODE_INFO3 (0x1f00, 1494 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1495 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1496 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1497 OPCODE_INFO2 (0x1f00, 1498 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1499 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1500 CSKYV1_ISA_E1), 1501 DOP16 ("addi", 1502 OPCODE_INFO3 (0x2000, 1503 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1504 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1505 (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), 1506 OPCODE_INFO2 (0x2000, 1507 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1508 (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), 1509 CSKYV1_ISA_E1), 1510 OP16 ("cmplti", 1511 OPCODE_INFO2 (0x2200, 1512 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1513 (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), 1514 CSKYV1_ISA_E1), 1515 DOP16 ("subi", 1516 OPCODE_INFO3 (0x2400, 1517 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1518 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1519 (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), 1520 OPCODE_INFO2 (0x2400, 1521 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1522 (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), 1523 CSKYV1_ISA_E1), 1524 OP16 ("cpwgr", 1525 OPCODE_INFO2 (0x2600, 1526 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1527 (4_8, CPREG, OPRND_SHIFT_0_BIT)), 1528 CSKY_ISA_CP), 1529 DOP16 ("rsubi", 1530 OPCODE_INFO3 (0x2800, 1531 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1532 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1533 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1534 OPCODE_INFO2 (0x2800, 1535 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1536 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1537 CSKYV1_ISA_E1), 1538 OP16 ("cmpnei", 1539 OPCODE_INFO2 (0x2a00, 1540 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1541 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1542 CSKYV1_ISA_E1), 1543 OP16 ("bmaski", 1544 OPCODE_INFO2 (0x2c00, 1545 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1546 (4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)), 1547 CSKYV1_ISA_E1), 1548 DOP16 ("divu", 1549 OPCODE_INFO3 (0x2c10, 1550 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1551 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1552 (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), 1553 OPCODE_INFO2 (0x2c10, 1554 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1555 (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), 1556 CSKYV1_ISA_E1), 1557 OP16 ("mflos", 1558 OPCODE_INFO1 (0x2c20, 1559 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1560 CSKY_ISA_MAC_DSP), 1561 OP16 ("mfhis", 1562 OPCODE_INFO1 (0x2c30, 1563 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1564 CSKY_ISA_MAC_DSP), 1565 OP16 ("mtlo", 1566 OPCODE_INFO1 (0x2c40, 1567 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1568 CSKY_ISA_MAC_DSP), 1569 OP16 ("mthi", 1570 OPCODE_INFO1 (0x2c50, 1571 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1572 CSKY_ISA_MAC_DSP), 1573 OP16 ("mflo", 1574 OPCODE_INFO1 (0x2c60, 1575 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1576 CSKY_ISA_MAC_DSP), 1577 OP16 ("mfhi", 1578 OPCODE_INFO1 (0x2c70, 1579 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1580 CSKY_ISA_MAC_DSP), 1581 DOP16 ("andi", 1582 OPCODE_INFO3 (0x2e00, 1583 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1584 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1585 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1586 OPCODE_INFO2 (0x2e00, 1587 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1588 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1589 CSKYV1_ISA_E1), 1590 DOP16 ("bclri", 1591 OPCODE_INFO3 (0x3000, 1592 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1593 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1594 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1595 OPCODE_INFO2 (0x3000, 1596 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1597 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1598 CSKYV1_ISA_E1), 1599 OP16 ("bgeni", 1600 OPCODE_INFO2 (0x3200, 1601 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1602 (4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)), 1603 CSKYV1_ISA_E1), 1604 OP16 ("cpwir", 1605 OPCODE_INFO1 (0x3200, 1606 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1607 CSKY_ISA_CP), 1608 DOP16 ("divs", 1609 OPCODE_INFO3 (0x3210, 1610 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1611 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1612 (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), 1613 OPCODE_INFO2 (0x3210, 1614 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1615 (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), 1616 CSKYV1_ISA_E1), 1617 OP16 ("cprsr", 1618 OPCODE_INFO1 (0x3220, 1619 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1620 CSKY_ISA_CP), 1621 OP16 ("cpwsr", 1622 OPCODE_INFO1 (0x3230, 1623 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1624 CSKY_ISA_CP), 1625 DOP16 ("bseti", 1626 OPCODE_INFO3 (0x3400, 1627 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1628 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1629 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1630 OPCODE_INFO2 (0x3400, 1631 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1632 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1633 CSKYV1_ISA_E1), 1634 OP16 ("btsti", 1635 OPCODE_INFO2 (0x3600, 1636 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1637 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 1638 CSKYV1_ISA_E1), 1639 DOP16 ("rotli", 1640 OPCODE_INFO3 (0x3800, 1641 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1642 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1643 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1644 OPCODE_INFO2 (0x3800, 1645 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1646 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1647 CSKYV1_ISA_E1), 1648 DOP16 ("xsr", 1649 OPCODE_INFO3 (0x3800, 1650 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1651 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1652 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1653 OPCODE_INFO1 (0x3800, 1654 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1655 CSKYV1_ISA_E1), 1656 DOP16 ("asrc", 1657 OPCODE_INFO3 (0x3a00, 1658 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1659 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1660 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1661 OPCODE_INFO1 (0x3a00, 1662 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1663 CSKYV1_ISA_E1), 1664 DOP16 ("asri", 1665 OPCODE_INFO3 (0x3a00, 1666 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1667 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1668 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1669 OPCODE_INFO2 (0x3a00, 1670 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1671 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1672 CSKYV1_ISA_E1), 1673 DOP16 ("lslc", 1674 OPCODE_INFO3 (0x3c00, 1675 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1676 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1677 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1678 OPCODE_INFO1 (0x3c00, 1679 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1680 CSKYV1_ISA_E1), 1681 DOP16 ("lsli", 1682 OPCODE_INFO3 (0x3c00, 1683 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1684 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1685 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1686 OPCODE_INFO2 (0x3c00, 1687 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1688 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1689 CSKYV1_ISA_E1), 1690 DOP16 ("lsrc", 1691 OPCODE_INFO3 (0x3e00, 1692 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1693 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1694 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 1695 OPCODE_INFO1 (0x3e00, 1696 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 1697 CSKYV1_ISA_E1), 1698 DOP16 ("lsri", 1699 OPCODE_INFO3 (0x3e00, 1700 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1701 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1702 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1703 OPCODE_INFO2 (0x3e00, 1704 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1705 (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), 1706 CSKYV1_ISA_E1), 1707 OP16 ("ldex", 1708 SOPCODE_INFO2 (0x4000, 1709 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1710 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1711 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1712 CSKY_ISA_MP), 1713 OP16 ("ldex.w", 1714 SOPCODE_INFO2 (0x4000, 1715 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1716 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1717 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1718 CSKY_ISA_MP), 1719 OP16 ("ldwex", 1720 SOPCODE_INFO2 (0x4000, 1721 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1722 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1723 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1724 CSKY_ISA_MP), 1725 OP16 ("stex", 1726 SOPCODE_INFO2 (0x5000, 1727 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1728 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1729 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1730 CSKY_ISA_MP), 1731 OP16 ("stex.w", 1732 SOPCODE_INFO2 (0x5000, 1733 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1734 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1735 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1736 CSKY_ISA_MP), 1737 OP16 ("stwex", 1738 SOPCODE_INFO2 (0x5000, 1739 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1740 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1741 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1742 CSKY_ISA_MP), 1743 OP16 ("omflip0", 1744 OPCODE_INFO2 (0x4000, 1745 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1746 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1747 CSKY_ISA_MAC), 1748 OP16 ("omflip1", 1749 OPCODE_INFO2 (0x4100, 1750 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1751 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1752 CSKY_ISA_MAC), 1753 OP16 ("omflip2", 1754 OPCODE_INFO2 (0x4200, 1755 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1756 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1757 CSKY_ISA_MAC), 1758 OP16 ("omflip3", 1759 OPCODE_INFO2 (0x4300, 1760 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1761 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1762 CSKY_ISA_MAC), 1763 OP16 ("muls", 1764 OPCODE_INFO2 (0x5000, 1765 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1766 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1767 CSKY_ISA_DSP), 1768 OP16 ("mulsa", 1769 OPCODE_INFO2 (0x5100, 1770 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1771 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1772 CSKY_ISA_DSP), 1773 OP16 ("mulss", 1774 OPCODE_INFO2 (0x5200, 1775 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1776 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1777 CSKY_ISA_DSP), 1778 OP16 ("mulu", 1779 OPCODE_INFO2 (0x5400, 1780 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1781 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1782 CSKY_ISA_DSP), 1783 OP16 ("mulua", 1784 OPCODE_INFO2 (0x5500, 1785 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1786 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1787 CSKY_ISA_DSP), 1788 OP16 ("mulus", 1789 OPCODE_INFO2 (0x5600, 1790 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1791 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1792 CSKY_ISA_DSP), 1793 OP16 ("vmulsh", 1794 OPCODE_INFO2 (0x5800, 1795 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1796 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1797 CSKY_ISA_DSP), 1798 OP16 ("vmulsha", 1799 OPCODE_INFO2 (0x5900, 1800 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1801 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1802 CSKY_ISA_DSP), 1803 OP16 ("vmulshs", 1804 OPCODE_INFO2 (0x5a00, 1805 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1806 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1807 CSKY_ISA_DSP), 1808 OP16 ("vmulsw", 1809 OPCODE_INFO2 (0x5c00, 1810 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1811 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1812 CSKY_ISA_DSP), 1813 OP16 ("vmulswa", 1814 OPCODE_INFO2 (0x5d00, 1815 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1816 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1817 CSKY_ISA_DSP), 1818 OP16 ("vmulsws", 1819 OPCODE_INFO2 (0x5e00, 1820 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1821 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1822 CSKY_ISA_DSP), 1823 OP16 ("movi", 1824 OPCODE_INFO2 (0x6000, 1825 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1826 (4_10, IMM7b, OPRND_SHIFT_0_BIT)), 1827 CSKYV1_ISA_E1), 1828 DOP16 ("mulsh", 1829 OPCODE_INFO3 (0x6800, 1830 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1831 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1832 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1833 OPCODE_INFO2 (0x6800, 1834 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1835 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1836 CSKYV1_ISA_E1), 1837 DOP16 ("mulsh.h", 1838 OPCODE_INFO3 (0x6800, 1839 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1840 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 1841 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1842 OPCODE_INFO2 (0x6800, 1843 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1844 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1845 CSKYV1_ISA_E1), 1846 OP16 ("mulsha", 1847 OPCODE_INFO2 (0x6900, 1848 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1849 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1850 CSKY_ISA_DSP), 1851 OP16 ("mulshs", 1852 OPCODE_INFO2 (0x6a00, 1853 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1854 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1855 CSKY_ISA_DSP), 1856 OP16 ("cprcr", 1857 OPCODE_INFO2 (0x6b00, 1858 (0_2, GREG0_7, OPRND_SHIFT_0_BIT), 1859 (3_7, CPCREG, OPRND_SHIFT_0_BIT)), 1860 CSKY_ISA_CP), 1861 OP16 ("mulsw", 1862 OPCODE_INFO2 (0x6c00, 1863 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1864 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1865 CSKY_ISA_DSP), 1866 OP16 ("mulswa", 1867 OPCODE_INFO2 (0x6d00, 1868 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1869 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1870 CSKY_ISA_DSP), 1871 OP16 ("mulsws", 1872 OPCODE_INFO2 (0x6e00, 1873 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1874 (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), 1875 CSKY_ISA_DSP), 1876 OP16 ("cpwcr", 1877 OPCODE_INFO2 (0x6f00, 1878 (0_2, GREG0_7, OPRND_SHIFT_0_BIT), 1879 (3_7, CPCREG, OPRND_SHIFT_0_BIT)), 1880 CSKY_ISA_CP), 1881 #undef _RELOC16 1882 #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4 1883 #undef _TRANSFER 1884 #define _TRANSFER 1 1885 OP16 ("jmpi", 1886 OPCODE_INFO1 (0x7000, 1887 (0_7, OFF8b, OPRND_SHIFT_2_BIT)), 1888 CSKYV1_ISA_E1), 1889 #undef _TRANSFER 1890 #define _TRANSFER 0 1891 OP16 ("jsri", 1892 OPCODE_INFO1 (0x7f00, 1893 (0_7, OFF8b, OPRND_SHIFT_2_BIT)), 1894 CSKYV1_ISA_E1), 1895 OP16_WITH_WORK ("lrw", 1896 OPCODE_INFO2 (0x7000, 1897 (8_11, REGnsplr, OPRND_SHIFT_0_BIT), 1898 (0_7, CONSTANT, OPRND_SHIFT_2_BIT)), 1899 CSKYV1_ISA_E1, 1900 v1_work_lrw), 1901 #undef _RELOC16 1902 #define _RELOC16 0 1903 DOP16 ("ld.w", 1904 SOPCODE_INFO2 (0x8000, 1905 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1906 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1907 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1908 OPCODE_INFO2 (0x8000, 1909 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1910 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1911 CSKYV1_ISA_E1), 1912 DOP16 ("ldw", 1913 SOPCODE_INFO2 (0x8000, 1914 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1915 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1916 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1917 OPCODE_INFO2 (0x8000, 1918 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1919 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1920 CSKYV1_ISA_E1), 1921 DOP16 ("ld", 1922 SOPCODE_INFO2 (0x8000, 1923 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1924 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1925 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1926 OPCODE_INFO2 (0x8000, 1927 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1928 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1929 CSKYV1_ISA_E1), 1930 DOP16 ("st.w", 1931 SOPCODE_INFO2 (0x9000, 1932 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1933 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1934 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1935 OPCODE_INFO2 (0x9000, 1936 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1937 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1938 CSKYV1_ISA_E1), 1939 DOP16 ("stw", 1940 SOPCODE_INFO2 (0x9000, 1941 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1942 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1943 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1944 OPCODE_INFO2 (0x9000, 1945 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1946 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1947 CSKYV1_ISA_E1), 1948 DOP16 ("st", 1949 SOPCODE_INFO2 (0x9000, 1950 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1951 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1952 (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), 1953 OPCODE_INFO2 (0x9000, 1954 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1955 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1956 CSKYV1_ISA_E1), 1957 DOP16 ("ld.b", 1958 SOPCODE_INFO2 (0xa000, 1959 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1960 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1961 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1962 OPCODE_INFO2 (0xa000, 1963 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1964 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1965 CSKYV1_ISA_E1), 1966 DOP16 ("ldb", 1967 SOPCODE_INFO2 (0xa000, 1968 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1969 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1970 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1971 OPCODE_INFO2 (0xa000, 1972 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1973 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1974 CSKYV1_ISA_E1), 1975 DOP16 ("st.b", 1976 SOPCODE_INFO2 (0xb000, 1977 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1978 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1979 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1980 OPCODE_INFO2 (0xb000, 1981 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1982 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1983 CSKYV1_ISA_E1), 1984 DOP16 ("stb", 1985 SOPCODE_INFO2 (0xb000, 1986 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1987 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1988 (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), 1989 OPCODE_INFO2 (0xb000, 1990 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1991 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 1992 CSKYV1_ISA_E1), 1993 DOP16 ("ld.h", 1994 SOPCODE_INFO2 (0xc000, 1995 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 1996 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 1997 (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), 1998 OPCODE_INFO2 (0xc000, 1999 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2000 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 2001 CSKYV1_ISA_E1), 2002 DOP16 ("ldh", 2003 SOPCODE_INFO2 (0xc000, 2004 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2005 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2006 (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), 2007 OPCODE_INFO2 (0xc000, 2008 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2009 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 2010 CSKYV1_ISA_E1), 2011 DOP16 ("st.h", 2012 SOPCODE_INFO2 (0xd000, 2013 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2014 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2015 (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), 2016 OPCODE_INFO2 (0xd000, 2017 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2018 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 2019 CSKYV1_ISA_E1), 2020 DOP16 ("sth", 2021 SOPCODE_INFO2 (0xd000, 2022 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2023 BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2024 (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), 2025 OPCODE_INFO2 (0xd000, 2026 (8_11, GREG0_15, OPRND_SHIFT_0_BIT), 2027 (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 2028 CSKYV1_ISA_E1), 2029 2030 #undef _RELOC16 2031 #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2 2032 OP16 ("bt", 2033 OPCODE_INFO1 (0xe000, 2034 (0_10, OFF11b, OPRND_SHIFT_1_BIT)), 2035 CSKYV1_ISA_E1), 2036 OP16 ("bf", 2037 OPCODE_INFO1 (0xe800, 2038 (0_10, OFF11b, OPRND_SHIFT_1_BIT)), 2039 CSKYV1_ISA_E1), 2040 #undef _TRANSFER 2041 #define _TRANSFER 1 2042 OP16 ("br", 2043 OPCODE_INFO1 (0xf000, 2044 (0_10, OFF11b, OPRND_SHIFT_1_BIT)), 2045 CSKYV1_ISA_E1), 2046 #undef _TRANSFER 2047 #define _TRANSFER 0 2048 OP16 ("bsr", 2049 OPCODE_INFO1 (0xf800, 2050 (0_10, OFF11b, OPRND_SHIFT_1_BIT)), 2051 CSKYV1_ISA_E1), 2052 #undef _RELOC16 2053 #define _RELOC16 0 2054 2055 #undef _RELAX 2056 #define _RELAX 1 2057 OP16 ("jbt", 2058 OPCODE_INFO1 (0xe000, 2059 (0_10, JBTF, OPRND_SHIFT_0_BIT)), 2060 CSKYV1_ISA_E1), 2061 OP16 ("jbf", 2062 OPCODE_INFO1 (0xe800, 2063 (0_10, JBTF, OPRND_SHIFT_0_BIT)), 2064 CSKYV1_ISA_E1), 2065 #undef _TRANSFER 2066 #define _TRANSFER 1 2067 OP16 ("jbr", 2068 OPCODE_INFO1 (0xf000, 2069 (0_10, JBR, OPRND_SHIFT_0_BIT)), 2070 CSKYV1_ISA_E1), 2071 #undef _TRANSFER 2072 #define _TRANSFER 0 2073 #undef _RELAX 2074 #define _RELAX 0 2075 2076 OP16_WITH_WORK ("jbsr", 2077 OPCODE_INFO1 (0xf800, 2078 (0_10, JBSR, OPRND_SHIFT_0_BIT)), 2079 CSKYV1_ISA_E1, 2080 v1_work_jbsr), 2081 2082 /* The following are aliases for other instructions. */ 2083 /* rts -> jmp r15. */ 2084 #undef _TRANSFER 2085 #define _TRANSFER 2 2086 OP16 ("rts", 2087 OPCODE_INFO0 (0x00CF), 2088 CSKYV1_ISA_E1), 2089 OP16 ("rte", 2090 OPCODE_INFO0 (0x0002), 2091 CSKYV1_ISA_E1), 2092 OP16 ("rfe", 2093 OPCODE_INFO0 (0x0002), 2094 CSKYV1_ISA_E1), 2095 #undef _TRANSFER 2096 #define _TRANSFER 0 2097 2098 /* cmphs r0,r0 */ 2099 OP16 ("setc", 2100 OPCODE_INFO0 (0x0c00), 2101 CSKYV1_ISA_E1), 2102 /* cmpne r0,r0 */ 2103 OP16 ("clrc", 2104 OPCODE_INFO0 (0x0f00), 2105 CSKYV1_ISA_E1), 2106 /* cmplti rd,1 */ 2107 OP16 ("tstle", 2108 OPCODE_INFO1 (0x2200, 2109 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 2110 CSKYV1_ISA_E1), 2111 /* cmplei rd,X -> cmplti rd,X+1 */ 2112 OP16 ("cmplei", 2113 OPCODE_INFO2 (0x2200, 2114 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2115 (4_8, IMM5b, OPRND_SHIFT_0_BIT)), 2116 CSKYV1_ISA_E1), 2117 /* rsubi rd,0 */ 2118 OP16 ("neg", 2119 OPCODE_INFO1 (0x2800, 2120 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 2121 CSKYV1_ISA_E1), 2122 /* cmpnei rd,0. */ 2123 OP16 ("tstne", 2124 OPCODE_INFO1 (0x2a00, 2125 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 2126 CSKYV1_ISA_E1), 2127 /* btsti rx,31. */ 2128 OP16 ("tstlt", 2129 OPCODE_INFO1 (0x37f0, 2130 (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), 2131 CSKYV1_ISA_E1), 2132 /* bclri rx,log2(imm). */ 2133 OP16 ("mclri", 2134 OPCODE_INFO2 (0x3000, 2135 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2136 (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), 2137 CSKYV1_ISA_E1), 2138 /* bgeni rx,log2(imm). */ 2139 OP16 ("mgeni", 2140 OPCODE_INFO2 (0x3200, 2141 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2142 (4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)), 2143 CSKYV1_ISA_E1), 2144 /* bseti rx,log2(imm). */ 2145 OP16 ("mseti", 2146 OPCODE_INFO2 (0x3400, 2147 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2148 (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), 2149 CSKYV1_ISA_E1), 2150 /* btsti rx,log2(imm). */ 2151 OP16 ("mtsti", 2152 OPCODE_INFO2 (0x3600, 2153 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2154 (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), 2155 CSKYV1_ISA_E1), 2156 OP16 ("rori", 2157 OPCODE_INFO2 (0x3800, 2158 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2159 (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 2160 CSKYV1_ISA_E1), 2161 OP16 ("rotri", 2162 OPCODE_INFO2 (0x3800, 2163 (0_3, GREG0_15, OPRND_SHIFT_0_BIT), 2164 (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 2165 CSKYV1_ISA_E1), 2166 /* mov r0, r0. */ 2167 OP16 ("nop", 2168 OPCODE_INFO0 (0x1200), 2169 CSKYV1_ISA_E1), 2170 2171 /* Float instruction with work. */ 2172 OP16_WITH_WORK ("fabss", 2173 OPCODE_INFO3 (0xffe04400, 2174 (5_9, FREG, OPRND_SHIFT_0_BIT), 2175 (0_4, FREG, OPRND_SHIFT_0_BIT), 2176 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2177 CSKY_ISA_FLOAT_E1, 2178 v1_work_fpu_fo), 2179 OP16_WITH_WORK ("fnegs", 2180 OPCODE_INFO3 (0xffe04c00, 2181 (5_9, FREG, OPRND_SHIFT_0_BIT), 2182 (0_4, FREG, OPRND_SHIFT_0_BIT), 2183 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2184 CSKY_ISA_FLOAT_E1, 2185 v1_work_fpu_fo), 2186 OP16_WITH_WORK ("fsqrts", 2187 OPCODE_INFO3 (0xffe05400, 2188 (5_9, FREG, OPRND_SHIFT_0_BIT), 2189 (0_4, FREG, OPRND_SHIFT_0_BIT), 2190 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2191 CSKY_ISA_FLOAT_E1, 2192 v1_work_fpu_fo), 2193 OP16_WITH_WORK ("frecips", 2194 OPCODE_INFO3 (0xffe05c00, 2195 (5_9, FREG, OPRND_SHIFT_0_BIT), 2196 (0_4, FREG, OPRND_SHIFT_0_BIT), 2197 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2198 CSKY_ISA_FLOAT_E1, 2199 v1_work_fpu_fo), 2200 OP16_WITH_WORK ("fadds", 2201 OPCODE_INFO4 (0xffe38000, 2202 (5_9, FREG, OPRND_SHIFT_0_BIT), 2203 (0_4, FREG, OPRND_SHIFT_0_BIT), 2204 (10_14, FREG, OPRND_SHIFT_0_BIT), 2205 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2206 CSKY_ISA_FLOAT_E1, 2207 v1_work_fpu_fo), 2208 OP16_WITH_WORK ("fsubs", 2209 OPCODE_INFO4 (0xffe48000, 2210 (5_9, FREG, OPRND_SHIFT_0_BIT), 2211 (0_4, FREG, OPRND_SHIFT_0_BIT), 2212 (10_14, FREG, OPRND_SHIFT_0_BIT), 2213 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2214 CSKY_ISA_FLOAT_E1, v1_work_fpu_fo), 2215 OP16_WITH_WORK ("fmacs", 2216 OPCODE_INFO4 (0xffe58000, 2217 (5_9, FREG, OPRND_SHIFT_0_BIT), 2218 (0_4, FREG, OPRND_SHIFT_0_BIT), 2219 (10_14, FREG, OPRND_SHIFT_0_BIT), 2220 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2221 CSKY_ISA_FLOAT_E1, 2222 v1_work_fpu_fo), 2223 OP16_WITH_WORK ("fmscs", 2224 OPCODE_INFO4 (0xffe68000, 2225 (5_9, FREG, OPRND_SHIFT_0_BIT), 2226 (0_4, FREG, OPRND_SHIFT_0_BIT), 2227 (10_14, FREG, OPRND_SHIFT_0_BIT), 2228 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2229 CSKY_ISA_FLOAT_E1, 2230 v1_work_fpu_fo), 2231 OP16_WITH_WORK ("fmuls", 2232 OPCODE_INFO4 (0xffe78000, 2233 (5_9, FREG, OPRND_SHIFT_0_BIT), 2234 (0_4, FREG, OPRND_SHIFT_0_BIT), 2235 (10_14, FREG, OPRND_SHIFT_0_BIT), 2236 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2237 CSKY_ISA_FLOAT_E1, 2238 v1_work_fpu_fo), 2239 OP16_WITH_WORK ("fdivs", 2240 OPCODE_INFO4 (0xffe88000, 2241 (5_9, FREG, OPRND_SHIFT_0_BIT), 2242 (0_4, FREG, OPRND_SHIFT_0_BIT), 2243 (10_14, FREG, OPRND_SHIFT_0_BIT), 2244 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2245 CSKY_ISA_FLOAT_E1, 2246 v1_work_fpu_fo), 2247 OP16_WITH_WORK ("fnmacs", 2248 OPCODE_INFO4 (0xffe98000, 2249 (5_9, FREG, OPRND_SHIFT_0_BIT), 2250 (0_4, FREG, OPRND_SHIFT_0_BIT), 2251 (10_14, FREG, OPRND_SHIFT_0_BIT), 2252 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2253 CSKY_ISA_FLOAT_E1, 2254 v1_work_fpu_fo), 2255 OP16_WITH_WORK ("fnmscs", 2256 OPCODE_INFO4 (0xffea8000, 2257 (5_9, FREG, OPRND_SHIFT_0_BIT), 2258 (0_4, FREG, OPRND_SHIFT_0_BIT), 2259 (10_14, FREG, OPRND_SHIFT_0_BIT), 2260 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2261 CSKY_ISA_FLOAT_E1, 2262 v1_work_fpu_fo), 2263 OP16_WITH_WORK ("fnmuls", 2264 OPCODE_INFO4 (0xffeb8000, 2265 (5_9, FREG, OPRND_SHIFT_0_BIT), 2266 (0_4, FREG, OPRND_SHIFT_0_BIT), 2267 (10_14, FREG, OPRND_SHIFT_0_BIT), 2268 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2269 CSKY_ISA_FLOAT_E1, 2270 v1_work_fpu_fo), 2271 OP16_WITH_WORK ("fabsd", 2272 OPCODE_INFO3 (0xffe04000, 2273 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2274 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2275 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2276 CSKY_ISA_FLOAT_E1, 2277 v1_work_fpu_fo), 2278 OP16_WITH_WORK ("fnegd", 2279 OPCODE_INFO3 (0xffe04800, 2280 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2281 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2282 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2283 CSKY_ISA_FLOAT_E1, 2284 v1_work_fpu_fo), 2285 OP16_WITH_WORK ("fsqrtd", 2286 OPCODE_INFO3 (0xffe05000, 2287 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2288 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2289 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2290 CSKY_ISA_FLOAT_E1, 2291 v1_work_fpu_fo), 2292 OP16_WITH_WORK ("frecipd", 2293 OPCODE_INFO3 (0xffe05800, 2294 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2295 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2296 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2297 CSKY_ISA_FLOAT_E1, 2298 v1_work_fpu_fo), 2299 OP16_WITH_WORK ("faddd", 2300 OPCODE_INFO4 (0xffe30000, 2301 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2302 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2303 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2304 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2305 CSKY_ISA_FLOAT_E1, 2306 v1_work_fpu_fo), 2307 OP16_WITH_WORK ("fsubd", 2308 OPCODE_INFO4 (0xffe40000, 2309 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2310 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2311 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2312 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2313 CSKY_ISA_FLOAT_E1, 2314 v1_work_fpu_fo), 2315 OP16_WITH_WORK ("fmacd", 2316 OPCODE_INFO4 (0xffe50000, 2317 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2318 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2319 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2320 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2321 CSKY_ISA_FLOAT_E1, 2322 v1_work_fpu_fo), 2323 OP16_WITH_WORK ("fmscd", 2324 OPCODE_INFO4 (0xffe60000, 2325 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2326 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2327 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2328 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2329 CSKY_ISA_FLOAT_E1, 2330 v1_work_fpu_fo), 2331 OP16_WITH_WORK ("fmuld", 2332 OPCODE_INFO4 (0xffe70000, 2333 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2334 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2335 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2336 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2337 CSKY_ISA_FLOAT_E1, 2338 v1_work_fpu_fo), 2339 OP16_WITH_WORK ("fdivd", 2340 OPCODE_INFO4 (0xffe80000, 2341 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2342 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2343 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2344 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2345 CSKY_ISA_FLOAT_E1, 2346 v1_work_fpu_fo), 2347 OP16_WITH_WORK ("fnmacd", 2348 OPCODE_INFO4 (0xffe90000, 2349 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2350 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2351 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2352 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2353 CSKY_ISA_FLOAT_E1, 2354 v1_work_fpu_fo), 2355 OP16_WITH_WORK ("fnmscd", 2356 OPCODE_INFO4 (0xffea0000, 2357 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2358 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2359 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2360 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2361 CSKY_ISA_FLOAT_E1, 2362 v1_work_fpu_fo), 2363 OP16_WITH_WORK ("fnmuld", 2364 OPCODE_INFO4 (0xffeb0000, 2365 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2366 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2367 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2368 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2369 CSKY_ISA_FLOAT_E1, 2370 v1_work_fpu_fo), 2371 OP16_WITH_WORK ("fabsm", 2372 OPCODE_INFO3 (0xffe06000, 2373 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2374 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2375 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2376 CSKY_ISA_FLOAT_E1, 2377 v1_work_fpu_fo), 2378 OP16_WITH_WORK ("fnegm", 2379 OPCODE_INFO3 (0xffe06400, 2380 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2381 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2382 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2383 CSKY_ISA_FLOAT_E1, 2384 v1_work_fpu_fo), 2385 OP16_WITH_WORK ("faddm", 2386 OPCODE_INFO4 (0xffec0000, 2387 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2388 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2389 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2390 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2391 CSKY_ISA_FLOAT_E1, 2392 v1_work_fpu_fo), 2393 OP16_WITH_WORK ("fsubm", 2394 OPCODE_INFO4 (0xffec8000, 2395 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2396 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2397 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2398 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2399 CSKY_ISA_FLOAT_E1, 2400 v1_work_fpu_fo), 2401 OP16_WITH_WORK ("fmacm", 2402 OPCODE_INFO4 (0xffed8000, 2403 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2404 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2405 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2406 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2407 CSKY_ISA_FLOAT_E1, 2408 v1_work_fpu_fo), 2409 OP16_WITH_WORK ("fmscm", 2410 OPCODE_INFO4 (0xffee0000, 2411 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2412 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2413 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2414 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2415 CSKY_ISA_FLOAT_E1, 2416 v1_work_fpu_fo), 2417 OP16_WITH_WORK ("fmulm", 2418 OPCODE_INFO4 (0xffed0000, 2419 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2420 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2421 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2422 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2423 CSKY_ISA_FLOAT_E1, 2424 v1_work_fpu_fo), 2425 OP16_WITH_WORK ("fnmacm", 2426 OPCODE_INFO4 (0xffee8000, 2427 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2428 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2429 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2430 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2431 CSKY_ISA_FLOAT_E1, 2432 v1_work_fpu_fo), 2433 OP16_WITH_WORK ("fnmscm", 2434 OPCODE_INFO4 (0xffef0000, 2435 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2436 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2437 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2438 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2439 CSKY_ISA_FLOAT_E1, 2440 v1_work_fpu_fo), 2441 OP16_WITH_WORK ("fnmulm", 2442 OPCODE_INFO4 (0xffef8000, 2443 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2444 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2445 (10_14, FEREG, OPRND_SHIFT_0_BIT), 2446 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2447 CSKY_ISA_FLOAT_E1, 2448 v1_work_fpu_fo), 2449 OP16_WITH_WORK ("fcmphsd", 2450 OPCODE_INFO3 (0xffe00800, 2451 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2452 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2453 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2454 CSKY_ISA_FLOAT_E1, 2455 v1_work_fpu_fo_fc), 2456 OP16_WITH_WORK ("fcmpltd", 2457 OPCODE_INFO3 (0xffe00c00, 2458 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2459 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2460 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2461 CSKY_ISA_FLOAT_E1, 2462 v1_work_fpu_fo_fc), 2463 OP16_WITH_WORK ("fcmpned", 2464 OPCODE_INFO3 (0xffe01000, 2465 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2466 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2467 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2468 CSKY_ISA_FLOAT_E1, 2469 v1_work_fpu_fo_fc), 2470 OP16_WITH_WORK ("fcmpuod", 2471 OPCODE_INFO3 (0xffe01400, 2472 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2473 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2474 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2475 CSKY_ISA_FLOAT_E1, 2476 v1_work_fpu_fo_fc), 2477 OP16_WITH_WORK ("fcmphss", 2478 OPCODE_INFO3 (0xffe01800, 2479 (0_4, FREG, OPRND_SHIFT_0_BIT), 2480 (5_9, FREG, OPRND_SHIFT_0_BIT), 2481 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2482 CSKY_ISA_FLOAT_E1, 2483 v1_work_fpu_fo_fc), 2484 OP16_WITH_WORK ("fcmplts", 2485 OPCODE_INFO3 (0xffe01c00, 2486 (0_4, FREG, OPRND_SHIFT_0_BIT), 2487 (5_9, FREG, OPRND_SHIFT_0_BIT), 2488 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2489 CSKY_ISA_FLOAT_E1, 2490 v1_work_fpu_fo_fc), 2491 OP16_WITH_WORK ("fcmpnes", 2492 OPCODE_INFO3 (0xffe02000, 2493 (0_4, FREG, OPRND_SHIFT_0_BIT), 2494 (5_9, FREG, OPRND_SHIFT_0_BIT), 2495 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2496 CSKY_ISA_FLOAT_E1, 2497 v1_work_fpu_fo_fc), 2498 OP16_WITH_WORK ("fcmpuos", 2499 OPCODE_INFO3 (0xffe02400, 2500 (0_4, FREG, OPRND_SHIFT_0_BIT), 2501 (5_9, FREG, OPRND_SHIFT_0_BIT), 2502 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2503 CSKY_ISA_FLOAT_E1, 2504 v1_work_fpu_fo_fc), 2505 OP16_WITH_WORK ("fcmpzhsd", 2506 OPCODE_INFO2 (0xffe00400, 2507 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2508 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2509 CSKY_ISA_FLOAT_E1, 2510 v1_work_fpu_fo_fc), 2511 OP16_WITH_WORK ("fcmpzltd", 2512 OPCODE_INFO2 (0xffe00480, 2513 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2514 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2515 CSKY_ISA_FLOAT_E1, 2516 v1_work_fpu_fo_fc), 2517 OP16_WITH_WORK ("fcmpzned", 2518 OPCODE_INFO2 (0xffe00500, 2519 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2520 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2521 CSKY_ISA_FLOAT_E1, 2522 v1_work_fpu_fo_fc), 2523 OP16_WITH_WORK ("fcmpzuod", 2524 OPCODE_INFO2 (0xffe00580, 2525 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2526 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2527 CSKY_ISA_FLOAT_E1, 2528 v1_work_fpu_fo_fc), 2529 OP16_WITH_WORK ("fcmpzhss", 2530 OPCODE_INFO2 (0xffe00600, 2531 (0_4, FREG, OPRND_SHIFT_0_BIT), 2532 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2533 CSKY_ISA_FLOAT_E1, 2534 v1_work_fpu_fo_fc), 2535 OP16_WITH_WORK ("fcmpzlts", 2536 OPCODE_INFO2 (0xffe00680, 2537 (0_4, FREG, OPRND_SHIFT_0_BIT), 2538 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2539 CSKY_ISA_FLOAT_E1, 2540 v1_work_fpu_fo_fc), 2541 OP16_WITH_WORK ("fcmpznes", 2542 OPCODE_INFO2 (0xffe00700, 2543 (0_4, FREG, OPRND_SHIFT_0_BIT), 2544 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2545 CSKY_ISA_FLOAT_E1, 2546 v1_work_fpu_fo_fc), 2547 OP16_WITH_WORK ("fcmpzuos", 2548 OPCODE_INFO2 (0xffe00780, 2549 (0_4, FREG, OPRND_SHIFT_0_BIT), 2550 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2551 CSKY_ISA_FLOAT_E1, 2552 v1_work_fpu_fo_fc), 2553 OP16_WITH_WORK ("fstod", 2554 OPCODE_INFO3 (0xffe02800, 2555 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2556 (0_4, FREG, OPRND_SHIFT_0_BIT), 2557 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2558 CSKY_ISA_FLOAT_E1, 2559 v1_work_fpu_fo), 2560 OP16_WITH_WORK ("fdtos", 2561 OPCODE_INFO3 (0xffe02c00, 2562 (5_9, FREG, OPRND_SHIFT_0_BIT), 2563 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2564 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2565 CSKY_ISA_FLOAT_E1, 2566 v1_work_fpu_fo), 2567 OP16_WITH_WORK ("fsitos", 2568 OPCODE_INFO3 (0xffe03400, 2569 (5_9, FREG, OPRND_SHIFT_0_BIT), 2570 (0_4, FREG, OPRND_SHIFT_0_BIT), 2571 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2572 CSKY_ISA_FLOAT_E1, 2573 v1_work_fpu_fo), 2574 OP16_WITH_WORK ("fsitod", 2575 OPCODE_INFO3 (0xffe03000, 2576 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2577 (0_4, FREG, OPRND_SHIFT_0_BIT), 2578 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2579 CSKY_ISA_FLOAT_E1, 2580 v1_work_fpu_fo), 2581 OP16_WITH_WORK ("fuitos", 2582 OPCODE_INFO3 (0xffe03c00, 2583 (5_9, FREG, OPRND_SHIFT_0_BIT), 2584 (0_4, FREG, OPRND_SHIFT_0_BIT), 2585 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2586 CSKY_ISA_FLOAT_E1, 2587 v1_work_fpu_fo), 2588 OP16_WITH_WORK ("fuitod", 2589 OPCODE_INFO3 (0xffe03800, 2590 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2591 (0_4, FREG, OPRND_SHIFT_0_BIT), 2592 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2593 CSKY_ISA_FLOAT_E1, 2594 v1_work_fpu_fo), 2595 OP16_WITH_WORK ("fstosi", 2596 OPCODE_INFO4 (0xffe10000, 2597 (5_9, FREG, OPRND_SHIFT_0_BIT), 2598 (0_4, FREG, OPRND_SHIFT_0_BIT), 2599 (13_17, RM, OPRND_SHIFT_0_BIT), 2600 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2601 CSKY_ISA_FLOAT_E1, 2602 v1_work_fpu_fo), 2603 OP16_WITH_WORK ("fdtosi", 2604 OPCODE_INFO4 (0xffe08000, 2605 (5_9, FREG, OPRND_SHIFT_0_BIT), 2606 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2607 (13_17, RM, OPRND_SHIFT_0_BIT), 2608 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2609 CSKY_ISA_FLOAT_E1, 2610 v1_work_fpu_fo), 2611 OP16_WITH_WORK ("fstoui", 2612 OPCODE_INFO4 (0xffe20000, 2613 (5_9, FREG, OPRND_SHIFT_0_BIT), 2614 (0_4, FREG, OPRND_SHIFT_0_BIT), 2615 (13_17, RM, OPRND_SHIFT_0_BIT), 2616 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2617 CSKY_ISA_FLOAT_E1, 2618 v1_work_fpu_fo), 2619 OP16_WITH_WORK ("fdtoui", 2620 OPCODE_INFO4 (0xffe18000, 2621 (5_9, FREG, OPRND_SHIFT_0_BIT), 2622 (0_4, FEREG, OPRND_SHIFT_0_BIT), 2623 (13_17, RM, OPRND_SHIFT_0_BIT), 2624 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2625 CSKY_ISA_FLOAT_E1, 2626 v1_work_fpu_fo), 2627 OP16_WITH_WORK ("fmovd", 2628 OPCODE_INFO3 (0xffe06800, 2629 (5_9, FEREG, OPRND_SHIFT_0_BIT), 2630 (0_4, FREG, OPRND_SHIFT_0_BIT), 2631 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2632 CSKY_ISA_FLOAT_E1, 2633 v1_work_fpu_fo), 2634 OP16_WITH_WORK ("fmovs", 2635 OPCODE_INFO3 (0xffe06c00, 2636 (5_9, FREG, OPRND_SHIFT_0_BIT), 2637 (0_4, FREG, OPRND_SHIFT_0_BIT), 2638 (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), 2639 CSKY_ISA_FLOAT_E1, 2640 v1_work_fpu_fo), 2641 OP16_WITH_WORK ("fmts", 2642 OPCODE_INFO2 (0x00000000, 2643 (NONE, GREG0_15, OPRND_SHIFT_0_BIT), 2644 (NONE, FREG, OPRND_SHIFT_0_BIT)), 2645 CSKY_ISA_FLOAT_E1, 2646 v1_work_fpu_write), 2647 OP16_WITH_WORK ("fmfs", 2648 OPCODE_INFO2 (0x00000000, 2649 (NONE, GREG0_15, OPRND_SHIFT_0_BIT), 2650 (NONE, FREG, OPRND_SHIFT_0_BIT)), 2651 CSKY_ISA_FLOAT_E1, 2652 v1_work_fpu_read), 2653 OP16_WITH_WORK ("fmtd", 2654 OPCODE_INFO2 (0x00000000, 2655 (NONE, GREG0_15, OPRND_SHIFT_0_BIT), 2656 (NONE, FEREG, OPRND_SHIFT_0_BIT)), 2657 CSKY_ISA_FLOAT_E1, 2658 v1_work_fpu_writed), 2659 OP16_WITH_WORK ("fmfd", 2660 OPCODE_INFO2 (0x00000000, 2661 (NONE, GREG0_15, OPRND_SHIFT_0_BIT), 2662 (NONE, FEREG, OPRND_SHIFT_0_BIT)), 2663 CSKY_ISA_FLOAT_E1, 2664 v1_work_fpu_readd), 2665 {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} 2666 }; 2667 2668 #undef _TRANSFER 2669 #undef _RELOC16 2670 #undef _RELOC32 2671 #undef _RELAX 2672 2673 /* C-SKY v2 opcodes. */ 2674 const struct csky_opcode csky_v2_opcodes[] = 2675 { 2676 #define _TRANSFER 0 2677 #define _RELOC16 0 2678 #define _RELOC32 0 2679 #define _RELAX 0 2680 OP16 ("bkpt", 2681 OPCODE_INFO0 (0x0000), 2682 CSKYV2_ISA_E1), 2683 OP16_WITH_WORK ("nie", 2684 OPCODE_INFO0 (0x1460), 2685 CSKYV2_ISA_E1, 2686 v2_work_istack), 2687 OP16_WITH_WORK ("nir", 2688 OPCODE_INFO0 (0x1461), 2689 CSKYV2_ISA_E1, 2690 v2_work_istack), 2691 OP16_WITH_WORK ("ipush", 2692 OPCODE_INFO0 (0x1462), 2693 CSKYV2_ISA_E1, 2694 v2_work_istack), 2695 OP16_WITH_WORK ("ipop", 2696 OPCODE_INFO0 (0x1463), 2697 CSKYV2_ISA_E1, 2698 v2_work_istack), 2699 OP16 ("bpop.h", 2700 OPCODE_INFO1 (0x14a0, 2701 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 2702 CSKY_ISA_JAVA), 2703 OP16 ("bpop.w", 2704 OPCODE_INFO1 (0x14a2, 2705 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 2706 CSKY_ISA_JAVA), 2707 OP16 ("bpush.h", 2708 OPCODE_INFO1 (0x14e0, 2709 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 2710 CSKY_ISA_JAVA), 2711 OP16 ("bpush.w", 2712 OPCODE_INFO1 (0x14e2, 2713 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 2714 CSKY_ISA_JAVA), 2715 OP32 ("bmset", 2716 OPCODE_INFO0 (0xc0001020), 2717 CSKY_ISA_JAVA), 2718 OP32 ("bmclr", 2719 OPCODE_INFO0 (0xc0001420), 2720 CSKY_ISA_JAVA), 2721 OP32 ("sce", 2722 OPCODE_INFO1 (0xc0001820, 2723 (21_24, IMM4b, OPRND_SHIFT_0_BIT)), 2724 CSKY_ISA_MP), 2725 OP32 ("trap", 2726 OPCODE_INFO1 (0xc0002020, 2727 (10_11, IMM2b, OPRND_SHIFT_0_BIT)), 2728 CSKYV2_ISA_E1), 2729 /* Secure/nsecure world switch. */ 2730 OP32 ("wsc", 2731 OPCODE_INFO0 (0xc0003c20), 2732 CSKY_ISA_TRUST), 2733 OP32 ("mtcr", 2734 OPCODE_INFO2 (0xc0006420, 2735 (16_20, AREG, OPRND_SHIFT_0_BIT), 2736 (0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), 2737 CSKYV2_ISA_E1), 2738 OP32 ("mfcr", 2739 OPCODE_INFO2 (0xc0006020, 2740 (0_4, AREG, OPRND_SHIFT_0_BIT), 2741 (16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), 2742 CSKYV2_ISA_E1), 2743 #undef _TRANSFER 2744 #define _TRANSFER 2 2745 OP32 ("rte", 2746 OPCODE_INFO0 (0xc0004020), 2747 CSKYV2_ISA_E1), 2748 OP32 ("rfi", 2749 OPCODE_INFO0 (0xc0004420), 2750 CSKYV2_ISA_2E3), 2751 #undef _TRANSFER 2752 #define _TRANSFER 0 2753 OP32 ("stop", 2754 OPCODE_INFO0 (0xc0004820), 2755 CSKYV2_ISA_E1), 2756 OP32 ("wait", 2757 OPCODE_INFO0 (0xc0004c20), 2758 CSKYV2_ISA_E1), 2759 OP32 ("doze", 2760 OPCODE_INFO0 (0xc0005020), 2761 CSKYV2_ISA_E1), 2762 OP32 ("we", 2763 OPCODE_INFO0 (0xc0005420), 2764 CSKY_ISA_MP_1E2), 2765 OP32 ("se", 2766 OPCODE_INFO0 (0xc0005820), 2767 CSKY_ISA_MP_1E2), 2768 OP32 ("psrclr", 2769 OPCODE_INFO_LIST (0xc0007020, 2770 (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), 2771 CSKYV2_ISA_E1), 2772 OP32 ("psrset", 2773 OPCODE_INFO_LIST (0xc0007420, 2774 (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), 2775 CSKYV2_ISA_E1), 2776 DOP32 ("abs", 2777 OPCODE_INFO2 (0xc4000200, 2778 (0_4, AREG, OPRND_SHIFT_0_BIT), 2779 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2780 OPCODE_INFO1 (0xc4000200, 2781 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 2782 CSKYV2_ISA_2E3), 2783 OP32 ("mvc", 2784 OPCODE_INFO1 (0xc4000500, 2785 (0_4, AREG, OPRND_SHIFT_0_BIT)), 2786 CSKYV2_ISA_1E2), 2787 OP32 ("incf", 2788 OPCODE_INFO3 (0xc4000c20, 2789 (21_25, AREG, OPRND_SHIFT_0_BIT), 2790 (16_20, AREG, OPRND_SHIFT_0_BIT), 2791 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 2792 CSKYV2_ISA_1E2), 2793 OP32 ("movf", 2794 OPCODE_INFO2 (0xc4000c20, 2795 (21_25, AREG, OPRND_SHIFT_0_BIT), 2796 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2797 CSKYV2_ISA_1E2), 2798 OP32 ("inct", 2799 OPCODE_INFO3 (0xc4000c40, 2800 (21_25, AREG, OPRND_SHIFT_0_BIT), 2801 (16_20, AREG, OPRND_SHIFT_0_BIT), 2802 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 2803 CSKYV2_ISA_1E2), 2804 OP32 ("movt", 2805 OPCODE_INFO2 (0xc4000c40, 2806 (21_25, AREG, OPRND_SHIFT_0_BIT), 2807 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2808 CSKYV2_ISA_1E2), 2809 OP32 ("decf", 2810 OPCODE_INFO3 (0xc4000c80, 2811 (21_25, AREG, OPRND_SHIFT_0_BIT), 2812 (16_20, AREG, OPRND_SHIFT_0_BIT), 2813 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 2814 CSKYV2_ISA_1E2), 2815 OP32 ("dect", 2816 OPCODE_INFO3 (0xc4000d00, 2817 (21_25, AREG, OPRND_SHIFT_0_BIT), 2818 (16_20, AREG, OPRND_SHIFT_0_BIT), 2819 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 2820 CSKYV2_ISA_1E2), 2821 OP32 ("decgt", 2822 OPCODE_INFO3 (0xc4001020, 2823 (0_4, AREG, OPRND_SHIFT_0_BIT), 2824 (16_20, AREG, OPRND_SHIFT_0_BIT), 2825 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 2826 CSKYV2_ISA_2E3), 2827 OP32 ("declt", 2828 OPCODE_INFO3 (0xc4001040, 2829 (0_4, AREG, OPRND_SHIFT_0_BIT), 2830 (16_20, AREG, OPRND_SHIFT_0_BIT), 2831 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 2832 CSKYV2_ISA_2E3), 2833 OP32 ("decne", 2834 OPCODE_INFO3 (0xc4001080, 2835 (0_4, AREG, OPRND_SHIFT_0_BIT), 2836 (16_20, AREG, OPRND_SHIFT_0_BIT), 2837 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 2838 CSKYV2_ISA_2E3), 2839 OP32 ("clrf", 2840 OPCODE_INFO1 (0xc4002c20, 2841 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2842 CSKYV2_ISA_2E3), 2843 OP32 ("clrt", 2844 OPCODE_INFO1 (0xc4002c40, 2845 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2846 CSKYV2_ISA_2E3), 2847 DOP32 ("rotli", 2848 OPCODE_INFO3 (0xc4004900, 2849 (0_4, AREG, OPRND_SHIFT_0_BIT), 2850 (16_20, AREG, OPRND_SHIFT_0_BIT), 2851 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 2852 OPCODE_INFO2 (0xc4004900, 2853 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 2854 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 2855 CSKYV2_ISA_1E2), 2856 OP32 ("lslc", 2857 OPCODE_INFO3 (0xc4004c20, 2858 (0_4, AREG, OPRND_SHIFT_0_BIT), 2859 (16_20, AREG, OPRND_SHIFT_0_BIT), 2860 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 2861 CSKYV2_ISA_1E2), 2862 OP32 ("lsrc", 2863 OPCODE_INFO3 (0xc4004c40, 2864 (0_4, AREG, OPRND_SHIFT_0_BIT), 2865 (16_20, AREG, OPRND_SHIFT_0_BIT), 2866 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 2867 CSKYV2_ISA_1E2), 2868 DOP32 ("asrc", 2869 OPCODE_INFO3 (0xc4004c80, 2870 (0_4, AREG, OPRND_SHIFT_0_BIT), 2871 (16_20, AREG, OPRND_SHIFT_0_BIT), 2872 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 2873 OPCODE_INFO1 (0xc4004c80, 2874 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 2875 CSKYV2_ISA_1E2), 2876 OP32 ("xsr", 2877 OPCODE_INFO3 (0xc4004d00, 2878 (0_4, AREG, OPRND_SHIFT_0_BIT), 2879 (16_20, AREG, OPRND_SHIFT_0_BIT), 2880 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 2881 CSKYV2_ISA_1E2), 2882 OP32 ("bgenr", 2883 OPCODE_INFO2 (0xc4005040, 2884 (0_4, AREG, OPRND_SHIFT_0_BIT), 2885 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2886 CSKYV2_ISA_2E3), 2887 DOP32 ("brev", 2888 OPCODE_INFO2 (0xc4006200, 2889 (0_4, AREG, OPRND_SHIFT_0_BIT), 2890 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2891 OPCODE_INFO1 (0xc4006200, 2892 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 2893 CSKYV2_ISA_2E3), 2894 OP32 ("xtrb0", 2895 OPCODE_INFO2 (0xc4007020, 2896 (0_4, AREG, OPRND_SHIFT_0_BIT), 2897 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2898 CSKYV2_ISA_1E2), 2899 OP32 ("xtrb1", 2900 OPCODE_INFO2 (0xc4007040, 2901 (0_4, AREG, OPRND_SHIFT_0_BIT), 2902 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2903 CSKYV2_ISA_1E2), 2904 OP32 ("xtrb2", 2905 OPCODE_INFO2 (0xc4007080, 2906 (0_4, AREG, OPRND_SHIFT_0_BIT), 2907 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2908 CSKYV2_ISA_1E2), 2909 OP32 ("xtrb3", 2910 OPCODE_INFO2 (0xc4007100, 2911 (0_4, AREG, OPRND_SHIFT_0_BIT), 2912 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2913 CSKYV2_ISA_1E2), 2914 OP32 ("ff0", 2915 OPCODE_INFO2 (0xc4007c20, 2916 (0_4, AREG, OPRND_SHIFT_0_BIT), 2917 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2918 CSKYV2_ISA_1E2), 2919 DOP32 ("ff1", 2920 OPCODE_INFO2 (0xc4007c40, 2921 (0_4, AREG, OPRND_SHIFT_0_BIT), 2922 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2923 OPCODE_INFO1 (0xc4007c40, 2924 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 2925 CSKYV2_ISA_1E2), 2926 OP32 ("mulu", 2927 OPCODE_INFO2 (0xc4008820, 2928 (16_20, AREG, OPRND_SHIFT_0_BIT), 2929 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2930 CSKY_ISA_DSP), 2931 OP32 ("mulua", 2932 OPCODE_INFO2 (0xc4008840, 2933 (16_20, AREG, OPRND_SHIFT_0_BIT), 2934 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2935 CSKY_ISA_DSP), 2936 OP32 ("mulus", 2937 OPCODE_INFO2 (0xc4008880, 2938 (16_20, AREG, OPRND_SHIFT_0_BIT), 2939 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2940 CSKY_ISA_DSP), 2941 OP32 ("muls", 2942 OPCODE_INFO2 (0xc4008c20, 2943 (16_20, AREG, OPRND_SHIFT_0_BIT), 2944 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2945 CSKY_ISA_DSP), 2946 OP32 ("mulsa", 2947 OPCODE_INFO2 (0xc4008c40, 2948 (16_20, AREG, OPRND_SHIFT_0_BIT), 2949 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2950 CSKY_ISA_DSP), 2951 OP32 ("mulss", 2952 OPCODE_INFO2 (0xc4008c80, 2953 (16_20, AREG, OPRND_SHIFT_0_BIT), 2954 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2955 CSKY_ISA_DSP), 2956 OP32 ("mulsha", 2957 OPCODE_INFO2 (0xc4009040, 2958 (16_20, AREG, OPRND_SHIFT_0_BIT), 2959 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2960 CSKY_ISA_DSP), 2961 OP32 ("mulshs", 2962 OPCODE_INFO2 (0xc4009080, 2963 (16_20, AREG, OPRND_SHIFT_0_BIT), 2964 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2965 CSKY_ISA_DSP), 2966 OP32 ("mulswa", 2967 OPCODE_INFO2 (0xc4009440, 2968 (16_20, AREG, OPRND_SHIFT_0_BIT), 2969 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2970 CSKY_ISA_DSP), 2971 OP32 ("mulsws", 2972 OPCODE_INFO2 (0xc4009500, 2973 (16_20, AREG, OPRND_SHIFT_0_BIT), 2974 (21_25, AREG, OPRND_SHIFT_0_BIT)), 2975 CSKY_ISA_DSP), 2976 OP32 ("mfhis", 2977 OPCODE_INFO1 (0xc4009820, 2978 (0_4, AREG, OPRND_SHIFT_0_BIT)), 2979 CSKY_ISA_DSP), 2980 OP32 ("mflos", 2981 OPCODE_INFO1 (0xc4009880, 2982 (0_4, AREG, OPRND_SHIFT_0_BIT)), 2983 CSKY_ISA_DSP), 2984 OP32 ("mvtc", 2985 OPCODE_INFO0 (0xc4009a00), 2986 CSKY_ISA_DSPE60), 2987 OP32 ("mfhi", 2988 OPCODE_INFO1 (0xc4009c20, 2989 (0_4, AREG, OPRND_SHIFT_0_BIT)), 2990 CSKY_ISA_DSP), 2991 OP32 ("mthi", 2992 OPCODE_INFO1 (0xc4009c40, 2993 (16_20, AREG, OPRND_SHIFT_0_BIT)), 2994 CSKY_ISA_DSP), 2995 OP32 ("mflo", 2996 OPCODE_INFO1 (0xc4009c80, 2997 (0_4, AREG, OPRND_SHIFT_0_BIT)), 2998 CSKY_ISA_DSP), 2999 OP32 ("mtlo", 3000 OPCODE_INFO1 (0xc4009d00, 3001 (16_20, AREG, OPRND_SHIFT_0_BIT)), 3002 CSKY_ISA_DSP), 3003 OP32 ("vmulsh", 3004 OPCODE_INFO2 (0xc400b020, 3005 (16_20, AREG, OPRND_SHIFT_0_BIT), 3006 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3007 CSKY_ISA_DSP_1E2), 3008 OP32 ("vmulsha", 3009 OPCODE_INFO2 (0xc400b040, 3010 (16_20, AREG, OPRND_SHIFT_0_BIT), 3011 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3012 CSKY_ISA_DSP_1E2), 3013 OP32 ("vmulshs", 3014 OPCODE_INFO2 (0xc400b080, 3015 (16_20, AREG, OPRND_SHIFT_0_BIT), 3016 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3017 CSKY_ISA_DSP_1E2), 3018 OP32 ("vmulsw", 3019 OPCODE_INFO2 (0xc400b420, 3020 (16_20, AREG, OPRND_SHIFT_0_BIT), 3021 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3022 CSKY_ISA_DSP_1E2), 3023 OP32 ("vmulswa", 3024 OPCODE_INFO2 (0xc400b440, 3025 (16_20, AREG, OPRND_SHIFT_0_BIT), 3026 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3027 CSKY_ISA_DSP_1E2), 3028 OP32 ("vmulsws", 3029 OPCODE_INFO2 (0xc400b480, 3030 (16_20, AREG, OPRND_SHIFT_0_BIT), 3031 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3032 CSKY_ISA_DSP_1E2), 3033 OP32 ("ldr.b", 3034 SOPCODE_INFO2 (0xd0000000, 3035 (0_4, AREG, OPRND_SHIFT_0_BIT), 3036 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3037 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3038 CSKYV2_ISA_2E3), 3039 OP32 ("ldr.bs", 3040 SOPCODE_INFO2 (0xd0001000, 3041 (0_4, AREG, OPRND_SHIFT_0_BIT), 3042 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3043 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3044 CSKYV2_ISA_2E3), 3045 OP32 ("ldr.h", 3046 SOPCODE_INFO2 (0xd0000400, 3047 (0_4, AREG, OPRND_SHIFT_0_BIT), 3048 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3049 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3050 CSKYV2_ISA_2E3), 3051 OP32 ("ldr.hs", 3052 SOPCODE_INFO2 (0xd0001400, 3053 (0_4, AREG, OPRND_SHIFT_0_BIT), 3054 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3055 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3056 CSKYV2_ISA_2E3), 3057 OP32 ("ldr.w", 3058 SOPCODE_INFO2 (0xd0000800, 3059 (0_4, AREG, OPRND_SHIFT_0_BIT), 3060 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3061 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3062 CSKYV2_ISA_2E3), 3063 OP32 ("ldm", 3064 OPCODE_INFO2 (0xd0001c20, 3065 (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), 3066 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3067 CSKYV2_ISA_1E2), 3068 OP32 ("ldq", 3069 OPCODE_INFO2 (0xd0801c23, 3070 (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), 3071 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3072 CSKYV2_ISA_2E3), 3073 OP32 ("str.b", 3074 SOPCODE_INFO2 (0xd4000000, 3075 (0_4, AREG, OPRND_SHIFT_0_BIT), 3076 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3077 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3078 CSKYV2_ISA_2E3), 3079 OP32 ("str.h", 3080 SOPCODE_INFO2 (0xd4000400, 3081 (0_4, AREG, OPRND_SHIFT_0_BIT), 3082 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3083 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3084 CSKYV2_ISA_2E3), 3085 OP32 ("str.w", 3086 SOPCODE_INFO2 (0xd4000800, 3087 (0_4, AREG, OPRND_SHIFT_0_BIT), 3088 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3089 (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), 3090 CSKYV2_ISA_2E3), 3091 OP32 ("stm", 3092 OPCODE_INFO2 (0xd4001c20, 3093 (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), 3094 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3095 CSKYV2_ISA_1E2), 3096 OP32 ("stq", 3097 OPCODE_INFO2 (0xd4801c23, 3098 (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), 3099 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3100 CSKYV2_ISA_2E3), 3101 OP32 ("ld.bs", 3102 SOPCODE_INFO2 (0xd8004000, 3103 (21_25, AREG, OPRND_SHIFT_0_BIT), 3104 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3105 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 3106 CSKYV2_ISA_1E2), 3107 OP32 ("ldbs", 3108 SOPCODE_INFO2 (0xd8004000, 3109 (21_25, AREG, OPRND_SHIFT_0_BIT), 3110 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3111 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 3112 CSKYV2_ISA_1E2), 3113 OP32 ("ld.hs", 3114 SOPCODE_INFO2 (0xd8005000, 3115 (21_25, AREG, OPRND_SHIFT_0_BIT), 3116 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3117 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 3118 CSKYV2_ISA_1E2), 3119 OP32 ("ldhs", 3120 SOPCODE_INFO2 (0xd8005000, 3121 (21_25, AREG, OPRND_SHIFT_0_BIT), 3122 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3123 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 3124 CSKYV2_ISA_1E2), 3125 OP32 ("ld.d", 3126 SOPCODE_INFO2 (0xd8003000, 3127 (21_25, AREG, OPRND_SHIFT_0_BIT), 3128 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3129 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3130 CSKYV2_ISA_3E7), 3131 OP32 ("ldex.w", 3132 SOPCODE_INFO2 (0xd8007000, 3133 (21_25, AREG, OPRND_SHIFT_0_BIT), 3134 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3135 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3136 CSKY_ISA_MP_1E2), 3137 OP32 ("ldexw", 3138 SOPCODE_INFO2 (0xd8007000, 3139 (21_25, AREG, OPRND_SHIFT_0_BIT), 3140 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3141 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3142 CSKY_ISA_MP_1E2), 3143 OP32 ("ldex", 3144 SOPCODE_INFO2 (0xd8007000, 3145 (21_25, AREG, OPRND_SHIFT_0_BIT), 3146 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3147 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3148 CSKY_ISA_MP_1E2), 3149 OP32 ("st.d", 3150 SOPCODE_INFO2 (0xdc003000, 3151 (21_25, AREG, OPRND_SHIFT_0_BIT), 3152 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3153 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3154 CSKYV2_ISA_3E7), 3155 OP32 ("stex.w", 3156 SOPCODE_INFO2 (0xdc007000, 3157 (21_25, AREG, OPRND_SHIFT_0_BIT), 3158 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3159 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3160 CSKY_ISA_MP_1E2), 3161 OP32 ("stexw", 3162 SOPCODE_INFO2 (0xdc007000, 3163 (21_25, AREG, OPRND_SHIFT_0_BIT), 3164 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3165 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3166 CSKY_ISA_MP_1E2), 3167 OP32 ("stex", 3168 SOPCODE_INFO2 (0xdc007000, 3169 (21_25, AREG, OPRND_SHIFT_0_BIT), 3170 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3171 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3172 CSKY_ISA_MP_1E2), 3173 DOP32 ("andi", 3174 OPCODE_INFO3 (0xe4002000, 3175 (21_25, AREG, OPRND_SHIFT_0_BIT), 3176 (16_20, AREG, OPRND_SHIFT_0_BIT), 3177 (0_11, IMM12b, OPRND_SHIFT_0_BIT)), 3178 OPCODE_INFO2 (0xe4002000, 3179 (16_20or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), 3180 (0_11, IMM12b, OPRND_SHIFT_0_BIT)), 3181 CSKYV2_ISA_1E2), 3182 OP32 ("andni", 3183 OPCODE_INFO3 (0xe4003000, 3184 (21_25, AREG, OPRND_SHIFT_0_BIT), 3185 (16_20, AREG, OPRND_SHIFT_0_BIT), 3186 (0_11, IMM12b, OPRND_SHIFT_0_BIT)), 3187 CSKYV2_ISA_1E2), 3188 OP32 ("xori", 3189 OPCODE_INFO3 (0xe4004000, 3190 (21_25, AREG, OPRND_SHIFT_0_BIT), 3191 (16_20, AREG, OPRND_SHIFT_0_BIT), 3192 (0_11, IMM12b, OPRND_SHIFT_0_BIT)), 3193 CSKYV2_ISA_1E2), 3194 OP32 ("ins", 3195 OPCODE_INFO4 (0xc4005c00, 3196 (21_25, AREG, OPRND_SHIFT_0_BIT), 3197 (16_20, AREG, OPRND_SHIFT_0_BIT), 3198 (5_9, MSB2SIZE, OPRND_SHIFT_0_BIT), 3199 (0_4, LSB2SIZE, OPRND_SHIFT_0_BIT)), 3200 CSKYV2_ISA_2E3), 3201 #undef _TRANSFER 3202 #undef _RELOC32 3203 #define _TRANSFER 1 3204 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 3205 OP32 ("jmpi", 3206 OPCODE_INFO1 (0xeac00000, 3207 (0_15, OFF16b, OPRND_SHIFT_2_BIT)), 3208 CSKYV2_ISA_2E3), 3209 #undef _TRANSFER 3210 #undef _RELOC32 3211 #define _TRANSFER 0 3212 #define _RELOC32 0 3213 3214 OP32 ("fadds", 3215 OPCODE_INFO3 (0xf4000000, 3216 (0_3, FREG, OPRND_SHIFT_0_BIT), 3217 (16_19, FREG, OPRND_SHIFT_0_BIT), 3218 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3219 CSKY_ISA_FLOAT_E1), 3220 OP32 ("fsubs", 3221 OPCODE_INFO3 (0xf4000020, 3222 (0_3, FREG, OPRND_SHIFT_0_BIT), 3223 (16_19, FREG, OPRND_SHIFT_0_BIT), 3224 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3225 CSKY_ISA_FLOAT_E1), 3226 OP32 ("fmovs", 3227 OPCODE_INFO2 (0xf4000080, 3228 (0_3, FREG, OPRND_SHIFT_0_BIT), 3229 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3230 CSKY_ISA_FLOAT_E1), 3231 OP32 ("fabss", 3232 OPCODE_INFO2 (0xf40000c0, 3233 (0_3, FREG, OPRND_SHIFT_0_BIT), 3234 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3235 CSKY_ISA_FLOAT_E1), 3236 OP32 ("fnegs", 3237 OPCODE_INFO2 (0xf40000e0, 3238 (0_3, FREG, OPRND_SHIFT_0_BIT), 3239 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3240 CSKY_ISA_FLOAT_E1), 3241 OP32 ("fcmpzhss", 3242 OPCODE_INFO1 (0xf4000100, 3243 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3244 CSKY_ISA_FLOAT_E1), 3245 OP32 ("fcmpzlss", 3246 OPCODE_INFO1 (0xf4000120, 3247 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3248 CSKY_ISA_FLOAT_E1), 3249 OP32 ("fcmpznes", 3250 OPCODE_INFO1 (0xf4000140, 3251 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3252 CSKY_ISA_FLOAT_E1), 3253 OP32 ("fcmpzuos", 3254 OPCODE_INFO1 (0xf4000160, 3255 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3256 CSKY_ISA_FLOAT_E1), 3257 OP32 ("fcmphss", 3258 OPCODE_INFO2 (0xf4000180, 3259 (16_19, FREG, OPRND_SHIFT_0_BIT), 3260 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3261 CSKY_ISA_FLOAT_E1), 3262 OP32 ("fcmplts", 3263 OPCODE_INFO2 (0xf40001a0, 3264 (16_19, FREG, OPRND_SHIFT_0_BIT), 3265 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3266 CSKY_ISA_FLOAT_E1), 3267 OP32 ("fcmpnes", 3268 OPCODE_INFO2 (0xf40001c0, 3269 (16_19, FREG, OPRND_SHIFT_0_BIT), 3270 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3271 CSKY_ISA_FLOAT_E1), 3272 OP32 ("fcmpuos", 3273 OPCODE_INFO2 (0xf40001e0, 3274 (16_19, FREG, OPRND_SHIFT_0_BIT), 3275 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3276 CSKY_ISA_FLOAT_E1), 3277 OP32 ("fmuls", 3278 OPCODE_INFO3 (0xf4000200, 3279 (0_3, FREG, OPRND_SHIFT_0_BIT), 3280 (16_19, FREG, OPRND_SHIFT_0_BIT), 3281 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3282 CSKY_ISA_FLOAT_E1), 3283 OP32 ("fmacs", 3284 OPCODE_INFO3 (0xf4000280, 3285 (0_3, FREG, OPRND_SHIFT_0_BIT), 3286 (16_19, FREG, OPRND_SHIFT_0_BIT), 3287 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3288 CSKY_ISA_FLOAT_E1), 3289 OP32 ("fmscs", 3290 OPCODE_INFO3 (0xf40002a0, 3291 (0_3, FREG, OPRND_SHIFT_0_BIT), 3292 (16_19, FREG, OPRND_SHIFT_0_BIT), 3293 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3294 CSKY_ISA_FLOAT_E1), 3295 OP32 ("fnmacs", 3296 OPCODE_INFO3 (0xf40002c0, 3297 (0_3, FREG, OPRND_SHIFT_0_BIT), 3298 (16_19, FREG, OPRND_SHIFT_0_BIT), 3299 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3300 CSKY_ISA_FLOAT_E1), 3301 OP32 ("fnmscs", 3302 OPCODE_INFO3 (0xf40002e0, 3303 (0_3, FREG, OPRND_SHIFT_0_BIT), 3304 (16_19, FREG, OPRND_SHIFT_0_BIT), 3305 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3306 CSKY_ISA_FLOAT_E1), 3307 OP32 ("fnmuls", 3308 OPCODE_INFO3 (0xf4000220, 3309 (0_3, FREG, OPRND_SHIFT_0_BIT), 3310 (16_19, FREG, OPRND_SHIFT_0_BIT), 3311 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3312 CSKY_ISA_FLOAT_E1), 3313 OP32 ("fdivs", 3314 OPCODE_INFO3 (0xf4000300, 3315 (0_3, FREG, OPRND_SHIFT_0_BIT), 3316 (16_19, FREG, OPRND_SHIFT_0_BIT), 3317 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3318 CSKY_ISA_FLOAT_E1), 3319 OP32 ("frecips", 3320 OPCODE_INFO2 (0xf4000320, 3321 (0_3, FREG, OPRND_SHIFT_0_BIT), 3322 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3323 CSKY_ISA_FLOAT_E1), 3324 OP32 ("fsqrts", 3325 OPCODE_INFO2 (0xf4000340, 3326 (0_3, FREG, OPRND_SHIFT_0_BIT), 3327 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3328 CSKY_ISA_FLOAT_E1), 3329 OP32 ("faddd", 3330 OPCODE_INFO3 (0xf4000800, 3331 (0_3, FREG, OPRND_SHIFT_0_BIT), 3332 (16_19, FREG, OPRND_SHIFT_0_BIT), 3333 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3334 CSKY_ISA_FLOAT_1E2), 3335 OP32 ("fsubd", 3336 OPCODE_INFO3 (0xf4000820, 3337 (0_3, FREG, OPRND_SHIFT_0_BIT), 3338 (16_19, FREG, OPRND_SHIFT_0_BIT), 3339 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3340 CSKY_ISA_FLOAT_1E2), 3341 OP32 ("fmovd", 3342 OPCODE_INFO2 (0xf4000880, 3343 (0_3, FREG, OPRND_SHIFT_0_BIT), 3344 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3345 CSKY_ISA_FLOAT_1E2), 3346 OP32 ("fabsd", 3347 OPCODE_INFO2 (0xf40008c0, 3348 (0_3, FREG, OPRND_SHIFT_0_BIT), 3349 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3350 CSKY_ISA_FLOAT_1E2), 3351 OP32 ("fnegd", 3352 OPCODE_INFO2 (0xf40008e0, 3353 (0_3, FREG, OPRND_SHIFT_0_BIT), 3354 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3355 CSKY_ISA_FLOAT_1E2), 3356 OP32 ("fcmpzhsd", 3357 OPCODE_INFO1 (0xf4000900, 3358 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3359 CSKY_ISA_FLOAT_1E2), 3360 OP32 ("fcmpzlsd", 3361 OPCODE_INFO1 (0xf4000920, 3362 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3363 CSKY_ISA_FLOAT_1E2), 3364 OP32 ("fcmpzned", 3365 OPCODE_INFO1 (0xf4000940, 3366 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3367 CSKY_ISA_FLOAT_1E2), 3368 OP32 ("fcmpzuod", 3369 OPCODE_INFO1 (0xf4000960, 3370 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3371 CSKY_ISA_FLOAT_1E2), 3372 OP32 ("fcmphsd", 3373 OPCODE_INFO2 (0xf4000980, 3374 (16_19, FREG, OPRND_SHIFT_0_BIT), 3375 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3376 CSKY_ISA_FLOAT_1E2), 3377 OP32 ("fcmpltd", 3378 OPCODE_INFO2 (0xf40009a0, 3379 (16_19, FREG, OPRND_SHIFT_0_BIT), 3380 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3381 CSKY_ISA_FLOAT_1E2), 3382 OP32 ("fcmpned", 3383 OPCODE_INFO2 (0xf40009c0, 3384 (16_19, FREG, OPRND_SHIFT_0_BIT), 3385 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3386 CSKY_ISA_FLOAT_1E2), 3387 OP32 ("fcmpuod", 3388 OPCODE_INFO2 (0xf40009e0, 3389 (16_19, FREG, OPRND_SHIFT_0_BIT), 3390 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3391 CSKY_ISA_FLOAT_1E2), 3392 OP32 ("fmuld", 3393 OPCODE_INFO3 (0xf4000a00, 3394 (0_3, FREG, OPRND_SHIFT_0_BIT), 3395 (16_19, FREG, OPRND_SHIFT_0_BIT), 3396 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3397 CSKY_ISA_FLOAT_1E2), 3398 OP32 ("fnmuld", 3399 OPCODE_INFO3 (0xf4000a20, 3400 (0_3, FREG, OPRND_SHIFT_0_BIT), 3401 (16_19, FREG, OPRND_SHIFT_0_BIT), 3402 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3403 CSKY_ISA_FLOAT_1E2), 3404 OP32 ("fmacd", 3405 OPCODE_INFO3 (0xf4000a80, 3406 (0_3, FREG, OPRND_SHIFT_0_BIT), 3407 (16_19, FREG, OPRND_SHIFT_0_BIT), 3408 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3409 CSKY_ISA_FLOAT_1E2), 3410 OP32 ("fmscd", 3411 OPCODE_INFO3 (0xf4000aa0, 3412 (0_3, FREG, OPRND_SHIFT_0_BIT), 3413 (16_19, FREG, OPRND_SHIFT_0_BIT), 3414 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3415 CSKY_ISA_FLOAT_1E2), 3416 OP32 ("fnmacd", 3417 OPCODE_INFO3 (0xf4000ac0, 3418 (0_3, FREG, OPRND_SHIFT_0_BIT), 3419 (16_19, FREG, OPRND_SHIFT_0_BIT), 3420 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3421 CSKY_ISA_FLOAT_1E2), 3422 OP32 ("fnmscd", 3423 OPCODE_INFO3 (0xf4000ae0, 3424 (0_3, FREG, OPRND_SHIFT_0_BIT), 3425 (16_19, FREG, OPRND_SHIFT_0_BIT), 3426 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3427 CSKY_ISA_FLOAT_1E2), 3428 OP32 ("fdivd", 3429 OPCODE_INFO3 (0xf4000b00, 3430 (0_3, FREG, OPRND_SHIFT_0_BIT), 3431 (16_19, FREG, OPRND_SHIFT_0_BIT), 3432 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3433 CSKY_ISA_FLOAT_1E2), 3434 OP32 ("frecipd", 3435 OPCODE_INFO2 (0xf4000b20, 3436 (0_3, FREG, OPRND_SHIFT_0_BIT), 3437 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3438 CSKY_ISA_FLOAT_1E2), 3439 OP32 ("fsqrtd", 3440 OPCODE_INFO2 (0xf4000b40, 3441 (0_3, FREG, OPRND_SHIFT_0_BIT), 3442 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3443 CSKY_ISA_FLOAT_1E2), 3444 OP32 ("faddm", 3445 OPCODE_INFO3 (0xf4001000, 3446 (0_3, FREG, OPRND_SHIFT_0_BIT), 3447 (16_19, FREG, OPRND_SHIFT_0_BIT), 3448 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3449 CSKY_ISA_FLOAT_1E2), 3450 OP32 ("fsubm", 3451 OPCODE_INFO3 (0xf4001020, 3452 (0_3, FREG, OPRND_SHIFT_0_BIT), 3453 (16_19, FREG, OPRND_SHIFT_0_BIT), 3454 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3455 CSKY_ISA_FLOAT_1E2), 3456 OP32 ("fmovm", 3457 OPCODE_INFO2 (0xf4001080, 3458 (0_3, FREG, OPRND_SHIFT_0_BIT), 3459 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3460 CSKY_ISA_FLOAT_1E2), 3461 OP32 ("fabsm", 3462 OPCODE_INFO2 (0xf40010c0, 3463 (0_3, FREG, OPRND_SHIFT_0_BIT), 3464 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3465 CSKY_ISA_FLOAT_1E2), 3466 OP32 ("fnegm", 3467 OPCODE_INFO2 (0xf40010e0, 3468 (0_3, FREG, OPRND_SHIFT_0_BIT), 3469 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3470 CSKY_ISA_FLOAT_1E2), 3471 OP32 ("fmulm", 3472 OPCODE_INFO3 (0xf4001200, 3473 (0_3, FREG, OPRND_SHIFT_0_BIT), 3474 (16_19, FREG, OPRND_SHIFT_0_BIT), 3475 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3476 CSKY_ISA_FLOAT_1E2), 3477 OP32 ("fnmulm", 3478 OPCODE_INFO3 (0xf4001220, 3479 (0_3, FREG, OPRND_SHIFT_0_BIT), 3480 (16_19, FREG, OPRND_SHIFT_0_BIT), 3481 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3482 CSKY_ISA_FLOAT_1E2), 3483 OP32 ("fmacm", 3484 OPCODE_INFO3 (0xf4001280, 3485 (0_3, FREG, OPRND_SHIFT_0_BIT), 3486 (16_19, FREG, OPRND_SHIFT_0_BIT), 3487 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3488 CSKY_ISA_FLOAT_1E2), 3489 OP32 ("fmscm", 3490 OPCODE_INFO3 (0xf40012a0, 3491 (0_3, FREG, OPRND_SHIFT_0_BIT), 3492 (16_19, FREG, OPRND_SHIFT_0_BIT), 3493 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3494 CSKY_ISA_FLOAT_1E2), 3495 OP32 ("fnmacm", 3496 OPCODE_INFO3 (0xf40012c0, 3497 (0_3, FREG, OPRND_SHIFT_0_BIT), 3498 (16_19, FREG, OPRND_SHIFT_0_BIT), 3499 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3500 CSKY_ISA_FLOAT_1E2), 3501 OP32 ("fnmscm", 3502 OPCODE_INFO3 (0xf40012e0, 3503 (0_3, FREG, OPRND_SHIFT_0_BIT), 3504 (16_19, FREG, OPRND_SHIFT_0_BIT), 3505 (21_24, FREG, OPRND_SHIFT_0_BIT)), 3506 CSKY_ISA_FLOAT_1E2), 3507 OP32 ("fstosi.rn", 3508 OPCODE_INFO2 (0xf4001800, 3509 (0_3, FREG, OPRND_SHIFT_0_BIT), 3510 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3511 CSKY_ISA_FLOAT_E1), 3512 OP32 ("fstosi.rz", 3513 OPCODE_INFO2 (0xf4001820, 3514 (0_3, FREG, OPRND_SHIFT_0_BIT), 3515 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3516 CSKY_ISA_FLOAT_E1), 3517 OP32 ("fstosi.rpi", 3518 OPCODE_INFO2 (0xf4001840, 3519 (0_3, FREG, OPRND_SHIFT_0_BIT), 3520 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3521 CSKY_ISA_FLOAT_E1), 3522 OP32 ("fstosi.rni", 3523 OPCODE_INFO2 (0xf4001860, 3524 (0_3, FREG, OPRND_SHIFT_0_BIT), 3525 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3526 CSKY_ISA_FLOAT_E1), 3527 OP32 ("fstoui.rn", 3528 OPCODE_INFO2 (0xf4001880, 3529 (0_3, FREG, OPRND_SHIFT_0_BIT), 3530 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3531 CSKY_ISA_FLOAT_E1), 3532 OP32 ("fstoui.rz", 3533 OPCODE_INFO2 (0xf40018a0, 3534 (0_3, FREG, OPRND_SHIFT_0_BIT), 3535 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3536 CSKY_ISA_FLOAT_E1), 3537 OP32 ("fstoui.rpi", 3538 OPCODE_INFO2 (0xf40018c0, 3539 (0_3, FREG, OPRND_SHIFT_0_BIT), 3540 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3541 CSKY_ISA_FLOAT_E1), 3542 OP32 ("fstoui.rni", 3543 OPCODE_INFO2 (0xf40018e0, 3544 (0_3, FREG, OPRND_SHIFT_0_BIT), 3545 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3546 CSKY_ISA_FLOAT_E1), 3547 OP32 ("fdtosi.rn", 3548 OPCODE_INFO2 (0xf4001900, 3549 (0_3, FREG, OPRND_SHIFT_0_BIT), 3550 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3551 CSKY_ISA_FLOAT_1E2), 3552 OP32 ("fdtosi.rz", 3553 OPCODE_INFO2 (0xf4001920, 3554 (0_3, FREG, OPRND_SHIFT_0_BIT), 3555 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3556 CSKY_ISA_FLOAT_1E2), 3557 OP32 ("fdtosi.rpi", 3558 OPCODE_INFO2 (0xf4001940, 3559 (0_3, FREG, OPRND_SHIFT_0_BIT), 3560 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3561 CSKY_ISA_FLOAT_1E2), 3562 OP32 ("fdtosi.rni", 3563 OPCODE_INFO2 (0xf4001960, 3564 (0_3, FREG, OPRND_SHIFT_0_BIT), 3565 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3566 CSKY_ISA_FLOAT_1E2), 3567 OP32 ("fdtoui.rn", 3568 OPCODE_INFO2 (0xf4001980, 3569 (0_3, FREG, OPRND_SHIFT_0_BIT), 3570 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3571 CSKY_ISA_FLOAT_1E2), 3572 OP32 ("fdtoui.rz", 3573 OPCODE_INFO2 (0xf40019a0, 3574 (0_3, FREG, OPRND_SHIFT_0_BIT), 3575 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3576 CSKY_ISA_FLOAT_1E2), 3577 OP32 ("fdtoui.rpi", 3578 OPCODE_INFO2 (0xf40019c0, 3579 (0_3, FREG, OPRND_SHIFT_0_BIT), 3580 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3581 CSKY_ISA_FLOAT_1E2), 3582 OP32 ("fdtoui.rni", 3583 OPCODE_INFO2 (0xf40019e0, 3584 (0_3, FREG, OPRND_SHIFT_0_BIT), 3585 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3586 CSKY_ISA_FLOAT_1E2), 3587 OP32 ("fsitos", 3588 OPCODE_INFO2 (0xf4001a00, 3589 (0_3, FREG, OPRND_SHIFT_0_BIT), 3590 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3591 CSKY_ISA_FLOAT_E1), 3592 OP32 ("fuitos", 3593 OPCODE_INFO2 (0xf4001a20, 3594 (0_3, FREG, OPRND_SHIFT_0_BIT), 3595 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3596 CSKY_ISA_FLOAT_E1), 3597 OP32 ("fsitod", 3598 OPCODE_INFO2 (0xf4001a80, 3599 (0_3, FREG, OPRND_SHIFT_0_BIT), 3600 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3601 CSKY_ISA_FLOAT_1E2), 3602 OP32 ("fuitod", 3603 OPCODE_INFO2 (0xf4001aa0, 3604 (0_3, FREG, OPRND_SHIFT_0_BIT), 3605 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3606 CSKY_ISA_FLOAT_1E2), 3607 OP32 ("fdtos", 3608 OPCODE_INFO2 (0xf4001ac0, 3609 (0_3, FREG, OPRND_SHIFT_0_BIT), 3610 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3611 CSKY_ISA_FLOAT_1E2), 3612 OP32 ("fstod", 3613 OPCODE_INFO2 (0xf4001ae0, 3614 (0_3, FREG, OPRND_SHIFT_0_BIT), 3615 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3616 CSKY_ISA_FLOAT_1E2), 3617 OP32 ("fmfvrh", 3618 OPCODE_INFO2 (0xf4001b00, 3619 (0_4, AREG, OPRND_SHIFT_0_BIT), 3620 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3621 CSKY_ISA_FLOAT_1E2), 3622 OP32 ("fmfvrl", 3623 OPCODE_INFO2 (0xf4001b20, 3624 (0_4, AREG, OPRND_SHIFT_0_BIT), 3625 (16_19, FREG, OPRND_SHIFT_0_BIT)), 3626 CSKY_ISA_FLOAT_E1), 3627 OP32 ("fmtvrh", 3628 OPCODE_INFO2 (0xf4001b40, 3629 (0_3, FREG, OPRND_SHIFT_0_BIT), 3630 (16_20, AREG, OPRND_SHIFT_0_BIT)), 3631 CSKY_ISA_FLOAT_1E2), 3632 OP32 ("fmtvrl", 3633 OPCODE_INFO2 (0xf4001b60, 3634 (0_3, FREG, OPRND_SHIFT_0_BIT), 3635 (16_20, AREG, OPRND_SHIFT_0_BIT)), 3636 CSKY_ISA_FLOAT_E1), 3637 OP32 ("flds", 3638 SOPCODE_INFO2 (0xf4002000, 3639 (0_3, FREG, OPRND_SHIFT_0_BIT), 3640 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3641 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), 3642 CSKY_ISA_FLOAT_E1), 3643 OP32 ("fldd", 3644 SOPCODE_INFO2 (0xf4002100, 3645 (0_3, FREG, OPRND_SHIFT_0_BIT), 3646 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3647 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), 3648 CSKY_ISA_FLOAT_1E2), 3649 OP32 ("fldm", 3650 SOPCODE_INFO2 (0xf4002200, 3651 (0_3, FREG, OPRND_SHIFT_0_BIT), 3652 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3653 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 3654 CSKY_ISA_FLOAT_1E2), 3655 OP32 ("fsts", 3656 SOPCODE_INFO2 (0xf4002400, 3657 (0_3, FREG, OPRND_SHIFT_0_BIT), 3658 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3659 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), 3660 CSKY_ISA_FLOAT_E1), 3661 OP32 ("fstd", 3662 SOPCODE_INFO2 (0xf4002500, 3663 (0_3, FREG, OPRND_SHIFT_0_BIT), 3664 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3665 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), 3666 CSKY_ISA_FLOAT_1E2), 3667 OP32 ("fstm", 3668 SOPCODE_INFO2 (0xf4002600, 3669 (0_3, FREG, OPRND_SHIFT_0_BIT), 3670 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3671 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 3672 CSKY_ISA_FLOAT_1E2), 3673 OP32 ("fldrs", 3674 SOPCODE_INFO2 (0xf4002800, 3675 (0_3, FREG, OPRND_SHIFT_0_BIT), 3676 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3677 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3678 CSKY_ISA_FLOAT_E1), 3679 OP32 ("fstrs", 3680 SOPCODE_INFO2 (0xf4002c00, 3681 (0_3, FREG, OPRND_SHIFT_0_BIT), 3682 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3683 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3684 CSKY_ISA_FLOAT_E1), 3685 OP32 ("fldrd", 3686 SOPCODE_INFO2 (0xf4002900, 3687 (0_3, FREG, OPRND_SHIFT_0_BIT), 3688 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3689 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3690 CSKY_ISA_FLOAT_1E2), 3691 OP32 ("fldrm", 3692 SOPCODE_INFO2 (0xf4002a00, 3693 (0_3, FREG, OPRND_SHIFT_0_BIT), 3694 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3695 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3696 CSKY_ISA_FLOAT_1E2), 3697 OP32 ("fstrd", 3698 SOPCODE_INFO2 (0xf4002d00, 3699 (0_3, FREG, OPRND_SHIFT_0_BIT), 3700 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3701 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3702 CSKY_ISA_FLOAT_1E2), 3703 OP32 ("fstrm", 3704 SOPCODE_INFO2 (0xf4002e00, 3705 (0_3, FREG, OPRND_SHIFT_0_BIT), 3706 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3707 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 3708 CSKY_ISA_FLOAT_1E2), 3709 OP32 ("fldms", 3710 OPCODE_INFO2 (0xf4003000, 3711 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3712 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3713 CSKY_ISA_FLOAT_E1), 3714 OP32 ("fldmd", 3715 OPCODE_INFO2 (0xf4003100, 3716 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3717 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3718 CSKY_ISA_FLOAT_1E2), 3719 OP32 ("fldmm", 3720 OPCODE_INFO2 (0xf4003200, 3721 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3722 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3723 CSKY_ISA_FLOAT_1E2), 3724 OP32 ("fstms", 3725 OPCODE_INFO2 (0xf4003400, 3726 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3727 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3728 CSKY_ISA_FLOAT_E1), 3729 OP32 ("fstmd", 3730 OPCODE_INFO2 (0xf4003500, 3731 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3732 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3733 CSKY_ISA_FLOAT_1E2), 3734 OP32 ("fstmm", 3735 OPCODE_INFO2 (0xf4003600, 3736 (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 3737 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 3738 CSKY_ISA_FLOAT_1E2), 3739 DOP32 ("idly", 3740 OPCODE_INFO1 (0xc0001c20, 3741 (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)), 3742 OPCODE_INFO0 (0xc0601c20), 3743 CSKYV2_ISA_E1), 3744 3745 #undef _RELOC32 3746 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM18BY2 3747 OP32 ("grs", 3748 OPCODE_INFO2 (0xcc0c0000, 3749 (21_25, AREG, OPRND_SHIFT_0_BIT), 3750 (0_17, IMM_OFF18b, OPRND_SHIFT_1_BIT)), 3751 CSKYV2_ISA_2E3), 3752 #undef _RELOC32 3753 #define _RELOC32 0 3754 DOP32 ("ixh", 3755 OPCODE_INFO3 (0xc4000820, 3756 (0_4, AREG, OPRND_SHIFT_0_BIT), 3757 (16_20, AREG, OPRND_SHIFT_0_BIT), 3758 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3759 OPCODE_INFO2 (0xc4000820, 3760 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3761 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3762 CSKYV2_ISA_1E2), 3763 DOP32 ("ixw", 3764 OPCODE_INFO3 (0xc4000840, 3765 (0_4, AREG, OPRND_SHIFT_0_BIT), 3766 (16_20, AREG, OPRND_SHIFT_0_BIT), 3767 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3768 OPCODE_INFO2 (0xc4000840, 3769 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3770 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3771 CSKYV2_ISA_1E2), 3772 OP32 ("ixd", 3773 OPCODE_INFO3 (0xc4000880, 3774 (0_4, AREG, OPRND_SHIFT_0_BIT), 3775 (16_20, AREG, OPRND_SHIFT_0_BIT), 3776 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3777 CSKYV2_ISA_2E3), 3778 DOP32 ("divu", 3779 OPCODE_INFO3 (0xc4008020, 3780 (0_4, AREG, OPRND_SHIFT_0_BIT), 3781 (16_20, AREG, OPRND_SHIFT_0_BIT), 3782 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3783 OPCODE_INFO2 (0xc4008020, 3784 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3785 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3786 CSKYV2_ISA_2E3), 3787 DOP32 ("divs", 3788 OPCODE_INFO3 (0xc4008040, 3789 (0_4, AREG, OPRND_SHIFT_0_BIT), 3790 (16_20, AREG, OPRND_SHIFT_0_BIT), 3791 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3792 OPCODE_INFO2 (0xc4008040, 3793 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3794 (21_25, AREG, OPRND_SHIFT_0_BIT)), 3795 CSKYV2_ISA_2E3), 3796 OP32 ("pldr", 3797 SOPCODE_INFO1 (0xd8006000, 3798 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3799 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3800 CSKY_ISA_CACHE), 3801 OP32 ("pldw", 3802 SOPCODE_INFO1 (0xdc006000, 3803 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 3804 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 3805 CSKY_ISA_CACHE), 3806 OP32 ("cprgr", 3807 SOPCODE_INFO2 (0xfc000000, 3808 (16_20, AREG, OPRND_SHIFT_0_BIT), 3809 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3810 (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), 3811 CSKYV2_ISA_E1), 3812 OP32 ("cpwgr", 3813 SOPCODE_INFO2 (0xfc001000, 3814 (16_20, AREG, OPRND_SHIFT_0_BIT), 3815 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3816 (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), 3817 CSKYV2_ISA_E1), 3818 OP32 ("cprcr", 3819 SOPCODE_INFO2 (0xfc002000, 3820 (16_20, AREG, OPRND_SHIFT_0_BIT), 3821 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3822 (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), 3823 CSKYV2_ISA_E1), 3824 OP32 ("cpwcr", 3825 SOPCODE_INFO2 (0xfc003000, 3826 (16_20, AREG, OPRND_SHIFT_0_BIT), 3827 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3828 (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), 3829 CSKYV2_ISA_E1), 3830 OP32 ("cprc", 3831 SOPCODE_INFO1 (0xfc004000, 3832 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3833 (0_11, IMM12b, OPRND_SHIFT_0_BIT))), 3834 CSKYV2_ISA_E1), 3835 OP32 ("cpop", 3836 SOPCODE_INFO1 (0xfc008000, 3837 ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), 3838 (0_14or16_20 , IMM15b, OPRND_SHIFT_0_BIT))), 3839 CSKYV2_ISA_E1), 3840 3841 OP16_OP32 ("push", 3842 OPCODE_INFO_LIST (0x14c0, 3843 (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), 3844 CSKYV2_ISA_E1, 3845 OPCODE_INFO_LIST (0xebe00000, 3846 (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), 3847 CSKYV2_ISA_2E3), 3848 #undef _TRANSFER 3849 #define _TRANSFER 2 3850 OP16_OP32 ("pop", 3851 OPCODE_INFO_LIST (0x1480, 3852 (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), 3853 CSKYV2_ISA_E1, 3854 OPCODE_INFO_LIST (0xebc00000, 3855 (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), 3856 CSKYV2_ISA_2E3), 3857 #undef _TRANSFER 3858 #define _TRANSFER 0 3859 OP16_OP32 ("movi", 3860 OPCODE_INFO2 (0x3000, 3861 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3862 (0_7, IMM8b, OPRND_SHIFT_0_BIT)), 3863 CSKYV2_ISA_E1, 3864 OPCODE_INFO2 (0xea000000, 3865 (16_20, AREG, OPRND_SHIFT_0_BIT), 3866 (0_15, IMM16b, OPRND_SHIFT_0_BIT)), 3867 CSKYV2_ISA_1E2), 3868 /* bmaski will transfer to movi when imm < 17. */ 3869 OP16_OP32 ("bmaski", 3870 OPCODE_INFO2 (0x3000, 3871 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3872 (0_7, IMM8b_BMASKI, OPRND_SHIFT_0_BIT)), 3873 CSKYV2_ISA_1E2, 3874 OPCODE_INFO2 (0xc4005020, 3875 (0_4, AREG, OPRND_SHIFT_0_BIT), 3876 (21_25, OIMM5b_BMASKI, OPRND_SHIFT_0_BIT)), 3877 CSKYV2_ISA_1E2), 3878 OP16_OP32 ("cmphsi", 3879 OPCODE_INFO2 (0x3800, 3880 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3881 (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), 3882 CSKYV2_ISA_E1, 3883 OPCODE_INFO2 (0xeb000000, 3884 (16_20, AREG, OPRND_SHIFT_0_BIT), 3885 (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), 3886 CSKYV2_ISA_1E2), 3887 OP16_OP32 ("cmplti", 3888 OPCODE_INFO2 (0x3820, 3889 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3890 (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), 3891 CSKYV2_ISA_E1, 3892 OPCODE_INFO2 (0xeb200000, 3893 (16_20, AREG, OPRND_SHIFT_0_BIT), 3894 (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), 3895 CSKYV2_ISA_1E2), 3896 OP16_OP32 ("cmpnei", 3897 OPCODE_INFO2 (0x3840, 3898 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3899 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3900 CSKYV2_ISA_E1, 3901 OPCODE_INFO2 (0xeb400000, 3902 (16_20, AREG, OPRND_SHIFT_0_BIT), 3903 (0_15, IMM16b, OPRND_SHIFT_0_BIT)), 3904 CSKYV2_ISA_1E2), 3905 #undef _TRANSFER 3906 #define _TRANSFER 1 3907 OP16_OP32 ("jmpix", 3908 OPCODE_INFO2 (0x38e0, 3909 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3910 (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), 3911 CSKY_ISA_JAVA, 3912 OPCODE_INFO2 (0xe9e00000, 3913 (16_20, GREG0_7, OPRND_SHIFT_0_BIT), 3914 (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), 3915 CSKY_ISA_JAVA), 3916 #undef _TRANSFER 3917 #define _TRANSFER 0 3918 DOP16_DOP32 ("bclri", 3919 OPCODE_INFO2 (0x3880, 3920 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3921 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3922 OPCODE_INFO3 (0x3880, 3923 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3924 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 3925 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3926 CSKYV2_ISA_E1, 3927 OPCODE_INFO3 (0xc4002820, 3928 (0_4, AREG, OPRND_SHIFT_0_BIT), 3929 (16_20, AREG, OPRND_SHIFT_0_BIT), 3930 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3931 OPCODE_INFO2 (0xc4002820, 3932 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3933 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3934 CSKYV2_ISA_1E2), 3935 DOP16_DOP32 ("bseti", 3936 OPCODE_INFO2 (0x38a0, 3937 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3938 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3939 OPCODE_INFO3 (0x38a0, 3940 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3941 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 3942 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3943 CSKYV2_ISA_E1, 3944 OPCODE_INFO3 (0xc4002840, 3945 (0_4, AREG, OPRND_SHIFT_0_BIT), 3946 (16_20, AREG, OPRND_SHIFT_0_BIT), 3947 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3948 OPCODE_INFO2 (0xc4002840, 3949 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3950 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3951 CSKYV2_ISA_1E2), 3952 OP16_OP32_WITH_WORK ("btsti", 3953 OPCODE_INFO2 (0x38c0, 3954 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3955 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3956 CSKYV2_ISA_E1, 3957 OPCODE_INFO2 (0xc4002880, 3958 (16_20, AREG, OPRND_SHIFT_0_BIT), 3959 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3960 CSKYV2_ISA_1E2, v2_work_btsti), 3961 DOP16_DOP32 ("lsli", 3962 OPCODE_INFO3 (0x4000, 3963 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 3964 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3965 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3966 OPCODE_INFO2 (0x4000, 3967 (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), 3968 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3969 CSKYV2_ISA_E1, 3970 OPCODE_INFO3 (0xc4004820, 3971 (0_4, AREG, OPRND_SHIFT_0_BIT), 3972 (16_20, AREG, OPRND_SHIFT_0_BIT), 3973 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3974 OPCODE_INFO2 (0xc4004820, 3975 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3976 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3977 CSKYV2_ISA_1E2), 3978 DOP16_DOP32 ("lsri", 3979 OPCODE_INFO3 (0x4800, 3980 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 3981 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3982 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3983 OPCODE_INFO2 (0x4800, 3984 (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), 3985 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 3986 CSKYV2_ISA_E1, 3987 OPCODE_INFO3 (0xc4004840, 3988 (0_4, AREG, OPRND_SHIFT_0_BIT), 3989 (16_20, AREG, OPRND_SHIFT_0_BIT), 3990 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3991 OPCODE_INFO2 (0xc4004840, 3992 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 3993 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 3994 CSKYV2_ISA_1E2), 3995 OP16_OP32 ("asri", 3996 OPCODE_INFO3 (0x5000, 3997 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 3998 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 3999 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 4000 CSKYV2_ISA_E1, 4001 OPCODE_INFO3 (0xc4004880, 4002 (0_4, AREG, OPRND_SHIFT_0_BIT), 4003 (16_20, AREG, OPRND_SHIFT_0_BIT), 4004 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 4005 CSKYV2_ISA_1E2), 4006 DOP16_DOP32_WITH_WORK ("addc", 4007 OPCODE_INFO2 (0x6001, 4008 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4009 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4010 OPCODE_INFO3 (0x6001, 4011 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4012 (2_5, GREG0_15, OPRND_SHIFT_0_BIT), 4013 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4014 CSKYV2_ISA_E1, 4015 OPCODE_INFO3 (0xc4000040, 4016 (0_4, AREG, OPRND_SHIFT_0_BIT), 4017 (16_20, AREG, OPRND_SHIFT_0_BIT), 4018 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4019 OPCODE_INFO2 (0xc4000040, 4020 (0_4or16_20, AREG, OPRND_SHIFT_0_BIT), 4021 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4022 CSKYV2_ISA_1E2, 4023 v2_work_addc), 4024 DOP16_DOP32 ("subc", 4025 OPCODE_INFO2 (0x6003, 4026 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4027 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4028 OPCODE_INFO3 (0x6003, 4029 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4030 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4031 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4032 CSKYV2_ISA_E1, 4033 OPCODE_INFO3 (0xc4000100, 4034 (0_4, AREG, OPRND_SHIFT_0_BIT), 4035 (16_20, AREG, OPRND_SHIFT_0_BIT), 4036 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4037 OPCODE_INFO2 (0xc4000100, 4038 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4039 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4040 CSKYV2_ISA_1E2), 4041 OP16_OP32 ("cmphs", 4042 OPCODE_INFO2 (0x6400, 4043 (2_5, GREG0_15, OPRND_SHIFT_0_BIT), 4044 (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), 4045 CSKYV2_ISA_E1, 4046 OPCODE_INFO2 (0xc4000420, 4047 (16_20, AREG, OPRND_SHIFT_0_BIT), 4048 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4049 CSKYV2_ISA_2E3), 4050 OP16_OP32 ("cmplt", 4051 OPCODE_INFO2 (0x6401, 4052 (2_5, GREG0_15, OPRND_SHIFT_0_BIT), 4053 (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), 4054 CSKYV2_ISA_E1, 4055 OPCODE_INFO2 (0xc4000440, 4056 (16_20, AREG, OPRND_SHIFT_0_BIT), 4057 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4058 CSKYV2_ISA_2E3), 4059 OP16_OP32 ("cmpne", 4060 OPCODE_INFO2 (0x6402, 4061 (2_5, GREG0_15, OPRND_SHIFT_0_BIT), 4062 (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), 4063 CSKYV2_ISA_E1, 4064 OPCODE_INFO2 (0xc4000480, 4065 (16_20, AREG, OPRND_SHIFT_0_BIT), 4066 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4067 CSKYV2_ISA_2E3), 4068 OP16_OP32 ("mvcv", 4069 OPCODE_INFO1 (0x6403, 4070 (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), 4071 CSKYV2_ISA_E1, 4072 OPCODE_INFO1 (0xc4000600, 4073 (0_4, AREG, OPRND_SHIFT_0_BIT)), 4074 CSKYV2_ISA_2E3), 4075 DOP16_DOP32 ("and", 4076 OPCODE_INFO2 (0x6800, 4077 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4078 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4079 OPCODE_INFO3 (0x6800, 4080 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4081 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4082 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4083 CSKYV2_ISA_E1, 4084 OPCODE_INFO3 (0xc4002020, 4085 (0_4, AREG, OPRND_SHIFT_0_BIT), 4086 (16_20, AREG, OPRND_SHIFT_0_BIT), 4087 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4088 OPCODE_INFO2 (0xc4002020, 4089 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4090 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4091 CSKYV2_ISA_1E2), 4092 DOP16_DOP32 ("andn", 4093 OPCODE_INFO2 (0x6801, 4094 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4095 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4096 OPCODE_INFO3 (0x6801, 4097 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4098 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4099 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4100 CSKYV2_ISA_E1, 4101 OPCODE_INFO3 (0xc4002040, 4102 (0_4, AREG, OPRND_SHIFT_0_BIT), 4103 (16_20, AREG, OPRND_SHIFT_0_BIT), 4104 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4105 OPCODE_INFO2 (0xc4002040, 4106 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4107 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4108 CSKYV2_ISA_1E2), 4109 OP16_OP32 ("tst", 4110 OPCODE_INFO2 (0x6802, 4111 (2_5, GREG0_15, OPRND_SHIFT_0_BIT), 4112 (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), 4113 CSKYV2_ISA_E1, 4114 OPCODE_INFO2 (0xc4002080, 4115 (16_20, AREG, OPRND_SHIFT_0_BIT), 4116 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4117 CSKYV2_ISA_2E3), 4118 OP16_OP32 ("tstnbz", 4119 OPCODE_INFO1 (0x6803, 4120 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4121 CSKYV2_ISA_E1, 4122 OPCODE_INFO1 (0xc4002100, 4123 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4124 CSKYV2_ISA_2E3), 4125 DOP16_DOP32 ("or", 4126 OPCODE_INFO2 (0x6c00, 4127 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4128 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4129 OPCODE_INFO3 (0x6c00, 4130 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4131 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4132 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4133 CSKYV2_ISA_E1, 4134 OPCODE_INFO3 (0xc4002420, 4135 (0_4, AREG, OPRND_SHIFT_0_BIT), 4136 (16_20, AREG, OPRND_SHIFT_0_BIT), 4137 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4138 OPCODE_INFO2 (0xc4002420, 4139 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4140 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4141 CSKYV2_ISA_1E2), 4142 DOP16_DOP32 ("xor", 4143 OPCODE_INFO2 (0x6c01, 4144 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4145 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4146 OPCODE_INFO3 (0x6c01, 4147 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4148 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4149 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4150 CSKYV2_ISA_E1, 4151 OPCODE_INFO3 (0xc4002440, 4152 (0_4, AREG, OPRND_SHIFT_0_BIT), 4153 (16_20, AREG, OPRND_SHIFT_0_BIT), 4154 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4155 OPCODE_INFO2 (0xc4002440, 4156 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4157 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4158 CSKYV2_ISA_1E2), 4159 DOP16_DOP32 ("nor", 4160 OPCODE_INFO2 (0x6c02, 4161 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4162 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4163 OPCODE_INFO3 (0x6c02, 4164 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4165 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4166 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4167 CSKYV2_ISA_E1, 4168 OPCODE_INFO3 (0xc4002480, 4169 (0_4, AREG, OPRND_SHIFT_0_BIT), 4170 (16_20, AREG, OPRND_SHIFT_0_BIT), 4171 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4172 OPCODE_INFO2 (0xc4002480, 4173 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4174 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4175 CSKYV2_ISA_1E2), 4176 OP16_OP32 ("mov", 4177 OPCODE_INFO2 (0x6c03, 4178 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4179 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4180 CSKYV2_ISA_E1, 4181 OPCODE_INFO2 (0xc4004820, 4182 (0_4, AREG, OPRND_SHIFT_0_BIT), 4183 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4184 CSKYV2_ISA_1E2), 4185 OP16_OP32 ("nop", 4186 OPCODE_INFO0 (0x6c03), 4187 CSKYV2_ISA_E1, 4188 OPCODE_INFO0 (0xc4004820), 4189 CSKYV2_ISA_E1), 4190 DOP16_DOP32 ("lsl", 4191 OPCODE_INFO2 (0x7000, 4192 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4193 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4194 OPCODE_INFO3 (0x7000, 4195 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4196 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4197 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4198 CSKYV2_ISA_E1, 4199 OPCODE_INFO3 (0xc4004020, 4200 (0_4, AREG, OPRND_SHIFT_0_BIT), 4201 (16_20, AREG, OPRND_SHIFT_0_BIT), 4202 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4203 OPCODE_INFO2 (0xc4004020, 4204 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4205 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4206 CSKYV2_ISA_1E2), 4207 DOP16_DOP32 ("lsr", 4208 OPCODE_INFO2 (0x7001, 4209 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4210 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4211 OPCODE_INFO3 (0x7001, 4212 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4213 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4214 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4215 CSKYV2_ISA_E1, 4216 OPCODE_INFO3 (0xc4004040, 4217 (0_4, AREG, OPRND_SHIFT_0_BIT), 4218 (16_20, AREG, OPRND_SHIFT_0_BIT), 4219 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4220 OPCODE_INFO2 (0xc4004040, 4221 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4222 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4223 CSKYV2_ISA_1E2), 4224 DOP16_DOP32 ("asr", 4225 OPCODE_INFO2 (0x7002, 4226 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4227 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4228 OPCODE_INFO3 (0x7002, 4229 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4230 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4231 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4232 CSKYV2_ISA_E1, 4233 OPCODE_INFO3 (0xc4004080, 4234 (0_4, AREG, OPRND_SHIFT_0_BIT), 4235 (16_20, AREG, OPRND_SHIFT_0_BIT), 4236 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4237 OPCODE_INFO2 (0xc4004080, 4238 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4239 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4240 CSKYV2_ISA_1E2), 4241 DOP16_DOP32 ("rotl", 4242 OPCODE_INFO2 (0x7003, 4243 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4244 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4245 OPCODE_INFO3 (0x7003, 4246 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4247 (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), 4248 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4249 CSKYV2_ISA_E1, 4250 OPCODE_INFO3 (0xc4004100, 4251 (0_4, AREG, OPRND_SHIFT_0_BIT), 4252 (16_20, AREG, OPRND_SHIFT_0_BIT), 4253 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4254 OPCODE_INFO2 (0xc4004100, 4255 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4256 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4257 CSKYV2_ISA_1E2), 4258 DOP16_DOP32 ("zextb", 4259 OPCODE_INFO2 (0x7400, 4260 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4261 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4262 OPCODE_INFO1 (0x7400, 4263 (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), 4264 CSKYV2_ISA_E1, 4265 OPCODE_INFO2 (0xc40054e0, 4266 (0_4, AREG, OPRND_SHIFT_0_BIT), 4267 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4268 OPCODE_INFO1 (0xc40054e0, 4269 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 4270 CSKYV2_ISA_2E3), 4271 DOP16_DOP32 ("zexth", 4272 OPCODE_INFO2 (0x7401, 4273 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4274 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4275 OPCODE_INFO1 (0x7401, 4276 (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), 4277 CSKYV2_ISA_E1, 4278 OPCODE_INFO2 (0xc40055e0, 4279 (0_4, AREG, OPRND_SHIFT_0_BIT), 4280 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4281 OPCODE_INFO1 (0xc40055e0, 4282 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 4283 CSKYV2_ISA_2E3), 4284 DOP16_DOP32 ("sextb", 4285 OPCODE_INFO2 (0x7402, 4286 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4287 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4288 OPCODE_INFO1 (0x7402, 4289 (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), 4290 CSKYV2_ISA_E1, 4291 OPCODE_INFO2 (0xc40058e0, 4292 (0_4, AREG, OPRND_SHIFT_0_BIT), 4293 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4294 OPCODE_INFO1 (0xc40058e0, 4295 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 4296 CSKYV2_ISA_2E3), 4297 DOP16_DOP32 ("sexth", 4298 OPCODE_INFO2 (0x7403, 4299 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4300 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4301 OPCODE_INFO1 (0x7403, 4302 (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), 4303 CSKYV2_ISA_E1, 4304 OPCODE_INFO2 (0xc40059e0, 4305 (0_4, AREG, OPRND_SHIFT_0_BIT), 4306 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4307 OPCODE_INFO1 (0xc40059e0, 4308 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 4309 CSKYV2_ISA_2E3), 4310 OP32 ("zext", 4311 OPCODE_INFO4 (0xc4005400, 4312 (0_4, AREG, OPRND_SHIFT_0_BIT), 4313 (16_20, AREG, OPRND_SHIFT_0_BIT), 4314 (5_9, IMM5b, OPRND_SHIFT_0_BIT), 4315 (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)), 4316 CSKYV2_ISA_2E3), 4317 OP32 ("sext", 4318 OPCODE_INFO4 (0xc4005800, 4319 (0_4, AREG, OPRND_SHIFT_0_BIT), 4320 (16_20, AREG, OPRND_SHIFT_0_BIT), 4321 (5_9, IMM5b, OPRND_SHIFT_0_BIT), 4322 (21_25, IMM5b_LS, OPRND_SHIFT_0_BIT)), 4323 CSKYV2_ISA_2E3), 4324 #undef _TRANSFER 4325 #define _TRANSFER 2 4326 OP16_OP32 ("rts", 4327 OPCODE_INFO0 (0x783c), 4328 CSKYV2_ISA_E1, 4329 OPCODE_INFO0 (0xe8cf0000), 4330 CSKYV2_ISA_E1), 4331 #undef _TRANSFER 4332 #define _TRANSFER 1 4333 OP16_OP32 ("jmp", 4334 OPCODE_INFO1 (0x7800, 4335 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4336 CSKYV2_ISA_E1, 4337 OPCODE_INFO1 (0xe8c00000, 4338 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4339 CSKYV2_ISA_2E3), 4340 #undef _TRANSFER 4341 #define _TRANSFER 0 4342 OP16_OP32 ("revb", 4343 OPCODE_INFO2 (0x7802, 4344 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4345 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4346 CSKYV2_ISA_1E2, 4347 OPCODE_INFO2 (0xc4006080, 4348 (0_4, AREG, OPRND_SHIFT_0_BIT), 4349 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4350 CSKYV2_ISA_2E3), 4351 OP16_OP32 ("revh", 4352 OPCODE_INFO2 (0x7803, 4353 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4354 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4355 CSKYV2_ISA_1E2, 4356 OPCODE_INFO2 (0xc4006100, 4357 (0_4, AREG, OPRND_SHIFT_0_BIT), 4358 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4359 CSKYV2_ISA_2E3), 4360 OP16_OP32 ("jsr", 4361 OPCODE_INFO1 (0x7bc1, 4362 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4363 CSKYV2_ISA_E1, 4364 OPCODE_INFO1 (0xe8e00000, 4365 (16_20, AREG, OPRND_SHIFT_0_BIT)), 4366 CSKYV2_ISA_2E3), 4367 DOP16_DOP32 ("mult", 4368 OPCODE_INFO2 (0x7c00, 4369 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4370 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4371 OPCODE_INFO3 (0x7c00, 4372 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4373 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4374 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4375 CSKYV2_ISA_E1, 4376 OPCODE_INFO3 (0xc4008420, 4377 (0_4, AREG, OPRND_SHIFT_0_BIT), 4378 (16_20, AREG, OPRND_SHIFT_0_BIT), 4379 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4380 OPCODE_INFO2 (0xc4008420, 4381 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4382 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4383 CSKYV2_ISA_1E2), 4384 OP16 ("mul", 4385 OPCODE_INFO2 (0x7c00, 4386 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4387 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4388 CSKYV2_ISA_E1), 4389 DOP16_DOP32 ("mulsh", 4390 OPCODE_INFO2 (0x7c01, 4391 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4392 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4393 OPCODE_INFO3 (0x7c01, 4394 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4395 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), 4396 (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), 4397 CSKYV2_ISA_2E3, 4398 OPCODE_INFO3 (0xc4009020, 4399 (0_4, AREG, OPRND_SHIFT_0_BIT), 4400 (16_20, AREG, OPRND_SHIFT_0_BIT), 4401 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4402 OPCODE_INFO2 (0xc4009020, 4403 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4404 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4405 CSKYV2_ISA_2E3), 4406 OP16 ("muls.h", 4407 OPCODE_INFO2 (0x7c01, 4408 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4409 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4410 CSKYV2_ISA_2E3), 4411 DOP32 ("mulsw", 4412 OPCODE_INFO3 (0xc4009420, 4413 (0_4, AREG, OPRND_SHIFT_0_BIT), 4414 (16_20, AREG, OPRND_SHIFT_0_BIT), 4415 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4416 OPCODE_INFO2 (0xc4009420, 4417 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4418 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4419 CSKY_ISA_DSPE60), 4420 OP16_OP32 ("ld.b", 4421 SOPCODE_INFO2 (0x8000, 4422 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4423 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4424 (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), 4425 CSKYV2_ISA_E1, 4426 SOPCODE_INFO2 (0xd8000000, 4427 (21_25, AREG, OPRND_SHIFT_0_BIT), 4428 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4429 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 4430 CSKYV2_ISA_E1), 4431 OP16_OP32 ("ldb", 4432 SOPCODE_INFO2 (0x8000, 4433 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4434 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4435 (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), 4436 CSKYV2_ISA_E1, 4437 SOPCODE_INFO2 (0xd8000000, 4438 (21_25, AREG, OPRND_SHIFT_0_BIT), 4439 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4440 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 4441 CSKYV2_ISA_E1), 4442 OP16_OP32 ("st.b", 4443 SOPCODE_INFO2 (0xa000, 4444 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4445 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4446 (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), 4447 CSKYV2_ISA_E1, 4448 SOPCODE_INFO2 (0xdc000000, 4449 (21_25, AREG, OPRND_SHIFT_0_BIT), 4450 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4451 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 4452 CSKYV2_ISA_E1), 4453 OP16_OP32 ("stb", 4454 SOPCODE_INFO2 (0xa000, 4455 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4456 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4457 (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), 4458 CSKYV2_ISA_E1, 4459 SOPCODE_INFO2 (0xdc000000, 4460 (21_25, AREG, OPRND_SHIFT_0_BIT), 4461 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4462 (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), 4463 CSKYV2_ISA_E1), 4464 4465 OP16_OP32 ("ld.h", 4466 SOPCODE_INFO2 (0x8800, 4467 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4468 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4469 (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), 4470 CSKYV2_ISA_E1, 4471 SOPCODE_INFO2 (0xd8001000, 4472 (21_25, AREG, OPRND_SHIFT_0_BIT), 4473 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4474 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 4475 CSKYV2_ISA_E1), 4476 OP16_OP32 ("ldh", 4477 SOPCODE_INFO2 (0x8800, 4478 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4479 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4480 (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), 4481 CSKYV2_ISA_E1, 4482 SOPCODE_INFO2 (0xd8001000, 4483 (21_25, AREG, OPRND_SHIFT_0_BIT), 4484 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4485 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 4486 CSKYV2_ISA_E1), 4487 OP16_OP32 ("st.h", 4488 SOPCODE_INFO2 (0xa800, 4489 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4490 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4491 (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), 4492 CSKYV2_ISA_E1, 4493 SOPCODE_INFO2 (0xdc001000, 4494 (21_25, AREG, OPRND_SHIFT_0_BIT), 4495 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4496 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 4497 CSKYV2_ISA_E1), 4498 OP16_OP32 ("sth", 4499 SOPCODE_INFO2 (0xa800, 4500 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4501 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4502 (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), 4503 CSKYV2_ISA_E1, 4504 SOPCODE_INFO2 (0xdc001000, 4505 (21_25, AREG, OPRND_SHIFT_0_BIT), 4506 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4507 (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), 4508 CSKYV2_ISA_E1), 4509 DOP16_OP32 ("ld.w", 4510 SOPCODE_INFO2 (0x9000, 4511 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4512 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4513 (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), 4514 SOPCODE_INFO2 (0x9800, 4515 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4516 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4517 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4518 CSKYV2_ISA_E1, 4519 SOPCODE_INFO2 (0xd8002000, 4520 (21_25, AREG, OPRND_SHIFT_0_BIT), 4521 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4522 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4523 CSKYV2_ISA_E1), 4524 DOP16_OP32 ("ldw", 4525 SOPCODE_INFO2 (0x9000, 4526 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4527 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4528 (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), 4529 SOPCODE_INFO2 (0x9800, 4530 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4531 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4532 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4533 CSKYV2_ISA_E1, 4534 SOPCODE_INFO2 (0xd8002000, 4535 (21_25, AREG, OPRND_SHIFT_0_BIT), 4536 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4537 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4538 CSKYV2_ISA_E1), 4539 DOP16_OP32 ("ld", 4540 SOPCODE_INFO2 (0x9000, 4541 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4542 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4543 (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), 4544 SOPCODE_INFO2 (0x9800, 4545 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4546 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4547 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4548 CSKYV2_ISA_E1, 4549 SOPCODE_INFO2 (0xd8002000, 4550 (21_25, AREG, OPRND_SHIFT_0_BIT), 4551 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4552 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4553 CSKYV2_ISA_E1), 4554 DOP16_OP32 ("st.w", 4555 SOPCODE_INFO2 (0xb000, 4556 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4557 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4558 (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), 4559 SOPCODE_INFO2 (0xb800, 4560 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4561 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4562 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4563 CSKYV2_ISA_E1, 4564 SOPCODE_INFO2 (0xdc002000, 4565 (21_25, AREG, OPRND_SHIFT_0_BIT), 4566 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4567 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4568 CSKYV2_ISA_E1), 4569 DOP16_OP32 ("stw", 4570 SOPCODE_INFO2 (0xb000, 4571 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4572 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4573 (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), 4574 SOPCODE_INFO2 (0xb800, 4575 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4576 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4577 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4578 CSKYV2_ISA_E1, 4579 SOPCODE_INFO2 (0xdc002000, 4580 (21_25, AREG, OPRND_SHIFT_0_BIT), 4581 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4582 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4583 CSKYV2_ISA_E1), 4584 DOP16_OP32 ("st", 4585 SOPCODE_INFO2 (0xb000, 4586 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4587 BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4588 (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), 4589 SOPCODE_INFO2 (0xb800, 4590 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4591 BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), 4592 (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), 4593 CSKYV2_ISA_E1, 4594 SOPCODE_INFO2 (0xdc002000, 4595 (21_25, AREG, OPRND_SHIFT_0_BIT), 4596 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 4597 (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), 4598 CSKYV2_ISA_E1), 4599 #ifdef BUILD_AS 4600 DOP16_DOP32_WITH_WORK ("addi", 4601 OPCODE_INFO2 (0x2000, 4602 (NONE, AREG, OPRND_SHIFT_0_BIT), 4603 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4604 OPCODE_INFO3 (0x2000, 4605 (NONE, AREG, OPRND_SHIFT_0_BIT), 4606 (NONE, AREG, OPRND_SHIFT_0_BIT), 4607 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4608 CSKYV2_ISA_E1, 4609 OPCODE_INFO2 (0xe4000000, 4610 (NONE, AREG, OPRND_SHIFT_0_BIT), 4611 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4612 OPCODE_INFO3 (0xe4000000, 4613 (NONE, AREG, OPRND_SHIFT_0_BIT), 4614 (NONE, AREG, OPRND_SHIFT_0_BIT), 4615 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4616 CSKYV2_ISA_1E2, 4617 v2_work_addi), 4618 #else 4619 DOP16 ("addi", 4620 OPCODE_INFO2 (0x2000, 4621 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4622 (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), 4623 OPCODE_INFO3 (0x5802, 4624 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4625 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4626 (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), 4627 CSKYV2_ISA_E1), 4628 DOP16 ("addi", 4629 OPCODE_INFO3 (0x1800, 4630 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4631 (NONE, REGsp, OPRND_SHIFT_0_BIT), 4632 (0_7, IMM8b_LS2, OPRND_SHIFT_0_BIT)), 4633 OPCODE_INFO3 (0x1400, 4634 (NONE, REGsp, OPRND_SHIFT_0_BIT), 4635 (NONE, REGsp, OPRND_SHIFT_0_BIT), 4636 (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), 4637 CSKYV2_ISA_E1), 4638 DOP32 ("addi", 4639 OPCODE_INFO3 (0xe4000000, 4640 (21_25, AREG, OPRND_SHIFT_0_BIT), 4641 (16_20, AREG, OPRND_SHIFT_0_BIT), 4642 (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), 4643 OPCODE_INFO3 (0xcc1c0000, 4644 (21_25, AREG, OPRND_SHIFT_0_BIT), 4645 (NONE, REG_r28, OPRND_SHIFT_0_BIT), 4646 (0_17, OIMM18b, OPRND_SHIFT_0_BIT)), 4647 CSKYV2_ISA_1E2), 4648 #endif 4649 #ifdef BUILD_AS 4650 DOP16_DOP32_WITH_WORK ("subi", 4651 OPCODE_INFO2 (0x2800, 4652 (NONE, AREG, OPRND_SHIFT_0_BIT), 4653 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4654 OPCODE_INFO3 (0x2800, 4655 (NONE, AREG, OPRND_SHIFT_0_BIT), 4656 (NONE, AREG, OPRND_SHIFT_0_BIT), 4657 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4658 CSKYV2_ISA_E1, 4659 OPCODE_INFO2 (0xe4001000, 4660 (NONE, AREG, OPRND_SHIFT_0_BIT), 4661 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4662 OPCODE_INFO3 (0xe4001000, 4663 (NONE, AREG, OPRND_SHIFT_0_BIT), 4664 (NONE, AREG, OPRND_SHIFT_0_BIT), 4665 (NONE, IMM32b, OPRND_SHIFT_0_BIT)), 4666 CSKYV2_ISA_1E2, v2_work_subi), 4667 #else 4668 DOP16 ("subi", 4669 OPCODE_INFO2 (0x2800, 4670 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4671 (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), 4672 OPCODE_INFO3 (0x5803, 4673 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4674 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4675 (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), 4676 CSKYV2_ISA_E1), 4677 OP32 ("subi", 4678 OPCODE_INFO3 (0xe4001000, 4679 (21_25, AREG, OPRND_SHIFT_0_BIT), 4680 (16_20, AREG, OPRND_SHIFT_0_BIT), 4681 (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), 4682 CSKYV2_ISA_1E2), 4683 OP16 ("subi", 4684 OPCODE_INFO3 (0x1420, 4685 (NONE, REGsp, OPRND_SHIFT_0_BIT), 4686 (NONE, REGsp, OPRND_SHIFT_0_BIT), 4687 (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), 4688 CSKYV2_ISA_E1), 4689 #endif 4690 DOP16_DOP32_WITH_WORK ("addu", 4691 OPCODE_INFO2 (0x6000, 4692 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4693 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4694 OPCODE_INFO3 (0x5800, 4695 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4696 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4697 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 4698 CSKYV2_ISA_E1, 4699 OPCODE_INFO3 (0xc4000020, 4700 (0_4, AREG, OPRND_SHIFT_0_BIT), 4701 (16_20, AREG, OPRND_SHIFT_0_BIT), 4702 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4703 OPCODE_INFO2 (0xc4000020, 4704 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4705 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4706 CSKYV2_ISA_E1, 4707 v2_work_add_sub), 4708 DOP16_DOP32_WITH_WORK ("add", 4709 OPCODE_INFO2 (0x6000, 4710 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4711 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4712 OPCODE_INFO3 (0x5800, 4713 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4714 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4715 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 4716 CSKYV2_ISA_E1, 4717 OPCODE_INFO3 (0xc4000020, 4718 (0_4, AREG, OPRND_SHIFT_0_BIT), 4719 (16_20, AREG, OPRND_SHIFT_0_BIT), 4720 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4721 OPCODE_INFO2 (0xc4000020, 4722 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4723 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4724 CSKYV2_ISA_E1, 4725 v2_work_add_sub), 4726 DOP16_DOP32_WITH_WORK ("subu", 4727 OPCODE_INFO2 (0x6002, 4728 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4729 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4730 OPCODE_INFO3 (0x5801, 4731 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4732 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4733 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 4734 CSKYV2_ISA_E1, 4735 OPCODE_INFO3 (0xc4000080, 4736 (0_4, AREG, OPRND_SHIFT_0_BIT), 4737 (16_20, AREG, OPRND_SHIFT_0_BIT), 4738 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4739 OPCODE_INFO2 (0xc4000080, 4740 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4741 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4742 CSKYV2_ISA_E1, 4743 v2_work_add_sub), 4744 DOP16_DOP32_WITH_WORK ("sub", 4745 OPCODE_INFO2 (0x6002, 4746 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 4747 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 4748 OPCODE_INFO3 (0x5801, 4749 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4750 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 4751 (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), 4752 CSKYV2_ISA_E1, 4753 OPCODE_INFO3 (0xc4000080, 4754 (0_4, AREG, OPRND_SHIFT_0_BIT), 4755 (16_20, AREG, OPRND_SHIFT_0_BIT), 4756 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4757 OPCODE_INFO2 (0xc4000080, 4758 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 4759 (21_25, AREG, OPRND_SHIFT_0_BIT)), 4760 CSKYV2_ISA_E1, 4761 v2_work_add_sub), 4762 OP32_WITH_WORK ("fmovis", 4763 OPCODE_INFO2 (0xf4001c00, 4764 (0_3, FREG, OPRND_SHIFT_0_BIT), 4765 (4_7or16_24, SFLOAT, OPRND_SHIFT_2_BIT)), 4766 CSKY_ISA_FLOAT_1E3, 4767 float_work_fmovi), 4768 OP32_WITH_WORK ("fmovid", 4769 OPCODE_INFO2 (0xf4001e00, 4770 (0_3, FREG, OPRND_SHIFT_0_BIT), 4771 (4_7or16_24, DFLOAT, OPRND_SHIFT_2_BIT)), 4772 CSKY_ISA_FLOAT_3E4, 4773 float_work_fmovi), 4774 #undef _RELOC32 4775 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM26BY2 4776 OP32 ("bsr", 4777 OPCODE_INFO1 (0xe0000000, 4778 (0_25, OFF26b, OPRND_SHIFT_1_BIT)), 4779 CSKYV2_ISA_E1), 4780 #undef _RELOC32 4781 #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18 4782 OP32 ("lrs.b", 4783 OPCODE_INFO2 (0xcc000000, 4784 (21_25, AREG, OPRND_SHIFT_0_BIT), 4785 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4786 CSKYV2_ISA_2E3), 4787 OP32 ("srs.b", 4788 OPCODE_INFO2 (0xcc100000, 4789 (21_25, AREG, OPRND_SHIFT_0_BIT), 4790 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4791 CSKYV2_ISA_2E3), 4792 #undef _RELOC32 4793 #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 4794 OP32 ("lrs.h", 4795 OPCODE_INFO2 (0xcc040000, 4796 (21_25, AREG, OPRND_SHIFT_0_BIT), 4797 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4798 CSKYV2_ISA_2E3), 4799 OP32 ("srs.h", 4800 OPCODE_INFO2 (0xcc140000, 4801 (21_25, AREG, OPRND_SHIFT_0_BIT), 4802 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4803 CSKYV2_ISA_2E3), 4804 #undef _RELOC32 4805 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 4806 OP32 ("flrws", 4807 OPCODE_INFO2 (0xf4003800, 4808 (0_3, FREG, OPRND_SHIFT_0_BIT), 4809 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 4810 CSKY_ISA_FLOAT_1E3), 4811 OP32 ("flrwd", 4812 OPCODE_INFO2 (0xf4003900, 4813 (0_3, FREG, OPRND_SHIFT_0_BIT), 4814 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 4815 CSKY_ISA_FLOAT_3E4), 4816 #undef _RELOC32 4817 #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 4818 OP32_WITH_WORK ("lrs.w", 4819 OPCODE_INFO2 (0xcc080000, 4820 (21_25, AREG, OPRND_SHIFT_0_BIT), 4821 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4822 CSKYV2_ISA_2E3, 4823 v2_work_lrsrsw), 4824 OP32_WITH_WORK ("srs.w", 4825 OPCODE_INFO2 (0xcc180000, 4826 (21_25, AREG, OPRND_SHIFT_0_BIT), 4827 (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 4828 CSKYV2_ISA_2E3, 4829 v2_work_lrsrsw), 4830 4831 #undef _RELOC32 4832 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 4833 OP32_WITH_WORK ("jsri", 4834 OPCODE_INFO1 (0xeae00000, 4835 (0_15, OFF16b, OPRND_SHIFT_2_BIT)), 4836 CSKYV2_ISA_2E3, 4837 v2_work_jsri), 4838 #undef _RELOC32 4839 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY2 4840 OP32 ("bez", 4841 OPCODE_INFO2 (0xe9000000, 4842 (16_20, AREG, OPRND_SHIFT_0_BIT), 4843 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4844 CSKYV2_ISA_2E3), 4845 OP32 ("bnez", 4846 OPCODE_INFO2 (0xe9200000, 4847 (16_20, AREG, OPRND_SHIFT_0_BIT), 4848 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4849 CSKYV2_ISA_2E3), 4850 OP32 ("bhz", 4851 OPCODE_INFO2 (0xe9400000, 4852 (16_20, AREG, OPRND_SHIFT_0_BIT), 4853 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4854 CSKYV2_ISA_2E3), 4855 OP32 ("blsz", 4856 OPCODE_INFO2 (0xe9600000, 4857 (16_20, AREG, OPRND_SHIFT_0_BIT), 4858 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4859 CSKYV2_ISA_2E3), 4860 OP32 ("blz", 4861 OPCODE_INFO2 (0xe9800000, 4862 (16_20, AREG, OPRND_SHIFT_0_BIT), 4863 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4864 CSKYV2_ISA_2E3), 4865 OP32 ("bhsz", 4866 OPCODE_INFO2 (0xe9a00000, 4867 (16_20, AREG, OPRND_SHIFT_0_BIT), 4868 (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), 4869 CSKYV2_ISA_2E3), 4870 #undef _RELAX 4871 #undef _RELOC16 4872 #undef _TRANSFER 4873 #define _TRANSFER 1 4874 #define _RELAX 1 4875 #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM10BY2 4876 OP16_OP32 ("br", 4877 OPCODE_INFO1 (0x0400, 4878 (0_9, UNCOND10b, OPRND_SHIFT_1_BIT)), 4879 CSKYV2_ISA_E1, 4880 OPCODE_INFO1 (0xe8000000, 4881 (0_15, UNCOND16b, OPRND_SHIFT_1_BIT)), 4882 CSKYV2_ISA_E1), 4883 #undef _TRANSFER 4884 #define _TRANSFER 0 4885 OP16_OP32 ("bt", 4886 OPCODE_INFO1 (0x0800, 4887 (0_9, COND10b, OPRND_SHIFT_1_BIT)), 4888 CSKYV2_ISA_E1, 4889 OPCODE_INFO1 (0xe8600000, 4890 (0_15, COND16b, OPRND_SHIFT_1_BIT)), 4891 CSKYV2_ISA_1E2), 4892 OP16_OP32 ("bf", 4893 OPCODE_INFO1 (0x0c00, 4894 (0_9, COND10b, OPRND_SHIFT_1_BIT)), 4895 CSKYV2_ISA_E1, 4896 OPCODE_INFO1 (0xe8400000, 4897 (0_15, COND16b, OPRND_SHIFT_1_BIT)), 4898 CSKYV2_ISA_1E2), 4899 #undef _RELAX 4900 #undef _RELOC16 4901 #define _RELAX 0 4902 #define _RELOC16 0 4903 OP32 ("bnezad", 4904 OPCODE_INFO2 (0xe8200000, 4905 (16_20, AREG, OPRND_SHIFT_0_BIT), 4906 (0_15, COND16b, OPRND_SHIFT_1_BIT)), 4907 CSKYV2_ISA_3E3R2), 4908 #undef _RELOC16 4909 #undef _RELOC32 4910 #define _RELOC16 0 4911 #define _RELOC32 0 4912 #undef _TRANSFER 4913 #define _TRANSFER 1 4914 OP16_WITH_WORK ("jbr", 4915 OPCODE_INFO1 (0x0400, 4916 (0_10, UNCOND10b, OPRND_SHIFT_1_BIT)), 4917 CSKYV2_ISA_E1, 4918 v2_work_jbr), 4919 #undef _TRANSFER 4920 #define _TRANSFER 0 4921 OP16_WITH_WORK ("jbt", 4922 OPCODE_INFO1 (0x0800, 4923 (0_10, COND10b, OPRND_SHIFT_1_BIT)), 4924 CSKYV2_ISA_E1, 4925 v2_work_jbtf), 4926 OP16_WITH_WORK ("jbf", 4927 OPCODE_INFO1 (0x0c00, 4928 (0_10, COND10b, OPRND_SHIFT_1_BIT)), 4929 CSKYV2_ISA_E1, 4930 v2_work_jbtf), 4931 OP32_WITH_WORK ("jbsr", 4932 OPCODE_INFO1 (0xe0000000, 4933 (0_25, OFF26b, OPRND_SHIFT_1_BIT)), 4934 CSKYV2_ISA_E1, 4935 v2_work_jbsr), 4936 OP32_WITH_WORK ("movih", 4937 OPCODE_INFO2 (0xea200000, 4938 (16_20, AREG, OPRND_SHIFT_0_BIT), 4939 (0_15, IMM16b_MOVIH, OPRND_SHIFT_0_BIT)), 4940 CSKYV2_ISA_1E2, 4941 v2_work_movih), 4942 OP32_WITH_WORK ("ori", 4943 OPCODE_INFO3 (0xec000000, 4944 (21_25, AREG, OPRND_SHIFT_0_BIT), 4945 (16_20, AREG, OPRND_SHIFT_0_BIT), 4946 (0_15, IMM16b_ORI, OPRND_SHIFT_0_BIT)), 4947 CSKYV2_ISA_1E2, 4948 v2_work_ori), 4949 DOP32_WITH_WORK ("bgeni", 4950 OPCODE_INFO2 (0xea000000, 4951 (16_20, AREG, OPRND_SHIFT_0_BIT), 4952 (0_4, IMM4b, OPRND_SHIFT_0_BIT)), 4953 OPCODE_INFO2 (0xea200000, 4954 (16_20, AREG, OPRND_SHIFT_0_BIT), 4955 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 4956 CSKYV2_ISA_E1, 4957 v2_work_bgeni), 4958 #undef _RELOC16 4959 #undef _RELOC32 4960 #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM7BY4 4961 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 4962 DOP16_OP32_WITH_WORK ("lrw", 4963 OPCODE_INFO2 (0x1000, 4964 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4965 (0_4or8_9, CONSTANT, OPRND_SHIFT_2_BIT)), 4966 OPCODE_INFO2 (0x0000, 4967 (5_7, GREG0_7, OPRND_SHIFT_0_BIT), 4968 (0_4or8_9, ELRW_CONSTANT, OPRND_SHIFT_2_BIT)), 4969 CSKYV2_ISA_E1, 4970 OPCODE_INFO2 (0xea800000, 4971 (16_20, AREG, OPRND_SHIFT_0_BIT), 4972 (0_15, CONSTANT, OPRND_SHIFT_2_BIT)), 4973 CSKYV2_ISA_E1, 4974 v2_work_lrw), 4975 #undef _RELOC16 4976 #undef _RELOC32 4977 #define _RELOC16 0 4978 #define _RELOC32 0 4979 4980 #undef _RELAX 4981 #define _RELAX 1 4982 OP32 ("jbez", 4983 OPCODE_INFO2 (0xe9000000, 4984 (16_20, AREG, OPRND_SHIFT_0_BIT), 4985 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 4986 CSKYV2_ISA_2E3), 4987 OP32 ("jbnez", 4988 OPCODE_INFO2 (0xe9200000, 4989 (16_20, AREG, OPRND_SHIFT_0_BIT), 4990 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 4991 CSKYV2_ISA_2E3), 4992 OP32 ("jbhz", 4993 OPCODE_INFO2 (0xe9400000, 4994 (16_20, AREG, OPRND_SHIFT_0_BIT), 4995 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 4996 CSKYV2_ISA_2E3), 4997 OP32 ("jblsz", 4998 OPCODE_INFO2 (0xe9600000, 4999 (16_20, AREG, OPRND_SHIFT_0_BIT), 5000 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 5001 CSKYV2_ISA_2E3), 5002 OP32 ("jblz", 5003 OPCODE_INFO2 (0xe9800000, 5004 (16_20, AREG, OPRND_SHIFT_0_BIT), 5005 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 5006 CSKYV2_ISA_2E3), 5007 OP32 ("jbhsz", 5008 OPCODE_INFO2 (0xe9a00000, 5009 (16_20, AREG, OPRND_SHIFT_0_BIT), 5010 (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), 5011 CSKYV2_ISA_2E3), 5012 #undef _RELAX 5013 #define _RELAX 0 5014 5015 /* CK860 instructions. */ 5016 OP32 ("sync.is", 5017 OPCODE_INFO0 (0xc2200420), 5018 CSKYV2_ISA_10E60), 5019 OP32 ("sync.i", 5020 OPCODE_INFO0 (0xc0200420), 5021 CSKYV2_ISA_10E60), 5022 OP32 ("sync.s", 5023 OPCODE_INFO0 (0xc2000420), 5024 CSKYV2_ISA_10E60), 5025 OP32 ("bar.brwarw", 5026 OPCODE_INFO0 (0xc000842f), 5027 CSKYV2_ISA_10E60), 5028 OP32 ("bar.brwarws", 5029 OPCODE_INFO0 (0xc200842f), 5030 CSKYV2_ISA_10E60), 5031 OP32 ("bar.brar", 5032 OPCODE_INFO0 (0xc0008425), 5033 CSKYV2_ISA_10E60), 5034 OP32 ("bar.brars", 5035 OPCODE_INFO0 (0xc2008425), 5036 CSKYV2_ISA_10E60), 5037 OP32 ("bar.bwaw", 5038 OPCODE_INFO0 (0xc000842a), 5039 CSKYV2_ISA_10E60), 5040 OP32 ("bar.bwaws", 5041 OPCODE_INFO0 (0xc200842a), 5042 CSKYV2_ISA_10E60), 5043 OP32 ("icache.iall", 5044 OPCODE_INFO0 (0xc1009020), 5045 CSKYV2_ISA_10E60), 5046 OP32 ("icache.ialls", 5047 OPCODE_INFO0 (0xc3009020), 5048 CSKYV2_ISA_10E60), 5049 OP32 ("l2cache.iall", 5050 OPCODE_INFO0 (0xc1009820), 5051 CSKYV2_ISA_10E60), 5052 OP32 ("l2cache.call", 5053 OPCODE_INFO0 (0xc0809820), 5054 CSKYV2_ISA_10E60), 5055 OP32 ("l2cache.ciall", 5056 OPCODE_INFO0 (0xc1809820), 5057 CSKYV2_ISA_10E60), 5058 OP32 ("icache.iva", 5059 OPCODE_INFO1 (0xc1609020, 5060 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5061 CSKYV2_ISA_10E60), 5062 OP32 ("dcache.iall", 5063 OPCODE_INFO0 (0xc1009420), 5064 CSKYV2_ISA_10E60), 5065 OP32 ("dcache.iva", 5066 OPCODE_INFO1 (0xc1609420, 5067 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5068 CSKYV2_ISA_10E60), 5069 OP32 ("dcache.isw", 5070 OPCODE_INFO1 (0xc1409420, 5071 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5072 CSKYV2_ISA_10E60), 5073 OP32 ("dcache.call", 5074 OPCODE_INFO0 (0xc0809420), 5075 CSKYV2_ISA_10E60), 5076 OP32 ("dcache.cva", 5077 OPCODE_INFO1 (0xc0e09420, 5078 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5079 CSKYV2_ISA_10E60), 5080 OP32 ("dcache.cval1", 5081 OPCODE_INFO1 (0xc2e09420, 5082 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5083 CSKYV2_ISA_10E60), 5084 OP32 ("dcache.csw", 5085 OPCODE_INFO1 (0xc0c09420, 5086 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5087 CSKYV2_ISA_10E60), 5088 OP32 ("dcache.ciall", 5089 OPCODE_INFO0 (0xc1809420), 5090 CSKYV2_ISA_10E60), 5091 OP32 ("dcache.civa", 5092 OPCODE_INFO1 (0xc1e09420, 5093 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5094 CSKYV2_ISA_10E60), 5095 OP32 ("dcache.cisw", 5096 OPCODE_INFO1 (0xc1c09420, 5097 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5098 CSKYV2_ISA_10E60), 5099 OP32 ("tlbi.vaa", 5100 OPCODE_INFO1 (0xc0408820, 5101 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5102 CSKYV2_ISA_10E60), 5103 OP32 ("tlbi.vaas", 5104 OPCODE_INFO1 (0xc2408820, 5105 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5106 CSKYV2_ISA_10E60), 5107 OP32 ("tlbi.asid", 5108 OPCODE_INFO1 (0xc0208820, 5109 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5110 CSKYV2_ISA_10E60), 5111 OP32 ("tlbi.asids", 5112 OPCODE_INFO1 (0xc2208820, 5113 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5114 CSKYV2_ISA_10E60), 5115 OP32 ("tlbi.va", 5116 OPCODE_INFO1 (0xc0608820, 5117 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5118 CSKYV2_ISA_10E60), 5119 OP32 ("tlbi.vas", 5120 OPCODE_INFO1 (0xc2608820, 5121 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5122 CSKYV2_ISA_10E60), 5123 OP32 ("tlbi.all", 5124 OPCODE_INFO0 (0xc0008820), 5125 CSKYV2_ISA_10E60), 5126 OP32 ("tlbi.alls", 5127 OPCODE_INFO0 (0xc2008820), 5128 CSKYV2_ISA_10E60), 5129 DOP32 ("sync", 5130 OPCODE_INFO0 (0xc0000420), 5131 OPCODE_INFO1 (0xc0000420, 5132 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 5133 CSKYV2_ISA_E1), 5134 5135 /* The followings are enhance DSP instructions. */ 5136 DOP32_WITH_WORK ("bloop", 5137 OPCODE_INFO3 (0xe9c00000, 5138 (16_20, AREG, OPRND_SHIFT_0_BIT), 5139 (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT), 5140 (12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)), 5141 OPCODE_INFO2 (0xe9c00000, 5142 (16_20, AREG, OPRND_SHIFT_0_BIT), 5143 (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT)), 5144 CSKY_ISA_DSP_ENHANCE, 5145 dsp_work_bloop), 5146 /* The followings are ld/st instructions. */ 5147 OP32 ("ldbi.b", 5148 OPCODE_INFO2 (0xd0008000, 5149 (0_4, AREG, OPRND_SHIFT_0_BIT), 5150 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5151 CSKY_ISA_DSP_ENHANCE), 5152 OP32 ("ldbi.h", 5153 OPCODE_INFO2 (0xd0008400, 5154 (0_4, AREG, OPRND_SHIFT_0_BIT), 5155 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5156 CSKY_ISA_DSP_ENHANCE), 5157 OP32 ("ldbi.w", 5158 OPCODE_INFO2 (0xd0008800, 5159 (0_4, AREG, OPRND_SHIFT_0_BIT), 5160 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5161 CSKY_ISA_DSP_ENHANCE), 5162 OP32 ("pldbi.d", 5163 OPCODE_INFO2 (0xd0008c00, 5164 (0_4, AREG, OPRND_SHIFT_0_BIT), 5165 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5166 CSKY_ISA_DSP_ENHANCE), 5167 OP32 ("ldbi.hs", 5168 OPCODE_INFO2 (0xd0009000, 5169 (0_4, AREG, OPRND_SHIFT_0_BIT), 5170 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5171 CSKY_ISA_DSP_ENHANCE), 5172 OP32 ("ldbi.bs", 5173 OPCODE_INFO2 (0xd0009400, 5174 (0_4, AREG, OPRND_SHIFT_0_BIT), 5175 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5176 CSKY_ISA_DSP_ENHANCE), 5177 OP32 ("stbi.b", 5178 OPCODE_INFO2 (0xd4008000, 5179 (0_4, AREG, OPRND_SHIFT_0_BIT), 5180 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5181 CSKY_ISA_DSP_ENHANCE), 5182 OP32 ("stbi.h", 5183 OPCODE_INFO2 (0xd4008400, 5184 (0_4, AREG, OPRND_SHIFT_0_BIT), 5185 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5186 CSKY_ISA_DSP_ENHANCE), 5187 OP32 ("stbi.w", 5188 OPCODE_INFO2 (0xd4008800, 5189 (0_4, AREG, OPRND_SHIFT_0_BIT), 5190 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), 5191 CSKY_ISA_DSP_ENHANCE), 5192 OP32 ("ldbir.b", 5193 OPCODE_INFO3 (0xd000a000, 5194 (0_4, AREG, OPRND_SHIFT_0_BIT), 5195 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5196 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5197 CSKY_ISA_DSP_ENHANCE), 5198 OP32 ("ldbir.h", 5199 OPCODE_INFO3 (0xd000a400, 5200 (0_4, AREG, OPRND_SHIFT_0_BIT), 5201 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5202 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5203 CSKY_ISA_DSP_ENHANCE), 5204 OP32 ("ldbir.w", 5205 OPCODE_INFO3 (0xd000a800, 5206 (0_4, AREG, OPRND_SHIFT_0_BIT), 5207 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5208 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5209 CSKY_ISA_DSP_ENHANCE), 5210 OP32 ("pldbir.d", 5211 OPCODE_INFO3 (0xd000ac00, 5212 (0_4, AREG, OPRND_SHIFT_0_BIT), 5213 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5214 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5215 CSKY_ISA_DSP_ENHANCE), 5216 OP32 ("ldbir.bs", 5217 OPCODE_INFO3 (0xd000b000, 5218 (0_4, AREG, OPRND_SHIFT_0_BIT), 5219 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5220 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5221 CSKY_ISA_DSP_ENHANCE), 5222 OP32 ("ldbir.hs", 5223 OPCODE_INFO3 (0xd000b400, 5224 (0_4, AREG, OPRND_SHIFT_0_BIT), 5225 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5226 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5227 CSKY_ISA_DSP_ENHANCE), 5228 OP32 ("stbir.b", 5229 OPCODE_INFO3 (0xd400a000, 5230 (0_4, AREG, OPRND_SHIFT_0_BIT), 5231 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5232 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5233 CSKY_ISA_DSP_ENHANCE), 5234 OP32 ("stbir.h", 5235 OPCODE_INFO3 (0xd400a400, 5236 (0_4, AREG, OPRND_SHIFT_0_BIT), 5237 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5238 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5239 CSKY_ISA_DSP_ENHANCE), 5240 OP32 ("stbir.w", 5241 OPCODE_INFO3 (0xd400a800, 5242 (0_4, AREG, OPRND_SHIFT_0_BIT), 5243 (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), 5244 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5245 CSKY_ISA_DSP_ENHANCE), 5246 /* The followings are add/sub instructions. */ 5247 OP32 ("padd.8", 5248 OPCODE_INFO3 (0xf800c040, 5249 (0_4, AREG, OPRND_SHIFT_0_BIT), 5250 (16_20, AREG, OPRND_SHIFT_0_BIT), 5251 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5252 CSKY_ISA_DSP_ENHANCE), 5253 OP32 ("padd.16", 5254 OPCODE_INFO3 (0xf800c000, 5255 (0_4, AREG, OPRND_SHIFT_0_BIT), 5256 (16_20, AREG, OPRND_SHIFT_0_BIT), 5257 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5258 CSKY_ISA_DSP_ENHANCE), 5259 OP32 ("padd.u8.s", 5260 OPCODE_INFO3 (0xf800c140, 5261 (0_4, AREG, OPRND_SHIFT_0_BIT), 5262 (16_20, AREG, OPRND_SHIFT_0_BIT), 5263 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5264 CSKY_ISA_DSP_ENHANCE), 5265 OP32 ("padd.s8.s", 5266 OPCODE_INFO3 (0xf800c1c0, 5267 (0_4, AREG, OPRND_SHIFT_0_BIT), 5268 (16_20, AREG, OPRND_SHIFT_0_BIT), 5269 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5270 CSKY_ISA_DSP_ENHANCE), 5271 OP32 ("padd.u16.s", 5272 OPCODE_INFO3 (0xf800c100, 5273 (0_4, AREG, OPRND_SHIFT_0_BIT), 5274 (16_20, AREG, OPRND_SHIFT_0_BIT), 5275 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5276 CSKY_ISA_DSP_ENHANCE), 5277 OP32 ("padd.s16.s", 5278 OPCODE_INFO3 (0xf800c180, 5279 (0_4, AREG, OPRND_SHIFT_0_BIT), 5280 (16_20, AREG, OPRND_SHIFT_0_BIT), 5281 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5282 CSKY_ISA_DSP_ENHANCE), 5283 OP32 ("add.u32.s", 5284 OPCODE_INFO3 (0xf800c120, 5285 (0_4, AREG, OPRND_SHIFT_0_BIT), 5286 (16_20, AREG, OPRND_SHIFT_0_BIT), 5287 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5288 CSKY_ISA_DSP_ENHANCE), 5289 OP32 ("add.s32.s", 5290 OPCODE_INFO3 (0xf800c1a0, 5291 (0_4, AREG, OPRND_SHIFT_0_BIT), 5292 (16_20, AREG, OPRND_SHIFT_0_BIT), 5293 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5294 CSKY_ISA_DSP_ENHANCE), 5295 OP32 ("psub.8", 5296 OPCODE_INFO3 (0xf800c440, 5297 (0_4, AREG, OPRND_SHIFT_0_BIT), 5298 (16_20, AREG, OPRND_SHIFT_0_BIT), 5299 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5300 CSKY_ISA_DSP_ENHANCE), 5301 OP32 ("psub.16", 5302 OPCODE_INFO3 (0xf800c400, 5303 (0_4, AREG, OPRND_SHIFT_0_BIT), 5304 (16_20, AREG, OPRND_SHIFT_0_BIT), 5305 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5306 CSKY_ISA_DSP_ENHANCE), 5307 OP32 ("psub.u8.s", 5308 OPCODE_INFO3 (0xf800c540, 5309 (0_4, AREG, OPRND_SHIFT_0_BIT), 5310 (16_20, AREG, OPRND_SHIFT_0_BIT), 5311 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5312 CSKY_ISA_DSP_ENHANCE), 5313 OP32 ("psub.s8.s", 5314 OPCODE_INFO3 (0xf800c5c0, 5315 (0_4, AREG, OPRND_SHIFT_0_BIT), 5316 (16_20, AREG, OPRND_SHIFT_0_BIT), 5317 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5318 CSKY_ISA_DSP_ENHANCE), 5319 OP32 ("psub.u16.s", 5320 OPCODE_INFO3 (0xf800c500, 5321 (0_4, AREG, OPRND_SHIFT_0_BIT), 5322 (16_20, AREG, OPRND_SHIFT_0_BIT), 5323 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5324 CSKY_ISA_DSP_ENHANCE), 5325 OP32 ("psub.s16.s", 5326 OPCODE_INFO3 (0xf800c580, 5327 (0_4, AREG, OPRND_SHIFT_0_BIT), 5328 (16_20, AREG, OPRND_SHIFT_0_BIT), 5329 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5330 CSKY_ISA_DSP_ENHANCE), 5331 OP32 ("sub.u32.s", 5332 OPCODE_INFO3 (0xf800c520, 5333 (0_4, AREG, OPRND_SHIFT_0_BIT), 5334 (16_20, AREG, OPRND_SHIFT_0_BIT), 5335 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5336 CSKY_ISA_DSP_ENHANCE), 5337 OP32 ("sub.s32.s", 5338 OPCODE_INFO3 (0xf800c5a0, 5339 (0_4, AREG, OPRND_SHIFT_0_BIT), 5340 (16_20, AREG, OPRND_SHIFT_0_BIT), 5341 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5342 CSKY_ISA_DSP_ENHANCE), 5343 OP32 ("paddh.u8", 5344 OPCODE_INFO3 (0xf800c240, 5345 (0_4, AREG, OPRND_SHIFT_0_BIT), 5346 (16_20, AREG, OPRND_SHIFT_0_BIT), 5347 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5348 CSKY_ISA_DSP_ENHANCE), 5349 OP32 ("paddh.s8", 5350 OPCODE_INFO3 (0xf800c2c0, 5351 (0_4, AREG, OPRND_SHIFT_0_BIT), 5352 (16_20, AREG, OPRND_SHIFT_0_BIT), 5353 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5354 CSKY_ISA_DSP_ENHANCE), 5355 OP32 ("paddh.u16", 5356 OPCODE_INFO3 (0xf800c200, 5357 (0_4, AREG, OPRND_SHIFT_0_BIT), 5358 (16_20, AREG, OPRND_SHIFT_0_BIT), 5359 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5360 CSKY_ISA_DSP_ENHANCE), 5361 OP32 ("paddh.s16", 5362 OPCODE_INFO3 (0xf800c280, 5363 (0_4, AREG, OPRND_SHIFT_0_BIT), 5364 (16_20, AREG, OPRND_SHIFT_0_BIT), 5365 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5366 CSKY_ISA_DSP_ENHANCE), 5367 OP32 ("addh.u32", 5368 OPCODE_INFO3 (0xf800c220, 5369 (0_4, AREG, OPRND_SHIFT_0_BIT), 5370 (16_20, AREG, OPRND_SHIFT_0_BIT), 5371 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5372 CSKY_ISA_DSP_ENHANCE), 5373 OP32 ("addh.s32", 5374 OPCODE_INFO3 (0xf800c2a0, 5375 (0_4, AREG, OPRND_SHIFT_0_BIT), 5376 (16_20, AREG, OPRND_SHIFT_0_BIT), 5377 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5378 CSKY_ISA_DSP_ENHANCE), 5379 OP32 ("psubh.u8", 5380 OPCODE_INFO3 (0xf800c640, 5381 (0_4, AREG, OPRND_SHIFT_0_BIT), 5382 (16_20, AREG, OPRND_SHIFT_0_BIT), 5383 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5384 CSKY_ISA_DSP_ENHANCE), 5385 OP32 ("psubh.s8", 5386 OPCODE_INFO3 (0xf800c6c0, 5387 (0_4, AREG, OPRND_SHIFT_0_BIT), 5388 (16_20, AREG, OPRND_SHIFT_0_BIT), 5389 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5390 CSKY_ISA_DSP_ENHANCE), 5391 OP32 ("psubh.u16", 5392 OPCODE_INFO3 (0xf800c600, 5393 (0_4, AREG, OPRND_SHIFT_0_BIT), 5394 (16_20, AREG, OPRND_SHIFT_0_BIT), 5395 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5396 CSKY_ISA_DSP_ENHANCE), 5397 OP32 ("psubh.s16", 5398 OPCODE_INFO3 (0xf800c680, 5399 (0_4, AREG, OPRND_SHIFT_0_BIT), 5400 (16_20, AREG, OPRND_SHIFT_0_BIT), 5401 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5402 CSKY_ISA_DSP_ENHANCE), 5403 OP32 ("subh.u32", 5404 OPCODE_INFO3 (0xf800c620, 5405 (0_4, AREG, OPRND_SHIFT_0_BIT), 5406 (16_20, AREG, OPRND_SHIFT_0_BIT), 5407 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5408 CSKY_ISA_DSP_ENHANCE), 5409 OP32 ("subh.s32", 5410 OPCODE_INFO3 (0xf800c6a0, 5411 (0_4, AREG, OPRND_SHIFT_0_BIT), 5412 (16_20, AREG, OPRND_SHIFT_0_BIT), 5413 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5414 CSKY_ISA_DSP_ENHANCE), 5415 OP32 ("add.64", 5416 OPCODE_INFO3 (0xf800c060, 5417 (0_4, AREG, OPRND_SHIFT_0_BIT), 5418 (16_20, AREG, OPRND_SHIFT_0_BIT), 5419 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5420 CSKY_ISA_DSP_ENHANCE), 5421 OP32 ("sub.64", 5422 OPCODE_INFO3 (0xf800c460, 5423 (0_4, AREG, OPRND_SHIFT_0_BIT), 5424 (16_20, AREG, OPRND_SHIFT_0_BIT), 5425 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5426 CSKY_ISA_DSP_ENHANCE), 5427 OP32 ("add.u64.s", 5428 OPCODE_INFO3 (0xf800c160, 5429 (0_4, AREG, OPRND_SHIFT_0_BIT), 5430 (16_20, AREG, OPRND_SHIFT_0_BIT), 5431 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5432 CSKY_ISA_DSP_ENHANCE), 5433 OP32 ("add.s64.s", 5434 OPCODE_INFO3 (0xf800c1e0, 5435 (0_4, AREG, OPRND_SHIFT_0_BIT), 5436 (16_20, AREG, OPRND_SHIFT_0_BIT), 5437 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5438 CSKY_ISA_DSP_ENHANCE), 5439 OP32 ("sub.u64.s", 5440 OPCODE_INFO3 (0xf800c560, 5441 (0_4, AREG, OPRND_SHIFT_0_BIT), 5442 (16_20, AREG, OPRND_SHIFT_0_BIT), 5443 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5444 CSKY_ISA_DSP_ENHANCE), 5445 OP32 ("sub.s64.s", 5446 OPCODE_INFO3 (0xf800c5e0, 5447 (0_4, AREG, OPRND_SHIFT_0_BIT), 5448 (16_20, AREG, OPRND_SHIFT_0_BIT), 5449 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5450 CSKY_ISA_DSP_ENHANCE), 5451 /* The following are comparison instructions. */ 5452 OP32 ("pasx.16", 5453 OPCODE_INFO3 (0xf800c860, 5454 (0_4, AREG, OPRND_SHIFT_0_BIT), 5455 (16_20, AREG, OPRND_SHIFT_0_BIT), 5456 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5457 CSKY_ISA_DSP_ENHANCE), 5458 OP32 ("psax.16", 5459 OPCODE_INFO3 (0xf800cc60, 5460 (0_4, AREG, OPRND_SHIFT_0_BIT), 5461 (16_20, AREG, OPRND_SHIFT_0_BIT), 5462 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5463 CSKY_ISA_DSP_ENHANCE), 5464 OP32 ("pasx.u16.s", 5465 OPCODE_INFO3 (0xf800c960, 5466 (0_4, AREG, OPRND_SHIFT_0_BIT), 5467 (16_20, AREG, OPRND_SHIFT_0_BIT), 5468 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5469 CSKY_ISA_DSP_ENHANCE), 5470 OP32 ("pasx.s16.s", 5471 OPCODE_INFO3 (0xf800c9e0, 5472 (0_4, AREG, OPRND_SHIFT_0_BIT), 5473 (16_20, AREG, OPRND_SHIFT_0_BIT), 5474 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5475 CSKY_ISA_DSP_ENHANCE), 5476 OP32 ("psax.u16.s", 5477 OPCODE_INFO3 (0xf800cd60, 5478 (0_4, AREG, OPRND_SHIFT_0_BIT), 5479 (16_20, AREG, OPRND_SHIFT_0_BIT), 5480 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5481 CSKY_ISA_DSP_ENHANCE), 5482 OP32 ("psax.s16.s", 5483 OPCODE_INFO3 (0xf800cde0, 5484 (0_4, AREG, OPRND_SHIFT_0_BIT), 5485 (16_20, AREG, OPRND_SHIFT_0_BIT), 5486 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5487 CSKY_ISA_DSP_ENHANCE), 5488 OP32 ("pasxh.u16", 5489 OPCODE_INFO3 (0xf800ca60, 5490 (0_4, AREG, OPRND_SHIFT_0_BIT), 5491 (16_20, AREG, OPRND_SHIFT_0_BIT), 5492 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5493 CSKY_ISA_DSP_ENHANCE), 5494 OP32 ("pasxh.s16", 5495 OPCODE_INFO3 (0xf800cae0, 5496 (0_4, AREG, OPRND_SHIFT_0_BIT), 5497 (16_20, AREG, OPRND_SHIFT_0_BIT), 5498 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5499 CSKY_ISA_DSP_ENHANCE), 5500 OP32 ("psaxh.u16", 5501 OPCODE_INFO3 (0xf800ce60, 5502 (0_4, AREG, OPRND_SHIFT_0_BIT), 5503 (16_20, AREG, OPRND_SHIFT_0_BIT), 5504 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5505 CSKY_ISA_DSP_ENHANCE), 5506 OP32 ("psaxh.s16", 5507 OPCODE_INFO3 (0xf800cee0, 5508 (0_4, AREG, OPRND_SHIFT_0_BIT), 5509 (16_20, AREG, OPRND_SHIFT_0_BIT), 5510 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5511 CSKY_ISA_DSP_ENHANCE), 5512 OP32 ("pcmpne.8", 5513 OPCODE_INFO3 (0xf800c840, 5514 (0_4, AREG, OPRND_SHIFT_0_BIT), 5515 (16_20, AREG, OPRND_SHIFT_0_BIT), 5516 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5517 CSKY_ISA_DSP_ENHANCE), 5518 OP32 ("pcmpne.16", 5519 OPCODE_INFO3 (0xf800c800, 5520 (0_4, AREG, OPRND_SHIFT_0_BIT), 5521 (16_20, AREG, OPRND_SHIFT_0_BIT), 5522 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5523 CSKY_ISA_DSP_ENHANCE), 5524 OP32 ("pcmphs.u8", 5525 OPCODE_INFO3 (0xf800c940, 5526 (0_4, AREG, OPRND_SHIFT_0_BIT), 5527 (16_20, AREG, OPRND_SHIFT_0_BIT), 5528 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5529 CSKY_ISA_DSP_ENHANCE), 5530 OP32 ("pcmphs.s8", 5531 OPCODE_INFO3 (0xf800c9c0, 5532 (0_4, AREG, OPRND_SHIFT_0_BIT), 5533 (16_20, AREG, OPRND_SHIFT_0_BIT), 5534 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5535 CSKY_ISA_DSP_ENHANCE), 5536 OP32 ("pcmphs.u16", 5537 OPCODE_INFO3 (0xf800c900, 5538 (0_4, AREG, OPRND_SHIFT_0_BIT), 5539 (16_20, AREG, OPRND_SHIFT_0_BIT), 5540 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5541 CSKY_ISA_DSP_ENHANCE), 5542 OP32 ("pcmphs.s16", 5543 OPCODE_INFO3 (0xf800c980, 5544 (0_4, AREG, OPRND_SHIFT_0_BIT), 5545 (16_20, AREG, OPRND_SHIFT_0_BIT), 5546 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5547 CSKY_ISA_DSP_ENHANCE), 5548 OP32 ("pcmplt.u8", 5549 OPCODE_INFO3 (0xf800ca40, 5550 (0_4, AREG, OPRND_SHIFT_0_BIT), 5551 (16_20, AREG, OPRND_SHIFT_0_BIT), 5552 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5553 CSKY_ISA_DSP_ENHANCE), 5554 OP32 ("pcmplt.s8", 5555 OPCODE_INFO3 (0xf800cac0, 5556 (0_4, AREG, OPRND_SHIFT_0_BIT), 5557 (16_20, AREG, OPRND_SHIFT_0_BIT), 5558 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5559 CSKY_ISA_DSP_ENHANCE), 5560 OP32 ("pcmplt.u16", 5561 OPCODE_INFO3 (0xf800ca00, 5562 (0_4, AREG, OPRND_SHIFT_0_BIT), 5563 (16_20, AREG, OPRND_SHIFT_0_BIT), 5564 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5565 CSKY_ISA_DSP_ENHANCE), 5566 OP32 ("pcmplt.s16", 5567 OPCODE_INFO3 (0xf800ca80, 5568 (0_4, AREG, OPRND_SHIFT_0_BIT), 5569 (16_20, AREG, OPRND_SHIFT_0_BIT), 5570 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5571 CSKY_ISA_DSP_ENHANCE), 5572 OP32 ("pmax.u8", 5573 OPCODE_INFO3 (0xf800cc40, 5574 (0_4, AREG, OPRND_SHIFT_0_BIT), 5575 (16_20, AREG, OPRND_SHIFT_0_BIT), 5576 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5577 CSKY_ISA_DSP_ENHANCE), 5578 OP32 ("pmax.s8", 5579 OPCODE_INFO3 (0xf800ccc0, 5580 (0_4, AREG, OPRND_SHIFT_0_BIT), 5581 (16_20, AREG, OPRND_SHIFT_0_BIT), 5582 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5583 CSKY_ISA_DSP_ENHANCE), 5584 OP32 ("pmax.u16", 5585 OPCODE_INFO3 (0xf800cc00, 5586 (0_4, AREG, OPRND_SHIFT_0_BIT), 5587 (16_20, AREG, OPRND_SHIFT_0_BIT), 5588 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5589 CSKY_ISA_DSP_ENHANCE), 5590 OP32 ("pmax.s16", 5591 OPCODE_INFO3 (0xf800cc80, 5592 (0_4, AREG, OPRND_SHIFT_0_BIT), 5593 (16_20, AREG, OPRND_SHIFT_0_BIT), 5594 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5595 CSKY_ISA_DSP_ENHANCE), 5596 OP32 ("max.u32", 5597 OPCODE_INFO3 (0xf800cc20, 5598 (0_4, AREG, OPRND_SHIFT_0_BIT), 5599 (16_20, AREG, OPRND_SHIFT_0_BIT), 5600 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5601 CSKY_ISA_DSP_ENHANCE), 5602 OP32 ("max.s32", 5603 OPCODE_INFO3 (0xf800cca0, 5604 (0_4, AREG, OPRND_SHIFT_0_BIT), 5605 (16_20, AREG, OPRND_SHIFT_0_BIT), 5606 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5607 CSKY_ISA_DSP_ENHANCE), 5608 OP32 ("pmin.u8", 5609 OPCODE_INFO3 (0xf800cd40, 5610 (0_4, AREG, OPRND_SHIFT_0_BIT), 5611 (16_20, AREG, OPRND_SHIFT_0_BIT), 5612 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5613 CSKY_ISA_DSP_ENHANCE), 5614 OP32 ("pmin.s8", 5615 OPCODE_INFO3 (0xf800cdc0, 5616 (0_4, AREG, OPRND_SHIFT_0_BIT), 5617 (16_20, AREG, OPRND_SHIFT_0_BIT), 5618 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5619 CSKY_ISA_DSP_ENHANCE), 5620 OP32 ("pmin.u16", 5621 OPCODE_INFO3 (0xf800cd00, 5622 (0_4, AREG, OPRND_SHIFT_0_BIT), 5623 (16_20, AREG, OPRND_SHIFT_0_BIT), 5624 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5625 CSKY_ISA_DSP_ENHANCE), 5626 OP32 ("pmin.s16", 5627 OPCODE_INFO3 (0xf800cd80, 5628 (0_4, AREG, OPRND_SHIFT_0_BIT), 5629 (16_20, AREG, OPRND_SHIFT_0_BIT), 5630 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5631 CSKY_ISA_DSP_ENHANCE), 5632 OP32 ("min.u32", 5633 OPCODE_INFO3 (0xf800cd20, 5634 (0_4, AREG, OPRND_SHIFT_0_BIT), 5635 (16_20, AREG, OPRND_SHIFT_0_BIT), 5636 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5637 CSKY_ISA_DSP_ENHANCE), 5638 OP32 ("min.s32", 5639 OPCODE_INFO3 (0xf800cda0, 5640 (0_4, AREG, OPRND_SHIFT_0_BIT), 5641 (16_20, AREG, OPRND_SHIFT_0_BIT), 5642 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5643 CSKY_ISA_DSP_ENHANCE), 5644 OP32 ("sel", 5645 OPCODE_INFO4 (0xf8009000, 5646 (0_4, AREG, OPRND_SHIFT_0_BIT), 5647 (16_20, AREG, OPRND_SHIFT_0_BIT), 5648 (21_25, AREG, OPRND_SHIFT_0_BIT), 5649 (5_9, AREG, OPRND_SHIFT_0_BIT)), 5650 CSKY_ISA_DSP_ENHANCE), 5651 /* The followings are miscs. */ 5652 OP32 ("psabsa.u8", 5653 OPCODE_INFO3 (0xf800e040, 5654 (0_4, AREG, OPRND_SHIFT_0_BIT), 5655 (16_20, AREG, OPRND_SHIFT_0_BIT), 5656 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5657 CSKY_ISA_DSP_ENHANCE), 5658 OP32 ("psabsaa.u8", 5659 OPCODE_INFO3 (0xf800e140, 5660 (0_4, AREG, OPRND_SHIFT_0_BIT), 5661 (16_20, AREG, OPRND_SHIFT_0_BIT), 5662 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5663 CSKY_ISA_DSP_ENHANCE), 5664 OP32 ("divul", 5665 OPCODE_INFO3 (0xf800e260, 5666 (0_4, AREG, OPRND_SHIFT_0_BIT), 5667 (16_20, AREG, OPRND_SHIFT_0_BIT), 5668 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5669 CSKYV2_ISA_3E3R3), 5670 OP32 ("divsl", 5671 OPCODE_INFO3 (0xf800e2e0, 5672 (0_4, AREG, OPRND_SHIFT_0_BIT), 5673 (16_20, AREG, OPRND_SHIFT_0_BIT), 5674 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5675 CSKYV2_ISA_3E3R3), 5676 OP32 ("mulaca.s8", 5677 OPCODE_INFO3 (0xf800e4c0, 5678 (0_4, AREG, OPRND_SHIFT_0_BIT), 5679 (16_20, AREG, OPRND_SHIFT_0_BIT), 5680 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5681 CSKY_ISA_DSP_ENHANCE), 5682 /* The followings are shift instructions. */ 5683 OP32 ("asri.s32.r", 5684 OPCODE_INFO3 (0xf800d1a0, 5685 (0_4, AREG, OPRND_SHIFT_0_BIT), 5686 (16_20, AREG, OPRND_SHIFT_0_BIT), 5687 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 5688 CSKY_ISA_DSP_ENHANCE), 5689 OP32 ("asr.s32.r", 5690 OPCODE_INFO3 (0xf800d1e0, 5691 (0_4, AREG, OPRND_SHIFT_0_BIT), 5692 (16_20, AREG, OPRND_SHIFT_0_BIT), 5693 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5694 CSKY_ISA_DSP_ENHANCE), 5695 OP32 ("lsri.u32.r", 5696 OPCODE_INFO3 (0xf800d320, 5697 (0_4, AREG, OPRND_SHIFT_0_BIT), 5698 (16_20, AREG, OPRND_SHIFT_0_BIT), 5699 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 5700 CSKY_ISA_DSP_ENHANCE), 5701 OP32 ("lsr.u32.r", 5702 OPCODE_INFO3 (0xf800d360, 5703 (0_4, AREG, OPRND_SHIFT_0_BIT), 5704 (16_20, AREG, OPRND_SHIFT_0_BIT), 5705 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5706 CSKY_ISA_DSP_ENHANCE), 5707 OP32 ("lsli.u32.s", 5708 OPCODE_INFO3 (0xf800d520, 5709 (0_4, AREG, OPRND_SHIFT_0_BIT), 5710 (16_20, AREG, OPRND_SHIFT_0_BIT), 5711 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 5712 CSKY_ISA_DSP_ENHANCE), 5713 OP32 ("lsli.s32.s", 5714 OPCODE_INFO3 (0xf800d5a0, 5715 (0_4, AREG, OPRND_SHIFT_0_BIT), 5716 (16_20, AREG, OPRND_SHIFT_0_BIT), 5717 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 5718 CSKY_ISA_DSP_ENHANCE), 5719 OP32 ("lsl.u32.s", 5720 OPCODE_INFO3 (0xf800d560, 5721 (0_4, AREG, OPRND_SHIFT_0_BIT), 5722 (16_20, AREG, OPRND_SHIFT_0_BIT), 5723 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5724 CSKY_ISA_DSP_ENHANCE), 5725 OP32 ("lsl.s32.s", 5726 OPCODE_INFO3 (0xf800d5e0, 5727 (0_4, AREG, OPRND_SHIFT_0_BIT), 5728 (16_20, AREG, OPRND_SHIFT_0_BIT), 5729 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5730 CSKY_ISA_DSP_ENHANCE), 5731 OP32 ("pasri.s16", 5732 OPCODE_INFO3 (0xf800d080, 5733 (0_4, AREG, OPRND_SHIFT_0_BIT), 5734 (16_20, AREG, OPRND_SHIFT_0_BIT), 5735 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5736 CSKY_ISA_DSP_ENHANCE), 5737 OP32 ("pasr.s16", 5738 OPCODE_INFO3 (0xf800d0c0, 5739 (0_4, AREG, OPRND_SHIFT_0_BIT), 5740 (16_20, AREG, OPRND_SHIFT_0_BIT), 5741 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5742 CSKY_ISA_DSP_ENHANCE), 5743 OP32 ("pasri.s16.r", 5744 OPCODE_INFO3 (0xf800d180, 5745 (0_4, AREG, OPRND_SHIFT_0_BIT), 5746 (16_20, AREG, OPRND_SHIFT_0_BIT), 5747 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5748 CSKY_ISA_DSP_ENHANCE), 5749 OP32 ("pasr.s16.r", 5750 OPCODE_INFO3 (0xf800d1c0, 5751 (0_4, AREG, OPRND_SHIFT_0_BIT), 5752 (16_20, AREG, OPRND_SHIFT_0_BIT), 5753 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5754 CSKY_ISA_DSP_ENHANCE), 5755 OP32 ("plsri.u16", 5756 OPCODE_INFO3 (0xf800d200, 5757 (0_4, AREG, OPRND_SHIFT_0_BIT), 5758 (16_20, AREG, OPRND_SHIFT_0_BIT), 5759 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5760 CSKY_ISA_DSP_ENHANCE), 5761 OP32 ("plsr.u16", 5762 OPCODE_INFO3 (0xf800d240, 5763 (0_4, AREG, OPRND_SHIFT_0_BIT), 5764 (16_20, AREG, OPRND_SHIFT_0_BIT), 5765 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5766 CSKY_ISA_DSP_ENHANCE), 5767 OP32 ("plsri.u16.r", 5768 OPCODE_INFO3 (0xf800d300, 5769 (0_4, AREG, OPRND_SHIFT_0_BIT), 5770 (16_20, AREG, OPRND_SHIFT_0_BIT), 5771 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5772 CSKY_ISA_DSP_ENHANCE), 5773 OP32 ("plsr.u16.r", 5774 OPCODE_INFO3 (0xf800d340, 5775 (0_4, AREG, OPRND_SHIFT_0_BIT), 5776 (16_20, AREG, OPRND_SHIFT_0_BIT), 5777 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5778 CSKY_ISA_DSP_ENHANCE), 5779 OP32 ("plsli.16", 5780 OPCODE_INFO3 (0xf800d400, 5781 (0_4, AREG, OPRND_SHIFT_0_BIT), 5782 (16_20, AREG, OPRND_SHIFT_0_BIT), 5783 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5784 CSKY_ISA_DSP_ENHANCE), 5785 OP32 ("plsl.16", 5786 OPCODE_INFO3 (0xf800d440, 5787 (0_4, AREG, OPRND_SHIFT_0_BIT), 5788 (16_20, AREG, OPRND_SHIFT_0_BIT), 5789 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5790 CSKY_ISA_DSP_ENHANCE), 5791 OP32 ("plsli.u16.s", 5792 OPCODE_INFO3 (0xf800d500, 5793 (0_4, AREG, OPRND_SHIFT_0_BIT), 5794 (16_20, AREG, OPRND_SHIFT_0_BIT), 5795 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5796 CSKY_ISA_DSP_ENHANCE), 5797 OP32 ("plsli.s16.s", 5798 OPCODE_INFO3 (0xf800d580, 5799 (0_4, AREG, OPRND_SHIFT_0_BIT), 5800 (16_20, AREG, OPRND_SHIFT_0_BIT), 5801 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5802 CSKY_ISA_DSP_ENHANCE), 5803 OP32 ("plsl.u16.s", 5804 OPCODE_INFO3 (0xf800d540, 5805 (0_4, AREG, OPRND_SHIFT_0_BIT), 5806 (16_20, AREG, OPRND_SHIFT_0_BIT), 5807 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5808 CSKY_ISA_DSP_ENHANCE), 5809 OP32 ("plsl.s16.s", 5810 OPCODE_INFO3 (0xf800d5c0, 5811 (0_4, AREG, OPRND_SHIFT_0_BIT), 5812 (16_20, AREG, OPRND_SHIFT_0_BIT), 5813 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5814 CSKY_ISA_DSP_ENHANCE), 5815 /* The following are package & unpackage instructions. */ 5816 OP32 ("pkg", 5817 OPCODE_INFO5 (0xf800a000, 5818 (0_4, AREG, OPRND_SHIFT_0_BIT), 5819 (16_20, AREG, OPRND_SHIFT_0_BIT), 5820 (5_8, IMM4b, OPRND_SHIFT_0_BIT), 5821 (21_25, AREG, OPRND_SHIFT_0_BIT), 5822 (9_12, OIMM4b, OPRND_SHIFT_0_BIT)), 5823 CSKY_ISA_DSP_ENHANCE), 5824 OP32 ("dexti", 5825 OPCODE_INFO4 (0xf8009800, 5826 (0_4, AREG, OPRND_SHIFT_0_BIT), 5827 (16_20, AREG, OPRND_SHIFT_0_BIT), 5828 (21_25, AREG, OPRND_SHIFT_0_BIT), 5829 (5_9, IMM5b, OPRND_SHIFT_0_BIT)), 5830 CSKY_ISA_DSP_ENHANCE), 5831 OP32 ("dext", 5832 OPCODE_INFO4 (0xf8009c00, 5833 (0_4, AREG, OPRND_SHIFT_0_BIT), 5834 (16_20, AREG, OPRND_SHIFT_0_BIT), 5835 (21_25, AREG, OPRND_SHIFT_0_BIT), 5836 (5_9, AREG, OPRND_SHIFT_0_BIT)), 5837 CSKY_ISA_DSP_ENHANCE), 5838 OP32 ("pkgll", 5839 OPCODE_INFO3 (0xf800d840, 5840 (0_4, AREG, OPRND_SHIFT_0_BIT), 5841 (16_20, AREG, OPRND_SHIFT_0_BIT), 5842 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5843 CSKY_ISA_DSP_ENHANCE), 5844 OP32 ("pkghh", 5845 OPCODE_INFO3 (0xf800d860, 5846 (0_4, AREG, OPRND_SHIFT_0_BIT), 5847 (16_20, AREG, OPRND_SHIFT_0_BIT), 5848 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5849 CSKY_ISA_DSP_ENHANCE), 5850 OP32 ("pext.u8.e", 5851 OPCODE_INFO2 (0xf800d900, 5852 (0_4, AREG, OPRND_SHIFT_0_BIT), 5853 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5854 CSKY_ISA_DSP_ENHANCE), 5855 OP32 ("pext.s8.e", 5856 OPCODE_INFO2 (0xf800d980, 5857 (0_4, AREG, OPRND_SHIFT_0_BIT), 5858 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5859 CSKY_ISA_DSP_ENHANCE), 5860 OP32 ("pextx.u8.e", 5861 OPCODE_INFO2 (0xf800d920, 5862 (0_4, AREG, OPRND_SHIFT_0_BIT), 5863 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5864 CSKY_ISA_DSP_ENHANCE), 5865 OP32 ("pextx.s8.e", 5866 OPCODE_INFO2 (0xf800d9a0, 5867 (0_4, AREG, OPRND_SHIFT_0_BIT), 5868 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5869 CSKY_ISA_DSP_ENHANCE), 5870 OP32 ("narl", 5871 OPCODE_INFO3 (0xf800da00, 5872 (0_4, AREG, OPRND_SHIFT_0_BIT), 5873 (16_20, AREG, OPRND_SHIFT_0_BIT), 5874 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5875 CSKY_ISA_DSP_ENHANCE), 5876 OP32 ("narh", 5877 OPCODE_INFO3 (0xf800da20, 5878 (0_4, AREG, OPRND_SHIFT_0_BIT), 5879 (16_20, AREG, OPRND_SHIFT_0_BIT), 5880 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5881 CSKY_ISA_DSP_ENHANCE), 5882 OP32 ("narlx", 5883 OPCODE_INFO3 (0xf800da40, 5884 (0_4, AREG, OPRND_SHIFT_0_BIT), 5885 (16_20, AREG, OPRND_SHIFT_0_BIT), 5886 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5887 CSKY_ISA_DSP_ENHANCE), 5888 OP32 ("narhx", 5889 OPCODE_INFO3 (0xf800da60, 5890 (0_4, AREG, OPRND_SHIFT_0_BIT), 5891 (16_20, AREG, OPRND_SHIFT_0_BIT), 5892 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5893 CSKY_ISA_DSP_ENHANCE), 5894 OP32 ("clipi.u32", 5895 OPCODE_INFO3 (0xf800db00, 5896 (0_4, AREG, OPRND_SHIFT_0_BIT), 5897 (16_20, AREG, OPRND_SHIFT_0_BIT), 5898 (21_25, IMM5b, OPRND_SHIFT_0_BIT)), 5899 CSKY_ISA_DSP_ENHANCE), 5900 OP32 ("clipi.s32", 5901 OPCODE_INFO3 (0xf800db80, 5902 (0_4, AREG, OPRND_SHIFT_0_BIT), 5903 (16_20, AREG, OPRND_SHIFT_0_BIT), 5904 (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), 5905 CSKY_ISA_DSP_ENHANCE), 5906 OP32 ("clip.u32", 5907 OPCODE_INFO3 (0xf800db20, 5908 (0_4, AREG, OPRND_SHIFT_0_BIT), 5909 (16_20, AREG, OPRND_SHIFT_0_BIT), 5910 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5911 CSKY_ISA_DSP_ENHANCE), 5912 OP32 ("clip.s32", 5913 OPCODE_INFO3 (0xf800dba0, 5914 (0_4, AREG, OPRND_SHIFT_0_BIT), 5915 (16_20, AREG, OPRND_SHIFT_0_BIT), 5916 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5917 CSKY_ISA_DSP_ENHANCE), 5918 OP32 ("pclipi.u16", 5919 OPCODE_INFO3 (0xf800db40, 5920 (0_4, AREG, OPRND_SHIFT_0_BIT), 5921 (16_20, AREG, OPRND_SHIFT_0_BIT), 5922 (21_25, IMM4b, OPRND_SHIFT_0_BIT)), 5923 CSKY_ISA_DSP_ENHANCE), 5924 OP32 ("pclipi.s16", 5925 OPCODE_INFO3 (0xf800dbc0, 5926 (0_4, AREG, OPRND_SHIFT_0_BIT), 5927 (16_20, AREG, OPRND_SHIFT_0_BIT), 5928 (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), 5929 CSKY_ISA_DSP_ENHANCE), 5930 OP32 ("pclip.u16", 5931 OPCODE_INFO3 (0xf800db60, 5932 (0_4, AREG, OPRND_SHIFT_0_BIT), 5933 (16_20, AREG, OPRND_SHIFT_0_BIT), 5934 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5935 CSKY_ISA_DSP_ENHANCE), 5936 OP32 ("pclip.s16", 5937 OPCODE_INFO3 (0xf800dbe0, 5938 (0_4, AREG, OPRND_SHIFT_0_BIT), 5939 (16_20, AREG, OPRND_SHIFT_0_BIT), 5940 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5941 CSKY_ISA_DSP_ENHANCE), 5942 OP32 ("pabs.s8.s", 5943 OPCODE_INFO2 (0xf800dc80, 5944 (0_4, AREG, OPRND_SHIFT_0_BIT), 5945 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5946 CSKY_ISA_DSP_ENHANCE), 5947 OP32 ("pabs.s16.s", 5948 OPCODE_INFO2 (0xf800dca0, 5949 (0_4, AREG, OPRND_SHIFT_0_BIT), 5950 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5951 CSKY_ISA_DSP_ENHANCE), 5952 OP32 ("abs.s32.s", 5953 OPCODE_INFO2 (0xf800dcc0, 5954 (0_4, AREG, OPRND_SHIFT_0_BIT), 5955 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5956 CSKY_ISA_DSP_ENHANCE), 5957 OP32 ("pneg.s8.s", 5958 OPCODE_INFO2 (0xf800dd80, 5959 (0_4, AREG, OPRND_SHIFT_0_BIT), 5960 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5961 CSKY_ISA_DSP_ENHANCE), 5962 OP32 ("pneg.s16.s", 5963 OPCODE_INFO2 (0xf800dda0, 5964 (0_4, AREG, OPRND_SHIFT_0_BIT), 5965 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5966 CSKY_ISA_DSP_ENHANCE), 5967 OP32 ("neg.s32.s", 5968 OPCODE_INFO2 (0xf800ddc0, 5969 (0_4, AREG, OPRND_SHIFT_0_BIT), 5970 (16_20, AREG, OPRND_SHIFT_0_BIT)), 5971 CSKY_ISA_DSP_ENHANCE), 5972 OP32 ("dup.8", 5973 OPCODE_INFO3 (0xf800de00, 5974 (0_4, AREG, OPRND_SHIFT_0_BIT), 5975 (16_20, AREG, OPRND_SHIFT_0_BIT), 5976 (5_6, IMM2b, OPRND_SHIFT_0_BIT)), 5977 CSKY_ISA_DSP_ENHANCE), 5978 OP32 ("dup.16", 5979 OPCODE_INFO3 (0xf800df00, 5980 (0_4, AREG, OPRND_SHIFT_0_BIT), 5981 (16_20, AREG, OPRND_SHIFT_0_BIT), 5982 (5_6, IMM1b, OPRND_SHIFT_0_BIT)), 5983 CSKY_ISA_DSP_ENHANCE), 5984 /* The followings are multiplication instructions. */ 5985 OP32 ("mul.u32", 5986 OPCODE_INFO3 (0xf8008000, 5987 (0_4, AREG, OPRND_SHIFT_0_BIT), 5988 (16_20, AREG, OPRND_SHIFT_0_BIT), 5989 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5990 CSKYV2_ISA_3E3R1), 5991 OP32 ("mul.s32", 5992 OPCODE_INFO3 (0xf8008200, 5993 (0_4, AREG, OPRND_SHIFT_0_BIT), 5994 (16_20, AREG, OPRND_SHIFT_0_BIT), 5995 (21_25, AREG, OPRND_SHIFT_0_BIT)), 5996 CSKYV2_ISA_3E3R1), 5997 OP32 ("mula.u32", 5998 OPCODE_INFO3 (0xf8008080, 5999 (0_4, AREG, OPRND_SHIFT_0_BIT), 6000 (16_20, AREG, OPRND_SHIFT_0_BIT), 6001 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6002 CSKYV2_ISA_3E3R1), 6003 OP32 ("mula.s32", 6004 OPCODE_INFO3 (0xf8008280, 6005 (0_4, AREG, OPRND_SHIFT_0_BIT), 6006 (16_20, AREG, OPRND_SHIFT_0_BIT), 6007 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6008 CSKYV2_ISA_3E3R1), 6009 OP32 ("mula.32.l", 6010 OPCODE_INFO3 (0xf8008440, 6011 (0_4, AREG, OPRND_SHIFT_0_BIT), 6012 (16_20, AREG, OPRND_SHIFT_0_BIT), 6013 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6014 CSKYV2_ISA_3E3R1), 6015 OP32 ("mulall.s16.s", 6016 OPCODE_INFO3 (0xf80081a0, 6017 (0_4, AREG, OPRND_SHIFT_0_BIT), 6018 (16_20, AREG, OPRND_SHIFT_0_BIT), 6019 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6020 CSKYV2_ISA_3E3R1), 6021 OP32 ("muls.u32", 6022 OPCODE_INFO3 (0xf80080c0, 6023 (0_4, AREG, OPRND_SHIFT_0_BIT), 6024 (16_20, AREG, OPRND_SHIFT_0_BIT), 6025 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6026 CSKY_ISA_DSP_ENHANCE), 6027 OP32 ("muls.s32", 6028 OPCODE_INFO3 (0xf80082c0, 6029 (0_4, AREG, OPRND_SHIFT_0_BIT), 6030 (16_20, AREG, OPRND_SHIFT_0_BIT), 6031 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6032 CSKY_ISA_DSP_ENHANCE), 6033 OP32 ("mula.u32.s", 6034 OPCODE_INFO3 (0xf8008180, 6035 (0_4, AREG, OPRND_SHIFT_0_BIT), 6036 (16_20, AREG, OPRND_SHIFT_0_BIT), 6037 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6038 CSKY_ISA_DSP_ENHANCE), 6039 OP32 ("mula.s32.s", 6040 OPCODE_INFO3 (0xf8008380, 6041 (0_4, AREG, OPRND_SHIFT_0_BIT), 6042 (16_20, AREG, OPRND_SHIFT_0_BIT), 6043 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6044 CSKY_ISA_DSP_ENHANCE), 6045 OP32 ("muls.u32.s", 6046 OPCODE_INFO3 (0xf80081c0, 6047 (0_4, AREG, OPRND_SHIFT_0_BIT), 6048 (16_20, AREG, OPRND_SHIFT_0_BIT), 6049 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6050 CSKY_ISA_DSP_ENHANCE), 6051 OP32 ("muls.s32.s", 6052 OPCODE_INFO3 (0xf80083c0, 6053 (0_4, AREG, OPRND_SHIFT_0_BIT), 6054 (16_20, AREG, OPRND_SHIFT_0_BIT), 6055 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6056 CSKY_ISA_DSP_ENHANCE), 6057 OP32 ("mul.s32.h", 6058 OPCODE_INFO3 (0xf8008400, 6059 (0_4, AREG, OPRND_SHIFT_0_BIT), 6060 (16_20, AREG, OPRND_SHIFT_0_BIT), 6061 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6062 CSKY_ISA_DSP_ENHANCE), 6063 OP32 ("mul.s32.rh", 6064 OPCODE_INFO3 (0xf8008600, 6065 (0_4, AREG, OPRND_SHIFT_0_BIT), 6066 (16_20, AREG, OPRND_SHIFT_0_BIT), 6067 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6068 CSKY_ISA_DSP_ENHANCE), 6069 OP32 ("rmul.s32.h", 6070 OPCODE_INFO3 (0xf8008500, 6071 (0_4, AREG, OPRND_SHIFT_0_BIT), 6072 (16_20, AREG, OPRND_SHIFT_0_BIT), 6073 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6074 CSKY_ISA_DSP_ENHANCE), 6075 OP32 ("rmul.s32.rh", 6076 OPCODE_INFO3 (0xf8008700, 6077 (0_4, AREG, OPRND_SHIFT_0_BIT), 6078 (16_20, AREG, OPRND_SHIFT_0_BIT), 6079 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6080 CSKY_ISA_DSP_ENHANCE), 6081 OP32 ("mula.s32.hs", 6082 OPCODE_INFO3 (0xf8008580, 6083 (0_4, AREG, OPRND_SHIFT_0_BIT), 6084 (16_20, AREG, OPRND_SHIFT_0_BIT), 6085 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6086 CSKY_ISA_DSP_ENHANCE), 6087 OP32 ("muls.s32.hs", 6088 OPCODE_INFO3 (0xf80085c0, 6089 (0_4, AREG, OPRND_SHIFT_0_BIT), 6090 (16_20, AREG, OPRND_SHIFT_0_BIT), 6091 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6092 CSKY_ISA_DSP_ENHANCE), 6093 OP32 ("mula.s32.rhs", 6094 OPCODE_INFO3 (0xf8008780, 6095 (0_4, AREG, OPRND_SHIFT_0_BIT), 6096 (16_20, AREG, OPRND_SHIFT_0_BIT), 6097 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6098 CSKY_ISA_DSP_ENHANCE), 6099 OP32 ("muls.s32.rhs", 6100 OPCODE_INFO3 (0xf80087c0, 6101 (0_4, AREG, OPRND_SHIFT_0_BIT), 6102 (16_20, AREG, OPRND_SHIFT_0_BIT), 6103 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6104 CSKY_ISA_DSP_ENHANCE), 6105 OP32 ("mulxl.s32", 6106 OPCODE_INFO3 (0xf8008800, 6107 (0_4, AREG, OPRND_SHIFT_0_BIT), 6108 (16_20, AREG, OPRND_SHIFT_0_BIT), 6109 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6110 CSKY_ISA_DSP_ENHANCE), 6111 OP32 ("mulxl.s32.r", 6112 OPCODE_INFO3 (0xf8008a00, 6113 (0_4, AREG, OPRND_SHIFT_0_BIT), 6114 (16_20, AREG, OPRND_SHIFT_0_BIT), 6115 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6116 CSKY_ISA_DSP_ENHANCE), 6117 OP32 ("mulxh.s32", 6118 OPCODE_INFO3 (0xf8008c00, 6119 (0_4, AREG, OPRND_SHIFT_0_BIT), 6120 (16_20, AREG, OPRND_SHIFT_0_BIT), 6121 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6122 CSKY_ISA_DSP_ENHANCE), 6123 OP32 ("mulxh.s32.r", 6124 OPCODE_INFO3 (0xf8008e00, 6125 (0_4, AREG, OPRND_SHIFT_0_BIT), 6126 (16_20, AREG, OPRND_SHIFT_0_BIT), 6127 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6128 CSKY_ISA_DSP_ENHANCE), 6129 OP32 ("rmulxl.s32", 6130 OPCODE_INFO3 (0xf8008900, 6131 (0_4, AREG, OPRND_SHIFT_0_BIT), 6132 (16_20, AREG, OPRND_SHIFT_0_BIT), 6133 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6134 CSKY_ISA_DSP_ENHANCE), 6135 OP32 ("rmulxl.s32.r", 6136 OPCODE_INFO3 (0xf8008b00, 6137 (0_4, AREG, OPRND_SHIFT_0_BIT), 6138 (16_20, AREG, OPRND_SHIFT_0_BIT), 6139 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6140 CSKY_ISA_DSP_ENHANCE), 6141 OP32 ("rmulxh.s32", 6142 OPCODE_INFO3 (0xf8008d00, 6143 (0_4, AREG, OPRND_SHIFT_0_BIT), 6144 (16_20, AREG, OPRND_SHIFT_0_BIT), 6145 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6146 CSKY_ISA_DSP_ENHANCE), 6147 OP32 ("rmulxh.s32.r", 6148 OPCODE_INFO3 (0xf8008f00, 6149 (0_4, AREG, OPRND_SHIFT_0_BIT), 6150 (16_20, AREG, OPRND_SHIFT_0_BIT), 6151 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6152 CSKY_ISA_DSP_ENHANCE), 6153 OP32 ("mulaxl.s32.s", 6154 OPCODE_INFO3 (0xf8008980, 6155 (0_4, AREG, OPRND_SHIFT_0_BIT), 6156 (16_20, AREG, OPRND_SHIFT_0_BIT), 6157 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6158 CSKY_ISA_DSP_ENHANCE), 6159 OP32 ("mulaxl.s32.rs", 6160 OPCODE_INFO3 (0xf8008b80, 6161 (0_4, AREG, OPRND_SHIFT_0_BIT), 6162 (16_20, AREG, OPRND_SHIFT_0_BIT), 6163 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6164 CSKY_ISA_DSP_ENHANCE), 6165 OP32 ("mulaxh.s32.s", 6166 OPCODE_INFO3 (0xf8008d80, 6167 (0_4, AREG, OPRND_SHIFT_0_BIT), 6168 (16_20, AREG, OPRND_SHIFT_0_BIT), 6169 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6170 CSKY_ISA_DSP_ENHANCE), 6171 OP32 ("mulaxh.s32.rs", 6172 OPCODE_INFO3 (0xf8008f80, 6173 (0_4, AREG, OPRND_SHIFT_0_BIT), 6174 (16_20, AREG, OPRND_SHIFT_0_BIT), 6175 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6176 CSKY_ISA_DSP_ENHANCE), 6177 OP32 ("mulll.s16", 6178 OPCODE_INFO3 (0xf8008020, 6179 (0_4, AREG, OPRND_SHIFT_0_BIT), 6180 (16_20, AREG, OPRND_SHIFT_0_BIT), 6181 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6182 CSKY_ISA_DSP_ENHANCE), 6183 OP32 ("mulhh.s16", 6184 OPCODE_INFO3 (0xf8008260, 6185 (0_4, AREG, OPRND_SHIFT_0_BIT), 6186 (16_20, AREG, OPRND_SHIFT_0_BIT), 6187 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6188 CSKY_ISA_DSP_ENHANCE), 6189 OP32 ("mulhl.s16", 6190 OPCODE_INFO3 (0xf8008220, 6191 (0_4, AREG, OPRND_SHIFT_0_BIT), 6192 (16_20, AREG, OPRND_SHIFT_0_BIT), 6193 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6194 CSKY_ISA_DSP_ENHANCE), 6195 OP32 ("rmulll.s16", 6196 OPCODE_INFO3 (0xf8008120, 6197 (0_4, AREG, OPRND_SHIFT_0_BIT), 6198 (16_20, AREG, OPRND_SHIFT_0_BIT), 6199 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6200 CSKY_ISA_DSP_ENHANCE), 6201 OP32 ("rmulhh.s16", 6202 OPCODE_INFO3 (0xf8008360, 6203 (0_4, AREG, OPRND_SHIFT_0_BIT), 6204 (16_20, AREG, OPRND_SHIFT_0_BIT), 6205 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6206 CSKY_ISA_DSP_ENHANCE), 6207 OP32 ("rmulhl.s16", 6208 OPCODE_INFO3 (0xf8008320, 6209 (0_4, AREG, OPRND_SHIFT_0_BIT), 6210 (16_20, AREG, OPRND_SHIFT_0_BIT), 6211 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6212 CSKY_ISA_DSP_ENHANCE), 6213 OP32 ("mulahh.s16.s", 6214 OPCODE_INFO3 (0xf80083e0, 6215 (0_4, AREG, OPRND_SHIFT_0_BIT), 6216 (16_20, AREG, OPRND_SHIFT_0_BIT), 6217 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6218 CSKY_ISA_DSP_ENHANCE), 6219 OP32 ("mulahl.s16.s", 6220 OPCODE_INFO3 (0xf80083a0, 6221 (0_4, AREG, OPRND_SHIFT_0_BIT), 6222 (16_20, AREG, OPRND_SHIFT_0_BIT), 6223 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6224 CSKY_ISA_DSP_ENHANCE), 6225 OP32 ("mulall.s16.e", 6226 OPCODE_INFO3 (0xf80080a0, 6227 (0_4, AREG, OPRND_SHIFT_0_BIT), 6228 (16_20, AREG, OPRND_SHIFT_0_BIT), 6229 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6230 CSKY_ISA_DSP_ENHANCE), 6231 OP32 ("mulahh.s16.e", 6232 OPCODE_INFO3 (0xf80082e0, 6233 (0_4, AREG, OPRND_SHIFT_0_BIT), 6234 (16_20, AREG, OPRND_SHIFT_0_BIT), 6235 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6236 CSKY_ISA_DSP_ENHANCE), 6237 OP32 ("mulahl.s16.e", 6238 OPCODE_INFO3 (0xf80080e0, 6239 (0_4, AREG, OPRND_SHIFT_0_BIT), 6240 (16_20, AREG, OPRND_SHIFT_0_BIT), 6241 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6242 CSKY_ISA_DSP_ENHANCE), 6243 OP32 ("pmul.u16", 6244 OPCODE_INFO3 (0xf80084a0, 6245 (0_4, AREG, OPRND_SHIFT_0_BIT), 6246 (16_20, AREG, OPRND_SHIFT_0_BIT), 6247 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6248 CSKY_ISA_DSP_ENHANCE), 6249 OP32 ("pmulx.u16", 6250 OPCODE_INFO3 (0xf80084e0, 6251 (0_4, AREG, OPRND_SHIFT_0_BIT), 6252 (16_20, AREG, OPRND_SHIFT_0_BIT), 6253 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6254 CSKY_ISA_DSP_ENHANCE), 6255 OP32 ("pmul.s16", 6256 OPCODE_INFO3 (0xf8008420, 6257 (0_4, AREG, OPRND_SHIFT_0_BIT), 6258 (16_20, AREG, OPRND_SHIFT_0_BIT), 6259 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6260 CSKY_ISA_DSP_ENHANCE), 6261 OP32 ("pmulx.s16", 6262 OPCODE_INFO3 (0xf8008460, 6263 (0_4, AREG, OPRND_SHIFT_0_BIT), 6264 (16_20, AREG, OPRND_SHIFT_0_BIT), 6265 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6266 CSKY_ISA_DSP_ENHANCE), 6267 OP32 ("prmul.s16", 6268 OPCODE_INFO3 (0xf8008520, 6269 (0_4, AREG, OPRND_SHIFT_0_BIT), 6270 (16_20, AREG, OPRND_SHIFT_0_BIT), 6271 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6272 CSKY_ISA_DSP_ENHANCE), 6273 OP32 ("prmulx.s16", 6274 OPCODE_INFO3 (0xf8008560, 6275 (0_4, AREG, OPRND_SHIFT_0_BIT), 6276 (16_20, AREG, OPRND_SHIFT_0_BIT), 6277 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6278 CSKY_ISA_DSP_ENHANCE), 6279 OP32 ("prmul.s16.h", 6280 OPCODE_INFO3 (0xf80085a0, 6281 (0_4, AREG, OPRND_SHIFT_0_BIT), 6282 (16_20, AREG, OPRND_SHIFT_0_BIT), 6283 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6284 CSKY_ISA_DSP_ENHANCE), 6285 OP32 ("prmul.s16.rh", 6286 OPCODE_INFO3 (0xf80087a0, 6287 (0_4, AREG, OPRND_SHIFT_0_BIT), 6288 (16_20, AREG, OPRND_SHIFT_0_BIT), 6289 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6290 CSKY_ISA_DSP_ENHANCE), 6291 OP32 ("prmulx.s16.h", 6292 OPCODE_INFO3 (0xf80085e0, 6293 (0_4, AREG, OPRND_SHIFT_0_BIT), 6294 (16_20, AREG, OPRND_SHIFT_0_BIT), 6295 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6296 CSKY_ISA_DSP_ENHANCE), 6297 OP32 ("prmulx.s16.rh", 6298 OPCODE_INFO3 (0xf80087e0, 6299 (0_4, AREG, OPRND_SHIFT_0_BIT), 6300 (16_20, AREG, OPRND_SHIFT_0_BIT), 6301 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6302 CSKY_ISA_DSP_ENHANCE), 6303 OP32 ("mulca.s16.s", 6304 OPCODE_INFO3 (0xf8008920, 6305 (0_4, AREG, OPRND_SHIFT_0_BIT), 6306 (16_20, AREG, OPRND_SHIFT_0_BIT), 6307 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6308 CSKY_ISA_DSP_ENHANCE), 6309 OP32 ("mulcax.s16.s", 6310 OPCODE_INFO3 (0xf8008960, 6311 (0_4, AREG, OPRND_SHIFT_0_BIT), 6312 (16_20, AREG, OPRND_SHIFT_0_BIT), 6313 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6314 CSKY_ISA_DSP_ENHANCE), 6315 OP32 ("mulcs.s16", 6316 OPCODE_INFO3 (0xf8008a20, 6317 (0_4, AREG, OPRND_SHIFT_0_BIT), 6318 (16_20, AREG, OPRND_SHIFT_0_BIT), 6319 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6320 CSKY_ISA_DSP_ENHANCE), 6321 OP32 ("mulcsr.s16", 6322 OPCODE_INFO3 (0xf8008a60, 6323 (0_4, AREG, OPRND_SHIFT_0_BIT), 6324 (16_20, AREG, OPRND_SHIFT_0_BIT), 6325 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6326 CSKY_ISA_DSP_ENHANCE), 6327 OP32 ("mulcsx.s16", 6328 OPCODE_INFO3 (0xf8008c20, 6329 (0_4, AREG, OPRND_SHIFT_0_BIT), 6330 (16_20, AREG, OPRND_SHIFT_0_BIT), 6331 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6332 CSKY_ISA_DSP_ENHANCE), 6333 OP32 ("mulaca.s16.s", 6334 OPCODE_INFO3 (0xf80089a0, 6335 (0_4, AREG, OPRND_SHIFT_0_BIT), 6336 (16_20, AREG, OPRND_SHIFT_0_BIT), 6337 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6338 CSKY_ISA_DSP_ENHANCE), 6339 OP32 ("mulacax.s16.s", 6340 OPCODE_INFO3 (0xf80089e0, 6341 (0_4, AREG, OPRND_SHIFT_0_BIT), 6342 (16_20, AREG, OPRND_SHIFT_0_BIT), 6343 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6344 CSKY_ISA_DSP_ENHANCE), 6345 OP32 ("mulacs.s16.s", 6346 OPCODE_INFO3 (0xf8008ba0, 6347 (0_4, AREG, OPRND_SHIFT_0_BIT), 6348 (16_20, AREG, OPRND_SHIFT_0_BIT), 6349 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6350 CSKY_ISA_DSP_ENHANCE), 6351 OP32 ("mulacsr.s16.s", 6352 OPCODE_INFO3 (0xf8008be0, 6353 (0_4, AREG, OPRND_SHIFT_0_BIT), 6354 (16_20, AREG, OPRND_SHIFT_0_BIT), 6355 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6356 CSKY_ISA_DSP_ENHANCE), 6357 OP32 ("mulacsx.s16.s", 6358 OPCODE_INFO3 (0xf8008da0, 6359 (0_4, AREG, OPRND_SHIFT_0_BIT), 6360 (16_20, AREG, OPRND_SHIFT_0_BIT), 6361 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6362 CSKY_ISA_DSP_ENHANCE), 6363 OP32 ("mulsca.s16.s", 6364 OPCODE_INFO3 (0xf8008de0, 6365 (0_4, AREG, OPRND_SHIFT_0_BIT), 6366 (16_20, AREG, OPRND_SHIFT_0_BIT), 6367 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6368 CSKY_ISA_DSP_ENHANCE), 6369 OP32 ("mulscax.s16.s", 6370 OPCODE_INFO3 (0xf8008fa0, 6371 (0_4, AREG, OPRND_SHIFT_0_BIT), 6372 (16_20, AREG, OPRND_SHIFT_0_BIT), 6373 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6374 CSKY_ISA_DSP_ENHANCE), 6375 OP32 ("mulaca.s16.e", 6376 OPCODE_INFO3 (0xf80088a0, 6377 (0_4, AREG, OPRND_SHIFT_0_BIT), 6378 (16_20, AREG, OPRND_SHIFT_0_BIT), 6379 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6380 CSKY_ISA_DSP_ENHANCE), 6381 OP32 ("mulacax.s16.e", 6382 OPCODE_INFO3 (0xf80088e0, 6383 (0_4, AREG, OPRND_SHIFT_0_BIT), 6384 (16_20, AREG, OPRND_SHIFT_0_BIT), 6385 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6386 CSKY_ISA_DSP_ENHANCE), 6387 OP32 ("mulacs.s16.e", 6388 OPCODE_INFO3 (0xf8008aa0, 6389 (0_4, AREG, OPRND_SHIFT_0_BIT), 6390 (16_20, AREG, OPRND_SHIFT_0_BIT), 6391 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6392 CSKY_ISA_DSP_ENHANCE), 6393 OP32 ("mulacsr.s16.e", 6394 OPCODE_INFO3 (0xf8008ae0, 6395 (0_4, AREG, OPRND_SHIFT_0_BIT), 6396 (16_20, AREG, OPRND_SHIFT_0_BIT), 6397 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6398 CSKY_ISA_DSP_ENHANCE), 6399 OP32 ("mulacsx.s16.e", 6400 OPCODE_INFO3 (0xf8008ca0, 6401 (0_4, AREG, OPRND_SHIFT_0_BIT), 6402 (16_20, AREG, OPRND_SHIFT_0_BIT), 6403 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6404 CSKY_ISA_DSP_ENHANCE), 6405 OP32 ("mulsca.s16.e", 6406 OPCODE_INFO3 (0xf8008ce0, 6407 (0_4, AREG, OPRND_SHIFT_0_BIT), 6408 (16_20, AREG, OPRND_SHIFT_0_BIT), 6409 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6410 CSKY_ISA_DSP_ENHANCE), 6411 OP32 ("mulscax.s16.e", 6412 OPCODE_INFO3 (0xf8008ea0, 6413 (0_4, AREG, OPRND_SHIFT_0_BIT), 6414 (16_20, AREG, OPRND_SHIFT_0_BIT), 6415 (21_25, AREG, OPRND_SHIFT_0_BIT)), 6416 CSKY_ISA_DSP_ENHANCE), 6417 6418 /* The followings are vdsp instructions for ck810. */ 6419 OP32 ("vdup.8", 6420 OPCODE_INFO2 (0xf8000e80, 6421 (0_3, VREG, OPRND_SHIFT_0_BIT), 6422 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6423 CSKY_ISA_VDSP), 6424 OP32 ("vdup.16", 6425 OPCODE_INFO2 (0xf8100e80, 6426 (0_3, VREG, OPRND_SHIFT_0_BIT), 6427 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6428 CSKY_ISA_VDSP), 6429 OP32 ("vdup.32", 6430 OPCODE_INFO2 (0xfa000e80, 6431 (0_3, VREG, OPRND_SHIFT_0_BIT), 6432 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6433 CSKY_ISA_VDSP), 6434 OP32 ("vmfvr.u8", 6435 OPCODE_INFO2 (0xf8001200, 6436 (0_4, AREG, OPRND_SHIFT_0_BIT), 6437 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6438 CSKY_ISA_VDSP), 6439 OP32 ("vmfvr.u16", 6440 OPCODE_INFO2 (0xf8001220, 6441 (0_4, AREG, OPRND_SHIFT_0_BIT), 6442 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6443 CSKY_ISA_VDSP), 6444 OP32 ("vmfvr.u32", 6445 OPCODE_INFO2 (0xf8001240, 6446 (0_4, AREG, OPRND_SHIFT_0_BIT), 6447 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6448 CSKY_ISA_VDSP), 6449 OP32 ("vmfvr.s8", 6450 OPCODE_INFO2 (0xf8001280, 6451 (0_4, AREG, OPRND_SHIFT_0_BIT), 6452 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6453 CSKY_ISA_VDSP), 6454 OP32 ("vmfvr.s16", 6455 OPCODE_INFO2 (0xf80012a0, 6456 (0_4, AREG, OPRND_SHIFT_0_BIT), 6457 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6458 CSKY_ISA_VDSP), 6459 OP32 ("vmtvr.u8", 6460 OPCODE_INFO2 (0xf8001300, 6461 (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6462 (16_20, AREG, OPRND_SHIFT_0_BIT)), 6463 CSKY_ISA_VDSP), 6464 OP32 ("vmtvr.u16", 6465 OPCODE_INFO2 (0xf8001320, 6466 (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6467 (16_20, AREG, OPRND_SHIFT_0_BIT)), 6468 CSKY_ISA_VDSP), 6469 OP32 ("vins.8", 6470 OPCODE_INFO2 (0xf8001400, 6471 (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6472 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6473 CSKY_ISA_VDSP), 6474 OP32 ("vins.16", 6475 OPCODE_INFO2 (0xf8101400, 6476 (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6477 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6478 CSKY_ISA_VDSP), 6479 OP32 ("vins.32", 6480 OPCODE_INFO2 (0xfa001400, 6481 (0_3or5_8, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6482 (16_19or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), 6483 CSKY_ISA_VDSP), 6484 OP32 ("vmtvr.u32", 6485 OPCODE_INFO2 (0xf8001340, 6486 (0_3or21_24, VREG_WITH_INDEX, OPRND_SHIFT_0_BIT), 6487 (16_20, AREG, OPRND_SHIFT_0_BIT)), 6488 CSKY_ISA_VDSP), 6489 OP32 ("vldd.8", 6490 SOPCODE_INFO2 (0xf8002000, 6491 (0_3, VREG, OPRND_SHIFT_0_BIT), 6492 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6493 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6494 CSKY_ISA_VDSP), 6495 OP32 ("vldd.16", 6496 SOPCODE_INFO2 (0xf8002100, 6497 (0_3, VREG, OPRND_SHIFT_0_BIT), 6498 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6499 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6500 CSKY_ISA_VDSP), 6501 OP32 ("vldd.32", 6502 SOPCODE_INFO2 (0xf8002200, 6503 (0_3, VREG, OPRND_SHIFT_0_BIT), 6504 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6505 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6506 CSKY_ISA_VDSP), 6507 OP32 ("vldq.8", 6508 SOPCODE_INFO2 (0xf8002400, 6509 (0_3, VREG, OPRND_SHIFT_0_BIT), 6510 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6511 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6512 CSKY_ISA_VDSP), 6513 OP32 ("vldq.16", 6514 SOPCODE_INFO2 (0xf8002500, 6515 (0_3, VREG, OPRND_SHIFT_0_BIT), 6516 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6517 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6518 CSKY_ISA_VDSP), 6519 OP32 ("vldq.32", 6520 SOPCODE_INFO2 (0xf8002600, 6521 (0_3, VREG, OPRND_SHIFT_0_BIT), 6522 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6523 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6524 CSKY_ISA_VDSP), 6525 OP32 ("vstd.8", 6526 SOPCODE_INFO2 (0xf8002800, 6527 (0_3, VREG, OPRND_SHIFT_0_BIT), 6528 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6529 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6530 CSKY_ISA_VDSP), 6531 OP32 ("vstd.16", 6532 SOPCODE_INFO2 (0xf8002900, 6533 (0_3, VREG, OPRND_SHIFT_0_BIT), 6534 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6535 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6536 CSKY_ISA_VDSP), 6537 OP32 ("vstd.32", 6538 SOPCODE_INFO2 (0xf8002a00, 6539 (0_3, VREG, OPRND_SHIFT_0_BIT), 6540 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6541 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), 6542 CSKY_ISA_VDSP), 6543 OP32 ("vstq.8", 6544 SOPCODE_INFO2 (0xf8002c00, 6545 (0_3, VREG, OPRND_SHIFT_0_BIT), 6546 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6547 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6548 CSKY_ISA_VDSP), 6549 OP32 ("vstq.16", 6550 SOPCODE_INFO2 (0xf8002d00, 6551 (0_3, VREG, OPRND_SHIFT_0_BIT), 6552 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6553 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6554 CSKY_ISA_VDSP), 6555 OP32 ("vstq.32", 6556 SOPCODE_INFO2 (0xf8002e00, 6557 (0_3, VREG, OPRND_SHIFT_0_BIT), 6558 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6559 (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), 6560 CSKY_ISA_VDSP), 6561 OP32 ("vldrd.8", 6562 SOPCODE_INFO2 (0xf8003000, 6563 (0_3, VREG, OPRND_SHIFT_0_BIT), 6564 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6565 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6566 CSKY_ISA_VDSP), 6567 OP32 ("vldrd.16", 6568 SOPCODE_INFO2 (0xf8003100, 6569 (0_3, VREG, OPRND_SHIFT_0_BIT), 6570 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6571 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6572 CSKY_ISA_VDSP), 6573 OP32 ("vldrd.32", 6574 SOPCODE_INFO2 (0xf8003200, 6575 (0_3, VREG, OPRND_SHIFT_0_BIT), 6576 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6577 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6578 CSKY_ISA_VDSP), 6579 OP32 ("vldrq.8", 6580 SOPCODE_INFO2 (0xf8003400, 6581 (0_3, VREG, OPRND_SHIFT_0_BIT), 6582 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6583 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6584 CSKY_ISA_VDSP), 6585 OP32 ("vldrq.16", 6586 SOPCODE_INFO2 (0xf8003500, 6587 (0_3, VREG, OPRND_SHIFT_0_BIT), 6588 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6589 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6590 CSKY_ISA_VDSP), 6591 OP32 ("vldrq.32", 6592 SOPCODE_INFO2 (0xf8003600, 6593 (0_3, VREG, OPRND_SHIFT_0_BIT), 6594 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6595 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6596 CSKY_ISA_VDSP), 6597 OP32 ("vstrd.8", 6598 SOPCODE_INFO2 (0xf8003800, 6599 (0_3, VREG, OPRND_SHIFT_0_BIT), 6600 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6601 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6602 CSKY_ISA_VDSP), 6603 OP32 ("vstrd.16", 6604 SOPCODE_INFO2 (0xf8003900, 6605 (0_3, VREG, OPRND_SHIFT_0_BIT), 6606 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6607 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6608 CSKY_ISA_VDSP), 6609 OP32 ("vstrd.32", 6610 SOPCODE_INFO2 (0xf8003a00, 6611 (0_3, VREG, OPRND_SHIFT_0_BIT), 6612 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6613 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6614 CSKY_ISA_VDSP), 6615 OP32 ("vstrq.8", 6616 SOPCODE_INFO2 (0xf8003c00, 6617 (0_3, VREG, OPRND_SHIFT_0_BIT), 6618 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6619 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6620 CSKY_ISA_VDSP), 6621 OP32 ("vstrq.16", 6622 SOPCODE_INFO2 (0xf8003d00, 6623 (0_3, VREG, OPRND_SHIFT_0_BIT), 6624 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6625 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6626 CSKY_ISA_VDSP), 6627 OP32 ("vstrq.32", 6628 SOPCODE_INFO2 (0xf8003e00, 6629 (0_3, VREG, OPRND_SHIFT_0_BIT), 6630 BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), 6631 (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), 6632 CSKY_ISA_VDSP), 6633 OP32 ("vmov", 6634 OPCODE_INFO2 (0xf8000c00, 6635 (0_3, VREG, OPRND_SHIFT_0_BIT), 6636 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6637 CSKY_ISA_VDSP), 6638 OP32 ("vcadd.eu8", 6639 OPCODE_INFO2 (0xf8000060, 6640 (0_3, VREG, OPRND_SHIFT_0_BIT), 6641 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6642 CSKY_ISA_VDSP), 6643 OP32 ("vcadd.eu16", 6644 OPCODE_INFO2 (0xf8100060, 6645 (0_3, VREG, OPRND_SHIFT_0_BIT), 6646 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6647 CSKY_ISA_VDSP), 6648 OP32 ("vcadd.es8", 6649 OPCODE_INFO2 (0xf8000070, 6650 (0_3, VREG, OPRND_SHIFT_0_BIT), 6651 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6652 CSKY_ISA_VDSP), 6653 OP32 ("vcadd.es16", 6654 OPCODE_INFO2 (0xf8100070, 6655 (0_3, VREG, OPRND_SHIFT_0_BIT), 6656 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6657 CSKY_ISA_VDSP), 6658 OP32 ("vmov.eu8", 6659 OPCODE_INFO2 (0xf8000c20, 6660 (0_3, VREG, OPRND_SHIFT_0_BIT), 6661 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6662 CSKY_ISA_VDSP), 6663 OP32 ("vmov.eu16", 6664 OPCODE_INFO2 (0xf8100c20, 6665 (0_3, VREG, OPRND_SHIFT_0_BIT), 6666 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6667 CSKY_ISA_VDSP), 6668 OP32 ("vmov.es8", 6669 OPCODE_INFO2 (0xf8000c30, 6670 (0_3, VREG, OPRND_SHIFT_0_BIT), 6671 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6672 CSKY_ISA_VDSP), 6673 OP32 ("vmov.es16", 6674 OPCODE_INFO2 (0xf8100c30, 6675 (0_3, VREG, OPRND_SHIFT_0_BIT), 6676 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6677 CSKY_ISA_VDSP), 6678 OP32 ("vmov.u16.l", 6679 OPCODE_INFO2 (0xf8100d00, 6680 (0_3, VREG, OPRND_SHIFT_0_BIT), 6681 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6682 CSKY_ISA_VDSP), 6683 OP32 ("vmov.u32.l", 6684 OPCODE_INFO2 (0xfa000d00, 6685 (0_3, VREG, OPRND_SHIFT_0_BIT), 6686 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6687 CSKY_ISA_VDSP), 6688 OP32 ("vmov.s16.l", 6689 OPCODE_INFO2 (0xf8100d10, 6690 (0_3, VREG, OPRND_SHIFT_0_BIT), 6691 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6692 CSKY_ISA_VDSP), 6693 OP32 ("vmov.s32.l", 6694 OPCODE_INFO2 (0xfa000d10, 6695 (0_3, VREG, OPRND_SHIFT_0_BIT), 6696 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6697 CSKY_ISA_VDSP), 6698 OP32 ("vmov.u16.sl", 6699 OPCODE_INFO2 (0xf8100d40, 6700 (0_3, VREG, OPRND_SHIFT_0_BIT), 6701 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6702 CSKY_ISA_VDSP), 6703 OP32 ("vmov.u32.sl", 6704 OPCODE_INFO2 (0xfa000d40, 6705 (0_3, VREG, OPRND_SHIFT_0_BIT), 6706 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6707 CSKY_ISA_VDSP), 6708 OP32 ("vmov.s16.sl", 6709 OPCODE_INFO2 (0xf8100d50, 6710 (0_3, VREG, OPRND_SHIFT_0_BIT), 6711 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6712 CSKY_ISA_VDSP), 6713 OP32 ("vmov.s32.sl", 6714 OPCODE_INFO2 (0xfa000d50, 6715 (0_3, VREG, OPRND_SHIFT_0_BIT), 6716 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6717 CSKY_ISA_VDSP), 6718 OP32 ("vmov.u16.h", 6719 OPCODE_INFO2 (0xf8100d60, 6720 (0_3, VREG, OPRND_SHIFT_0_BIT), 6721 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6722 CSKY_ISA_VDSP), 6723 OP32 ("vmov.u32.h", 6724 OPCODE_INFO2 (0xfa000d60, 6725 (0_3, VREG, OPRND_SHIFT_0_BIT), 6726 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6727 CSKY_ISA_VDSP), 6728 OP32 ("vmov.s16.h", 6729 OPCODE_INFO2 (0xf8100d70, 6730 (0_3, VREG, OPRND_SHIFT_0_BIT), 6731 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6732 CSKY_ISA_VDSP), 6733 OP32 ("vmov.s32.h", 6734 OPCODE_INFO2 (0xfa000d70, 6735 (0_3, VREG, OPRND_SHIFT_0_BIT), 6736 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6737 CSKY_ISA_VDSP), 6738 OP32 ("vmov.u16.rh", 6739 OPCODE_INFO2 (0xf8100d80, 6740 (0_3, VREG, OPRND_SHIFT_0_BIT), 6741 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6742 CSKY_ISA_VDSP), 6743 OP32 ("vmov.u32.rh", 6744 OPCODE_INFO2 (0xfa000d80, 6745 (0_3, VREG, OPRND_SHIFT_0_BIT), 6746 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6747 CSKY_ISA_VDSP), 6748 OP32 ("vmov.s16.rh", 6749 OPCODE_INFO2 (0xf8100d90, 6750 (0_3, VREG, OPRND_SHIFT_0_BIT), 6751 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6752 CSKY_ISA_VDSP), 6753 OP32 ("vmov.s32.rh", 6754 OPCODE_INFO2 (0xfa000d90, 6755 (0_3, VREG, OPRND_SHIFT_0_BIT), 6756 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6757 CSKY_ISA_VDSP), 6758 OP32 ("vstou.u16.sl", 6759 OPCODE_INFO2 (0xf8100dc0, 6760 (0_3, VREG, OPRND_SHIFT_0_BIT), 6761 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6762 CSKY_ISA_VDSP), 6763 OP32 ("vstou.u32.sl", 6764 OPCODE_INFO2 (0xfa000dc0, 6765 (0_3, VREG, OPRND_SHIFT_0_BIT), 6766 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6767 CSKY_ISA_VDSP), 6768 OP32 ("vstou.s16.sl", 6769 OPCODE_INFO2 (0xf8100dd0, 6770 (0_3, VREG, OPRND_SHIFT_0_BIT), 6771 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6772 CSKY_ISA_VDSP), 6773 OP32 ("vstou.s32.sl", 6774 OPCODE_INFO2 (0xfa000dd0, 6775 (0_3, VREG, OPRND_SHIFT_0_BIT), 6776 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6777 CSKY_ISA_VDSP), 6778 OP32 ("vrev.8", 6779 OPCODE_INFO2 (0xf8000e60, 6780 (0_3, VREG, OPRND_SHIFT_0_BIT), 6781 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6782 CSKY_ISA_VDSP), 6783 OP32 ("vrev.16", 6784 OPCODE_INFO2 (0xf8100e60, 6785 (0_3, VREG, OPRND_SHIFT_0_BIT), 6786 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6787 CSKY_ISA_VDSP), 6788 OP32 ("vrev.32", 6789 OPCODE_INFO2 (0xfa000e60, 6790 (0_3, VREG, OPRND_SHIFT_0_BIT), 6791 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6792 CSKY_ISA_VDSP), 6793 OP32 ("vcnt1.8", 6794 OPCODE_INFO2 (0xf8000ea0, 6795 (0_3, VREG, OPRND_SHIFT_0_BIT), 6796 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6797 CSKY_ISA_VDSP), 6798 OP32 ("vclz.8", 6799 OPCODE_INFO2 (0xf8000ec0, 6800 (0_3, VREG, OPRND_SHIFT_0_BIT), 6801 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6802 CSKY_ISA_VDSP), 6803 OP32 ("vclz.16", 6804 OPCODE_INFO2 (0xf8100ec0, 6805 (0_3, VREG, OPRND_SHIFT_0_BIT), 6806 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6807 CSKY_ISA_VDSP), 6808 OP32 ("vclz.32", 6809 OPCODE_INFO2 (0xfa000ec0, 6810 (0_3, VREG, OPRND_SHIFT_0_BIT), 6811 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6812 CSKY_ISA_VDSP), 6813 OP32 ("vcls.u8", 6814 OPCODE_INFO2 (0xf8000ee0, 6815 (0_3, VREG, OPRND_SHIFT_0_BIT), 6816 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6817 CSKY_ISA_VDSP), 6818 OP32 ("vcls.u16", 6819 OPCODE_INFO2 (0xf8100ee0, 6820 (0_3, VREG, OPRND_SHIFT_0_BIT), 6821 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6822 CSKY_ISA_VDSP), 6823 OP32 ("vcls.u32", 6824 OPCODE_INFO2 (0xfa000ee0, 6825 (0_3, VREG, OPRND_SHIFT_0_BIT), 6826 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6827 CSKY_ISA_VDSP), 6828 OP32 ("vcls.s8", 6829 OPCODE_INFO2 (0xf8000ef0, 6830 (0_3, VREG, OPRND_SHIFT_0_BIT), 6831 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6832 CSKY_ISA_VDSP), 6833 OP32 ("vcls.s16", 6834 OPCODE_INFO2 (0xf8100ef0, 6835 (0_3, VREG, OPRND_SHIFT_0_BIT), 6836 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6837 CSKY_ISA_VDSP), 6838 OP32 ("vcls.s32", 6839 OPCODE_INFO2 (0xfa000ef0, 6840 (0_3, VREG, OPRND_SHIFT_0_BIT), 6841 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6842 CSKY_ISA_VDSP), 6843 OP32 ("vabs.s8", 6844 OPCODE_INFO2 (0xf8001010, 6845 (0_3, VREG, OPRND_SHIFT_0_BIT), 6846 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6847 CSKY_ISA_VDSP), 6848 OP32 ("vabs.s16", 6849 OPCODE_INFO2 (0xf8101010, 6850 (0_3, VREG, OPRND_SHIFT_0_BIT), 6851 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6852 CSKY_ISA_VDSP), 6853 OP32 ("vabs.s32", 6854 OPCODE_INFO2 (0xfa001010, 6855 (0_3, VREG, OPRND_SHIFT_0_BIT), 6856 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6857 CSKY_ISA_VDSP), 6858 OP32 ("vabs.u8.s", 6859 OPCODE_INFO2 (0xf8001040, 6860 (0_3, VREG, OPRND_SHIFT_0_BIT), 6861 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6862 CSKY_ISA_VDSP), 6863 OP32 ("vabs.u16.s", 6864 OPCODE_INFO2 (0xf8101040, 6865 (0_3, VREG, OPRND_SHIFT_0_BIT), 6866 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6867 CSKY_ISA_VDSP), 6868 OP32 ("vabs.u32.s", 6869 OPCODE_INFO2 (0xfa001040, 6870 (0_3, VREG, OPRND_SHIFT_0_BIT), 6871 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6872 CSKY_ISA_VDSP), 6873 OP32 ("vabs.s8.s", 6874 OPCODE_INFO2 (0xf8001050, 6875 (0_3, VREG, OPRND_SHIFT_0_BIT), 6876 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6877 CSKY_ISA_VDSP), 6878 OP32 ("vabs.s16.s", 6879 OPCODE_INFO2 (0xf8101050, 6880 (0_3, VREG, OPRND_SHIFT_0_BIT), 6881 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6882 CSKY_ISA_VDSP), 6883 OP32 ("vabs.s32.s", 6884 OPCODE_INFO2 (0xfa001050, 6885 (0_3, VREG, OPRND_SHIFT_0_BIT), 6886 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6887 CSKY_ISA_VDSP), 6888 OP32 ("vneg.u8", 6889 OPCODE_INFO2 (0xf8001080, 6890 (0_3, VREG, OPRND_SHIFT_0_BIT), 6891 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6892 CSKY_ISA_VDSP), 6893 OP32 ("vneg.u16", 6894 OPCODE_INFO2 (0xf8101080, 6895 (0_3, VREG, OPRND_SHIFT_0_BIT), 6896 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6897 CSKY_ISA_VDSP), 6898 OP32 ("vneg.u32", 6899 OPCODE_INFO2 (0xfa001080, 6900 (0_3, VREG, OPRND_SHIFT_0_BIT), 6901 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6902 CSKY_ISA_VDSP), 6903 OP32 ("vneg.s8", 6904 OPCODE_INFO2 (0xf8001090, 6905 (0_3, VREG, OPRND_SHIFT_0_BIT), 6906 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6907 CSKY_ISA_VDSP), 6908 OP32 ("vneg.s16", 6909 OPCODE_INFO2 (0xf8101090, 6910 (0_3, VREG, OPRND_SHIFT_0_BIT), 6911 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6912 CSKY_ISA_VDSP), 6913 OP32 ("vneg.s32", 6914 OPCODE_INFO2 (0xfa001090, 6915 (0_3, VREG, OPRND_SHIFT_0_BIT), 6916 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6917 CSKY_ISA_VDSP), 6918 OP32 ("vneg.u8.s", 6919 OPCODE_INFO2 (0xf80010c0, 6920 (0_3, VREG, OPRND_SHIFT_0_BIT), 6921 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6922 CSKY_ISA_VDSP), 6923 OP32 ("vneg.u16.s", 6924 OPCODE_INFO2 (0xf81010c0, 6925 (0_3, VREG, OPRND_SHIFT_0_BIT), 6926 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6927 CSKY_ISA_VDSP), 6928 OP32 ("vneg.u32.s", 6929 OPCODE_INFO2 (0xfa0010c0, 6930 (0_3, VREG, OPRND_SHIFT_0_BIT), 6931 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6932 CSKY_ISA_VDSP), 6933 OP32 ("vneg.s8.s", 6934 OPCODE_INFO2 (0xf80010d0, 6935 (0_3, VREG, OPRND_SHIFT_0_BIT), 6936 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6937 CSKY_ISA_VDSP), 6938 OP32 ("vneg.s16.s", 6939 OPCODE_INFO2 (0xf81010d0, 6940 (0_3, VREG, OPRND_SHIFT_0_BIT), 6941 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6942 CSKY_ISA_VDSP), 6943 OP32 ("vneg.s32.s", 6944 OPCODE_INFO2 (0xfa0010d0, 6945 (0_3, VREG, OPRND_SHIFT_0_BIT), 6946 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6947 CSKY_ISA_VDSP), 6948 OP32 ("vcmphsz.u8", 6949 OPCODE_INFO2 (0xf8000880, 6950 (0_3, VREG, OPRND_SHIFT_0_BIT), 6951 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6952 CSKY_ISA_VDSP), 6953 OP32 ("vcmphsz.u16", 6954 OPCODE_INFO2 (0xf8100880, 6955 (0_3, VREG, OPRND_SHIFT_0_BIT), 6956 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6957 CSKY_ISA_VDSP), 6958 OP32 ("vcmphsz.u32", 6959 OPCODE_INFO2 (0xfa000880, 6960 (0_3, VREG, OPRND_SHIFT_0_BIT), 6961 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6962 CSKY_ISA_VDSP), 6963 OP32 ("vcmphsz.s8", 6964 OPCODE_INFO2 (0xf8000890, 6965 (0_3, VREG, OPRND_SHIFT_0_BIT), 6966 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6967 CSKY_ISA_VDSP), 6968 OP32 ("vcmphsz.s16", 6969 OPCODE_INFO2 (0xf8100890, 6970 (0_3, VREG, OPRND_SHIFT_0_BIT), 6971 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6972 CSKY_ISA_VDSP), 6973 OP32 ("vcmphsz.s32", 6974 OPCODE_INFO2 (0xfa000890, 6975 (0_3, VREG, OPRND_SHIFT_0_BIT), 6976 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6977 CSKY_ISA_VDSP), 6978 OP32 ("vcmpltz.u8", 6979 OPCODE_INFO2 (0xf80008a0, 6980 (0_3, VREG, OPRND_SHIFT_0_BIT), 6981 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6982 CSKY_ISA_VDSP), 6983 OP32 ("vcmpltz.u16", 6984 OPCODE_INFO2 (0xf81008a0, 6985 (0_3, VREG, OPRND_SHIFT_0_BIT), 6986 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6987 CSKY_ISA_VDSP), 6988 OP32 ("vcmpltz.u32", 6989 OPCODE_INFO2 (0xfa0008a0, 6990 (0_3, VREG, OPRND_SHIFT_0_BIT), 6991 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6992 CSKY_ISA_VDSP), 6993 OP32 ("vcmpltz.s8", 6994 OPCODE_INFO2 (0xf80008b0, 6995 (0_3, VREG, OPRND_SHIFT_0_BIT), 6996 (16_19, VREG, OPRND_SHIFT_0_BIT)), 6997 CSKY_ISA_VDSP), 6998 OP32 ("vcmpltz.s16", 6999 OPCODE_INFO2 (0xf81008b0, 7000 (0_3, VREG, OPRND_SHIFT_0_BIT), 7001 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7002 CSKY_ISA_VDSP), 7003 OP32 ("vcmpltz.s32", 7004 OPCODE_INFO2 (0xfa0008b0, 7005 (0_3, VREG, OPRND_SHIFT_0_BIT), 7006 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7007 CSKY_ISA_VDSP), 7008 OP32 ("vcmpnez.u8", 7009 OPCODE_INFO2 (0xf80008c0, 7010 (0_3, VREG, OPRND_SHIFT_0_BIT), 7011 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7012 CSKY_ISA_VDSP), 7013 OP32 ("vcmpnez.u16", 7014 OPCODE_INFO2 (0xf81008c0, 7015 (0_3, VREG, OPRND_SHIFT_0_BIT), 7016 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7017 CSKY_ISA_VDSP), 7018 OP32 ("vcmpnez.u32", 7019 OPCODE_INFO2 (0xfa0008c0, 7020 (0_3, VREG, OPRND_SHIFT_0_BIT), 7021 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7022 CSKY_ISA_VDSP), 7023 OP32 ("vcmpnez.s8", 7024 OPCODE_INFO2 (0xf80008d0, 7025 (0_3, VREG, OPRND_SHIFT_0_BIT), 7026 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7027 CSKY_ISA_VDSP), 7028 OP32 ("vcmpnez.s16", 7029 OPCODE_INFO2 (0xf81008d0, 7030 (0_3, VREG, OPRND_SHIFT_0_BIT), 7031 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7032 CSKY_ISA_VDSP), 7033 OP32 ("vcmpnez.s32", 7034 OPCODE_INFO2 (0xfa0008d0, 7035 (0_3, VREG, OPRND_SHIFT_0_BIT), 7036 (16_19, VREG, OPRND_SHIFT_0_BIT)), 7037 CSKY_ISA_VDSP), 7038 OP32 ("vtrch.8", 7039 OPCODE_INFO3 (0xf8000f40, 7040 (0_3, VREG, OPRND_SHIFT_0_BIT), 7041 (16_19, VREG, OPRND_SHIFT_0_BIT), 7042 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7043 CSKY_ISA_VDSP), 7044 OP32 ("vtrch.16", 7045 OPCODE_INFO3 (0xf8100f40, 7046 (0_3, VREG, OPRND_SHIFT_0_BIT), 7047 (16_19, VREG, OPRND_SHIFT_0_BIT), 7048 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7049 CSKY_ISA_VDSP), 7050 OP32 ("vtrch.32", 7051 OPCODE_INFO3 (0xfa000f40, 7052 (0_3, VREG, OPRND_SHIFT_0_BIT), 7053 (16_19, VREG, OPRND_SHIFT_0_BIT), 7054 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7055 CSKY_ISA_VDSP), 7056 OP32 ("vtrcl.8", 7057 OPCODE_INFO3 (0xf8000f60, 7058 (0_3, VREG, OPRND_SHIFT_0_BIT), 7059 (16_19, VREG, OPRND_SHIFT_0_BIT), 7060 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7061 CSKY_ISA_VDSP), 7062 OP32 ("vtrcl.16", 7063 OPCODE_INFO3 (0xf8100f60, 7064 (0_3, VREG, OPRND_SHIFT_0_BIT), 7065 (16_19, VREG, OPRND_SHIFT_0_BIT), 7066 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7067 CSKY_ISA_VDSP), 7068 OP32 ("vtrcl.32", 7069 OPCODE_INFO3 (0xfa000f60, 7070 (0_3, VREG, OPRND_SHIFT_0_BIT), 7071 (16_19, VREG, OPRND_SHIFT_0_BIT), 7072 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7073 CSKY_ISA_VDSP), 7074 OP32 ("vadd.u8", 7075 OPCODE_INFO3 (0xf8000000, 7076 (0_3, VREG, OPRND_SHIFT_0_BIT), 7077 (16_19, VREG, OPRND_SHIFT_0_BIT), 7078 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7079 CSKY_ISA_VDSP), 7080 OP32 ("vadd.u16", 7081 OPCODE_INFO3 (0xf8100000, 7082 (0_3, VREG, OPRND_SHIFT_0_BIT), 7083 (16_19, VREG, OPRND_SHIFT_0_BIT), 7084 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7085 CSKY_ISA_VDSP), 7086 OP32 ("vadd.u32", 7087 OPCODE_INFO3 (0xfa000000, 7088 (0_3, VREG, OPRND_SHIFT_0_BIT), 7089 (16_19, VREG, OPRND_SHIFT_0_BIT), 7090 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7091 CSKY_ISA_VDSP), 7092 OP32 ("vadd.s8", 7093 OPCODE_INFO3 (0xf8000010, 7094 (0_3, VREG, OPRND_SHIFT_0_BIT), 7095 (16_19, VREG, OPRND_SHIFT_0_BIT), 7096 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7097 CSKY_ISA_VDSP), 7098 OP32 ("vadd.s16", 7099 OPCODE_INFO3 (0xf8100010, 7100 (0_3, VREG, OPRND_SHIFT_0_BIT), 7101 (16_19, VREG, OPRND_SHIFT_0_BIT), 7102 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7103 CSKY_ISA_VDSP), 7104 OP32 ("vadd.s32", 7105 OPCODE_INFO3 (0xfa000010, 7106 (0_3, VREG, OPRND_SHIFT_0_BIT), 7107 (16_19, VREG, OPRND_SHIFT_0_BIT), 7108 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7109 CSKY_ISA_VDSP), 7110 OP32 ("vadd.eu8", 7111 OPCODE_INFO3 (0xf8000020, 7112 (0_3, VREG, OPRND_SHIFT_0_BIT), 7113 (16_19, VREG, OPRND_SHIFT_0_BIT), 7114 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7115 CSKY_ISA_VDSP), 7116 OP32 ("vadd.eu16", 7117 OPCODE_INFO3 (0xf8100020, 7118 (0_3, VREG, OPRND_SHIFT_0_BIT), 7119 (16_19, VREG, OPRND_SHIFT_0_BIT), 7120 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7121 CSKY_ISA_VDSP), 7122 OP32 ("vadd.es8", 7123 OPCODE_INFO3 (0xf8000030, 7124 (0_3, VREG, OPRND_SHIFT_0_BIT), 7125 (16_19, VREG, OPRND_SHIFT_0_BIT), 7126 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7127 CSKY_ISA_VDSP), 7128 OP32 ("vadd.es16", 7129 OPCODE_INFO3 (0xf8100030, 7130 (0_3, VREG, OPRND_SHIFT_0_BIT), 7131 (16_19, VREG, OPRND_SHIFT_0_BIT), 7132 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7133 CSKY_ISA_VDSP), 7134 OP32 ("vcadd.u8", 7135 OPCODE_INFO3 (0xf8000040, 7136 (0_3, VREG, OPRND_SHIFT_0_BIT), 7137 (16_19, VREG, OPRND_SHIFT_0_BIT), 7138 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7139 CSKY_ISA_VDSP), 7140 OP32 ("vcadd.u16", 7141 OPCODE_INFO3 (0xf8100040, 7142 (0_3, VREG, OPRND_SHIFT_0_BIT), 7143 (16_19, VREG, OPRND_SHIFT_0_BIT), 7144 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7145 CSKY_ISA_VDSP), 7146 OP32 ("vcadd.u32", 7147 OPCODE_INFO3 (0xfa000040, 7148 (0_3, VREG, OPRND_SHIFT_0_BIT), 7149 (16_19, VREG, OPRND_SHIFT_0_BIT), 7150 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7151 CSKY_ISA_VDSP), 7152 OP32 ("vcadd.s8", 7153 OPCODE_INFO3 (0xf8000050, 7154 (0_3, VREG, OPRND_SHIFT_0_BIT), 7155 (16_19, VREG, OPRND_SHIFT_0_BIT), 7156 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7157 CSKY_ISA_VDSP), 7158 OP32 ("vcadd.s16", 7159 OPCODE_INFO3 (0xf8100050, 7160 (0_3, VREG, OPRND_SHIFT_0_BIT), 7161 (16_19, VREG, OPRND_SHIFT_0_BIT), 7162 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7163 CSKY_ISA_VDSP), 7164 OP32 ("vcadd.s32", 7165 OPCODE_INFO3 (0xfa000050, 7166 (0_3, VREG, OPRND_SHIFT_0_BIT), 7167 (16_19, VREG, OPRND_SHIFT_0_BIT), 7168 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7169 CSKY_ISA_VDSP), 7170 OP32 ("vadd.xu16.sl", 7171 OPCODE_INFO3 (0xf8100140, 7172 (0_3, VREG, OPRND_SHIFT_0_BIT), 7173 (16_19, VREG, OPRND_SHIFT_0_BIT), 7174 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7175 CSKY_ISA_VDSP), 7176 OP32 ("vadd.xu32.sl", 7177 OPCODE_INFO3 (0xfa000140, 7178 (0_3, VREG, OPRND_SHIFT_0_BIT), 7179 (16_19, VREG, OPRND_SHIFT_0_BIT), 7180 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7181 CSKY_ISA_VDSP), 7182 OP32 ("vadd.xs16.sl", 7183 OPCODE_INFO3 (0xf8100150, 7184 (0_3, VREG, OPRND_SHIFT_0_BIT), 7185 (16_19, VREG, OPRND_SHIFT_0_BIT), 7186 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7187 CSKY_ISA_VDSP), 7188 OP32 ("vadd.xs32.sl", 7189 OPCODE_INFO3 (0xfa000150, 7190 (0_3, VREG, OPRND_SHIFT_0_BIT), 7191 (16_19, VREG, OPRND_SHIFT_0_BIT), 7192 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7193 CSKY_ISA_VDSP), 7194 OP32 ("vadd.xu16", 7195 OPCODE_INFO3 (0xf8100160, 7196 (0_3, VREG, OPRND_SHIFT_0_BIT), 7197 (16_19, VREG, OPRND_SHIFT_0_BIT), 7198 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7199 CSKY_ISA_VDSP), 7200 OP32 ("vadd.xu32", 7201 OPCODE_INFO3 (0xfa000160, 7202 (0_3, VREG, OPRND_SHIFT_0_BIT), 7203 (16_19, VREG, OPRND_SHIFT_0_BIT), 7204 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7205 CSKY_ISA_VDSP), 7206 OP32 ("vadd.xs16", 7207 OPCODE_INFO3 (0xf8100170, 7208 (0_3, VREG, OPRND_SHIFT_0_BIT), 7209 (16_19, VREG, OPRND_SHIFT_0_BIT), 7210 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7211 CSKY_ISA_VDSP), 7212 OP32 ("vadd.xs32", 7213 OPCODE_INFO3 (0xfa000170, 7214 (0_3, VREG, OPRND_SHIFT_0_BIT), 7215 (16_19, VREG, OPRND_SHIFT_0_BIT), 7216 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7217 CSKY_ISA_VDSP), 7218 OP32 ("vaddh.u8", 7219 OPCODE_INFO3 (0xf8000180, 7220 (0_3, VREG, OPRND_SHIFT_0_BIT), 7221 (16_19, VREG, OPRND_SHIFT_0_BIT), 7222 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7223 CSKY_ISA_VDSP), 7224 OP32 ("vaddh.u16", 7225 OPCODE_INFO3 (0xf8100180, 7226 (0_3, VREG, OPRND_SHIFT_0_BIT), 7227 (16_19, VREG, OPRND_SHIFT_0_BIT), 7228 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7229 CSKY_ISA_VDSP), 7230 OP32 ("vaddh.u32", 7231 OPCODE_INFO3 (0xfa000180, 7232 (0_3, VREG, OPRND_SHIFT_0_BIT), 7233 (16_19, VREG, OPRND_SHIFT_0_BIT), 7234 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7235 CSKY_ISA_VDSP), 7236 OP32 ("vaddh.s8", 7237 OPCODE_INFO3 (0xf8000190, 7238 (0_3, VREG, OPRND_SHIFT_0_BIT), 7239 (16_19, VREG, OPRND_SHIFT_0_BIT), 7240 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7241 CSKY_ISA_VDSP), 7242 OP32 ("vaddh.s16", 7243 OPCODE_INFO3 (0xf8100190, 7244 (0_3, VREG, OPRND_SHIFT_0_BIT), 7245 (16_19, VREG, OPRND_SHIFT_0_BIT), 7246 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7247 CSKY_ISA_VDSP), 7248 OP32 ("vaddh.s32", 7249 OPCODE_INFO3 (0xfa000190, 7250 (0_3, VREG, OPRND_SHIFT_0_BIT), 7251 (16_19, VREG, OPRND_SHIFT_0_BIT), 7252 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7253 CSKY_ISA_VDSP), 7254 OP32 ("vaddh.u8.r", 7255 OPCODE_INFO3 (0xf80001a0, 7256 (0_3, VREG, OPRND_SHIFT_0_BIT), 7257 (16_19, VREG, OPRND_SHIFT_0_BIT), 7258 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7259 CSKY_ISA_VDSP), 7260 OP32 ("vaddh.u16.r", 7261 OPCODE_INFO3 (0xf81001a0, 7262 (0_3, VREG, OPRND_SHIFT_0_BIT), 7263 (16_19, VREG, OPRND_SHIFT_0_BIT), 7264 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7265 CSKY_ISA_VDSP), 7266 OP32 ("vaddh.u32.r", 7267 OPCODE_INFO3 (0xfa0001a0, 7268 (0_3, VREG, OPRND_SHIFT_0_BIT), 7269 (16_19, VREG, OPRND_SHIFT_0_BIT), 7270 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7271 CSKY_ISA_VDSP), 7272 OP32 ("vaddh.s8.r", 7273 OPCODE_INFO3 (0xf80001b0, 7274 (0_3, VREG, OPRND_SHIFT_0_BIT), 7275 (16_19, VREG, OPRND_SHIFT_0_BIT), 7276 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7277 CSKY_ISA_VDSP), 7278 OP32 ("vaddh.s16.r", 7279 OPCODE_INFO3 (0xf81001b0, 7280 (0_3, VREG, OPRND_SHIFT_0_BIT), 7281 (16_19, VREG, OPRND_SHIFT_0_BIT), 7282 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7283 CSKY_ISA_VDSP), 7284 OP32 ("vaddh.s32.r", 7285 OPCODE_INFO3 (0xfa0001b0, 7286 (0_3, VREG, OPRND_SHIFT_0_BIT), 7287 (16_19, VREG, OPRND_SHIFT_0_BIT), 7288 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7289 CSKY_ISA_VDSP), 7290 OP32 ("vadd.u8.s", 7291 OPCODE_INFO3 (0xf80001c0, 7292 (0_3, VREG, OPRND_SHIFT_0_BIT), 7293 (16_19, VREG, OPRND_SHIFT_0_BIT), 7294 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7295 CSKY_ISA_VDSP), 7296 OP32 ("vadd.u16.s", 7297 OPCODE_INFO3 (0xf81001c0, 7298 (0_3, VREG, OPRND_SHIFT_0_BIT), 7299 (16_19, VREG, OPRND_SHIFT_0_BIT), 7300 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7301 CSKY_ISA_VDSP), 7302 OP32 ("vadd.u32.s", 7303 OPCODE_INFO3 (0xfa0001c0, 7304 (0_3, VREG, OPRND_SHIFT_0_BIT), 7305 (16_19, VREG, OPRND_SHIFT_0_BIT), 7306 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7307 CSKY_ISA_VDSP), 7308 OP32 ("vadd.s8.s", 7309 OPCODE_INFO3 (0xf80001d0, 7310 (0_3, VREG, OPRND_SHIFT_0_BIT), 7311 (16_19, VREG, OPRND_SHIFT_0_BIT), 7312 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7313 CSKY_ISA_VDSP), 7314 OP32 ("vadd.s16.s", 7315 OPCODE_INFO3 (0xf81001d0, 7316 (0_3, VREG, OPRND_SHIFT_0_BIT), 7317 (16_19, VREG, OPRND_SHIFT_0_BIT), 7318 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7319 CSKY_ISA_VDSP), 7320 OP32 ("vadd.s32.s", 7321 OPCODE_INFO3 (0xfa0001d0, 7322 (0_3, VREG, OPRND_SHIFT_0_BIT), 7323 (16_19, VREG, OPRND_SHIFT_0_BIT), 7324 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7325 CSKY_ISA_VDSP), 7326 OP32 ("vsub.u8", 7327 OPCODE_INFO3 (0xf8000200, 7328 (0_3, VREG, OPRND_SHIFT_0_BIT), 7329 (16_19, VREG, OPRND_SHIFT_0_BIT), 7330 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7331 CSKY_ISA_VDSP), 7332 OP32 ("vsub.u16", 7333 OPCODE_INFO3 (0xf8100200, 7334 (0_3, VREG, OPRND_SHIFT_0_BIT), 7335 (16_19, VREG, OPRND_SHIFT_0_BIT), 7336 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7337 CSKY_ISA_VDSP), 7338 OP32 ("vsub.u32", 7339 OPCODE_INFO3 (0xfa000200, 7340 (0_3, VREG, OPRND_SHIFT_0_BIT), 7341 (16_19, VREG, OPRND_SHIFT_0_BIT), 7342 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7343 CSKY_ISA_VDSP), 7344 OP32 ("vsub.s8", 7345 OPCODE_INFO3 (0xf8000210, 7346 (0_3, VREG, OPRND_SHIFT_0_BIT), 7347 (16_19, VREG, OPRND_SHIFT_0_BIT), 7348 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7349 CSKY_ISA_VDSP), 7350 OP32 ("vsub.s16", 7351 OPCODE_INFO3 (0xf8100210, 7352 (0_3, VREG, OPRND_SHIFT_0_BIT), 7353 (16_19, VREG, OPRND_SHIFT_0_BIT), 7354 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7355 CSKY_ISA_VDSP), 7356 OP32 ("vsub.s32", 7357 OPCODE_INFO3 (0xfa000210, 7358 (0_3, VREG, OPRND_SHIFT_0_BIT), 7359 (16_19, VREG, OPRND_SHIFT_0_BIT), 7360 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7361 CSKY_ISA_VDSP), 7362 OP32 ("vsub.eu8", 7363 OPCODE_INFO3 (0xf8000220, 7364 (0_3, VREG, OPRND_SHIFT_0_BIT), 7365 (16_19, VREG, OPRND_SHIFT_0_BIT), 7366 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7367 CSKY_ISA_VDSP), 7368 OP32 ("vsub.eu16", 7369 OPCODE_INFO3 (0xf8100220, 7370 (0_3, VREG, OPRND_SHIFT_0_BIT), 7371 (16_19, VREG, OPRND_SHIFT_0_BIT), 7372 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7373 CSKY_ISA_VDSP), 7374 OP32 ("vsub.eu32", 7375 OPCODE_INFO3 (0xfa000220, 7376 (0_3, VREG, OPRND_SHIFT_0_BIT), 7377 (16_19, VREG, OPRND_SHIFT_0_BIT), 7378 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7379 CSKY_ISA_VDSP), 7380 OP32 ("vsub.es8", 7381 OPCODE_INFO3 (0xf8000230, 7382 (0_3, VREG, OPRND_SHIFT_0_BIT), 7383 (16_19, VREG, OPRND_SHIFT_0_BIT), 7384 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7385 CSKY_ISA_VDSP), 7386 OP32 ("vsub.es16", 7387 OPCODE_INFO3 (0xf8100230, 7388 (0_3, VREG, OPRND_SHIFT_0_BIT), 7389 (16_19, VREG, OPRND_SHIFT_0_BIT), 7390 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7391 CSKY_ISA_VDSP), 7392 OP32 ("vsub.es32", 7393 OPCODE_INFO3 (0xfa000230, 7394 (0_3, VREG, OPRND_SHIFT_0_BIT), 7395 (16_19, VREG, OPRND_SHIFT_0_BIT), 7396 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7397 CSKY_ISA_VDSP), 7398 OP32 ("vsabs.u8", 7399 OPCODE_INFO3 (0xf8000240, 7400 (0_3, VREG, OPRND_SHIFT_0_BIT), 7401 (16_19, VREG, OPRND_SHIFT_0_BIT), 7402 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7403 CSKY_ISA_VDSP), 7404 OP32 ("vsabs.u16", 7405 OPCODE_INFO3 (0xf8100240, 7406 (0_3, VREG, OPRND_SHIFT_0_BIT), 7407 (16_19, VREG, OPRND_SHIFT_0_BIT), 7408 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7409 CSKY_ISA_VDSP), 7410 OP32 ("vsabs.u32", 7411 OPCODE_INFO3 (0xfa000240, 7412 (0_3, VREG, OPRND_SHIFT_0_BIT), 7413 (16_19, VREG, OPRND_SHIFT_0_BIT), 7414 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7415 CSKY_ISA_VDSP), 7416 OP32 ("vsabs.s8", 7417 OPCODE_INFO3 (0xf8000250, 7418 (0_3, VREG, OPRND_SHIFT_0_BIT), 7419 (16_19, VREG, OPRND_SHIFT_0_BIT), 7420 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7421 CSKY_ISA_VDSP), 7422 OP32 ("vsabs.s16", 7423 OPCODE_INFO3 (0xf8100250, 7424 (0_3, VREG, OPRND_SHIFT_0_BIT), 7425 (16_19, VREG, OPRND_SHIFT_0_BIT), 7426 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7427 CSKY_ISA_VDSP), 7428 OP32 ("vsabs.s32", 7429 OPCODE_INFO3 (0xfa000250, 7430 (0_3, VREG, OPRND_SHIFT_0_BIT), 7431 (16_19, VREG, OPRND_SHIFT_0_BIT), 7432 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7433 CSKY_ISA_VDSP), 7434 OP32 ("vsabs.eu8", 7435 OPCODE_INFO3 (0xf8000260, 7436 (0_3, VREG, OPRND_SHIFT_0_BIT), 7437 (16_19, VREG, OPRND_SHIFT_0_BIT), 7438 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7439 CSKY_ISA_VDSP), 7440 OP32 ("vsabs.eu16", 7441 OPCODE_INFO3 (0xf8100260, 7442 (0_3, VREG, OPRND_SHIFT_0_BIT), 7443 (16_19, VREG, OPRND_SHIFT_0_BIT), 7444 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7445 CSKY_ISA_VDSP), 7446 OP32 ("vsabs.es8", 7447 OPCODE_INFO3 (0xf8000270, 7448 (0_3, VREG, OPRND_SHIFT_0_BIT), 7449 (16_19, VREG, OPRND_SHIFT_0_BIT), 7450 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7451 CSKY_ISA_VDSP), 7452 OP32 ("vsabs.es16", 7453 OPCODE_INFO3 (0xf8100270, 7454 (0_3, VREG, OPRND_SHIFT_0_BIT), 7455 (16_19, VREG, OPRND_SHIFT_0_BIT), 7456 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7457 CSKY_ISA_VDSP), 7458 OP32 ("vsabsa.u8", 7459 OPCODE_INFO3 (0xf8000280, 7460 (0_3, VREG, OPRND_SHIFT_0_BIT), 7461 (16_19, VREG, OPRND_SHIFT_0_BIT), 7462 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7463 CSKY_ISA_VDSP), 7464 OP32 ("vsabsa.u16", 7465 OPCODE_INFO3 (0xf8100280, 7466 (0_3, VREG, OPRND_SHIFT_0_BIT), 7467 (16_19, VREG, OPRND_SHIFT_0_BIT), 7468 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7469 CSKY_ISA_VDSP), 7470 OP32 ("vsabsa.u32", 7471 OPCODE_INFO3 (0xfa000280, 7472 (0_3, VREG, OPRND_SHIFT_0_BIT), 7473 (16_19, VREG, OPRND_SHIFT_0_BIT), 7474 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7475 CSKY_ISA_VDSP), 7476 OP32 ("vsabsa.s8", 7477 OPCODE_INFO3 (0xf8000290, 7478 (0_3, VREG, OPRND_SHIFT_0_BIT), 7479 (16_19, VREG, OPRND_SHIFT_0_BIT), 7480 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7481 CSKY_ISA_VDSP), 7482 OP32 ("vsabsa.s16", 7483 OPCODE_INFO3 (0xf8100290, 7484 (0_3, VREG, OPRND_SHIFT_0_BIT), 7485 (16_19, VREG, OPRND_SHIFT_0_BIT), 7486 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7487 CSKY_ISA_VDSP), 7488 OP32 ("vsabsa.s32", 7489 OPCODE_INFO3 (0xfa000290, 7490 (0_3, VREG, OPRND_SHIFT_0_BIT), 7491 (16_19, VREG, OPRND_SHIFT_0_BIT), 7492 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7493 CSKY_ISA_VDSP), 7494 OP32 ("vsabsa.eu8", 7495 OPCODE_INFO3 (0xf80002a0, 7496 (0_3, VREG, OPRND_SHIFT_0_BIT), 7497 (16_19, VREG, OPRND_SHIFT_0_BIT), 7498 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7499 CSKY_ISA_VDSP), 7500 OP32 ("vsabsa.eu16", 7501 OPCODE_INFO3 (0xf81002a0, 7502 (0_3, VREG, OPRND_SHIFT_0_BIT), 7503 (16_19, VREG, OPRND_SHIFT_0_BIT), 7504 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7505 CSKY_ISA_VDSP), 7506 OP32 ("vsabsa.es8", 7507 OPCODE_INFO3 (0xf80002b0, 7508 (0_3, VREG, OPRND_SHIFT_0_BIT), 7509 (16_19, VREG, OPRND_SHIFT_0_BIT), 7510 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7511 CSKY_ISA_VDSP), 7512 OP32 ("vsabsa.es16", 7513 OPCODE_INFO3 (0xf81002b0, 7514 (0_3, VREG, OPRND_SHIFT_0_BIT), 7515 (16_19, VREG, OPRND_SHIFT_0_BIT), 7516 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7517 CSKY_ISA_VDSP), 7518 OP32 ("vsub.xu16", 7519 OPCODE_INFO3 (0xf8100360, 7520 (0_3, VREG, OPRND_SHIFT_0_BIT), 7521 (16_19, VREG, OPRND_SHIFT_0_BIT), 7522 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7523 CSKY_ISA_VDSP), 7524 OP32 ("vsub.xu32", 7525 OPCODE_INFO3 (0xfa000360, 7526 (0_3, VREG, OPRND_SHIFT_0_BIT), 7527 (16_19, VREG, OPRND_SHIFT_0_BIT), 7528 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7529 CSKY_ISA_VDSP), 7530 OP32 ("vsub.xs16", 7531 OPCODE_INFO3 (0xf8100370, 7532 (0_3, VREG, OPRND_SHIFT_0_BIT), 7533 (16_19, VREG, OPRND_SHIFT_0_BIT), 7534 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7535 CSKY_ISA_VDSP), 7536 OP32 ("vsub.xs32", 7537 OPCODE_INFO3 (0xfa000370, 7538 (0_3, VREG, OPRND_SHIFT_0_BIT), 7539 (16_19, VREG, OPRND_SHIFT_0_BIT), 7540 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7541 CSKY_ISA_VDSP), 7542 OP32 ("vsubh.u8", 7543 OPCODE_INFO3 (0xf8000380, 7544 (0_3, VREG, OPRND_SHIFT_0_BIT), 7545 (16_19, VREG, OPRND_SHIFT_0_BIT), 7546 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7547 CSKY_ISA_VDSP), 7548 OP32 ("vsubh.u16", 7549 OPCODE_INFO3 (0xf8100380, 7550 (0_3, VREG, OPRND_SHIFT_0_BIT), 7551 (16_19, VREG, OPRND_SHIFT_0_BIT), 7552 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7553 CSKY_ISA_VDSP), 7554 OP32 ("vsubh.u32", 7555 OPCODE_INFO3 (0xfa000380, 7556 (0_3, VREG, OPRND_SHIFT_0_BIT), 7557 (16_19, VREG, OPRND_SHIFT_0_BIT), 7558 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7559 CSKY_ISA_VDSP), 7560 OP32 ("vsubh.s8", 7561 OPCODE_INFO3 (0xf8000390, 7562 (0_3, VREG, OPRND_SHIFT_0_BIT), 7563 (16_19, VREG, OPRND_SHIFT_0_BIT), 7564 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7565 CSKY_ISA_VDSP), 7566 OP32 ("vsubh.s16", 7567 OPCODE_INFO3 (0xf8100390, 7568 (0_3, VREG, OPRND_SHIFT_0_BIT), 7569 (16_19, VREG, OPRND_SHIFT_0_BIT), 7570 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7571 CSKY_ISA_VDSP), 7572 OP32 ("vsubh.s32", 7573 OPCODE_INFO3 (0xfa000390, 7574 (0_3, VREG, OPRND_SHIFT_0_BIT), 7575 (16_19, VREG, OPRND_SHIFT_0_BIT), 7576 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7577 CSKY_ISA_VDSP), 7578 OP32 ("vsubh.u8.r", 7579 OPCODE_INFO3 (0xf80003a0, 7580 (0_3, VREG, OPRND_SHIFT_0_BIT), 7581 (16_19, VREG, OPRND_SHIFT_0_BIT), 7582 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7583 CSKY_ISA_VDSP), 7584 OP32 ("vsubh.u16.r", 7585 OPCODE_INFO3 (0xf81003a0, 7586 (0_3, VREG, OPRND_SHIFT_0_BIT), 7587 (16_19, VREG, OPRND_SHIFT_0_BIT), 7588 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7589 CSKY_ISA_VDSP), 7590 OP32 ("vsubh.u32.r", 7591 OPCODE_INFO3 (0xfa0003a0, 7592 (0_3, VREG, OPRND_SHIFT_0_BIT), 7593 (16_19, VREG, OPRND_SHIFT_0_BIT), 7594 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7595 CSKY_ISA_VDSP), 7596 OP32 ("vsubh.s8.r", 7597 OPCODE_INFO3 (0xf80003b0, 7598 (0_3, VREG, OPRND_SHIFT_0_BIT), 7599 (16_19, VREG, OPRND_SHIFT_0_BIT), 7600 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7601 CSKY_ISA_VDSP), 7602 OP32 ("vsubh.s16.r", 7603 OPCODE_INFO3 (0xf81003b0, 7604 (0_3, VREG, OPRND_SHIFT_0_BIT), 7605 (16_19, VREG, OPRND_SHIFT_0_BIT), 7606 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7607 CSKY_ISA_VDSP), 7608 OP32 ("vsubh.s32.r", 7609 OPCODE_INFO3 (0xfa0003b0, 7610 (0_3, VREG, OPRND_SHIFT_0_BIT), 7611 (16_19, VREG, OPRND_SHIFT_0_BIT), 7612 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7613 CSKY_ISA_VDSP), 7614 OP32 ("vsub.u8.s", 7615 OPCODE_INFO3 (0xf80003c0, 7616 (0_3, VREG, OPRND_SHIFT_0_BIT), 7617 (16_19, VREG, OPRND_SHIFT_0_BIT), 7618 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7619 CSKY_ISA_VDSP), 7620 OP32 ("vsub.u16.s", 7621 OPCODE_INFO3 (0xf81003c0, 7622 (0_3, VREG, OPRND_SHIFT_0_BIT), 7623 (16_19, VREG, OPRND_SHIFT_0_BIT), 7624 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7625 CSKY_ISA_VDSP), 7626 OP32 ("vsub.u32.s", 7627 OPCODE_INFO3 (0xfa0003c0, 7628 (0_3, VREG, OPRND_SHIFT_0_BIT), 7629 (16_19, VREG, OPRND_SHIFT_0_BIT), 7630 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7631 CSKY_ISA_VDSP), 7632 OP32 ("vsub.s8.s", 7633 OPCODE_INFO3 (0xf80003d0, 7634 (0_3, VREG, OPRND_SHIFT_0_BIT), 7635 (16_19, VREG, OPRND_SHIFT_0_BIT), 7636 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7637 CSKY_ISA_VDSP), 7638 OP32 ("vsub.s16.s", 7639 OPCODE_INFO3 (0xf81003d0, 7640 (0_3, VREG, OPRND_SHIFT_0_BIT), 7641 (16_19, VREG, OPRND_SHIFT_0_BIT), 7642 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7643 CSKY_ISA_VDSP), 7644 OP32 ("vsub.s32.s", 7645 OPCODE_INFO3 (0xfa0003d0, 7646 (0_3, VREG, OPRND_SHIFT_0_BIT), 7647 (16_19, VREG, OPRND_SHIFT_0_BIT), 7648 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7649 CSKY_ISA_VDSP), 7650 OP32 ("vmul.u8", 7651 OPCODE_INFO3 (0xf8000400, 7652 (0_3, VREG, OPRND_SHIFT_0_BIT), 7653 (16_19, VREG, OPRND_SHIFT_0_BIT), 7654 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7655 CSKY_ISA_VDSP), 7656 OP32 ("vmul.u16", 7657 OPCODE_INFO3 (0xf8100400, 7658 (0_3, VREG, OPRND_SHIFT_0_BIT), 7659 (16_19, VREG, OPRND_SHIFT_0_BIT), 7660 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7661 CSKY_ISA_VDSP), 7662 OP32 ("vmul.u32", 7663 OPCODE_INFO3 (0xfa000400, 7664 (0_3, VREG, OPRND_SHIFT_0_BIT), 7665 (16_19, VREG, OPRND_SHIFT_0_BIT), 7666 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7667 CSKY_ISA_VDSP), 7668 OP32 ("vmul.s8", 7669 OPCODE_INFO3 (0xf8000410, 7670 (0_3, VREG, OPRND_SHIFT_0_BIT), 7671 (16_19, VREG, OPRND_SHIFT_0_BIT), 7672 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7673 CSKY_ISA_VDSP), 7674 OP32 ("vmul.s16", 7675 OPCODE_INFO3 (0xf8100410, 7676 (0_3, VREG, OPRND_SHIFT_0_BIT), 7677 (16_19, VREG, OPRND_SHIFT_0_BIT), 7678 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7679 CSKY_ISA_VDSP), 7680 OP32 ("vmul.s32", 7681 OPCODE_INFO3 (0xfa000410, 7682 (0_3, VREG, OPRND_SHIFT_0_BIT), 7683 (16_19, VREG, OPRND_SHIFT_0_BIT), 7684 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7685 CSKY_ISA_VDSP), 7686 OP32 ("vmul.eu8", 7687 OPCODE_INFO3 (0xf8000420, 7688 (0_3, VREG, OPRND_SHIFT_0_BIT), 7689 (16_19, VREG, OPRND_SHIFT_0_BIT), 7690 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7691 CSKY_ISA_VDSP), 7692 OP32 ("vmul.eu16", 7693 OPCODE_INFO3 (0xf8100420, 7694 (0_3, VREG, OPRND_SHIFT_0_BIT), 7695 (16_19, VREG, OPRND_SHIFT_0_BIT), 7696 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7697 CSKY_ISA_VDSP), 7698 OP32 ("vmul.es8", 7699 OPCODE_INFO3 (0xf8000430, 7700 (0_3, VREG, OPRND_SHIFT_0_BIT), 7701 (16_19, VREG, OPRND_SHIFT_0_BIT), 7702 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7703 CSKY_ISA_VDSP), 7704 OP32 ("vmul.es16", 7705 OPCODE_INFO3 (0xf8100430, 7706 (0_3, VREG, OPRND_SHIFT_0_BIT), 7707 (16_19, VREG, OPRND_SHIFT_0_BIT), 7708 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7709 CSKY_ISA_VDSP), 7710 OP32 ("vmula.u8", 7711 OPCODE_INFO3 (0xf8000440, 7712 (0_3, VREG, OPRND_SHIFT_0_BIT), 7713 (16_19, VREG, OPRND_SHIFT_0_BIT), 7714 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7715 CSKY_ISA_VDSP), 7716 OP32 ("vmula.u16", 7717 OPCODE_INFO3 (0xf8100440, 7718 (0_3, VREG, OPRND_SHIFT_0_BIT), 7719 (16_19, VREG, OPRND_SHIFT_0_BIT), 7720 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7721 CSKY_ISA_VDSP), 7722 OP32 ("vmula.u32", 7723 OPCODE_INFO3 (0xfa000440, 7724 (0_3, VREG, OPRND_SHIFT_0_BIT), 7725 (16_19, VREG, OPRND_SHIFT_0_BIT), 7726 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7727 CSKY_ISA_VDSP), 7728 OP32 ("vmula.s8", 7729 OPCODE_INFO3 (0xf8000450, 7730 (0_3, VREG, OPRND_SHIFT_0_BIT), 7731 (16_19, VREG, OPRND_SHIFT_0_BIT), 7732 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7733 CSKY_ISA_VDSP), 7734 OP32 ("vmula.s16", 7735 OPCODE_INFO3 (0xf8100450, 7736 (0_3, VREG, OPRND_SHIFT_0_BIT), 7737 (16_19, VREG, OPRND_SHIFT_0_BIT), 7738 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7739 CSKY_ISA_VDSP), 7740 OP32 ("vmula.s32", 7741 OPCODE_INFO3 (0xfa000450, 7742 (0_3, VREG, OPRND_SHIFT_0_BIT), 7743 (16_19, VREG, OPRND_SHIFT_0_BIT), 7744 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7745 CSKY_ISA_VDSP), 7746 OP32 ("vmula.eu8", 7747 OPCODE_INFO3 (0xf8000460, 7748 (0_3, VREG, OPRND_SHIFT_0_BIT), 7749 (16_19, VREG, OPRND_SHIFT_0_BIT), 7750 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7751 CSKY_ISA_VDSP), 7752 OP32 ("vmula.eu16", 7753 OPCODE_INFO3 (0xf8100460, 7754 (0_3, VREG, OPRND_SHIFT_0_BIT), 7755 (16_19, VREG, OPRND_SHIFT_0_BIT), 7756 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7757 CSKY_ISA_VDSP), 7758 OP32 ("vmula.eu32", 7759 OPCODE_INFO3 (0xfa000460, 7760 (0_3, VREG, OPRND_SHIFT_0_BIT), 7761 (16_19, VREG, OPRND_SHIFT_0_BIT), 7762 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7763 CSKY_ISA_VDSP), 7764 OP32 ("vmula.es8", 7765 OPCODE_INFO3 (0xf8000470, 7766 (0_3, VREG, OPRND_SHIFT_0_BIT), 7767 (16_19, VREG, OPRND_SHIFT_0_BIT), 7768 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7769 CSKY_ISA_VDSP), 7770 OP32 ("vmula.es16", 7771 OPCODE_INFO3 (0xf8100470, 7772 (0_3, VREG, OPRND_SHIFT_0_BIT), 7773 (16_19, VREG, OPRND_SHIFT_0_BIT), 7774 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7775 CSKY_ISA_VDSP), 7776 OP32 ("vmula.es32", 7777 OPCODE_INFO3 (0xfa000470, 7778 (0_3, VREG, OPRND_SHIFT_0_BIT), 7779 (16_19, VREG, OPRND_SHIFT_0_BIT), 7780 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7781 CSKY_ISA_VDSP), 7782 OP32 ("vmuls.u8", 7783 OPCODE_INFO3 (0xf8000480, 7784 (0_3, VREG, OPRND_SHIFT_0_BIT), 7785 (16_19, VREG, OPRND_SHIFT_0_BIT), 7786 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7787 CSKY_ISA_VDSP), 7788 OP32 ("vmuls.u16", 7789 OPCODE_INFO3 (0xf8100480, 7790 (0_3, VREG, OPRND_SHIFT_0_BIT), 7791 (16_19, VREG, OPRND_SHIFT_0_BIT), 7792 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7793 CSKY_ISA_VDSP), 7794 OP32 ("vmuls.u32", 7795 OPCODE_INFO3 (0xfa000480, 7796 (0_3, VREG, OPRND_SHIFT_0_BIT), 7797 (16_19, VREG, OPRND_SHIFT_0_BIT), 7798 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7799 CSKY_ISA_VDSP), 7800 OP32 ("vmuls.s8", 7801 OPCODE_INFO3 (0xf8000490, 7802 (0_3, VREG, OPRND_SHIFT_0_BIT), 7803 (16_19, VREG, OPRND_SHIFT_0_BIT), 7804 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7805 CSKY_ISA_VDSP), 7806 OP32 ("vmuls.s16", 7807 OPCODE_INFO3 (0xf8100490, 7808 (0_3, VREG, OPRND_SHIFT_0_BIT), 7809 (16_19, VREG, OPRND_SHIFT_0_BIT), 7810 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7811 CSKY_ISA_VDSP), 7812 OP32 ("vmuls.s32", 7813 OPCODE_INFO3 (0xfa000490, 7814 (0_3, VREG, OPRND_SHIFT_0_BIT), 7815 (16_19, VREG, OPRND_SHIFT_0_BIT), 7816 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7817 CSKY_ISA_VDSP), 7818 OP32 ("vmuls.eu8", 7819 OPCODE_INFO3 (0xf80004a0, 7820 (0_3, VREG, OPRND_SHIFT_0_BIT), 7821 (16_19, VREG, OPRND_SHIFT_0_BIT), 7822 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7823 CSKY_ISA_VDSP), 7824 OP32 ("vmuls.eu16", 7825 OPCODE_INFO3 (0xf81004a0, 7826 (0_3, VREG, OPRND_SHIFT_0_BIT), 7827 (16_19, VREG, OPRND_SHIFT_0_BIT), 7828 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7829 CSKY_ISA_VDSP), 7830 OP32 ("vmuls.es8", 7831 OPCODE_INFO3 (0xf80004b0, 7832 (0_3, VREG, OPRND_SHIFT_0_BIT), 7833 (16_19, VREG, OPRND_SHIFT_0_BIT), 7834 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7835 CSKY_ISA_VDSP), 7836 OP32 ("vmuls.es16", 7837 OPCODE_INFO3 (0xf81004b0, 7838 (0_3, VREG, OPRND_SHIFT_0_BIT), 7839 (16_19, VREG, OPRND_SHIFT_0_BIT), 7840 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7841 CSKY_ISA_VDSP), 7842 OP32 ("vshr.u8", 7843 OPCODE_INFO3 (0xf8000680, 7844 (0_3, VREG, OPRND_SHIFT_0_BIT), 7845 (16_19, VREG, OPRND_SHIFT_0_BIT), 7846 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7847 CSKY_ISA_VDSP), 7848 OP32 ("vshr.u16", 7849 OPCODE_INFO3 (0xf8100680, 7850 (0_3, VREG, OPRND_SHIFT_0_BIT), 7851 (16_19, VREG, OPRND_SHIFT_0_BIT), 7852 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7853 CSKY_ISA_VDSP), 7854 OP32 ("vshr.u32", 7855 OPCODE_INFO3 (0xfa000680, 7856 (0_3, VREG, OPRND_SHIFT_0_BIT), 7857 (16_19, VREG, OPRND_SHIFT_0_BIT), 7858 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7859 CSKY_ISA_VDSP), 7860 OP32 ("vshr.s8", 7861 OPCODE_INFO3 (0xf8000690, 7862 (0_3, VREG, OPRND_SHIFT_0_BIT), 7863 (16_19, VREG, OPRND_SHIFT_0_BIT), 7864 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7865 CSKY_ISA_VDSP), 7866 OP32 ("vshr.s16", 7867 OPCODE_INFO3 (0xf8100690, 7868 (0_3, VREG, OPRND_SHIFT_0_BIT), 7869 (16_19, VREG, OPRND_SHIFT_0_BIT), 7870 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7871 CSKY_ISA_VDSP), 7872 OP32 ("vshr.s32", 7873 OPCODE_INFO3 (0xfa000690, 7874 (0_3, VREG, OPRND_SHIFT_0_BIT), 7875 (16_19, VREG, OPRND_SHIFT_0_BIT), 7876 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7877 CSKY_ISA_VDSP), 7878 OP32 ("vshr.u8.r", 7879 OPCODE_INFO3 (0xf80006c0, 7880 (0_3, VREG, OPRND_SHIFT_0_BIT), 7881 (16_19, VREG, OPRND_SHIFT_0_BIT), 7882 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7883 CSKY_ISA_VDSP), 7884 OP32 ("vshr.u16.r", 7885 OPCODE_INFO3 (0xf81006c0, 7886 (0_3, VREG, OPRND_SHIFT_0_BIT), 7887 (16_19, VREG, OPRND_SHIFT_0_BIT), 7888 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7889 CSKY_ISA_VDSP), 7890 OP32 ("vshr.u32.r", 7891 OPCODE_INFO3 (0xfa0006c0, 7892 (0_3, VREG, OPRND_SHIFT_0_BIT), 7893 (16_19, VREG, OPRND_SHIFT_0_BIT), 7894 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7895 CSKY_ISA_VDSP), 7896 OP32 ("vshr.s8.r", 7897 OPCODE_INFO3 (0xf80006d0, 7898 (0_3, VREG, OPRND_SHIFT_0_BIT), 7899 (16_19, VREG, OPRND_SHIFT_0_BIT), 7900 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7901 CSKY_ISA_VDSP), 7902 OP32 ("vshr.s16.r", 7903 OPCODE_INFO3 (0xf81006d0, 7904 (0_3, VREG, OPRND_SHIFT_0_BIT), 7905 (16_19, VREG, OPRND_SHIFT_0_BIT), 7906 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7907 CSKY_ISA_VDSP), 7908 OP32 ("vshri.u8", 7909 OPCODE_INFO3 (0xf8000600, 7910 (0_3, VREG, OPRND_SHIFT_0_BIT), 7911 (16_19, VREG, OPRND_SHIFT_0_BIT), 7912 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7913 CSKY_ISA_VDSP), 7914 OP32 ("vshri.u16", 7915 OPCODE_INFO3 (0xf8100600, 7916 (0_3, VREG, OPRND_SHIFT_0_BIT), 7917 (16_19, VREG, OPRND_SHIFT_0_BIT), 7918 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7919 CSKY_ISA_VDSP), 7920 OP32 ("vshri.u32", 7921 OPCODE_INFO3 (0xfa000600, 7922 (0_3, VREG, OPRND_SHIFT_0_BIT), 7923 (16_19, VREG, OPRND_SHIFT_0_BIT), 7924 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7925 CSKY_ISA_VDSP), 7926 OP32 ("vshri.s8", 7927 OPCODE_INFO3 (0xf8000610, 7928 (0_3, VREG, OPRND_SHIFT_0_BIT), 7929 (16_19, VREG, OPRND_SHIFT_0_BIT), 7930 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7931 CSKY_ISA_VDSP), 7932 OP32 ("vshri.s16", 7933 OPCODE_INFO3 (0xf8100610, 7934 (0_3, VREG, OPRND_SHIFT_0_BIT), 7935 (16_19, VREG, OPRND_SHIFT_0_BIT), 7936 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7937 CSKY_ISA_VDSP), 7938 OP32 ("vshri.s32", 7939 OPCODE_INFO3 (0xfa000610, 7940 (0_3, VREG, OPRND_SHIFT_0_BIT), 7941 (16_19, VREG, OPRND_SHIFT_0_BIT), 7942 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7943 CSKY_ISA_VDSP), 7944 OP32 ("vshri.u8.r", 7945 OPCODE_INFO3 (0xf8000640, 7946 (0_3, VREG, OPRND_SHIFT_0_BIT), 7947 (16_19, VREG, OPRND_SHIFT_0_BIT), 7948 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7949 CSKY_ISA_VDSP), 7950 OP32 ("vshri.u16.r", 7951 OPCODE_INFO3 (0xf8100640, 7952 (0_3, VREG, OPRND_SHIFT_0_BIT), 7953 (16_19, VREG, OPRND_SHIFT_0_BIT), 7954 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7955 CSKY_ISA_VDSP), 7956 OP32 ("vshri.u32.r", 7957 OPCODE_INFO3 (0xfa000640, 7958 (0_3, VREG, OPRND_SHIFT_0_BIT), 7959 (16_19, VREG, OPRND_SHIFT_0_BIT), 7960 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7961 CSKY_ISA_VDSP), 7962 OP32 ("vshri.s8.r", 7963 OPCODE_INFO3 (0xf8000650, 7964 (0_3, VREG, OPRND_SHIFT_0_BIT), 7965 (16_19, VREG, OPRND_SHIFT_0_BIT), 7966 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7967 CSKY_ISA_VDSP), 7968 OP32 ("vshri.s16.r", 7969 OPCODE_INFO3 (0xf8100650, 7970 (0_3, VREG, OPRND_SHIFT_0_BIT), 7971 (16_19, VREG, OPRND_SHIFT_0_BIT), 7972 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7973 CSKY_ISA_VDSP), 7974 OP32 ("vshri.s32.r", 7975 OPCODE_INFO3 (0xfa000650, 7976 (0_3, VREG, OPRND_SHIFT_0_BIT), 7977 (16_19, VREG, OPRND_SHIFT_0_BIT), 7978 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 7979 CSKY_ISA_VDSP), 7980 OP32 ("vshr.s32.r", 7981 OPCODE_INFO3 (0xfa0006d0, 7982 (0_3, VREG, OPRND_SHIFT_0_BIT), 7983 (16_19, VREG, OPRND_SHIFT_0_BIT), 7984 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7985 CSKY_ISA_VDSP), 7986 OP32 ("vshr.s32.r", 7987 OPCODE_INFO3 (0xfa0006d0, 7988 (0_3, VREG, OPRND_SHIFT_0_BIT), 7989 (16_19, VREG, OPRND_SHIFT_0_BIT), 7990 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7991 CSKY_ISA_VDSP), 7992 OP32 ("vshl.u8", 7993 OPCODE_INFO3 (0xf8000780, 7994 (0_3, VREG, OPRND_SHIFT_0_BIT), 7995 (16_19, VREG, OPRND_SHIFT_0_BIT), 7996 (21_24, VREG, OPRND_SHIFT_0_BIT)), 7997 CSKY_ISA_VDSP), 7998 OP32 ("vshl.u16", 7999 OPCODE_INFO3 (0xf8100780, 8000 (0_3, VREG, OPRND_SHIFT_0_BIT), 8001 (16_19, VREG, OPRND_SHIFT_0_BIT), 8002 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8003 CSKY_ISA_VDSP), 8004 OP32 ("vshl.u32", 8005 OPCODE_INFO3 (0xfa000780, 8006 (0_3, VREG, OPRND_SHIFT_0_BIT), 8007 (16_19, VREG, OPRND_SHIFT_0_BIT), 8008 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8009 CSKY_ISA_VDSP), 8010 OP32 ("vshl.s8", 8011 OPCODE_INFO3 (0xf8000790, 8012 (0_3, VREG, OPRND_SHIFT_0_BIT), 8013 (16_19, VREG, OPRND_SHIFT_0_BIT), 8014 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8015 CSKY_ISA_VDSP), 8016 OP32 ("vshl.s16", 8017 OPCODE_INFO3 (0xf8100790, 8018 (0_3, VREG, OPRND_SHIFT_0_BIT), 8019 (16_19, VREG, OPRND_SHIFT_0_BIT), 8020 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8021 CSKY_ISA_VDSP), 8022 OP32 ("vshl.s32", 8023 OPCODE_INFO3 (0xfa000790, 8024 (0_3, VREG, OPRND_SHIFT_0_BIT), 8025 (16_19, VREG, OPRND_SHIFT_0_BIT), 8026 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8027 CSKY_ISA_VDSP), 8028 OP32 ("vshl.u8.s", 8029 OPCODE_INFO3 (0xf80007c0, 8030 (0_3, VREG, OPRND_SHIFT_0_BIT), 8031 (16_19, VREG, OPRND_SHIFT_0_BIT), 8032 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8033 CSKY_ISA_VDSP), 8034 OP32 ("vshl.u16.s", 8035 OPCODE_INFO3 (0xf81007c0, 8036 (0_3, VREG, OPRND_SHIFT_0_BIT), 8037 (16_19, VREG, OPRND_SHIFT_0_BIT), 8038 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8039 CSKY_ISA_VDSP), 8040 OP32 ("vshl.u32.s", 8041 OPCODE_INFO3 (0xfa0007c0, 8042 (0_3, VREG, OPRND_SHIFT_0_BIT), 8043 (16_19, VREG, OPRND_SHIFT_0_BIT), 8044 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8045 CSKY_ISA_VDSP), 8046 OP32 ("vshl.s8.s", 8047 OPCODE_INFO3 (0xf80007d0, 8048 (0_3, VREG, OPRND_SHIFT_0_BIT), 8049 (16_19, VREG, OPRND_SHIFT_0_BIT), 8050 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8051 CSKY_ISA_VDSP), 8052 OP32 ("vshl.s16.s", 8053 OPCODE_INFO3 (0xf81007d0, 8054 (0_3, VREG, OPRND_SHIFT_0_BIT), 8055 (16_19, VREG, OPRND_SHIFT_0_BIT), 8056 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8057 CSKY_ISA_VDSP), 8058 OP32 ("vshl.s32.s", 8059 OPCODE_INFO3 (0xfa0007d0, 8060 (0_3, VREG, OPRND_SHIFT_0_BIT), 8061 (16_19, VREG, OPRND_SHIFT_0_BIT), 8062 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8063 CSKY_ISA_VDSP), 8064 OP32 ("vshli.u8", 8065 OPCODE_INFO3 (0xf8000700, 8066 (0_3, VREG, OPRND_SHIFT_0_BIT), 8067 (16_19, VREG, OPRND_SHIFT_0_BIT), 8068 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8069 CSKY_ISA_VDSP), 8070 OP32 ("vshli.u16", 8071 OPCODE_INFO3 (0xf8100700, 8072 (0_3, VREG, OPRND_SHIFT_0_BIT), 8073 (16_19, VREG, OPRND_SHIFT_0_BIT), 8074 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8075 CSKY_ISA_VDSP), 8076 OP32 ("vshli.u32", 8077 OPCODE_INFO3 (0xfa000700, 8078 (0_3, VREG, OPRND_SHIFT_0_BIT), 8079 (16_19, VREG, OPRND_SHIFT_0_BIT), 8080 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8081 CSKY_ISA_VDSP), 8082 OP32 ("vshli.s8", 8083 OPCODE_INFO3 (0xf8000710, 8084 (0_3, VREG, OPRND_SHIFT_0_BIT), 8085 (16_19, VREG, OPRND_SHIFT_0_BIT), 8086 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8087 CSKY_ISA_VDSP), 8088 OP32 ("vshli.s16", 8089 OPCODE_INFO3 (0xf8100710, 8090 (0_3, VREG, OPRND_SHIFT_0_BIT), 8091 (16_19, VREG, OPRND_SHIFT_0_BIT), 8092 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8093 CSKY_ISA_VDSP), 8094 OP32 ("vshli.s32", 8095 OPCODE_INFO3 (0xfa000710, 8096 (0_3, VREG, OPRND_SHIFT_0_BIT), 8097 (16_19, VREG, OPRND_SHIFT_0_BIT), 8098 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8099 CSKY_ISA_VDSP), 8100 OP32 ("vshli.u8.s", 8101 OPCODE_INFO3 (0xf8000740, 8102 (0_3, VREG, OPRND_SHIFT_0_BIT), 8103 (16_19, VREG, OPRND_SHIFT_0_BIT), 8104 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8105 CSKY_ISA_VDSP), 8106 OP32 ("vshli.u16.s", 8107 OPCODE_INFO3 (0xf8100740, 8108 (0_3, VREG, OPRND_SHIFT_0_BIT), 8109 (16_19, VREG, OPRND_SHIFT_0_BIT), 8110 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8111 CSKY_ISA_VDSP), 8112 OP32 ("vshli.u32.s", 8113 OPCODE_INFO3 (0xfa000740, 8114 (0_3, VREG, OPRND_SHIFT_0_BIT), 8115 (16_19, VREG, OPRND_SHIFT_0_BIT), 8116 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8117 CSKY_ISA_VDSP), 8118 OP32 ("vshli.s8.s", 8119 OPCODE_INFO3 (0xf8000750, 8120 (0_3, VREG, OPRND_SHIFT_0_BIT), 8121 (16_19, VREG, OPRND_SHIFT_0_BIT), 8122 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8123 CSKY_ISA_VDSP), 8124 OP32 ("vshli.s16.s", 8125 OPCODE_INFO3 (0xf8100750, 8126 (0_3, VREG, OPRND_SHIFT_0_BIT), 8127 (16_19, VREG, OPRND_SHIFT_0_BIT), 8128 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8129 CSKY_ISA_VDSP), 8130 OP32 ("vshli.s32.s", 8131 OPCODE_INFO3 (0xfa000750, 8132 (0_3, VREG, OPRND_SHIFT_0_BIT), 8133 (16_19, VREG, OPRND_SHIFT_0_BIT), 8134 (5or21_24, IMM5b_VSH, OPRND_SHIFT_0_BIT)), 8135 CSKY_ISA_VDSP), 8136 OP32 ("vcmphs.u8", 8137 OPCODE_INFO3 (0xf8000800, 8138 (0_3, VREG, OPRND_SHIFT_0_BIT), 8139 (16_19, VREG, OPRND_SHIFT_0_BIT), 8140 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8141 CSKY_ISA_VDSP), 8142 OP32 ("vcmphs.u16", 8143 OPCODE_INFO3 (0xf8100800, 8144 (0_3, VREG, OPRND_SHIFT_0_BIT), 8145 (16_19, VREG, OPRND_SHIFT_0_BIT), 8146 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8147 CSKY_ISA_VDSP), 8148 OP32 ("vcmphs.u32", 8149 OPCODE_INFO3 (0xfa000800, 8150 (0_3, VREG, OPRND_SHIFT_0_BIT), 8151 (16_19, VREG, OPRND_SHIFT_0_BIT), 8152 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8153 CSKY_ISA_VDSP), 8154 OP32 ("vcmphs.s8", 8155 OPCODE_INFO3 (0xf8000810, 8156 (0_3, VREG, OPRND_SHIFT_0_BIT), 8157 (16_19, VREG, OPRND_SHIFT_0_BIT), 8158 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8159 CSKY_ISA_VDSP), 8160 OP32 ("vcmphs.s16", 8161 OPCODE_INFO3 (0xf8100810, 8162 (0_3, VREG, OPRND_SHIFT_0_BIT), 8163 (16_19, VREG, OPRND_SHIFT_0_BIT), 8164 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8165 CSKY_ISA_VDSP), 8166 OP32 ("vcmphs.s32", 8167 OPCODE_INFO3 (0xfa000810, 8168 (0_3, VREG, OPRND_SHIFT_0_BIT), 8169 (16_19, VREG, OPRND_SHIFT_0_BIT), 8170 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8171 CSKY_ISA_VDSP), 8172 OP32 ("vcmplt.u8", 8173 OPCODE_INFO3 (0xf8000820, 8174 (0_3, VREG, OPRND_SHIFT_0_BIT), 8175 (16_19, VREG, OPRND_SHIFT_0_BIT), 8176 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8177 CSKY_ISA_VDSP), 8178 OP32 ("vcmplt.u16", 8179 OPCODE_INFO3 (0xf8100820, 8180 (0_3, VREG, OPRND_SHIFT_0_BIT), 8181 (16_19, VREG, OPRND_SHIFT_0_BIT), 8182 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8183 CSKY_ISA_VDSP), 8184 OP32 ("vcmplt.u32", 8185 OPCODE_INFO3 (0xfa000820, 8186 (0_3, VREG, OPRND_SHIFT_0_BIT), 8187 (16_19, VREG, OPRND_SHIFT_0_BIT), 8188 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8189 CSKY_ISA_VDSP), 8190 OP32 ("vcmplt.s8", 8191 OPCODE_INFO3 (0xf8000830, 8192 (0_3, VREG, OPRND_SHIFT_0_BIT), 8193 (16_19, VREG, OPRND_SHIFT_0_BIT), 8194 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8195 CSKY_ISA_VDSP), 8196 OP32 ("vcmplt.s16", 8197 OPCODE_INFO3 (0xf8100830, 8198 (0_3, VREG, OPRND_SHIFT_0_BIT), 8199 (16_19, VREG, OPRND_SHIFT_0_BIT), 8200 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8201 CSKY_ISA_VDSP), 8202 OP32 ("vcmplt.s32", 8203 OPCODE_INFO3 (0xfa000830, 8204 (0_3, VREG, OPRND_SHIFT_0_BIT), 8205 (16_19, VREG, OPRND_SHIFT_0_BIT), 8206 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8207 CSKY_ISA_VDSP), 8208 OP32 ("vcmpne.u8", 8209 OPCODE_INFO3 (0xf8000840, 8210 (0_3, VREG, OPRND_SHIFT_0_BIT), 8211 (16_19, VREG, OPRND_SHIFT_0_BIT), 8212 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8213 CSKY_ISA_VDSP), 8214 OP32 ("vcmpne.u16", 8215 OPCODE_INFO3 (0xf8100840, 8216 (0_3, VREG, OPRND_SHIFT_0_BIT), 8217 (16_19, VREG, OPRND_SHIFT_0_BIT), 8218 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8219 CSKY_ISA_VDSP), 8220 OP32 ("vcmpne.u32", 8221 OPCODE_INFO3 (0xfa000840, 8222 (0_3, VREG, OPRND_SHIFT_0_BIT), 8223 (16_19, VREG, OPRND_SHIFT_0_BIT), 8224 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8225 CSKY_ISA_VDSP), 8226 OP32 ("vcmpne.s8", 8227 OPCODE_INFO3 (0xf8000850, 8228 (0_3, VREG, OPRND_SHIFT_0_BIT), 8229 (16_19, VREG, OPRND_SHIFT_0_BIT), 8230 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8231 CSKY_ISA_VDSP), 8232 OP32 ("vcmpne.s16", 8233 OPCODE_INFO3 (0xf8100850, 8234 (0_3, VREG, OPRND_SHIFT_0_BIT), 8235 (16_19, VREG, OPRND_SHIFT_0_BIT), 8236 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8237 CSKY_ISA_VDSP), 8238 OP32 ("vcmpne.s32", 8239 OPCODE_INFO3 (0xfa000850, 8240 (0_3, VREG, OPRND_SHIFT_0_BIT), 8241 (16_19, VREG, OPRND_SHIFT_0_BIT), 8242 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8243 CSKY_ISA_VDSP), 8244 OP32 ("vmax.u8", 8245 OPCODE_INFO3 (0xf8000900, 8246 (0_3, VREG, OPRND_SHIFT_0_BIT), 8247 (16_19, VREG, OPRND_SHIFT_0_BIT), 8248 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8249 CSKY_ISA_VDSP), 8250 OP32 ("vmax.u16", 8251 OPCODE_INFO3 (0xf8100900, 8252 (0_3, VREG, OPRND_SHIFT_0_BIT), 8253 (16_19, VREG, OPRND_SHIFT_0_BIT), 8254 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8255 CSKY_ISA_VDSP), 8256 OP32 ("vmax.u32", 8257 OPCODE_INFO3 (0xfa000900, 8258 (0_3, VREG, OPRND_SHIFT_0_BIT), 8259 (16_19, VREG, OPRND_SHIFT_0_BIT), 8260 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8261 CSKY_ISA_VDSP), 8262 OP32 ("vmax.s8", 8263 OPCODE_INFO3 (0xf8000910, 8264 (0_3, VREG, OPRND_SHIFT_0_BIT), 8265 (16_19, VREG, OPRND_SHIFT_0_BIT), 8266 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8267 CSKY_ISA_VDSP), 8268 OP32 ("vmax.s16", 8269 OPCODE_INFO3 (0xf8100910, 8270 (0_3, VREG, OPRND_SHIFT_0_BIT), 8271 (16_19, VREG, OPRND_SHIFT_0_BIT), 8272 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8273 CSKY_ISA_VDSP), 8274 OP32 ("vmax.s32", 8275 OPCODE_INFO3 (0xfa000910, 8276 (0_3, VREG, OPRND_SHIFT_0_BIT), 8277 (16_19, VREG, OPRND_SHIFT_0_BIT), 8278 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8279 CSKY_ISA_VDSP), 8280 OP32 ("vmin.u8", 8281 OPCODE_INFO3 (0xf8000920, 8282 (0_3, VREG, OPRND_SHIFT_0_BIT), 8283 (16_19, VREG, OPRND_SHIFT_0_BIT), 8284 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8285 CSKY_ISA_VDSP), 8286 OP32 ("vmin.u16", 8287 OPCODE_INFO3 (0xf8100920, 8288 (0_3, VREG, OPRND_SHIFT_0_BIT), 8289 (16_19, VREG, OPRND_SHIFT_0_BIT), 8290 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8291 CSKY_ISA_VDSP), 8292 OP32 ("vmin.u32", 8293 OPCODE_INFO3 (0xfa000920, 8294 (0_3, VREG, OPRND_SHIFT_0_BIT), 8295 (16_19, VREG, OPRND_SHIFT_0_BIT), 8296 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8297 CSKY_ISA_VDSP), 8298 OP32 ("vmin.s8", 8299 OPCODE_INFO3 (0xf8000930, 8300 (0_3, VREG, OPRND_SHIFT_0_BIT), 8301 (16_19, VREG, OPRND_SHIFT_0_BIT), 8302 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8303 CSKY_ISA_VDSP), 8304 OP32 ("vmin.s16", 8305 OPCODE_INFO3 (0xf8100930, 8306 (0_3, VREG, OPRND_SHIFT_0_BIT), 8307 (16_19, VREG, OPRND_SHIFT_0_BIT), 8308 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8309 CSKY_ISA_VDSP), 8310 OP32 ("vmin.s32", 8311 OPCODE_INFO3 (0xfa000930, 8312 (0_3, VREG, OPRND_SHIFT_0_BIT), 8313 (16_19, VREG, OPRND_SHIFT_0_BIT), 8314 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8315 CSKY_ISA_VDSP), 8316 OP32 ("vcmax.u8", 8317 OPCODE_INFO3 (0xf8000980, 8318 (0_3, VREG, OPRND_SHIFT_0_BIT), 8319 (16_19, VREG, OPRND_SHIFT_0_BIT), 8320 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8321 CSKY_ISA_VDSP), 8322 OP32 ("vcmax.u16", 8323 OPCODE_INFO3 (0xf8100980, 8324 (0_3, VREG, OPRND_SHIFT_0_BIT), 8325 (16_19, VREG, OPRND_SHIFT_0_BIT), 8326 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8327 CSKY_ISA_VDSP), 8328 OP32 ("vcmax.u32", 8329 OPCODE_INFO3 (0xfa000980, 8330 (0_3, VREG, OPRND_SHIFT_0_BIT), 8331 (16_19, VREG, OPRND_SHIFT_0_BIT), 8332 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8333 CSKY_ISA_VDSP), 8334 OP32 ("vcmax.s8", 8335 OPCODE_INFO3 (0xf8000990, 8336 (0_3, VREG, OPRND_SHIFT_0_BIT), 8337 (16_19, VREG, OPRND_SHIFT_0_BIT), 8338 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8339 CSKY_ISA_VDSP), 8340 OP32 ("vcmax.s16", 8341 OPCODE_INFO3 (0xf8100990, 8342 (0_3, VREG, OPRND_SHIFT_0_BIT), 8343 (16_19, VREG, OPRND_SHIFT_0_BIT), 8344 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8345 CSKY_ISA_VDSP), 8346 OP32 ("vcmax.s32", 8347 OPCODE_INFO3 (0xfa000990, 8348 (0_3, VREG, OPRND_SHIFT_0_BIT), 8349 (16_19, VREG, OPRND_SHIFT_0_BIT), 8350 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8351 CSKY_ISA_VDSP), 8352 OP32 ("vcmin.u8", 8353 OPCODE_INFO3 (0xf80009a0, 8354 (0_3, VREG, OPRND_SHIFT_0_BIT), 8355 (16_19, VREG, OPRND_SHIFT_0_BIT), 8356 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8357 CSKY_ISA_VDSP), 8358 OP32 ("vcmin.u16", 8359 OPCODE_INFO3 (0xf81009a0, 8360 (0_3, VREG, OPRND_SHIFT_0_BIT), 8361 (16_19, VREG, OPRND_SHIFT_0_BIT), 8362 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8363 CSKY_ISA_VDSP), 8364 OP32 ("vcmin.u32", 8365 OPCODE_INFO3 (0xfa0009a0, 8366 (0_3, VREG, OPRND_SHIFT_0_BIT), 8367 (16_19, VREG, OPRND_SHIFT_0_BIT), 8368 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8369 CSKY_ISA_VDSP), 8370 OP32 ("vcmin.s8", 8371 OPCODE_INFO3 (0xf80009b0, 8372 (0_3, VREG, OPRND_SHIFT_0_BIT), 8373 (16_19, VREG, OPRND_SHIFT_0_BIT), 8374 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8375 CSKY_ISA_VDSP), 8376 OP32 ("vcmin.s16", 8377 OPCODE_INFO3 (0xf81009b0, 8378 (0_3, VREG, OPRND_SHIFT_0_BIT), 8379 (16_19, VREG, OPRND_SHIFT_0_BIT), 8380 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8381 CSKY_ISA_VDSP), 8382 OP32 ("vcmin.s32", 8383 OPCODE_INFO3 (0xfa0009b0, 8384 (0_3, VREG, OPRND_SHIFT_0_BIT), 8385 (16_19, VREG, OPRND_SHIFT_0_BIT), 8386 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8387 CSKY_ISA_VDSP), 8388 OP32 ("vand.8", 8389 OPCODE_INFO3 (0xf8000a00, 8390 (0_3, VREG, OPRND_SHIFT_0_BIT), 8391 (16_19, VREG, OPRND_SHIFT_0_BIT), 8392 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8393 CSKY_ISA_VDSP), 8394 OP32 ("vand.16", 8395 OPCODE_INFO3 (0xf8100a00, 8396 (0_3, VREG, OPRND_SHIFT_0_BIT), 8397 (16_19, VREG, OPRND_SHIFT_0_BIT), 8398 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8399 CSKY_ISA_VDSP), 8400 OP32 ("vand.32", 8401 OPCODE_INFO3 (0xfa000a00, 8402 (0_3, VREG, OPRND_SHIFT_0_BIT), 8403 (16_19, VREG, OPRND_SHIFT_0_BIT), 8404 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8405 CSKY_ISA_VDSP), 8406 OP32 ("vandn.8", 8407 OPCODE_INFO3 (0xf8000a20, 8408 (0_3, VREG, OPRND_SHIFT_0_BIT), 8409 (16_19, VREG, OPRND_SHIFT_0_BIT), 8410 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8411 CSKY_ISA_VDSP), 8412 OP32 ("vandn.16", 8413 OPCODE_INFO3 (0xf8100a20, 8414 (0_3, VREG, OPRND_SHIFT_0_BIT), 8415 (16_19, VREG, OPRND_SHIFT_0_BIT), 8416 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8417 CSKY_ISA_VDSP), 8418 OP32 ("vandn.32", 8419 OPCODE_INFO3 (0xfa000a20, 8420 (0_3, VREG, OPRND_SHIFT_0_BIT), 8421 (16_19, VREG, OPRND_SHIFT_0_BIT), 8422 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8423 CSKY_ISA_VDSP), 8424 OP32 ("vor.8", 8425 OPCODE_INFO3 (0xf8000a40, 8426 (0_3, VREG, OPRND_SHIFT_0_BIT), 8427 (16_19, VREG, OPRND_SHIFT_0_BIT), 8428 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8429 CSKY_ISA_VDSP), 8430 OP32 ("vor.16", 8431 OPCODE_INFO3 (0xf8100a40, 8432 (0_3, VREG, OPRND_SHIFT_0_BIT), 8433 (16_19, VREG, OPRND_SHIFT_0_BIT), 8434 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8435 CSKY_ISA_VDSP), 8436 OP32 ("vor.32", 8437 OPCODE_INFO3 (0xfa000a40, 8438 (0_3, VREG, OPRND_SHIFT_0_BIT), 8439 (16_19, VREG, OPRND_SHIFT_0_BIT), 8440 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8441 CSKY_ISA_VDSP), 8442 OP32 ("vnor.8", 8443 OPCODE_INFO3 (0xf8000a60, 8444 (0_3, VREG, OPRND_SHIFT_0_BIT), 8445 (16_19, VREG, OPRND_SHIFT_0_BIT), 8446 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8447 CSKY_ISA_VDSP), 8448 OP32 ("vnor.16", 8449 OPCODE_INFO3 (0xf8100a60, 8450 (0_3, VREG, OPRND_SHIFT_0_BIT), 8451 (16_19, VREG, OPRND_SHIFT_0_BIT), 8452 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8453 CSKY_ISA_VDSP), 8454 OP32 ("vnor.32", 8455 OPCODE_INFO3 (0xfa000a60, 8456 (0_3, VREG, OPRND_SHIFT_0_BIT), 8457 (16_19, VREG, OPRND_SHIFT_0_BIT), 8458 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8459 CSKY_ISA_VDSP), 8460 OP32 ("vxor.8", 8461 OPCODE_INFO3 (0xf8000a80, 8462 (0_3, VREG, OPRND_SHIFT_0_BIT), 8463 (16_19, VREG, OPRND_SHIFT_0_BIT), 8464 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8465 CSKY_ISA_VDSP), 8466 OP32 ("vxor.16", 8467 OPCODE_INFO3 (0xf8100a80, 8468 (0_3, VREG, OPRND_SHIFT_0_BIT), 8469 (16_19, VREG, OPRND_SHIFT_0_BIT), 8470 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8471 CSKY_ISA_VDSP), 8472 OP32 ("vxor.32", 8473 OPCODE_INFO3 (0xfa000a80, 8474 (0_3, VREG, OPRND_SHIFT_0_BIT), 8475 (16_19, VREG, OPRND_SHIFT_0_BIT), 8476 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8477 CSKY_ISA_VDSP), 8478 OP32 ("vtst.8", 8479 OPCODE_INFO3 (0xf8000b20, 8480 (0_3, VREG, OPRND_SHIFT_0_BIT), 8481 (16_19, VREG, OPRND_SHIFT_0_BIT), 8482 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8483 CSKY_ISA_VDSP), 8484 OP32 ("vtst.16", 8485 OPCODE_INFO3 (0xf8100b20, 8486 (0_3, VREG, OPRND_SHIFT_0_BIT), 8487 (16_19, VREG, OPRND_SHIFT_0_BIT), 8488 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8489 CSKY_ISA_VDSP), 8490 OP32 ("vtst.32", 8491 OPCODE_INFO3 (0xfa000b20, 8492 (0_3, VREG, OPRND_SHIFT_0_BIT), 8493 (16_19, VREG, OPRND_SHIFT_0_BIT), 8494 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8495 CSKY_ISA_VDSP), 8496 OP32 ("vbpermz.8", 8497 OPCODE_INFO3 (0xf8000f00, 8498 (0_3, VREG, OPRND_SHIFT_0_BIT), 8499 (16_19, VREG, OPRND_SHIFT_0_BIT), 8500 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8501 CSKY_ISA_VDSP), 8502 OP32 ("vbpermz.16", 8503 OPCODE_INFO3 (0xf8100f00, 8504 (0_3, VREG, OPRND_SHIFT_0_BIT), 8505 (16_19, VREG, OPRND_SHIFT_0_BIT), 8506 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8507 CSKY_ISA_VDSP), 8508 OP32 ("vbpermz.32", 8509 OPCODE_INFO3 (0xfa000f00, 8510 (0_3, VREG, OPRND_SHIFT_0_BIT), 8511 (16_19, VREG, OPRND_SHIFT_0_BIT), 8512 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8513 CSKY_ISA_VDSP), 8514 OP32 ("vbperm.8", 8515 OPCODE_INFO3 (0xf8000f20, 8516 (0_3, VREG, OPRND_SHIFT_0_BIT), 8517 (16_19, VREG, OPRND_SHIFT_0_BIT), 8518 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8519 CSKY_ISA_VDSP), 8520 OP32 ("vbperm.16", 8521 OPCODE_INFO3 (0xf8100f20, 8522 (0_3, VREG, OPRND_SHIFT_0_BIT), 8523 (16_19, VREG, OPRND_SHIFT_0_BIT), 8524 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8525 CSKY_ISA_VDSP), 8526 OP32 ("vbperm.32", 8527 OPCODE_INFO3 (0xfa000f20, 8528 (0_3, VREG, OPRND_SHIFT_0_BIT), 8529 (16_19, VREG, OPRND_SHIFT_0_BIT), 8530 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8531 CSKY_ISA_VDSP), 8532 OP32 ("vdch.8", 8533 OPCODE_INFO3 (0xf8000fc0, 8534 (0_3, VREG, OPRND_SHIFT_0_BIT), 8535 (16_19, VREG, OPRND_SHIFT_0_BIT), 8536 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8537 CSKY_ISA_VDSP), 8538 OP32 ("vdch.16", 8539 OPCODE_INFO3 (0xf8100fc0, 8540 (0_3, VREG, OPRND_SHIFT_0_BIT), 8541 (16_19, VREG, OPRND_SHIFT_0_BIT), 8542 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8543 CSKY_ISA_VDSP), 8544 OP32 ("vdch.32", 8545 OPCODE_INFO3 (0xfa000fc0, 8546 (0_3, VREG, OPRND_SHIFT_0_BIT), 8547 (16_19, VREG, OPRND_SHIFT_0_BIT), 8548 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8549 CSKY_ISA_VDSP), 8550 OP32 ("vdcl.8", 8551 OPCODE_INFO3 (0xf8000fe0, 8552 (0_3, VREG, OPRND_SHIFT_0_BIT), 8553 (16_19, VREG, OPRND_SHIFT_0_BIT), 8554 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8555 CSKY_ISA_VDSP), 8556 OP32 ("vdcl.16", 8557 OPCODE_INFO3 (0xf8100fe0, 8558 (0_3, VREG, OPRND_SHIFT_0_BIT), 8559 (16_19, VREG, OPRND_SHIFT_0_BIT), 8560 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8561 CSKY_ISA_VDSP), 8562 OP32 ("vdcl.32", 8563 OPCODE_INFO3 (0xfa000fe0, 8564 (0_3, VREG, OPRND_SHIFT_0_BIT), 8565 (16_19, VREG, OPRND_SHIFT_0_BIT), 8566 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8567 CSKY_ISA_VDSP), 8568 OP32 ("vich.8", 8569 OPCODE_INFO3 (0xf8000f80, 8570 (0_3, VREG, OPRND_SHIFT_0_BIT), 8571 (16_19, VREG, OPRND_SHIFT_0_BIT), 8572 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8573 CSKY_ISA_VDSP), 8574 OP32 ("vich.16", 8575 OPCODE_INFO3 (0xf8100f80, 8576 (0_3, VREG, OPRND_SHIFT_0_BIT), 8577 (16_19, VREG, OPRND_SHIFT_0_BIT), 8578 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8579 CSKY_ISA_VDSP), 8580 OP32 ("vich.32", 8581 OPCODE_INFO3 (0xfa000f80, 8582 (0_3, VREG, OPRND_SHIFT_0_BIT), 8583 (16_19, VREG, OPRND_SHIFT_0_BIT), 8584 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8585 CSKY_ISA_VDSP), 8586 OP32 ("vicl.8", 8587 OPCODE_INFO3 (0xf8000fa0, 8588 (0_3, VREG, OPRND_SHIFT_0_BIT), 8589 (16_19, VREG, OPRND_SHIFT_0_BIT), 8590 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8591 CSKY_ISA_VDSP), 8592 OP32 ("vicl.16", 8593 OPCODE_INFO3 (0xf8100fa0, 8594 (0_3, VREG, OPRND_SHIFT_0_BIT), 8595 (16_19, VREG, OPRND_SHIFT_0_BIT), 8596 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8597 CSKY_ISA_VDSP), 8598 OP32 ("vicl.32", 8599 OPCODE_INFO3 (0xfa000fa0, 8600 (0_3, VREG, OPRND_SHIFT_0_BIT), 8601 (16_19, VREG, OPRND_SHIFT_0_BIT), 8602 (21_24, VREG, OPRND_SHIFT_0_BIT)), 8603 CSKY_ISA_VDSP), 8604 8605 #define OPRND_SHIFT0(mask, type) (mask, type, OPRND_SHIFT_0_BIT) 8606 #define OPRND_SHIFT1(mask, type) (mask, type, OPRND_SHIFT_1_BIT) 8607 #define OPRND_SHIFT2(mask, type) (mask, type, OPRND_SHIFT_2_BIT) 8608 #define OPRND_SHIFT3(mask, type) (mask, type, OPRND_SHIFT_3_BIT) 8609 #define OPRND_SHIFT4(mask, type) (mask, type, OPRND_SHIFT_4_BIT) 8610 8611 /* The followings are 860 floating instructions. */ 8612 OP32 ("fadd.16", 8613 OPCODE_INFO3 (0xf400c800, 8614 OPRND_SHIFT0 (0_4, FREG), 8615 OPRND_SHIFT0 (16_20, FREG), 8616 OPRND_SHIFT0 (21_25, FREG)), 8617 CSKY_ISA_FLOAT_7E60), 8618 OP32 ("faddh", 8619 OPCODE_INFO3 (0xf400c800, 8620 OPRND_SHIFT0 (0_4, FREG), 8621 OPRND_SHIFT0 (16_20, FREG), 8622 OPRND_SHIFT0 (21_25, FREG)), 8623 CSKY_ISA_FLOAT_7E60), 8624 OP32 ("fsub.16", 8625 OPCODE_INFO3 (0xf400c820, 8626 OPRND_SHIFT0 (0_4, FREG), 8627 OPRND_SHIFT0 (16_20, FREG), 8628 OPRND_SHIFT0 (21_25, FREG)), 8629 CSKY_ISA_FLOAT_7E60), 8630 OP32 ("fsubh", 8631 OPCODE_INFO3 (0xf400c820, 8632 OPRND_SHIFT0 (0_4, FREG), 8633 OPRND_SHIFT0 (16_20, FREG), 8634 OPRND_SHIFT0 (21_25, FREG)), 8635 CSKY_ISA_FLOAT_7E60), 8636 OP32 ("fmov.16", 8637 OPCODE_INFO2 (0xf400c880, 8638 OPRND_SHIFT0 (0_4, FREG), 8639 OPRND_SHIFT0 (16_20, FREG)), 8640 CSKY_ISA_FLOAT_7E60), 8641 OP32 ("fmovh", 8642 OPCODE_INFO2 (0xf400c880, 8643 OPRND_SHIFT0 (0_4, FREG), 8644 OPRND_SHIFT0 (16_20, FREG)), 8645 CSKY_ISA_FLOAT_7E60), 8646 OP32 ("fabs.16", 8647 OPCODE_INFO2 (0xf400c8c0, 8648 OPRND_SHIFT0 (0_4, FREG), 8649 OPRND_SHIFT0 (16_20, FREG)), 8650 CSKY_ISA_FLOAT_7E60), 8651 OP32 ("fabsh", 8652 OPCODE_INFO2 (0xf400c8c0, 8653 OPRND_SHIFT0 (0_4, FREG), 8654 OPRND_SHIFT0 (16_20, FREG)), 8655 CSKY_ISA_FLOAT_7E60), 8656 OP32 ("fneg.16", 8657 OPCODE_INFO2 (0xf400c8e0, 8658 OPRND_SHIFT0 (0_4, FREG), 8659 OPRND_SHIFT0 (16_20, FREG)), 8660 CSKY_ISA_FLOAT_7E60), 8661 OP32 ("fnegh", 8662 OPCODE_INFO2 (0xf400c8e0, 8663 OPRND_SHIFT0 (0_4, FREG), 8664 OPRND_SHIFT0 (16_20, FREG)), 8665 CSKY_ISA_FLOAT_7E60), 8666 OP32 ("fcmphsz.16", 8667 OPCODE_INFO1 (0xf400c900, 8668 OPRND_SHIFT0 (16_20, FREG)), 8669 CSKY_ISA_FLOAT_7E60), 8670 OP32 ("fcmpzhsh", 8671 OPCODE_INFO1 (0xf400c900, 8672 OPRND_SHIFT0 (16_20, FREG)), 8673 CSKY_ISA_FLOAT_7E60), 8674 OP32 ("fcmpltz.16", 8675 OPCODE_INFO1 (0xf400c920, 8676 OPRND_SHIFT0 (16_20, FREG)), 8677 CSKY_ISA_FLOAT_7E60), 8678 OP32 ("fcmpzlth", 8679 OPCODE_INFO1 (0xf400c920, 8680 OPRND_SHIFT0 (16_20, FREG)), 8681 CSKY_ISA_FLOAT_7E60), 8682 OP32 ("fcmpnez.16", 8683 OPCODE_INFO1 (0xf400c940, 8684 OPRND_SHIFT0 (16_20, FREG)), 8685 CSKY_ISA_FLOAT_7E60), 8686 OP32 ("fcmpzneh", 8687 OPCODE_INFO1 (0xf400c940, 8688 OPRND_SHIFT0 (16_20, FREG)), 8689 CSKY_ISA_FLOAT_7E60), 8690 OP32 ("fcmpuoz.16", 8691 OPCODE_INFO1 (0xf400c960, 8692 OPRND_SHIFT0 (16_20, FREG)), 8693 CSKY_ISA_FLOAT_7E60), 8694 OP32 ("fcmpzuoh", 8695 OPCODE_INFO1 (0xf400c960, 8696 OPRND_SHIFT0 (16_20, FREG)), 8697 CSKY_ISA_FLOAT_7E60), 8698 OP32 ("fcmphs.16", 8699 OPCODE_INFO2 (0xf400c980, 8700 OPRND_SHIFT0 (16_20, FREG), 8701 OPRND_SHIFT0 (21_25, FREG)), 8702 CSKY_ISA_FLOAT_7E60), 8703 OP32 ("fcmphsh", 8704 OPCODE_INFO2 (0xf400c980, 8705 OPRND_SHIFT0 (16_20, FREG), 8706 OPRND_SHIFT0 (21_25, FREG)), 8707 CSKY_ISA_FLOAT_7E60), 8708 OP32 ("fcmplt.16", 8709 OPCODE_INFO2 (0xf400c9a0, 8710 OPRND_SHIFT0 (16_20, FREG), 8711 OPRND_SHIFT0 (21_25, FREG)), 8712 CSKY_ISA_FLOAT_7E60), 8713 OP32 ("fcmpne.16", 8714 OPCODE_INFO2 (0xf400c9c0, 8715 OPRND_SHIFT0 (16_20, FREG), 8716 OPRND_SHIFT0 (21_25, FREG)), 8717 CSKY_ISA_FLOAT_7E60), 8718 OP32 ("fcmpneh", 8719 OPCODE_INFO2 (0xf400c9c0, 8720 OPRND_SHIFT0 (16_20, FREG), 8721 OPRND_SHIFT0 (21_25, FREG)), 8722 CSKY_ISA_FLOAT_7E60), 8723 OP32 ("fcmpuo.16", 8724 OPCODE_INFO2 (0xf400c9e0, 8725 OPRND_SHIFT0 (16_20, FREG), 8726 OPRND_SHIFT0 (21_25, FREG)), 8727 CSKY_ISA_FLOAT_7E60), 8728 OP32 ("fcmpuoh", 8729 OPCODE_INFO2 (0xf400c9e0, 8730 OPRND_SHIFT0 (16_20, FREG), 8731 OPRND_SHIFT0 (21_25, FREG)), 8732 CSKY_ISA_FLOAT_7E60), 8733 OP32 ("fmaxnm.16", 8734 OPCODE_INFO3 (0xf400cd00, 8735 OPRND_SHIFT0 (0_4, FREG), 8736 OPRND_SHIFT0 (16_20, FREG), 8737 OPRND_SHIFT0 (21_25, FREG)), 8738 CSKY_ISA_FLOAT_7E60), 8739 OP32 ("fminnm.16", 8740 OPCODE_INFO3 (0xf400cd20, 8741 OPRND_SHIFT0 (0_4, FREG), 8742 OPRND_SHIFT0 (16_20, FREG), 8743 OPRND_SHIFT0 (21_25, FREG)), 8744 CSKY_ISA_FLOAT_7E60), 8745 OP32 ("fcmphz.16", 8746 OPCODE_INFO1 (0xf400cd40, 8747 OPRND_SHIFT0 (16_20, FREG)), 8748 CSKY_ISA_FLOAT_7E60), 8749 OP32 ("fcmplsz.16", 8750 OPCODE_INFO1 (0xf400cd60, 8751 OPRND_SHIFT0 (16_20, FREG)), 8752 CSKY_ISA_FLOAT_7E60), 8753 OP32 ("fmul.16", 8754 OPCODE_INFO3 (0xf400ca00, 8755 OPRND_SHIFT0 (0_4, FREG), 8756 OPRND_SHIFT0 (16_20, FREG), 8757 OPRND_SHIFT0 (21_25, FREG)), 8758 CSKY_ISA_FLOAT_7E60), 8759 OP32 ("fmulh", 8760 OPCODE_INFO3 (0xf400ca00, 8761 OPRND_SHIFT0 (0_4, FREG), 8762 OPRND_SHIFT0 (16_20, FREG), 8763 OPRND_SHIFT0 (21_25, FREG)), 8764 CSKY_ISA_FLOAT_7E60), 8765 OP32 ("fnmul.16", 8766 OPCODE_INFO3 (0xf400ca20, 8767 OPRND_SHIFT0 (0_4, FREG), 8768 OPRND_SHIFT0 (16_20, FREG), 8769 OPRND_SHIFT0 (21_25, FREG)), 8770 CSKY_ISA_FLOAT_7E60), 8771 OP32 ("fnmulh", 8772 OPCODE_INFO3 (0xf400ca20, 8773 OPRND_SHIFT0 (0_4, FREG), 8774 OPRND_SHIFT0 (16_20, FREG), 8775 OPRND_SHIFT0 (21_25, FREG)), 8776 CSKY_ISA_FLOAT_7E60), 8777 OP32 ("fmula.16", 8778 OPCODE_INFO3 (0xf400ca80, 8779 OPRND_SHIFT0 (0_4, FREG), 8780 OPRND_SHIFT0 (16_20, FREG), 8781 OPRND_SHIFT0 (21_25, FREG)), 8782 CSKY_ISA_FLOAT_7E60), 8783 OP32 ("fmach", 8784 OPCODE_INFO3 (0xf400ca80, 8785 OPRND_SHIFT0 (0_4, FREG), 8786 OPRND_SHIFT0 (16_20, FREG), 8787 OPRND_SHIFT0 (21_25, FREG)), 8788 CSKY_ISA_FLOAT_7E60), 8789 OP32 ("fnmuls.16", 8790 OPCODE_INFO3 (0xf400caa0, 8791 OPRND_SHIFT0 (0_4, FREG), 8792 OPRND_SHIFT0 (16_20, FREG), 8793 OPRND_SHIFT0 (21_25, FREG)), 8794 CSKY_ISA_FLOAT_7E60), 8795 OP32 ("fmsch", 8796 OPCODE_INFO3 (0xf400caa0, 8797 OPRND_SHIFT0 (0_4, FREG), 8798 OPRND_SHIFT0 (16_20, FREG), 8799 OPRND_SHIFT0 (21_25, FREG)), 8800 CSKY_ISA_FLOAT_7E60), 8801 OP32 ("fmuls.16", 8802 OPCODE_INFO3 (0xf400cac0, 8803 OPRND_SHIFT0 (0_4, FREG), 8804 OPRND_SHIFT0 (16_20, FREG), 8805 OPRND_SHIFT0 (21_25, FREG)), 8806 CSKY_ISA_FLOAT_7E60), 8807 OP32 ("fnmach", 8808 OPCODE_INFO3 (0xf400cac0, 8809 OPRND_SHIFT0 (0_4, FREG), 8810 OPRND_SHIFT0 (16_20, FREG), 8811 OPRND_SHIFT0 (21_25, FREG)), 8812 CSKY_ISA_FLOAT_7E60), 8813 OP32 ("fnmula.16", 8814 OPCODE_INFO3 (0xf400cae0, 8815 OPRND_SHIFT0 (0_4, FREG), 8816 OPRND_SHIFT0 (16_20, FREG), 8817 OPRND_SHIFT0 (21_25, FREG)), 8818 CSKY_ISA_FLOAT_7E60), 8819 OP32 ("fnmsch", 8820 OPCODE_INFO3 (0xf400cae0, 8821 OPRND_SHIFT0 (0_4, FREG), 8822 OPRND_SHIFT0 (16_20, FREG), 8823 OPRND_SHIFT0 (21_25, FREG)), 8824 CSKY_ISA_FLOAT_7E60), 8825 OP32 ("ffmula.16", 8826 OPCODE_INFO3 (0xf400ce00, 8827 OPRND_SHIFT0 (0_4, FREG), 8828 OPRND_SHIFT0 (16_20, FREG), 8829 OPRND_SHIFT0 (21_25, FREG)), 8830 CSKY_ISA_FLOAT_7E60), 8831 OP32 ("ffmuls.16", 8832 OPCODE_INFO3 (0xf400ce20, 8833 OPRND_SHIFT0 (0_4, FREG), 8834 OPRND_SHIFT0 (16_20, FREG), 8835 OPRND_SHIFT0 (21_25, FREG)), 8836 CSKY_ISA_FLOAT_7E60), 8837 OP32 ("ffnmula.16", 8838 OPCODE_INFO3 (0xf400ce40, 8839 OPRND_SHIFT0 (0_4, FREG), 8840 OPRND_SHIFT0 (16_20, FREG), 8841 OPRND_SHIFT0 (21_25, FREG)), 8842 CSKY_ISA_FLOAT_7E60), 8843 OP32 ("ffnmuls.16", 8844 OPCODE_INFO3 (0xf400ce60, 8845 OPRND_SHIFT0 (0_4, FREG), 8846 OPRND_SHIFT0 (16_20, FREG), 8847 OPRND_SHIFT0 (21_25, FREG)), 8848 CSKY_ISA_FLOAT_7E60), 8849 OP32 ("fdivh", 8850 OPCODE_INFO3 (0xf400cb00, 8851 OPRND_SHIFT0 (0_4, FREG), 8852 OPRND_SHIFT0 (16_20, FREG), 8853 OPRND_SHIFT0 (21_25, FREG)), 8854 CSKY_ISA_FLOAT_7E60), 8855 OP32 ("fdiv.16", 8856 OPCODE_INFO3 (0xf400cb00, 8857 OPRND_SHIFT0 (0_4, FREG), 8858 OPRND_SHIFT0 (16_20, FREG), 8859 OPRND_SHIFT0 (21_25, FREG)), 8860 CSKY_ISA_FLOAT_7E60), 8861 OP32 ("freciph", 8862 OPCODE_INFO2 (0xf400cb20, 8863 OPRND_SHIFT0 (0_4, FREG), 8864 OPRND_SHIFT0 (16_20, FREG)), 8865 CSKY_ISA_FLOAT_7E60), 8866 OP32 ("frecip.16", 8867 OPCODE_INFO2 (0xf400cb20, 8868 OPRND_SHIFT0 (0_4, FREG), 8869 OPRND_SHIFT0 (16_20, FREG)), 8870 CSKY_ISA_FLOAT_7E60), 8871 OP32 ("fsqrt.16", 8872 OPCODE_INFO2 (0xf400cb40, 8873 OPRND_SHIFT0 (0_4, FREG), 8874 OPRND_SHIFT0 (16_20, FREG)), 8875 CSKY_ISA_FLOAT_7E60), 8876 OP32 ("fsqrth", 8877 OPCODE_INFO2 (0xf400cb40, 8878 OPRND_SHIFT0 (0_4, FREG), 8879 OPRND_SHIFT0 (16_20, FREG)), 8880 CSKY_ISA_FLOAT_7E60), 8881 OP32 ("fsel.16", 8882 OPCODE_INFO3 (0xf400cf20, 8883 OPRND_SHIFT0 (0_4, FREG), 8884 OPRND_SHIFT0 (16_20, FREG), 8885 OPRND_SHIFT0 (21_25, FREG)), 8886 CSKY_ISA_FLOAT_7E60), 8887 /* Single floating. */ 8888 OP32 ("fadd.32", 8889 OPCODE_INFO3 (0xf4000000, 8890 OPRND_SHIFT0 (0_4, FREG), 8891 OPRND_SHIFT0 (16_20, FREG), 8892 OPRND_SHIFT0 (21_25, FREG)), 8893 CSKY_ISA_FLOAT_7E60), 8894 OP32 ("fadds", 8895 OPCODE_INFO3 (0xf4000000, 8896 OPRND_SHIFT0 (0_4, FREG), 8897 OPRND_SHIFT0 (16_20, FREG), 8898 OPRND_SHIFT0 (21_25, FREG)), 8899 CSKY_ISA_FLOAT_7E60), 8900 OP32 ("fsub.32", 8901 OPCODE_INFO3 (0xf4000020, 8902 OPRND_SHIFT0 (0_4, FREG), 8903 OPRND_SHIFT0 (16_20, FREG), 8904 OPRND_SHIFT0 (21_25, FREG)), 8905 CSKY_ISA_FLOAT_7E60), 8906 OP32 ("fsubs", 8907 OPCODE_INFO3 (0xf4000020, 8908 OPRND_SHIFT0 (0_4, FREG), 8909 OPRND_SHIFT0 (16_20, FREG), 8910 OPRND_SHIFT0 (21_25, FREG)), 8911 CSKY_ISA_FLOAT_7E60), 8912 OP32 ("fmov.32", 8913 OPCODE_INFO2 (0xf4000080, 8914 OPRND_SHIFT0 (0_4, FREG), 8915 OPRND_SHIFT0 (16_20, FREG)), 8916 CSKY_ISA_FLOAT_7E60), 8917 OP32 ("fmovs", 8918 OPCODE_INFO2 (0xf4000080, 8919 OPRND_SHIFT0 (0_4, FREG), 8920 OPRND_SHIFT0 (16_20, FREG)), 8921 CSKY_ISA_FLOAT_7E60), 8922 OP32 ("fabs.32", 8923 OPCODE_INFO2 (0xf40000c0, 8924 OPRND_SHIFT0 (0_4, FREG), 8925 OPRND_SHIFT0 (16_20, FREG)), 8926 CSKY_ISA_FLOAT_7E60), 8927 OP32 ("fabss", 8928 OPCODE_INFO2 (0xf40000c0, 8929 OPRND_SHIFT0 (0_4, FREG), 8930 OPRND_SHIFT0 (16_20, FREG)), 8931 CSKY_ISA_FLOAT_7E60), 8932 OP32 ("fneg.32", 8933 OPCODE_INFO2 (0xf40000e0, 8934 OPRND_SHIFT0 (0_4, FREG), 8935 OPRND_SHIFT0 (16_20, FREG)), 8936 CSKY_ISA_FLOAT_7E60), 8937 OP32 ("fnegs", 8938 OPCODE_INFO2 (0xf40000e0, 8939 OPRND_SHIFT0 (0_4, FREG), 8940 OPRND_SHIFT0 (16_20, FREG)), 8941 CSKY_ISA_FLOAT_7E60), 8942 OP32 ("fcmphsz.32", 8943 OPCODE_INFO1 (0xf4000100, 8944 OPRND_SHIFT0 (16_20, FREG)), 8945 CSKY_ISA_FLOAT_7E60), 8946 OP32 ("fcmpzhss", 8947 OPCODE_INFO1 (0xf4000100, 8948 OPRND_SHIFT0 (16_20, FREG)), 8949 CSKY_ISA_FLOAT_7E60), 8950 OP32 ("fcmpltz.32", 8951 OPCODE_INFO1 (0xf4000120, 8952 OPRND_SHIFT0 (16_20, FREG)), 8953 CSKY_ISA_FLOAT_7E60), 8954 OP32 ("fcmpzlts", 8955 OPCODE_INFO1 (0xf4000120, 8956 OPRND_SHIFT0 (16_20, FREG)), 8957 CSKY_ISA_FLOAT_7E60), 8958 OP32 ("fcmpnez.32", 8959 OPCODE_INFO1 (0xf4000140, 8960 OPRND_SHIFT0 (16_20, FREG)), 8961 CSKY_ISA_FLOAT_7E60), 8962 OP32 ("fcmpznes", 8963 OPCODE_INFO1 (0xf4000140, 8964 OPRND_SHIFT0 (16_20, FREG)), 8965 CSKY_ISA_FLOAT_7E60), 8966 OP32 ("fcmpuoz.32", 8967 OPCODE_INFO1 (0xf4000160, 8968 OPRND_SHIFT0 (16_20, FREG)), 8969 CSKY_ISA_FLOAT_7E60), 8970 OP32 ("fcmpzuos", 8971 OPCODE_INFO1 (0xf4000160, 8972 OPRND_SHIFT0 (16_20, FREG)), 8973 CSKY_ISA_FLOAT_7E60), 8974 OP32 ("fcmphs.32", 8975 OPCODE_INFO2 (0xf4000180, 8976 OPRND_SHIFT0 (16_20, FREG), 8977 OPRND_SHIFT0 (21_25, FREG)), 8978 CSKY_ISA_FLOAT_7E60), 8979 OP32 ("fcmphss", 8980 OPCODE_INFO2 (0xf4000180, 8981 OPRND_SHIFT0 (16_20, FREG), 8982 OPRND_SHIFT0 (21_25, FREG)), 8983 CSKY_ISA_FLOAT_7E60), 8984 OP32 ("fcmplt.32", 8985 OPCODE_INFO2 (0xf40001a0, 8986 OPRND_SHIFT0 (16_20, FREG), 8987 OPRND_SHIFT0 (21_25, FREG)), 8988 CSKY_ISA_FLOAT_7E60), 8989 OP32 ("fcmplts", 8990 OPCODE_INFO2 (0xf40001a0, 8991 OPRND_SHIFT0 (16_20, FREG), 8992 OPRND_SHIFT0 (21_25, FREG)), 8993 CSKY_ISA_FLOAT_7E60), 8994 OP32 ("fcmpne.32", 8995 OPCODE_INFO2 (0xf40001c0, 8996 OPRND_SHIFT0 (16_20, FREG), 8997 OPRND_SHIFT0 (21_25, FREG)), 8998 CSKY_ISA_FLOAT_7E60), 8999 OP32 ("fcmpnes", 9000 OPCODE_INFO2 (0xf40001c0, 9001 OPRND_SHIFT0 (16_20, FREG), 9002 OPRND_SHIFT0 (21_25, FREG)), 9003 CSKY_ISA_FLOAT_7E60), 9004 OP32 ("fcmpuo.32", 9005 OPCODE_INFO2 (0xf40001e0, 9006 OPRND_SHIFT0 (16_20, FREG), 9007 OPRND_SHIFT0 (21_25, FREG)), 9008 CSKY_ISA_FLOAT_7E60), 9009 OP32 ("fcmpuos", 9010 OPCODE_INFO2 (0xf40001e0, 9011 OPRND_SHIFT0 (16_20, FREG), 9012 OPRND_SHIFT0 (21_25, FREG)), 9013 CSKY_ISA_FLOAT_7E60), 9014 OP32 ("fmaxnm.32", 9015 OPCODE_INFO3 (0xf4000500, 9016 OPRND_SHIFT0 (0_4, FREG), 9017 OPRND_SHIFT0 (16_20, FREG), 9018 OPRND_SHIFT0 (21_25, FREG)), 9019 CSKY_ISA_FLOAT_7E60), 9020 OP32 ("fminnm.32", 9021 OPCODE_INFO3 (0xf4000520, 9022 OPRND_SHIFT0 (0_4, FREG), 9023 OPRND_SHIFT0 (16_20, FREG), 9024 OPRND_SHIFT0 (21_25, FREG)), 9025 CSKY_ISA_FLOAT_7E60), 9026 OP32 ("fcmphz.32", 9027 OPCODE_INFO1 (0xf4000540, 9028 OPRND_SHIFT0 (16_20, FREG)), 9029 CSKY_ISA_FLOAT_7E60), 9030 OP32 ("fcmplsz.32", 9031 OPCODE_INFO1 (0xf4000560, 9032 OPRND_SHIFT0 (16_20, FREG)), 9033 CSKY_ISA_FLOAT_7E60), 9034 OP32 ("fmul.32", 9035 OPCODE_INFO3 (0xf4000200, 9036 OPRND_SHIFT0 (0_4, FREG), 9037 OPRND_SHIFT0 (16_20, FREG), 9038 OPRND_SHIFT0 (21_25, FREG)), 9039 CSKY_ISA_FLOAT_7E60), 9040 OP32 ("fmuls", 9041 OPCODE_INFO3 (0xf4000200, 9042 OPRND_SHIFT0 (0_4, FREG), 9043 OPRND_SHIFT0 (16_20, FREG), 9044 OPRND_SHIFT0 (21_25, FREG)), 9045 CSKY_ISA_FLOAT_7E60), 9046 OP32 ("fnmul.32", 9047 OPCODE_INFO3 (0xf4000220, 9048 OPRND_SHIFT0 (0_4, FREG), 9049 OPRND_SHIFT0 (16_20, FREG), 9050 OPRND_SHIFT0 (21_25, FREG)), 9051 CSKY_ISA_FLOAT_7E60), 9052 OP32 ("fnmuls", 9053 OPCODE_INFO3 (0xf4000220, 9054 OPRND_SHIFT0 (0_4, FREG), 9055 OPRND_SHIFT0 (16_20, FREG), 9056 OPRND_SHIFT0 (21_25, FREG)), 9057 CSKY_ISA_FLOAT_7E60), 9058 OP32 ("fmula.32", 9059 OPCODE_INFO3 (0xf4000280, 9060 OPRND_SHIFT0 (0_4, FREG), 9061 OPRND_SHIFT0 (16_20, FREG), 9062 OPRND_SHIFT0 (21_25, FREG)), 9063 CSKY_ISA_FLOAT_7E60), 9064 OP32 ("fmacs", 9065 OPCODE_INFO3 (0xf4000280, 9066 OPRND_SHIFT0 (0_4, FREG), 9067 OPRND_SHIFT0 (16_20, FREG), 9068 OPRND_SHIFT0 (21_25, FREG)), 9069 CSKY_ISA_FLOAT_7E60), 9070 OP32 ("fnmuls.32", 9071 OPCODE_INFO3 (0xf40002a0, 9072 OPRND_SHIFT0 (0_4, FREG), 9073 OPRND_SHIFT0 (16_20, FREG), 9074 OPRND_SHIFT0 (21_25, FREG)), 9075 CSKY_ISA_FLOAT_7E60), 9076 OP32 ("fmscs", 9077 OPCODE_INFO3 (0xf40002a0, 9078 OPRND_SHIFT0 (0_4, FREG), 9079 OPRND_SHIFT0 (16_20, FREG), 9080 OPRND_SHIFT0 (21_25, FREG)), 9081 CSKY_ISA_FLOAT_7E60), 9082 OP32 ("fmuls.32", 9083 OPCODE_INFO3 (0xf40002c0, 9084 OPRND_SHIFT0 (0_4, FREG), 9085 OPRND_SHIFT0 (16_20, FREG), 9086 OPRND_SHIFT0 (21_25, FREG)), 9087 CSKY_ISA_FLOAT_7E60), 9088 OP32 ("fnmacs", 9089 OPCODE_INFO3 (0xf40002c0, 9090 OPRND_SHIFT0 (0_4, FREG), 9091 OPRND_SHIFT0 (16_20, FREG), 9092 OPRND_SHIFT0 (21_25, FREG)), 9093 CSKY_ISA_FLOAT_7E60), 9094 OP32 ("fnmula.32", 9095 OPCODE_INFO3 (0xf40002e0, 9096 OPRND_SHIFT0 (0_4, FREG), 9097 OPRND_SHIFT0 (16_20, FREG), 9098 OPRND_SHIFT0 (21_25, FREG)), 9099 CSKY_ISA_FLOAT_7E60), 9100 OP32 ("fnmscs", 9101 OPCODE_INFO3 (0xf40002e0, 9102 OPRND_SHIFT0 (0_4, FREG), 9103 OPRND_SHIFT0 (16_20, FREG), 9104 OPRND_SHIFT0 (21_25, FREG)), 9105 CSKY_ISA_FLOAT_7E60), 9106 OP32 ("ffmula.32", 9107 OPCODE_INFO3 (0xf4000600, 9108 OPRND_SHIFT0 (0_4, FREG), 9109 OPRND_SHIFT0 (16_20, FREG), 9110 OPRND_SHIFT0 (21_25, FREG)), 9111 CSKY_ISA_FLOAT_7E60), 9112 OP32 ("ffmuls.32", 9113 OPCODE_INFO3 (0xf4000620, 9114 OPRND_SHIFT0 (0_4, FREG), 9115 OPRND_SHIFT0 (16_20, FREG), 9116 OPRND_SHIFT0 (21_25, FREG)), 9117 CSKY_ISA_FLOAT_7E60), 9118 OP32 ("ffnmula.32", 9119 OPCODE_INFO3 (0xf4000640, 9120 OPRND_SHIFT0 (0_4, FREG), 9121 OPRND_SHIFT0 (16_20, FREG), 9122 OPRND_SHIFT0 (21_25, FREG)), 9123 CSKY_ISA_FLOAT_7E60), 9124 OP32 ("ffnmuls.32", 9125 OPCODE_INFO3 (0xf4000660, 9126 OPRND_SHIFT0 (0_4, FREG), 9127 OPRND_SHIFT0 (16_20, FREG), 9128 OPRND_SHIFT0 (21_25, FREG)), 9129 CSKY_ISA_FLOAT_7E60), 9130 OP32 ("fdiv.32", 9131 OPCODE_INFO3 (0xf4000300, 9132 OPRND_SHIFT0 (0_4, FREG), 9133 OPRND_SHIFT0 (16_20, FREG), 9134 OPRND_SHIFT0 (21_25, FREG)), 9135 CSKY_ISA_FLOAT_7E60), 9136 OP32 ("fdivs", 9137 OPCODE_INFO3 (0xf4000300, 9138 OPRND_SHIFT0 (0_4, FREG), 9139 OPRND_SHIFT0 (16_20, FREG), 9140 OPRND_SHIFT0 (21_25, FREG)), 9141 CSKY_ISA_FLOAT_7E60), 9142 OP32 ("frecip.32", 9143 OPCODE_INFO2 (0xf4000320, 9144 OPRND_SHIFT0 (0_4, FREG), 9145 OPRND_SHIFT0 (16_20, FREG)), 9146 CSKY_ISA_FLOAT_7E60), 9147 OP32 ("frecips", 9148 OPCODE_INFO2 (0xf4000320, 9149 OPRND_SHIFT0 (0_4, FREG), 9150 OPRND_SHIFT0 (16_20, FREG)), 9151 CSKY_ISA_FLOAT_7E60), 9152 OP32 ("fsqrt.32", 9153 OPCODE_INFO2 (0xf4000340, 9154 OPRND_SHIFT0 (0_4, FREG), 9155 OPRND_SHIFT0 (16_20, FREG)), 9156 CSKY_ISA_FLOAT_7E60), 9157 OP32 ("fsqrts", 9158 OPCODE_INFO2 (0xf4000340, 9159 OPRND_SHIFT0 (0_4, FREG), 9160 OPRND_SHIFT0 (16_20, FREG)), 9161 CSKY_ISA_FLOAT_7E60), 9162 OP32 ("fsel.32", 9163 OPCODE_INFO3 (0xf4000720, 9164 OPRND_SHIFT0 (0_4, FREG), 9165 OPRND_SHIFT0 (16_20, FREG), 9166 OPRND_SHIFT0 (21_25, FREG)), 9167 CSKY_ISA_FLOAT_7E60), 9168 /* Double floating. */ 9169 OP32 ("fadd.64", 9170 OPCODE_INFO3 (0xf4000800, 9171 OPRND_SHIFT0 (0_4, FREG), 9172 OPRND_SHIFT0 (16_20, FREG), 9173 OPRND_SHIFT0 (21_25, FREG)), 9174 CSKY_ISA_FLOAT_7E60), 9175 OP32 ("faddd", 9176 OPCODE_INFO3 (0xf4000800, 9177 OPRND_SHIFT0 (0_4, FREG), 9178 OPRND_SHIFT0 (16_20, FREG), 9179 OPRND_SHIFT0 (21_25, FREG)), 9180 CSKY_ISA_FLOAT_7E60), 9181 OP32 ("fsub.64", 9182 OPCODE_INFO3 (0xf4000820, 9183 OPRND_SHIFT0 (0_4, FREG), 9184 OPRND_SHIFT0 (16_20, FREG), 9185 OPRND_SHIFT0 (21_25, FREG)), 9186 CSKY_ISA_FLOAT_7E60), 9187 OP32 ("fsubd", 9188 OPCODE_INFO3 (0xf4000820, 9189 OPRND_SHIFT0 (0_4, FREG), 9190 OPRND_SHIFT0 (16_20, FREG), 9191 OPRND_SHIFT0 (21_25, FREG)), 9192 CSKY_ISA_FLOAT_7E60), 9193 OP32 ("fmov.64", 9194 OPCODE_INFO2 (0xf4000880, 9195 OPRND_SHIFT0 (0_4, FREG), 9196 OPRND_SHIFT0 (16_20, FREG)), 9197 CSKY_ISA_FLOAT_7E60), 9198 OP32 ("fmovd", 9199 OPCODE_INFO2 (0xf4000880, 9200 OPRND_SHIFT0 (0_4, FREG), 9201 OPRND_SHIFT0 (16_20, FREG)), 9202 CSKY_ISA_FLOAT_7E60), 9203 OP32 ("fmovx.32", 9204 OPCODE_INFO2 (0xf40008a0, 9205 OPRND_SHIFT0 (0_4, FREG), 9206 OPRND_SHIFT0 (16_20, FREG)), 9207 CSKY_ISA_FLOAT_7E60), 9208 OP32 ("fabs.64", 9209 OPCODE_INFO2 (0xf40008c0, 9210 OPRND_SHIFT0 (0_4, FREG), 9211 OPRND_SHIFT0 (16_20, FREG)), 9212 CSKY_ISA_FLOAT_7E60), 9213 OP32 ("fabsd", 9214 OPCODE_INFO2 (0xf40008c0, 9215 OPRND_SHIFT0 (0_4, FREG), 9216 OPRND_SHIFT0 (16_20, FREG)), 9217 CSKY_ISA_FLOAT_7E60), 9218 OP32 ("fneg.64", 9219 OPCODE_INFO2 (0xf40008e0, 9220 OPRND_SHIFT0 (0_4, FREG), 9221 OPRND_SHIFT0 (16_20, FREG)), 9222 CSKY_ISA_FLOAT_7E60), 9223 OP32 ("fnegd", 9224 OPCODE_INFO2 (0xf40008e0, 9225 OPRND_SHIFT0 (0_4, FREG), 9226 OPRND_SHIFT0 (16_20, FREG)), 9227 CSKY_ISA_FLOAT_7E60), 9228 OP32 ("fcmphsz.64", 9229 OPCODE_INFO1 (0xf4000900, 9230 OPRND_SHIFT0 (16_20, FREG)), 9231 CSKY_ISA_FLOAT_7E60), 9232 OP32 ("fcmpzhsd", 9233 OPCODE_INFO1 (0xf4000900, 9234 OPRND_SHIFT0 (16_20, FREG)), 9235 CSKY_ISA_FLOAT_7E60), 9236 OP32 ("fcmpltz.64", 9237 OPCODE_INFO1 (0xf4000920, 9238 OPRND_SHIFT0 (16_20, FREG)), 9239 CSKY_ISA_FLOAT_7E60), 9240 OP32 ("fcmpzltd", 9241 OPCODE_INFO1 (0xf4000920, 9242 OPRND_SHIFT0 (16_20, FREG)), 9243 CSKY_ISA_FLOAT_7E60), 9244 OP32 ("fcmpnez.64", 9245 OPCODE_INFO1 (0xf4000940, 9246 OPRND_SHIFT0 (16_20, FREG)), 9247 CSKY_ISA_FLOAT_7E60), 9248 OP32 ("fcmpzned", 9249 OPCODE_INFO1 (0xf4000940, 9250 OPRND_SHIFT0 (16_20, FREG)), 9251 CSKY_ISA_FLOAT_7E60), 9252 OP32 ("fcmpuoz.64", 9253 OPCODE_INFO1 (0xf4000960, 9254 OPRND_SHIFT0 (16_20, FREG)), 9255 CSKY_ISA_FLOAT_7E60), 9256 OP32 ("fcmpzuod", 9257 OPCODE_INFO1 (0xf4000960, 9258 OPRND_SHIFT0 (16_20, FREG)), 9259 CSKY_ISA_FLOAT_7E60), 9260 OP32 ("fcmphs.64", 9261 OPCODE_INFO2 (0xf4000980, 9262 OPRND_SHIFT0 (16_20, FREG), 9263 OPRND_SHIFT0 (21_25, FREG)), 9264 CSKY_ISA_FLOAT_7E60), 9265 OP32 ("fcmphsd", 9266 OPCODE_INFO2 (0xf4000980, 9267 OPRND_SHIFT0 (16_20, FREG), 9268 OPRND_SHIFT0 (21_25, FREG)), 9269 CSKY_ISA_FLOAT_7E60), 9270 OP32 ("fcmplt.64", 9271 OPCODE_INFO2 (0xf40009a0, 9272 OPRND_SHIFT0 (16_20, FREG), 9273 OPRND_SHIFT0 (21_25, FREG)), 9274 CSKY_ISA_FLOAT_7E60), 9275 OP32 ("fcmpltd", 9276 OPCODE_INFO2 (0xf40009a0, 9277 OPRND_SHIFT0 (16_20, FREG), 9278 OPRND_SHIFT0 (21_25, FREG)), 9279 CSKY_ISA_FLOAT_7E60), 9280 OP32 ("fcmpne.64", 9281 OPCODE_INFO2 (0xf40009c0, 9282 OPRND_SHIFT0 (16_20, FREG), 9283 OPRND_SHIFT0 (21_25, FREG)), 9284 CSKY_ISA_FLOAT_7E60), 9285 OP32 ("fcmpned", 9286 OPCODE_INFO2 (0xf40009c0, 9287 OPRND_SHIFT0 (16_20, FREG), 9288 OPRND_SHIFT0 (21_25, FREG)), 9289 CSKY_ISA_FLOAT_7E60), 9290 OP32 ("fcmpuo.64", 9291 OPCODE_INFO2 (0xf40009e0, 9292 OPRND_SHIFT0 (16_20, FREG), 9293 OPRND_SHIFT0 (21_25, FREG)), 9294 CSKY_ISA_FLOAT_7E60), 9295 OP32 ("fcmpuod", 9296 OPCODE_INFO2 (0xf40009e0, 9297 OPRND_SHIFT0 (16_20, FREG), 9298 OPRND_SHIFT0 (21_25, FREG)), 9299 CSKY_ISA_FLOAT_7E60), 9300 OP32 ("fmaxnm.64", 9301 OPCODE_INFO3 (0xf4000d00, 9302 OPRND_SHIFT0 (0_4, FREG), 9303 OPRND_SHIFT0 (16_20, FREG), 9304 OPRND_SHIFT0 (21_25, FREG)), 9305 CSKY_ISA_FLOAT_7E60), 9306 OP32 ("fminnm.64", 9307 OPCODE_INFO3 (0xf4000d20, 9308 OPRND_SHIFT0 (0_4, FREG), 9309 OPRND_SHIFT0 (16_20, FREG), 9310 OPRND_SHIFT0 (21_25, FREG)), 9311 CSKY_ISA_FLOAT_7E60), 9312 OP32 ("fcmphz.64", 9313 OPCODE_INFO1 (0xf4000d40, 9314 OPRND_SHIFT0 (16_20, FREG)), 9315 CSKY_ISA_FLOAT_7E60), 9316 OP32 ("fcmplsz.64", 9317 OPCODE_INFO1 (0xf4000d60, 9318 OPRND_SHIFT0 (16_20, FREG)), 9319 CSKY_ISA_FLOAT_7E60), 9320 OP32 ("fmul.64", 9321 OPCODE_INFO3 (0xf4000a00, 9322 OPRND_SHIFT0 (0_4, FREG), 9323 OPRND_SHIFT0 (16_20, FREG), 9324 OPRND_SHIFT0 (21_25, FREG)), 9325 CSKY_ISA_FLOAT_7E60), 9326 OP32 ("fmuld", 9327 OPCODE_INFO3 (0xf4000a00, 9328 OPRND_SHIFT0 (0_4, FREG), 9329 OPRND_SHIFT0 (16_20, FREG), 9330 OPRND_SHIFT0 (21_25, FREG)), 9331 CSKY_ISA_FLOAT_7E60), 9332 OP32 ("fnmul.64", 9333 OPCODE_INFO3 (0xf4000a20, 9334 OPRND_SHIFT0 (0_4, FREG), 9335 OPRND_SHIFT0 (16_20, FREG), 9336 OPRND_SHIFT0 (21_25, FREG)), 9337 CSKY_ISA_FLOAT_7E60), 9338 OP32 ("fnmuld", 9339 OPCODE_INFO3 (0xf4000a20, 9340 OPRND_SHIFT0 (0_4, FREG), 9341 OPRND_SHIFT0 (16_20, FREG), 9342 OPRND_SHIFT0 (21_25, FREG)), 9343 CSKY_ISA_FLOAT_7E60), 9344 OP32 ("fmula.64", 9345 OPCODE_INFO3 (0xf4000a80, 9346 OPRND_SHIFT0 (0_4, FREG), 9347 OPRND_SHIFT0 (16_20, FREG), 9348 OPRND_SHIFT0 (21_25, FREG)), 9349 CSKY_ISA_FLOAT_7E60), 9350 OP32 ("fmacd", 9351 OPCODE_INFO3 (0xf4000a80, 9352 OPRND_SHIFT0 (0_4, FREG), 9353 OPRND_SHIFT0 (16_20, FREG), 9354 OPRND_SHIFT0 (21_25, FREG)), 9355 CSKY_ISA_FLOAT_7E60), 9356 OP32 ("fnmuls.64", 9357 OPCODE_INFO3 (0xf4000aa0, 9358 OPRND_SHIFT0 (0_4, FREG), 9359 OPRND_SHIFT0 (16_20, FREG), 9360 OPRND_SHIFT0 (21_25, FREG)), 9361 CSKY_ISA_FLOAT_7E60), 9362 OP32 ("fmscd", 9363 OPCODE_INFO3 (0xf4000aa0, 9364 OPRND_SHIFT0 (0_4, FREG), 9365 OPRND_SHIFT0 (16_20, FREG), 9366 OPRND_SHIFT0 (21_25, FREG)), 9367 CSKY_ISA_FLOAT_7E60), 9368 OP32 ("fmuls.64", 9369 OPCODE_INFO3 (0xf4000ac0, 9370 OPRND_SHIFT0 (0_4, FREG), 9371 OPRND_SHIFT0 (16_20, FREG), 9372 OPRND_SHIFT0 (21_25, FREG)), 9373 CSKY_ISA_FLOAT_7E60), 9374 OP32 ("fnmacd", 9375 OPCODE_INFO3 (0xf4000ac0, 9376 OPRND_SHIFT0 (0_4, FREG), 9377 OPRND_SHIFT0 (16_20, FREG), 9378 OPRND_SHIFT0 (21_25, FREG)), 9379 CSKY_ISA_FLOAT_7E60), 9380 OP32 ("fnmula.64", 9381 OPCODE_INFO3 (0xf4000ae0, 9382 OPRND_SHIFT0 (0_4, FREG), 9383 OPRND_SHIFT0 (16_20, FREG), 9384 OPRND_SHIFT0 (21_25, FREG)), 9385 CSKY_ISA_FLOAT_7E60), 9386 OP32 ("fnmscd", 9387 OPCODE_INFO3 (0xf4000ae0, 9388 OPRND_SHIFT0 (0_4, FREG), 9389 OPRND_SHIFT0 (16_20, FREG), 9390 OPRND_SHIFT0 (21_25, FREG)), 9391 CSKY_ISA_FLOAT_7E60), 9392 OP32 ("ffmula.64", 9393 OPCODE_INFO3 (0xf4000e00, 9394 OPRND_SHIFT0 (0_4, FREG), 9395 OPRND_SHIFT0 (16_20, FREG), 9396 OPRND_SHIFT0 (21_25, FREG)), 9397 CSKY_ISA_FLOAT_7E60), 9398 OP32 ("ffmuls.64", 9399 OPCODE_INFO3 (0xf4000e20, 9400 OPRND_SHIFT0 (0_4, FREG), 9401 OPRND_SHIFT0 (16_20, FREG), 9402 OPRND_SHIFT0 (21_25, FREG)), 9403 CSKY_ISA_FLOAT_7E60), 9404 OP32 ("ffnmula.64", 9405 OPCODE_INFO3 (0xf4000e40, 9406 OPRND_SHIFT0 (0_4, FREG), 9407 OPRND_SHIFT0 (16_20, FREG), 9408 OPRND_SHIFT0 (21_25, FREG)), 9409 CSKY_ISA_FLOAT_7E60), 9410 OP32 ("ffnmuls.64", 9411 OPCODE_INFO3 (0xf4000e60, 9412 OPRND_SHIFT0 (0_4, FREG), 9413 OPRND_SHIFT0 (16_20, FREG), 9414 OPRND_SHIFT0 (21_25, FREG)), 9415 CSKY_ISA_FLOAT_7E60), 9416 OP32 ("fdiv.64", 9417 OPCODE_INFO3 (0xf4000b00, 9418 OPRND_SHIFT0 (0_4, FREG), 9419 OPRND_SHIFT0 (16_20, FREG), 9420 OPRND_SHIFT0 (21_25, FREG)), 9421 CSKY_ISA_FLOAT_7E60), 9422 OP32 ("fdivd", 9423 OPCODE_INFO3 (0xf4000b00, 9424 OPRND_SHIFT0 (0_4, FREG), 9425 OPRND_SHIFT0 (16_20, FREG), 9426 OPRND_SHIFT0 (21_25, FREG)), 9427 CSKY_ISA_FLOAT_7E60), 9428 OP32 ("frecip.64", 9429 OPCODE_INFO2 (0xf4000b20, 9430 OPRND_SHIFT0 (0_4, FREG), 9431 OPRND_SHIFT0 (16_20, FREG)), 9432 CSKY_ISA_FLOAT_7E60), 9433 OP32 ("frecipd", 9434 OPCODE_INFO2 (0xf4000b20, 9435 OPRND_SHIFT0 (0_4, FREG), 9436 OPRND_SHIFT0 (16_20, FREG)), 9437 CSKY_ISA_FLOAT_7E60), 9438 OP32 ("fsqrt.64", 9439 OPCODE_INFO2 (0xf4000b40, 9440 OPRND_SHIFT0 (0_4, FREG), 9441 OPRND_SHIFT0 (16_20, FREG)), 9442 CSKY_ISA_FLOAT_7E60), 9443 OP32 ("fsqrtd", 9444 OPCODE_INFO2 (0xf4000b40, 9445 OPRND_SHIFT0 (0_4, FREG), 9446 OPRND_SHIFT0 (16_20, FREG)), 9447 CSKY_ISA_FLOAT_7E60), 9448 OP32 ("fins.32", 9449 OPCODE_INFO2 (0xf4000360, 9450 OPRND_SHIFT0 (0_4, FREG), 9451 OPRND_SHIFT0 (16_20, FREG)), 9452 CSKY_ISA_FLOAT_7E60), 9453 OP32 ("fsel.64", 9454 OPCODE_INFO3 (0xf4000f20, 9455 OPRND_SHIFT0 (0_4, FREG), 9456 OPRND_SHIFT0 (16_20, FREG), 9457 OPRND_SHIFT0 (21_25, FREG)), 9458 CSKY_ISA_FLOAT_7E60), 9459 /* SIMD floating. */ 9460 OP32 ("fadd.f32", 9461 OPCODE_INFO3 (0xf4001000, 9462 OPRND_SHIFT0 (0_4, FREG), 9463 OPRND_SHIFT0 (16_20, FREG), 9464 OPRND_SHIFT0 (21_25, FREG)), 9465 CSKY_ISA_FLOAT_7E60), 9466 OP32 ("faddm", 9467 OPCODE_INFO3 (0xf4001000, 9468 OPRND_SHIFT0 (0_4, FREG), 9469 OPRND_SHIFT0 (16_20, FREG), 9470 OPRND_SHIFT0 (21_25, FREG)), 9471 CSKY_ISA_FLOAT_7E60), 9472 OP32 ("fsub.f32", 9473 OPCODE_INFO3 (0xf4001020, 9474 OPRND_SHIFT0 (0_4, FREG), 9475 OPRND_SHIFT0 (16_20, FREG), 9476 OPRND_SHIFT0 (21_25, FREG)), 9477 CSKY_ISA_FLOAT_7E60), 9478 OP32 ("fsubm", 9479 OPCODE_INFO3 (0xf4001020, 9480 OPRND_SHIFT0 (0_4, FREG), 9481 OPRND_SHIFT0 (16_20, FREG), 9482 OPRND_SHIFT0 (21_25, FREG)), 9483 CSKY_ISA_FLOAT_7E60), 9484 OP32 ("fmov.f32", 9485 OPCODE_INFO2 (0xf4001080, 9486 OPRND_SHIFT0 (0_4, FREG), 9487 OPRND_SHIFT0 (16_20, FREG)), 9488 CSKY_ISA_FLOAT_7E60), 9489 OP32 ("fmovm", 9490 OPCODE_INFO2 (0xf4001080, 9491 OPRND_SHIFT0 (0_4, FREG), 9492 OPRND_SHIFT0 (16_20, FREG)), 9493 CSKY_ISA_FLOAT_7E60), 9494 OP32 ("fabs.f32", 9495 OPCODE_INFO2 (0xf40010c0, 9496 OPRND_SHIFT0 (0_4, FREG), 9497 OPRND_SHIFT0 (16_20, FREG)), 9498 CSKY_ISA_FLOAT_7E60), 9499 OP32 ("fabsm", 9500 OPCODE_INFO2 (0xf40010c0, 9501 OPRND_SHIFT0 (0_4, FREG), 9502 OPRND_SHIFT0 (16_20, FREG)), 9503 CSKY_ISA_FLOAT_7E60), 9504 OP32 ("fneg.f32", 9505 OPCODE_INFO2 (0xf40010e0, 9506 OPRND_SHIFT0 (0_4, FREG), 9507 OPRND_SHIFT0 (16_20, FREG)), 9508 CSKY_ISA_FLOAT_7E60), 9509 OP32 ("fnegm", 9510 OPCODE_INFO2 (0xf40010e0, 9511 OPRND_SHIFT0 (0_4, FREG), 9512 OPRND_SHIFT0 (16_20, FREG)), 9513 CSKY_ISA_FLOAT_7E60), 9514 OP32 ("fmul.f32", 9515 OPCODE_INFO3 (0xf4001200, 9516 OPRND_SHIFT0 (0_4, FREG), 9517 OPRND_SHIFT0 (16_20, FREG), 9518 OPRND_SHIFT0 (21_25, FREG)), 9519 CSKY_ISA_FLOAT_7E60), 9520 OP32 ("fmulm", 9521 OPCODE_INFO3 (0xf4001200, 9522 OPRND_SHIFT0 (0_4, FREG), 9523 OPRND_SHIFT0 (16_20, FREG), 9524 OPRND_SHIFT0 (21_25, FREG)), 9525 CSKY_ISA_FLOAT_7E60), 9526 OP32 ("fmula.f32", 9527 OPCODE_INFO3 (0xf4001280, 9528 OPRND_SHIFT0 (0_4, FREG), 9529 OPRND_SHIFT0 (16_20, FREG), 9530 OPRND_SHIFT0 (21_25, FREG)), 9531 CSKY_ISA_FLOAT_7E60), 9532 OP32 ("fmuls.f32", 9533 OPCODE_INFO3 (0xf40012c0, 9534 OPRND_SHIFT0 (0_4, FREG), 9535 OPRND_SHIFT0 (16_20, FREG), 9536 OPRND_SHIFT0 (21_25, FREG)), 9537 CSKY_ISA_FLOAT_7E60), 9538 OP32 ("fnmacm", 9539 OPCODE_INFO3 (0xf40012c0, 9540 OPRND_SHIFT0 (0_4, FREG), 9541 OPRND_SHIFT0 (16_20, FREG), 9542 OPRND_SHIFT0 (21_25, FREG)), 9543 CSKY_ISA_FLOAT_7E60), 9544 /* floating formate. */ 9545 OP32 ("fftoi.f32.s32.rn", 9546 OPCODE_INFO2 (0xf4001800, 9547 OPRND_SHIFT0 (0_4, FREG), 9548 OPRND_SHIFT0 (16_20, FREG)), 9549 CSKY_ISA_FLOAT_7E60), 9550 OP32 ("fstosi.rn", 9551 OPCODE_INFO2 (0xf4001800, 9552 OPRND_SHIFT0 (0_4, FREG), 9553 OPRND_SHIFT0 (16_20, FREG)), 9554 CSKY_ISA_FLOAT_7E60), 9555 OP32 ("fftoi.f32.s32.rz", 9556 OPCODE_INFO2 (0xf4001820, 9557 OPRND_SHIFT0 (0_4, FREG), 9558 OPRND_SHIFT0 (16_20, FREG)), 9559 CSKY_ISA_FLOAT_7E60), 9560 OP32 ("fstosi.rz", 9561 OPCODE_INFO2 (0xf4001820, 9562 OPRND_SHIFT0 (0_4, FREG), 9563 OPRND_SHIFT0 (16_20, FREG)), 9564 CSKY_ISA_FLOAT_7E60), 9565 OP32 ("fftoi.f32.s32.rpi", 9566 OPCODE_INFO2 (0xf4001840, 9567 OPRND_SHIFT0 (0_4, FREG), 9568 OPRND_SHIFT0 (16_20, FREG)), 9569 CSKY_ISA_FLOAT_7E60), 9570 OP32 ("fstosi.rpi", 9571 OPCODE_INFO2 (0xf4001840, 9572 OPRND_SHIFT0 (0_4, FREG), 9573 OPRND_SHIFT0 (16_20, FREG)), 9574 CSKY_ISA_FLOAT_7E60), 9575 OP32 ("fftoi.f32.s32.rni", 9576 OPCODE_INFO2 (0xf4001860, 9577 OPRND_SHIFT0 (0_4, FREG), 9578 OPRND_SHIFT0 (16_20, FREG)), 9579 CSKY_ISA_FLOAT_7E60), 9580 OP32 ("fstosi.rni", 9581 OPCODE_INFO2 (0xf4001860, 9582 OPRND_SHIFT0 (0_4, FREG), 9583 OPRND_SHIFT0 (16_20, FREG)), 9584 CSKY_ISA_FLOAT_7E60), 9585 OP32 ("fftoi.f32.u32.rn", 9586 OPCODE_INFO2 (0xf4001880, 9587 OPRND_SHIFT0 (0_4, FREG), 9588 OPRND_SHIFT0 (16_20, FREG)), 9589 CSKY_ISA_FLOAT_7E60), 9590 OP32 ("fstoui.rn", 9591 OPCODE_INFO2 (0xf4001880, 9592 OPRND_SHIFT0 (0_4, FREG), 9593 OPRND_SHIFT0 (16_20, FREG)), 9594 CSKY_ISA_FLOAT_7E60), 9595 OP32 ("fftoi.f32.u32.rz", 9596 OPCODE_INFO2 (0xf40018a0, 9597 OPRND_SHIFT0 (0_4, FREG), 9598 OPRND_SHIFT0 (16_20, FREG)), 9599 CSKY_ISA_FLOAT_7E60), 9600 OP32 ("fstoui.rz", 9601 OPCODE_INFO2 (0xf40018a0, 9602 OPRND_SHIFT0 (0_4, FREG), 9603 OPRND_SHIFT0 (16_20, FREG)), 9604 CSKY_ISA_FLOAT_7E60), 9605 OP32 ("fftoi.f32.u32.rpi", 9606 OPCODE_INFO2 (0xf40018c0, 9607 OPRND_SHIFT0 (0_4, FREG), 9608 OPRND_SHIFT0 (16_20, FREG)), 9609 CSKY_ISA_FLOAT_7E60), 9610 OP32 ("fstoui.rpi", 9611 OPCODE_INFO2 (0xf40018c0, 9612 OPRND_SHIFT0 (0_4, FREG), 9613 OPRND_SHIFT0 (16_20, FREG)), 9614 CSKY_ISA_FLOAT_7E60), 9615 OP32 ("fftoi.f32.u32.rni", 9616 OPCODE_INFO2 (0xf40018e0, 9617 OPRND_SHIFT0 (0_4, FREG), 9618 OPRND_SHIFT0 (16_20, FREG)), 9619 CSKY_ISA_FLOAT_7E60), 9620 OP32 ("fstoui.rni", 9621 OPCODE_INFO2 (0xf40018e0, 9622 OPRND_SHIFT0 (0_4, FREG), 9623 OPRND_SHIFT0 (16_20, FREG)), 9624 CSKY_ISA_FLOAT_7E60), 9625 OP32 ("fftoi.f64.s32.rn", 9626 OPCODE_INFO2 (0xf4001900, 9627 OPRND_SHIFT0 (0_4, FREG), 9628 OPRND_SHIFT0 (16_20, FREG)), 9629 CSKY_ISA_FLOAT_7E60), 9630 OP32 ("fdtosi.rn", 9631 OPCODE_INFO2 (0xf4001900, 9632 OPRND_SHIFT0 (0_4, FREG), 9633 OPRND_SHIFT0 (16_20, FREG)), 9634 CSKY_ISA_FLOAT_7E60), 9635 OP32 ("fftoi.f64.s32.rz", 9636 OPCODE_INFO2 (0xf4001920, 9637 OPRND_SHIFT0 (0_4, FREG), 9638 OPRND_SHIFT0 (16_20, FREG)), 9639 CSKY_ISA_FLOAT_7E60), 9640 OP32 ("fdtosi.rz", 9641 OPCODE_INFO2 (0xf4001920, 9642 OPRND_SHIFT0 (0_4, FREG), 9643 OPRND_SHIFT0 (16_20, FREG)), 9644 CSKY_ISA_FLOAT_7E60), 9645 OP32 ("fftoi.f64.s32.rpi", 9646 OPCODE_INFO2 (0xf4001940, 9647 OPRND_SHIFT0 (0_4, FREG), 9648 OPRND_SHIFT0 (16_20, FREG)), 9649 CSKY_ISA_FLOAT_7E60), 9650 OP32 ("fdtosi.rpi", 9651 OPCODE_INFO2 (0xf4001940, 9652 OPRND_SHIFT0 (0_4, FREG), 9653 OPRND_SHIFT0 (16_20, FREG)), 9654 CSKY_ISA_FLOAT_7E60), 9655 OP32 ("fftoi.f64.s32.rni", 9656 OPCODE_INFO2 (0xf4001960, 9657 OPRND_SHIFT0 (0_4, FREG), 9658 OPRND_SHIFT0 (16_20, FREG)), 9659 CSKY_ISA_FLOAT_7E60), 9660 OP32 ("fdtosi.rni", 9661 OPCODE_INFO2 (0xf4001960, 9662 OPRND_SHIFT0 (0_4, FREG), 9663 OPRND_SHIFT0 (16_20, FREG)), 9664 CSKY_ISA_FLOAT_7E60), 9665 OP32 ("fftoi.f64.u32.rn", 9666 OPCODE_INFO2 (0xf4001980, 9667 OPRND_SHIFT0 (0_4, FREG), 9668 OPRND_SHIFT0 (16_20, FREG)), 9669 CSKY_ISA_FLOAT_7E60), 9670 OP32 ("fdtoui.rn", 9671 OPCODE_INFO2 (0xf4001980, 9672 OPRND_SHIFT0 (0_4, FREG), 9673 OPRND_SHIFT0 (16_20, FREG)), 9674 CSKY_ISA_FLOAT_7E60), 9675 OP32 ("fftoi.f64.u32.rz", 9676 OPCODE_INFO2 (0xf40019a0, 9677 OPRND_SHIFT0 (0_4, FREG), 9678 OPRND_SHIFT0 (16_20, FREG)), 9679 CSKY_ISA_FLOAT_7E60), 9680 OP32 ("fdtoui.rz", 9681 OPCODE_INFO2 (0xf40019a0, 9682 OPRND_SHIFT0 (0_4, FREG), 9683 OPRND_SHIFT0 (16_20, FREG)), 9684 CSKY_ISA_FLOAT_7E60), 9685 OP32 ("fftoi.f64.u32.rpi", 9686 OPCODE_INFO2 (0xf40019c0, 9687 OPRND_SHIFT0 (0_4, FREG), 9688 OPRND_SHIFT0 (16_20, FREG)), 9689 CSKY_ISA_FLOAT_7E60), 9690 OP32 ("fdtoui.rpi", 9691 OPCODE_INFO2 (0xf40019c0, 9692 OPRND_SHIFT0 (0_4, FREG), 9693 OPRND_SHIFT0 (16_20, FREG)), 9694 CSKY_ISA_FLOAT_7E60), 9695 OP32 ("fftoi.f64.u32.rni", 9696 OPCODE_INFO2 (0xf40019e0, 9697 OPRND_SHIFT0 (0_4, FREG), 9698 OPRND_SHIFT0 (16_20, FREG)), 9699 CSKY_ISA_FLOAT_7E60), 9700 OP32 ("fdtoui.rni", 9701 OPCODE_INFO2 (0xf40019e0, 9702 OPRND_SHIFT0 (0_4, FREG), 9703 OPRND_SHIFT0 (16_20, FREG)), 9704 CSKY_ISA_FLOAT_7E60), 9705 OP32 ("fftoi.f16.s32.rn", 9706 OPCODE_INFO2 (0xf4001c00, 9707 OPRND_SHIFT0 (0_4, FREG), 9708 OPRND_SHIFT0 (16_20, FREG)), 9709 CSKY_ISA_FLOAT_7E60), 9710 OP32 ("fhtosi.rn", 9711 OPCODE_INFO2 (0xf4001c00, 9712 OPRND_SHIFT0 (0_4, FREG), 9713 OPRND_SHIFT0 (16_20, FREG)), 9714 CSKY_ISA_FLOAT_7E60), 9715 OP32 ("fftoi.f16.s32.rz", 9716 OPCODE_INFO2 (0xf4001c20, 9717 OPRND_SHIFT0 (0_4, FREG), 9718 OPRND_SHIFT0 (16_20, FREG)), 9719 CSKY_ISA_FLOAT_7E60), 9720 OP32 ("fhtosi.rz", 9721 OPCODE_INFO2 (0xf4001c20, 9722 OPRND_SHIFT0 (0_4, FREG), 9723 OPRND_SHIFT0 (16_20, FREG)), 9724 CSKY_ISA_FLOAT_7E60), 9725 OP32 ("fftoi.f16.s32.rpi", 9726 OPCODE_INFO2 (0xf4001c40, 9727 OPRND_SHIFT0 (0_4, FREG), 9728 OPRND_SHIFT0 (16_20, FREG)), 9729 CSKY_ISA_FLOAT_7E60), 9730 OP32 ("fhtosi.rpi", 9731 OPCODE_INFO2 (0xf4001c40, 9732 OPRND_SHIFT0 (0_4, FREG), 9733 OPRND_SHIFT0 (16_20, FREG)), 9734 CSKY_ISA_FLOAT_7E60), 9735 OP32 ("fftoi.f16.s32.rni", 9736 OPCODE_INFO2 (0xf4001c60, 9737 OPRND_SHIFT0 (0_4, FREG), 9738 OPRND_SHIFT0 (16_20, FREG)), 9739 CSKY_ISA_FLOAT_7E60), 9740 OP32 ("fhtosi.rni", 9741 OPCODE_INFO2 (0xf4001c60, 9742 OPRND_SHIFT0 (0_4, FREG), 9743 OPRND_SHIFT0 (16_20, FREG)), 9744 CSKY_ISA_FLOAT_7E60), 9745 OP32 ("fftoi.f16.u32.rn", 9746 OPCODE_INFO2 (0xf4001c80, 9747 OPRND_SHIFT0 (0_4, FREG), 9748 OPRND_SHIFT0 (16_20, FREG)), 9749 CSKY_ISA_FLOAT_7E60), 9750 OP32 ("fhtoui.rn", 9751 OPCODE_INFO2 (0xf4001c80, 9752 OPRND_SHIFT0 (0_4, FREG), 9753 OPRND_SHIFT0 (16_20, FREG)), 9754 CSKY_ISA_FLOAT_7E60), 9755 OP32 ("fftoi.f16.u32.rz", 9756 OPCODE_INFO2 (0xf4001ca0, 9757 OPRND_SHIFT0 (0_4, FREG), 9758 OPRND_SHIFT0 (16_20, FREG)), 9759 CSKY_ISA_FLOAT_7E60), 9760 OP32 ("fhtoui.rz", 9761 OPCODE_INFO2 (0xf4001ca0, 9762 OPRND_SHIFT0 (0_4, FREG), 9763 OPRND_SHIFT0 (16_20, FREG)), 9764 CSKY_ISA_FLOAT_7E60), 9765 OP32 ("fftoi.f16.u32.rpi", 9766 OPCODE_INFO2 (0xf4001cc0, 9767 OPRND_SHIFT0 (0_4, FREG), 9768 OPRND_SHIFT0 (16_20, FREG)), 9769 CSKY_ISA_FLOAT_7E60), 9770 OP32 ("fhtoui.rpi", 9771 OPCODE_INFO2 (0xf4001cc0, 9772 OPRND_SHIFT0 (0_4, FREG), 9773 OPRND_SHIFT0 (16_20, FREG)), 9774 CSKY_ISA_FLOAT_7E60), 9775 OP32 ("fftoi.f16.u32.rni", 9776 OPCODE_INFO2 (0xf4001ce0, 9777 OPRND_SHIFT0 (0_4, FREG), 9778 OPRND_SHIFT0 (16_20, FREG)), 9779 CSKY_ISA_FLOAT_7E60), 9780 OP32 ("fhtoui.rni", 9781 OPCODE_INFO2 (0xf4001ce0, 9782 OPRND_SHIFT0 (0_4, FREG), 9783 OPRND_SHIFT0 (16_20, FREG)), 9784 CSKY_ISA_FLOAT_7E60), 9785 OP32 ("fhtos", 9786 OPCODE_INFO2 (0xf4001a40, 9787 OPRND_SHIFT0 (0_4, FREG), 9788 OPRND_SHIFT0 (16_20, FREG)), 9789 CSKY_ISA_FLOAT_7E60), 9790 OP32 ("fhtos.f16", 9791 OPCODE_INFO2 (0xf4001a40, 9792 OPRND_SHIFT0 (0_4, FREG), 9793 OPRND_SHIFT0 (16_20, FREG)), 9794 CSKY_ISA_FLOAT_7E60), 9795 OP32 ("fstoh", 9796 OPCODE_INFO2 (0xf4001a60, 9797 OPRND_SHIFT0 (0_4, FREG), 9798 OPRND_SHIFT0 (16_20, FREG)), 9799 CSKY_ISA_FLOAT_7E60), 9800 OP32 ("fstoh.f32", 9801 OPCODE_INFO2 (0xf4001a60, 9802 OPRND_SHIFT0 (0_4, FREG), 9803 OPRND_SHIFT0 (16_20, FREG)), 9804 CSKY_ISA_FLOAT_7E60), 9805 OP32 ("fdtos", 9806 OPCODE_INFO2 (0xf4001ac0, 9807 OPRND_SHIFT0 (0_4, FREG), 9808 OPRND_SHIFT0 (16_20, FREG)), 9809 CSKY_ISA_FLOAT_7E60), 9810 OP32 ("fdtos.f64", 9811 OPCODE_INFO2 (0xf4001ac0, 9812 OPRND_SHIFT0 (0_4, FREG), 9813 OPRND_SHIFT0 (16_20, FREG)), 9814 CSKY_ISA_FLOAT_7E60), 9815 OP32 ("fstod", 9816 OPCODE_INFO2 (0xf4001ae0, 9817 OPRND_SHIFT0 (0_4, FREG), 9818 OPRND_SHIFT0 (16_20, FREG)), 9819 CSKY_ISA_FLOAT_7E60), 9820 OP32 ("fmfvrh", 9821 OPCODE_INFO2 (0xf4001b00, 9822 OPRND_SHIFT0 (0_4, AREG), 9823 OPRND_SHIFT0 (16_20, FREG)), 9824 CSKY_ISA_FLOAT_7E60), 9825 OP32 ("fmfvr.32.1", 9826 OPCODE_INFO2 (0xf4001b20, 9827 OPRND_SHIFT0 (0_4, AREG), 9828 OPRND_SHIFT0 (16_20, FREG)), 9829 CSKY_ISA_FLOAT_7E60), 9830 OP32 ("fmfvrl", 9831 OPCODE_INFO2 (0xf4001b20, 9832 OPRND_SHIFT0 (0_4, AREG), 9833 OPRND_SHIFT0 (16_20, FREG)), 9834 CSKY_ISA_FLOAT_7E60), 9835 OP32 ("fmtvr.16", 9836 OPCODE_INFO2 (0xf4001fa0, 9837 OPRND_SHIFT0 (0_4, FREG), 9838 OPRND_SHIFT0 (16_20, AREG)), 9839 CSKY_ISA_FLOAT_7E60), 9840 OP32 ("fmfvr.16", 9841 OPCODE_INFO2 (0xf4001f20, 9842 OPRND_SHIFT0 (0_4, AREG), 9843 OPRND_SHIFT0 (16_20, FREG)), 9844 CSKY_ISA_FLOAT_7E60), 9845 OP32 ("fmtvrh", 9846 OPCODE_INFO2 (0xf4001b40, 9847 OPRND_SHIFT0 (0_4, FREG), 9848 OPRND_SHIFT0 (16_20, AREG)), 9849 CSKY_ISA_FLOAT_7E60), 9850 OP32 ("fmtvr.32.1", 9851 OPCODE_INFO2 (0xf4001b60, 9852 OPRND_SHIFT0 (0_4, FREG), 9853 OPRND_SHIFT0 (16_20, AREG)), 9854 CSKY_ISA_FLOAT_7E60), 9855 OP32 ("fmtvrl", 9856 OPCODE_INFO2 (0xf4001b60, 9857 OPRND_SHIFT0 (0_4, FREG), 9858 OPRND_SHIFT0 (16_20, AREG)), 9859 CSKY_ISA_FLOAT_7E60), 9860 OP32 ("fmtvr.64", 9861 OPCODE_INFO3 (0xf4001f80, 9862 OPRND_SHIFT0 (0_4, FREG), 9863 OPRND_SHIFT0 (16_20, AREG), 9864 OPRND_SHIFT0 (21_25, AREG)), 9865 CSKY_ISA_FLOAT_7E60), 9866 OP32 ("fmfvr.64", 9867 OPCODE_INFO3 (0xf4001f00, 9868 OPRND_SHIFT0 (0_4, AREG), 9869 OPRND_SHIFT0 (21_25, AREG), 9870 OPRND_SHIFT0 (16_20, FREG)), 9871 CSKY_ISA_FLOAT_7E60), 9872 OP32 ("fmtvr.32.2", 9873 OPCODE_INFO3 (0xf4001fc0, 9874 OPRND_SHIFT0 (0_4, FREG), 9875 OPRND_SHIFT0 (16_20, AREG), 9876 OPRND_SHIFT0 (21_25, AREG)), 9877 CSKY_ISA_FLOAT_7E60), 9878 OP32 ("fmfvr.32.2", 9879 OPCODE_INFO3 (0xf4001f40, 9880 OPRND_SHIFT0 (0_4, AREG), 9881 OPRND_SHIFT0 (21_25, AREG), 9882 OPRND_SHIFT0 (16_20, FREG)), 9883 CSKY_ISA_FLOAT_7E60), 9884 /* flsu. */ 9885 OP32 ("fld.16", 9886 SOPCODE_INFO2 (0xf4002300, 9887 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 9888 BRACKET_OPRND ((16_20, 9889 AREG, 9890 OPRND_SHIFT_0_BIT), 9891 (4_7or21_24, 9892 IMM_FLDST, 9893 OPRND_SHIFT_1_BIT))), 9894 CSKY_ISA_FLOAT_7E60), 9895 OP32 ("fldh", 9896 SOPCODE_INFO2 (0xf4002300, 9897 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 9898 BRACKET_OPRND ((16_20, 9899 AREG, 9900 OPRND_SHIFT_0_BIT), 9901 (4_7or21_24, 9902 IMM_FLDST, 9903 OPRND_SHIFT_1_BIT))), 9904 CSKY_ISA_FLOAT_7E60), 9905 OP32_WITH_WORK ("fst.16", 9906 SOPCODE_INFO2 (0xf4002700, 9907 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 9908 BRACKET_OPRND ((16_20, 9909 AREG, 9910 OPRND_SHIFT_0_BIT), 9911 (4_7or21_24, 9912 IMM_FLDST, 9913 OPRND_SHIFT_1_BIT))), 9914 CSKY_ISA_FLOAT_7E60, 9915 float_work_fpuv3_fstore), 9916 OP32_WITH_WORK ("fsth", 9917 SOPCODE_INFO2 (0xf4002700, 9918 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 9919 BRACKET_OPRND ((16_20, 9920 AREG, 9921 OPRND_SHIFT_0_BIT), 9922 (4_7or21_24, 9923 IMM_FLDST, 9924 OPRND_SHIFT_1_BIT))), 9925 CSKY_ISA_FLOAT_7E60, 9926 float_work_fpuv3_fstore), 9927 OP32 ("fldr16", 9928 SOPCODE_INFO2 (0xf4002b00, 9929 (0_4, FREG, OPRND_SHIFT_0_BIT), 9930 BRACKET_OPRND ((16_20, 9931 AREG, 9932 OPRND_SHIFT_0_BIT), 9933 (5_6or21_25, 9934 AREG_WITH_LSHIFT_FPU, 9935 OPRND_SHIFT_0_BIT))), 9936 CSKY_ISA_FLOAT_7E60), 9937 OP32 ("fldrh", 9938 SOPCODE_INFO2 (0xf4002b00, 9939 (0_4, FREG, OPRND_SHIFT_0_BIT), 9940 BRACKET_OPRND ((16_20, 9941 AREG, 9942 OPRND_SHIFT_0_BIT), 9943 (5_6or21_25, 9944 AREG_WITH_LSHIFT_FPU, 9945 OPRND_SHIFT_0_BIT))), 9946 CSKY_ISA_FLOAT_7E60), 9947 OP32_WITH_WORK ("fstr.16", 9948 SOPCODE_INFO2 (0xf4002f00, 9949 (0_4, FREG, OPRND_SHIFT_0_BIT), 9950 BRACKET_OPRND ((16_20, 9951 AREG, 9952 OPRND_SHIFT_0_BIT), 9953 (5_6or21_25, 9954 AREG_WITH_LSHIFT_FPU, 9955 OPRND_SHIFT_0_BIT))), 9956 CSKY_ISA_FLOAT_7E60, 9957 float_work_fpuv3_fstore), 9958 OP32_WITH_WORK ("fstrh", 9959 SOPCODE_INFO2 (0xf4002f00, 9960 (0_4, FREG, OPRND_SHIFT_0_BIT), 9961 BRACKET_OPRND ((16_20, 9962 AREG, 9963 OPRND_SHIFT_0_BIT), 9964 (5_6or21_25, 9965 AREG_WITH_LSHIFT_FPU, 9966 OPRND_SHIFT_0_BIT))), 9967 CSKY_ISA_FLOAT_7E60, 9968 float_work_fpuv3_fstore), 9969 OP32 ("fldm.16", 9970 OPCODE_INFO2 (0xf4003300, 9971 (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 9972 (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), 9973 CSKY_ISA_FLOAT_7E60), 9974 OP32 ("fldmh", 9975 OPCODE_INFO2 (0xf4003300, 9976 (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 9977 (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), 9978 CSKY_ISA_FLOAT_7E60), 9979 OP32_WITH_WORK ("fstm.16", 9980 OPCODE_INFO2 (0xf4003700, 9981 (0_4or21_24, 9982 FREGLIST_DASH, 9983 OPRND_SHIFT_0_BIT), 9984 (16_20, 9985 AREG_WITH_BRACKET, 9986 OPRND_SHIFT_0_BIT)), 9987 CSKY_ISA_FLOAT_7E60, 9988 float_work_fpuv3_fstore), 9989 OP32_WITH_WORK ("fstmh", 9990 OPCODE_INFO2 (0xf4003700, 9991 (0_4or21_24, 9992 FREGLIST_DASH, 9993 OPRND_SHIFT_0_BIT), 9994 (16_20, 9995 AREG_WITH_BRACKET, 9996 OPRND_SHIFT_0_BIT)), 9997 CSKY_ISA_FLOAT_7E60, 9998 float_work_fpuv3_fstore), 9999 OP32 ("fldmu.16", 10000 OPCODE_INFO2 (0xf4003380, 10001 OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), 10002 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10003 CSKY_ISA_FLOAT_7E60), 10004 OP32 ("fldmu.h", 10005 OPCODE_INFO2 (0xf4003380, 10006 OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), 10007 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10008 CSKY_ISA_FLOAT_7E60), 10009 OP32_WITH_WORK ("fstmu.16", 10010 OPCODE_INFO2 (0xf4003780, 10011 OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), 10012 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10013 CSKY_ISA_FLOAT_7E60, 10014 float_work_fpuv3_fstore), 10015 OP32_WITH_WORK ("fstmu.h", 10016 OPCODE_INFO2 (0xf4003780, 10017 OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), 10018 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10019 CSKY_ISA_FLOAT_7E60, 10020 float_work_fpuv3_fstore), 10021 OP32 ("fld.32", 10022 SOPCODE_INFO2 (0xf4002000, 10023 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10024 BRACKET_OPRND ((16_20, 10025 AREG, 10026 OPRND_SHIFT_0_BIT), 10027 (4_7or21_24, 10028 IMM_FLDST, 10029 OPRND_SHIFT_2_BIT))), 10030 CSKY_ISA_FLOAT_7E60), 10031 OP32 ("flds", 10032 SOPCODE_INFO2 (0xf4002000, 10033 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10034 BRACKET_OPRND ((16_20, 10035 AREG, 10036 OPRND_SHIFT_0_BIT), 10037 (4_7or21_24, 10038 IMM_FLDST, 10039 OPRND_SHIFT_2_BIT))), 10040 CSKY_ISA_FLOAT_7E60), 10041 OP32_WITH_WORK ("fst.32", 10042 SOPCODE_INFO2 (0xf4002400, 10043 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10044 BRACKET_OPRND ((16_20, 10045 AREG, 10046 OPRND_SHIFT_0_BIT), 10047 (4_7or21_24, 10048 IMM_FLDST, 10049 OPRND_SHIFT_2_BIT))), 10050 CSKY_ISA_FLOAT_7E60, 10051 float_work_fpuv3_fstore), 10052 OP32_WITH_WORK ("fsts", 10053 SOPCODE_INFO2 (0xf4002400, 10054 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10055 BRACKET_OPRND ((16_20, 10056 AREG, 10057 OPRND_SHIFT_0_BIT), 10058 (4_7or21_24, 10059 IMM_FLDST, 10060 OPRND_SHIFT_2_BIT))), 10061 CSKY_ISA_FLOAT_7E60, 10062 float_work_fpuv3_fstore), 10063 OP32 ("fldr.32", 10064 SOPCODE_INFO2 (0xf4002800, 10065 (0_4, FREG, OPRND_SHIFT_0_BIT), 10066 BRACKET_OPRND ((16_20, 10067 AREG, 10068 OPRND_SHIFT_0_BIT), 10069 (5_6or21_25, 10070 AREG_WITH_LSHIFT_FPU, 10071 OPRND_SHIFT_0_BIT))), 10072 CSKY_ISA_FLOAT_7E60), 10073 OP32 ("fldrs", 10074 SOPCODE_INFO2 (0xf4002800, 10075 (0_4, FREG, OPRND_SHIFT_0_BIT), 10076 BRACKET_OPRND ((16_20, 10077 AREG, 10078 OPRND_SHIFT_0_BIT), 10079 (5_6or21_25, 10080 AREG_WITH_LSHIFT_FPU, 10081 OPRND_SHIFT_0_BIT))), 10082 CSKY_ISA_FLOAT_7E60), 10083 OP32_WITH_WORK ("fstr.32", 10084 SOPCODE_INFO2 (0xf4002c00, 10085 (0_4, FREG, OPRND_SHIFT_0_BIT), 10086 BRACKET_OPRND ((16_20, 10087 AREG, 10088 OPRND_SHIFT_0_BIT), 10089 (5_6or21_25, 10090 AREG_WITH_LSHIFT_FPU, 10091 OPRND_SHIFT_0_BIT))), 10092 CSKY_ISA_FLOAT_7E60, 10093 float_work_fpuv3_fstore), 10094 OP32_WITH_WORK ("fstrs", 10095 SOPCODE_INFO2 (0xf4002c00, 10096 (0_4, FREG, OPRND_SHIFT_0_BIT), 10097 BRACKET_OPRND ((16_20, 10098 AREG, 10099 OPRND_SHIFT_0_BIT), 10100 (5_6or21_25, 10101 AREG_WITH_LSHIFT_FPU, 10102 OPRND_SHIFT_0_BIT))), 10103 CSKY_ISA_FLOAT_7E60, 10104 float_work_fpuv3_fstore), 10105 OP32 ("fldm.32", 10106 OPCODE_INFO2 (0xf4003000, 10107 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10108 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10109 CSKY_ISA_FLOAT_7E60), 10110 OP32 ("fldms", 10111 OPCODE_INFO2 (0xf4003000, 10112 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10113 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10114 CSKY_ISA_FLOAT_7E60), 10115 OP32_WITH_WORK ("fstm.32", 10116 OPCODE_INFO2 (0xf4003400, 10117 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10118 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10119 CSKY_ISA_FLOAT_7E60, 10120 float_work_fpuv3_fstore), 10121 OP32_WITH_WORK ("fstms", 10122 OPCODE_INFO2 (0xf4003400, 10123 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10124 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10125 CSKY_ISA_FLOAT_7E60, 10126 float_work_fpuv3_fstore), 10127 OP32 ("fldmu.32", 10128 OPCODE_INFO2 (0xf4003080, 10129 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10130 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10131 CSKY_ISA_FLOAT_7E60), 10132 OP32 ("fldmu.s", 10133 OPCODE_INFO2 (0xf4003080, 10134 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10135 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10136 CSKY_ISA_FLOAT_7E60), 10137 OP32_WITH_WORK ("fstmu.32", 10138 OPCODE_INFO2 (0xf4003480, 10139 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10140 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10141 CSKY_ISA_FLOAT_7E60, 10142 float_work_fpuv3_fstore), 10143 OP32_WITH_WORK ("fstmu.s", 10144 OPCODE_INFO2 (0xf4003480, 10145 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10146 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10147 CSKY_ISA_FLOAT_7E60, 10148 float_work_fpuv3_fstore), 10149 OP32 ("fld.64", 10150 SOPCODE_INFO2 (0xf4002100, 10151 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10152 BRACKET_OPRND ((16_20, 10153 AREG, 10154 OPRND_SHIFT_0_BIT), 10155 (4_7or21_24, 10156 IMM_FLDST, 10157 OPRND_SHIFT_2_BIT))), 10158 CSKY_ISA_FLOAT_7E60), 10159 OP32 ("fldd", 10160 SOPCODE_INFO2 (0xf4002100, 10161 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10162 BRACKET_OPRND ((16_20, 10163 AREG, 10164 OPRND_SHIFT_0_BIT), 10165 (4_7or21_24, 10166 IMM_FLDST, 10167 OPRND_SHIFT_2_BIT))), 10168 CSKY_ISA_FLOAT_7E60), 10169 OP32_WITH_WORK ("fst.64", 10170 SOPCODE_INFO2 (0xf4002500, 10171 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10172 BRACKET_OPRND ((16_20, 10173 AREG, 10174 OPRND_SHIFT_0_BIT), 10175 (4_7or21_24, 10176 IMM_FLDST, 10177 OPRND_SHIFT_2_BIT))), 10178 CSKY_ISA_FLOAT_7E60, 10179 float_work_fpuv3_fstore), 10180 OP32_WITH_WORK ("fstd", 10181 SOPCODE_INFO2 (0xf4002500, 10182 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10183 BRACKET_OPRND ((16_20, 10184 AREG, 10185 OPRND_SHIFT_0_BIT), 10186 (4_7or21_24, 10187 IMM_FLDST, 10188 OPRND_SHIFT_2_BIT))), 10189 CSKY_ISA_FLOAT_7E60, 10190 float_work_fpuv3_fstore), 10191 OP32 ("fldr.64", 10192 SOPCODE_INFO2 (0xf4002900, 10193 (0_4, FREG, OPRND_SHIFT_0_BIT), 10194 BRACKET_OPRND ((16_20, 10195 AREG, 10196 OPRND_SHIFT_0_BIT), 10197 (5_6or21_25, 10198 AREG_WITH_LSHIFT_FPU, 10199 OPRND_SHIFT_0_BIT))), 10200 CSKY_ISA_FLOAT_7E60), 10201 OP32 ("fldrd", 10202 SOPCODE_INFO2 (0xf4002900, 10203 (0_4, FREG, OPRND_SHIFT_0_BIT), 10204 BRACKET_OPRND ((16_20, 10205 AREG, 10206 OPRND_SHIFT_0_BIT), 10207 (5_6or21_25, 10208 AREG_WITH_LSHIFT_FPU, 10209 OPRND_SHIFT_0_BIT))), 10210 CSKY_ISA_FLOAT_7E60), 10211 OP32_WITH_WORK ("fstr.64", 10212 SOPCODE_INFO2 (0xf4002d00, 10213 (0_4, FREG, OPRND_SHIFT_0_BIT), 10214 BRACKET_OPRND ((16_20, 10215 AREG, 10216 OPRND_SHIFT_0_BIT), 10217 (5_6or21_25, 10218 AREG_WITH_LSHIFT_FPU, 10219 OPRND_SHIFT_0_BIT))), 10220 CSKY_ISA_FLOAT_7E60, 10221 float_work_fpuv3_fstore), 10222 OP32_WITH_WORK ("fstrd", 10223 SOPCODE_INFO2 (0xf4002d00, 10224 (0_4, FREG, OPRND_SHIFT_0_BIT), 10225 BRACKET_OPRND ((16_20, 10226 AREG, 10227 OPRND_SHIFT_0_BIT), 10228 (5_6or21_25, 10229 AREG_WITH_LSHIFT_FPU, 10230 OPRND_SHIFT_0_BIT))), 10231 CSKY_ISA_FLOAT_7E60, 10232 float_work_fpuv3_fstore), 10233 OP32 ("fldm.64", 10234 OPCODE_INFO2 (0xf4003100, 10235 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10236 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10237 CSKY_ISA_FLOAT_7E60), 10238 OP32 ("fldmd", 10239 OPCODE_INFO2 (0xf4003100, 10240 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10241 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10242 CSKY_ISA_FLOAT_7E60), 10243 OP32_WITH_WORK ("fstm.64", 10244 OPCODE_INFO2 (0xf4003500, 10245 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10246 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10247 CSKY_ISA_FLOAT_7E60, 10248 float_work_fpuv3_fstore), 10249 OP32_WITH_WORK ("fstmd", 10250 OPCODE_INFO2 (0xf4003500, 10251 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10252 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10253 CSKY_ISA_FLOAT_7E60, 10254 float_work_fpuv3_fstore), 10255 OP32 ("fldmu.64", 10256 OPCODE_INFO2 (0xf4003180, 10257 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10258 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10259 CSKY_ISA_FLOAT_7E60), 10260 OP32 ("fldmu.d", 10261 OPCODE_INFO2 (0xf4003180, 10262 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10263 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10264 CSKY_ISA_FLOAT_7E60), 10265 OP32_WITH_WORK ("fstmu.64", 10266 OPCODE_INFO2 (0xf4003580, 10267 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10268 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10269 CSKY_ISA_FLOAT_7E60, 10270 float_work_fpuv3_fstore), 10271 OP32_WITH_WORK ("fstmu.d", 10272 OPCODE_INFO2 (0xf4003580, 10273 OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), 10274 OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), 10275 CSKY_ISA_FLOAT_7E60, 10276 float_work_fpuv3_fstore), 10277 OP32 ("fldrm", 10278 SOPCODE_INFO2 (0xf4002a00, 10279 (0_4, FREG, OPRND_SHIFT_0_BIT), 10280 BRACKET_OPRND ((16_20, 10281 AREG, 10282 OPRND_SHIFT_0_BIT), 10283 (5_6or21_25, 10284 AREG_WITH_LSHIFT_FPU, 10285 OPRND_SHIFT_0_BIT))), 10286 CSKY_ISA_FLOAT_7E60), 10287 OP32_WITH_WORK ("fstrm", 10288 SOPCODE_INFO2 (0xf4002e00, 10289 (0_4, FREG, OPRND_SHIFT_0_BIT), 10290 BRACKET_OPRND ((16_20, 10291 AREG, 10292 OPRND_SHIFT_0_BIT), 10293 (5_6or21_25, 10294 AREG_WITH_LSHIFT_FPU, 10295 OPRND_SHIFT_0_BIT))), 10296 CSKY_ISA_FLOAT_7E60, 10297 float_work_fpuv3_fstore), 10298 OP32 ("fldmm", 10299 OPCODE_INFO2 (0xf4003200, 10300 (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 10301 (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), 10302 CSKY_ISA_FLOAT_7E60), 10303 OP32_WITH_WORK ("fstmm", 10304 OPCODE_INFO2 (0xf4003600, 10305 (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), 10306 (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), 10307 CSKY_ISA_FLOAT_7E60, 10308 float_work_fpuv3_fstore), 10309 OP32 ("fftox.f16.u16", 10310 OPCODE_INFO2 (0xf4004000, 10311 OPRND_SHIFT0 (0_4, FREG), 10312 OPRND_SHIFT0 (16_20, FREG)), 10313 CSKY_ISA_FLOAT_7E60), 10314 OP32 ("fftox.f16.s16", 10315 OPCODE_INFO2 (0xf4004020, 10316 OPRND_SHIFT0 (0_4, FREG), 10317 OPRND_SHIFT0 (16_20, FREG)), 10318 CSKY_ISA_FLOAT_7E60), 10319 OP32 ("fftox.f16.u32", 10320 OPCODE_INFO2 (0xf4004100, 10321 OPRND_SHIFT0 (0_4, FREG), 10322 OPRND_SHIFT0 (16_20, FREG)), 10323 CSKY_ISA_FLOAT_7E60), 10324 OP32 ("fftox.f16.s32", 10325 OPCODE_INFO2 (0xf4004120, 10326 OPRND_SHIFT0 (0_4, FREG), 10327 OPRND_SHIFT0 (16_20, FREG)), 10328 CSKY_ISA_FLOAT_7E60), 10329 OP32 ("fftox.f32.u32", 10330 OPCODE_INFO2 (0xf4004140, 10331 OPRND_SHIFT0 (0_4, FREG), 10332 OPRND_SHIFT0 (16_20, FREG)), 10333 CSKY_ISA_FLOAT_7E60), 10334 OP32 ("fftox.f32.s32", 10335 OPCODE_INFO2 (0xf4004160, 10336 OPRND_SHIFT0 (0_4, FREG), 10337 OPRND_SHIFT0 (16_20, FREG)), 10338 CSKY_ISA_FLOAT_7E60), 10339 OP32 ("fftox.f64.u32", 10340 OPCODE_INFO2 (0xf4004180, 10341 OPRND_SHIFT0 (0_4, FREG), 10342 OPRND_SHIFT0 (16_20, FREG)), 10343 CSKY_ISA_FLOAT_7E60), 10344 OP32 ("fftox.f64.s32", 10345 OPCODE_INFO2 (0xf40041a0, 10346 OPRND_SHIFT0 (0_4, FREG), 10347 OPRND_SHIFT0 (16_20, FREG)), 10348 CSKY_ISA_FLOAT_7E60), 10349 OP32 ("fxtof.u16.f16", 10350 OPCODE_INFO2 (0xf4004800, 10351 OPRND_SHIFT0 (0_4, FREG), 10352 OPRND_SHIFT0 (16_20, FREG)), 10353 CSKY_ISA_FLOAT_7E60), 10354 OP32 ("fxtof.s16.f16", 10355 OPCODE_INFO2 (0xf4004820, 10356 OPRND_SHIFT0 (0_4, FREG), 10357 OPRND_SHIFT0 (16_20, FREG)), 10358 CSKY_ISA_FLOAT_7E60), 10359 OP32 ("fxtof.u32.f16", 10360 OPCODE_INFO2 (0xf4004900, 10361 OPRND_SHIFT0 (0_4, FREG), 10362 OPRND_SHIFT0 (16_20, FREG)), 10363 CSKY_ISA_FLOAT_7E60), 10364 OP32 ("fxtof.s32.f16", 10365 OPCODE_INFO2 (0xf4004920, 10366 OPRND_SHIFT0 (0_4, FREG), 10367 OPRND_SHIFT0 (16_20, FREG)), 10368 CSKY_ISA_FLOAT_7E60), 10369 OP32 ("fxtof.u32.f32", 10370 OPCODE_INFO2 (0xf4004940, 10371 OPRND_SHIFT0 (0_4, FREG), 10372 OPRND_SHIFT0 (16_20, FREG)), 10373 CSKY_ISA_FLOAT_7E60), 10374 OP32 ("fxtof.s32.f32", 10375 OPCODE_INFO2 (0xf4004960, 10376 OPRND_SHIFT0 (0_4, FREG), 10377 OPRND_SHIFT0 (16_20, FREG)), 10378 CSKY_ISA_FLOAT_7E60), 10379 OP32 ("fxtof.u32.f64", 10380 OPCODE_INFO2 (0xf4004980, 10381 OPRND_SHIFT0 (0_4, FREG), 10382 OPRND_SHIFT0 (16_20, FREG)), 10383 CSKY_ISA_FLOAT_7E60), 10384 OP32 ("fxtof.s32.f64", 10385 OPCODE_INFO2 (0xf40049a0, 10386 OPRND_SHIFT0 (0_4, FREG), 10387 OPRND_SHIFT0 (16_20, FREG)), 10388 CSKY_ISA_FLOAT_7E60), 10389 OP32 ("fftoi.f16.s16", 10390 OPCODE_INFO2 (0xf4004220, 10391 OPRND_SHIFT0 (0_4, FREG), 10392 OPRND_SHIFT0 (16_20, FREG)), 10393 CSKY_ISA_FLOAT_7E60), 10394 OP32 ("fftoi.f16.u16", 10395 OPCODE_INFO2 (0xf4004200, 10396 OPRND_SHIFT0 (0_4, FREG), 10397 OPRND_SHIFT0 (16_20, FREG)), 10398 CSKY_ISA_FLOAT_7E60), 10399 OP32 ("fftoi.f16.s32", 10400 OPCODE_INFO2 (0xf4004320, 10401 OPRND_SHIFT0 (0_4, FREG), 10402 OPRND_SHIFT0 (16_20, FREG)), 10403 CSKY_ISA_FLOAT_7E60), 10404 OP32 ("fftoi.f16.u32", 10405 OPCODE_INFO2 (0xf4004300, 10406 OPRND_SHIFT0 (0_4, FREG), 10407 OPRND_SHIFT0 (16_20, FREG)), 10408 CSKY_ISA_FLOAT_7E60), 10409 OP32 ("fftoi.f32.s32", 10410 OPCODE_INFO2 (0xf4004360, 10411 OPRND_SHIFT0 (0_4, FREG), 10412 OPRND_SHIFT0 (16_20, FREG)), 10413 CSKY_ISA_FLOAT_7E60), 10414 OP32 ("fftoi.f32.u32", 10415 OPCODE_INFO2 (0xf4004340, 10416 OPRND_SHIFT0 (0_4, FREG), 10417 OPRND_SHIFT0 (16_20, FREG)), 10418 CSKY_ISA_FLOAT_7E60), 10419 OP32 ("fftoi.f64.s32", 10420 OPCODE_INFO2 (0xf40043a0, 10421 OPRND_SHIFT0 (0_4, FREG), 10422 OPRND_SHIFT0 (16_20, FREG)), 10423 CSKY_ISA_FLOAT_7E60), 10424 OP32 ("fftoi.f64.u32", 10425 OPCODE_INFO2 (0xf4004380, 10426 OPRND_SHIFT0 (0_4, FREG), 10427 OPRND_SHIFT0 (16_20, FREG)), 10428 CSKY_ISA_FLOAT_7E60), 10429 OP32 ("fitof.s16.f16", 10430 OPCODE_INFO2 (0xf4004a20, 10431 OPRND_SHIFT0 (0_4, FREG), 10432 OPRND_SHIFT0 (16_20, FREG)), 10433 CSKY_ISA_FLOAT_7E60), 10434 OP32 ("fitof.u16.f16", 10435 OPCODE_INFO2 (0xf4004a00, 10436 OPRND_SHIFT0 (0_4, FREG), 10437 OPRND_SHIFT0 (16_20, FREG)), 10438 CSKY_ISA_FLOAT_7E60), 10439 OP32 ("fitof.s32.f16", 10440 OPCODE_INFO2 (0xf4004b20, 10441 OPRND_SHIFT0 (0_4, FREG), 10442 OPRND_SHIFT0 (16_20, FREG)), 10443 CSKY_ISA_FLOAT_7E60), 10444 OP32 ("fitof.u32.f16", 10445 OPCODE_INFO2 (0xf4004b00, 10446 OPRND_SHIFT0 (0_4, FREG), 10447 OPRND_SHIFT0 (16_20, FREG)), 10448 CSKY_ISA_FLOAT_7E60), 10449 OP32 ("fitof.s32.f32", 10450 OPCODE_INFO2 (0xf4004b60, 10451 OPRND_SHIFT0 (0_4, FREG), 10452 OPRND_SHIFT0 (16_20, FREG)), 10453 CSKY_ISA_FLOAT_7E60), 10454 OP32 ("fsitos", 10455 OPCODE_INFO2 (0xf4004b60, 10456 OPRND_SHIFT0 (0_4, FREG), 10457 OPRND_SHIFT0 (16_20, FREG)), 10458 CSKY_ISA_FLOAT_7E60), 10459 OP32 ("fitof.u32.f32", 10460 OPCODE_INFO2 (0xf4004b40, 10461 OPRND_SHIFT0 (0_4, FREG), 10462 OPRND_SHIFT0 (16_20, FREG)), 10463 CSKY_ISA_FLOAT_7E60), 10464 OP32 ("fuitos", 10465 OPCODE_INFO2 (0xf4004b40, 10466 OPRND_SHIFT0 (0_4, FREG), 10467 OPRND_SHIFT0 (16_20, FREG)), 10468 CSKY_ISA_FLOAT_7E60), 10469 OP32 ("fitof.s32.f64", 10470 OPCODE_INFO2 (0xf4004ba0, 10471 OPRND_SHIFT0 (0_4, FREG), 10472 OPRND_SHIFT0 (16_20, FREG)), 10473 CSKY_ISA_FLOAT_7E60), 10474 OP32 ("fsitod", 10475 OPCODE_INFO2 (0xf4004ba0, 10476 OPRND_SHIFT0 (0_4, FREG), 10477 OPRND_SHIFT0 (16_20, FREG)), 10478 CSKY_ISA_FLOAT_7E60), 10479 OP32 ("fitof.u32.f64", 10480 OPCODE_INFO2 (0xf4004b80, 10481 OPRND_SHIFT0 (0_4, FREG), 10482 OPRND_SHIFT0 (16_20, FREG)), 10483 CSKY_ISA_FLOAT_7E60), 10484 OP32 ("fuitod", 10485 OPCODE_INFO2 (0xf4004b80, 10486 OPRND_SHIFT0 (0_4, FREG), 10487 OPRND_SHIFT0 (16_20, FREG)), 10488 CSKY_ISA_FLOAT_7E60), 10489 OP32 ("fftofi.f16.rn", 10490 OPCODE_INFO2 (0xf4004400, 10491 OPRND_SHIFT0 (0_4, FREG), 10492 OPRND_SHIFT0 (16_20, FREG)), 10493 CSKY_ISA_FLOAT_7E60), 10494 OP32 ("fftofi.f16.rz", 10495 OPCODE_INFO2 (0xf4004420, 10496 OPRND_SHIFT0 (0_4, FREG), 10497 OPRND_SHIFT0 (16_20, FREG)), 10498 CSKY_ISA_FLOAT_7E60), 10499 OP32 ("fftofi.f16.rpi", 10500 OPCODE_INFO2 (0xf4004440, 10501 OPRND_SHIFT0 (0_4, FREG), 10502 OPRND_SHIFT0 (16_20, FREG)), 10503 CSKY_ISA_FLOAT_7E60), 10504 OP32 ("fftofi.f16.rni", 10505 OPCODE_INFO2 (0xf4004460, 10506 OPRND_SHIFT0 (0_4, FREG), 10507 OPRND_SHIFT0 (16_20, FREG)), 10508 CSKY_ISA_FLOAT_7E60), 10509 OP32 ("fftofi.f32.rn", 10510 OPCODE_INFO2 (0xf4004480, 10511 OPRND_SHIFT0 (0_4, FREG), 10512 OPRND_SHIFT0 (16_20, FREG)), 10513 CSKY_ISA_FLOAT_7E60), 10514 OP32 ("fftofi.f32.rz", 10515 OPCODE_INFO2 (0xf40044a0, 10516 OPRND_SHIFT0 (0_4, FREG), 10517 OPRND_SHIFT0 (16_20, FREG)), 10518 CSKY_ISA_FLOAT_7E60), 10519 OP32 ("fftofi.f32.rpi", 10520 OPCODE_INFO2 (0xf40044c0, 10521 OPRND_SHIFT0 (0_4, FREG), 10522 OPRND_SHIFT0 (16_20, FREG)), 10523 CSKY_ISA_FLOAT_7E60), 10524 OP32 ("fftofi.f32.rni", 10525 OPCODE_INFO2 (0xf40044e0, 10526 OPRND_SHIFT0 (0_4, FREG), 10527 OPRND_SHIFT0 (16_20, FREG)), 10528 CSKY_ISA_FLOAT_7E60), 10529 OP32 ("fftofi.f64.rn", 10530 OPCODE_INFO2 (0xf4004500, 10531 OPRND_SHIFT0 (0_4, FREG), 10532 OPRND_SHIFT0 (16_20, FREG)), 10533 CSKY_ISA_FLOAT_7E60), 10534 OP32 ("fftofi.f64.rz", 10535 OPCODE_INFO2 (0xf4004520, 10536 OPRND_SHIFT0 (0_4, FREG), 10537 OPRND_SHIFT0 (16_20, FREG)), 10538 CSKY_ISA_FLOAT_7E60), 10539 OP32 ("fftofi.f64.rpi", 10540 OPCODE_INFO2 (0xf4004540, 10541 OPRND_SHIFT0 (0_4, FREG), 10542 OPRND_SHIFT0 (16_20, FREG)), 10543 CSKY_ISA_FLOAT_7E60), 10544 OP32 ("fftofi.f64.rni", 10545 OPCODE_INFO2 (0xf4004560, 10546 OPRND_SHIFT0 (0_4, FREG), 10547 OPRND_SHIFT0 (16_20, FREG)), 10548 CSKY_ISA_FLOAT_7E60), 10549 DOP32_WITH_WORK ("fmovi.16", 10550 OPCODE_INFO2 (0xf400e400, 10551 OPRND_SHIFT0 (0_4, FREG), 10552 OPRND_SHIFT0 (5or8_9or16_25, HFLOAT_FMOVI)), 10553 OPCODE_INFO3 (0xf400e400, 10554 OPRND_SHIFT0 (0_4, FREG), 10555 OPRND_SHIFT0 (5or8_9or20_25, IMM9b), 10556 OPRND_SHIFT0 (16_19, IMM4b)), 10557 CSKY_ISA_FLOAT_7E60, 10558 float_work_fpuv3_fmovi), 10559 DOP32_WITH_WORK ("fmovi.32", 10560 OPCODE_INFO2 (0xf400e440, 10561 OPRND_SHIFT0 (0_4, FREG), 10562 OPRND_SHIFT0 (5or8_9or16_25, SFLOAT_FMOVI)), 10563 OPCODE_INFO3 (0xf400e440, 10564 OPRND_SHIFT0 (0_4, FREG), 10565 OPRND_SHIFT0 (5or8_9or20_25, IMM9b), 10566 OPRND_SHIFT0 (16_19, IMM4b)), 10567 CSKY_ISA_FLOAT_7E60, 10568 float_work_fpuv3_fmovi), 10569 DOP32_WITH_WORK ("fmovi.64", 10570 OPCODE_INFO2 (0xf400e480, 10571 OPRND_SHIFT0 (0_4, FREG), 10572 OPRND_SHIFT0 (5or8_9or16_25, DFLOAT_FMOVI)), 10573 OPCODE_INFO3 (0xf400e480, 10574 OPRND_SHIFT0 (0_4, FREG), 10575 OPRND_SHIFT0 (5or8_9or20_25, IMM9b), 10576 OPRND_SHIFT0 (16_19, IMM4b)), 10577 CSKY_ISA_FLOAT_7E60, 10578 float_work_fpuv3_fmovi), 10579 #undef _RELOC32 10580 #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 10581 OP32 ("flrw.32", 10582 OPCODE_INFO2 (0xf4003800, 10583 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10584 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 10585 CSKY_ISA_FLOAT_7E60), 10586 OP32 ("flrws", 10587 OPCODE_INFO2 (0xf4003800, 10588 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10589 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 10590 CSKY_ISA_FLOAT_7E60), 10591 OP32 ("flrw.64", 10592 OPCODE_INFO2 (0xf4003900, 10593 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10594 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 10595 CSKY_ISA_FLOAT_7E60), 10596 OP32 ("flrwd", 10597 OPCODE_INFO2 (0xf4003900, 10598 (0_3or25, FREG, OPRND_SHIFT_0_BIT), 10599 (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), 10600 CSKY_ISA_FLOAT_7E60), 10601 #undef _RELOC32 10602 #define _RELOC32 0 10603 10604 /* The following are aliases for other instructions. */ 10605 /* setc -> cmphs r0, r0 */ 10606 OP16 ("setc", 10607 OPCODE_INFO0 (0x6400), 10608 CSKYV2_ISA_E1), 10609 /* clrc -> cmpne r0, r0 */ 10610 OP16 ("clrc", 10611 OPCODE_INFO0 (0x6402), 10612 CSKYV2_ISA_E1), 10613 /* tstlt rd -> btsti rd,31 */ 10614 OP32 ("tstlt", 10615 OPCODE_INFO1 (0xc7e02880, 10616 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10617 CSKYV2_ISA_1E2), 10618 /* idly4 -> idly 4 */ 10619 OP32 ("idly4", 10620 OPCODE_INFO0 (0xc0601c20), 10621 CSKYV2_ISA_E1), 10622 /* rsub rz, ry, rx -> subu rz, rx, ry */ 10623 DOP32 ("rsub", 10624 OPCODE_INFO3 (0xc4000080, 10625 (0_4, AREG, OPRND_SHIFT_0_BIT), 10626 (21_25, AREG, OPRND_SHIFT_0_BIT), 10627 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10628 OPCODE_INFO2 (0xc4000080, 10629 (0_4or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), 10630 (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKYV2_ISA_1E2), 10631 /* cmplei rd,X -> cmplti rd,X+1 */ 10632 OP16_OP32 ("cmplei", 10633 OPCODE_INFO2 (0x3820, 10634 (8_10, GREG0_7, OPRND_SHIFT_0_BIT), 10635 (0_4, IMM5b, OPRND_SHIFT_0_BIT)), 10636 CSKYV2_ISA_E1, 10637 OPCODE_INFO2 (0xeb200000, 10638 (16_20, AREG, OPRND_SHIFT_0_BIT), 10639 (0_15, IMM16b, OPRND_SHIFT_0_BIT)), 10640 CSKYV2_ISA_1E2), 10641 /* cmpls -> cmphs */ 10642 OP16_OP32 ("cmpls", 10643 OPCODE_INFO2 (0x6400, 10644 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 10645 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 10646 CSKYV2_ISA_E1, 10647 OPCODE_INFO2 (0xc4000420, 10648 (21_25, AREG, OPRND_SHIFT_0_BIT), 10649 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10650 CSKYV2_ISA_2E3), 10651 /* cmpgt -> cmplt */ 10652 OP16_OP32 ("cmpgt", 10653 OPCODE_INFO2 (0x6401, 10654 (6_9, GREG0_15, OPRND_SHIFT_0_BIT), 10655 (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), 10656 CSKYV2_ISA_E1, 10657 OPCODE_INFO2 (0xc4000440, 10658 (21_25, AREG, OPRND_SHIFT_0_BIT), 10659 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10660 CSKYV2_ISA_2E3), 10661 /* tstle rd -> cmplti rd,1 */ 10662 OP16_OP32 ("tstle", 10663 OPCODE_INFO1 (0x3820, 10664 (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), 10665 CSKYV2_ISA_E1, 10666 OPCODE_INFO1 (0xeb200000, 10667 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10668 CSKYV2_ISA_1E2), 10669 /* tstne rd -> cmpnei rd,0 */ 10670 OP16_OP32 ("tstne", 10671 OPCODE_INFO1 (0x3840, 10672 (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), 10673 CSKYV2_ISA_E1, 10674 OPCODE_INFO1 (0xeb400000, 10675 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10676 CSKYV2_ISA_1E2), 10677 /* rotri rz, rx, imm5 -> rotli rz, rx, 32-imm5 */ 10678 DOP32 ("rotri", 10679 OPCODE_INFO3 (0xc4004900, 10680 (0_4, AREG, OPRND_SHIFT_0_BIT), 10681 (16_20, AREG, OPRND_SHIFT_0_BIT), 10682 (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 10683 OPCODE_INFO2 (0xc4004900, 10684 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 10685 (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 10686 CSKYV2_ISA_2E3), 10687 DOP32 ("rori", 10688 OPCODE_INFO3 (0xc4004900, 10689 (0_4, AREG, OPRND_SHIFT_0_BIT), 10690 (16_20, AREG, OPRND_SHIFT_0_BIT), 10691 (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 10692 OPCODE_INFO2 (0xc4004900, 10693 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), 10694 (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), 10695 CSKYV2_ISA_2E3), 10696 10697 /* rotlc rd -> addc rd, rd/ addc rd, rd, rd */ 10698 OP16_OP32_WITH_WORK ("rotlc", 10699 OPCODE_INFO2 (0x6001, 10700 (NONE, GREG0_15, OPRND_SHIFT_0_BIT), 10701 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 10702 CSKYV2_ISA_E1, 10703 OPCODE_INFO2 (0xc4000040, 10704 (NONE, AREG, OPRND_SHIFT_0_BIT), 10705 (NONE, CONST1, OPRND_SHIFT_0_BIT)), 10706 CSKYV2_ISA_2E3, 10707 v2_work_rotlc), 10708 /* not rd -> nor rd, rd, not rz, rx -> nor rz, rx, rx */ 10709 OP16_OP32_WITH_WORK ("not", 10710 OPCODE_INFO1 (0x6c02, 10711 (NONE, AREG, OPRND_SHIFT_0_BIT)), 10712 CSKYV2_ISA_E1, 10713 OPCODE_INFO2 (0xc4002480, 10714 (NONE, AREG, OPRND_SHIFT_0_BIT), 10715 (NONE, AREG, OPRND_SHIFT_0_BIT)), 10716 CSKYV2_ISA_E1, v2_work_not), 10717 10718 /* Special force 32 bits instruction. */ 10719 OP32 ("xtrb0.32", 10720 OPCODE_INFO2 (0xc4007020, 10721 (0_4, AREG, OPRND_SHIFT_0_BIT), 10722 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10723 CSKYV2_ISA_1E2), 10724 OP32 ("xtrb1.32", 10725 OPCODE_INFO2 (0xc4007040, 10726 (0_4, AREG, OPRND_SHIFT_0_BIT), 10727 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10728 CSKYV2_ISA_1E2), 10729 OP32 ("xtrb2.32", 10730 OPCODE_INFO2 (0xc4007080, 10731 (0_4, AREG, OPRND_SHIFT_0_BIT), 10732 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10733 CSKYV2_ISA_1E2), 10734 OP32 ("xtrb3.32", 10735 OPCODE_INFO2 (0xc4007100, 10736 (0_4, AREG, OPRND_SHIFT_0_BIT), 10737 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10738 CSKYV2_ISA_1E2), 10739 OP32 ("ff0.32", 10740 OPCODE_INFO2 (0xc4007c20, 10741 (0_4, AREG, OPRND_SHIFT_0_BIT), 10742 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10743 CSKYV2_ISA_1E2), 10744 DOP32 ("ff1.32", 10745 OPCODE_INFO2 (0xc4007c40, 10746 (0_4, AREG, OPRND_SHIFT_0_BIT), 10747 (16_20, AREG, OPRND_SHIFT_0_BIT)), 10748 OPCODE_INFO1 (0xc4007c40, 10749 (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), 10750 CSKYV2_ISA_1E2), 10751 10752 {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} 10753 }; 10754