1 /* GNU/Linux/x86-64 specific low level interface, for the remote server 2 for GDB. 3 Copyright (C) 2002-2024 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include <signal.h> 21 #include <limits.h> 22 #include <inttypes.h> 23 #include "linux-low.h" 24 #include "i387-fp.h" 25 #include "x86-low.h" 26 #include "gdbsupport/x86-xstate.h" 27 #include "nat/x86-xstate.h" 28 #include "nat/gdb_ptrace.h" 29 30 #ifdef __x86_64__ 31 #include "nat/amd64-linux-siginfo.h" 32 #endif 33 34 #include "gdb_proc_service.h" 35 /* Don't include elf/common.h if linux/elf.h got included by 36 gdb_proc_service.h. */ 37 #ifndef ELFMAG0 38 #include "elf/common.h" 39 #endif 40 41 #include "gdbsupport/agent.h" 42 #include "tdesc.h" 43 #include "tracepoint.h" 44 #include "ax.h" 45 #include "nat/linux-nat.h" 46 #include "nat/x86-linux.h" 47 #include "nat/x86-linux-dregs.h" 48 #include "linux-x86-tdesc.h" 49 50 #ifdef __x86_64__ 51 static target_desc_up tdesc_amd64_linux_no_xml; 52 #endif 53 static target_desc_up tdesc_i386_linux_no_xml; 54 55 56 static unsigned char jump_insn[] = { 0xe9, 0, 0, 0, 0 }; 57 static unsigned char small_jump_insn[] = { 0x66, 0xe9, 0, 0 }; 58 59 /* Backward compatibility for gdb without XML support. */ 60 61 static const char xmltarget_i386_linux_no_xml[] = "@<target>\ 62 <architecture>i386</architecture>\ 63 <osabi>GNU/Linux</osabi>\ 64 </target>"; 65 66 #ifdef __x86_64__ 67 static const char xmltarget_amd64_linux_no_xml[] = "@<target>\ 68 <architecture>i386:x86-64</architecture>\ 69 <osabi>GNU/Linux</osabi>\ 70 </target>"; 71 #endif 72 73 #include <sys/reg.h> 74 #include <sys/procfs.h> 75 #include <sys/uio.h> 76 77 #ifndef PTRACE_GET_THREAD_AREA 78 #define PTRACE_GET_THREAD_AREA 25 79 #endif 80 81 /* This definition comes from prctl.h, but some kernels may not have it. */ 82 #ifndef PTRACE_ARCH_PRCTL 83 #define PTRACE_ARCH_PRCTL 30 84 #endif 85 86 /* The following definitions come from prctl.h, but may be absent 87 for certain configurations. */ 88 #ifndef ARCH_GET_FS 89 #define ARCH_SET_GS 0x1001 90 #define ARCH_SET_FS 0x1002 91 #define ARCH_GET_FS 0x1003 92 #define ARCH_GET_GS 0x1004 93 #endif 94 95 /* Linux target op definitions for the x86 architecture. 96 This is initialized assuming an amd64 target. 97 'low_arch_setup' will correct it for i386 or amd64 targets. */ 98 99 class x86_target : public linux_process_target 100 { 101 public: 102 103 const regs_info *get_regs_info () override; 104 105 const gdb_byte *sw_breakpoint_from_kind (int kind, int *size) override; 106 107 bool supports_z_point_type (char z_type) override; 108 109 void process_qsupported (gdb::array_view<const char * const> features) override; 110 111 bool supports_tracepoints () override; 112 113 bool supports_fast_tracepoints () override; 114 115 int install_fast_tracepoint_jump_pad 116 (CORE_ADDR tpoint, CORE_ADDR tpaddr, CORE_ADDR collector, 117 CORE_ADDR lockaddr, ULONGEST orig_size, CORE_ADDR *jump_entry, 118 CORE_ADDR *trampoline, ULONGEST *trampoline_size, 119 unsigned char *jjump_pad_insn, ULONGEST *jjump_pad_insn_size, 120 CORE_ADDR *adjusted_insn_addr, CORE_ADDR *adjusted_insn_addr_end, 121 char *err) override; 122 123 int get_min_fast_tracepoint_insn_len () override; 124 125 struct emit_ops *emit_ops () override; 126 127 int get_ipa_tdesc_idx () override; 128 129 protected: 130 131 void low_arch_setup () override; 132 133 bool low_cannot_fetch_register (int regno) override; 134 135 bool low_cannot_store_register (int regno) override; 136 137 bool low_supports_breakpoints () override; 138 139 CORE_ADDR low_get_pc (regcache *regcache) override; 140 141 void low_set_pc (regcache *regcache, CORE_ADDR newpc) override; 142 143 int low_decr_pc_after_break () override; 144 145 bool low_breakpoint_at (CORE_ADDR pc) override; 146 147 int low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 148 int size, raw_breakpoint *bp) override; 149 150 int low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 151 int size, raw_breakpoint *bp) override; 152 153 bool low_stopped_by_watchpoint () override; 154 155 CORE_ADDR low_stopped_data_address () override; 156 157 /* collect_ptrace_register/supply_ptrace_register are not needed in the 158 native i386 case (no registers smaller than an xfer unit), and are not 159 used in the biarch case (HAVE_LINUX_USRREGS is not defined). */ 160 161 /* Need to fix up i386 siginfo if host is amd64. */ 162 bool low_siginfo_fixup (siginfo_t *native, gdb_byte *inf, 163 int direction) override; 164 165 arch_process_info *low_new_process () override; 166 167 void low_delete_process (arch_process_info *info) override; 168 169 void low_new_thread (lwp_info *) override; 170 171 void low_delete_thread (arch_lwp_info *) override; 172 173 void low_new_fork (process_info *parent, process_info *child) override; 174 175 void low_prepare_to_resume (lwp_info *lwp) override; 176 177 int low_get_thread_area (int lwpid, CORE_ADDR *addrp) override; 178 179 bool low_supports_range_stepping () override; 180 181 bool low_supports_catch_syscall () override; 182 183 void low_get_syscall_trapinfo (regcache *regcache, int *sysno) override; 184 185 private: 186 187 /* Update all the target description of all processes; a new GDB 188 connected, and it may or not support xml target descriptions. */ 189 void update_xmltarget (); 190 }; 191 192 /* The singleton target ops object. */ 193 194 static x86_target the_x86_target; 195 196 /* Per-process arch-specific data we want to keep. */ 197 198 struct arch_process_info 199 { 200 struct x86_debug_reg_state debug_reg_state; 201 }; 202 203 #ifdef __x86_64__ 204 205 /* Mapping between the general-purpose registers in `struct user' 206 format and GDB's register array layout. 207 Note that the transfer layout uses 64-bit regs. */ 208 static /*const*/ int i386_regmap[] = 209 { 210 RAX * 8, RCX * 8, RDX * 8, RBX * 8, 211 RSP * 8, RBP * 8, RSI * 8, RDI * 8, 212 RIP * 8, EFLAGS * 8, CS * 8, SS * 8, 213 DS * 8, ES * 8, FS * 8, GS * 8 214 }; 215 216 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) 217 218 /* So code below doesn't have to care, i386 or amd64. */ 219 #define ORIG_EAX ORIG_RAX 220 #define REGSIZE 8 221 222 static const int x86_64_regmap[] = 223 { 224 RAX * 8, RBX * 8, RCX * 8, RDX * 8, 225 RSI * 8, RDI * 8, RBP * 8, RSP * 8, 226 R8 * 8, R9 * 8, R10 * 8, R11 * 8, 227 R12 * 8, R13 * 8, R14 * 8, R15 * 8, 228 RIP * 8, EFLAGS * 8, CS * 8, SS * 8, 229 DS * 8, ES * 8, FS * 8, GS * 8, 230 -1, -1, -1, -1, -1, -1, -1, -1, 231 -1, -1, -1, -1, -1, -1, -1, -1, 232 -1, -1, -1, -1, -1, -1, -1, -1, 233 -1, 234 -1, -1, -1, -1, -1, -1, -1, -1, 235 ORIG_RAX * 8, 236 21 * 8, 22 * 8, 237 -1, -1, -1, -1, /* MPX registers BND0 ... BND3. */ 238 -1, -1, /* MPX registers BNDCFGU, BNDSTATUS. */ 239 -1, -1, -1, -1, -1, -1, -1, -1, /* xmm16 ... xmm31 (AVX512) */ 240 -1, -1, -1, -1, -1, -1, -1, -1, 241 -1, -1, -1, -1, -1, -1, -1, -1, /* ymm16 ... ymm31 (AVX512) */ 242 -1, -1, -1, -1, -1, -1, -1, -1, 243 -1, -1, -1, -1, -1, -1, -1, -1, /* k0 ... k7 (AVX512) */ 244 -1, -1, -1, -1, -1, -1, -1, -1, /* zmm0 ... zmm31 (AVX512) */ 245 -1, -1, -1, -1, -1, -1, -1, -1, 246 -1, -1, -1, -1, -1, -1, -1, -1, 247 -1, -1, -1, -1, -1, -1, -1, -1, 248 -1 /* pkru */ 249 }; 250 251 #define X86_64_NUM_REGS (sizeof (x86_64_regmap) / sizeof (x86_64_regmap[0])) 252 #define X86_64_USER_REGS (GS + 1) 253 254 #else /* ! __x86_64__ */ 255 256 /* Mapping between the general-purpose registers in `struct user' 257 format and GDB's register array layout. */ 258 static /*const*/ int i386_regmap[] = 259 { 260 EAX * 4, ECX * 4, EDX * 4, EBX * 4, 261 UESP * 4, EBP * 4, ESI * 4, EDI * 4, 262 EIP * 4, EFL * 4, CS * 4, SS * 4, 263 DS * 4, ES * 4, FS * 4, GS * 4 264 }; 265 266 #define I386_NUM_REGS (sizeof (i386_regmap) / sizeof (i386_regmap[0])) 267 268 #define REGSIZE 4 269 270 #endif 271 272 #ifdef __x86_64__ 273 274 /* Returns true if THREAD belongs to a x86-64 process, per the tdesc. */ 275 276 static int 277 is_64bit_tdesc (thread_info *thread) 278 { 279 struct regcache *regcache = get_thread_regcache (thread, 0); 280 281 return register_size (regcache->tdesc, 0) == 8; 282 } 283 284 #endif 285 286 287 /* Called by libthread_db. */ 288 289 ps_err_e 290 ps_get_thread_area (struct ps_prochandle *ph, 291 lwpid_t lwpid, int idx, void **base) 292 { 293 #ifdef __x86_64__ 294 lwp_info *lwp = find_lwp_pid (ptid_t (lwpid)); 295 gdb_assert (lwp != nullptr); 296 int use_64bit = is_64bit_tdesc (get_lwp_thread (lwp)); 297 298 if (use_64bit) 299 { 300 switch (idx) 301 { 302 case FS: 303 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_FS) == 0) 304 return PS_OK; 305 break; 306 case GS: 307 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, base, ARCH_GET_GS) == 0) 308 return PS_OK; 309 break; 310 default: 311 return PS_BADADDR; 312 } 313 return PS_ERR; 314 } 315 #endif 316 317 { 318 unsigned int desc[4]; 319 320 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, 321 (void *) (intptr_t) idx, (unsigned long) &desc) < 0) 322 return PS_ERR; 323 324 /* Ensure we properly extend the value to 64-bits for x86_64. */ 325 *base = (void *) (uintptr_t) desc[1]; 326 return PS_OK; 327 } 328 } 329 330 /* Get the thread area address. This is used to recognize which 331 thread is which when tracing with the in-process agent library. We 332 don't read anything from the address, and treat it as opaque; it's 333 the address itself that we assume is unique per-thread. */ 334 335 int 336 x86_target::low_get_thread_area (int lwpid, CORE_ADDR *addr) 337 { 338 lwp_info *lwp = find_lwp_pid (ptid_t (lwpid)); 339 gdb_assert (lwp != nullptr); 340 #ifdef __x86_64__ 341 int use_64bit = is_64bit_tdesc (get_lwp_thread (lwp)); 342 343 if (use_64bit) 344 { 345 void *base; 346 if (ptrace (PTRACE_ARCH_PRCTL, lwpid, &base, ARCH_GET_FS) == 0) 347 { 348 *addr = (CORE_ADDR) (uintptr_t) base; 349 return 0; 350 } 351 352 return -1; 353 } 354 #endif 355 356 { 357 struct thread_info *thr = get_lwp_thread (lwp); 358 struct regcache *regcache = get_thread_regcache (thr, 1); 359 unsigned int desc[4]; 360 ULONGEST gs = 0; 361 const int reg_thread_area = 3; /* bits to scale down register value. */ 362 int idx; 363 364 collect_register_by_name (regcache, "gs", &gs); 365 366 idx = gs >> reg_thread_area; 367 368 if (ptrace (PTRACE_GET_THREAD_AREA, 369 lwpid_of (thr), 370 (void *) (long) idx, (unsigned long) &desc) < 0) 371 return -1; 372 373 *addr = desc[1]; 374 return 0; 375 } 376 } 377 378 379 380 bool 381 x86_target::low_cannot_store_register (int regno) 382 { 383 #ifdef __x86_64__ 384 if (is_64bit_tdesc (current_thread)) 385 return false; 386 #endif 387 388 return regno >= I386_NUM_REGS; 389 } 390 391 bool 392 x86_target::low_cannot_fetch_register (int regno) 393 { 394 #ifdef __x86_64__ 395 if (is_64bit_tdesc (current_thread)) 396 return false; 397 #endif 398 399 return regno >= I386_NUM_REGS; 400 } 401 402 static void 403 collect_register_i386 (struct regcache *regcache, int regno, void *buf) 404 { 405 collect_register (regcache, regno, buf); 406 407 #ifdef __x86_64__ 408 /* In case of x86_64 -m32, collect_register only writes 4 bytes, but the 409 space reserved in buf for the register is 8 bytes. Make sure the entire 410 reserved space is initialized. */ 411 412 gdb_assert (register_size (regcache->tdesc, regno) == 4); 413 414 if (regno == RAX) 415 { 416 /* Sign extend EAX value to avoid potential syscall restart 417 problems. 418 419 See amd64_linux_collect_native_gregset() in 420 gdb/amd64-linux-nat.c for a detailed explanation. */ 421 *(int64_t *) buf = *(int32_t *) buf; 422 } 423 else 424 { 425 /* Zero-extend. */ 426 *(uint64_t *) buf = *(uint32_t *) buf; 427 } 428 #endif 429 } 430 431 static void 432 x86_fill_gregset (struct regcache *regcache, void *buf) 433 { 434 int i; 435 436 #ifdef __x86_64__ 437 if (register_size (regcache->tdesc, 0) == 8) 438 { 439 for (i = 0; i < X86_64_NUM_REGS; i++) 440 if (x86_64_regmap[i] != -1) 441 collect_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); 442 443 return; 444 } 445 #endif 446 447 for (i = 0; i < I386_NUM_REGS; i++) 448 collect_register_i386 (regcache, i, ((char *) buf) + i386_regmap[i]); 449 450 /* Handle ORIG_EAX, which is not in i386_regmap. */ 451 collect_register_i386 (regcache, find_regno (regcache->tdesc, "orig_eax"), 452 ((char *) buf) + ORIG_EAX * REGSIZE); 453 } 454 455 static void 456 x86_store_gregset (struct regcache *regcache, const void *buf) 457 { 458 int i; 459 460 #ifdef __x86_64__ 461 if (register_size (regcache->tdesc, 0) == 8) 462 { 463 for (i = 0; i < X86_64_NUM_REGS; i++) 464 if (x86_64_regmap[i] != -1) 465 supply_register (regcache, i, ((char *) buf) + x86_64_regmap[i]); 466 467 return; 468 } 469 #endif 470 471 for (i = 0; i < I386_NUM_REGS; i++) 472 supply_register (regcache, i, ((char *) buf) + i386_regmap[i]); 473 474 supply_register_by_name (regcache, "orig_eax", 475 ((char *) buf) + ORIG_EAX * REGSIZE); 476 } 477 478 static void 479 x86_fill_fpregset (struct regcache *regcache, void *buf) 480 { 481 #ifdef __x86_64__ 482 i387_cache_to_fxsave (regcache, buf); 483 #else 484 i387_cache_to_fsave (regcache, buf); 485 #endif 486 } 487 488 static void 489 x86_store_fpregset (struct regcache *regcache, const void *buf) 490 { 491 #ifdef __x86_64__ 492 i387_fxsave_to_cache (regcache, buf); 493 #else 494 i387_fsave_to_cache (regcache, buf); 495 #endif 496 } 497 498 #ifndef __x86_64__ 499 500 static void 501 x86_fill_fpxregset (struct regcache *regcache, void *buf) 502 { 503 i387_cache_to_fxsave (regcache, buf); 504 } 505 506 static void 507 x86_store_fpxregset (struct regcache *regcache, const void *buf) 508 { 509 i387_fxsave_to_cache (regcache, buf); 510 } 511 512 #endif 513 514 static void 515 x86_fill_xstateregset (struct regcache *regcache, void *buf) 516 { 517 i387_cache_to_xsave (regcache, buf); 518 } 519 520 static void 521 x86_store_xstateregset (struct regcache *regcache, const void *buf) 522 { 523 i387_xsave_to_cache (regcache, buf); 524 } 525 526 /* ??? The non-biarch i386 case stores all the i387 regs twice. 527 Once in i387_.*fsave.* and once in i387_.*fxsave.*. 528 This is, presumably, to handle the case where PTRACE_[GS]ETFPXREGS 529 doesn't work. IWBN to avoid the duplication in the case where it 530 does work. Maybe the arch_setup routine could check whether it works 531 and update the supported regsets accordingly. */ 532 533 static struct regset_info x86_regsets[] = 534 { 535 #ifdef HAVE_PTRACE_GETREGS 536 { PTRACE_GETREGS, PTRACE_SETREGS, 0, sizeof (elf_gregset_t), 537 GENERAL_REGS, 538 x86_fill_gregset, x86_store_gregset }, 539 { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_X86_XSTATE, 0, 540 EXTENDED_REGS, x86_fill_xstateregset, x86_store_xstateregset }, 541 # ifndef __x86_64__ 542 # ifdef HAVE_PTRACE_GETFPXREGS 543 { PTRACE_GETFPXREGS, PTRACE_SETFPXREGS, 0, sizeof (elf_fpxregset_t), 544 EXTENDED_REGS, 545 x86_fill_fpxregset, x86_store_fpxregset }, 546 # endif 547 # endif 548 { PTRACE_GETFPREGS, PTRACE_SETFPREGS, 0, sizeof (elf_fpregset_t), 549 FP_REGS, 550 x86_fill_fpregset, x86_store_fpregset }, 551 #endif /* HAVE_PTRACE_GETREGS */ 552 NULL_REGSET 553 }; 554 555 bool 556 x86_target::low_supports_breakpoints () 557 { 558 return true; 559 } 560 561 CORE_ADDR 562 x86_target::low_get_pc (regcache *regcache) 563 { 564 int use_64bit = register_size (regcache->tdesc, 0) == 8; 565 566 if (use_64bit) 567 { 568 uint64_t pc; 569 570 collect_register_by_name (regcache, "rip", &pc); 571 return (CORE_ADDR) pc; 572 } 573 else 574 { 575 uint32_t pc; 576 577 collect_register_by_name (regcache, "eip", &pc); 578 return (CORE_ADDR) pc; 579 } 580 } 581 582 void 583 x86_target::low_set_pc (regcache *regcache, CORE_ADDR pc) 584 { 585 int use_64bit = register_size (regcache->tdesc, 0) == 8; 586 587 if (use_64bit) 588 { 589 uint64_t newpc = pc; 590 591 supply_register_by_name (regcache, "rip", &newpc); 592 } 593 else 594 { 595 uint32_t newpc = pc; 596 597 supply_register_by_name (regcache, "eip", &newpc); 598 } 599 } 600 601 int 602 x86_target::low_decr_pc_after_break () 603 { 604 return 1; 605 } 606 607 608 static const gdb_byte x86_breakpoint[] = { 0xCC }; 609 #define x86_breakpoint_len 1 610 611 bool 612 x86_target::low_breakpoint_at (CORE_ADDR pc) 613 { 614 unsigned char c; 615 616 read_memory (pc, &c, 1); 617 if (c == 0xCC) 618 return true; 619 620 return false; 621 } 622 623 /* Low-level function vector. */ 624 struct x86_dr_low_type x86_dr_low = 625 { 626 x86_linux_dr_set_control, 627 x86_linux_dr_set_addr, 628 x86_linux_dr_get_addr, 629 x86_linux_dr_get_status, 630 x86_linux_dr_get_control, 631 sizeof (void *), 632 }; 633 634 /* Breakpoint/Watchpoint support. */ 635 636 bool 637 x86_target::supports_z_point_type (char z_type) 638 { 639 switch (z_type) 640 { 641 case Z_PACKET_SW_BP: 642 case Z_PACKET_HW_BP: 643 case Z_PACKET_WRITE_WP: 644 case Z_PACKET_ACCESS_WP: 645 return true; 646 default: 647 return false; 648 } 649 } 650 651 int 652 x86_target::low_insert_point (raw_bkpt_type type, CORE_ADDR addr, 653 int size, raw_breakpoint *bp) 654 { 655 struct process_info *proc = current_process (); 656 657 switch (type) 658 { 659 case raw_bkpt_type_hw: 660 case raw_bkpt_type_write_wp: 661 case raw_bkpt_type_access_wp: 662 { 663 enum target_hw_bp_type hw_type 664 = raw_bkpt_type_to_target_hw_bp_type (type); 665 struct x86_debug_reg_state *state 666 = &proc->priv->arch_private->debug_reg_state; 667 668 return x86_dr_insert_watchpoint (state, hw_type, addr, size); 669 } 670 671 default: 672 /* Unsupported. */ 673 return 1; 674 } 675 } 676 677 int 678 x86_target::low_remove_point (raw_bkpt_type type, CORE_ADDR addr, 679 int size, raw_breakpoint *bp) 680 { 681 struct process_info *proc = current_process (); 682 683 switch (type) 684 { 685 case raw_bkpt_type_hw: 686 case raw_bkpt_type_write_wp: 687 case raw_bkpt_type_access_wp: 688 { 689 enum target_hw_bp_type hw_type 690 = raw_bkpt_type_to_target_hw_bp_type (type); 691 struct x86_debug_reg_state *state 692 = &proc->priv->arch_private->debug_reg_state; 693 694 return x86_dr_remove_watchpoint (state, hw_type, addr, size); 695 } 696 default: 697 /* Unsupported. */ 698 return 1; 699 } 700 } 701 702 bool 703 x86_target::low_stopped_by_watchpoint () 704 { 705 struct process_info *proc = current_process (); 706 return x86_dr_stopped_by_watchpoint (&proc->priv->arch_private->debug_reg_state); 707 } 708 709 CORE_ADDR 710 x86_target::low_stopped_data_address () 711 { 712 struct process_info *proc = current_process (); 713 CORE_ADDR addr; 714 if (x86_dr_stopped_data_address (&proc->priv->arch_private->debug_reg_state, 715 &addr)) 716 return addr; 717 return 0; 718 } 719 720 /* Called when a new process is created. */ 721 722 arch_process_info * 723 x86_target::low_new_process () 724 { 725 struct arch_process_info *info = XCNEW (struct arch_process_info); 726 727 x86_low_init_dregs (&info->debug_reg_state); 728 729 return info; 730 } 731 732 /* Called when a process is being deleted. */ 733 734 void 735 x86_target::low_delete_process (arch_process_info *info) 736 { 737 xfree (info); 738 } 739 740 void 741 x86_target::low_new_thread (lwp_info *lwp) 742 { 743 /* This comes from nat/. */ 744 x86_linux_new_thread (lwp); 745 } 746 747 void 748 x86_target::low_delete_thread (arch_lwp_info *alwp) 749 { 750 /* This comes from nat/. */ 751 x86_linux_delete_thread (alwp); 752 } 753 754 /* Target routine for new_fork. */ 755 756 void 757 x86_target::low_new_fork (process_info *parent, process_info *child) 758 { 759 /* These are allocated by linux_add_process. */ 760 gdb_assert (parent->priv != NULL 761 && parent->priv->arch_private != NULL); 762 gdb_assert (child->priv != NULL 763 && child->priv->arch_private != NULL); 764 765 /* Linux kernel before 2.6.33 commit 766 72f674d203cd230426437cdcf7dd6f681dad8b0d 767 will inherit hardware debug registers from parent 768 on fork/vfork/clone. Newer Linux kernels create such tasks with 769 zeroed debug registers. 770 771 GDB core assumes the child inherits the watchpoints/hw 772 breakpoints of the parent, and will remove them all from the 773 forked off process. Copy the debug registers mirrors into the 774 new process so that all breakpoints and watchpoints can be 775 removed together. The debug registers mirror will become zeroed 776 in the end before detaching the forked off process, thus making 777 this compatible with older Linux kernels too. */ 778 779 *child->priv->arch_private = *parent->priv->arch_private; 780 } 781 782 void 783 x86_target::low_prepare_to_resume (lwp_info *lwp) 784 { 785 /* This comes from nat/. */ 786 x86_linux_prepare_to_resume (lwp); 787 } 788 789 /* See nat/x86-dregs.h. */ 790 791 struct x86_debug_reg_state * 792 x86_debug_reg_state (pid_t pid) 793 { 794 struct process_info *proc = find_process_pid (pid); 795 796 return &proc->priv->arch_private->debug_reg_state; 797 } 798 799 /* When GDBSERVER is built as a 64-bit application on linux, the 800 PTRACE_GETSIGINFO data is always presented in 64-bit layout. Since 801 debugging a 32-bit inferior with a 64-bit GDBSERVER should look the same 802 as debugging it with a 32-bit GDBSERVER, we do the 32-bit <-> 64-bit 803 conversion in-place ourselves. */ 804 805 /* Convert a ptrace/host siginfo object, into/from the siginfo in the 806 layout of the inferiors' architecture. Returns true if any 807 conversion was done; false otherwise. If DIRECTION is 1, then copy 808 from INF to PTRACE. If DIRECTION is 0, copy from PTRACE to 809 INF. */ 810 811 bool 812 x86_target::low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction) 813 { 814 #ifdef __x86_64__ 815 unsigned int machine; 816 int tid = lwpid_of (current_thread); 817 int is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); 818 819 /* Is the inferior 32-bit? If so, then fixup the siginfo object. */ 820 if (!is_64bit_tdesc (current_thread)) 821 return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, 822 FIXUP_32); 823 /* No fixup for native x32 GDB. */ 824 else if (!is_elf64 && sizeof (void *) == 8) 825 return amd64_linux_siginfo_fixup_common (ptrace, inf, direction, 826 FIXUP_X32); 827 #endif 828 829 return false; 830 } 831 832 static int use_xml; 833 834 /* Format of XSAVE extended state is: 835 struct 836 { 837 fxsave_bytes[0..463] 838 sw_usable_bytes[464..511] 839 xstate_hdr_bytes[512..575] 840 avx_bytes[576..831] 841 future_state etc 842 }; 843 844 Same memory layout will be used for the coredump NT_X86_XSTATE 845 representing the XSAVE extended state registers. 846 847 The first 8 bytes of the sw_usable_bytes[464..467] is the OS enabled 848 extended state mask, which is the same as the extended control register 849 0 (the XFEATURE_ENABLED_MASK register), XCR0. We can use this mask 850 together with the mask saved in the xstate_hdr_bytes to determine what 851 states the processor/OS supports and what state, used or initialized, 852 the process/thread is in. */ 853 #define I386_LINUX_XSAVE_XCR0_OFFSET 464 854 855 /* Does the current host support the GETFPXREGS request? The header 856 file may or may not define it, and even if it is defined, the 857 kernel will return EIO if it's running on a pre-SSE processor. */ 858 int have_ptrace_getfpxregs = 859 #ifdef HAVE_PTRACE_GETFPXREGS 860 -1 861 #else 862 0 863 #endif 864 ; 865 866 /* Get Linux/x86 target description from running target. */ 867 868 static const struct target_desc * 869 x86_linux_read_description (void) 870 { 871 unsigned int machine; 872 int is_elf64; 873 int xcr0_features; 874 int tid; 875 static uint64_t xcr0; 876 static int xsave_len; 877 struct regset_info *regset; 878 879 tid = lwpid_of (current_thread); 880 881 is_elf64 = linux_pid_exe_is_elf_64_file (tid, &machine); 882 883 if (sizeof (void *) == 4) 884 { 885 if (is_elf64 > 0) 886 error (_("Can't debug 64-bit process with 32-bit GDBserver")); 887 #ifndef __x86_64__ 888 else if (machine == EM_X86_64) 889 error (_("Can't debug x86-64 process with 32-bit GDBserver")); 890 #endif 891 } 892 893 #if !defined __x86_64__ && defined HAVE_PTRACE_GETFPXREGS 894 if (machine == EM_386 && have_ptrace_getfpxregs == -1) 895 { 896 elf_fpxregset_t fpxregs; 897 898 if (ptrace (PTRACE_GETFPXREGS, tid, 0, (long) &fpxregs) < 0) 899 { 900 have_ptrace_getfpxregs = 0; 901 have_ptrace_getregset = TRIBOOL_FALSE; 902 return i386_linux_read_description (X86_XSTATE_X87); 903 } 904 else 905 have_ptrace_getfpxregs = 1; 906 } 907 #endif 908 909 if (!use_xml) 910 { 911 /* Don't use XML. */ 912 #ifdef __x86_64__ 913 if (machine == EM_X86_64) 914 return tdesc_amd64_linux_no_xml.get (); 915 else 916 #endif 917 return tdesc_i386_linux_no_xml.get (); 918 } 919 920 if (have_ptrace_getregset == TRIBOOL_UNKNOWN) 921 { 922 uint64_t xstateregs[(X86_XSTATE_SSE_SIZE / sizeof (uint64_t))]; 923 struct iovec iov; 924 925 iov.iov_base = xstateregs; 926 iov.iov_len = sizeof (xstateregs); 927 928 /* Check if PTRACE_GETREGSET works. */ 929 if (ptrace (PTRACE_GETREGSET, tid, 930 (unsigned int) NT_X86_XSTATE, (long) &iov) < 0) 931 have_ptrace_getregset = TRIBOOL_FALSE; 932 else 933 { 934 have_ptrace_getregset = TRIBOOL_TRUE; 935 936 /* Get XCR0 from XSAVE extended state. */ 937 xcr0 = xstateregs[(I386_LINUX_XSAVE_XCR0_OFFSET 938 / sizeof (uint64_t))]; 939 940 /* No MPX on x32. */ 941 if (machine == EM_X86_64 && !is_elf64) 942 xcr0 &= ~X86_XSTATE_MPX; 943 944 xsave_len = x86_xsave_length (); 945 946 /* Use PTRACE_GETREGSET if it is available. */ 947 for (regset = x86_regsets; 948 regset->fill_function != NULL; regset++) 949 if (regset->get_request == PTRACE_GETREGSET) 950 regset->size = xsave_len; 951 else if (regset->type != GENERAL_REGS) 952 regset->size = 0; 953 } 954 } 955 956 /* Check the native XCR0 only if PTRACE_GETREGSET is available. */ 957 xcr0_features = (have_ptrace_getregset == TRIBOOL_TRUE 958 && (xcr0 & X86_XSTATE_ALL_MASK)); 959 960 if (xcr0_features) 961 i387_set_xsave_mask (xcr0, xsave_len); 962 963 if (machine == EM_X86_64) 964 { 965 #ifdef __x86_64__ 966 const target_desc *tdesc = NULL; 967 968 if (xcr0_features) 969 { 970 tdesc = amd64_linux_read_description (xcr0 & X86_XSTATE_ALL_MASK, 971 !is_elf64); 972 } 973 974 if (tdesc == NULL) 975 tdesc = amd64_linux_read_description (X86_XSTATE_SSE_MASK, !is_elf64); 976 return tdesc; 977 #endif 978 } 979 else 980 { 981 const target_desc *tdesc = NULL; 982 983 if (xcr0_features) 984 tdesc = i386_linux_read_description (xcr0 & X86_XSTATE_ALL_MASK); 985 986 if (tdesc == NULL) 987 tdesc = i386_linux_read_description (X86_XSTATE_SSE); 988 989 return tdesc; 990 } 991 992 gdb_assert_not_reached ("failed to return tdesc"); 993 } 994 995 /* Update all the target description of all processes; a new GDB 996 connected, and it may or not support xml target descriptions. */ 997 998 void 999 x86_target::update_xmltarget () 1000 { 1001 scoped_restore_current_thread restore_thread; 1002 1003 /* Before changing the register cache's internal layout, flush the 1004 contents of the current valid caches back to the threads, and 1005 release the current regcache objects. */ 1006 regcache_release (); 1007 1008 for_each_process ([this] (process_info *proc) { 1009 int pid = proc->pid; 1010 1011 /* Look up any thread of this process. */ 1012 switch_to_thread (find_any_thread_of_pid (pid)); 1013 1014 low_arch_setup (); 1015 }); 1016 } 1017 1018 /* Process qSupported query, "xmlRegisters=". Update the buffer size for 1019 PTRACE_GETREGSET. */ 1020 1021 void 1022 x86_target::process_qsupported (gdb::array_view<const char * const> features) 1023 { 1024 /* Return if gdb doesn't support XML. If gdb sends "xmlRegisters=" 1025 with "i386" in qSupported query, it supports x86 XML target 1026 descriptions. */ 1027 use_xml = 0; 1028 1029 for (const char *feature : features) 1030 { 1031 if (startswith (feature, "xmlRegisters=")) 1032 { 1033 char *copy = xstrdup (feature + 13); 1034 1035 char *saveptr; 1036 for (char *p = strtok_r (copy, ",", &saveptr); 1037 p != NULL; 1038 p = strtok_r (NULL, ",", &saveptr)) 1039 { 1040 if (strcmp (p, "i386") == 0) 1041 { 1042 use_xml = 1; 1043 break; 1044 } 1045 } 1046 1047 free (copy); 1048 } 1049 } 1050 1051 update_xmltarget (); 1052 } 1053 1054 /* Common for x86/x86-64. */ 1055 1056 static struct regsets_info x86_regsets_info = 1057 { 1058 x86_regsets, /* regsets */ 1059 0, /* num_regsets */ 1060 NULL, /* disabled_regsets */ 1061 }; 1062 1063 #ifdef __x86_64__ 1064 static struct regs_info amd64_linux_regs_info = 1065 { 1066 NULL, /* regset_bitmap */ 1067 NULL, /* usrregs_info */ 1068 &x86_regsets_info 1069 }; 1070 #endif 1071 static struct usrregs_info i386_linux_usrregs_info = 1072 { 1073 I386_NUM_REGS, 1074 i386_regmap, 1075 }; 1076 1077 static struct regs_info i386_linux_regs_info = 1078 { 1079 NULL, /* regset_bitmap */ 1080 &i386_linux_usrregs_info, 1081 &x86_regsets_info 1082 }; 1083 1084 const regs_info * 1085 x86_target::get_regs_info () 1086 { 1087 #ifdef __x86_64__ 1088 if (is_64bit_tdesc (current_thread)) 1089 return &amd64_linux_regs_info; 1090 else 1091 #endif 1092 return &i386_linux_regs_info; 1093 } 1094 1095 /* Initialize the target description for the architecture of the 1096 inferior. */ 1097 1098 void 1099 x86_target::low_arch_setup () 1100 { 1101 current_process ()->tdesc = x86_linux_read_description (); 1102 } 1103 1104 bool 1105 x86_target::low_supports_catch_syscall () 1106 { 1107 return true; 1108 } 1109 1110 /* Fill *SYSNO and *SYSRET with the syscall nr trapped and the syscall return 1111 code. This should only be called if LWP got a SYSCALL_SIGTRAP. */ 1112 1113 void 1114 x86_target::low_get_syscall_trapinfo (regcache *regcache, int *sysno) 1115 { 1116 int use_64bit = register_size (regcache->tdesc, 0) == 8; 1117 1118 if (use_64bit) 1119 { 1120 long l_sysno; 1121 1122 collect_register_by_name (regcache, "orig_rax", &l_sysno); 1123 *sysno = (int) l_sysno; 1124 } 1125 else 1126 collect_register_by_name (regcache, "orig_eax", sysno); 1127 } 1128 1129 bool 1130 x86_target::supports_tracepoints () 1131 { 1132 return true; 1133 } 1134 1135 static void 1136 append_insns (CORE_ADDR *to, size_t len, const unsigned char *buf) 1137 { 1138 target_write_memory (*to, buf, len); 1139 *to += len; 1140 } 1141 1142 static int 1143 push_opcode (unsigned char *buf, const char *op) 1144 { 1145 unsigned char *buf_org = buf; 1146 1147 while (1) 1148 { 1149 char *endptr; 1150 unsigned long ul = strtoul (op, &endptr, 16); 1151 1152 if (endptr == op) 1153 break; 1154 1155 *buf++ = ul; 1156 op = endptr; 1157 } 1158 1159 return buf - buf_org; 1160 } 1161 1162 #ifdef __x86_64__ 1163 1164 /* Build a jump pad that saves registers and calls a collection 1165 function. Writes a jump instruction to the jump pad to 1166 JJUMPAD_INSN. The caller is responsible to write it in at the 1167 tracepoint address. */ 1168 1169 static int 1170 amd64_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, 1171 CORE_ADDR collector, 1172 CORE_ADDR lockaddr, 1173 ULONGEST orig_size, 1174 CORE_ADDR *jump_entry, 1175 CORE_ADDR *trampoline, 1176 ULONGEST *trampoline_size, 1177 unsigned char *jjump_pad_insn, 1178 ULONGEST *jjump_pad_insn_size, 1179 CORE_ADDR *adjusted_insn_addr, 1180 CORE_ADDR *adjusted_insn_addr_end, 1181 char *err) 1182 { 1183 unsigned char buf[40]; 1184 int i, offset; 1185 int64_t loffset; 1186 1187 CORE_ADDR buildaddr = *jump_entry; 1188 1189 /* Build the jump pad. */ 1190 1191 /* First, do tracepoint data collection. Save registers. */ 1192 i = 0; 1193 /* Need to ensure stack pointer saved first. */ 1194 buf[i++] = 0x54; /* push %rsp */ 1195 buf[i++] = 0x55; /* push %rbp */ 1196 buf[i++] = 0x57; /* push %rdi */ 1197 buf[i++] = 0x56; /* push %rsi */ 1198 buf[i++] = 0x52; /* push %rdx */ 1199 buf[i++] = 0x51; /* push %rcx */ 1200 buf[i++] = 0x53; /* push %rbx */ 1201 buf[i++] = 0x50; /* push %rax */ 1202 buf[i++] = 0x41; buf[i++] = 0x57; /* push %r15 */ 1203 buf[i++] = 0x41; buf[i++] = 0x56; /* push %r14 */ 1204 buf[i++] = 0x41; buf[i++] = 0x55; /* push %r13 */ 1205 buf[i++] = 0x41; buf[i++] = 0x54; /* push %r12 */ 1206 buf[i++] = 0x41; buf[i++] = 0x53; /* push %r11 */ 1207 buf[i++] = 0x41; buf[i++] = 0x52; /* push %r10 */ 1208 buf[i++] = 0x41; buf[i++] = 0x51; /* push %r9 */ 1209 buf[i++] = 0x41; buf[i++] = 0x50; /* push %r8 */ 1210 buf[i++] = 0x9c; /* pushfq */ 1211 buf[i++] = 0x48; /* movabs <addr>,%rdi */ 1212 buf[i++] = 0xbf; 1213 memcpy (buf + i, &tpaddr, 8); 1214 i += 8; 1215 buf[i++] = 0x57; /* push %rdi */ 1216 append_insns (&buildaddr, i, buf); 1217 1218 /* Stack space for the collecting_t object. */ 1219 i = 0; 1220 i += push_opcode (&buf[i], "48 83 ec 18"); /* sub $0x18,%rsp */ 1221 i += push_opcode (&buf[i], "48 b8"); /* mov <tpoint>,%rax */ 1222 memcpy (buf + i, &tpoint, 8); 1223 i += 8; 1224 i += push_opcode (&buf[i], "48 89 04 24"); /* mov %rax,(%rsp) */ 1225 i += push_opcode (&buf[i], 1226 "64 48 8b 04 25 00 00 00 00"); /* mov %fs:0x0,%rax */ 1227 i += push_opcode (&buf[i], "48 89 44 24 08"); /* mov %rax,0x8(%rsp) */ 1228 append_insns (&buildaddr, i, buf); 1229 1230 /* spin-lock. */ 1231 i = 0; 1232 i += push_opcode (&buf[i], "48 be"); /* movl <lockaddr>,%rsi */ 1233 memcpy (&buf[i], (void *) &lockaddr, 8); 1234 i += 8; 1235 i += push_opcode (&buf[i], "48 89 e1"); /* mov %rsp,%rcx */ 1236 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ 1237 i += push_opcode (&buf[i], "f0 48 0f b1 0e"); /* lock cmpxchg %rcx,(%rsi) */ 1238 i += push_opcode (&buf[i], "48 85 c0"); /* test %rax,%rax */ 1239 i += push_opcode (&buf[i], "75 f4"); /* jne <again> */ 1240 append_insns (&buildaddr, i, buf); 1241 1242 /* Set up the gdb_collect call. */ 1243 /* At this point, (stack pointer + 0x18) is the base of our saved 1244 register block. */ 1245 1246 i = 0; 1247 i += push_opcode (&buf[i], "48 89 e6"); /* mov %rsp,%rsi */ 1248 i += push_opcode (&buf[i], "48 83 c6 18"); /* add $0x18,%rsi */ 1249 1250 /* tpoint address may be 64-bit wide. */ 1251 i += push_opcode (&buf[i], "48 bf"); /* movl <addr>,%rdi */ 1252 memcpy (buf + i, &tpoint, 8); 1253 i += 8; 1254 append_insns (&buildaddr, i, buf); 1255 1256 /* The collector function being in the shared library, may be 1257 >31-bits away off the jump pad. */ 1258 i = 0; 1259 i += push_opcode (&buf[i], "48 b8"); /* mov $collector,%rax */ 1260 memcpy (buf + i, &collector, 8); 1261 i += 8; 1262 i += push_opcode (&buf[i], "ff d0"); /* callq *%rax */ 1263 append_insns (&buildaddr, i, buf); 1264 1265 /* Clear the spin-lock. */ 1266 i = 0; 1267 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ 1268 i += push_opcode (&buf[i], "48 a3"); /* mov %rax, lockaddr */ 1269 memcpy (buf + i, &lockaddr, 8); 1270 i += 8; 1271 append_insns (&buildaddr, i, buf); 1272 1273 /* Remove stack that had been used for the collect_t object. */ 1274 i = 0; 1275 i += push_opcode (&buf[i], "48 83 c4 18"); /* add $0x18,%rsp */ 1276 append_insns (&buildaddr, i, buf); 1277 1278 /* Restore register state. */ 1279 i = 0; 1280 buf[i++] = 0x48; /* add $0x8,%rsp */ 1281 buf[i++] = 0x83; 1282 buf[i++] = 0xc4; 1283 buf[i++] = 0x08; 1284 buf[i++] = 0x9d; /* popfq */ 1285 buf[i++] = 0x41; buf[i++] = 0x58; /* pop %r8 */ 1286 buf[i++] = 0x41; buf[i++] = 0x59; /* pop %r9 */ 1287 buf[i++] = 0x41; buf[i++] = 0x5a; /* pop %r10 */ 1288 buf[i++] = 0x41; buf[i++] = 0x5b; /* pop %r11 */ 1289 buf[i++] = 0x41; buf[i++] = 0x5c; /* pop %r12 */ 1290 buf[i++] = 0x41; buf[i++] = 0x5d; /* pop %r13 */ 1291 buf[i++] = 0x41; buf[i++] = 0x5e; /* pop %r14 */ 1292 buf[i++] = 0x41; buf[i++] = 0x5f; /* pop %r15 */ 1293 buf[i++] = 0x58; /* pop %rax */ 1294 buf[i++] = 0x5b; /* pop %rbx */ 1295 buf[i++] = 0x59; /* pop %rcx */ 1296 buf[i++] = 0x5a; /* pop %rdx */ 1297 buf[i++] = 0x5e; /* pop %rsi */ 1298 buf[i++] = 0x5f; /* pop %rdi */ 1299 buf[i++] = 0x5d; /* pop %rbp */ 1300 buf[i++] = 0x5c; /* pop %rsp */ 1301 append_insns (&buildaddr, i, buf); 1302 1303 /* Now, adjust the original instruction to execute in the jump 1304 pad. */ 1305 *adjusted_insn_addr = buildaddr; 1306 relocate_instruction (&buildaddr, tpaddr); 1307 *adjusted_insn_addr_end = buildaddr; 1308 1309 /* Finally, write a jump back to the program. */ 1310 1311 loffset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); 1312 if (loffset > INT_MAX || loffset < INT_MIN) 1313 { 1314 sprintf (err, 1315 "E.Jump back from jump pad too far from tracepoint " 1316 "(offset 0x%" PRIx64 " > int32).", loffset); 1317 return 1; 1318 } 1319 1320 offset = (int) loffset; 1321 memcpy (buf, jump_insn, sizeof (jump_insn)); 1322 memcpy (buf + 1, &offset, 4); 1323 append_insns (&buildaddr, sizeof (jump_insn), buf); 1324 1325 /* The jump pad is now built. Wire in a jump to our jump pad. This 1326 is always done last (by our caller actually), so that we can 1327 install fast tracepoints with threads running. This relies on 1328 the agent's atomic write support. */ 1329 loffset = *jump_entry - (tpaddr + sizeof (jump_insn)); 1330 if (loffset > INT_MAX || loffset < INT_MIN) 1331 { 1332 sprintf (err, 1333 "E.Jump pad too far from tracepoint " 1334 "(offset 0x%" PRIx64 " > int32).", loffset); 1335 return 1; 1336 } 1337 1338 offset = (int) loffset; 1339 1340 memcpy (buf, jump_insn, sizeof (jump_insn)); 1341 memcpy (buf + 1, &offset, 4); 1342 memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); 1343 *jjump_pad_insn_size = sizeof (jump_insn); 1344 1345 /* Return the end address of our pad. */ 1346 *jump_entry = buildaddr; 1347 1348 return 0; 1349 } 1350 1351 #endif /* __x86_64__ */ 1352 1353 /* Build a jump pad that saves registers and calls a collection 1354 function. Writes a jump instruction to the jump pad to 1355 JJUMPAD_INSN. The caller is responsible to write it in at the 1356 tracepoint address. */ 1357 1358 static int 1359 i386_install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, CORE_ADDR tpaddr, 1360 CORE_ADDR collector, 1361 CORE_ADDR lockaddr, 1362 ULONGEST orig_size, 1363 CORE_ADDR *jump_entry, 1364 CORE_ADDR *trampoline, 1365 ULONGEST *trampoline_size, 1366 unsigned char *jjump_pad_insn, 1367 ULONGEST *jjump_pad_insn_size, 1368 CORE_ADDR *adjusted_insn_addr, 1369 CORE_ADDR *adjusted_insn_addr_end, 1370 char *err) 1371 { 1372 unsigned char buf[0x100]; 1373 int i, offset; 1374 CORE_ADDR buildaddr = *jump_entry; 1375 1376 /* Build the jump pad. */ 1377 1378 /* First, do tracepoint data collection. Save registers. */ 1379 i = 0; 1380 buf[i++] = 0x60; /* pushad */ 1381 buf[i++] = 0x68; /* push tpaddr aka $pc */ 1382 *((int *)(buf + i)) = (int) tpaddr; 1383 i += 4; 1384 buf[i++] = 0x9c; /* pushf */ 1385 buf[i++] = 0x1e; /* push %ds */ 1386 buf[i++] = 0x06; /* push %es */ 1387 buf[i++] = 0x0f; /* push %fs */ 1388 buf[i++] = 0xa0; 1389 buf[i++] = 0x0f; /* push %gs */ 1390 buf[i++] = 0xa8; 1391 buf[i++] = 0x16; /* push %ss */ 1392 buf[i++] = 0x0e; /* push %cs */ 1393 append_insns (&buildaddr, i, buf); 1394 1395 /* Stack space for the collecting_t object. */ 1396 i = 0; 1397 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ 1398 1399 /* Build the object. */ 1400 i += push_opcode (&buf[i], "b8"); /* mov <tpoint>,%eax */ 1401 memcpy (buf + i, &tpoint, 4); 1402 i += 4; 1403 i += push_opcode (&buf[i], "89 04 24"); /* mov %eax,(%esp) */ 1404 1405 i += push_opcode (&buf[i], "65 a1 00 00 00 00"); /* mov %gs:0x0,%eax */ 1406 i += push_opcode (&buf[i], "89 44 24 04"); /* mov %eax,0x4(%esp) */ 1407 append_insns (&buildaddr, i, buf); 1408 1409 /* spin-lock. Note this is using cmpxchg, which leaves i386 behind. 1410 If we cared for it, this could be using xchg alternatively. */ 1411 1412 i = 0; 1413 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ 1414 i += push_opcode (&buf[i], "f0 0f b1 25"); /* lock cmpxchg 1415 %esp,<lockaddr> */ 1416 memcpy (&buf[i], (void *) &lockaddr, 4); 1417 i += 4; 1418 i += push_opcode (&buf[i], "85 c0"); /* test %eax,%eax */ 1419 i += push_opcode (&buf[i], "75 f2"); /* jne <again> */ 1420 append_insns (&buildaddr, i, buf); 1421 1422 1423 /* Set up arguments to the gdb_collect call. */ 1424 i = 0; 1425 i += push_opcode (&buf[i], "89 e0"); /* mov %esp,%eax */ 1426 i += push_opcode (&buf[i], "83 c0 08"); /* add $0x08,%eax */ 1427 i += push_opcode (&buf[i], "89 44 24 fc"); /* mov %eax,-0x4(%esp) */ 1428 append_insns (&buildaddr, i, buf); 1429 1430 i = 0; 1431 i += push_opcode (&buf[i], "83 ec 08"); /* sub $0x8,%esp */ 1432 append_insns (&buildaddr, i, buf); 1433 1434 i = 0; 1435 i += push_opcode (&buf[i], "c7 04 24"); /* movl <addr>,(%esp) */ 1436 memcpy (&buf[i], (void *) &tpoint, 4); 1437 i += 4; 1438 append_insns (&buildaddr, i, buf); 1439 1440 buf[0] = 0xe8; /* call <reladdr> */ 1441 offset = collector - (buildaddr + sizeof (jump_insn)); 1442 memcpy (buf + 1, &offset, 4); 1443 append_insns (&buildaddr, 5, buf); 1444 /* Clean up after the call. */ 1445 buf[0] = 0x83; /* add $0x8,%esp */ 1446 buf[1] = 0xc4; 1447 buf[2] = 0x08; 1448 append_insns (&buildaddr, 3, buf); 1449 1450 1451 /* Clear the spin-lock. This would need the LOCK prefix on older 1452 broken archs. */ 1453 i = 0; 1454 i += push_opcode (&buf[i], "31 c0"); /* xor %eax,%eax */ 1455 i += push_opcode (&buf[i], "a3"); /* mov %eax, lockaddr */ 1456 memcpy (buf + i, &lockaddr, 4); 1457 i += 4; 1458 append_insns (&buildaddr, i, buf); 1459 1460 1461 /* Remove stack that had been used for the collect_t object. */ 1462 i = 0; 1463 i += push_opcode (&buf[i], "83 c4 08"); /* add $0x08,%esp */ 1464 append_insns (&buildaddr, i, buf); 1465 1466 i = 0; 1467 buf[i++] = 0x83; /* add $0x4,%esp (no pop of %cs, assume unchanged) */ 1468 buf[i++] = 0xc4; 1469 buf[i++] = 0x04; 1470 buf[i++] = 0x17; /* pop %ss */ 1471 buf[i++] = 0x0f; /* pop %gs */ 1472 buf[i++] = 0xa9; 1473 buf[i++] = 0x0f; /* pop %fs */ 1474 buf[i++] = 0xa1; 1475 buf[i++] = 0x07; /* pop %es */ 1476 buf[i++] = 0x1f; /* pop %ds */ 1477 buf[i++] = 0x9d; /* popf */ 1478 buf[i++] = 0x83; /* add $0x4,%esp (pop of tpaddr aka $pc) */ 1479 buf[i++] = 0xc4; 1480 buf[i++] = 0x04; 1481 buf[i++] = 0x61; /* popad */ 1482 append_insns (&buildaddr, i, buf); 1483 1484 /* Now, adjust the original instruction to execute in the jump 1485 pad. */ 1486 *adjusted_insn_addr = buildaddr; 1487 relocate_instruction (&buildaddr, tpaddr); 1488 *adjusted_insn_addr_end = buildaddr; 1489 1490 /* Write the jump back to the program. */ 1491 offset = (tpaddr + orig_size) - (buildaddr + sizeof (jump_insn)); 1492 memcpy (buf, jump_insn, sizeof (jump_insn)); 1493 memcpy (buf + 1, &offset, 4); 1494 append_insns (&buildaddr, sizeof (jump_insn), buf); 1495 1496 /* The jump pad is now built. Wire in a jump to our jump pad. This 1497 is always done last (by our caller actually), so that we can 1498 install fast tracepoints with threads running. This relies on 1499 the agent's atomic write support. */ 1500 if (orig_size == 4) 1501 { 1502 /* Create a trampoline. */ 1503 *trampoline_size = sizeof (jump_insn); 1504 if (!claim_trampoline_space (*trampoline_size, trampoline)) 1505 { 1506 /* No trampoline space available. */ 1507 strcpy (err, 1508 "E.Cannot allocate trampoline space needed for fast " 1509 "tracepoints on 4-byte instructions."); 1510 return 1; 1511 } 1512 1513 offset = *jump_entry - (*trampoline + sizeof (jump_insn)); 1514 memcpy (buf, jump_insn, sizeof (jump_insn)); 1515 memcpy (buf + 1, &offset, 4); 1516 target_write_memory (*trampoline, buf, sizeof (jump_insn)); 1517 1518 /* Use a 16-bit relative jump instruction to jump to the trampoline. */ 1519 offset = (*trampoline - (tpaddr + sizeof (small_jump_insn))) & 0xffff; 1520 memcpy (buf, small_jump_insn, sizeof (small_jump_insn)); 1521 memcpy (buf + 2, &offset, 2); 1522 memcpy (jjump_pad_insn, buf, sizeof (small_jump_insn)); 1523 *jjump_pad_insn_size = sizeof (small_jump_insn); 1524 } 1525 else 1526 { 1527 /* Else use a 32-bit relative jump instruction. */ 1528 offset = *jump_entry - (tpaddr + sizeof (jump_insn)); 1529 memcpy (buf, jump_insn, sizeof (jump_insn)); 1530 memcpy (buf + 1, &offset, 4); 1531 memcpy (jjump_pad_insn, buf, sizeof (jump_insn)); 1532 *jjump_pad_insn_size = sizeof (jump_insn); 1533 } 1534 1535 /* Return the end address of our pad. */ 1536 *jump_entry = buildaddr; 1537 1538 return 0; 1539 } 1540 1541 bool 1542 x86_target::supports_fast_tracepoints () 1543 { 1544 return true; 1545 } 1546 1547 int 1548 x86_target::install_fast_tracepoint_jump_pad (CORE_ADDR tpoint, 1549 CORE_ADDR tpaddr, 1550 CORE_ADDR collector, 1551 CORE_ADDR lockaddr, 1552 ULONGEST orig_size, 1553 CORE_ADDR *jump_entry, 1554 CORE_ADDR *trampoline, 1555 ULONGEST *trampoline_size, 1556 unsigned char *jjump_pad_insn, 1557 ULONGEST *jjump_pad_insn_size, 1558 CORE_ADDR *adjusted_insn_addr, 1559 CORE_ADDR *adjusted_insn_addr_end, 1560 char *err) 1561 { 1562 #ifdef __x86_64__ 1563 if (is_64bit_tdesc (current_thread)) 1564 return amd64_install_fast_tracepoint_jump_pad (tpoint, tpaddr, 1565 collector, lockaddr, 1566 orig_size, jump_entry, 1567 trampoline, trampoline_size, 1568 jjump_pad_insn, 1569 jjump_pad_insn_size, 1570 adjusted_insn_addr, 1571 adjusted_insn_addr_end, 1572 err); 1573 #endif 1574 1575 return i386_install_fast_tracepoint_jump_pad (tpoint, tpaddr, 1576 collector, lockaddr, 1577 orig_size, jump_entry, 1578 trampoline, trampoline_size, 1579 jjump_pad_insn, 1580 jjump_pad_insn_size, 1581 adjusted_insn_addr, 1582 adjusted_insn_addr_end, 1583 err); 1584 } 1585 1586 /* Return the minimum instruction length for fast tracepoints on x86/x86-64 1587 architectures. */ 1588 1589 int 1590 x86_target::get_min_fast_tracepoint_insn_len () 1591 { 1592 static int warned_about_fast_tracepoints = 0; 1593 1594 #ifdef __x86_64__ 1595 /* On x86-64, 5-byte jump instructions with a 4-byte offset are always 1596 used for fast tracepoints. */ 1597 if (is_64bit_tdesc (current_thread)) 1598 return 5; 1599 #endif 1600 1601 if (agent_loaded_p ()) 1602 { 1603 char errbuf[IPA_BUFSIZ]; 1604 1605 errbuf[0] = '\0'; 1606 1607 /* On x86, if trampolines are available, then 4-byte jump instructions 1608 with a 2-byte offset may be used, otherwise 5-byte jump instructions 1609 with a 4-byte offset are used instead. */ 1610 if (have_fast_tracepoint_trampoline_buffer (errbuf)) 1611 return 4; 1612 else 1613 { 1614 /* GDB has no channel to explain to user why a shorter fast 1615 tracepoint is not possible, but at least make GDBserver 1616 mention that something has gone awry. */ 1617 if (!warned_about_fast_tracepoints) 1618 { 1619 warning ("4-byte fast tracepoints not available; %s", errbuf); 1620 warned_about_fast_tracepoints = 1; 1621 } 1622 return 5; 1623 } 1624 } 1625 else 1626 { 1627 /* Indicate that the minimum length is currently unknown since the IPA 1628 has not loaded yet. */ 1629 return 0; 1630 } 1631 } 1632 1633 static void 1634 add_insns (unsigned char *start, int len) 1635 { 1636 CORE_ADDR buildaddr = current_insn_ptr; 1637 1638 threads_debug_printf ("Adding %d bytes of insn at %s", 1639 len, paddress (buildaddr)); 1640 1641 append_insns (&buildaddr, len, start); 1642 current_insn_ptr = buildaddr; 1643 } 1644 1645 /* Our general strategy for emitting code is to avoid specifying raw 1646 bytes whenever possible, and instead copy a block of inline asm 1647 that is embedded in the function. This is a little messy, because 1648 we need to keep the compiler from discarding what looks like dead 1649 code, plus suppress various warnings. */ 1650 1651 #define EMIT_ASM(NAME, INSNS) \ 1652 do \ 1653 { \ 1654 extern unsigned char start_ ## NAME, end_ ## NAME; \ 1655 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ 1656 __asm__ ("jmp end_" #NAME "\n" \ 1657 "\t" "start_" #NAME ":" \ 1658 "\t" INSNS "\n" \ 1659 "\t" "end_" #NAME ":"); \ 1660 } while (0) 1661 1662 #ifdef __x86_64__ 1663 1664 #define EMIT_ASM32(NAME,INSNS) \ 1665 do \ 1666 { \ 1667 extern unsigned char start_ ## NAME, end_ ## NAME; \ 1668 add_insns (&start_ ## NAME, &end_ ## NAME - &start_ ## NAME); \ 1669 __asm__ (".code32\n" \ 1670 "\t" "jmp end_" #NAME "\n" \ 1671 "\t" "start_" #NAME ":\n" \ 1672 "\t" INSNS "\n" \ 1673 "\t" "end_" #NAME ":\n" \ 1674 ".code64\n"); \ 1675 } while (0) 1676 1677 #else 1678 1679 #define EMIT_ASM32(NAME,INSNS) EMIT_ASM(NAME,INSNS) 1680 1681 #endif 1682 1683 #ifdef __x86_64__ 1684 1685 static void 1686 amd64_emit_prologue (void) 1687 { 1688 EMIT_ASM (amd64_prologue, 1689 "pushq %rbp\n\t" 1690 "movq %rsp,%rbp\n\t" 1691 "sub $0x20,%rsp\n\t" 1692 "movq %rdi,-8(%rbp)\n\t" 1693 "movq %rsi,-16(%rbp)"); 1694 } 1695 1696 1697 static void 1698 amd64_emit_epilogue (void) 1699 { 1700 EMIT_ASM (amd64_epilogue, 1701 "movq -16(%rbp),%rdi\n\t" 1702 "movq %rax,(%rdi)\n\t" 1703 "xor %rax,%rax\n\t" 1704 "leave\n\t" 1705 "ret"); 1706 } 1707 1708 static void 1709 amd64_emit_add (void) 1710 { 1711 EMIT_ASM (amd64_add, 1712 "add (%rsp),%rax\n\t" 1713 "lea 0x8(%rsp),%rsp"); 1714 } 1715 1716 static void 1717 amd64_emit_sub (void) 1718 { 1719 EMIT_ASM (amd64_sub, 1720 "sub %rax,(%rsp)\n\t" 1721 "pop %rax"); 1722 } 1723 1724 static void 1725 amd64_emit_mul (void) 1726 { 1727 emit_error = 1; 1728 } 1729 1730 static void 1731 amd64_emit_lsh (void) 1732 { 1733 emit_error = 1; 1734 } 1735 1736 static void 1737 amd64_emit_rsh_signed (void) 1738 { 1739 emit_error = 1; 1740 } 1741 1742 static void 1743 amd64_emit_rsh_unsigned (void) 1744 { 1745 emit_error = 1; 1746 } 1747 1748 static void 1749 amd64_emit_ext (int arg) 1750 { 1751 switch (arg) 1752 { 1753 case 8: 1754 EMIT_ASM (amd64_ext_8, 1755 "cbtw\n\t" 1756 "cwtl\n\t" 1757 "cltq"); 1758 break; 1759 case 16: 1760 EMIT_ASM (amd64_ext_16, 1761 "cwtl\n\t" 1762 "cltq"); 1763 break; 1764 case 32: 1765 EMIT_ASM (amd64_ext_32, 1766 "cltq"); 1767 break; 1768 default: 1769 emit_error = 1; 1770 } 1771 } 1772 1773 static void 1774 amd64_emit_log_not (void) 1775 { 1776 EMIT_ASM (amd64_log_not, 1777 "test %rax,%rax\n\t" 1778 "sete %cl\n\t" 1779 "movzbq %cl,%rax"); 1780 } 1781 1782 static void 1783 amd64_emit_bit_and (void) 1784 { 1785 EMIT_ASM (amd64_and, 1786 "and (%rsp),%rax\n\t" 1787 "lea 0x8(%rsp),%rsp"); 1788 } 1789 1790 static void 1791 amd64_emit_bit_or (void) 1792 { 1793 EMIT_ASM (amd64_or, 1794 "or (%rsp),%rax\n\t" 1795 "lea 0x8(%rsp),%rsp"); 1796 } 1797 1798 static void 1799 amd64_emit_bit_xor (void) 1800 { 1801 EMIT_ASM (amd64_xor, 1802 "xor (%rsp),%rax\n\t" 1803 "lea 0x8(%rsp),%rsp"); 1804 } 1805 1806 static void 1807 amd64_emit_bit_not (void) 1808 { 1809 EMIT_ASM (amd64_bit_not, 1810 "xorq $0xffffffffffffffff,%rax"); 1811 } 1812 1813 static void 1814 amd64_emit_equal (void) 1815 { 1816 EMIT_ASM (amd64_equal, 1817 "cmp %rax,(%rsp)\n\t" 1818 "je .Lamd64_equal_true\n\t" 1819 "xor %rax,%rax\n\t" 1820 "jmp .Lamd64_equal_end\n\t" 1821 ".Lamd64_equal_true:\n\t" 1822 "mov $0x1,%rax\n\t" 1823 ".Lamd64_equal_end:\n\t" 1824 "lea 0x8(%rsp),%rsp"); 1825 } 1826 1827 static void 1828 amd64_emit_less_signed (void) 1829 { 1830 EMIT_ASM (amd64_less_signed, 1831 "cmp %rax,(%rsp)\n\t" 1832 "jl .Lamd64_less_signed_true\n\t" 1833 "xor %rax,%rax\n\t" 1834 "jmp .Lamd64_less_signed_end\n\t" 1835 ".Lamd64_less_signed_true:\n\t" 1836 "mov $1,%rax\n\t" 1837 ".Lamd64_less_signed_end:\n\t" 1838 "lea 0x8(%rsp),%rsp"); 1839 } 1840 1841 static void 1842 amd64_emit_less_unsigned (void) 1843 { 1844 EMIT_ASM (amd64_less_unsigned, 1845 "cmp %rax,(%rsp)\n\t" 1846 "jb .Lamd64_less_unsigned_true\n\t" 1847 "xor %rax,%rax\n\t" 1848 "jmp .Lamd64_less_unsigned_end\n\t" 1849 ".Lamd64_less_unsigned_true:\n\t" 1850 "mov $1,%rax\n\t" 1851 ".Lamd64_less_unsigned_end:\n\t" 1852 "lea 0x8(%rsp),%rsp"); 1853 } 1854 1855 static void 1856 amd64_emit_ref (int size) 1857 { 1858 switch (size) 1859 { 1860 case 1: 1861 EMIT_ASM (amd64_ref1, 1862 "movb (%rax),%al"); 1863 break; 1864 case 2: 1865 EMIT_ASM (amd64_ref2, 1866 "movw (%rax),%ax"); 1867 break; 1868 case 4: 1869 EMIT_ASM (amd64_ref4, 1870 "movl (%rax),%eax"); 1871 break; 1872 case 8: 1873 EMIT_ASM (amd64_ref8, 1874 "movq (%rax),%rax"); 1875 break; 1876 } 1877 } 1878 1879 static void 1880 amd64_emit_if_goto (int *offset_p, int *size_p) 1881 { 1882 EMIT_ASM (amd64_if_goto, 1883 "mov %rax,%rcx\n\t" 1884 "pop %rax\n\t" 1885 "cmp $0,%rcx\n\t" 1886 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); 1887 if (offset_p) 1888 *offset_p = 10; 1889 if (size_p) 1890 *size_p = 4; 1891 } 1892 1893 static void 1894 amd64_emit_goto (int *offset_p, int *size_p) 1895 { 1896 EMIT_ASM (amd64_goto, 1897 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); 1898 if (offset_p) 1899 *offset_p = 1; 1900 if (size_p) 1901 *size_p = 4; 1902 } 1903 1904 static void 1905 amd64_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) 1906 { 1907 int diff = (to - (from + size)); 1908 unsigned char buf[sizeof (int)]; 1909 1910 if (size != 4) 1911 { 1912 emit_error = 1; 1913 return; 1914 } 1915 1916 memcpy (buf, &diff, sizeof (int)); 1917 target_write_memory (from, buf, sizeof (int)); 1918 } 1919 1920 static void 1921 amd64_emit_const (LONGEST num) 1922 { 1923 unsigned char buf[16]; 1924 int i; 1925 CORE_ADDR buildaddr = current_insn_ptr; 1926 1927 i = 0; 1928 buf[i++] = 0x48; buf[i++] = 0xb8; /* mov $<n>,%rax */ 1929 memcpy (&buf[i], &num, sizeof (num)); 1930 i += 8; 1931 append_insns (&buildaddr, i, buf); 1932 current_insn_ptr = buildaddr; 1933 } 1934 1935 static void 1936 amd64_emit_call (CORE_ADDR fn) 1937 { 1938 unsigned char buf[16]; 1939 int i; 1940 CORE_ADDR buildaddr; 1941 LONGEST offset64; 1942 1943 /* The destination function being in the shared library, may be 1944 >31-bits away off the compiled code pad. */ 1945 1946 buildaddr = current_insn_ptr; 1947 1948 offset64 = fn - (buildaddr + 1 /* call op */ + 4 /* 32-bit offset */); 1949 1950 i = 0; 1951 1952 if (offset64 > INT_MAX || offset64 < INT_MIN) 1953 { 1954 /* Offset is too large for a call. Use callq, but that requires 1955 a register, so avoid it if possible. Use r10, since it is 1956 call-clobbered, we don't have to push/pop it. */ 1957 buf[i++] = 0x48; /* mov $fn,%r10 */ 1958 buf[i++] = 0xba; 1959 memcpy (buf + i, &fn, 8); 1960 i += 8; 1961 buf[i++] = 0xff; /* callq *%r10 */ 1962 buf[i++] = 0xd2; 1963 } 1964 else 1965 { 1966 int offset32 = offset64; /* we know we can't overflow here. */ 1967 1968 buf[i++] = 0xe8; /* call <reladdr> */ 1969 memcpy (buf + i, &offset32, 4); 1970 i += 4; 1971 } 1972 1973 append_insns (&buildaddr, i, buf); 1974 current_insn_ptr = buildaddr; 1975 } 1976 1977 static void 1978 amd64_emit_reg (int reg) 1979 { 1980 unsigned char buf[16]; 1981 int i; 1982 CORE_ADDR buildaddr; 1983 1984 /* Assume raw_regs is still in %rdi. */ 1985 buildaddr = current_insn_ptr; 1986 i = 0; 1987 buf[i++] = 0xbe; /* mov $<n>,%esi */ 1988 memcpy (&buf[i], ®, sizeof (reg)); 1989 i += 4; 1990 append_insns (&buildaddr, i, buf); 1991 current_insn_ptr = buildaddr; 1992 amd64_emit_call (get_raw_reg_func_addr ()); 1993 } 1994 1995 static void 1996 amd64_emit_pop (void) 1997 { 1998 EMIT_ASM (amd64_pop, 1999 "pop %rax"); 2000 } 2001 2002 static void 2003 amd64_emit_stack_flush (void) 2004 { 2005 EMIT_ASM (amd64_stack_flush, 2006 "push %rax"); 2007 } 2008 2009 static void 2010 amd64_emit_zero_ext (int arg) 2011 { 2012 switch (arg) 2013 { 2014 case 8: 2015 EMIT_ASM (amd64_zero_ext_8, 2016 "and $0xff,%rax"); 2017 break; 2018 case 16: 2019 EMIT_ASM (amd64_zero_ext_16, 2020 "and $0xffff,%rax"); 2021 break; 2022 case 32: 2023 EMIT_ASM (amd64_zero_ext_32, 2024 "mov $0xffffffff,%rcx\n\t" 2025 "and %rcx,%rax"); 2026 break; 2027 default: 2028 emit_error = 1; 2029 } 2030 } 2031 2032 static void 2033 amd64_emit_swap (void) 2034 { 2035 EMIT_ASM (amd64_swap, 2036 "mov %rax,%rcx\n\t" 2037 "pop %rax\n\t" 2038 "push %rcx"); 2039 } 2040 2041 static void 2042 amd64_emit_stack_adjust (int n) 2043 { 2044 unsigned char buf[16]; 2045 int i; 2046 CORE_ADDR buildaddr = current_insn_ptr; 2047 2048 i = 0; 2049 buf[i++] = 0x48; /* lea $<n>(%rsp),%rsp */ 2050 buf[i++] = 0x8d; 2051 buf[i++] = 0x64; 2052 buf[i++] = 0x24; 2053 /* This only handles adjustments up to 16, but we don't expect any more. */ 2054 buf[i++] = n * 8; 2055 append_insns (&buildaddr, i, buf); 2056 current_insn_ptr = buildaddr; 2057 } 2058 2059 /* FN's prototype is `LONGEST(*fn)(int)'. */ 2060 2061 static void 2062 amd64_emit_int_call_1 (CORE_ADDR fn, int arg1) 2063 { 2064 unsigned char buf[16]; 2065 int i; 2066 CORE_ADDR buildaddr; 2067 2068 buildaddr = current_insn_ptr; 2069 i = 0; 2070 buf[i++] = 0xbf; /* movl $<n>,%edi */ 2071 memcpy (&buf[i], &arg1, sizeof (arg1)); 2072 i += 4; 2073 append_insns (&buildaddr, i, buf); 2074 current_insn_ptr = buildaddr; 2075 amd64_emit_call (fn); 2076 } 2077 2078 /* FN's prototype is `void(*fn)(int,LONGEST)'. */ 2079 2080 static void 2081 amd64_emit_void_call_2 (CORE_ADDR fn, int arg1) 2082 { 2083 unsigned char buf[16]; 2084 int i; 2085 CORE_ADDR buildaddr; 2086 2087 buildaddr = current_insn_ptr; 2088 i = 0; 2089 buf[i++] = 0xbf; /* movl $<n>,%edi */ 2090 memcpy (&buf[i], &arg1, sizeof (arg1)); 2091 i += 4; 2092 append_insns (&buildaddr, i, buf); 2093 current_insn_ptr = buildaddr; 2094 EMIT_ASM (amd64_void_call_2_a, 2095 /* Save away a copy of the stack top. */ 2096 "push %rax\n\t" 2097 /* Also pass top as the second argument. */ 2098 "mov %rax,%rsi"); 2099 amd64_emit_call (fn); 2100 EMIT_ASM (amd64_void_call_2_b, 2101 /* Restore the stack top, %rax may have been trashed. */ 2102 "pop %rax"); 2103 } 2104 2105 static void 2106 amd64_emit_eq_goto (int *offset_p, int *size_p) 2107 { 2108 EMIT_ASM (amd64_eq, 2109 "cmp %rax,(%rsp)\n\t" 2110 "jne .Lamd64_eq_fallthru\n\t" 2111 "lea 0x8(%rsp),%rsp\n\t" 2112 "pop %rax\n\t" 2113 /* jmp, but don't trust the assembler to choose the right jump */ 2114 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2115 ".Lamd64_eq_fallthru:\n\t" 2116 "lea 0x8(%rsp),%rsp\n\t" 2117 "pop %rax"); 2118 2119 if (offset_p) 2120 *offset_p = 13; 2121 if (size_p) 2122 *size_p = 4; 2123 } 2124 2125 static void 2126 amd64_emit_ne_goto (int *offset_p, int *size_p) 2127 { 2128 EMIT_ASM (amd64_ne, 2129 "cmp %rax,(%rsp)\n\t" 2130 "je .Lamd64_ne_fallthru\n\t" 2131 "lea 0x8(%rsp),%rsp\n\t" 2132 "pop %rax\n\t" 2133 /* jmp, but don't trust the assembler to choose the right jump */ 2134 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2135 ".Lamd64_ne_fallthru:\n\t" 2136 "lea 0x8(%rsp),%rsp\n\t" 2137 "pop %rax"); 2138 2139 if (offset_p) 2140 *offset_p = 13; 2141 if (size_p) 2142 *size_p = 4; 2143 } 2144 2145 static void 2146 amd64_emit_lt_goto (int *offset_p, int *size_p) 2147 { 2148 EMIT_ASM (amd64_lt, 2149 "cmp %rax,(%rsp)\n\t" 2150 "jnl .Lamd64_lt_fallthru\n\t" 2151 "lea 0x8(%rsp),%rsp\n\t" 2152 "pop %rax\n\t" 2153 /* jmp, but don't trust the assembler to choose the right jump */ 2154 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2155 ".Lamd64_lt_fallthru:\n\t" 2156 "lea 0x8(%rsp),%rsp\n\t" 2157 "pop %rax"); 2158 2159 if (offset_p) 2160 *offset_p = 13; 2161 if (size_p) 2162 *size_p = 4; 2163 } 2164 2165 static void 2166 amd64_emit_le_goto (int *offset_p, int *size_p) 2167 { 2168 EMIT_ASM (amd64_le, 2169 "cmp %rax,(%rsp)\n\t" 2170 "jnle .Lamd64_le_fallthru\n\t" 2171 "lea 0x8(%rsp),%rsp\n\t" 2172 "pop %rax\n\t" 2173 /* jmp, but don't trust the assembler to choose the right jump */ 2174 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2175 ".Lamd64_le_fallthru:\n\t" 2176 "lea 0x8(%rsp),%rsp\n\t" 2177 "pop %rax"); 2178 2179 if (offset_p) 2180 *offset_p = 13; 2181 if (size_p) 2182 *size_p = 4; 2183 } 2184 2185 static void 2186 amd64_emit_gt_goto (int *offset_p, int *size_p) 2187 { 2188 EMIT_ASM (amd64_gt, 2189 "cmp %rax,(%rsp)\n\t" 2190 "jng .Lamd64_gt_fallthru\n\t" 2191 "lea 0x8(%rsp),%rsp\n\t" 2192 "pop %rax\n\t" 2193 /* jmp, but don't trust the assembler to choose the right jump */ 2194 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2195 ".Lamd64_gt_fallthru:\n\t" 2196 "lea 0x8(%rsp),%rsp\n\t" 2197 "pop %rax"); 2198 2199 if (offset_p) 2200 *offset_p = 13; 2201 if (size_p) 2202 *size_p = 4; 2203 } 2204 2205 static void 2206 amd64_emit_ge_goto (int *offset_p, int *size_p) 2207 { 2208 EMIT_ASM (amd64_ge, 2209 "cmp %rax,(%rsp)\n\t" 2210 "jnge .Lamd64_ge_fallthru\n\t" 2211 ".Lamd64_ge_jump:\n\t" 2212 "lea 0x8(%rsp),%rsp\n\t" 2213 "pop %rax\n\t" 2214 /* jmp, but don't trust the assembler to choose the right jump */ 2215 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2216 ".Lamd64_ge_fallthru:\n\t" 2217 "lea 0x8(%rsp),%rsp\n\t" 2218 "pop %rax"); 2219 2220 if (offset_p) 2221 *offset_p = 13; 2222 if (size_p) 2223 *size_p = 4; 2224 } 2225 2226 static emit_ops amd64_emit_ops = 2227 { 2228 amd64_emit_prologue, 2229 amd64_emit_epilogue, 2230 amd64_emit_add, 2231 amd64_emit_sub, 2232 amd64_emit_mul, 2233 amd64_emit_lsh, 2234 amd64_emit_rsh_signed, 2235 amd64_emit_rsh_unsigned, 2236 amd64_emit_ext, 2237 amd64_emit_log_not, 2238 amd64_emit_bit_and, 2239 amd64_emit_bit_or, 2240 amd64_emit_bit_xor, 2241 amd64_emit_bit_not, 2242 amd64_emit_equal, 2243 amd64_emit_less_signed, 2244 amd64_emit_less_unsigned, 2245 amd64_emit_ref, 2246 amd64_emit_if_goto, 2247 amd64_emit_goto, 2248 amd64_write_goto_address, 2249 amd64_emit_const, 2250 amd64_emit_call, 2251 amd64_emit_reg, 2252 amd64_emit_pop, 2253 amd64_emit_stack_flush, 2254 amd64_emit_zero_ext, 2255 amd64_emit_swap, 2256 amd64_emit_stack_adjust, 2257 amd64_emit_int_call_1, 2258 amd64_emit_void_call_2, 2259 amd64_emit_eq_goto, 2260 amd64_emit_ne_goto, 2261 amd64_emit_lt_goto, 2262 amd64_emit_le_goto, 2263 amd64_emit_gt_goto, 2264 amd64_emit_ge_goto 2265 }; 2266 2267 #endif /* __x86_64__ */ 2268 2269 static void 2270 i386_emit_prologue (void) 2271 { 2272 EMIT_ASM32 (i386_prologue, 2273 "push %ebp\n\t" 2274 "mov %esp,%ebp\n\t" 2275 "push %ebx"); 2276 /* At this point, the raw regs base address is at 8(%ebp), and the 2277 value pointer is at 12(%ebp). */ 2278 } 2279 2280 static void 2281 i386_emit_epilogue (void) 2282 { 2283 EMIT_ASM32 (i386_epilogue, 2284 "mov 12(%ebp),%ecx\n\t" 2285 "mov %eax,(%ecx)\n\t" 2286 "mov %ebx,0x4(%ecx)\n\t" 2287 "xor %eax,%eax\n\t" 2288 "pop %ebx\n\t" 2289 "pop %ebp\n\t" 2290 "ret"); 2291 } 2292 2293 static void 2294 i386_emit_add (void) 2295 { 2296 EMIT_ASM32 (i386_add, 2297 "add (%esp),%eax\n\t" 2298 "adc 0x4(%esp),%ebx\n\t" 2299 "lea 0x8(%esp),%esp"); 2300 } 2301 2302 static void 2303 i386_emit_sub (void) 2304 { 2305 EMIT_ASM32 (i386_sub, 2306 "subl %eax,(%esp)\n\t" 2307 "sbbl %ebx,4(%esp)\n\t" 2308 "pop %eax\n\t" 2309 "pop %ebx\n\t"); 2310 } 2311 2312 static void 2313 i386_emit_mul (void) 2314 { 2315 emit_error = 1; 2316 } 2317 2318 static void 2319 i386_emit_lsh (void) 2320 { 2321 emit_error = 1; 2322 } 2323 2324 static void 2325 i386_emit_rsh_signed (void) 2326 { 2327 emit_error = 1; 2328 } 2329 2330 static void 2331 i386_emit_rsh_unsigned (void) 2332 { 2333 emit_error = 1; 2334 } 2335 2336 static void 2337 i386_emit_ext (int arg) 2338 { 2339 switch (arg) 2340 { 2341 case 8: 2342 EMIT_ASM32 (i386_ext_8, 2343 "cbtw\n\t" 2344 "cwtl\n\t" 2345 "movl %eax,%ebx\n\t" 2346 "sarl $31,%ebx"); 2347 break; 2348 case 16: 2349 EMIT_ASM32 (i386_ext_16, 2350 "cwtl\n\t" 2351 "movl %eax,%ebx\n\t" 2352 "sarl $31,%ebx"); 2353 break; 2354 case 32: 2355 EMIT_ASM32 (i386_ext_32, 2356 "movl %eax,%ebx\n\t" 2357 "sarl $31,%ebx"); 2358 break; 2359 default: 2360 emit_error = 1; 2361 } 2362 } 2363 2364 static void 2365 i386_emit_log_not (void) 2366 { 2367 EMIT_ASM32 (i386_log_not, 2368 "or %ebx,%eax\n\t" 2369 "test %eax,%eax\n\t" 2370 "sete %cl\n\t" 2371 "xor %ebx,%ebx\n\t" 2372 "movzbl %cl,%eax"); 2373 } 2374 2375 static void 2376 i386_emit_bit_and (void) 2377 { 2378 EMIT_ASM32 (i386_and, 2379 "and (%esp),%eax\n\t" 2380 "and 0x4(%esp),%ebx\n\t" 2381 "lea 0x8(%esp),%esp"); 2382 } 2383 2384 static void 2385 i386_emit_bit_or (void) 2386 { 2387 EMIT_ASM32 (i386_or, 2388 "or (%esp),%eax\n\t" 2389 "or 0x4(%esp),%ebx\n\t" 2390 "lea 0x8(%esp),%esp"); 2391 } 2392 2393 static void 2394 i386_emit_bit_xor (void) 2395 { 2396 EMIT_ASM32 (i386_xor, 2397 "xor (%esp),%eax\n\t" 2398 "xor 0x4(%esp),%ebx\n\t" 2399 "lea 0x8(%esp),%esp"); 2400 } 2401 2402 static void 2403 i386_emit_bit_not (void) 2404 { 2405 EMIT_ASM32 (i386_bit_not, 2406 "xor $0xffffffff,%eax\n\t" 2407 "xor $0xffffffff,%ebx\n\t"); 2408 } 2409 2410 static void 2411 i386_emit_equal (void) 2412 { 2413 EMIT_ASM32 (i386_equal, 2414 "cmpl %ebx,4(%esp)\n\t" 2415 "jne .Li386_equal_false\n\t" 2416 "cmpl %eax,(%esp)\n\t" 2417 "je .Li386_equal_true\n\t" 2418 ".Li386_equal_false:\n\t" 2419 "xor %eax,%eax\n\t" 2420 "jmp .Li386_equal_end\n\t" 2421 ".Li386_equal_true:\n\t" 2422 "mov $1,%eax\n\t" 2423 ".Li386_equal_end:\n\t" 2424 "xor %ebx,%ebx\n\t" 2425 "lea 0x8(%esp),%esp"); 2426 } 2427 2428 static void 2429 i386_emit_less_signed (void) 2430 { 2431 EMIT_ASM32 (i386_less_signed, 2432 "cmpl %ebx,4(%esp)\n\t" 2433 "jl .Li386_less_signed_true\n\t" 2434 "jne .Li386_less_signed_false\n\t" 2435 "cmpl %eax,(%esp)\n\t" 2436 "jl .Li386_less_signed_true\n\t" 2437 ".Li386_less_signed_false:\n\t" 2438 "xor %eax,%eax\n\t" 2439 "jmp .Li386_less_signed_end\n\t" 2440 ".Li386_less_signed_true:\n\t" 2441 "mov $1,%eax\n\t" 2442 ".Li386_less_signed_end:\n\t" 2443 "xor %ebx,%ebx\n\t" 2444 "lea 0x8(%esp),%esp"); 2445 } 2446 2447 static void 2448 i386_emit_less_unsigned (void) 2449 { 2450 EMIT_ASM32 (i386_less_unsigned, 2451 "cmpl %ebx,4(%esp)\n\t" 2452 "jb .Li386_less_unsigned_true\n\t" 2453 "jne .Li386_less_unsigned_false\n\t" 2454 "cmpl %eax,(%esp)\n\t" 2455 "jb .Li386_less_unsigned_true\n\t" 2456 ".Li386_less_unsigned_false:\n\t" 2457 "xor %eax,%eax\n\t" 2458 "jmp .Li386_less_unsigned_end\n\t" 2459 ".Li386_less_unsigned_true:\n\t" 2460 "mov $1,%eax\n\t" 2461 ".Li386_less_unsigned_end:\n\t" 2462 "xor %ebx,%ebx\n\t" 2463 "lea 0x8(%esp),%esp"); 2464 } 2465 2466 static void 2467 i386_emit_ref (int size) 2468 { 2469 switch (size) 2470 { 2471 case 1: 2472 EMIT_ASM32 (i386_ref1, 2473 "movb (%eax),%al"); 2474 break; 2475 case 2: 2476 EMIT_ASM32 (i386_ref2, 2477 "movw (%eax),%ax"); 2478 break; 2479 case 4: 2480 EMIT_ASM32 (i386_ref4, 2481 "movl (%eax),%eax"); 2482 break; 2483 case 8: 2484 EMIT_ASM32 (i386_ref8, 2485 "movl 4(%eax),%ebx\n\t" 2486 "movl (%eax),%eax"); 2487 break; 2488 } 2489 } 2490 2491 static void 2492 i386_emit_if_goto (int *offset_p, int *size_p) 2493 { 2494 EMIT_ASM32 (i386_if_goto, 2495 "mov %eax,%ecx\n\t" 2496 "or %ebx,%ecx\n\t" 2497 "pop %eax\n\t" 2498 "pop %ebx\n\t" 2499 "cmpl $0,%ecx\n\t" 2500 /* Don't trust the assembler to choose the right jump */ 2501 ".byte 0x0f, 0x85, 0x0, 0x0, 0x0, 0x0"); 2502 2503 if (offset_p) 2504 *offset_p = 11; /* be sure that this matches the sequence above */ 2505 if (size_p) 2506 *size_p = 4; 2507 } 2508 2509 static void 2510 i386_emit_goto (int *offset_p, int *size_p) 2511 { 2512 EMIT_ASM32 (i386_goto, 2513 /* Don't trust the assembler to choose the right jump */ 2514 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0"); 2515 if (offset_p) 2516 *offset_p = 1; 2517 if (size_p) 2518 *size_p = 4; 2519 } 2520 2521 static void 2522 i386_write_goto_address (CORE_ADDR from, CORE_ADDR to, int size) 2523 { 2524 int diff = (to - (from + size)); 2525 unsigned char buf[sizeof (int)]; 2526 2527 /* We're only doing 4-byte sizes at the moment. */ 2528 if (size != 4) 2529 { 2530 emit_error = 1; 2531 return; 2532 } 2533 2534 memcpy (buf, &diff, sizeof (int)); 2535 target_write_memory (from, buf, sizeof (int)); 2536 } 2537 2538 static void 2539 i386_emit_const (LONGEST num) 2540 { 2541 unsigned char buf[16]; 2542 int i, hi, lo; 2543 CORE_ADDR buildaddr = current_insn_ptr; 2544 2545 i = 0; 2546 buf[i++] = 0xb8; /* mov $<n>,%eax */ 2547 lo = num & 0xffffffff; 2548 memcpy (&buf[i], &lo, sizeof (lo)); 2549 i += 4; 2550 hi = ((num >> 32) & 0xffffffff); 2551 if (hi) 2552 { 2553 buf[i++] = 0xbb; /* mov $<n>,%ebx */ 2554 memcpy (&buf[i], &hi, sizeof (hi)); 2555 i += 4; 2556 } 2557 else 2558 { 2559 buf[i++] = 0x31; buf[i++] = 0xdb; /* xor %ebx,%ebx */ 2560 } 2561 append_insns (&buildaddr, i, buf); 2562 current_insn_ptr = buildaddr; 2563 } 2564 2565 static void 2566 i386_emit_call (CORE_ADDR fn) 2567 { 2568 unsigned char buf[16]; 2569 int i, offset; 2570 CORE_ADDR buildaddr; 2571 2572 buildaddr = current_insn_ptr; 2573 i = 0; 2574 buf[i++] = 0xe8; /* call <reladdr> */ 2575 offset = ((int) fn) - (buildaddr + 5); 2576 memcpy (buf + 1, &offset, 4); 2577 append_insns (&buildaddr, 5, buf); 2578 current_insn_ptr = buildaddr; 2579 } 2580 2581 static void 2582 i386_emit_reg (int reg) 2583 { 2584 unsigned char buf[16]; 2585 int i; 2586 CORE_ADDR buildaddr; 2587 2588 EMIT_ASM32 (i386_reg_a, 2589 "sub $0x8,%esp"); 2590 buildaddr = current_insn_ptr; 2591 i = 0; 2592 buf[i++] = 0xb8; /* mov $<n>,%eax */ 2593 memcpy (&buf[i], ®, sizeof (reg)); 2594 i += 4; 2595 append_insns (&buildaddr, i, buf); 2596 current_insn_ptr = buildaddr; 2597 EMIT_ASM32 (i386_reg_b, 2598 "mov %eax,4(%esp)\n\t" 2599 "mov 8(%ebp),%eax\n\t" 2600 "mov %eax,(%esp)"); 2601 i386_emit_call (get_raw_reg_func_addr ()); 2602 EMIT_ASM32 (i386_reg_c, 2603 "xor %ebx,%ebx\n\t" 2604 "lea 0x8(%esp),%esp"); 2605 } 2606 2607 static void 2608 i386_emit_pop (void) 2609 { 2610 EMIT_ASM32 (i386_pop, 2611 "pop %eax\n\t" 2612 "pop %ebx"); 2613 } 2614 2615 static void 2616 i386_emit_stack_flush (void) 2617 { 2618 EMIT_ASM32 (i386_stack_flush, 2619 "push %ebx\n\t" 2620 "push %eax"); 2621 } 2622 2623 static void 2624 i386_emit_zero_ext (int arg) 2625 { 2626 switch (arg) 2627 { 2628 case 8: 2629 EMIT_ASM32 (i386_zero_ext_8, 2630 "and $0xff,%eax\n\t" 2631 "xor %ebx,%ebx"); 2632 break; 2633 case 16: 2634 EMIT_ASM32 (i386_zero_ext_16, 2635 "and $0xffff,%eax\n\t" 2636 "xor %ebx,%ebx"); 2637 break; 2638 case 32: 2639 EMIT_ASM32 (i386_zero_ext_32, 2640 "xor %ebx,%ebx"); 2641 break; 2642 default: 2643 emit_error = 1; 2644 } 2645 } 2646 2647 static void 2648 i386_emit_swap (void) 2649 { 2650 EMIT_ASM32 (i386_swap, 2651 "mov %eax,%ecx\n\t" 2652 "mov %ebx,%edx\n\t" 2653 "pop %eax\n\t" 2654 "pop %ebx\n\t" 2655 "push %edx\n\t" 2656 "push %ecx"); 2657 } 2658 2659 static void 2660 i386_emit_stack_adjust (int n) 2661 { 2662 unsigned char buf[16]; 2663 int i; 2664 CORE_ADDR buildaddr = current_insn_ptr; 2665 2666 i = 0; 2667 buf[i++] = 0x8d; /* lea $<n>(%esp),%esp */ 2668 buf[i++] = 0x64; 2669 buf[i++] = 0x24; 2670 buf[i++] = n * 8; 2671 append_insns (&buildaddr, i, buf); 2672 current_insn_ptr = buildaddr; 2673 } 2674 2675 /* FN's prototype is `LONGEST(*fn)(int)'. */ 2676 2677 static void 2678 i386_emit_int_call_1 (CORE_ADDR fn, int arg1) 2679 { 2680 unsigned char buf[16]; 2681 int i; 2682 CORE_ADDR buildaddr; 2683 2684 EMIT_ASM32 (i386_int_call_1_a, 2685 /* Reserve a bit of stack space. */ 2686 "sub $0x8,%esp"); 2687 /* Put the one argument on the stack. */ 2688 buildaddr = current_insn_ptr; 2689 i = 0; 2690 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ 2691 buf[i++] = 0x04; 2692 buf[i++] = 0x24; 2693 memcpy (&buf[i], &arg1, sizeof (arg1)); 2694 i += 4; 2695 append_insns (&buildaddr, i, buf); 2696 current_insn_ptr = buildaddr; 2697 i386_emit_call (fn); 2698 EMIT_ASM32 (i386_int_call_1_c, 2699 "mov %edx,%ebx\n\t" 2700 "lea 0x8(%esp),%esp"); 2701 } 2702 2703 /* FN's prototype is `void(*fn)(int,LONGEST)'. */ 2704 2705 static void 2706 i386_emit_void_call_2 (CORE_ADDR fn, int arg1) 2707 { 2708 unsigned char buf[16]; 2709 int i; 2710 CORE_ADDR buildaddr; 2711 2712 EMIT_ASM32 (i386_void_call_2_a, 2713 /* Preserve %eax only; we don't have to worry about %ebx. */ 2714 "push %eax\n\t" 2715 /* Reserve a bit of stack space for arguments. */ 2716 "sub $0x10,%esp\n\t" 2717 /* Copy "top" to the second argument position. (Note that 2718 we can't assume function won't scribble on its 2719 arguments, so don't try to restore from this.) */ 2720 "mov %eax,4(%esp)\n\t" 2721 "mov %ebx,8(%esp)"); 2722 /* Put the first argument on the stack. */ 2723 buildaddr = current_insn_ptr; 2724 i = 0; 2725 buf[i++] = 0xc7; /* movl $<arg1>,(%esp) */ 2726 buf[i++] = 0x04; 2727 buf[i++] = 0x24; 2728 memcpy (&buf[i], &arg1, sizeof (arg1)); 2729 i += 4; 2730 append_insns (&buildaddr, i, buf); 2731 current_insn_ptr = buildaddr; 2732 i386_emit_call (fn); 2733 EMIT_ASM32 (i386_void_call_2_b, 2734 "lea 0x10(%esp),%esp\n\t" 2735 /* Restore original stack top. */ 2736 "pop %eax"); 2737 } 2738 2739 2740 static void 2741 i386_emit_eq_goto (int *offset_p, int *size_p) 2742 { 2743 EMIT_ASM32 (eq, 2744 /* Check low half first, more likely to be decider */ 2745 "cmpl %eax,(%esp)\n\t" 2746 "jne .Leq_fallthru\n\t" 2747 "cmpl %ebx,4(%esp)\n\t" 2748 "jne .Leq_fallthru\n\t" 2749 "lea 0x8(%esp),%esp\n\t" 2750 "pop %eax\n\t" 2751 "pop %ebx\n\t" 2752 /* jmp, but don't trust the assembler to choose the right jump */ 2753 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2754 ".Leq_fallthru:\n\t" 2755 "lea 0x8(%esp),%esp\n\t" 2756 "pop %eax\n\t" 2757 "pop %ebx"); 2758 2759 if (offset_p) 2760 *offset_p = 18; 2761 if (size_p) 2762 *size_p = 4; 2763 } 2764 2765 static void 2766 i386_emit_ne_goto (int *offset_p, int *size_p) 2767 { 2768 EMIT_ASM32 (ne, 2769 /* Check low half first, more likely to be decider */ 2770 "cmpl %eax,(%esp)\n\t" 2771 "jne .Lne_jump\n\t" 2772 "cmpl %ebx,4(%esp)\n\t" 2773 "je .Lne_fallthru\n\t" 2774 ".Lne_jump:\n\t" 2775 "lea 0x8(%esp),%esp\n\t" 2776 "pop %eax\n\t" 2777 "pop %ebx\n\t" 2778 /* jmp, but don't trust the assembler to choose the right jump */ 2779 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2780 ".Lne_fallthru:\n\t" 2781 "lea 0x8(%esp),%esp\n\t" 2782 "pop %eax\n\t" 2783 "pop %ebx"); 2784 2785 if (offset_p) 2786 *offset_p = 18; 2787 if (size_p) 2788 *size_p = 4; 2789 } 2790 2791 static void 2792 i386_emit_lt_goto (int *offset_p, int *size_p) 2793 { 2794 EMIT_ASM32 (lt, 2795 "cmpl %ebx,4(%esp)\n\t" 2796 "jl .Llt_jump\n\t" 2797 "jne .Llt_fallthru\n\t" 2798 "cmpl %eax,(%esp)\n\t" 2799 "jnl .Llt_fallthru\n\t" 2800 ".Llt_jump:\n\t" 2801 "lea 0x8(%esp),%esp\n\t" 2802 "pop %eax\n\t" 2803 "pop %ebx\n\t" 2804 /* jmp, but don't trust the assembler to choose the right jump */ 2805 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2806 ".Llt_fallthru:\n\t" 2807 "lea 0x8(%esp),%esp\n\t" 2808 "pop %eax\n\t" 2809 "pop %ebx"); 2810 2811 if (offset_p) 2812 *offset_p = 20; 2813 if (size_p) 2814 *size_p = 4; 2815 } 2816 2817 static void 2818 i386_emit_le_goto (int *offset_p, int *size_p) 2819 { 2820 EMIT_ASM32 (le, 2821 "cmpl %ebx,4(%esp)\n\t" 2822 "jle .Lle_jump\n\t" 2823 "jne .Lle_fallthru\n\t" 2824 "cmpl %eax,(%esp)\n\t" 2825 "jnle .Lle_fallthru\n\t" 2826 ".Lle_jump:\n\t" 2827 "lea 0x8(%esp),%esp\n\t" 2828 "pop %eax\n\t" 2829 "pop %ebx\n\t" 2830 /* jmp, but don't trust the assembler to choose the right jump */ 2831 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2832 ".Lle_fallthru:\n\t" 2833 "lea 0x8(%esp),%esp\n\t" 2834 "pop %eax\n\t" 2835 "pop %ebx"); 2836 2837 if (offset_p) 2838 *offset_p = 20; 2839 if (size_p) 2840 *size_p = 4; 2841 } 2842 2843 static void 2844 i386_emit_gt_goto (int *offset_p, int *size_p) 2845 { 2846 EMIT_ASM32 (gt, 2847 "cmpl %ebx,4(%esp)\n\t" 2848 "jg .Lgt_jump\n\t" 2849 "jne .Lgt_fallthru\n\t" 2850 "cmpl %eax,(%esp)\n\t" 2851 "jng .Lgt_fallthru\n\t" 2852 ".Lgt_jump:\n\t" 2853 "lea 0x8(%esp),%esp\n\t" 2854 "pop %eax\n\t" 2855 "pop %ebx\n\t" 2856 /* jmp, but don't trust the assembler to choose the right jump */ 2857 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2858 ".Lgt_fallthru:\n\t" 2859 "lea 0x8(%esp),%esp\n\t" 2860 "pop %eax\n\t" 2861 "pop %ebx"); 2862 2863 if (offset_p) 2864 *offset_p = 20; 2865 if (size_p) 2866 *size_p = 4; 2867 } 2868 2869 static void 2870 i386_emit_ge_goto (int *offset_p, int *size_p) 2871 { 2872 EMIT_ASM32 (ge, 2873 "cmpl %ebx,4(%esp)\n\t" 2874 "jge .Lge_jump\n\t" 2875 "jne .Lge_fallthru\n\t" 2876 "cmpl %eax,(%esp)\n\t" 2877 "jnge .Lge_fallthru\n\t" 2878 ".Lge_jump:\n\t" 2879 "lea 0x8(%esp),%esp\n\t" 2880 "pop %eax\n\t" 2881 "pop %ebx\n\t" 2882 /* jmp, but don't trust the assembler to choose the right jump */ 2883 ".byte 0xe9, 0x0, 0x0, 0x0, 0x0\n\t" 2884 ".Lge_fallthru:\n\t" 2885 "lea 0x8(%esp),%esp\n\t" 2886 "pop %eax\n\t" 2887 "pop %ebx"); 2888 2889 if (offset_p) 2890 *offset_p = 20; 2891 if (size_p) 2892 *size_p = 4; 2893 } 2894 2895 static emit_ops i386_emit_ops = 2896 { 2897 i386_emit_prologue, 2898 i386_emit_epilogue, 2899 i386_emit_add, 2900 i386_emit_sub, 2901 i386_emit_mul, 2902 i386_emit_lsh, 2903 i386_emit_rsh_signed, 2904 i386_emit_rsh_unsigned, 2905 i386_emit_ext, 2906 i386_emit_log_not, 2907 i386_emit_bit_and, 2908 i386_emit_bit_or, 2909 i386_emit_bit_xor, 2910 i386_emit_bit_not, 2911 i386_emit_equal, 2912 i386_emit_less_signed, 2913 i386_emit_less_unsigned, 2914 i386_emit_ref, 2915 i386_emit_if_goto, 2916 i386_emit_goto, 2917 i386_write_goto_address, 2918 i386_emit_const, 2919 i386_emit_call, 2920 i386_emit_reg, 2921 i386_emit_pop, 2922 i386_emit_stack_flush, 2923 i386_emit_zero_ext, 2924 i386_emit_swap, 2925 i386_emit_stack_adjust, 2926 i386_emit_int_call_1, 2927 i386_emit_void_call_2, 2928 i386_emit_eq_goto, 2929 i386_emit_ne_goto, 2930 i386_emit_lt_goto, 2931 i386_emit_le_goto, 2932 i386_emit_gt_goto, 2933 i386_emit_ge_goto 2934 }; 2935 2936 2937 emit_ops * 2938 x86_target::emit_ops () 2939 { 2940 #ifdef __x86_64__ 2941 if (is_64bit_tdesc (current_thread)) 2942 return &amd64_emit_ops; 2943 else 2944 #endif 2945 return &i386_emit_ops; 2946 } 2947 2948 /* Implementation of target ops method "sw_breakpoint_from_kind". */ 2949 2950 const gdb_byte * 2951 x86_target::sw_breakpoint_from_kind (int kind, int *size) 2952 { 2953 *size = x86_breakpoint_len; 2954 return x86_breakpoint; 2955 } 2956 2957 bool 2958 x86_target::low_supports_range_stepping () 2959 { 2960 return true; 2961 } 2962 2963 int 2964 x86_target::get_ipa_tdesc_idx () 2965 { 2966 struct regcache *regcache = get_thread_regcache (current_thread, 0); 2967 const struct target_desc *tdesc = regcache->tdesc; 2968 2969 #ifdef __x86_64__ 2970 return amd64_get_ipa_tdesc_idx (tdesc); 2971 #endif 2972 2973 if (tdesc == tdesc_i386_linux_no_xml.get ()) 2974 return X86_TDESC_SSE; 2975 2976 return i386_get_ipa_tdesc_idx (tdesc); 2977 } 2978 2979 /* The linux target ops object. */ 2980 2981 linux_process_target *the_linux_target = &the_x86_target; 2982 2983 void 2984 initialize_low_arch (void) 2985 { 2986 /* Initialize the Linux target descriptions. */ 2987 #ifdef __x86_64__ 2988 tdesc_amd64_linux_no_xml = allocate_target_description (); 2989 copy_target_description (tdesc_amd64_linux_no_xml.get (), 2990 amd64_linux_read_description (X86_XSTATE_SSE_MASK, 2991 false)); 2992 tdesc_amd64_linux_no_xml->xmltarget = xmltarget_amd64_linux_no_xml; 2993 #endif 2994 2995 tdesc_i386_linux_no_xml = allocate_target_description (); 2996 copy_target_description (tdesc_i386_linux_no_xml.get (), 2997 i386_linux_read_description (X86_XSTATE_SSE_MASK)); 2998 tdesc_i386_linux_no_xml->xmltarget = xmltarget_i386_linux_no_xml; 2999 3000 initialize_regsets_info (&x86_regsets_info); 3001 } 3002