1 /* Target-dependent code for the ia64. 2 3 Copyright (C) 2004-2024 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef IA64_TDEP_H 21 #define IA64_TDEP_H 22 23 #include "gdbarch.h" 24 25 #ifdef HAVE_LIBUNWIND_IA64_H 26 #include "libunwind-ia64.h" 27 #include "ia64-libunwind-tdep.h" 28 #endif 29 30 /* Register numbers of various important registers. */ 31 32 /* General registers; there are 128 of these 64 bit wide registers. 33 The first 32 are static and the last 96 are stacked. */ 34 #define IA64_GR0_REGNUM 0 35 #define IA64_GR1_REGNUM (IA64_GR0_REGNUM + 1) 36 #define IA64_GR2_REGNUM (IA64_GR0_REGNUM + 2) 37 #define IA64_GR3_REGNUM (IA64_GR0_REGNUM + 3) 38 #define IA64_GR4_REGNUM (IA64_GR0_REGNUM + 4) 39 #define IA64_GR5_REGNUM (IA64_GR0_REGNUM + 5) 40 #define IA64_GR6_REGNUM (IA64_GR0_REGNUM + 6) 41 #define IA64_GR7_REGNUM (IA64_GR0_REGNUM + 7) 42 #define IA64_GR8_REGNUM (IA64_GR0_REGNUM + 8) 43 #define IA64_GR9_REGNUM (IA64_GR0_REGNUM + 9) 44 #define IA64_GR10_REGNUM (IA64_GR0_REGNUM + 10) 45 #define IA64_GR11_REGNUM (IA64_GR0_REGNUM + 11) 46 #define IA64_GR12_REGNUM (IA64_GR0_REGNUM + 12) 47 #define IA64_GR31_REGNUM (IA64_GR0_REGNUM + 31) 48 #define IA64_GR32_REGNUM (IA64_GR0_REGNUM + 32) 49 #define IA64_GR127_REGNUM (IA64_GR0_REGNUM + 127) 50 51 /* Floating point registers; 128 82-bit wide registers. */ 52 #define IA64_FR0_REGNUM 128 53 #define IA64_FR1_REGNUM (IA64_FR0_REGNUM + 1) 54 #define IA64_FR2_REGNUM (IA64_FR0_REGNUM + 2) 55 #define IA64_FR8_REGNUM (IA64_FR0_REGNUM + 8) 56 #define IA64_FR9_REGNUM (IA64_FR0_REGNUM + 9) 57 #define IA64_FR10_REGNUM (IA64_FR0_REGNUM + 10) 58 #define IA64_FR11_REGNUM (IA64_FR0_REGNUM + 11) 59 #define IA64_FR12_REGNUM (IA64_FR0_REGNUM + 12) 60 #define IA64_FR13_REGNUM (IA64_FR0_REGNUM + 13) 61 #define IA64_FR14_REGNUM (IA64_FR0_REGNUM + 14) 62 #define IA64_FR15_REGNUM (IA64_FR0_REGNUM + 15) 63 #define IA64_FR16_REGNUM (IA64_FR0_REGNUM + 16) 64 #define IA64_FR31_REGNUM (IA64_FR0_REGNUM + 31) 65 #define IA64_FR32_REGNUM (IA64_FR0_REGNUM + 32) 66 #define IA64_FR127_REGNUM (IA64_FR0_REGNUM + 127) 67 68 /* Predicate registers; There are 64 of these one bit registers. It'd 69 be more convenient (implementation-wise) to use a single 64 bit 70 word with all of these register in them. Note that there's also a 71 IA64_PR_REGNUM below which contains all the bits and is used for 72 communicating the actual values to the target. */ 73 #define IA64_PR0_REGNUM 256 74 #define IA64_PR1_REGNUM (IA64_PR0_REGNUM + 1) 75 #define IA64_PR2_REGNUM (IA64_PR0_REGNUM + 2) 76 #define IA64_PR3_REGNUM (IA64_PR0_REGNUM + 3) 77 #define IA64_PR4_REGNUM (IA64_PR0_REGNUM + 4) 78 #define IA64_PR5_REGNUM (IA64_PR0_REGNUM + 5) 79 #define IA64_PR6_REGNUM (IA64_PR0_REGNUM + 6) 80 #define IA64_PR7_REGNUM (IA64_PR0_REGNUM + 7) 81 #define IA64_PR8_REGNUM (IA64_PR0_REGNUM + 8) 82 #define IA64_PR9_REGNUM (IA64_PR0_REGNUM + 9) 83 #define IA64_PR10_REGNUM (IA64_PR0_REGNUM + 10) 84 #define IA64_PR11_REGNUM (IA64_PR0_REGNUM + 11) 85 #define IA64_PR12_REGNUM (IA64_PR0_REGNUM + 12) 86 #define IA64_PR13_REGNUM (IA64_PR0_REGNUM + 13) 87 #define IA64_PR14_REGNUM (IA64_PR0_REGNUM + 14) 88 #define IA64_PR15_REGNUM (IA64_PR0_REGNUM + 15) 89 #define IA64_PR16_REGNUM (IA64_PR0_REGNUM + 16) 90 #define IA64_PR17_REGNUM (IA64_PR0_REGNUM + 17) 91 #define IA64_PR18_REGNUM (IA64_PR0_REGNUM + 18) 92 #define IA64_PR19_REGNUM (IA64_PR0_REGNUM + 19) 93 #define IA64_PR20_REGNUM (IA64_PR0_REGNUM + 20) 94 #define IA64_PR21_REGNUM (IA64_PR0_REGNUM + 21) 95 #define IA64_PR22_REGNUM (IA64_PR0_REGNUM + 22) 96 #define IA64_PR23_REGNUM (IA64_PR0_REGNUM + 23) 97 #define IA64_PR24_REGNUM (IA64_PR0_REGNUM + 24) 98 #define IA64_PR25_REGNUM (IA64_PR0_REGNUM + 25) 99 #define IA64_PR26_REGNUM (IA64_PR0_REGNUM + 26) 100 #define IA64_PR27_REGNUM (IA64_PR0_REGNUM + 27) 101 #define IA64_PR28_REGNUM (IA64_PR0_REGNUM + 28) 102 #define IA64_PR29_REGNUM (IA64_PR0_REGNUM + 29) 103 #define IA64_PR30_REGNUM (IA64_PR0_REGNUM + 30) 104 #define IA64_PR31_REGNUM (IA64_PR0_REGNUM + 31) 105 #define IA64_PR32_REGNUM (IA64_PR0_REGNUM + 32) 106 #define IA64_PR33_REGNUM (IA64_PR0_REGNUM + 33) 107 #define IA64_PR34_REGNUM (IA64_PR0_REGNUM + 34) 108 #define IA64_PR35_REGNUM (IA64_PR0_REGNUM + 35) 109 #define IA64_PR36_REGNUM (IA64_PR0_REGNUM + 36) 110 #define IA64_PR37_REGNUM (IA64_PR0_REGNUM + 37) 111 #define IA64_PR38_REGNUM (IA64_PR0_REGNUM + 38) 112 #define IA64_PR39_REGNUM (IA64_PR0_REGNUM + 39) 113 #define IA64_PR40_REGNUM (IA64_PR0_REGNUM + 40) 114 #define IA64_PR41_REGNUM (IA64_PR0_REGNUM + 41) 115 #define IA64_PR42_REGNUM (IA64_PR0_REGNUM + 42) 116 #define IA64_PR43_REGNUM (IA64_PR0_REGNUM + 43) 117 #define IA64_PR44_REGNUM (IA64_PR0_REGNUM + 44) 118 #define IA64_PR45_REGNUM (IA64_PR0_REGNUM + 45) 119 #define IA64_PR46_REGNUM (IA64_PR0_REGNUM + 46) 120 #define IA64_PR47_REGNUM (IA64_PR0_REGNUM + 47) 121 #define IA64_PR48_REGNUM (IA64_PR0_REGNUM + 48) 122 #define IA64_PR49_REGNUM (IA64_PR0_REGNUM + 49) 123 #define IA64_PR50_REGNUM (IA64_PR0_REGNUM + 50) 124 #define IA64_PR51_REGNUM (IA64_PR0_REGNUM + 51) 125 #define IA64_PR52_REGNUM (IA64_PR0_REGNUM + 52) 126 #define IA64_PR53_REGNUM (IA64_PR0_REGNUM + 53) 127 #define IA64_PR54_REGNUM (IA64_PR0_REGNUM + 54) 128 #define IA64_PR55_REGNUM (IA64_PR0_REGNUM + 55) 129 #define IA64_PR56_REGNUM (IA64_PR0_REGNUM + 56) 130 #define IA64_PR57_REGNUM (IA64_PR0_REGNUM + 57) 131 #define IA64_PR58_REGNUM (IA64_PR0_REGNUM + 58) 132 #define IA64_PR59_REGNUM (IA64_PR0_REGNUM + 59) 133 #define IA64_PR60_REGNUM (IA64_PR0_REGNUM + 60) 134 #define IA64_PR61_REGNUM (IA64_PR0_REGNUM + 61) 135 #define IA64_PR62_REGNUM (IA64_PR0_REGNUM + 62) 136 #define IA64_PR63_REGNUM (IA64_PR0_REGNUM + 63) 137 138 /* Branch registers: 8 64-bit registers for holding branch targets. */ 139 #define IA64_BR0_REGNUM 320 140 #define IA64_BR1_REGNUM (IA64_BR0_REGNUM + 1) 141 #define IA64_BR2_REGNUM (IA64_BR0_REGNUM + 2) 142 #define IA64_BR3_REGNUM (IA64_BR0_REGNUM + 3) 143 #define IA64_BR4_REGNUM (IA64_BR0_REGNUM + 4) 144 #define IA64_BR5_REGNUM (IA64_BR0_REGNUM + 5) 145 #define IA64_BR6_REGNUM (IA64_BR0_REGNUM + 6) 146 #define IA64_BR7_REGNUM (IA64_BR0_REGNUM + 7) 147 148 /* Virtual frame pointer; this matches IA64_FRAME_POINTER_REGNUM in 149 gcc/config/ia64/ia64.h. */ 150 #define IA64_VFP_REGNUM 328 151 152 /* Virtual return address pointer; this matches 153 IA64_RETURN_ADDRESS_POINTER_REGNUM in gcc/config/ia64/ia64.h. */ 154 #define IA64_VRAP_REGNUM 329 155 156 /* Predicate registers: There are 64 of these 1-bit registers. We 157 define a single register which is used to communicate these values 158 to/from the target. We will somehow contrive to make it appear 159 that IA64_PR0_REGNUM thru IA64_PR63_REGNUM hold the actual values. */ 160 #define IA64_PR_REGNUM 330 161 162 /* Instruction pointer: 64 bits wide. */ 163 #define IA64_IP_REGNUM 331 164 165 /* Process Status Register. */ 166 #define IA64_PSR_REGNUM 332 167 168 /* Current Frame Marker (raw form may be the cr.ifs). */ 169 #define IA64_CFM_REGNUM 333 170 171 /* Application registers; 128 64-bit wide registers possible, but some 172 of them are reserved. */ 173 #define IA64_AR0_REGNUM 334 174 #define IA64_KR0_REGNUM (IA64_AR0_REGNUM + 0) 175 #define IA64_KR7_REGNUM (IA64_KR0_REGNUM + 7) 176 177 #define IA64_RSC_REGNUM (IA64_AR0_REGNUM + 16) 178 #define IA64_BSP_REGNUM (IA64_AR0_REGNUM + 17) 179 #define IA64_BSPSTORE_REGNUM (IA64_AR0_REGNUM + 18) 180 #define IA64_RNAT_REGNUM (IA64_AR0_REGNUM + 19) 181 #define IA64_FCR_REGNUM (IA64_AR0_REGNUM + 21) 182 #define IA64_EFLAG_REGNUM (IA64_AR0_REGNUM + 24) 183 #define IA64_CSD_REGNUM (IA64_AR0_REGNUM + 25) 184 #define IA64_SSD_REGNUM (IA64_AR0_REGNUM + 26) 185 #define IA64_CFLG_REGNUM (IA64_AR0_REGNUM + 27) 186 #define IA64_FSR_REGNUM (IA64_AR0_REGNUM + 28) 187 #define IA64_FIR_REGNUM (IA64_AR0_REGNUM + 29) 188 #define IA64_FDR_REGNUM (IA64_AR0_REGNUM + 30) 189 #define IA64_CCV_REGNUM (IA64_AR0_REGNUM + 32) 190 #define IA64_UNAT_REGNUM (IA64_AR0_REGNUM + 36) 191 #define IA64_FPSR_REGNUM (IA64_AR0_REGNUM + 40) 192 #define IA64_ITC_REGNUM (IA64_AR0_REGNUM + 44) 193 #define IA64_PFS_REGNUM (IA64_AR0_REGNUM + 64) 194 #define IA64_LC_REGNUM (IA64_AR0_REGNUM + 65) 195 #define IA64_EC_REGNUM (IA64_AR0_REGNUM + 66) 196 197 /* NAT (Not A Thing) Bits for the general registers; there are 128 of 198 these. */ 199 #define IA64_NAT0_REGNUM 462 200 #define IA64_NAT31_REGNUM (IA64_NAT0_REGNUM + 31) 201 #define IA64_NAT32_REGNUM (IA64_NAT0_REGNUM + 32) 202 #define IA64_NAT127_REGNUM (IA64_NAT0_REGNUM + 127) 203 204 class frame_info_ptr; 205 struct regcache; 206 207 /* A struct containing pointers to all the target-dependent operations 208 performed to setup an inferior function call. */ 209 210 struct ia64_infcall_ops 211 { 212 /* Allocate a new register stack frame starting after the output 213 region of the current frame. The new frame will contain SOF 214 registers, all in the output region. This is one way of protecting 215 the stacked registers of the current frame. 216 217 Should do nothing if this operation is not permitted by the OS. */ 218 void (*allocate_new_rse_frame) (struct regcache *regcache, ULONGEST bsp, 219 int sof); 220 221 /* Store the argument stored in BUF into the appropriate location 222 given the BSP and the SLOTNUM. */ 223 void (*store_argument_in_slot) (struct regcache *regcache, CORE_ADDR bsp, 224 int slotnum, gdb_byte *buf); 225 226 /* For targets where we cannot call the function directly, store 227 the address of the function we want to call at the location 228 expected by the calling sequence. */ 229 void (*set_function_addr) (struct regcache *regcache, CORE_ADDR func_addr); 230 }; 231 232 struct ia64_gdbarch_tdep : gdbarch_tdep_base 233 { 234 CORE_ADDR (*sigcontext_register_address) (struct gdbarch *, CORE_ADDR, int) 235 = nullptr; 236 int (*pc_in_sigtramp) (CORE_ADDR) = nullptr; 237 238 /* Return the total size of THIS_FRAME's register frame. 239 CFM is THIS_FRAME's cfm register value. 240 241 Normally, the size of the register frame is always obtained by 242 extracting the lowest 7 bits ("cfm & 0x7f"). */ 243 int (*size_of_register_frame) (const frame_info_ptr &this_frame, ULONGEST cfm) 244 = nullptr; 245 246 /* Determine the function address FADDR belongs to a shared library. 247 If it does, then return the associated global pointer. If no shared 248 library was found to contain that function, then return zero. 249 250 This pointer may be NULL. */ 251 CORE_ADDR (*find_global_pointer_from_solib) (struct gdbarch *gdbarch, 252 CORE_ADDR faddr) = nullptr; 253 254 /* ISA-specific data types. */ 255 struct type *ia64_ext_type = nullptr; 256 257 struct ia64_infcall_ops infcall_ops {}; 258 }; 259 260 extern void ia64_write_pc (struct regcache *, CORE_ADDR); 261 262 #ifdef HAVE_LIBUNWIND_IA64_H 263 extern unw_accessors_t ia64_unw_accessors; 264 extern unw_accessors_t ia64_unw_rse_accessors; 265 extern struct libunwind_descr ia64_libunwind_descr; 266 #endif 267 268 #endif /* ia64-tdep.h */ 269