1 /* This file is part of the program psim. 2 3 Copyright 1994, 1995, 2002 Andrew Cagney <cagney@highland.com.au> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public License 16 along with this program; if not, see <http://www.gnu.org/licenses/>. 17 18 */ 19 20 21 #ifndef _PSIM_CONFIG_H_ 22 #define _PSIM_CONFIG_H_ 23 24 #include "bfd.h" 25 26 /* endianness of the host/target: 27 28 If the build process is aware (at compile time) of the endianness 29 of the host/target it is able to eliminate slower generic endian 30 handling code. 31 32 Possible values are BFD_ENDIAN_UNKNOWN, BFD_ENDIAN_LITTLE, 33 BFD_ENDIAN_BIG. */ 34 35 #ifdef WORDS_BIGENDIAN 36 # define HOST_BYTE_ORDER BFD_ENDIAN_BIG 37 #else 38 # define HOST_BYTE_ORDER BFD_ENDIAN_LITTLE 39 #endif 40 41 #ifndef WITH_TARGET_BYTE_ORDER 42 #define WITH_TARGET_BYTE_ORDER BFD_ENDIAN_UNKNOWN 43 #endif 44 45 extern enum bfd_endian current_target_byte_order; 46 #define CURRENT_TARGET_BYTE_ORDER \ 47 (WITH_TARGET_BYTE_ORDER != BFD_ENDIAN_UNKNOWN \ 48 ? WITH_TARGET_BYTE_ORDER : current_target_byte_order) 49 50 51 /* PowerPC XOR endian. 52 53 In addition to the above, the simulator can support the PowerPC's 54 horrible XOR endian mode. This feature makes it possible to 55 control the endian mode of a processor using the MSR. */ 56 57 #ifndef WITH_XOR_ENDIAN 58 #define WITH_XOR_ENDIAN 8 59 #endif 60 61 62 /* SMP support: 63 64 Sets a limit on the number of processors that can be simulated. If 65 WITH_SMP is set to zero (0), the simulator is restricted to 66 suporting only on processor (and as a consequence leaves the SMP 67 code out of the build process). 68 69 The actual number of processors is taken from the device 70 /options/smp@<nr-cpu> */ 71 72 #ifndef WITH_SMP 73 #define WITH_SMP 5 74 #endif 75 #if WITH_SMP 76 #define MAX_NR_PROCESSORS WITH_SMP 77 #else 78 #define MAX_NR_PROCESSORS 1 79 #endif 80 81 82 /* Word size of target: 83 84 Set these according to your target requirements. At this 85 point in time, I've only compiled (not run) for a 64bit and never 86 built for a 64bit host. This will always remain a compile time 87 option */ 88 89 #ifndef WITH_TARGET_WORD_BITSIZE 90 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */ 91 #endif 92 93 94 /* Program environment: 95 96 Three environments are available - UEA (user), VEA (virtual) and 97 OEA (perating). The former two are environment that users would 98 expect to see (VEA includes things like coherency and the time 99 base) while OEA is what an operating system expects to see. By 100 setting these to specific values, the build process is able to 101 eliminate non relevent environment code 102 103 CURRENT_ENVIRONMENT specifies which of vea or oea is required for 104 the current runtime. */ 105 106 #define ALL_ENVIRONMENT 0 107 #define USER_ENVIRONMENT 1 108 #define VIRTUAL_ENVIRONMENT 2 109 #define OPERATING_ENVIRONMENT 3 110 111 extern int current_environment; 112 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \ 113 ? WITH_ENVIRONMENT \ 114 : current_environment) 115 116 117 /* Optional VEA/OEA code: 118 119 The below, required for the OEA model may also be included in the 120 VEA model however, as far as I can tell only make things 121 slower... */ 122 123 124 /* Events. Devices modeling real H/W need to be able to efficiently 125 schedule things to do at known times in the future. The event 126 queue implements this. Unfortunatly this adds the need to check 127 for any events once each full instruction cycle. */ 128 129 #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT) 130 131 132 /* Time base: 133 134 The PowerPC architecture includes the addition of both a time base 135 register and a decrement timer. Like events adds to the overhead 136 of of some instruction cycles. */ 137 138 #ifndef WITH_TIME_BASE 139 #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT) 140 #endif 141 142 143 /* Callback/Default Memory. 144 145 Core includes a builtin memory type (raw_memory) that is 146 implemented using an array. raw_memory does not require any 147 additional functions etc. 148 149 Callback memory is where the core calls a core device for the data 150 it requires. 151 152 Default memory is an extenstion of this where for addresses that do 153 not map into either a callback or core memory range a default map 154 can be used. 155 156 The OEA model uses callback memory for devices and default memory 157 for buses. 158 159 The VEA model uses callback memory to capture `page faults'. 160 161 While it may be possible to eliminate callback/default memory (and 162 hence also eliminate an additional test per memory fetch) it 163 probably is not worth the effort. 164 165 BTW, while raw_memory could have been implemented as a callback, 166 profiling has shown that there is a biger win (at least for the 167 x86) in eliminating a function call for the most common 168 (raw_memory) case. */ 169 170 #define WITH_CALLBACK_MEMORY 1 171 172 173 /* Alignment: 174 175 The PowerPC may or may not handle miss aligned transfers. An 176 implementation normally handles miss aligned transfers in big 177 endian mode but generates an exception in little endian mode. 178 179 This model. Instead allows both little and big endian modes to 180 either take exceptions or handle miss aligned transfers. 181 182 If 0 is specified then for big-endian mode miss aligned accesses 183 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the 184 processor will fault on them (STRICT_ALIGNMENT). */ 185 186 #define NONSTRICT_ALIGNMENT 1 187 #define STRICT_ALIGNMENT 2 188 189 #ifndef WITH_ALIGNMENT 190 #define WITH_ALIGNMENT 0 191 #endif 192 193 extern int current_alignment; 194 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \ 195 ? WITH_ALIGNMENT \ 196 : current_alignment) 197 198 199 /* Floating point suport: 200 201 Still under development. */ 202 203 #define SOFT_FLOATING_POINT 1 204 #define HARD_FLOATING_POINT 2 205 206 #ifndef WITH_FLOATING_POINT 207 #define WITH_FLOATING_POINT HARD_FLOATING_POINT 208 #endif 209 extern int current_floating_point; 210 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \ 211 ? WITH_FLOATING_POINT \ 212 : current_floating_point) 213 214 215 /* Debugging: 216 217 Control the inclusion of debugging code. */ 218 219 /* include monitoring code */ 220 221 #define MONITOR_INSTRUCTION_ISSUE 1 222 #define MONITOR_LOAD_STORE_UNIT 2 223 #ifndef WITH_MON 224 #define WITH_MON (MONITOR_LOAD_STORE_UNIT \ 225 | MONITOR_INSTRUCTION_ISSUE) 226 #endif 227 228 /* Current CPU model (models are in the generated models.h include file) */ 229 #ifndef WITH_MODEL 230 #define WITH_MODEL 0 231 #endif 232 233 #define CURRENT_MODEL (WITH_MODEL \ 234 ? WITH_MODEL \ 235 : current_model) 236 237 #ifndef WITH_DEFAULT_MODEL 238 #define WITH_DEFAULT_MODEL DEFAULT_MODEL 239 #endif 240 241 #define MODEL_ISSUE_IGNORE (-1) 242 #define MODEL_ISSUE_PROCESS 1 243 244 #ifndef WITH_MODEL_ISSUE 245 #define WITH_MODEL_ISSUE 0 246 #endif 247 248 extern int current_model_issue; 249 #define CURRENT_MODEL_ISSUE (WITH_MODEL_ISSUE \ 250 ? WITH_MODEL_ISSUE \ 251 : current_model_issue) 252 253 /* Whether or not input/output just uses stdio, or uses printf_filtered for 254 output, and polling input for input. */ 255 256 #define DONT_USE_STDIO 2 257 #define DO_USE_STDIO 1 258 259 extern int current_stdio; 260 #define CURRENT_STDIO (WITH_STDIO \ 261 ? WITH_STDIO \ 262 : current_stdio) 263 264 265 266 /* INLINE CODE SELECTION: 267 268 GCC -O3 attempts to inline any function or procedure in scope. The 269 options below facilitate fine grained control over what is and what 270 isn't made inline. For instance it can control things down to a 271 specific modules static routines. Doing this allows the compiler 272 to both eliminate the overhead of function calls and (as a 273 consequence) also eliminate further dead code. 274 275 On a CISC (x86) I've found that I can achieve an order of magnitude 276 speed improvement (x3-x5). In the case of RISC (sparc) while the 277 performance gain isn't as great it is still significant. 278 279 Each module is controled by the macro <module>_INLINE which can 280 have the values described below 281 282 0 Do not inline any thing for the given module 283 284 The following additional values are `bit fields' and can be 285 combined. 286 287 REVEAL_MODULE: 288 289 Include the C file for the module into the file being compiled 290 but do not make the functions within the module inline. 291 292 While of no apparent benefit, this makes it possible for the 293 included module, when compiled to inline its calls to what 294 would otherwize be external functions. 295 296 INLINE_MODULE: 297 298 Make external functions within the module `inline'. Thus if 299 the module is included into a file being compiled, calls to 300 its funtions can be eliminated. 2 implies 1. 301 302 INLINE_LOCALS: 303 304 Make internal (static) functions within the module `inline'. 305 306 The following abreviations are available: 307 308 INCLUDE_MODULE == (REVEAL_MODULE | INLINE_MODULE) 309 310 ALL_C_INLINE == (REVEAL_MODULE | INLINE_MODULE | INLINE_LOCALS) 311 312 In addition to this, modules have been put into two categories. 313 314 Simple modules - eg sim-endian.h bits.h 315 316 Because these modules are small and simple and do not have 317 any complex interpendencies they are configured, if 318 <module>_INLINE is so enabled, to inline themselves in all 319 modules that include those files. 320 321 For the default build, this is a real win as all byte 322 conversion and bit manipulation functions are inlined. 323 324 Complex modules - the rest 325 326 These are all handled using the files inline.h and inline.c. 327 psim.c includes the above which in turn include any remaining 328 code. 329 330 IMPLEMENTATION: 331 332 The inline ability is enabled by prefixing every data / function 333 declaration and definition with one of the following: 334 335 336 INLINE_<module> 337 338 Prefix to any global function that is a candidate for being 339 inline. 340 341 values - `', `static', `static INLINE' 342 343 344 EXTERN_<module> 345 346 Prefix to any global data structures for the module. Global 347 functions that are not to be inlined shall also be prefixed 348 with this. 349 350 values - `', `static', `static' 351 352 353 STATIC_INLINE_<module> 354 355 Prefix to any local (static) function that is a candidate for 356 being made inline. 357 358 values - `static', `static INLINE' 359 360 361 static 362 363 Prefix all local data structures. Local functions that are not 364 to be inlined shall also be prefixed with this. 365 366 values - `static', `static' 367 368 nb: will not work for modules that are being inlined for every 369 use (white lie). 370 371 372 extern 373 #ifndef _INLINE_C_ 374 #endif 375 376 Prefix to any declaration of a global object (function or 377 variable) that should not be inlined and should have only one 378 definition. The #ifndef wrapper goes around the definition 379 propper to ensure that only one copy is generated. 380 381 nb: this will not work when a module is being inlined for every 382 use. 383 384 385 STATIC_<module> 386 387 Replaced by either `static' or `EXTERN_MODULE'. 388 389 390 REALITY CHECK: 391 392 This is not for the faint hearted. I've seen GCC get up to 500mb 393 trying to compile what this can create. 394 395 Some of the modules do not yet implement the WITH_INLINE_STATIC 396 option. Instead they use the macro STATIC_INLINE to control their 397 local function. 398 399 Because of the way that GCC parses __attribute__(), the macro's 400 need to be adjacent to the function name rather than at the start 401 of the line vis: 402 403 int STATIC_INLINE_MODULE f(void); 404 void INLINE_MODULE *g(void); 405 406 */ 407 408 #include "../common/sim-inline.h" 409 #define REVEAL_MODULE H_REVEALS_MODULE 410 #define INLINE_MODULE C_REVEALS_MODULE 411 #define INCLUDE_MODULE (INLINE_MODULE | REVEAL_MODULE) 412 413 /* Your compilers inline reserved word */ 414 415 #ifndef INLINE 416 #if defined(__GNUC__) && defined(__OPTIMIZE__) 417 #define INLINE __inline__ 418 #else 419 #define INLINE /*inline*/ 420 #endif 421 #endif 422 423 424 /* Default prefix for static functions */ 425 426 #ifndef STATIC_INLINE 427 #define STATIC_INLINE static INLINE 428 #endif 429 430 /* Default macro to simplify control several of key the inlines */ 431 432 #ifndef DEFAULT_INLINE 433 #define DEFAULT_INLINE INLINE_LOCALS 434 #endif 435 436 /* Code that converts between hosts and target byte order. Used on 437 every memory access (instruction and data). See sim-endian.h for 438 additional byte swapping configuration information. This module 439 can inline for all callers */ 440 441 #ifndef SIM_ENDIAN_INLINE 442 #define SIM_ENDIAN_INLINE (DEFAULT_INLINE ? ALL_C_INLINE : 0) 443 #endif 444 445 /* Low level bit manipulation routines. This module can inline for all 446 callers */ 447 448 #ifndef BITS_INLINE 449 #define BITS_INLINE (DEFAULT_INLINE ? ALL_C_INLINE : 0) 450 #endif 451 452 /* Code that gives access to various CPU internals such as registers. 453 Used every time an instruction is executed */ 454 455 #ifndef CPU_INLINE 456 #define CPU_INLINE (DEFAULT_INLINE ? ALL_C_INLINE : 0) 457 #endif 458 459 /* Code that translates between an effective and real address. Used 460 by every load or store. */ 461 462 #ifndef VM_INLINE 463 #define VM_INLINE DEFAULT_INLINE 464 #endif 465 466 /* Code that loads/stores data to/from the memory data structure. 467 Used by every load or store */ 468 469 #ifndef CORE_INLINE 470 #define CORE_INLINE DEFAULT_INLINE 471 #endif 472 473 /* Code to check for and process any events scheduled in the future. 474 Called once per instruction cycle */ 475 476 #ifndef EVENTS_INLINE 477 #define EVENTS_INLINE (DEFAULT_INLINE ? ALL_C_INLINE : 0) 478 #endif 479 480 /* Code monotoring the processors performance. It counts events on 481 every instruction cycle */ 482 483 #ifndef MON_INLINE 484 #define MON_INLINE (DEFAULT_INLINE ? ALL_C_INLINE : 0) 485 #endif 486 487 /* Code called on the rare occasions that an interrupt occures. */ 488 489 #ifndef INTERRUPTS_INLINE 490 #define INTERRUPTS_INLINE DEFAULT_INLINE 491 #endif 492 493 /* Code called on the rare occasion that either gdb or the device tree 494 need to manipulate a register within a processor */ 495 496 #ifndef REGISTERS_INLINE 497 #define REGISTERS_INLINE DEFAULT_INLINE 498 #endif 499 500 /* Code called on the rare occasion that a processor is manipulating 501 real hardware instead of RAM. 502 503 Also, most of the functions in devices.c are always called through 504 a jump table. */ 505 506 #ifndef DEVICE_INLINE 507 #define DEVICE_INLINE (DEFAULT_INLINE ? INLINE_LOCALS : 0) 508 #endif 509 510 /* Code called used while the device tree is being built. 511 512 Inlining this is of no benefit */ 513 514 #ifndef TREE_INLINE 515 #define TREE_INLINE (DEFAULT_INLINE ? INLINE_LOCALS : 0) 516 #endif 517 518 /* Code called whenever information on a Special Purpose Register is 519 required. Called by the mflr/mtlr pseudo instructions */ 520 521 #ifndef SPREG_INLINE 522 #define SPREG_INLINE DEFAULT_INLINE 523 #endif 524 525 /* Functions modeling the semantics of each instruction. Two cases to 526 consider, firstly of idecode is implemented with a switch then this 527 allows the idecode function to inline each semantic function 528 (avoiding a call). The second case is when idecode is using a 529 table, even then while the semantic functions can't be inlined, 530 setting it to one still enables each semantic function to inline 531 anything they call (if that code is marked for being inlined). 532 533 WARNING: you need lots (like 200mb of swap) of swap. Setting this 534 to 1 is useful when using a table as it enables the sematic code to 535 inline all of their called functions */ 536 537 #ifndef SEMANTICS_INLINE 538 #define SEMANTICS_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 539 #endif 540 541 /* When using the instruction cache, code to decode an instruction and 542 install it into the cache. Normally called when ever there is a 543 miss in the instruction cache. */ 544 545 #ifndef ICACHE_INLINE 546 #define ICACHE_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 547 #endif 548 549 /* General functions called by semantics functions but part of the 550 instruction table. Although called by the semantic functions the 551 frequency of calls is low. Consequently the need to inline this 552 code is reduced. */ 553 554 #ifndef SUPPORT_INLINE 555 #define SUPPORT_INLINE INLINE_LOCALS 556 #endif 557 558 /* Model specific code used in simulating functional units. Note, it actaully 559 pays NOT to inline the PowerPC model functions (at least on the x86). This 560 is because if it is inlined, each PowerPC instruction gets a separate copy 561 of the code, which is not friendly to the cache. */ 562 563 #ifndef MODEL_INLINE 564 #define MODEL_INLINE (DEFAULT_INLINE & ~INLINE_MODULE) 565 #endif 566 567 /* Code to print out what options we were compiled with. Because this 568 is called at process startup, it doesn't have to be inlined, but 569 if it isn't brought in and the model routines are inline, the model 570 routines will be pulled in twice. */ 571 572 #ifndef OPTIONS_INLINE 573 #define OPTIONS_INLINE MODEL_INLINE 574 #endif 575 576 /* idecode acts as the hub of the system, everything else is imported 577 into this file */ 578 579 #ifndef IDECOCE_INLINE 580 #define IDECODE_INLINE INLINE_LOCALS 581 #endif 582 583 /* psim, isn't actually inlined */ 584 585 #ifndef PSIM_INLINE 586 #define PSIM_INLINE INLINE_LOCALS 587 #endif 588 589 /* Code to emulate os or rom compatibility. This code is called via a 590 table and hence there is little benefit in making it inline */ 591 592 #ifndef OS_EMUL_INLINE 593 #define OS_EMUL_INLINE 0 594 #endif 595 596 #endif /* _PSIM_CONFIG_H */ 597