1 /* MIPS Simulator definition. 2 Copyright (C) 1997-2023 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of the MIPS sim. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef SIM_MAIN_H 21 #define SIM_MAIN_H 22 23 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \ 24 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR)) 25 26 #include "sim-basics.h" 27 #include "sim-base.h" 28 #include "bfd.h" 29 #include "elf-bfd.h" 30 #include "elf/mips.h" 31 32 /* Deprecated macros and types for manipulating 64bit values. Use 33 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */ 34 35 typedef int64_t word64; 36 typedef uint64_t uword64; 37 38 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF) 39 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32) 40 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF) 41 #define SET64HI(t) (((uword64)(t))<<32) 42 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l)))) 43 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l)) 44 45 /* Check if a value will fit within a halfword: */ 46 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1)) 47 48 49 typedef enum { 50 cp0_dmfc0, 51 cp0_dmtc0, 52 cp0_mfc0, 53 cp0_mtc0, 54 cp0_tlbr, 55 cp0_tlbwi, 56 cp0_tlbwr, 57 cp0_tlbp, 58 cp0_cache, 59 cp0_eret, 60 cp0_deret, 61 cp0_rfe 62 } CP0_operation; 63 64 /* Floating-point operations: */ 65 66 #include "sim-fpu.h" 67 #include "cp1.h" 68 69 /* FPU registers must be one of the following types. All other values 70 are reserved (and undefined). */ 71 typedef enum { 72 fmt_single = 0, 73 fmt_double = 1, 74 fmt_word = 4, 75 fmt_long = 5, 76 fmt_ps = 6, 77 /* The following is a special case for FP conditions where only 78 the lower 32bits are considered. This is a HACK. */ 79 fmt_dc32 = 7, 80 /* The following are well outside the normal acceptable format 81 range, and are used in the register status vector. */ 82 fmt_unknown = 0x10000000, 83 fmt_uninterpreted = 0x20000000, 84 fmt_uninterpreted_32 = 0x40000000, 85 fmt_uninterpreted_64 = 0x80000000U, 86 } FP_formats; 87 88 /* For paired word (pw) operations, the opcode representation is fmt_word, 89 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */ 90 #define fmt_pw fmt_long 91 92 /* This should be the COC1 value at the start of the preceding 93 instruction: */ 94 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0) 95 96 #ifdef TARGET_ENABLE_FR 97 /* FIXME: this should be enabled for all targets, but needs testing first. */ 98 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \ 99 ? ((SR & status_FR) ? 64 : 32) \ 100 : (WITH_TARGET_FLOATING_POINT_BITSIZE)) 101 #else 102 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE) 103 #endif 104 105 106 107 108 109 /* HI/LO register accesses */ 110 111 /* For some MIPS targets, the HI/LO registers have certain timing 112 restrictions in that, for instance, a read of a HI register must be 113 separated by at least three instructions from a preceeding read. 114 115 The struct below is used to record the last access by each of A MT, 116 MF or other OP instruction to a HI/LO register. See mips.igen for 117 more details. */ 118 119 typedef struct _hilo_access { 120 int64_t timestamp; 121 address_word cia; 122 } hilo_access; 123 124 typedef struct _hilo_history { 125 hilo_access mt; 126 hilo_access mf; 127 hilo_access op; 128 } hilo_history; 129 130 131 132 133 /* Integer ALU operations: */ 134 135 #include "sim-alu.h" 136 137 #define ALU32_END(ANS) \ 138 if (ALU32_HAD_OVERFLOW) \ 139 SignalExceptionIntegerOverflow (); \ 140 (ANS) = (int32_t) ALU32_OVERFLOW_RESULT 141 142 143 #define ALU64_END(ANS) \ 144 if (ALU64_HAD_OVERFLOW) \ 145 SignalExceptionIntegerOverflow (); \ 146 (ANS) = ALU64_OVERFLOW_RESULT; 147 148 149 150 151 152 /* The following is probably not used for MIPS IV onwards: */ 153 /* Slots for delayed register updates. For the moment we just have a 154 fixed number of slots (rather than a more generic, dynamic 155 system). This keeps the simulator fast. However, we only allow 156 for the register update to be delayed for a single instruction 157 cycle. */ 158 #define PSLOTS (8) /* Maximum number of instruction cycles */ 159 160 typedef struct _pending_write_queue { 161 int in; 162 int out; 163 int total; 164 int slot_delay[PSLOTS]; 165 int slot_size[PSLOTS]; 166 int slot_bit[PSLOTS]; 167 void *slot_dest[PSLOTS]; 168 uint64_t slot_value[PSLOTS]; 169 } pending_write_queue; 170 171 #ifndef PENDING_TRACE 172 #define PENDING_TRACE 0 173 #endif 174 #define PENDING_IN ((CPU)->pending.in) 175 #define PENDING_OUT ((CPU)->pending.out) 176 #define PENDING_TOTAL ((CPU)->pending.total) 177 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size) 178 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit) 179 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay) 180 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest) 181 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value) 182 183 /* Invalidate the pending write queue, all pending writes are 184 discarded. */ 185 186 #define PENDING_INVALIDATE() \ 187 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending)) 188 189 /* Schedule a write to DEST for N cycles time. For 64 bit 190 destinations, schedule two writes. For floating point registers, 191 the caller should schedule a write to both the dest register and 192 the FPR_STATE register. When BIT is non-negative, only BIT of DEST 193 is updated. */ 194 195 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \ 196 do { \ 197 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \ 198 sim_engine_abort (SD, CPU, cia, \ 199 "PENDING_SCHED - buffer overflow\n"); \ 200 if (PENDING_TRACE) \ 201 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \ 202 (unsigned long) cia, (unsigned long) &(DEST), \ 203 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\ 204 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \ 205 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \ 206 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \ 207 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \ 208 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \ 209 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \ 210 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \ 211 PENDING_TOTAL += 1; \ 212 } while (0) 213 214 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1) 215 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT) 216 217 #define PENDING_TICK() pending_tick (SD, CPU, cia) 218 219 #define PENDING_FLUSH() abort () /* think about this one */ 220 #define PENDING_FP() abort () /* think about this one */ 221 222 /* For backward compatibility */ 223 #define PENDING_FILL(R,VAL) \ 224 do { \ 225 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \ 226 { \ 227 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \ 228 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \ 229 } \ 230 else \ 231 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \ 232 } while (0) 233 234 235 enum float_operation 236 { 237 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD, 238 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS, 239 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23 240 }; 241 242 243 /* The internal representation of an MDMX accumulator. 244 Note that 24 and 48 bit accumulator elements are represented in 245 32 or 64 bits. Since the accumulators are 2's complement with 246 overflow suppressed, high-order bits can be ignored in most contexts. */ 247 248 typedef int32_t signed24; 249 typedef int64_t signed48; 250 251 typedef union { 252 signed24 ob[8]; 253 signed48 qh[4]; 254 } MDMX_accumulator; 255 256 257 /* Conventional system arguments. */ 258 #define SIM_STATE sim_cpu *cpu, address_word cia 259 #define SIM_ARGS CPU, cia 260 261 struct _sim_cpu { 262 263 264 /* The following are internal simulator state variables: */ 265 address_word dspc; /* delay-slot PC */ 266 #define DSPC ((CPU)->dspc) 267 268 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET)) 269 #define FORBIDDEN_SLOT() { NIA = forbiddenslot32 (SD_); } 270 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_) 271 272 273 /* State of the simulator */ 274 unsigned int state; 275 unsigned int dsstate; 276 #define STATE ((CPU)->state) 277 #define DSSTATE ((CPU)->dsstate) 278 279 /* Flags in the "state" variable: */ 280 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */ 281 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */ 282 #define simTRACE (1 << 8) /* 1 = trace address activity */ 283 #define simPCOC0 (1 << 17) /* COC[1] from current */ 284 #define simPCOC1 (1 << 18) /* COC[1] from previous */ 285 #define simDELAYSLOT (1 << 24) /* 1 = delay slot entry exists */ 286 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */ 287 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */ 288 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */ 289 #define simFORBIDDENSLOT (1 << 30) /* 1 = n forbidden slot */ 290 291 #ifndef ENGINE_ISSUE_PREFIX_HOOK 292 #define ENGINE_ISSUE_PREFIX_HOOK() \ 293 { \ 294 /* Perform any pending writes */ \ 295 PENDING_TICK(); \ 296 /* Set previous flag, depending on current: */ \ 297 if (STATE & simPCOC0) \ 298 STATE |= simPCOC1; \ 299 else \ 300 STATE &= ~simPCOC1; \ 301 /* and update the current value: */ \ 302 if (GETFCC(0)) \ 303 STATE |= simPCOC0; \ 304 else \ 305 STATE &= ~simPCOC0; \ 306 } 307 #endif /* ENGINE_ISSUE_PREFIX_HOOK */ 308 309 310 /* This is nasty, since we have to rely on matching the register 311 numbers used by GDB. Unfortunately, depending on the MIPS target 312 GDB uses different register numbers. We cannot just include the 313 relevant "gdb/tm.h" link, since GDB may not be configured before 314 the sim world, and also the GDB header file requires too much other 315 state. */ 316 317 #ifndef TM_MIPS_H 318 #define LAST_EMBED_REGNUM (96) 319 #define NUM_REGS (LAST_EMBED_REGNUM + 1) 320 321 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */ 322 #define FCRCS_REGNUM 70 /* FP control/status */ 323 #define FCRIR_REGNUM 71 /* FP implementation/revision */ 324 #endif 325 326 327 /* To keep this default simulator simple, and fast, we use a direct 328 vector of registers. The internal simulator engine then uses 329 manifests to access the correct slot. */ 330 331 unsigned_word registers[LAST_EMBED_REGNUM + 1]; 332 333 int register_widths[NUM_REGS]; 334 #define REGISTERS ((CPU)->registers) 335 336 #define GPR (®ISTERS[0]) 337 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL)) 338 339 #define LO (REGISTERS[33]) 340 #define HI (REGISTERS[34]) 341 #define PCIDX 37 342 #define PC (REGISTERS[PCIDX]) 343 #define CAUSE (REGISTERS[36]) 344 #define SRIDX (32) 345 #define SR (REGISTERS[SRIDX]) /* CPU status register */ 346 #define FCR0IDX (71) 347 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */ 348 #define FCR31IDX (70) 349 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */ 350 #define FCSR (FCR31) 351 #define Debug (REGISTERS[86]) 352 #define DEPC (REGISTERS[87]) 353 #define EPC (REGISTERS[88]) 354 #define ACX (REGISTERS[89]) 355 356 #define AC0LOIDX (33) /* Must be the same register as LO */ 357 #define AC0HIIDX (34) /* Must be the same register as HI */ 358 #define AC1LOIDX (90) 359 #define AC1HIIDX (91) 360 #define AC2LOIDX (92) 361 #define AC2HIIDX (93) 362 #define AC3LOIDX (94) 363 #define AC3HIIDX (95) 364 365 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]]) 366 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]]) 367 368 #define DSPCRIDX (96) /* DSP control register */ 369 #define DSPCR (REGISTERS[DSPCRIDX]) 370 371 #define DSPCR_POS_SHIFT (0) 372 #define DSPCR_POS_MASK (0x3f) 373 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT) 374 375 #define DSPCR_SCOUNT_SHIFT (7) 376 #define DSPCR_SCOUNT_MASK (0x3f) 377 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT) 378 379 #define DSPCR_CARRY_SHIFT (13) 380 #define DSPCR_CARRY_MASK (1) 381 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT) 382 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT) 383 384 #define DSPCR_EFI_SHIFT (14) 385 #define DSPCR_EFI_MASK (1) 386 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT) 387 #define DSPCR_EFI (1 << DSPCR_EFI_MASK) 388 389 #define DSPCR_OUFLAG_SHIFT (16) 390 #define DSPCR_OUFLAG_MASK (0xff) 391 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT) 392 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4)) 393 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5)) 394 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6)) 395 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7)) 396 397 #define DSPCR_CCOND_SHIFT (24) 398 #define DSPCR_CCOND_MASK (0xf) 399 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT) 400 401 /* All internal state modified by signal_exception() that may need to be 402 rolled back for passing moment-of-exception image back to gdb. */ 403 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1]; 404 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1]; 405 int exc_suspended; 406 407 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA) 408 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC) 409 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC) 410 411 unsigned_word c0_config_reg; 412 #define C0_CONFIG ((CPU)->c0_config_reg) 413 414 /* The following are pseudonyms for standard registers */ 415 #define ZERO (REGISTERS[0]) 416 #define V0 (REGISTERS[2]) 417 #define A0 (REGISTERS[4]) 418 #define A1 (REGISTERS[5]) 419 #define A2 (REGISTERS[6]) 420 #define A3 (REGISTERS[7]) 421 #define T8IDX 24 422 #define T8 (REGISTERS[T8IDX]) 423 #define SPIDX 29 424 #define SP (REGISTERS[SPIDX]) 425 #define RAIDX 31 426 #define RA (REGISTERS[RAIDX]) 427 428 /* While space is allocated in the main registers arrray for some of 429 the COP0 registers, that space isn't sufficient. Unknown COP0 430 registers overflow into the array below */ 431 432 #define NR_COP0_GPR 32 433 unsigned_word cop0_gpr[NR_COP0_GPR]; 434 #define COP0_GPR ((CPU)->cop0_gpr) 435 #define COP0_BADVADDR (COP0_GPR[8]) 436 437 /* While space is allocated for the floating point registers in the 438 main registers array, they are stored separatly. This is because 439 their size may not necessarily match the size of either the 440 general-purpose or system specific registers. */ 441 #define NR_FGR (32) 442 #define FGR_BASE FP0_REGNUM 443 fp_word fgr[NR_FGR]; 444 #define FGR ((CPU)->fgr) 445 446 /* Keep the current format state for each register: */ 447 FP_formats fpr_state[32]; 448 #define FPR_STATE ((CPU)->fpr_state) 449 450 pending_write_queue pending; 451 452 /* The MDMX accumulator (used only for MDMX ASE). */ 453 MDMX_accumulator acc; 454 #define ACC ((CPU)->acc) 455 456 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic 457 read-write instructions. It is set when a linked load occurs. It 458 is tested and cleared by the conditional store. It is cleared 459 (during other CPU operations) when a store to the location would 460 no longer be atomic. In particular, it is cleared by exception 461 return instructions. */ 462 int llbit; 463 #define LLBIT ((CPU)->llbit) 464 465 466 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that 467 corruptions caused by using the HI or LO register too close to a 468 following operation is spotted. See mips.igen for more details. */ 469 470 hilo_history hi_history; 471 #define HIHISTORY (&(CPU)->hi_history) 472 hilo_history lo_history; 473 #define LOHISTORY (&(CPU)->lo_history) 474 475 476 sim_cpu_base base; 477 }; 478 479 extern void mips_sim_close (SIM_DESC sd, int quitting); 480 #define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__) 481 482 /* FIXME: At present much of the simulator is still static */ 483 struct mips_sim_state { 484 /* microMIPS ISA mode. */ 485 int isa_mode; 486 }; 487 #define MIPS_SIM_STATE(sd) ((struct mips_sim_state *) STATE_ARCH_DATA (sd)) 488 489 490 /* Status information: */ 491 492 /* TODO : these should be the bitmasks for these bits within the 493 status register. At the moment the following are VR4300 494 bit-positions: */ 495 #define status_KSU_mask (0x18) /* mask for KSU bits */ 496 #define status_KSU_shift (3) /* shift for field */ 497 #define ksu_kernel (0x0) 498 #define ksu_supervisor (0x1) 499 #define ksu_user (0x2) 500 #define ksu_unknown (0x3) 501 502 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift) 503 504 #define status_IE (1 << 0) /* Interrupt enable */ 505 #define status_EIE (1 << 16) /* Enable Interrupt Enable */ 506 #define status_EXL (1 << 1) /* Exception level */ 507 #define status_RE (1 << 25) /* Reverse Endian in user mode */ 508 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */ 509 #define status_SR (1 << 20) /* soft reset or NMI */ 510 #define status_BEV (1 << 22) /* Location of general exception vectors */ 511 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 512 #define status_ERL (1 << 2) /* Error level */ 513 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */ 514 #define status_RP (1 << 27) /* Reduced Power mode */ 515 516 /* Specializations for TX39 family */ 517 #define status_IEc (1 << 0) /* Interrupt enable (current) */ 518 #define status_KUc (1 << 1) /* Kernel/User mode */ 519 #define status_IEp (1 << 2) /* Interrupt enable (previous) */ 520 #define status_KUp (1 << 3) /* Kernel/User mode */ 521 #define status_IEo (1 << 4) /* Interrupt enable (old) */ 522 #define status_KUo (1 << 5) /* Kernel/User mode */ 523 #define status_IM_mask (0xff) /* Interrupt mask */ 524 #define status_IM_shift (8) 525 #define status_NMI (1 << 20) /* NMI */ 526 #define status_NMI (1 << 20) /* NMI */ 527 528 /* Status bits used by MIPS32/MIPS64. */ 529 #define status_UX (1 << 5) /* 64-bit user addrs */ 530 #define status_SX (1 << 6) /* 64-bit supervisor addrs */ 531 #define status_KX (1 << 7) /* 64-bit kernel addrs */ 532 #define status_TS (1 << 21) /* TLB shutdown has occurred */ 533 #define status_PX (1 << 23) /* Enable 64 bit operations */ 534 #define status_MX (1 << 24) /* Enable MDMX resources */ 535 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */ 536 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */ 537 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */ 538 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */ 539 /* Bits reserved for implementations: */ 540 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */ 541 542 /* From R6 onwards, some instructions (e.g. ADDIUPC) change behaviour based 543 * on the Status.UX bits to either sign extend, or act as full 64 bit. */ 544 #define status_optional_EXTEND32(x) ((SR & status_UX) ? x : EXTEND32(x)) 545 546 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */ 547 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */ 548 #define cause_CE_mask 0x30000000 /* Coprocessor exception */ 549 #define cause_CE_shift 28 550 #define cause_EXC2_mask 0x00070000 551 #define cause_EXC2_shift 16 552 #define cause_IP7 (1 << 15) /* Interrupt pending */ 553 #define cause_SIOP (1 << 12) /* SIO pending */ 554 #define cause_IP3 (1 << 11) /* Int 0 pending */ 555 #define cause_IP2 (1 << 10) /* Int 1 pending */ 556 557 #define cause_EXC_mask (0x1c) /* Exception code */ 558 #define cause_EXC_shift (2) 559 560 #define cause_SW0 (1 << 8) /* Software interrupt 0 */ 561 #define cause_SW1 (1 << 9) /* Software interrupt 1 */ 562 #define cause_IP_mask (0x3f) /* Interrupt pending field */ 563 #define cause_IP_shift (10) 564 565 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask) 566 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask) 567 568 569 /* NOTE: We keep the following status flags as bit values (1 for true, 570 0 for false). This allows them to be used in binary boolean 571 operations without worrying about what exactly the non-zero true 572 value is. */ 573 574 /* UserMode */ 575 #ifdef SUBTARGET_R3900 576 #define UserMode ((SR & status_KUc) ? 1 : 0) 577 #else 578 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0) 579 #endif /* SUBTARGET_R3900 */ 580 581 /* BigEndianMem */ 582 /* Hardware configuration. Affects endianness of LoadMemory and 583 StoreMemory and the endianness of Kernel and Supervisor mode 584 execution. The value is 0 for little-endian; 1 for big-endian. */ 585 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BFD_ENDIAN_BIG) 586 /*(state & simBE) ? 1 : 0)*/ 587 588 /* ReverseEndian */ 589 /* This mode is selected if in User mode with the RE bit being set in 590 SR (Status Register). It reverses the endianness of load and store 591 instructions. */ 592 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0) 593 594 /* BigEndianCPU */ 595 /* The endianness for load and store instructions (0=little;1=big). In 596 User mode this endianness may be switched by setting the state_RE 597 bit in the SR register. Thus, BigEndianCPU may be computed as 598 (BigEndianMem EOR ReverseEndian). */ 599 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */ 600 601 602 603 /* Exceptions: */ 604 605 /* NOTE: These numbers depend on the processor architecture being 606 simulated: */ 607 enum ExceptionCause { 608 Interrupt = 0, 609 TLBModification = 1, 610 TLBLoad = 2, 611 TLBStore = 3, 612 AddressLoad = 4, 613 AddressStore = 5, 614 InstructionFetch = 6, 615 DataReference = 7, 616 SystemCall = 8, 617 BreakPoint = 9, 618 ReservedInstruction = 10, 619 CoProcessorUnusable = 11, 620 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */ 621 Trap = 13, 622 FPE = 15, 623 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */ 624 MDMX = 22, 625 Watch = 23, 626 MCheck = 24, 627 CacheErr = 30, 628 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */ 629 630 631 /* The following exception code is actually private to the simulator 632 world. It is *NOT* a processor feature, and is used to signal 633 run-time errors in the simulator. */ 634 SimulatorFault = 0xFFFFFFFF 635 }; 636 637 #define TLB_REFILL (0) 638 #define TLB_INVALID (1) 639 640 641 /* The following break instructions are reserved for use by the 642 simulator. The first is used to halt the simulation. The second 643 is used by gdb for break-points. NOTE: Care must be taken, since 644 this value may be used in later revisions of the MIPS ISA. */ 645 #define HALT_INSTRUCTION_MASK (0x03FFFFC0) 646 647 #define HALT_INSTRUCTION (0x03ff000d) 648 #define HALT_INSTRUCTION2 (0x0000ffcd) 649 650 651 #define BREAKPOINT_INSTRUCTION (0x0005000d) 652 #define BREAKPOINT_INSTRUCTION2 (0x0000014d) 653 654 655 656 void interrupt_event (SIM_DESC sd, void *data); 657 658 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...); 659 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction)) 660 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level) 661 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch) 662 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore) 663 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad) 664 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference) 665 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf) 666 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE) 667 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow) 668 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable) 669 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset) 670 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL) 671 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL) 672 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID) 673 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID) 674 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification) 675 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX) 676 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch) 677 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck) 678 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr) 679 680 /* Co-processor accesses */ 681 682 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */ 683 #define COP_Usable(coproc_num) (coproc_num == 1) 684 685 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword); 686 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword); 687 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 688 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg); 689 690 #define COP_LW(coproc_num,coproc_reg,memword) \ 691 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword) 692 #define COP_LD(coproc_num,coproc_reg,memword) \ 693 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword) 694 #define COP_SW(coproc_num,coproc_reg) \ 695 cop_sw (SD, CPU, cia, coproc_num, coproc_reg) 696 #define COP_SD(coproc_num,coproc_reg) \ 697 cop_sd (SD, CPU, cia, coproc_num, coproc_reg) 698 699 700 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, 701 unsigned int instruction, int coprocnum, CP0_operation op, 702 int rt, int rd, int sel); 703 #define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \ 704 decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \ 705 (rt), (rd), (sel)) 706 707 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg); 708 709 710 /* FPR access. */ 711 uint64_t value_fpr (SIM_STATE, int fpr, FP_formats); 712 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT)) 713 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, uint64_t value); 714 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE)) 715 uint64_t ps_lower (SIM_STATE, uint64_t op); 716 #define PSLower(op) ps_lower (SIM_ARGS, op) 717 uint64_t ps_upper (SIM_STATE, uint64_t op); 718 #define PSUpper(op) ps_upper (SIM_ARGS, op) 719 uint64_t pack_ps (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats from); 720 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single) 721 722 723 /* FCR access. */ 724 unsigned_word value_fcr (SIM_STATE, int fcr); 725 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR)) 726 void store_fcr (SIM_STATE, int fcr, unsigned_word value); 727 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE)) 728 void test_fcsr (SIM_STATE); 729 #define TestFCSR() test_fcsr (SIM_ARGS) 730 731 732 /* FPU operations. */ 733 /* Non-signalling */ 734 #define FP_R6CMP_AF 0x0 735 #define FP_R6CMP_EQ 0x2 736 #define FP_R6CMP_LE 0x6 737 #define FP_R6CMP_LT 0x4 738 #define FP_R6CMP_NE 0x13 739 #define FP_R6CMP_OR 0x11 740 #define FP_R6CMP_UEQ 0x3 741 #define FP_R6CMP_ULE 0x7 742 #define FP_R6CMP_ULT 0x5 743 #define FP_R6CMP_UN 0x1 744 #define FP_R6CMP_UNE 0x12 745 746 /* Signalling */ 747 #define FP_R6CMP_SAF 0x8 748 #define FP_R6CMP_SEQ 0xa 749 #define FP_R6CMP_SLE 0xe 750 #define FP_R6CMP_SLT 0xc 751 #define FP_R6CMP_SNE 0x1b 752 #define FP_R6CMP_SOR 0x19 753 #define FP_R6CMP_SUEQ 0xb 754 #define FP_R6CMP_SULE 0xf 755 #define FP_R6CMP_SULT 0xd 756 #define FP_R6CMP_SUN 0x9 757 #define FP_R6CMP_SUNE 0x1a 758 759 /* FPU Class */ 760 #define FP_R6CLASS_SNAN (1<<0) 761 #define FP_R6CLASS_QNAN (1<<1) 762 #define FP_R6CLASS_NEGINF (1<<2) 763 #define FP_R6CLASS_NEGNORM (1<<3) 764 #define FP_R6CLASS_NEGSUB (1<<4) 765 #define FP_R6CLASS_NEGZERO (1<<5) 766 #define FP_R6CLASS_POSINF (1<<6) 767 #define FP_R6CLASS_POSNORM (1<<7) 768 #define FP_R6CLASS_POSSUB (1<<8) 769 #define FP_R6CLASS_POSZERO (1<<9) 770 771 void fp_cmp (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt, 772 int abs, int cond, int cc); 773 #define Compare(op1,op2,fmt,cond,cc) \ 774 fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc) 775 uint64_t fp_r6_cmp (SIM_STATE, uint64_t op1, uint64_t op2, 776 FP_formats fmt, int cond); 777 #define R6Compare(op1,op2,fmt,cond) fp_r6_cmp(SIM_ARGS, op1, op2, fmt, cond) 778 uint64_t fp_classify(SIM_STATE, uint64_t op, FP_formats fmt); 779 #define Classify(op, fmt) fp_classify(SIM_ARGS, op, fmt) 780 int fp_rint(SIM_STATE, uint64_t op, uint64_t *ans, FP_formats fmt); 781 #define RoundToIntegralExact(op, ans, fmt) fp_rint(SIM_ARGS, op, ans, fmt) 782 uint64_t fp_abs (SIM_STATE, uint64_t op, FP_formats fmt); 783 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt) 784 uint64_t fp_neg (SIM_STATE, uint64_t op, FP_formats fmt); 785 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt) 786 uint64_t fp_add (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 787 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt) 788 uint64_t fp_sub (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 789 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt) 790 uint64_t fp_mul (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 791 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt) 792 uint64_t fp_div (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 793 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt) 794 uint64_t fp_min (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 795 #define Min(op1,op2,fmt) fp_min(SIM_ARGS, op1, op2, fmt) 796 uint64_t fp_max (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 797 #define Max(op1,op2,fmt) fp_max(SIM_ARGS, op1, op2, fmt) 798 uint64_t fp_mina (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 799 #define MinA(op1,op2,fmt) fp_mina(SIM_ARGS, op1, op2, fmt) 800 uint64_t fp_maxa (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 801 #define MaxA(op1,op2,fmt) fp_maxa(SIM_ARGS, op1, op2, fmt) 802 uint64_t fp_recip (SIM_STATE, uint64_t op, FP_formats fmt); 803 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt) 804 uint64_t fp_sqrt (SIM_STATE, uint64_t op, FP_formats fmt); 805 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt) 806 uint64_t fp_rsqrt (SIM_STATE, uint64_t op, FP_formats fmt); 807 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt) 808 uint64_t fp_madd (SIM_STATE, uint64_t op1, uint64_t op2, 809 uint64_t op3, FP_formats fmt); 810 #define FusedMultiplyAdd(op1,op2,op3,fmt) fp_fmadd(SIM_ARGS, op1, op2, op3, fmt) 811 uint64_t fp_fmadd (SIM_STATE, uint64_t op1, uint64_t op2, 812 uint64_t op3, FP_formats fmt); 813 #define FusedMultiplySub(op1,op2,op3,fmt) fp_fmsub(SIM_ARGS, op1, op2, op3, fmt) 814 uint64_t fp_fmsub (SIM_STATE, uint64_t op1, uint64_t op2, 815 uint64_t op3, FP_formats fmt); 816 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt) 817 uint64_t fp_msub (SIM_STATE, uint64_t op1, uint64_t op2, 818 uint64_t op3, FP_formats fmt); 819 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt) 820 uint64_t fp_nmadd (SIM_STATE, uint64_t op1, uint64_t op2, 821 uint64_t op3, FP_formats fmt); 822 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt) 823 uint64_t fp_nmsub (SIM_STATE, uint64_t op1, uint64_t op2, 824 uint64_t op3, FP_formats fmt); 825 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt) 826 uint64_t convert (SIM_STATE, int rm, uint64_t op, FP_formats from, FP_formats to); 827 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to) 828 uint64_t convert_ps (SIM_STATE, int rm, uint64_t op, FP_formats from, 829 FP_formats to); 830 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to) 831 832 833 /* MIPS-3D ASE operations. */ 834 #define CompareAbs(op1,op2,fmt,cond,cc) \ 835 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc) 836 uint64_t fp_add_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 837 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt) 838 uint64_t fp_mul_r (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 839 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt) 840 uint64_t fp_recip1 (SIM_STATE, uint64_t op, FP_formats fmt); 841 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt) 842 uint64_t fp_recip2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 843 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt) 844 uint64_t fp_rsqrt1 (SIM_STATE, uint64_t op, FP_formats fmt); 845 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt) 846 uint64_t fp_rsqrt2 (SIM_STATE, uint64_t op1, uint64_t op2, FP_formats fmt); 847 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt) 848 849 850 /* MDMX access. */ 851 852 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */ 853 #define ob_fmtsel(sel) (((sel)<<1)|0x0) 854 #define qh_fmtsel(sel) (((sel)<<2)|0x1) 855 856 #define fmt_mdmx fmt_uninterpreted 857 858 #define MX_VECT_AND (0) 859 #define MX_VECT_NOR (1) 860 #define MX_VECT_OR (2) 861 #define MX_VECT_XOR (3) 862 #define MX_VECT_SLL (4) 863 #define MX_VECT_SRL (5) 864 #define MX_VECT_ADD (6) 865 #define MX_VECT_SUB (7) 866 #define MX_VECT_MIN (8) 867 #define MX_VECT_MAX (9) 868 #define MX_VECT_MUL (10) 869 #define MX_VECT_MSGN (11) 870 #define MX_VECT_SRA (12) 871 #define MX_VECT_ABSD (13) /* SB-1 only. */ 872 #define MX_VECT_AVG (14) /* SB-1 only. */ 873 874 uint64_t mdmx_cpr_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 875 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel) 876 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel) 877 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel) 878 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel) 879 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel) 880 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel) 881 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel) 882 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel) 883 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel) 884 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel) 885 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel) 886 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel) 887 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel) 888 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel) 889 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel) 890 891 #define MX_C_EQ 0x1 892 #define MX_C_LT 0x4 893 894 void mdmx_cc_op (SIM_STATE, int cond, uint64_t op1, int vt, MX_fmtsel fmtsel); 895 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel) 896 897 uint64_t mdmx_pick_op (SIM_STATE, int tf, uint64_t op1, int vt, MX_fmtsel fmtsel); 898 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel) 899 900 #define MX_VECT_ADDA (0) 901 #define MX_VECT_ADDL (1) 902 #define MX_VECT_MULA (2) 903 #define MX_VECT_MULL (3) 904 #define MX_VECT_MULS (4) 905 #define MX_VECT_MULSL (5) 906 #define MX_VECT_SUBA (6) 907 #define MX_VECT_SUBL (7) 908 #define MX_VECT_ABSDA (8) /* SB-1 only. */ 909 910 void mdmx_acc_op (SIM_STATE, int op, uint64_t op1, int vt, MX_fmtsel fmtsel); 911 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel) 912 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel) 913 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel) 914 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel) 915 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel) 916 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel) 917 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel) 918 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel) 919 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel) 920 921 #define MX_FMT_OB (0) 922 #define MX_FMT_QH (1) 923 924 /* The following codes chosen to indicate the units of shift. */ 925 #define MX_RAC_L (0) 926 #define MX_RAC_M (1) 927 #define MX_RAC_H (2) 928 929 uint64_t mdmx_rac_op (SIM_STATE, int, int); 930 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt) 931 932 void mdmx_wacl (SIM_STATE, int, uint64_t, uint64_t); 933 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt) 934 void mdmx_wach (SIM_STATE, int, uint64_t); 935 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs) 936 937 #define MX_RND_AS (0) 938 #define MX_RND_AU (1) 939 #define MX_RND_ES (2) 940 #define MX_RND_EU (3) 941 #define MX_RND_ZS (4) 942 #define MX_RND_ZU (5) 943 944 uint64_t mdmx_round_op (SIM_STATE, int, int, MX_fmtsel); 945 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt) 946 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt) 947 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt) 948 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt) 949 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt) 950 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt) 951 952 uint64_t mdmx_shuffle (SIM_STATE, int, uint64_t, uint64_t); 953 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2) 954 955 956 957 /* Memory accesses */ 958 959 /* The following are generic to all versions of the MIPS architecture 960 to date: */ 961 962 #define isINSTRUCTION (1 == 0) /* FALSE */ 963 #define isDATA (1 == 1) /* TRUE */ 964 #define isLOAD (1 == 0) /* FALSE */ 965 #define isSTORE (1 == 1) /* TRUE */ 966 #define isREAL (1 == 0) /* FALSE */ 967 #define isRAW (1 == 1) /* TRUE */ 968 /* The parameter HOST (isTARGET / isHOST) is ignored */ 969 #define isTARGET (1 == 0) /* FALSE */ 970 /* #define isHOST (1 == 1) TRUE */ 971 972 /* The "AccessLength" specifications for Loads and Stores. NOTE: This 973 is the number of bytes minus 1. */ 974 #define AccessLength_BYTE (0) 975 #define AccessLength_HALFWORD (1) 976 #define AccessLength_TRIPLEBYTE (2) 977 #define AccessLength_WORD (3) 978 #define AccessLength_QUINTIBYTE (4) 979 #define AccessLength_SEXTIBYTE (5) 980 #define AccessLength_SEPTIBYTE (6) 981 #define AccessLength_DOUBLEWORD (7) 982 #define AccessLength_QUADWORD (15) 983 984 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \ 985 ? AccessLength_DOUBLEWORD /*7*/ \ 986 : AccessLength_WORD /*3*/) 987 988 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD); 989 #define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \ 990 load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD) 991 992 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr); 993 #define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \ 994 store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr) 995 996 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction); 997 #define CacheOp(op,pAddr,vAddr,instruction) \ 998 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction) 999 1000 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype); 1001 #define SyncOperation(stype) \ 1002 sync_operation (SD, CPU, cia, (stype)) 1003 1004 void unpredictable_action (sim_cpu *cpu, address_word cia); 1005 #define NotWordValue(val) not_word_value (SD_, (val)) 1006 #define Unpredictable() unpredictable (SD_) 1007 #define UnpredictableResult() /* For now, do nothing. */ 1008 1009 INLINE_SIM_MAIN (uint32_t) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 1010 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA)) 1011 INLINE_SIM_MAIN (uint16_t) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr); 1012 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1)) 1013 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR)) 1014 #define IMEM32_MICROMIPS(CIA) \ 1015 (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \ 1016 (CIA + 2))) 1017 #define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA))) 1018 1019 #define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10) 1020 1021 #define MICROMIPS_DELAYSLOT_SIZE_ANY 0 1022 #define MICROMIPS_DELAYSLOT_SIZE_16 2 1023 #define MICROMIPS_DELAYSLOT_SIZE_32 4 1024 1025 extern int isa_mode; 1026 1027 #define ISA_MODE_MIPS32 0 1028 #define ISA_MODE_MICROMIPS 1 1029 1030 address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu, 1031 address_word cia, 1032 int instruction_size); 1033 1034 #if WITH_TRACE_ANY_P 1035 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, const char *comment, ...) ATTRIBUTE_PRINTF (7, 8); 1036 extern FILE *tracefh; 1037 #else 1038 #define dotrace(sd, cpu, tracefh, type, address, width, comment, ...) 1039 #endif 1040 1041 extern int DSPLO_REGNUM[4]; 1042 extern int DSPHI_REGNUM[4]; 1043 1044 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia); 1045 extern SIM_CORE_SIGNAL_FN mips_core_signal; 1046 1047 char* pr_addr (SIM_ADDR addr); 1048 char* pr_uword64 (uword64 addr); 1049 1050 1051 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0) 1052 1053 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc); 1054 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception); 1055 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception); 1056 1057 #ifdef MIPS_MACH_MULTI 1058 extern int mips_mach_multi(SIM_DESC sd); 1059 #define MIPS_MACH(SD) mips_mach_multi(SD) 1060 #else 1061 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT 1062 #endif 1063 1064 /* Macros for determining whether a MIPS IV or MIPS V part is subject 1065 to the hi/lo restrictions described in mips.igen. */ 1066 1067 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \ 1068 (MIPS_MACH (SD) != bfd_mach_mips5500) 1069 1070 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \ 1071 (MIPS_MACH (SD) != bfd_mach_mips5500) 1072 1073 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \ 1074 (MIPS_MACH (SD) != bfd_mach_mips5500) 1075 1076 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE) 1077 #include "sim-main.c" 1078 #endif 1079 1080 #endif 1081