1 /* collection of junk waiting time to sort out 2 Copyright (C) 1996-2023 Free Software Foundation, Inc. 3 Contributed by Cygnus Support. 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef M32R_SIM_H 21 #define M32R_SIM_H 22 23 /* GDB register numbers. */ 24 #define PSW_REGNUM 16 25 #define CBR_REGNUM 17 26 #define SPI_REGNUM 18 27 #define SPU_REGNUM 19 28 #define BPC_REGNUM 20 29 #define PC_REGNUM 21 30 #define ACCL_REGNUM 22 31 #define ACCH_REGNUM 23 32 #define ACC1L_REGNUM 24 33 #define ACC1H_REGNUM 25 34 #define BBPSW_REGNUM 26 35 #define BBPC_REGNUM 27 36 #define EVB_REGNUM 28 37 38 extern int m32r_decode_gdb_ctrl_regnum (int); 39 40 /* Cover macros for hardware accesses. 41 FIXME: Eventually move to cgen. */ 42 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0) 43 44 #ifndef GET_H_CR 45 extern USI m32rbf_h_cr_get_handler (SIM_CPU *, UINT); 46 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI); 47 48 #define GET_H_CR(regno) \ 49 XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno)) 50 #define SET_H_CR(regno, val) \ 51 XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val)) 52 #endif 53 54 #ifndef GET_H_PSW 55 extern UQI m32rbf_h_psw_get_handler (SIM_CPU *); 56 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI); 57 58 #define GET_H_PSW() \ 59 XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu) 60 #define SET_H_PSW(val) \ 61 XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val)) 62 #endif 63 64 /* FIXME: These prototypes are necessary because the cgen generated 65 cpu.h, cpux.h and cpu2.h headers do not provide them, and functions 66 which take or return parameters that are larger than an int must be 67 prototyed in order for them to work correctly. 68 69 The correct solution is to fix the code in cgen/sim.scm to generate 70 prototypes for each of the functions it generates. */ 71 extern DI m32rbf_h_accum_get_handler (SIM_CPU *); 72 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI); 73 extern DI m32r2f_h_accums_get_handler (SIM_CPU *, UINT); 74 extern void m32r2f_h_accums_set_handler (SIM_CPU *, UINT, DI); 75 76 #ifndef GET_H_ACCUM 77 #define GET_H_ACCUM() \ 78 XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu) 79 #define SET_H_ACCUM(val) \ 80 XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val)) 81 #endif 82 83 /* Misc. profile data. */ 84 85 typedef struct { 86 /* nop insn slot filler count */ 87 unsigned int fillnop_count; 88 /* number of parallel insns */ 89 unsigned int parallel_count; 90 91 /* FIXME: generalize this to handle all insn lengths, move to common. */ 92 /* number of short insns, not including parallel ones */ 93 unsigned int short_count; 94 /* number of long insns */ 95 unsigned int long_count; 96 97 /* Working area for computing cycle counts. */ 98 unsigned long insn_cycles; /* FIXME: delete */ 99 unsigned long cti_stall; 100 unsigned long load_stall; 101 unsigned long biggest_cycles; 102 103 /* Bitmask of registers loaded by previous insn. */ 104 unsigned int load_regs; 105 /* Bitmask of registers loaded by current insn. */ 106 unsigned int load_regs_pending; 107 } M32R_MISC_PROFILE; 108 109 /* Initialize the working area. */ 110 void m32r_init_insn_cycles (SIM_CPU *, int); 111 /* Update the totals for the insn. */ 112 void m32r_record_insn_cycles (SIM_CPU *, int); 113 114 /* This is invoked by the nop pattern in the .cpu file. */ 115 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \ 116 do { \ 117 if (PROFILE_INSN_P (cpu) \ 118 && (addr & 3) != 0) \ 119 ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \ 120 } while (0) 121 122 /* This is invoked by the execute section of mloop{,x}.in. */ 123 #define PROFILE_COUNT_PARINSNS(cpu) \ 124 do { \ 125 if (PROFILE_INSN_P (cpu)) \ 126 ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \ 127 } while (0) 128 129 /* This is invoked by the execute section of mloop{,x}.in. */ 130 #define PROFILE_COUNT_SHORTINSNS(cpu) \ 131 do { \ 132 if (PROFILE_INSN_P (cpu)) \ 133 ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \ 134 } while (0) 135 136 /* This is invoked by the execute section of mloop{,x}.in. */ 137 #define PROFILE_COUNT_LONGINSNS(cpu) \ 138 do { \ 139 if (PROFILE_INSN_P (cpu)) \ 140 ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \ 141 } while (0) 142 143 #define GETTWI GETTSI 144 #define SETTWI SETTSI 145 146 /* Additional execution support. */ 147 148 149 /* Hardware/device support. 150 ??? Will eventually want to move device stuff to config files. */ 151 152 /* Exception, Interrupt, and Trap addresses */ 153 #define EIT_SYSBREAK_ADDR 0x10 154 #define EIT_RSVD_INSN_ADDR 0x20 155 #define EIT_ADDR_EXCP_ADDR 0x30 156 #define EIT_TRAP_BASE_ADDR 0x40 157 #define EIT_EXTERN_ADDR 0x80 158 #define EIT_RESET_ADDR 0x7ffffff0 159 #define EIT_WAKEUP_ADDR 0x7ffffff0 160 161 /* Special purpose traps. */ 162 #define TRAP_SYSCALL 0 163 #define TRAP_BREAKPOINT 1 164 165 /* Handle the trap insn. */ 166 USI m32r_trap (SIM_CPU *, PCADDR, int); 167 168 #endif /* M32R_SIM_H */ 169