1 /* frv simulator fr400 dependent profiling code. 2 3 Copyright (C) 2001-2023 Free Software Foundation, Inc. 4 Contributed by Red Hat 5 6 This file is part of the GNU simulators. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 /* This must come before any other includes. */ 22 #include "defs.h" 23 24 #define WANT_CPU 25 #define WANT_CPU_FRVBF 26 27 #include "sim-main.h" 28 #include "bfd.h" 29 30 #if WITH_PROFILE_MODEL_P 31 32 #include "profile.h" 33 #include "profile-fr400.h" 34 35 /* These functions get and set flags representing the use of 36 registers/resources. */ 37 static void set_use_not_fp_load (SIM_CPU *, INT); 38 static void set_use_not_media_p4 (SIM_CPU *, INT); 39 static void set_use_not_media_p6 (SIM_CPU *, INT); 40 41 static void set_acc_use_not_media_p2 (SIM_CPU *, INT); 42 static void set_acc_use_not_media_p4 (SIM_CPU *, INT); 43 44 void 45 fr400_reset_gr_flags (SIM_CPU *cpu, INT fr) 46 { 47 set_use_not_gr_complex (cpu, fr); 48 } 49 50 void 51 fr400_reset_fr_flags (SIM_CPU *cpu, INT fr) 52 { 53 set_use_not_fp_load (cpu, fr); 54 set_use_not_media_p4 (cpu, fr); 55 set_use_not_media_p6 (cpu, fr); 56 } 57 58 void 59 fr400_reset_acc_flags (SIM_CPU *cpu, INT acc) 60 { 61 set_acc_use_not_media_p2 (cpu, acc); 62 set_acc_use_not_media_p4 (cpu, acc); 63 } 64 65 static void 66 set_use_is_fp_load (SIM_CPU *cpu, INT fr, INT fr_double) 67 { 68 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 69 if (fr != -1) 70 { 71 fr400_reset_fr_flags (cpu, fr); 72 d->cur_fp_load |= (((DI)1) << fr); 73 } 74 if (fr_double != -1) 75 { 76 fr400_reset_fr_flags (cpu, fr_double); 77 d->cur_fp_load |= (((DI)1) << fr_double); 78 if (fr_double < 63) 79 { 80 fr400_reset_fr_flags (cpu, fr_double + 1); 81 d->cur_fp_load |= (((DI)1) << (fr_double + 1)); 82 } 83 } 84 85 } 86 87 static void 88 set_use_not_fp_load (SIM_CPU *cpu, INT fr) 89 { 90 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 91 if (fr != -1) 92 d->cur_fp_load &= ~(((DI)1) << fr); 93 } 94 95 static int 96 use_is_fp_load (SIM_CPU *cpu, INT fr) 97 { 98 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 99 if (fr != -1) 100 return (d->prev_fp_load >> fr) & 1; 101 return 0; 102 } 103 104 static void 105 set_acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) 106 { 107 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 108 if (acc != -1) 109 { 110 fr400_reset_acc_flags (cpu, acc); 111 d->cur_acc_p2 |= (((DI)1) << acc); 112 } 113 } 114 115 static void 116 set_acc_use_not_media_p2 (SIM_CPU *cpu, INT acc) 117 { 118 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 119 if (acc != -1) 120 d->cur_acc_p2 &= ~(((DI)1) << acc); 121 } 122 123 static int 124 acc_use_is_media_p2 (SIM_CPU *cpu, INT acc) 125 { 126 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 127 if (acc != -1) 128 return d->cur_acc_p2 & (((DI)1) << acc); 129 return 0; 130 } 131 132 static void 133 set_use_is_media_p4 (SIM_CPU *cpu, INT fr) 134 { 135 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 136 if (fr != -1) 137 { 138 fr400_reset_fr_flags (cpu, fr); 139 d->cur_fr_p4 |= (((DI)1) << fr); 140 } 141 } 142 143 static void 144 set_use_not_media_p4 (SIM_CPU *cpu, INT fr) 145 { 146 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 147 if (fr != -1) 148 d->cur_fr_p4 &= ~(((DI)1) << fr); 149 } 150 151 static int 152 use_is_media_p4 (SIM_CPU *cpu, INT fr) 153 { 154 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 155 if (fr != -1) 156 return d->cur_fr_p4 & (((DI)1) << fr); 157 return 0; 158 } 159 160 static void 161 set_acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) 162 { 163 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 164 if (acc != -1) 165 { 166 fr400_reset_acc_flags (cpu, acc); 167 d->cur_acc_p4 |= (((DI)1) << acc); 168 } 169 } 170 171 static void 172 set_acc_use_not_media_p4 (SIM_CPU *cpu, INT acc) 173 { 174 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 175 if (acc != -1) 176 d->cur_acc_p4 &= ~(((DI)1) << acc); 177 } 178 179 #if 0 180 static int 181 acc_use_is_media_p4 (SIM_CPU *cpu, INT acc) 182 { 183 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 184 if (acc != -1) 185 return d->cur_acc_p4 & (((DI)1) << acc); 186 return 0; 187 } 188 #endif 189 190 static void 191 set_use_is_media_p6 (SIM_CPU *cpu, INT fr) 192 { 193 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 194 if (fr != -1) 195 { 196 fr400_reset_fr_flags (cpu, fr); 197 d->cur_fr_p6 |= (((DI)1) << fr); 198 } 199 } 200 201 static void 202 set_use_not_media_p6 (SIM_CPU *cpu, INT fr) 203 { 204 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 205 if (fr != -1) 206 d->cur_fr_p6 &= ~(((DI)1) << fr); 207 } 208 209 static int 210 use_is_media_p6 (SIM_CPU *cpu, INT fr) 211 { 212 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 213 if (fr != -1) 214 return d->cur_fr_p6 & (((DI)1) << fr); 215 return 0; 216 } 217 218 /* Initialize cycle counting for an insn. 219 FIRST_P is non-zero if this is the first insn in a set of parallel 220 insns. */ 221 void 222 fr400_model_insn_before (SIM_CPU *cpu, int first_p) 223 { 224 if (first_p) 225 { 226 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 227 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); 228 ps->cur_gr_complex = ps->prev_gr_complex; 229 d->cur_fp_load = d->prev_fp_load; 230 d->cur_fr_p4 = d->prev_fr_p4; 231 d->cur_fr_p6 = d->prev_fr_p6; 232 d->cur_acc_p2 = d->prev_acc_p2; 233 d->cur_acc_p4 = d->prev_acc_p4; 234 } 235 } 236 237 /* Record the cycles computed for an insn. 238 LAST_P is non-zero if this is the last insn in a set of parallel insns, 239 and we update the total cycle count. 240 CYCLES is the cycle count of the insn. */ 241 void 242 fr400_model_insn_after (SIM_CPU *cpu, int last_p, int cycles) 243 { 244 if (last_p) 245 { 246 MODEL_FR400_DATA *d = CPU_MODEL_DATA (cpu); 247 FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (cpu); 248 ps->prev_gr_complex = ps->cur_gr_complex; 249 d->prev_fp_load = d->cur_fp_load; 250 d->prev_fr_p4 = d->cur_fr_p4; 251 d->prev_fr_p6 = d->cur_fr_p6; 252 d->prev_acc_p2 = d->cur_acc_p2; 253 d->prev_acc_p4 = d->cur_acc_p4; 254 } 255 } 256 257 int 258 frvbf_model_fr400_u_exec (SIM_CPU *cpu, const IDESC *idesc, 259 int unit_num, int referenced) 260 { 261 return idesc->timing->units[unit_num].done; 262 } 263 264 int 265 frvbf_model_fr400_u_integer (SIM_CPU *cpu, const IDESC *idesc, 266 int unit_num, int referenced, 267 INT in_GRi, INT in_GRj, INT out_GRk, 268 INT out_ICCi_1) 269 { 270 /* Modelling for this unit is the same as for fr500. */ 271 return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced, 272 in_GRi, in_GRj, out_GRk, out_ICCi_1); 273 } 274 275 int 276 frvbf_model_fr400_u_imul (SIM_CPU *cpu, const IDESC *idesc, 277 int unit_num, int referenced, 278 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) 279 { 280 /* Modelling for this unit is the same as for fr500. */ 281 return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced, 282 in_GRi, in_GRj, out_GRk, out_ICCi_1); 283 } 284 285 int 286 frvbf_model_fr400_u_idiv (SIM_CPU *cpu, const IDESC *idesc, 287 int unit_num, int referenced, 288 INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1) 289 { 290 int cycles; 291 FRV_VLIW *vliw; 292 int slot; 293 294 /* icc0-icc4 are the upper 4 fields of the CCR. */ 295 if (out_ICCi_1 >= 0) 296 out_ICCi_1 += 4; 297 298 vliw = CPU_VLIW (cpu); 299 slot = vliw->next_slot - 1; 300 slot = (*vliw->current_vliw)[slot] - UNIT_I0; 301 302 if (model_insn == FRV_INSN_MODEL_PASS_1) 303 { 304 /* The entire VLIW insn must wait if there is a dependency on a register 305 which is not ready yet. 306 The latency of the registers may be less than previously recorded, 307 depending on how they were used previously. 308 See Table 13-8 in the LSI. */ 309 if (in_GRi != out_GRk && in_GRi >= 0) 310 { 311 if (use_is_gr_complex (cpu, in_GRi)) 312 decrease_GR_busy (cpu, in_GRi, 1); 313 } 314 if (in_GRj != out_GRk && in_GRj != in_GRi && in_GRj >= 0) 315 { 316 if (use_is_gr_complex (cpu, in_GRj)) 317 decrease_GR_busy (cpu, in_GRj, 1); 318 } 319 vliw_wait_for_GR (cpu, in_GRi); 320 vliw_wait_for_GR (cpu, in_GRj); 321 vliw_wait_for_GR (cpu, out_GRk); 322 vliw_wait_for_CCR (cpu, out_ICCi_1); 323 vliw_wait_for_idiv_resource (cpu, slot); 324 handle_resource_wait (cpu); 325 load_wait_for_GR (cpu, in_GRi); 326 load_wait_for_GR (cpu, in_GRj); 327 load_wait_for_GR (cpu, out_GRk); 328 trace_vliw_wait_cycles (cpu); 329 return 0; 330 } 331 332 /* GRk has a latency of 19 cycles! */ 333 cycles = idesc->timing->units[unit_num].done; 334 update_GR_latency (cpu, out_GRk, cycles + 19); 335 set_use_is_gr_complex (cpu, out_GRk); 336 337 /* ICCi_1 has a latency of 18 cycles. */ 338 update_CCR_latency (cpu, out_ICCi_1, cycles + 18); 339 340 /* the idiv resource has a latency of 18 cycles! */ 341 update_idiv_resource_latency (cpu, slot, cycles + 18); 342 343 return cycles; 344 } 345 346 int 347 frvbf_model_fr400_u_branch (SIM_CPU *cpu, const IDESC *idesc, 348 int unit_num, int referenced, 349 INT in_GRi, INT in_GRj, 350 INT in_ICCi_2, INT in_ICCi_3) 351 { 352 #define BRANCH_PREDICTED(ps) ((ps)->branch_hint & 2) 353 FRV_PROFILE_STATE *ps; 354 int cycles; 355 356 if (model_insn == FRV_INSN_MODEL_PASS_1) 357 { 358 /* Modelling for this unit is the same as for fr500 in pass 1. */ 359 return frvbf_model_fr500_u_branch (cpu, idesc, unit_num, referenced, 360 in_GRi, in_GRj, in_ICCi_2, in_ICCi_3); 361 } 362 363 cycles = idesc->timing->units[unit_num].done; 364 365 /* Compute the branch penalty, based on the the prediction and the out 366 come. When counting branches taken or not taken, don't consider branches 367 after the first taken branch in a vliw insn. */ 368 ps = CPU_PROFILE_STATE (cpu); 369 if (! ps->vliw_branch_taken) 370 { 371 int penalty; 372 /* (1 << 4): The pc is the 5th element in inputs, outputs. 373 ??? can be cleaned up */ 374 PROFILE_DATA *p = CPU_PROFILE_DATA (cpu); 375 int taken = (referenced & (1 << 4)) != 0; 376 if (taken) 377 { 378 ++PROFILE_MODEL_TAKEN_COUNT (p); 379 ps->vliw_branch_taken = 1; 380 if (BRANCH_PREDICTED (ps)) 381 penalty = 1; 382 else 383 penalty = 3; 384 } 385 else 386 { 387 ++PROFILE_MODEL_UNTAKEN_COUNT (p); 388 if (BRANCH_PREDICTED (ps)) 389 penalty = 3; 390 else 391 penalty = 0; 392 } 393 if (penalty > 0) 394 { 395 /* Additional 1 cycle penalty if the branch address is not 8 byte 396 aligned. */ 397 if (ps->branch_address & 7) 398 ++penalty; 399 update_branch_penalty (cpu, penalty); 400 PROFILE_MODEL_CTI_STALL_CYCLES (p) += penalty; 401 } 402 } 403 404 return cycles; 405 } 406 407 int 408 frvbf_model_fr400_u_trap (SIM_CPU *cpu, const IDESC *idesc, 409 int unit_num, int referenced, 410 INT in_GRi, INT in_GRj, 411 INT in_ICCi_2, INT in_FCCi_2) 412 { 413 /* Modelling for this unit is the same as for fr500. */ 414 return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced, 415 in_GRi, in_GRj, in_ICCi_2, in_FCCi_2); 416 } 417 418 int 419 frvbf_model_fr400_u_check (SIM_CPU *cpu, const IDESC *idesc, 420 int unit_num, int referenced, 421 INT in_ICCi_3, INT in_FCCi_3) 422 { 423 /* Modelling for this unit is the same as for fr500. */ 424 return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced, 425 in_ICCi_3, in_FCCi_3); 426 } 427 428 int 429 frvbf_model_fr400_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc, 430 int unit_num, int referenced, 431 INT out_GRkhi, INT out_GRklo) 432 { 433 /* Modelling for this unit is the same as for fr500. */ 434 return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced, 435 out_GRkhi, out_GRklo); 436 } 437 438 int 439 frvbf_model_fr400_u_gr_load (SIM_CPU *cpu, const IDESC *idesc, 440 int unit_num, int referenced, 441 INT in_GRi, INT in_GRj, 442 INT out_GRk, INT out_GRdoublek) 443 { 444 /* Modelling for this unit is the same as for fr500. */ 445 return frvbf_model_fr500_u_gr_load (cpu, idesc, unit_num, referenced, 446 in_GRi, in_GRj, out_GRk, out_GRdoublek); 447 } 448 449 int 450 frvbf_model_fr400_u_gr_store (SIM_CPU *cpu, const IDESC *idesc, 451 int unit_num, int referenced, 452 INT in_GRi, INT in_GRj, 453 INT in_GRk, INT in_GRdoublek) 454 { 455 /* Modelling for this unit is the same as for fr500. */ 456 return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced, 457 in_GRi, in_GRj, in_GRk, in_GRdoublek); 458 } 459 460 int 461 frvbf_model_fr400_u_fr_load (SIM_CPU *cpu, const IDESC *idesc, 462 int unit_num, int referenced, 463 INT in_GRi, INT in_GRj, 464 INT out_FRk, INT out_FRdoublek) 465 { 466 int cycles; 467 468 if (model_insn == FRV_INSN_MODEL_PASS_1) 469 { 470 /* Pass 1 is the same as for fr500. */ 471 return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced, 472 in_GRi, in_GRj, out_FRk, 473 out_FRdoublek); 474 } 475 476 cycles = idesc->timing->units[unit_num].done; 477 478 /* The latency of FRk for a load will depend on how long it takes to retrieve 479 the the data from the cache or memory. */ 480 update_FR_latency_for_load (cpu, out_FRk, cycles); 481 update_FRdouble_latency_for_load (cpu, out_FRdoublek, cycles); 482 483 set_use_is_fp_load (cpu, out_FRk, out_FRdoublek); 484 485 return cycles; 486 } 487 488 int 489 frvbf_model_fr400_u_fr_store (SIM_CPU *cpu, const IDESC *idesc, 490 int unit_num, int referenced, 491 INT in_GRi, INT in_GRj, 492 INT in_FRk, INT in_FRdoublek) 493 { 494 int cycles; 495 496 if (model_insn == FRV_INSN_MODEL_PASS_1) 497 { 498 /* The entire VLIW insn must wait if there is a dependency on a register 499 which is not ready yet. 500 The latency of the registers may be less than previously recorded, 501 depending on how they were used previously. 502 See Table 13-8 in the LSI. */ 503 if (in_GRi >= 0) 504 { 505 if (use_is_gr_complex (cpu, in_GRi)) 506 decrease_GR_busy (cpu, in_GRi, 1); 507 } 508 if (in_GRj != in_GRi && in_GRj >= 0) 509 { 510 if (use_is_gr_complex (cpu, in_GRj)) 511 decrease_GR_busy (cpu, in_GRj, 1); 512 } 513 if (in_FRk >= 0) 514 { 515 if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) 516 decrease_FR_busy (cpu, in_FRk, 1); 517 else 518 enforce_full_fr_latency (cpu, in_FRk); 519 } 520 vliw_wait_for_GR (cpu, in_GRi); 521 vliw_wait_for_GR (cpu, in_GRj); 522 vliw_wait_for_FR (cpu, in_FRk); 523 vliw_wait_for_FRdouble (cpu, in_FRdoublek); 524 handle_resource_wait (cpu); 525 load_wait_for_GR (cpu, in_GRi); 526 load_wait_for_GR (cpu, in_GRj); 527 load_wait_for_FR (cpu, in_FRk); 528 load_wait_for_FRdouble (cpu, in_FRdoublek); 529 trace_vliw_wait_cycles (cpu); 530 return 0; 531 } 532 533 cycles = idesc->timing->units[unit_num].done; 534 535 return cycles; 536 } 537 538 int 539 frvbf_model_fr400_u_swap (SIM_CPU *cpu, const IDESC *idesc, 540 int unit_num, int referenced, 541 INT in_GRi, INT in_GRj, INT out_GRk) 542 { 543 /* Modelling for this unit is the same as for fr500. */ 544 return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced, 545 in_GRi, in_GRj, out_GRk); 546 } 547 548 int 549 frvbf_model_fr400_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc, 550 int unit_num, int referenced, 551 INT in_FRk, INT out_GRj) 552 { 553 int cycles; 554 555 if (model_insn == FRV_INSN_MODEL_PASS_1) 556 { 557 /* The entire VLIW insn must wait if there is a dependency on a register 558 which is not ready yet. 559 The latency of the registers may be less than previously recorded, 560 depending on how they were used previously. 561 See Table 13-8 in the LSI. */ 562 if (in_FRk >= 0) 563 { 564 if (use_is_media_p4 (cpu, in_FRk) || use_is_media_p6 (cpu, in_FRk)) 565 decrease_FR_busy (cpu, in_FRk, 1); 566 else 567 enforce_full_fr_latency (cpu, in_FRk); 568 } 569 vliw_wait_for_FR (cpu, in_FRk); 570 vliw_wait_for_GR (cpu, out_GRj); 571 handle_resource_wait (cpu); 572 load_wait_for_FR (cpu, in_FRk); 573 load_wait_for_GR (cpu, out_GRj); 574 trace_vliw_wait_cycles (cpu); 575 return 0; 576 } 577 578 /* The latency of GRj is 2 cycles. */ 579 cycles = idesc->timing->units[unit_num].done; 580 update_GR_latency (cpu, out_GRj, cycles + 2); 581 set_use_is_gr_complex (cpu, out_GRj); 582 583 return cycles; 584 } 585 586 int 587 frvbf_model_fr400_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc, 588 int unit_num, int referenced, 589 INT in_spr, INT out_GRj) 590 { 591 /* Modelling for this unit is the same as for fr500. */ 592 return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced, 593 in_spr, out_GRj); 594 } 595 596 int 597 frvbf_model_fr400_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc, 598 int unit_num, int referenced, 599 INT in_GRj, INT out_FRk) 600 { 601 int cycles; 602 603 if (model_insn == FRV_INSN_MODEL_PASS_1) 604 { 605 /* Pass 1 is the same as for fr500. */ 606 frvbf_model_fr500_u_gr2fr (cpu, idesc, unit_num, referenced, 607 in_GRj, out_FRk); 608 } 609 610 /* The latency of FRk is 1 cycles. */ 611 cycles = idesc->timing->units[unit_num].done; 612 update_FR_latency (cpu, out_FRk, cycles + 1); 613 614 return cycles; 615 } 616 617 int 618 frvbf_model_fr400_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc, 619 int unit_num, int referenced, 620 INT in_GRj, INT out_spr) 621 { 622 /* Modelling for this unit is the same as for fr500. */ 623 return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced, 624 in_GRj, out_spr); 625 } 626 627 int 628 frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, 629 int unit_num, int referenced, 630 INT in_FRi, INT in_FRj, 631 INT out_FRk) 632 { 633 int cycles; 634 FRV_PROFILE_STATE *ps; 635 const CGEN_INSN *insn; 636 int busy_adjustment[] = {0, 0}; 637 int *fr; 638 639 if (model_insn == FRV_INSN_MODEL_PASS_1) 640 return 0; 641 642 /* The preprocessing can execute right away. */ 643 cycles = idesc->timing->units[unit_num].done; 644 645 ps = CPU_PROFILE_STATE (cpu); 646 insn = idesc->idata; 647 648 /* The latency of the registers may be less than previously recorded, 649 depending on how they were used previously. 650 See Table 13-8 in the LSI. */ 651 if (in_FRi >= 0) 652 { 653 if (use_is_fp_load (cpu, in_FRi)) 654 { 655 busy_adjustment[0] = 1; 656 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 657 } 658 else 659 enforce_full_fr_latency (cpu, in_FRi); 660 } 661 if (in_FRj >= 0 && in_FRj != in_FRi) 662 { 663 if (use_is_fp_load (cpu, in_FRj)) 664 { 665 busy_adjustment[1] = 1; 666 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); 667 } 668 else 669 enforce_full_fr_latency (cpu, in_FRj); 670 } 671 672 /* The post processing must wait if there is a dependency on a FR 673 which is not ready yet. */ 674 ps->post_wait = cycles; 675 post_wait_for_FR (cpu, in_FRi); 676 post_wait_for_FR (cpu, in_FRj); 677 post_wait_for_FR (cpu, out_FRk); 678 679 /* Restore the busy cycles of the registers we used. */ 680 fr = ps->fr_busy; 681 if (in_FRi >= 0) 682 fr[in_FRi] += busy_adjustment[0]; 683 if (in_FRj >= 0) 684 fr[in_FRj] += busy_adjustment[1]; 685 686 /* The latency of the output register will be at least the latency of the 687 other inputs. Once initiated, post-processing has no latency. */ 688 if (out_FRk >= 0) 689 { 690 update_FR_latency (cpu, out_FRk, ps->post_wait); 691 update_FR_ptime (cpu, out_FRk, 0); 692 } 693 694 return cycles; 695 } 696 697 int 698 frvbf_model_fr400_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc, 699 int unit_num, int referenced, 700 INT in_FRi, INT in_FRj, 701 INT out_FRk) 702 { 703 int cycles; 704 INT dual_FRi; 705 INT dual_FRj; 706 INT dual_FRk; 707 FRV_PROFILE_STATE *ps; 708 int busy_adjustment[] = {0, 0, 0, 0}; 709 int *fr; 710 711 if (model_insn == FRV_INSN_MODEL_PASS_1) 712 return 0; 713 714 /* The preprocessing can execute right away. */ 715 cycles = idesc->timing->units[unit_num].done; 716 717 ps = CPU_PROFILE_STATE (cpu); 718 dual_FRi = DUAL_REG (in_FRi); 719 dual_FRj = DUAL_REG (in_FRj); 720 dual_FRk = DUAL_REG (out_FRk); 721 722 /* The latency of the registers may be less than previously recorded, 723 depending on how they were used previously. 724 See Table 13-8 in the LSI. */ 725 if (use_is_fp_load (cpu, in_FRi)) 726 { 727 busy_adjustment[0] = 1; 728 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 729 } 730 else 731 enforce_full_fr_latency (cpu, in_FRi); 732 if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) 733 { 734 busy_adjustment[1] = 1; 735 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); 736 } 737 else 738 enforce_full_fr_latency (cpu, dual_FRi); 739 if (in_FRj != in_FRi) 740 { 741 if (use_is_fp_load (cpu, in_FRj)) 742 { 743 busy_adjustment[2] = 1; 744 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); 745 } 746 else 747 enforce_full_fr_latency (cpu, in_FRj); 748 if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) 749 { 750 busy_adjustment[3] = 1; 751 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); 752 } 753 else 754 enforce_full_fr_latency (cpu, dual_FRj); 755 } 756 757 /* The post processing must wait if there is a dependency on a FR 758 which is not ready yet. */ 759 ps->post_wait = cycles; 760 post_wait_for_FR (cpu, in_FRi); 761 post_wait_for_FR (cpu, dual_FRi); 762 post_wait_for_FR (cpu, in_FRj); 763 post_wait_for_FR (cpu, dual_FRj); 764 post_wait_for_FR (cpu, out_FRk); 765 post_wait_for_FR (cpu, dual_FRk); 766 767 /* Restore the busy cycles of the registers we used. */ 768 fr = ps->fr_busy; 769 fr[in_FRi] += busy_adjustment[0]; 770 if (dual_FRi >= 0) 771 fr[dual_FRi] += busy_adjustment[1]; 772 fr[in_FRj] += busy_adjustment[2]; 773 if (dual_FRj >= 0) 774 fr[dual_FRj] += busy_adjustment[3]; 775 776 /* The latency of the output register will be at least the latency of the 777 other inputs. */ 778 update_FR_latency (cpu, out_FRk, ps->post_wait); 779 780 /* Once initiated, post-processing has no latency. */ 781 update_FR_ptime (cpu, out_FRk, 0); 782 783 if (dual_FRk >= 0) 784 { 785 update_FR_latency (cpu, dual_FRk, ps->post_wait); 786 update_FR_ptime (cpu, dual_FRk, 0); 787 } 788 789 return cycles; 790 } 791 792 int 793 frvbf_model_fr400_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc, 794 int unit_num, int referenced, 795 INT out_FRkhi, INT out_FRklo) 796 { 797 int cycles; 798 FRV_PROFILE_STATE *ps; 799 800 if (model_insn == FRV_INSN_MODEL_PASS_1) 801 return 0; 802 803 /* The preprocessing can execute right away. */ 804 cycles = idesc->timing->units[unit_num].done; 805 806 ps = CPU_PROFILE_STATE (cpu); 807 808 /* The post processing must wait if there is a dependency on a FR 809 which is not ready yet. */ 810 ps->post_wait = cycles; 811 post_wait_for_FR (cpu, out_FRkhi); 812 post_wait_for_FR (cpu, out_FRklo); 813 814 /* The latency of the output register will be at least the latency of the 815 other inputs. Once initiated, post-processing has no latency. */ 816 if (out_FRkhi >= 0) 817 { 818 update_FR_latency (cpu, out_FRkhi, ps->post_wait); 819 update_FR_ptime (cpu, out_FRkhi, 0); 820 } 821 if (out_FRklo >= 0) 822 { 823 update_FR_latency (cpu, out_FRklo, ps->post_wait); 824 update_FR_ptime (cpu, out_FRklo, 0); 825 } 826 827 return cycles; 828 } 829 830 int 831 frvbf_model_fr400_u_media_2 (SIM_CPU *cpu, const IDESC *idesc, 832 int unit_num, int referenced, 833 INT in_FRi, INT in_FRj, 834 INT out_ACC40Sk, INT out_ACC40Uk) 835 { 836 int cycles; 837 INT dual_ACC40Sk; 838 INT dual_ACC40Uk; 839 FRV_PROFILE_STATE *ps; 840 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 841 int *fr; 842 int *acc; 843 844 if (model_insn == FRV_INSN_MODEL_PASS_1) 845 return 0; 846 847 /* The preprocessing can execute right away. */ 848 cycles = idesc->timing->units[unit_num].done; 849 850 ps = CPU_PROFILE_STATE (cpu); 851 dual_ACC40Sk = DUAL_REG (out_ACC40Sk); 852 dual_ACC40Uk = DUAL_REG (out_ACC40Uk); 853 854 /* The latency of the registers may be less than previously recorded, 855 depending on how they were used previously. 856 See Table 13-8 in the LSI. */ 857 if (in_FRi >= 0) 858 { 859 if (use_is_fp_load (cpu, in_FRi)) 860 { 861 busy_adjustment[0] = 1; 862 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 863 } 864 else 865 enforce_full_fr_latency (cpu, in_FRi); 866 } 867 if (in_FRj >= 0 && in_FRj != in_FRi) 868 { 869 if (use_is_fp_load (cpu, in_FRj)) 870 { 871 busy_adjustment[1] = 1; 872 decrease_FR_busy (cpu, in_FRj, busy_adjustment[1]); 873 } 874 else 875 enforce_full_fr_latency (cpu, in_FRj); 876 } 877 if (out_ACC40Sk >= 0) 878 { 879 if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) 880 { 881 busy_adjustment[2] = 1; 882 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); 883 } 884 } 885 if (dual_ACC40Sk >= 0) 886 { 887 if (acc_use_is_media_p2 (cpu, dual_ACC40Sk)) 888 { 889 busy_adjustment[3] = 1; 890 decrease_ACC_busy (cpu, dual_ACC40Sk, busy_adjustment[3]); 891 } 892 } 893 if (out_ACC40Uk >= 0) 894 { 895 if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) 896 { 897 busy_adjustment[4] = 1; 898 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); 899 } 900 } 901 if (dual_ACC40Uk >= 0) 902 { 903 if (acc_use_is_media_p2 (cpu, dual_ACC40Uk)) 904 { 905 busy_adjustment[5] = 1; 906 decrease_ACC_busy (cpu, dual_ACC40Uk, busy_adjustment[5]); 907 } 908 } 909 910 /* The post processing must wait if there is a dependency on a FR 911 which is not ready yet. */ 912 ps->post_wait = cycles; 913 post_wait_for_FR (cpu, in_FRi); 914 post_wait_for_FR (cpu, in_FRj); 915 post_wait_for_ACC (cpu, out_ACC40Sk); 916 post_wait_for_ACC (cpu, dual_ACC40Sk); 917 post_wait_for_ACC (cpu, out_ACC40Uk); 918 post_wait_for_ACC (cpu, dual_ACC40Uk); 919 920 /* Restore the busy cycles of the registers we used. */ 921 fr = ps->fr_busy; 922 acc = ps->acc_busy; 923 fr[in_FRi] += busy_adjustment[0]; 924 fr[in_FRj] += busy_adjustment[1]; 925 if (out_ACC40Sk >= 0) 926 acc[out_ACC40Sk] += busy_adjustment[2]; 927 if (dual_ACC40Sk >= 0) 928 acc[dual_ACC40Sk] += busy_adjustment[3]; 929 if (out_ACC40Uk >= 0) 930 acc[out_ACC40Uk] += busy_adjustment[4]; 931 if (dual_ACC40Uk >= 0) 932 acc[dual_ACC40Uk] += busy_adjustment[5]; 933 934 /* The latency of the output register will be at least the latency of the 935 other inputs. Once initiated, post-processing will take 1 cycles. */ 936 if (out_ACC40Sk >= 0) 937 { 938 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 939 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 940 } 941 if (dual_ACC40Sk >= 0) 942 { 943 update_ACC_latency (cpu, dual_ACC40Sk, ps->post_wait + 1); 944 set_acc_use_is_media_p2 (cpu, dual_ACC40Sk); 945 } 946 if (out_ACC40Uk >= 0) 947 { 948 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); 949 set_acc_use_is_media_p2 (cpu, out_ACC40Uk); 950 } 951 if (dual_ACC40Uk >= 0) 952 { 953 update_ACC_latency (cpu, dual_ACC40Uk, ps->post_wait + 1); 954 set_acc_use_is_media_p2 (cpu, dual_ACC40Uk); 955 } 956 957 return cycles; 958 } 959 960 int 961 frvbf_model_fr400_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc, 962 int unit_num, int referenced, 963 INT in_FRi, INT in_FRj, 964 INT out_ACC40Sk, INT out_ACC40Uk) 965 { 966 int cycles; 967 INT dual_FRi; 968 INT dual_FRj; 969 INT ACC40Sk_1; 970 INT ACC40Sk_2; 971 INT ACC40Sk_3; 972 INT ACC40Uk_1; 973 INT ACC40Uk_2; 974 INT ACC40Uk_3; 975 FRV_PROFILE_STATE *ps; 976 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0 ,0}; 977 int *fr; 978 int *acc; 979 980 if (model_insn == FRV_INSN_MODEL_PASS_1) 981 return 0; 982 983 /* The preprocessing can execute right away. */ 984 cycles = idesc->timing->units[unit_num].done; 985 986 dual_FRi = DUAL_REG (in_FRi); 987 dual_FRj = DUAL_REG (in_FRj); 988 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 989 ACC40Sk_2 = DUAL_REG (ACC40Sk_1); 990 ACC40Sk_3 = DUAL_REG (ACC40Sk_2); 991 ACC40Uk_1 = DUAL_REG (out_ACC40Uk); 992 ACC40Uk_2 = DUAL_REG (ACC40Uk_1); 993 ACC40Uk_3 = DUAL_REG (ACC40Uk_2); 994 995 ps = CPU_PROFILE_STATE (cpu); 996 /* The latency of the registers may be less than previously recorded, 997 depending on how they were used previously. 998 See Table 13-8 in the LSI. */ 999 if (use_is_fp_load (cpu, in_FRi)) 1000 { 1001 busy_adjustment[0] = 1; 1002 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 1003 } 1004 else 1005 enforce_full_fr_latency (cpu, in_FRi); 1006 if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) 1007 { 1008 busy_adjustment[1] = 1; 1009 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); 1010 } 1011 else 1012 enforce_full_fr_latency (cpu, dual_FRi); 1013 if (in_FRj != in_FRi) 1014 { 1015 if (use_is_fp_load (cpu, in_FRj)) 1016 { 1017 busy_adjustment[2] = 1; 1018 decrease_FR_busy (cpu, in_FRj, busy_adjustment[2]); 1019 } 1020 else 1021 enforce_full_fr_latency (cpu, in_FRj); 1022 if (dual_FRj >= 0 && use_is_fp_load (cpu, dual_FRj)) 1023 { 1024 busy_adjustment[3] = 1; 1025 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[3]); 1026 } 1027 else 1028 enforce_full_fr_latency (cpu, dual_FRj); 1029 } 1030 if (out_ACC40Sk >= 0) 1031 { 1032 if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) 1033 { 1034 busy_adjustment[4] = 1; 1035 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); 1036 } 1037 if (ACC40Sk_1 >= 0) 1038 { 1039 if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) 1040 { 1041 busy_adjustment[5] = 1; 1042 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); 1043 } 1044 } 1045 if (ACC40Sk_2 >= 0) 1046 { 1047 if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) 1048 { 1049 busy_adjustment[6] = 1; 1050 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); 1051 } 1052 } 1053 if (ACC40Sk_3 >= 0) 1054 { 1055 if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) 1056 { 1057 busy_adjustment[7] = 1; 1058 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); 1059 } 1060 } 1061 } 1062 else if (out_ACC40Uk >= 0) 1063 { 1064 if (acc_use_is_media_p2 (cpu, out_ACC40Uk)) 1065 { 1066 busy_adjustment[4] = 1; 1067 decrease_ACC_busy (cpu, out_ACC40Uk, busy_adjustment[4]); 1068 } 1069 if (ACC40Uk_1 >= 0) 1070 { 1071 if (acc_use_is_media_p2 (cpu, ACC40Uk_1)) 1072 { 1073 busy_adjustment[5] = 1; 1074 decrease_ACC_busy (cpu, ACC40Uk_1, busy_adjustment[5]); 1075 } 1076 } 1077 if (ACC40Uk_2 >= 0) 1078 { 1079 if (acc_use_is_media_p2 (cpu, ACC40Uk_2)) 1080 { 1081 busy_adjustment[6] = 1; 1082 decrease_ACC_busy (cpu, ACC40Uk_2, busy_adjustment[6]); 1083 } 1084 } 1085 if (ACC40Uk_3 >= 0) 1086 { 1087 if (acc_use_is_media_p2 (cpu, ACC40Uk_3)) 1088 { 1089 busy_adjustment[7] = 1; 1090 decrease_ACC_busy (cpu, ACC40Uk_3, busy_adjustment[7]); 1091 } 1092 } 1093 } 1094 1095 /* The post processing must wait if there is a dependency on a FR 1096 which is not ready yet. */ 1097 ps->post_wait = cycles; 1098 post_wait_for_FR (cpu, in_FRi); 1099 post_wait_for_FR (cpu, dual_FRi); 1100 post_wait_for_FR (cpu, in_FRj); 1101 post_wait_for_FR (cpu, dual_FRj); 1102 post_wait_for_ACC (cpu, out_ACC40Sk); 1103 post_wait_for_ACC (cpu, ACC40Sk_1); 1104 post_wait_for_ACC (cpu, ACC40Sk_2); 1105 post_wait_for_ACC (cpu, ACC40Sk_3); 1106 post_wait_for_ACC (cpu, out_ACC40Uk); 1107 post_wait_for_ACC (cpu, ACC40Uk_1); 1108 post_wait_for_ACC (cpu, ACC40Uk_2); 1109 post_wait_for_ACC (cpu, ACC40Uk_3); 1110 1111 /* Restore the busy cycles of the registers we used. */ 1112 fr = ps->fr_busy; 1113 acc = ps->acc_busy; 1114 fr[in_FRi] += busy_adjustment[0]; 1115 if (dual_FRi >= 0) 1116 fr[dual_FRi] += busy_adjustment[1]; 1117 fr[in_FRj] += busy_adjustment[2]; 1118 if (dual_FRj > 0) 1119 fr[dual_FRj] += busy_adjustment[3]; 1120 if (out_ACC40Sk >= 0) 1121 { 1122 acc[out_ACC40Sk] += busy_adjustment[4]; 1123 if (ACC40Sk_1 >= 0) 1124 acc[ACC40Sk_1] += busy_adjustment[5]; 1125 if (ACC40Sk_2 >= 0) 1126 acc[ACC40Sk_2] += busy_adjustment[6]; 1127 if (ACC40Sk_3 >= 0) 1128 acc[ACC40Sk_3] += busy_adjustment[7]; 1129 } 1130 else if (out_ACC40Uk >= 0) 1131 { 1132 acc[out_ACC40Uk] += busy_adjustment[4]; 1133 if (ACC40Uk_1 >= 0) 1134 acc[ACC40Uk_1] += busy_adjustment[5]; 1135 if (ACC40Uk_2 >= 0) 1136 acc[ACC40Uk_2] += busy_adjustment[6]; 1137 if (ACC40Uk_3 >= 0) 1138 acc[ACC40Uk_3] += busy_adjustment[7]; 1139 } 1140 1141 /* The latency of the output register will be at least the latency of the 1142 other inputs. Once initiated, post-processing will take 1 cycle. */ 1143 if (out_ACC40Sk >= 0) 1144 { 1145 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 1146 1147 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 1148 if (ACC40Sk_1 >= 0) 1149 { 1150 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 1151 1152 set_acc_use_is_media_p2 (cpu, ACC40Sk_1); 1153 } 1154 if (ACC40Sk_2 >= 0) 1155 { 1156 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); 1157 1158 set_acc_use_is_media_p2 (cpu, ACC40Sk_2); 1159 } 1160 if (ACC40Sk_3 >= 0) 1161 { 1162 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); 1163 1164 set_acc_use_is_media_p2 (cpu, ACC40Sk_3); 1165 } 1166 } 1167 else if (out_ACC40Uk >= 0) 1168 { 1169 update_ACC_latency (cpu, out_ACC40Uk, ps->post_wait + 1); 1170 1171 set_acc_use_is_media_p2 (cpu, out_ACC40Uk); 1172 if (ACC40Uk_1 >= 0) 1173 { 1174 update_ACC_latency (cpu, ACC40Uk_1, ps->post_wait + 1); 1175 1176 set_acc_use_is_media_p2 (cpu, ACC40Uk_1); 1177 } 1178 if (ACC40Uk_2 >= 0) 1179 { 1180 update_ACC_latency (cpu, ACC40Uk_2, ps->post_wait + 1); 1181 1182 set_acc_use_is_media_p2 (cpu, ACC40Uk_2); 1183 } 1184 if (ACC40Uk_3 >= 0) 1185 { 1186 update_ACC_latency (cpu, ACC40Uk_3, ps->post_wait + 1); 1187 1188 set_acc_use_is_media_p2 (cpu, ACC40Uk_3); 1189 } 1190 } 1191 1192 return cycles; 1193 } 1194 1195 int 1196 frvbf_model_fr400_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc, 1197 int unit_num, int referenced, 1198 INT in_ACC40Si, INT out_ACC40Sk) 1199 { 1200 int cycles; 1201 INT ACC40Si_1; 1202 FRV_PROFILE_STATE *ps; 1203 int busy_adjustment[] = {0, 0, 0}; 1204 int *acc; 1205 1206 if (model_insn == FRV_INSN_MODEL_PASS_1) 1207 return 0; 1208 1209 /* The preprocessing can execute right away. */ 1210 cycles = idesc->timing->units[unit_num].done; 1211 1212 ACC40Si_1 = DUAL_REG (in_ACC40Si); 1213 1214 ps = CPU_PROFILE_STATE (cpu); 1215 /* The latency of the registers may be less than previously recorded, 1216 depending on how they were used previously. 1217 See Table 13-8 in the LSI. */ 1218 if (acc_use_is_media_p2 (cpu, in_ACC40Si)) 1219 { 1220 busy_adjustment[0] = 1; 1221 decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); 1222 } 1223 if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) 1224 { 1225 busy_adjustment[1] = 1; 1226 decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); 1227 } 1228 if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 1229 && acc_use_is_media_p2 (cpu, out_ACC40Sk)) 1230 { 1231 busy_adjustment[2] = 1; 1232 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); 1233 } 1234 1235 /* The post processing must wait if there is a dependency on a register 1236 which is not ready yet. */ 1237 ps->post_wait = cycles; 1238 post_wait_for_ACC (cpu, in_ACC40Si); 1239 post_wait_for_ACC (cpu, ACC40Si_1); 1240 post_wait_for_ACC (cpu, out_ACC40Sk); 1241 1242 /* Restore the busy cycles of the registers we used. */ 1243 acc = ps->acc_busy; 1244 acc[in_ACC40Si] += busy_adjustment[0]; 1245 if (ACC40Si_1 >= 0) 1246 acc[ACC40Si_1] += busy_adjustment[1]; 1247 acc[out_ACC40Sk] += busy_adjustment[2]; 1248 1249 /* The latency of the output register will be at least the latency of the 1250 other inputs. Once initiated, post-processing will take 1 cycle. */ 1251 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 1252 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 1253 1254 return cycles; 1255 } 1256 1257 int 1258 frvbf_model_fr400_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc, 1259 int unit_num, int referenced, 1260 INT in_ACC40Si, INT out_ACC40Sk) 1261 { 1262 int cycles; 1263 INT ACC40Si_1; 1264 INT ACC40Si_2; 1265 INT ACC40Si_3; 1266 INT ACC40Sk_1; 1267 FRV_PROFILE_STATE *ps; 1268 int busy_adjustment[] = {0, 0, 0, 0, 0, 0}; 1269 int *acc; 1270 1271 if (model_insn == FRV_INSN_MODEL_PASS_1) 1272 return 0; 1273 1274 /* The preprocessing can execute right away. */ 1275 cycles = idesc->timing->units[unit_num].done; 1276 1277 ACC40Si_1 = DUAL_REG (in_ACC40Si); 1278 ACC40Si_2 = DUAL_REG (ACC40Si_1); 1279 ACC40Si_3 = DUAL_REG (ACC40Si_2); 1280 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 1281 1282 ps = CPU_PROFILE_STATE (cpu); 1283 /* The latency of the registers may be less than previously recorded, 1284 depending on how they were used previously. 1285 See Table 13-8 in the LSI. */ 1286 if (acc_use_is_media_p2 (cpu, in_ACC40Si)) 1287 { 1288 busy_adjustment[0] = 1; 1289 decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); 1290 } 1291 if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) 1292 { 1293 busy_adjustment[1] = 1; 1294 decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); 1295 } 1296 if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) 1297 { 1298 busy_adjustment[2] = 1; 1299 decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); 1300 } 1301 if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) 1302 { 1303 busy_adjustment[3] = 1; 1304 decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); 1305 } 1306 if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 1307 && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) 1308 { 1309 if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) 1310 { 1311 busy_adjustment[4] = 1; 1312 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); 1313 } 1314 } 1315 if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 1316 && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) 1317 { 1318 if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) 1319 { 1320 busy_adjustment[5] = 1; 1321 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); 1322 } 1323 } 1324 1325 /* The post processing must wait if there is a dependency on a register 1326 which is not ready yet. */ 1327 ps->post_wait = cycles; 1328 post_wait_for_ACC (cpu, in_ACC40Si); 1329 post_wait_for_ACC (cpu, ACC40Si_1); 1330 post_wait_for_ACC (cpu, ACC40Si_2); 1331 post_wait_for_ACC (cpu, ACC40Si_3); 1332 post_wait_for_ACC (cpu, out_ACC40Sk); 1333 post_wait_for_ACC (cpu, ACC40Sk_1); 1334 1335 /* Restore the busy cycles of the registers we used. */ 1336 acc = ps->acc_busy; 1337 acc[in_ACC40Si] += busy_adjustment[0]; 1338 if (ACC40Si_1 >= 0) 1339 acc[ACC40Si_1] += busy_adjustment[1]; 1340 if (ACC40Si_2 >= 0) 1341 acc[ACC40Si_2] += busy_adjustment[2]; 1342 if (ACC40Si_3 >= 0) 1343 acc[ACC40Si_3] += busy_adjustment[3]; 1344 acc[out_ACC40Sk] += busy_adjustment[4]; 1345 if (ACC40Sk_1 >= 0) 1346 acc[ACC40Sk_1] += busy_adjustment[5]; 1347 1348 /* The latency of the output register will be at least the latency of the 1349 other inputs. Once initiated, post-processing will take 1 cycle. */ 1350 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 1351 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 1352 if (ACC40Sk_1 >= 0) 1353 { 1354 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 1355 set_acc_use_is_media_p2 (cpu, ACC40Sk_1); 1356 } 1357 1358 return cycles; 1359 } 1360 1361 int 1362 frvbf_model_fr400_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc, 1363 int unit_num, int referenced, 1364 INT in_ACC40Si, INT out_ACC40Sk) 1365 { 1366 int cycles; 1367 INT ACC40Si_1; 1368 INT ACC40Sk_1; 1369 FRV_PROFILE_STATE *ps; 1370 int busy_adjustment[] = {0, 0, 0, 0}; 1371 int *acc; 1372 1373 if (model_insn == FRV_INSN_MODEL_PASS_1) 1374 return 0; 1375 1376 /* The preprocessing can execute right away. */ 1377 cycles = idesc->timing->units[unit_num].done; 1378 1379 ACC40Si_1 = DUAL_REG (in_ACC40Si); 1380 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 1381 1382 ps = CPU_PROFILE_STATE (cpu); 1383 /* The latency of the registers may be less than previously recorded, 1384 depending on how they were used previously. 1385 See Table 13-8 in the LSI. */ 1386 if (acc_use_is_media_p2 (cpu, in_ACC40Si)) 1387 { 1388 busy_adjustment[0] = 1; 1389 decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); 1390 } 1391 if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) 1392 { 1393 busy_adjustment[1] = 1; 1394 decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); 1395 } 1396 if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1) 1397 { 1398 if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) 1399 { 1400 busy_adjustment[2] = 1; 1401 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[2]); 1402 } 1403 } 1404 if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1) 1405 { 1406 if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) 1407 { 1408 busy_adjustment[3] = 1; 1409 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[3]); 1410 } 1411 } 1412 1413 /* The post processing must wait if there is a dependency on a register 1414 which is not ready yet. */ 1415 ps->post_wait = cycles; 1416 post_wait_for_ACC (cpu, in_ACC40Si); 1417 post_wait_for_ACC (cpu, ACC40Si_1); 1418 post_wait_for_ACC (cpu, out_ACC40Sk); 1419 post_wait_for_ACC (cpu, ACC40Sk_1); 1420 1421 /* Restore the busy cycles of the registers we used. */ 1422 acc = ps->acc_busy; 1423 acc[in_ACC40Si] += busy_adjustment[0]; 1424 if (ACC40Si_1 >= 0) 1425 acc[ACC40Si_1] += busy_adjustment[1]; 1426 acc[out_ACC40Sk] += busy_adjustment[2]; 1427 if (ACC40Sk_1 >= 0) 1428 acc[ACC40Sk_1] += busy_adjustment[3]; 1429 1430 /* The latency of the output register will be at least the latency of the 1431 other inputs. Once initiated, post-processing will take 1 cycle. */ 1432 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 1433 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 1434 if (ACC40Sk_1 >= 0) 1435 { 1436 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 1437 set_acc_use_is_media_p2 (cpu, ACC40Sk_1); 1438 } 1439 1440 return cycles; 1441 } 1442 1443 int 1444 frvbf_model_fr400_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc, 1445 int unit_num, int referenced, 1446 INT in_ACC40Si, INT out_ACC40Sk) 1447 { 1448 int cycles; 1449 INT ACC40Si_1; 1450 INT ACC40Si_2; 1451 INT ACC40Si_3; 1452 INT ACC40Sk_1; 1453 INT ACC40Sk_2; 1454 INT ACC40Sk_3; 1455 FRV_PROFILE_STATE *ps; 1456 int busy_adjustment[] = {0, 0, 0, 0, 0, 0, 0, 0}; 1457 int *acc; 1458 1459 if (model_insn == FRV_INSN_MODEL_PASS_1) 1460 return 0; 1461 1462 /* The preprocessing can execute right away. */ 1463 cycles = idesc->timing->units[unit_num].done; 1464 1465 ACC40Si_1 = DUAL_REG (in_ACC40Si); 1466 ACC40Si_2 = DUAL_REG (ACC40Si_1); 1467 ACC40Si_3 = DUAL_REG (ACC40Si_2); 1468 ACC40Sk_1 = DUAL_REG (out_ACC40Sk); 1469 ACC40Sk_2 = DUAL_REG (ACC40Sk_1); 1470 ACC40Sk_3 = DUAL_REG (ACC40Sk_2); 1471 1472 ps = CPU_PROFILE_STATE (cpu); 1473 /* The latency of the registers may be less than previously recorded, 1474 depending on how they were used previously. 1475 See Table 13-8 in the LSI. */ 1476 if (acc_use_is_media_p2 (cpu, in_ACC40Si)) 1477 { 1478 busy_adjustment[0] = 1; 1479 decrease_ACC_busy (cpu, in_ACC40Si, busy_adjustment[0]); 1480 } 1481 if (ACC40Si_1 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_1)) 1482 { 1483 busy_adjustment[1] = 1; 1484 decrease_ACC_busy (cpu, ACC40Si_1, busy_adjustment[1]); 1485 } 1486 if (ACC40Si_2 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_2)) 1487 { 1488 busy_adjustment[2] = 1; 1489 decrease_ACC_busy (cpu, ACC40Si_2, busy_adjustment[2]); 1490 } 1491 if (ACC40Si_3 >= 0 && acc_use_is_media_p2 (cpu, ACC40Si_3)) 1492 { 1493 busy_adjustment[3] = 1; 1494 decrease_ACC_busy (cpu, ACC40Si_3, busy_adjustment[3]); 1495 } 1496 if (out_ACC40Sk != in_ACC40Si && out_ACC40Sk != ACC40Si_1 1497 && out_ACC40Sk != ACC40Si_2 && out_ACC40Sk != ACC40Si_3) 1498 { 1499 if (acc_use_is_media_p2 (cpu, out_ACC40Sk)) 1500 { 1501 busy_adjustment[4] = 1; 1502 decrease_ACC_busy (cpu, out_ACC40Sk, busy_adjustment[4]); 1503 } 1504 } 1505 if (ACC40Sk_1 != in_ACC40Si && ACC40Sk_1 != ACC40Si_1 1506 && ACC40Sk_1 != ACC40Si_2 && ACC40Sk_1 != ACC40Si_3) 1507 { 1508 if (acc_use_is_media_p2 (cpu, ACC40Sk_1)) 1509 { 1510 busy_adjustment[5] = 1; 1511 decrease_ACC_busy (cpu, ACC40Sk_1, busy_adjustment[5]); 1512 } 1513 } 1514 if (ACC40Sk_2 != in_ACC40Si && ACC40Sk_2 != ACC40Si_1 1515 && ACC40Sk_2 != ACC40Si_2 && ACC40Sk_2 != ACC40Si_3) 1516 { 1517 if (acc_use_is_media_p2 (cpu, ACC40Sk_2)) 1518 { 1519 busy_adjustment[6] = 1; 1520 decrease_ACC_busy (cpu, ACC40Sk_2, busy_adjustment[6]); 1521 } 1522 } 1523 if (ACC40Sk_3 != in_ACC40Si && ACC40Sk_3 != ACC40Si_1 1524 && ACC40Sk_3 != ACC40Si_2 && ACC40Sk_3 != ACC40Si_3) 1525 { 1526 if (acc_use_is_media_p2 (cpu, ACC40Sk_3)) 1527 { 1528 busy_adjustment[7] = 1; 1529 decrease_ACC_busy (cpu, ACC40Sk_3, busy_adjustment[7]); 1530 } 1531 } 1532 1533 /* The post processing must wait if there is a dependency on a register 1534 which is not ready yet. */ 1535 ps->post_wait = cycles; 1536 post_wait_for_ACC (cpu, in_ACC40Si); 1537 post_wait_for_ACC (cpu, ACC40Si_1); 1538 post_wait_for_ACC (cpu, ACC40Si_2); 1539 post_wait_for_ACC (cpu, ACC40Si_3); 1540 post_wait_for_ACC (cpu, out_ACC40Sk); 1541 post_wait_for_ACC (cpu, ACC40Sk_1); 1542 post_wait_for_ACC (cpu, ACC40Sk_2); 1543 post_wait_for_ACC (cpu, ACC40Sk_3); 1544 1545 /* Restore the busy cycles of the registers we used. */ 1546 acc = ps->acc_busy; 1547 acc[in_ACC40Si] += busy_adjustment[0]; 1548 if (ACC40Si_1 >= 0) 1549 acc[ACC40Si_1] += busy_adjustment[1]; 1550 if (ACC40Si_2 >= 0) 1551 acc[ACC40Si_2] += busy_adjustment[2]; 1552 if (ACC40Si_3 >= 0) 1553 acc[ACC40Si_3] += busy_adjustment[3]; 1554 acc[out_ACC40Sk] += busy_adjustment[4]; 1555 if (ACC40Sk_1 >= 0) 1556 acc[ACC40Sk_1] += busy_adjustment[5]; 1557 if (ACC40Sk_2 >= 0) 1558 acc[ACC40Sk_2] += busy_adjustment[6]; 1559 if (ACC40Sk_3 >= 0) 1560 acc[ACC40Sk_3] += busy_adjustment[7]; 1561 1562 /* The latency of the output register will be at least the latency of the 1563 other inputs. Once initiated, post-processing will take 1 cycle. */ 1564 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait + 1); 1565 set_acc_use_is_media_p2 (cpu, out_ACC40Sk); 1566 if (ACC40Sk_1 >= 0) 1567 { 1568 update_ACC_latency (cpu, ACC40Sk_1, ps->post_wait + 1); 1569 set_acc_use_is_media_p2 (cpu, ACC40Sk_1); 1570 } 1571 if (ACC40Sk_2 >= 0) 1572 { 1573 update_ACC_latency (cpu, ACC40Sk_2, ps->post_wait + 1); 1574 set_acc_use_is_media_p2 (cpu, ACC40Sk_2); 1575 } 1576 if (ACC40Sk_3 >= 0) 1577 { 1578 update_ACC_latency (cpu, ACC40Sk_3, ps->post_wait + 1); 1579 set_acc_use_is_media_p2 (cpu, ACC40Sk_3); 1580 } 1581 1582 return cycles; 1583 } 1584 1585 int 1586 frvbf_model_fr400_u_media_3 (SIM_CPU *cpu, const IDESC *idesc, 1587 int unit_num, int referenced, 1588 INT in_FRi, INT in_FRj, 1589 INT out_FRk) 1590 { 1591 /* Modelling is the same as media unit 1. */ 1592 return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced, 1593 in_FRi, in_FRj, out_FRk); 1594 } 1595 1596 int 1597 frvbf_model_fr400_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc, 1598 int unit_num, int referenced, 1599 INT in_FRi, INT out_FRk) 1600 { 1601 int cycles; 1602 INT dual_FRi; 1603 FRV_PROFILE_STATE *ps; 1604 int busy_adjustment[] = {0, 0}; 1605 int *fr; 1606 1607 if (model_insn == FRV_INSN_MODEL_PASS_1) 1608 return 0; 1609 1610 /* The preprocessing can execute right away. */ 1611 cycles = idesc->timing->units[unit_num].done; 1612 1613 ps = CPU_PROFILE_STATE (cpu); 1614 dual_FRi = DUAL_REG (in_FRi); 1615 1616 /* The latency of the registers may be less than previously recorded, 1617 depending on how they were used previously. 1618 See Table 13-8 in the LSI. */ 1619 if (use_is_fp_load (cpu, in_FRi)) 1620 { 1621 busy_adjustment[0] = 1; 1622 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 1623 } 1624 else 1625 enforce_full_fr_latency (cpu, in_FRi); 1626 if (dual_FRi >= 0 && use_is_fp_load (cpu, dual_FRi)) 1627 { 1628 busy_adjustment[1] = 1; 1629 decrease_FR_busy (cpu, dual_FRi, busy_adjustment[1]); 1630 } 1631 else 1632 enforce_full_fr_latency (cpu, dual_FRi); 1633 1634 /* The post processing must wait if there is a dependency on a FR 1635 which is not ready yet. */ 1636 ps->post_wait = cycles; 1637 post_wait_for_FR (cpu, in_FRi); 1638 post_wait_for_FR (cpu, dual_FRi); 1639 post_wait_for_FR (cpu, out_FRk); 1640 1641 /* Restore the busy cycles of the registers we used. */ 1642 fr = ps->fr_busy; 1643 fr[in_FRi] += busy_adjustment[0]; 1644 if (dual_FRi >= 0) 1645 fr[dual_FRi] += busy_adjustment[1]; 1646 1647 /* The latency of the output register will be at least the latency of the 1648 other inputs. */ 1649 update_FR_latency (cpu, out_FRk, ps->post_wait); 1650 1651 /* Once initiated, post-processing has no latency. */ 1652 update_FR_ptime (cpu, out_FRk, 0); 1653 1654 return cycles; 1655 } 1656 1657 int 1658 frvbf_model_fr400_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc, 1659 int unit_num, int referenced, 1660 INT in_FRi, INT in_FRj, 1661 INT out_FRk) 1662 { 1663 /* Modelling is the same as media unit 1. */ 1664 return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced, 1665 in_FRi, in_FRj, out_FRk); 1666 } 1667 1668 int 1669 frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, 1670 int unit_num, int referenced, 1671 INT in_ACC40Si, INT in_FRj, 1672 INT out_ACC40Sk, INT out_FRk) 1673 { 1674 int cycles; 1675 FRV_PROFILE_STATE *ps; 1676 const CGEN_INSN *insn; 1677 int busy_adjustment[] = {0}; 1678 int *fr; 1679 1680 if (model_insn == FRV_INSN_MODEL_PASS_1) 1681 return 0; 1682 1683 /* The preprocessing can execute right away. */ 1684 cycles = idesc->timing->units[unit_num].done; 1685 1686 ps = CPU_PROFILE_STATE (cpu); 1687 insn = idesc->idata; 1688 1689 /* The latency of the registers may be less than previously recorded, 1690 depending on how they were used previously. 1691 See Table 13-8 in the LSI. */ 1692 if (in_FRj >= 0) 1693 { 1694 if (use_is_fp_load (cpu, in_FRj)) 1695 { 1696 busy_adjustment[0] = 1; 1697 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); 1698 } 1699 else 1700 enforce_full_fr_latency (cpu, in_FRj); 1701 } 1702 1703 /* The post processing must wait if there is a dependency on a FR 1704 which is not ready yet. */ 1705 ps->post_wait = cycles; 1706 post_wait_for_ACC (cpu, in_ACC40Si); 1707 post_wait_for_ACC (cpu, out_ACC40Sk); 1708 post_wait_for_FR (cpu, in_FRj); 1709 post_wait_for_FR (cpu, out_FRk); 1710 1711 /* Restore the busy cycles of the registers we used. */ 1712 fr = ps->fr_busy; 1713 1714 /* The latency of the output register will be at least the latency of the 1715 other inputs. Once initiated, post-processing will take 1 cycle. */ 1716 if (out_FRk >= 0) 1717 { 1718 update_FR_latency (cpu, out_FRk, ps->post_wait); 1719 update_FR_ptime (cpu, out_FRk, 1); 1720 /* Mark this use of the register as media unit 4. */ 1721 set_use_is_media_p4 (cpu, out_FRk); 1722 } 1723 else if (out_ACC40Sk >= 0) 1724 { 1725 update_ACC_latency (cpu, out_ACC40Sk, ps->post_wait); 1726 update_ACC_ptime (cpu, out_ACC40Sk, 1); 1727 /* Mark this use of the register as media unit 4. */ 1728 set_acc_use_is_media_p4 (cpu, out_ACC40Sk); 1729 } 1730 1731 return cycles; 1732 } 1733 1734 int 1735 frvbf_model_fr400_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc, 1736 int unit_num, int referenced, 1737 INT in_ACCGi, INT in_FRinti, 1738 INT out_ACCGk, INT out_FRintk) 1739 { 1740 /* Modelling is the same as media-4 unit except use accumulator guards 1741 as input instead of accumulators. */ 1742 return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced, 1743 in_ACCGi, in_FRinti, 1744 out_ACCGk, out_FRintk); 1745 } 1746 1747 int 1748 frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, 1749 int unit_num, int referenced, 1750 INT in_ACC40Si, INT out_FRk) 1751 { 1752 int cycles; 1753 FRV_PROFILE_STATE *ps; 1754 const CGEN_INSN *insn; 1755 INT ACC40Si_1; 1756 INT FRk_1; 1757 1758 if (model_insn == FRV_INSN_MODEL_PASS_1) 1759 return 0; 1760 1761 /* The preprocessing can execute right away. */ 1762 cycles = idesc->timing->units[unit_num].done; 1763 1764 ps = CPU_PROFILE_STATE (cpu); 1765 ACC40Si_1 = DUAL_REG (in_ACC40Si); 1766 FRk_1 = DUAL_REG (out_FRk); 1767 1768 insn = idesc->idata; 1769 1770 /* The post processing must wait if there is a dependency on a FR 1771 which is not ready yet. */ 1772 ps->post_wait = cycles; 1773 post_wait_for_ACC (cpu, in_ACC40Si); 1774 post_wait_for_ACC (cpu, ACC40Si_1); 1775 post_wait_for_FR (cpu, out_FRk); 1776 post_wait_for_FR (cpu, FRk_1); 1777 1778 /* The latency of the output register will be at least the latency of the 1779 other inputs. Once initiated, post-processing will take 1 cycle. */ 1780 if (out_FRk >= 0) 1781 { 1782 update_FR_latency (cpu, out_FRk, ps->post_wait); 1783 update_FR_ptime (cpu, out_FRk, 1); 1784 /* Mark this use of the register as media unit 4. */ 1785 set_use_is_media_p4 (cpu, out_FRk); 1786 } 1787 if (FRk_1 >= 0) 1788 { 1789 update_FR_latency (cpu, FRk_1, ps->post_wait); 1790 update_FR_ptime (cpu, FRk_1, 1); 1791 /* Mark this use of the register as media unit 4. */ 1792 set_use_is_media_p4 (cpu, FRk_1); 1793 } 1794 1795 return cycles; 1796 } 1797 1798 int 1799 frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, 1800 int unit_num, int referenced, 1801 INT in_FRi, INT out_FRk) 1802 { 1803 int cycles; 1804 FRV_PROFILE_STATE *ps; 1805 const CGEN_INSN *insn; 1806 int busy_adjustment[] = {0}; 1807 int *fr; 1808 1809 if (model_insn == FRV_INSN_MODEL_PASS_1) 1810 return 0; 1811 1812 /* The preprocessing can execute right away. */ 1813 cycles = idesc->timing->units[unit_num].done; 1814 1815 ps = CPU_PROFILE_STATE (cpu); 1816 insn = idesc->idata; 1817 1818 /* The latency of the registers may be less than previously recorded, 1819 depending on how they were used previously. 1820 See Table 13-8 in the LSI. */ 1821 if (in_FRi >= 0) 1822 { 1823 if (use_is_fp_load (cpu, in_FRi)) 1824 { 1825 busy_adjustment[0] = 1; 1826 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 1827 } 1828 else 1829 enforce_full_fr_latency (cpu, in_FRi); 1830 } 1831 1832 /* The post processing must wait if there is a dependency on a FR 1833 which is not ready yet. */ 1834 ps->post_wait = cycles; 1835 post_wait_for_FR (cpu, in_FRi); 1836 post_wait_for_FR (cpu, out_FRk); 1837 1838 /* Restore the busy cycles of the registers we used. */ 1839 fr = ps->fr_busy; 1840 if (in_FRi >= 0) 1841 fr[in_FRi] += busy_adjustment[0]; 1842 1843 /* The latency of the output register will be at least the latency of the 1844 other inputs. Once initiated, post-processing will take 1 cycle. */ 1845 if (out_FRk >= 0) 1846 { 1847 update_FR_latency (cpu, out_FRk, ps->post_wait); 1848 update_FR_ptime (cpu, out_FRk, 1); 1849 1850 /* Mark this use of the register as media unit 1. */ 1851 set_use_is_media_p6 (cpu, out_FRk); 1852 } 1853 1854 return cycles; 1855 } 1856 1857 int 1858 frvbf_model_fr400_u_media_7 (SIM_CPU *cpu, const IDESC *idesc, 1859 int unit_num, int referenced, 1860 INT in_FRinti, INT in_FRintj, 1861 INT out_FCCk) 1862 { 1863 int cycles; 1864 FRV_PROFILE_STATE *ps; 1865 int busy_adjustment[] = {0, 0}; 1866 int *fr; 1867 1868 if (model_insn == FRV_INSN_MODEL_PASS_1) 1869 return 0; 1870 1871 /* The preprocessing can execute right away. */ 1872 cycles = idesc->timing->units[unit_num].done; 1873 1874 /* The post processing must wait if there is a dependency on a FR 1875 which is not ready yet. */ 1876 ps = CPU_PROFILE_STATE (cpu); 1877 1878 /* The latency of the registers may be less than previously recorded, 1879 depending on how they were used previously. 1880 See Table 13-8 in the LSI. */ 1881 if (in_FRinti >= 0) 1882 { 1883 if (use_is_fp_load (cpu, in_FRinti)) 1884 { 1885 busy_adjustment[0] = 1; 1886 decrease_FR_busy (cpu, in_FRinti, busy_adjustment[0]); 1887 } 1888 else 1889 enforce_full_fr_latency (cpu, in_FRinti); 1890 } 1891 if (in_FRintj >= 0 && in_FRintj != in_FRinti) 1892 { 1893 if (use_is_fp_load (cpu, in_FRintj)) 1894 { 1895 busy_adjustment[1] = 1; 1896 decrease_FR_busy (cpu, in_FRintj, busy_adjustment[1]); 1897 } 1898 else 1899 enforce_full_fr_latency (cpu, in_FRintj); 1900 } 1901 1902 ps->post_wait = cycles; 1903 post_wait_for_FR (cpu, in_FRinti); 1904 post_wait_for_FR (cpu, in_FRintj); 1905 post_wait_for_CCR (cpu, out_FCCk); 1906 1907 /* Restore the busy cycles of the registers we used. */ 1908 fr = ps->fr_busy; 1909 if (in_FRinti >= 0) 1910 fr[in_FRinti] += busy_adjustment[0]; 1911 if (in_FRintj >= 0) 1912 fr[in_FRintj] += busy_adjustment[1]; 1913 1914 /* The latency of FCCi_2 will be the latency of the other inputs plus 1 1915 cycle. */ 1916 update_CCR_latency (cpu, out_FCCk, ps->post_wait + 1); 1917 1918 return cycles; 1919 } 1920 1921 int 1922 frvbf_model_fr400_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc, 1923 int unit_num, int referenced, 1924 INT in_FRi, 1925 INT out_FRk) 1926 { 1927 /* Insns using this unit are media-3 class insns, with a dual FRk output. */ 1928 int cycles; 1929 INT dual_FRk; 1930 FRV_PROFILE_STATE *ps; 1931 int busy_adjustment[] = {0}; 1932 int *fr; 1933 1934 if (model_insn == FRV_INSN_MODEL_PASS_1) 1935 return 0; 1936 1937 /* The preprocessing can execute right away. */ 1938 cycles = idesc->timing->units[unit_num].done; 1939 1940 /* If the previous use of the registers was a media op, 1941 then their latency will be less than previously recorded. 1942 See Table 13-13 in the LSI. */ 1943 dual_FRk = DUAL_REG (out_FRk); 1944 ps = CPU_PROFILE_STATE (cpu); 1945 if (use_is_fp_load (cpu, in_FRi)) 1946 { 1947 busy_adjustment[0] = 1; 1948 decrease_FR_busy (cpu, in_FRi, busy_adjustment[0]); 1949 } 1950 else 1951 enforce_full_fr_latency (cpu, in_FRi); 1952 1953 /* The post processing must wait if there is a dependency on a FR 1954 which is not ready yet. */ 1955 ps->post_wait = cycles; 1956 post_wait_for_FR (cpu, in_FRi); 1957 post_wait_for_FR (cpu, out_FRk); 1958 post_wait_for_FR (cpu, dual_FRk); 1959 1960 /* Restore the busy cycles of the registers we used. */ 1961 fr = ps->fr_busy; 1962 fr[in_FRi] += busy_adjustment[0]; 1963 1964 /* The latency of the output register will be at least the latency of the 1965 other inputs. Once initiated, post-processing has no latency. */ 1966 update_FR_latency (cpu, out_FRk, ps->post_wait); 1967 update_FR_ptime (cpu, out_FRk, 0); 1968 1969 if (dual_FRk >= 0) 1970 { 1971 update_FR_latency (cpu, dual_FRk, ps->post_wait); 1972 update_FR_ptime (cpu, dual_FRk, 0); 1973 } 1974 1975 return cycles; 1976 } 1977 1978 int 1979 frvbf_model_fr400_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc, 1980 int unit_num, int referenced, 1981 INT in_FRj, 1982 INT out_FRk) 1983 { 1984 /* Insns using this unit are media-3 class insns, with a dual FRj input. */ 1985 int cycles; 1986 INT dual_FRj; 1987 FRV_PROFILE_STATE *ps; 1988 int busy_adjustment[] = {0, 0}; 1989 int *fr; 1990 1991 if (model_insn == FRV_INSN_MODEL_PASS_1) 1992 return 0; 1993 1994 /* The preprocessing can execute right away. */ 1995 cycles = idesc->timing->units[unit_num].done; 1996 1997 /* If the previous use of the registers was a media op, 1998 then their latency will be less than previously recorded. 1999 See Table 13-13 in the LSI. */ 2000 dual_FRj = DUAL_REG (in_FRj); 2001 ps = CPU_PROFILE_STATE (cpu); 2002 if (use_is_fp_load (cpu, in_FRj)) 2003 { 2004 busy_adjustment[0] = 1; 2005 decrease_FR_busy (cpu, in_FRj, busy_adjustment[0]); 2006 } 2007 else 2008 enforce_full_fr_latency (cpu, in_FRj); 2009 if (dual_FRj >= 0) 2010 { 2011 if (use_is_fp_load (cpu, dual_FRj)) 2012 { 2013 busy_adjustment[1] = 1; 2014 decrease_FR_busy (cpu, dual_FRj, busy_adjustment[1]); 2015 } 2016 else 2017 enforce_full_fr_latency (cpu, dual_FRj); 2018 } 2019 2020 /* The post processing must wait if there is a dependency on a FR 2021 which is not ready yet. */ 2022 ps->post_wait = cycles; 2023 post_wait_for_FR (cpu, in_FRj); 2024 post_wait_for_FR (cpu, dual_FRj); 2025 post_wait_for_FR (cpu, out_FRk); 2026 2027 /* Restore the busy cycles of the registers we used. */ 2028 fr = ps->fr_busy; 2029 fr[in_FRj] += busy_adjustment[0]; 2030 if (dual_FRj >= 0) 2031 fr[dual_FRj] += busy_adjustment[1]; 2032 2033 /* The latency of the output register will be at least the latency of the 2034 other inputs. */ 2035 update_FR_latency (cpu, out_FRk, ps->post_wait); 2036 2037 /* Once initiated, post-processing has no latency. */ 2038 update_FR_ptime (cpu, out_FRk, 0); 2039 2040 return cycles; 2041 } 2042 2043 int 2044 frvbf_model_fr400_u_ici (SIM_CPU *cpu, const IDESC *idesc, 2045 int unit_num, int referenced, 2046 INT in_GRi, INT in_GRj) 2047 { 2048 /* Modelling for this unit is the same as for fr500. */ 2049 return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced, 2050 in_GRi, in_GRj); 2051 } 2052 2053 int 2054 frvbf_model_fr400_u_dci (SIM_CPU *cpu, const IDESC *idesc, 2055 int unit_num, int referenced, 2056 INT in_GRi, INT in_GRj) 2057 { 2058 /* Modelling for this unit is the same as for fr500. */ 2059 return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced, 2060 in_GRi, in_GRj); 2061 } 2062 2063 int 2064 frvbf_model_fr400_u_dcf (SIM_CPU *cpu, const IDESC *idesc, 2065 int unit_num, int referenced, 2066 INT in_GRi, INT in_GRj) 2067 { 2068 /* Modelling for this unit is the same as for fr500. */ 2069 return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced, 2070 in_GRi, in_GRj); 2071 } 2072 2073 int 2074 frvbf_model_fr400_u_icpl (SIM_CPU *cpu, const IDESC *idesc, 2075 int unit_num, int referenced, 2076 INT in_GRi, INT in_GRj) 2077 { 2078 /* Modelling for this unit is the same as for fr500. */ 2079 return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced, 2080 in_GRi, in_GRj); 2081 } 2082 2083 int 2084 frvbf_model_fr400_u_dcpl (SIM_CPU *cpu, const IDESC *idesc, 2085 int unit_num, int referenced, 2086 INT in_GRi, INT in_GRj) 2087 { 2088 /* Modelling for this unit is the same as for fr500. */ 2089 return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced, 2090 in_GRi, in_GRj); 2091 } 2092 2093 int 2094 frvbf_model_fr400_u_icul (SIM_CPU *cpu, const IDESC *idesc, 2095 int unit_num, int referenced, 2096 INT in_GRi, INT in_GRj) 2097 { 2098 /* Modelling for this unit is the same as for fr500. */ 2099 return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced, 2100 in_GRi, in_GRj); 2101 } 2102 2103 int 2104 frvbf_model_fr400_u_dcul (SIM_CPU *cpu, const IDESC *idesc, 2105 int unit_num, int referenced, 2106 INT in_GRi, INT in_GRj) 2107 { 2108 /* Modelling for this unit is the same as for fr500. */ 2109 return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced, 2110 in_GRi, in_GRj); 2111 } 2112 2113 int 2114 frvbf_model_fr400_u_barrier (SIM_CPU *cpu, const IDESC *idesc, 2115 int unit_num, int referenced) 2116 { 2117 /* Modelling for this unit is the same as for fr500. */ 2118 return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced); 2119 } 2120 2121 int 2122 frvbf_model_fr400_u_membar (SIM_CPU *cpu, const IDESC *idesc, 2123 int unit_num, int referenced) 2124 { 2125 /* Modelling for this unit is the same as for fr500. */ 2126 return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced); 2127 } 2128 2129 #endif /* WITH_PROFILE_MODEL_P */ 2130