1 /* This must come before any other includes. */ 2 #include "defs.h" 3 4 #include <signal.h> 5 #include <errno.h> 6 #include <sys/types.h> 7 #include <sys/stat.h> 8 #ifdef HAVE_UNISTD_H 9 #include <unistd.h> 10 #endif 11 #include <string.h> 12 13 #include "sim-main.h" 14 #include "sim-signal.h" 15 #include "simops.h" 16 #include "target-newlib-syscall.h" 17 18 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig) 19 20 enum op_types { 21 OP_VOID, 22 OP_REG, 23 OP_REG_OUTPUT, 24 OP_DREG, 25 OP_DREG_OUTPUT, 26 OP_ACCUM, 27 OP_ACCUM_OUTPUT, 28 OP_ACCUM_REVERSE, 29 OP_CR, 30 OP_CR_OUTPUT, 31 OP_CR_REVERSE, 32 OP_FLAG, 33 OP_FLAG_OUTPUT, 34 OP_CONSTANT16, 35 OP_CONSTANT8, 36 OP_CONSTANT3, 37 OP_CONSTANT4, 38 OP_MEMREF, 39 OP_MEMREF2, 40 OP_MEMREF3, 41 OP_POSTDEC, 42 OP_POSTINC, 43 OP_PREDEC, 44 OP_R0, 45 OP_R1, 46 OP_R2, 47 }; 48 49 50 enum { 51 PSW_MASK = (PSW_SM_BIT 52 | PSW_EA_BIT 53 | PSW_DB_BIT 54 | PSW_IE_BIT 55 | PSW_RP_BIT 56 | PSW_MD_BIT 57 | PSW_FX_BIT 58 | PSW_ST_BIT 59 | PSW_F0_BIT 60 | PSW_F1_BIT 61 | PSW_C_BIT), 62 /* The following bits in the PSW _can't_ be set by instructions such 63 as mvtc. */ 64 PSW_HW_MASK = (PSW_MASK | PSW_DM_BIT) 65 }; 66 67 reg_t 68 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, reg_t mask, reg_t val, int psw_hw_p) 69 { 70 /* A MASK bit is set when the corresponding bit in the CR should 71 be left alone */ 72 /* This assumes that (VAL & MASK) == 0 */ 73 switch (cr) 74 { 75 case PSW_CR: 76 if (psw_hw_p) 77 val &= PSW_HW_MASK; 78 else 79 val &= PSW_MASK; 80 if ((mask & PSW_SM_BIT) == 0) 81 { 82 int new_psw_sm = (val & PSW_SM_BIT) != 0; 83 /* save old SP */ 84 SET_HELD_SP (PSW_SM, GPR (SP_IDX)); 85 if (PSW_SM != new_psw_sm) 86 /* restore new SP */ 87 SET_GPR (SP_IDX, HELD_SP (new_psw_sm)); 88 } 89 if ((mask & (PSW_ST_BIT | PSW_FX_BIT)) == 0) 90 { 91 if (val & PSW_ST_BIT && !(val & PSW_FX_BIT)) 92 { 93 sim_io_printf 94 (sd, 95 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", 96 PC<<2); 97 EXCEPTION (SIM_SIGILL); 98 } 99 } 100 /* keep an up-to-date psw around for tracing */ 101 State.trace.psw = (State.trace.psw & mask) | val; 102 break; 103 case BPSW_CR: 104 case DPSW_CR: 105 /* Just like PSW, mask things like DM out. */ 106 if (psw_hw_p) 107 val &= PSW_HW_MASK; 108 else 109 val &= PSW_MASK; 110 break; 111 case MOD_S_CR: 112 case MOD_E_CR: 113 val &= ~1; 114 break; 115 default: 116 break; 117 } 118 /* only issue an update if the register is being changed */ 119 if ((State.cregs[cr] & ~mask) != val) 120 SLOT_PEND_MASK (State.cregs[cr], mask, val); 121 return val; 122 } 123 124 #ifdef DEBUG 125 static void trace_input_func (SIM_DESC sd, 126 const char *name, 127 enum op_types in1, 128 enum op_types in2, 129 enum op_types in3); 130 131 #define trace_input(name, in1, in2, in3) do { if (d10v_debug) trace_input_func (sd, name, in1, in2, in3); } while (0) 132 133 #ifndef SIZE_INSTRUCTION 134 #define SIZE_INSTRUCTION 8 135 #endif 136 137 #ifndef SIZE_OPERANDS 138 #define SIZE_OPERANDS 18 139 #endif 140 141 #ifndef SIZE_VALUES 142 #define SIZE_VALUES 13 143 #endif 144 145 #ifndef SIZE_LOCATION 146 #define SIZE_LOCATION 20 147 #endif 148 149 #ifndef SIZE_PC 150 #define SIZE_PC 6 151 #endif 152 153 #ifndef SIZE_LINE_NUMBER 154 #define SIZE_LINE_NUMBER 4 155 #endif 156 157 static void 158 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3) 159 { 160 char *comma; 161 enum op_types in[3]; 162 int i; 163 char buf[1024]; 164 char *p; 165 long tmp; 166 char *type; 167 const char *filename; 168 const char *functionname; 169 unsigned int linenumber; 170 bfd_vma byte_pc; 171 172 if ((d10v_debug & DEBUG_TRACE) == 0) 173 return; 174 175 switch (State.ins_type) 176 { 177 default: 178 case INS_UNKNOWN: type = " ?"; break; 179 case INS_LEFT: type = " L"; break; 180 case INS_RIGHT: type = " R"; break; 181 case INS_LEFT_PARALLEL: type = "*L"; break; 182 case INS_RIGHT_PARALLEL: type = "*R"; break; 183 case INS_LEFT_COND_TEST: type = "?L"; break; 184 case INS_RIGHT_COND_TEST: type = "?R"; break; 185 case INS_LEFT_COND_EXE: type = "&L"; break; 186 case INS_RIGHT_COND_EXE: type = "&R"; break; 187 case INS_LONG: type = " B"; break; 188 } 189 190 if ((d10v_debug & DEBUG_LINE_NUMBER) == 0) 191 sim_io_printf (sd, 192 "0x%.*x %s: %-*s ", 193 SIZE_PC, (unsigned)PC, 194 type, 195 SIZE_INSTRUCTION, name); 196 197 else 198 { 199 buf[0] = '\0'; 200 byte_pc = PC; 201 if (STATE_TEXT_SECTION (sd) 202 && byte_pc >= STATE_TEXT_START (sd) 203 && byte_pc < STATE_TEXT_END (sd)) 204 { 205 filename = (const char *)0; 206 functionname = (const char *)0; 207 linenumber = 0; 208 if (bfd_find_nearest_line (STATE_PROG_BFD (sd), 209 STATE_TEXT_SECTION (sd), 210 (struct bfd_symbol **)0, 211 byte_pc - STATE_TEXT_START (sd), 212 &filename, &functionname, &linenumber)) 213 { 214 p = buf; 215 if (linenumber) 216 { 217 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); 218 p += strlen (p); 219 } 220 else 221 { 222 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); 223 p += SIZE_LINE_NUMBER+2; 224 } 225 226 if (functionname) 227 { 228 sprintf (p, "%s ", functionname); 229 p += strlen (p); 230 } 231 else if (filename) 232 { 233 char *q = strrchr (filename, '/'); 234 sprintf (p, "%s ", (q) ? q+1 : filename); 235 p += strlen (p); 236 } 237 238 if (*p == ' ') 239 *p = '\0'; 240 } 241 } 242 243 sim_io_printf (sd, 244 "0x%.*x %s: %-*.*s %-*s ", 245 SIZE_PC, (unsigned)PC, 246 type, 247 SIZE_LOCATION, SIZE_LOCATION, buf, 248 SIZE_INSTRUCTION, name); 249 } 250 251 in[0] = in1; 252 in[1] = in2; 253 in[2] = in3; 254 comma = ""; 255 p = buf; 256 for (i = 0; i < 3; i++) 257 { 258 switch (in[i]) 259 { 260 case OP_VOID: 261 case OP_R0: 262 case OP_R1: 263 case OP_R2: 264 break; 265 266 case OP_REG: 267 case OP_REG_OUTPUT: 268 case OP_DREG: 269 case OP_DREG_OUTPUT: 270 sprintf (p, "%sr%d", comma, OP[i]); 271 p += strlen (p); 272 comma = ","; 273 break; 274 275 case OP_CR: 276 case OP_CR_OUTPUT: 277 case OP_CR_REVERSE: 278 sprintf (p, "%scr%d", comma, OP[i]); 279 p += strlen (p); 280 comma = ","; 281 break; 282 283 case OP_ACCUM: 284 case OP_ACCUM_OUTPUT: 285 case OP_ACCUM_REVERSE: 286 sprintf (p, "%sa%d", comma, OP[i]); 287 p += strlen (p); 288 comma = ","; 289 break; 290 291 case OP_CONSTANT16: 292 sprintf (p, "%s%d", comma, OP[i]); 293 p += strlen (p); 294 comma = ","; 295 break; 296 297 case OP_CONSTANT8: 298 sprintf (p, "%s%d", comma, SEXT8(OP[i])); 299 p += strlen (p); 300 comma = ","; 301 break; 302 303 case OP_CONSTANT4: 304 sprintf (p, "%s%d", comma, SEXT4(OP[i])); 305 p += strlen (p); 306 comma = ","; 307 break; 308 309 case OP_CONSTANT3: 310 sprintf (p, "%s%d", comma, SEXT3(OP[i])); 311 p += strlen (p); 312 comma = ","; 313 break; 314 315 case OP_MEMREF: 316 sprintf (p, "%s@r%d", comma, OP[i]); 317 p += strlen (p); 318 comma = ","; 319 break; 320 321 case OP_MEMREF2: 322 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]); 323 p += strlen (p); 324 comma = ","; 325 break; 326 327 case OP_MEMREF3: 328 sprintf (p, "%s@%d", comma, OP[i]); 329 p += strlen (p); 330 comma = ","; 331 break; 332 333 case OP_POSTINC: 334 sprintf (p, "%s@r%d+", comma, OP[i]); 335 p += strlen (p); 336 comma = ","; 337 break; 338 339 case OP_POSTDEC: 340 sprintf (p, "%s@r%d-", comma, OP[i]); 341 p += strlen (p); 342 comma = ","; 343 break; 344 345 case OP_PREDEC: 346 sprintf (p, "%s@-r%d", comma, OP[i]); 347 p += strlen (p); 348 comma = ","; 349 break; 350 351 case OP_FLAG: 352 case OP_FLAG_OUTPUT: 353 if (OP[i] == 0) 354 sprintf (p, "%sf0", comma); 355 356 else if (OP[i] == 1) 357 sprintf (p, "%sf1", comma); 358 359 else 360 sprintf (p, "%sc", comma); 361 362 p += strlen (p); 363 comma = ","; 364 break; 365 } 366 } 367 368 if ((d10v_debug & DEBUG_VALUES) == 0) 369 { 370 *p++ = '\n'; 371 *p = '\0'; 372 sim_io_printf (sd, "%s", buf); 373 } 374 else 375 { 376 *p = '\0'; 377 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf); 378 379 p = buf; 380 for (i = 0; i < 3; i++) 381 { 382 buf[0] = '\0'; 383 switch (in[i]) 384 { 385 case OP_VOID: 386 sim_io_printf (sd, "%*s", SIZE_VALUES, ""); 387 break; 388 389 case OP_REG_OUTPUT: 390 case OP_DREG_OUTPUT: 391 case OP_CR_OUTPUT: 392 case OP_ACCUM_OUTPUT: 393 case OP_FLAG_OUTPUT: 394 sim_io_printf (sd, "%*s", SIZE_VALUES, "---"); 395 break; 396 397 case OP_REG: 398 case OP_MEMREF: 399 case OP_POSTDEC: 400 case OP_POSTINC: 401 case OP_PREDEC: 402 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 403 (uint16_t) GPR (OP[i])); 404 break; 405 406 case OP_MEMREF3: 407 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", (uint16_t) OP[i]); 408 break; 409 410 case OP_DREG: 411 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1))); 412 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); 413 break; 414 415 case OP_CR: 416 case OP_CR_REVERSE: 417 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 418 (uint16_t) CREG (OP[i])); 419 break; 420 421 case OP_ACCUM: 422 case OP_ACCUM_REVERSE: 423 sim_io_printf (sd, "%*s0x%.2x%.8lx", SIZE_VALUES-12, "", 424 ((int)(ACC (OP[i]) >> 32) & 0xff), 425 ((unsigned long) ACC (OP[i])) & 0xffffffff); 426 break; 427 428 case OP_CONSTANT16: 429 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 430 (uint16_t)OP[i]); 431 break; 432 433 case OP_CONSTANT4: 434 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 435 (uint16_t)SEXT4(OP[i])); 436 break; 437 438 case OP_CONSTANT8: 439 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 440 (uint16_t)SEXT8(OP[i])); 441 break; 442 443 case OP_CONSTANT3: 444 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 445 (uint16_t)SEXT3(OP[i])); 446 break; 447 448 case OP_FLAG: 449 if (OP[i] == 0) 450 sim_io_printf (sd, "%*sF0 = %d", SIZE_VALUES-6, "", 451 PSW_F0 != 0); 452 453 else if (OP[i] == 1) 454 sim_io_printf (sd, "%*sF1 = %d", SIZE_VALUES-6, "", 455 PSW_F1 != 0); 456 457 else 458 sim_io_printf (sd, "%*sC = %d", SIZE_VALUES-5, "", 459 PSW_C != 0); 460 461 break; 462 463 case OP_MEMREF2: 464 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 465 (uint16_t)OP[i]); 466 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 467 (uint16_t)GPR (OP[i + 1])); 468 i++; 469 break; 470 471 case OP_R0: 472 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 473 (uint16_t) GPR (0)); 474 break; 475 476 case OP_R1: 477 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 478 (uint16_t) GPR (1)); 479 break; 480 481 case OP_R2: 482 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 483 (uint16_t) GPR (2)); 484 break; 485 486 } 487 } 488 } 489 490 sim_io_flush_stdout (sd); 491 } 492 493 static void 494 do_trace_output_flush (SIM_DESC sd) 495 { 496 sim_io_flush_stdout (sd); 497 } 498 499 static void 500 do_trace_output_finish (SIM_DESC sd) 501 { 502 sim_io_printf (sd, 503 " F0=%d F1=%d C=%d\n", 504 (State.trace.psw & PSW_F0_BIT) != 0, 505 (State.trace.psw & PSW_F1_BIT) != 0, 506 (State.trace.psw & PSW_C_BIT) != 0); 507 sim_io_flush_stdout (sd); 508 } 509 510 static void 511 trace_output_40 (SIM_DESC sd, uint64_t val) 512 { 513 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 514 { 515 sim_io_printf (sd, 516 " :: %*s0x%.2x%.8lx", 517 SIZE_VALUES - 12, 518 "", 519 ((int)(val >> 32) & 0xff), 520 ((unsigned long) val) & 0xffffffff); 521 do_trace_output_finish (sd); 522 } 523 } 524 525 static void 526 trace_output_32 (SIM_DESC sd, uint32_t val) 527 { 528 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 529 { 530 sim_io_printf (sd, 531 " :: %*s0x%.8x", 532 SIZE_VALUES - 10, 533 "", 534 (int) val); 535 do_trace_output_finish (sd); 536 } 537 } 538 539 static void 540 trace_output_16 (SIM_DESC sd, uint16_t val) 541 { 542 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 543 { 544 sim_io_printf (sd, 545 " :: %*s0x%.4x", 546 SIZE_VALUES - 6, 547 "", 548 (int) val); 549 do_trace_output_finish (sd); 550 } 551 } 552 553 static void 554 trace_output_void (SIM_DESC sd) 555 { 556 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 557 { 558 sim_io_printf (sd, "\n"); 559 do_trace_output_flush (sd); 560 } 561 } 562 563 static void 564 trace_output_flag (SIM_DESC sd) 565 { 566 if ((d10v_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 567 { 568 sim_io_printf (sd, 569 " :: %*s", 570 SIZE_VALUES, 571 ""); 572 do_trace_output_finish (sd); 573 } 574 } 575 576 577 578 579 #else 580 #define trace_input(NAME, IN1, IN2, IN3) 581 #define trace_output(RESULT) 582 #endif 583 584 /* abs */ 585 void 586 OP_4607 (SIM_DESC sd, SIM_CPU *cpu) 587 { 588 int16_t tmp; 589 trace_input ("abs", OP_REG, OP_VOID, OP_VOID); 590 SET_PSW_F1 (PSW_F0); 591 tmp = GPR(OP[0]); 592 if (tmp < 0) 593 { 594 tmp = - tmp; 595 SET_PSW_F0 (1); 596 } 597 else 598 SET_PSW_F0 (0); 599 SET_GPR (OP[0], tmp); 600 trace_output_16 (sd, tmp); 601 } 602 603 /* abs */ 604 void 605 OP_5607 (SIM_DESC sd, SIM_CPU *cpu) 606 { 607 int64_t tmp; 608 trace_input ("abs", OP_ACCUM, OP_VOID, OP_VOID); 609 SET_PSW_F1 (PSW_F0); 610 611 tmp = SEXT40 (ACC (OP[0])); 612 if (tmp < 0 ) 613 { 614 tmp = - tmp; 615 if (PSW_ST) 616 { 617 if (tmp > SEXT40(MAX32)) 618 tmp = (MAX32); 619 else if (tmp < SEXT40(MIN32)) 620 tmp = (MIN32); 621 else 622 tmp = (tmp & MASK40); 623 } 624 else 625 tmp = (tmp & MASK40); 626 SET_PSW_F0 (1); 627 } 628 else 629 { 630 tmp = (tmp & MASK40); 631 SET_PSW_F0 (0); 632 } 633 SET_ACC (OP[0], tmp); 634 trace_output_40 (sd, tmp); 635 } 636 637 /* add */ 638 void 639 OP_200 (SIM_DESC sd, SIM_CPU *cpu) 640 { 641 uint16_t a = GPR (OP[0]); 642 uint16_t b = GPR (OP[1]); 643 uint16_t tmp = (a + b); 644 trace_input ("add", OP_REG, OP_REG, OP_VOID); 645 SET_PSW_C (a > tmp); 646 SET_GPR (OP[0], tmp); 647 trace_output_16 (sd, tmp); 648 } 649 650 /* add */ 651 void 652 OP_1201 (SIM_DESC sd, SIM_CPU *cpu) 653 { 654 int64_t tmp; 655 tmp = SEXT40(ACC (OP[0])) + (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1)); 656 657 trace_input ("add", OP_ACCUM, OP_REG, OP_VOID); 658 if (PSW_ST) 659 { 660 if (tmp > SEXT40(MAX32)) 661 tmp = (MAX32); 662 else if (tmp < SEXT40(MIN32)) 663 tmp = (MIN32); 664 else 665 tmp = (tmp & MASK40); 666 } 667 else 668 tmp = (tmp & MASK40); 669 SET_ACC (OP[0], tmp); 670 trace_output_40 (sd, tmp); 671 } 672 673 /* add */ 674 void 675 OP_1203 (SIM_DESC sd, SIM_CPU *cpu) 676 { 677 int64_t tmp; 678 tmp = SEXT40(ACC (OP[0])) + SEXT40(ACC (OP[1])); 679 680 trace_input ("add", OP_ACCUM, OP_ACCUM, OP_VOID); 681 if (PSW_ST) 682 { 683 if (tmp > SEXT40(MAX32)) 684 tmp = (MAX32); 685 else if (tmp < SEXT40(MIN32)) 686 tmp = (MIN32); 687 else 688 tmp = (tmp & MASK40); 689 } 690 else 691 tmp = (tmp & MASK40); 692 SET_ACC (OP[0], tmp); 693 trace_output_40 (sd, tmp); 694 } 695 696 /* add2w */ 697 void 698 OP_1200 (SIM_DESC sd, SIM_CPU *cpu) 699 { 700 uint32_t tmp; 701 uint32_t a = (GPR (OP[0])) << 16 | GPR (OP[0] + 1); 702 uint32_t b = (GPR (OP[1])) << 16 | GPR (OP[1] + 1); 703 trace_input ("add2w", OP_DREG, OP_DREG, OP_VOID); 704 tmp = a + b; 705 SET_PSW_C (tmp < a); 706 SET_GPR (OP[0] + 0, (tmp >> 16)); 707 SET_GPR (OP[0] + 1, (tmp & 0xFFFF)); 708 trace_output_32 (sd, tmp); 709 } 710 711 /* add3 */ 712 void 713 OP_1000000 (SIM_DESC sd, SIM_CPU *cpu) 714 { 715 uint16_t a = GPR (OP[1]); 716 uint16_t b = OP[2]; 717 uint16_t tmp = (a + b); 718 trace_input ("add3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); 719 SET_PSW_C (tmp < a); 720 SET_GPR (OP[0], tmp); 721 trace_output_16 (sd, tmp); 722 } 723 724 /* addac3 */ 725 void 726 OP_17000200 (SIM_DESC sd, SIM_CPU *cpu) 727 { 728 int64_t tmp; 729 tmp = SEXT40(ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); 730 731 trace_input ("addac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); 732 SET_GPR (OP[0] + 0, ((tmp >> 16) & 0xffff)); 733 SET_GPR (OP[0] + 1, (tmp & 0xffff)); 734 trace_output_32 (sd, tmp); 735 } 736 737 /* addac3 */ 738 void 739 OP_17000202 (SIM_DESC sd, SIM_CPU *cpu) 740 { 741 int64_t tmp; 742 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2])); 743 744 trace_input ("addac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); 745 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); 746 SET_GPR (OP[0] + 1, tmp & 0xffff); 747 trace_output_32 (sd, tmp); 748 } 749 750 /* addac3s */ 751 void 752 OP_17001200 (SIM_DESC sd, SIM_CPU *cpu) 753 { 754 int64_t tmp; 755 SET_PSW_F1 (PSW_F0); 756 757 trace_input ("addac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); 758 tmp = SEXT40 (ACC (OP[2])) + SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); 759 if (tmp > SEXT40(MAX32)) 760 { 761 tmp = (MAX32); 762 SET_PSW_F0 (1); 763 } 764 else if (tmp < SEXT40(MIN32)) 765 { 766 tmp = (MIN32); 767 SET_PSW_F0 (1); 768 } 769 else 770 { 771 SET_PSW_F0 (0); 772 } 773 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); 774 SET_GPR (OP[0] + 1, (tmp & 0xffff)); 775 trace_output_32 (sd, tmp); 776 } 777 778 /* addac3s */ 779 void 780 OP_17001202 (SIM_DESC sd, SIM_CPU *cpu) 781 { 782 int64_t tmp; 783 SET_PSW_F1 (PSW_F0); 784 785 trace_input ("addac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); 786 tmp = SEXT40(ACC (OP[1])) + SEXT40(ACC (OP[2])); 787 if (tmp > SEXT40(MAX32)) 788 { 789 tmp = (MAX32); 790 SET_PSW_F0 (1); 791 } 792 else if (tmp < SEXT40(MIN32)) 793 { 794 tmp = (MIN32); 795 SET_PSW_F0 (1); 796 } 797 else 798 { 799 SET_PSW_F0 (0); 800 } 801 SET_GPR (OP[0] + 0, (tmp >> 16) & 0xffff); 802 SET_GPR (OP[0] + 1, (tmp & 0xffff)); 803 trace_output_32 (sd, tmp); 804 } 805 806 /* addi */ 807 void 808 OP_201 (SIM_DESC sd, SIM_CPU *cpu) 809 { 810 uint16_t a = GPR (OP[0]); 811 uint16_t b; 812 uint16_t tmp; 813 if (OP[1] == 0) 814 OP[1] = 16; 815 b = OP[1]; 816 tmp = (a + b); 817 trace_input ("addi", OP_REG, OP_CONSTANT16, OP_VOID); 818 SET_PSW_C (tmp < a); 819 SET_GPR (OP[0], tmp); 820 trace_output_16 (sd, tmp); 821 } 822 823 /* and */ 824 void 825 OP_C00 (SIM_DESC sd, SIM_CPU *cpu) 826 { 827 uint16_t tmp = GPR (OP[0]) & GPR (OP[1]); 828 trace_input ("and", OP_REG, OP_REG, OP_VOID); 829 SET_GPR (OP[0], tmp); 830 trace_output_16 (sd, tmp); 831 } 832 833 /* and3 */ 834 void 835 OP_6000000 (SIM_DESC sd, SIM_CPU *cpu) 836 { 837 uint16_t tmp = GPR (OP[1]) & OP[2]; 838 trace_input ("and3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); 839 SET_GPR (OP[0], tmp); 840 trace_output_16 (sd, tmp); 841 } 842 843 /* bclri */ 844 void 845 OP_C01 (SIM_DESC sd, SIM_CPU *cpu) 846 { 847 int16_t tmp; 848 trace_input ("bclri", OP_REG, OP_CONSTANT16, OP_VOID); 849 tmp = (GPR (OP[0]) &~(0x8000 >> OP[1])); 850 SET_GPR (OP[0], tmp); 851 trace_output_16 (sd, tmp); 852 } 853 854 /* bl.s */ 855 void 856 OP_4900 (SIM_DESC sd, SIM_CPU *cpu) 857 { 858 trace_input ("bl.s", OP_CONSTANT8, OP_R0, OP_R1); 859 SET_GPR (13, PC + 1); 860 JMP( PC + SEXT8 (OP[0])); 861 trace_output_void (sd); 862 } 863 864 /* bl.l */ 865 void 866 OP_24800000 (SIM_DESC sd, SIM_CPU *cpu) 867 { 868 trace_input ("bl.l", OP_CONSTANT16, OP_R0, OP_R1); 869 SET_GPR (13, (PC + 1)); 870 JMP (PC + OP[0]); 871 trace_output_void (sd); 872 } 873 874 /* bnoti */ 875 void 876 OP_A01 (SIM_DESC sd, SIM_CPU *cpu) 877 { 878 int16_t tmp; 879 trace_input ("bnoti", OP_REG, OP_CONSTANT16, OP_VOID); 880 tmp = (GPR (OP[0]) ^ (0x8000 >> OP[1])); 881 SET_GPR (OP[0], tmp); 882 trace_output_16 (sd, tmp); 883 } 884 885 /* bra.s */ 886 void 887 OP_4800 (SIM_DESC sd, SIM_CPU *cpu) 888 { 889 trace_input ("bra.s", OP_CONSTANT8, OP_VOID, OP_VOID); 890 JMP (PC + SEXT8 (OP[0])); 891 trace_output_void (sd); 892 } 893 894 /* bra.l */ 895 void 896 OP_24000000 (SIM_DESC sd, SIM_CPU *cpu) 897 { 898 trace_input ("bra.l", OP_CONSTANT16, OP_VOID, OP_VOID); 899 JMP (PC + OP[0]); 900 trace_output_void (sd); 901 } 902 903 /* brf0f.s */ 904 void 905 OP_4A00 (SIM_DESC sd, SIM_CPU *cpu) 906 { 907 trace_input ("brf0f.s", OP_CONSTANT8, OP_VOID, OP_VOID); 908 if (!PSW_F0) 909 JMP (PC + SEXT8 (OP[0])); 910 trace_output_flag (sd); 911 } 912 913 /* brf0f.l */ 914 void 915 OP_25000000 (SIM_DESC sd, SIM_CPU *cpu) 916 { 917 trace_input ("brf0f.l", OP_CONSTANT16, OP_VOID, OP_VOID); 918 if (!PSW_F0) 919 JMP (PC + OP[0]); 920 trace_output_flag (sd); 921 } 922 923 /* brf0t.s */ 924 void 925 OP_4B00 (SIM_DESC sd, SIM_CPU *cpu) 926 { 927 trace_input ("brf0t.s", OP_CONSTANT8, OP_VOID, OP_VOID); 928 if (PSW_F0) 929 JMP (PC + SEXT8 (OP[0])); 930 trace_output_flag (sd); 931 } 932 933 /* brf0t.l */ 934 void 935 OP_25800000 (SIM_DESC sd, SIM_CPU *cpu) 936 { 937 trace_input ("brf0t.l", OP_CONSTANT16, OP_VOID, OP_VOID); 938 if (PSW_F0) 939 JMP (PC + OP[0]); 940 trace_output_flag (sd); 941 } 942 943 /* bseti */ 944 void 945 OP_801 (SIM_DESC sd, SIM_CPU *cpu) 946 { 947 int16_t tmp; 948 trace_input ("bseti", OP_REG, OP_CONSTANT16, OP_VOID); 949 tmp = (GPR (OP[0]) | (0x8000 >> OP[1])); 950 SET_GPR (OP[0], tmp); 951 trace_output_16 (sd, tmp); 952 } 953 954 /* btsti */ 955 void 956 OP_E01 (SIM_DESC sd, SIM_CPU *cpu) 957 { 958 trace_input ("btsti", OP_REG, OP_CONSTANT16, OP_VOID); 959 SET_PSW_F1 (PSW_F0); 960 SET_PSW_F0 ((GPR (OP[0]) & (0x8000 >> OP[1])) ? 1 : 0); 961 trace_output_flag (sd); 962 } 963 964 /* clrac */ 965 void 966 OP_5601 (SIM_DESC sd, SIM_CPU *cpu) 967 { 968 trace_input ("clrac", OP_ACCUM_OUTPUT, OP_VOID, OP_VOID); 969 SET_ACC (OP[0], 0); 970 trace_output_40 (sd, 0); 971 } 972 973 /* cmp */ 974 void 975 OP_600 (SIM_DESC sd, SIM_CPU *cpu) 976 { 977 trace_input ("cmp", OP_REG, OP_REG, OP_VOID); 978 SET_PSW_F1 (PSW_F0); 979 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(GPR (OP[1]))) ? 1 : 0); 980 trace_output_flag (sd); 981 } 982 983 /* cmp */ 984 void 985 OP_1603 (SIM_DESC sd, SIM_CPU *cpu) 986 { 987 trace_input ("cmp", OP_ACCUM, OP_ACCUM, OP_VOID); 988 SET_PSW_F1 (PSW_F0); 989 SET_PSW_F0 ((SEXT40(ACC (OP[0])) < SEXT40(ACC (OP[1]))) ? 1 : 0); 990 trace_output_flag (sd); 991 } 992 993 /* cmpeq */ 994 void 995 OP_400 (SIM_DESC sd, SIM_CPU *cpu) 996 { 997 trace_input ("cmpeq", OP_REG, OP_REG, OP_VOID); 998 SET_PSW_F1 (PSW_F0); 999 SET_PSW_F0 ((GPR (OP[0]) == GPR (OP[1])) ? 1 : 0); 1000 trace_output_flag (sd); 1001 } 1002 1003 /* cmpeq */ 1004 void 1005 OP_1403 (SIM_DESC sd, SIM_CPU *cpu) 1006 { 1007 trace_input ("cmpeq", OP_ACCUM, OP_ACCUM, OP_VOID); 1008 SET_PSW_F1 (PSW_F0); 1009 SET_PSW_F0 (((ACC (OP[0]) & MASK40) == (ACC (OP[1]) & MASK40)) ? 1 : 0); 1010 trace_output_flag (sd); 1011 } 1012 1013 /* cmpeqi.s */ 1014 void 1015 OP_401 (SIM_DESC sd, SIM_CPU *cpu) 1016 { 1017 trace_input ("cmpeqi.s", OP_REG, OP_CONSTANT4, OP_VOID); 1018 SET_PSW_F1 (PSW_F0); 1019 SET_PSW_F0 ((GPR (OP[0]) == (reg_t) SEXT4 (OP[1])) ? 1 : 0); 1020 trace_output_flag (sd); 1021 } 1022 1023 /* cmpeqi.l */ 1024 void 1025 OP_2000000 (SIM_DESC sd, SIM_CPU *cpu) 1026 { 1027 trace_input ("cmpeqi.l", OP_REG, OP_CONSTANT16, OP_VOID); 1028 SET_PSW_F1 (PSW_F0); 1029 SET_PSW_F0 ((GPR (OP[0]) == (reg_t)OP[1]) ? 1 : 0); 1030 trace_output_flag (sd); 1031 } 1032 1033 /* cmpi.s */ 1034 void 1035 OP_601 (SIM_DESC sd, SIM_CPU *cpu) 1036 { 1037 trace_input ("cmpi.s", OP_REG, OP_CONSTANT4, OP_VOID); 1038 SET_PSW_F1 (PSW_F0); 1039 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)SEXT4(OP[1])) ? 1 : 0); 1040 trace_output_flag (sd); 1041 } 1042 1043 /* cmpi.l */ 1044 void 1045 OP_3000000 (SIM_DESC sd, SIM_CPU *cpu) 1046 { 1047 trace_input ("cmpi.l", OP_REG, OP_CONSTANT16, OP_VOID); 1048 SET_PSW_F1 (PSW_F0); 1049 SET_PSW_F0 (((int16_t)(GPR (OP[0])) < (int16_t)(OP[1])) ? 1 : 0); 1050 trace_output_flag (sd); 1051 } 1052 1053 /* cmpu */ 1054 void 1055 OP_4600 (SIM_DESC sd, SIM_CPU *cpu) 1056 { 1057 trace_input ("cmpu", OP_REG, OP_REG, OP_VOID); 1058 SET_PSW_F1 (PSW_F0); 1059 SET_PSW_F0 ((GPR (OP[0]) < GPR (OP[1])) ? 1 : 0); 1060 trace_output_flag (sd); 1061 } 1062 1063 /* cmpui */ 1064 void 1065 OP_23000000 (SIM_DESC sd, SIM_CPU *cpu) 1066 { 1067 trace_input ("cmpui", OP_REG, OP_CONSTANT16, OP_VOID); 1068 SET_PSW_F1 (PSW_F0); 1069 SET_PSW_F0 ((GPR (OP[0]) < (reg_t)OP[1]) ? 1 : 0); 1070 trace_output_flag (sd); 1071 } 1072 1073 /* cpfg */ 1074 void 1075 OP_4E09 (SIM_DESC sd, SIM_CPU *cpu) 1076 { 1077 uint8_t val; 1078 1079 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); 1080 1081 if (OP[1] == 0) 1082 val = PSW_F0; 1083 else if (OP[1] == 1) 1084 val = PSW_F1; 1085 else 1086 val = PSW_C; 1087 if (OP[0] == 0) 1088 SET_PSW_F0 (val); 1089 else 1090 SET_PSW_F1 (val); 1091 1092 trace_output_flag (sd); 1093 } 1094 1095 /* cpfg */ 1096 void 1097 OP_4E0F (SIM_DESC sd, SIM_CPU *cpu) 1098 { 1099 uint8_t val; 1100 1101 trace_input ("cpfg", OP_FLAG_OUTPUT, OP_FLAG, OP_VOID); 1102 1103 if (OP[1] == 0) 1104 val = PSW_F0; 1105 else if (OP[1] == 1) 1106 val = PSW_F1; 1107 else 1108 val = PSW_C; 1109 if (OP[0] == 0) 1110 SET_PSW_F0 (val); 1111 else 1112 SET_PSW_F1 (val); 1113 1114 trace_output_flag (sd); 1115 } 1116 1117 /* dbt */ 1118 void 1119 OP_5F20 (SIM_DESC sd, SIM_CPU *cpu) 1120 { 1121 /* sim_io_printf (sd, "***** DBT ***** PC=%x\n",PC); */ 1122 1123 /* GDB uses the instruction pair ``dbt || nop'' as a break-point. 1124 The conditional below is for either of the instruction pairs 1125 ``dbt -> XXX'' or ``dbt <- XXX'' and treats them as as cases 1126 where the dbt instruction should be interpreted. 1127 1128 The module `sim-break' provides a more effective mechanism for 1129 detecting GDB planted breakpoints. The code below may, 1130 eventually, be changed to use that mechanism. */ 1131 1132 if (State.ins_type == INS_LEFT 1133 || State.ins_type == INS_RIGHT) 1134 { 1135 trace_input ("dbt", OP_VOID, OP_VOID, OP_VOID); 1136 SET_DPC (PC + 1); 1137 SET_DPSW (PSW); 1138 SET_HW_PSW (PSW_DM_BIT | (PSW & (PSW_F0_BIT | PSW_F1_BIT | PSW_C_BIT))); 1139 JMP (DBT_VECTOR_START); 1140 trace_output_void (sd); 1141 } 1142 else 1143 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, SIM_SIGTRAP); 1144 } 1145 1146 /* divs */ 1147 void 1148 OP_14002800 (SIM_DESC sd, SIM_CPU *cpu) 1149 { 1150 uint16_t foo, tmp, tmpf; 1151 uint16_t hi; 1152 uint16_t lo; 1153 1154 trace_input ("divs", OP_DREG, OP_REG, OP_VOID); 1155 foo = (GPR (OP[0]) << 1) | (GPR (OP[0] + 1) >> 15); 1156 tmp = (int16_t)foo - (int16_t)(GPR (OP[1])); 1157 tmpf = (foo >= GPR (OP[1])) ? 1 : 0; 1158 hi = ((tmpf == 1) ? tmp : foo); 1159 lo = ((GPR (OP[0] + 1) << 1) | tmpf); 1160 SET_GPR (OP[0] + 0, hi); 1161 SET_GPR (OP[0] + 1, lo); 1162 trace_output_32 (sd, ((uint32_t) hi << 16) | lo); 1163 } 1164 1165 /* exef0f */ 1166 void 1167 OP_4E04 (SIM_DESC sd, SIM_CPU *cpu) 1168 { 1169 trace_input ("exef0f", OP_VOID, OP_VOID, OP_VOID); 1170 State.exe = (PSW_F0 == 0); 1171 trace_output_flag (sd); 1172 } 1173 1174 /* exef0t */ 1175 void 1176 OP_4E24 (SIM_DESC sd, SIM_CPU *cpu) 1177 { 1178 trace_input ("exef0t", OP_VOID, OP_VOID, OP_VOID); 1179 State.exe = (PSW_F0 != 0); 1180 trace_output_flag (sd); 1181 } 1182 1183 /* exef1f */ 1184 void 1185 OP_4E40 (SIM_DESC sd, SIM_CPU *cpu) 1186 { 1187 trace_input ("exef1f", OP_VOID, OP_VOID, OP_VOID); 1188 State.exe = (PSW_F1 == 0); 1189 trace_output_flag (sd); 1190 } 1191 1192 /* exef1t */ 1193 void 1194 OP_4E42 (SIM_DESC sd, SIM_CPU *cpu) 1195 { 1196 trace_input ("exef1t", OP_VOID, OP_VOID, OP_VOID); 1197 State.exe = (PSW_F1 != 0); 1198 trace_output_flag (sd); 1199 } 1200 1201 /* exefaf */ 1202 void 1203 OP_4E00 (SIM_DESC sd, SIM_CPU *cpu) 1204 { 1205 trace_input ("exefaf", OP_VOID, OP_VOID, OP_VOID); 1206 State.exe = (PSW_F0 == 0) & (PSW_F1 == 0); 1207 trace_output_flag (sd); 1208 } 1209 1210 /* exefat */ 1211 void 1212 OP_4E02 (SIM_DESC sd, SIM_CPU *cpu) 1213 { 1214 trace_input ("exefat", OP_VOID, OP_VOID, OP_VOID); 1215 State.exe = (PSW_F0 == 0) & (PSW_F1 != 0); 1216 trace_output_flag (sd); 1217 } 1218 1219 /* exetaf */ 1220 void 1221 OP_4E20 (SIM_DESC sd, SIM_CPU *cpu) 1222 { 1223 trace_input ("exetaf", OP_VOID, OP_VOID, OP_VOID); 1224 State.exe = (PSW_F0 != 0) & (PSW_F1 == 0); 1225 trace_output_flag (sd); 1226 } 1227 1228 /* exetat */ 1229 void 1230 OP_4E22 (SIM_DESC sd, SIM_CPU *cpu) 1231 { 1232 trace_input ("exetat", OP_VOID, OP_VOID, OP_VOID); 1233 State.exe = (PSW_F0 != 0) & (PSW_F1 != 0); 1234 trace_output_flag (sd); 1235 } 1236 1237 /* exp */ 1238 void 1239 OP_15002A00 (SIM_DESC sd, SIM_CPU *cpu) 1240 { 1241 uint32_t tmp, foo; 1242 int i; 1243 1244 trace_input ("exp", OP_REG_OUTPUT, OP_DREG, OP_VOID); 1245 if (((int16_t)GPR (OP[1])) >= 0) 1246 tmp = (GPR (OP[1]) << 16) | GPR (OP[1] + 1); 1247 else 1248 tmp = ~((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); 1249 1250 foo = 0x40000000; 1251 for (i=1;i<17;i++) 1252 { 1253 if (tmp & foo) 1254 { 1255 SET_GPR (OP[0], (i - 1)); 1256 trace_output_16 (sd, i - 1); 1257 return; 1258 } 1259 foo >>= 1; 1260 } 1261 SET_GPR (OP[0], 16); 1262 trace_output_16 (sd, 16); 1263 } 1264 1265 /* exp */ 1266 void 1267 OP_15002A02 (SIM_DESC sd, SIM_CPU *cpu) 1268 { 1269 int64_t tmp, foo; 1270 int i; 1271 1272 trace_input ("exp", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 1273 tmp = SEXT40(ACC (OP[1])); 1274 if (tmp < 0) 1275 tmp = ~tmp & MASK40; 1276 1277 foo = 0x4000000000LL; 1278 for (i=1;i<25;i++) 1279 { 1280 if (tmp & foo) 1281 { 1282 SET_GPR (OP[0], i - 9); 1283 trace_output_16 (sd, i - 9); 1284 return; 1285 } 1286 foo >>= 1; 1287 } 1288 SET_GPR (OP[0], 16); 1289 trace_output_16 (sd, 16); 1290 } 1291 1292 /* jl */ 1293 void 1294 OP_4D00 (SIM_DESC sd, SIM_CPU *cpu) 1295 { 1296 trace_input ("jl", OP_REG, OP_R0, OP_R1); 1297 SET_GPR (13, PC + 1); 1298 JMP (GPR (OP[0])); 1299 trace_output_void (sd); 1300 } 1301 1302 /* jmp */ 1303 void 1304 OP_4C00 (SIM_DESC sd, SIM_CPU *cpu) 1305 { 1306 trace_input ("jmp", OP_REG, 1307 (OP[0] == 13) ? OP_R0 : OP_VOID, 1308 (OP[0] == 13) ? OP_R1 : OP_VOID); 1309 1310 JMP (GPR (OP[0])); 1311 trace_output_void (sd); 1312 } 1313 1314 /* ld */ 1315 void 1316 OP_30000000 (SIM_DESC sd, SIM_CPU *cpu) 1317 { 1318 uint16_t tmp; 1319 uint16_t addr = OP[1] + GPR (OP[2]); 1320 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); 1321 if ((addr & 1)) 1322 { 1323 trace_output_void (sd); 1324 EXCEPTION (SIM_SIGBUS); 1325 } 1326 tmp = RW (addr); 1327 SET_GPR (OP[0], tmp); 1328 trace_output_16 (sd, tmp); 1329 } 1330 1331 /* ld */ 1332 void 1333 OP_6401 (SIM_DESC sd, SIM_CPU *cpu) 1334 { 1335 uint16_t tmp; 1336 uint16_t addr = GPR (OP[1]); 1337 trace_input ("ld", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); 1338 if ((addr & 1)) 1339 { 1340 trace_output_void (sd); 1341 EXCEPTION (SIM_SIGBUS); 1342 } 1343 tmp = RW (addr); 1344 SET_GPR (OP[0], tmp); 1345 if (OP[0] != OP[1]) 1346 INC_ADDR (OP[1], -2); 1347 trace_output_16 (sd, tmp); 1348 } 1349 1350 /* ld */ 1351 void 1352 OP_6001 (SIM_DESC sd, SIM_CPU *cpu) 1353 { 1354 uint16_t tmp; 1355 uint16_t addr = GPR (OP[1]); 1356 trace_input ("ld", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); 1357 if ((addr & 1)) 1358 { 1359 trace_output_void (sd); 1360 EXCEPTION (SIM_SIGBUS); 1361 } 1362 tmp = RW (addr); 1363 SET_GPR (OP[0], tmp); 1364 if (OP[0] != OP[1]) 1365 INC_ADDR (OP[1], 2); 1366 trace_output_16 (sd, tmp); 1367 } 1368 1369 /* ld */ 1370 void 1371 OP_6000 (SIM_DESC sd, SIM_CPU *cpu) 1372 { 1373 uint16_t tmp; 1374 uint16_t addr = GPR (OP[1]); 1375 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); 1376 if ((addr & 1)) 1377 { 1378 trace_output_void (sd); 1379 EXCEPTION (SIM_SIGBUS); 1380 } 1381 tmp = RW (addr); 1382 SET_GPR (OP[0], tmp); 1383 trace_output_16 (sd, tmp); 1384 } 1385 1386 /* ld */ 1387 void 1388 OP_32010000 (SIM_DESC sd, SIM_CPU *cpu) 1389 { 1390 uint16_t tmp; 1391 uint16_t addr = OP[1]; 1392 trace_input ("ld", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); 1393 if ((addr & 1)) 1394 { 1395 trace_output_void (sd); 1396 EXCEPTION (SIM_SIGBUS); 1397 } 1398 tmp = RW (addr); 1399 SET_GPR (OP[0], tmp); 1400 trace_output_16 (sd, tmp); 1401 } 1402 1403 /* ld2w */ 1404 void 1405 OP_31000000 (SIM_DESC sd, SIM_CPU *cpu) 1406 { 1407 int32_t tmp; 1408 uint16_t addr = OP[1] + GPR (OP[2]); 1409 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); 1410 if ((addr & 1)) 1411 { 1412 trace_output_void (sd); 1413 EXCEPTION (SIM_SIGBUS); 1414 } 1415 tmp = RLW (addr); 1416 SET_GPR32 (OP[0], tmp); 1417 trace_output_32 (sd, tmp); 1418 } 1419 1420 /* ld2w */ 1421 void 1422 OP_6601 (SIM_DESC sd, SIM_CPU *cpu) 1423 { 1424 uint16_t addr = GPR (OP[1]); 1425 int32_t tmp; 1426 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTDEC, OP_VOID); 1427 if ((addr & 1)) 1428 { 1429 trace_output_void (sd); 1430 EXCEPTION (SIM_SIGBUS); 1431 } 1432 tmp = RLW (addr); 1433 SET_GPR32 (OP[0], tmp); 1434 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) 1435 INC_ADDR (OP[1], -4); 1436 trace_output_32 (sd, tmp); 1437 } 1438 1439 /* ld2w */ 1440 void 1441 OP_6201 (SIM_DESC sd, SIM_CPU *cpu) 1442 { 1443 int32_t tmp; 1444 uint16_t addr = GPR (OP[1]); 1445 trace_input ("ld2w", OP_REG_OUTPUT, OP_POSTINC, OP_VOID); 1446 if ((addr & 1)) 1447 { 1448 trace_output_void (sd); 1449 EXCEPTION (SIM_SIGBUS); 1450 } 1451 tmp = RLW (addr); 1452 SET_GPR32 (OP[0], tmp); 1453 if (OP[0] != OP[1] && ((OP[0] + 1) != OP[1])) 1454 INC_ADDR (OP[1], 4); 1455 trace_output_32 (sd, tmp); 1456 } 1457 1458 /* ld2w */ 1459 void 1460 OP_6200 (SIM_DESC sd, SIM_CPU *cpu) 1461 { 1462 uint16_t addr = GPR (OP[1]); 1463 int32_t tmp; 1464 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); 1465 if ((addr & 1)) 1466 { 1467 trace_output_void (sd); 1468 EXCEPTION (SIM_SIGBUS); 1469 } 1470 tmp = RLW (addr); 1471 SET_GPR32 (OP[0], tmp); 1472 trace_output_32 (sd, tmp); 1473 } 1474 1475 /* ld2w */ 1476 void 1477 OP_33010000 (SIM_DESC sd, SIM_CPU *cpu) 1478 { 1479 int32_t tmp; 1480 uint16_t addr = OP[1]; 1481 trace_input ("ld2w", OP_REG_OUTPUT, OP_MEMREF3, OP_VOID); 1482 if ((addr & 1)) 1483 { 1484 trace_output_void (sd); 1485 EXCEPTION (SIM_SIGBUS); 1486 } 1487 tmp = RLW (addr); 1488 SET_GPR32 (OP[0], tmp); 1489 trace_output_32 (sd, tmp); 1490 } 1491 1492 /* ldb */ 1493 void 1494 OP_38000000 (SIM_DESC sd, SIM_CPU *cpu) 1495 { 1496 int16_t tmp; 1497 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); 1498 tmp = SEXT8 (RB (OP[1] + GPR (OP[2]))); 1499 SET_GPR (OP[0], tmp); 1500 trace_output_16 (sd, tmp); 1501 } 1502 1503 /* ldb */ 1504 void 1505 OP_7000 (SIM_DESC sd, SIM_CPU *cpu) 1506 { 1507 int16_t tmp; 1508 trace_input ("ldb", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); 1509 tmp = SEXT8 (RB (GPR (OP[1]))); 1510 SET_GPR (OP[0], tmp); 1511 trace_output_16 (sd, tmp); 1512 } 1513 1514 /* ldi.s */ 1515 void 1516 OP_4001 (SIM_DESC sd, SIM_CPU *cpu) 1517 { 1518 int16_t tmp; 1519 trace_input ("ldi.s", OP_REG_OUTPUT, OP_CONSTANT4, OP_VOID); 1520 tmp = SEXT4 (OP[1]); 1521 SET_GPR (OP[0], tmp); 1522 trace_output_16 (sd, tmp); 1523 } 1524 1525 /* ldi.l */ 1526 void 1527 OP_20000000 (SIM_DESC sd, SIM_CPU *cpu) 1528 { 1529 int16_t tmp; 1530 trace_input ("ldi.l", OP_REG_OUTPUT, OP_CONSTANT16, OP_VOID); 1531 tmp = OP[1]; 1532 SET_GPR (OP[0], tmp); 1533 trace_output_16 (sd, tmp); 1534 } 1535 1536 /* ldub */ 1537 void 1538 OP_39000000 (SIM_DESC sd, SIM_CPU *cpu) 1539 { 1540 int16_t tmp; 1541 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF2, OP_VOID); 1542 tmp = RB (OP[1] + GPR (OP[2])); 1543 SET_GPR (OP[0], tmp); 1544 trace_output_16 (sd, tmp); 1545 } 1546 1547 /* ldub */ 1548 void 1549 OP_7200 (SIM_DESC sd, SIM_CPU *cpu) 1550 { 1551 int16_t tmp; 1552 trace_input ("ldub", OP_REG_OUTPUT, OP_MEMREF, OP_VOID); 1553 tmp = RB (GPR (OP[1])); 1554 SET_GPR (OP[0], tmp); 1555 trace_output_16 (sd, tmp); 1556 } 1557 1558 /* mac */ 1559 void 1560 OP_2A00 (SIM_DESC sd, SIM_CPU *cpu) 1561 { 1562 int64_t tmp; 1563 1564 trace_input ("mac", OP_ACCUM, OP_REG, OP_REG); 1565 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2]))); 1566 1567 if (PSW_FX) 1568 tmp = SEXT40( (tmp << 1) & MASK40); 1569 1570 if (PSW_ST && tmp > SEXT40(MAX32)) 1571 tmp = (MAX32); 1572 1573 tmp += SEXT40 (ACC (OP[0])); 1574 if (PSW_ST) 1575 { 1576 if (tmp > SEXT40(MAX32)) 1577 tmp = (MAX32); 1578 else if (tmp < SEXT40(MIN32)) 1579 tmp = (MIN32); 1580 else 1581 tmp = (tmp & MASK40); 1582 } 1583 else 1584 tmp = (tmp & MASK40); 1585 SET_ACC (OP[0], tmp); 1586 trace_output_40 (sd, tmp); 1587 } 1588 1589 /* macsu */ 1590 void 1591 OP_1A00 (SIM_DESC sd, SIM_CPU *cpu) 1592 { 1593 int64_t tmp; 1594 1595 trace_input ("macsu", OP_ACCUM, OP_REG, OP_REG); 1596 tmp = SEXT40 ((int16_t) GPR (OP[1]) * GPR (OP[2])); 1597 if (PSW_FX) 1598 tmp = SEXT40 ((tmp << 1) & MASK40); 1599 tmp = ((SEXT40 (ACC (OP[0])) + tmp) & MASK40); 1600 SET_ACC (OP[0], tmp); 1601 trace_output_40 (sd, tmp); 1602 } 1603 1604 /* macu */ 1605 void 1606 OP_3A00 (SIM_DESC sd, SIM_CPU *cpu) 1607 { 1608 uint64_t tmp; 1609 uint32_t src1; 1610 uint32_t src2; 1611 1612 trace_input ("macu", OP_ACCUM, OP_REG, OP_REG); 1613 src1 = (uint16_t) GPR (OP[1]); 1614 src2 = (uint16_t) GPR (OP[2]); 1615 tmp = src1 * src2; 1616 if (PSW_FX) 1617 tmp = (tmp << 1); 1618 tmp = ((ACC (OP[0]) + tmp) & MASK40); 1619 SET_ACC (OP[0], tmp); 1620 trace_output_40 (sd, tmp); 1621 } 1622 1623 /* max */ 1624 void 1625 OP_2600 (SIM_DESC sd, SIM_CPU *cpu) 1626 { 1627 int16_t tmp; 1628 trace_input ("max", OP_REG, OP_REG, OP_VOID); 1629 SET_PSW_F1 (PSW_F0); 1630 if ((int16_t) GPR (OP[1]) > (int16_t)GPR (OP[0])) 1631 { 1632 tmp = GPR (OP[1]); 1633 SET_PSW_F0 (1); 1634 } 1635 else 1636 { 1637 tmp = GPR (OP[0]); 1638 SET_PSW_F0 (0); 1639 } 1640 SET_GPR (OP[0], tmp); 1641 trace_output_16 (sd, tmp); 1642 } 1643 1644 /* max */ 1645 void 1646 OP_3600 (SIM_DESC sd, SIM_CPU *cpu) 1647 { 1648 int64_t tmp; 1649 1650 trace_input ("max", OP_ACCUM, OP_DREG, OP_VOID); 1651 SET_PSW_F1 (PSW_F0); 1652 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1); 1653 if (tmp > SEXT40 (ACC (OP[0]))) 1654 { 1655 tmp = (tmp & MASK40); 1656 SET_PSW_F0 (1); 1657 } 1658 else 1659 { 1660 tmp = ACC (OP[0]); 1661 SET_PSW_F0 (0); 1662 } 1663 SET_ACC (OP[0], tmp); 1664 trace_output_40 (sd, tmp); 1665 } 1666 1667 /* max */ 1668 void 1669 OP_3602 (SIM_DESC sd, SIM_CPU *cpu) 1670 { 1671 int64_t tmp; 1672 trace_input ("max", OP_ACCUM, OP_ACCUM, OP_VOID); 1673 SET_PSW_F1 (PSW_F0); 1674 if (SEXT40 (ACC (OP[1])) > SEXT40 (ACC (OP[0]))) 1675 { 1676 tmp = ACC (OP[1]); 1677 SET_PSW_F0 (1); 1678 } 1679 else 1680 { 1681 tmp = ACC (OP[0]); 1682 SET_PSW_F0 (0); 1683 } 1684 SET_ACC (OP[0], tmp); 1685 trace_output_40 (sd, tmp); 1686 } 1687 1688 1689 /* min */ 1690 void 1691 OP_2601 (SIM_DESC sd, SIM_CPU *cpu) 1692 { 1693 int16_t tmp; 1694 trace_input ("min", OP_REG, OP_REG, OP_VOID); 1695 SET_PSW_F1 (PSW_F0); 1696 if ((int16_t)GPR (OP[1]) < (int16_t)GPR (OP[0])) 1697 { 1698 tmp = GPR (OP[1]); 1699 SET_PSW_F0 (1); 1700 } 1701 else 1702 { 1703 tmp = GPR (OP[0]); 1704 SET_PSW_F0 (0); 1705 } 1706 SET_GPR (OP[0], tmp); 1707 trace_output_16 (sd, tmp); 1708 } 1709 1710 /* min */ 1711 void 1712 OP_3601 (SIM_DESC sd, SIM_CPU *cpu) 1713 { 1714 int64_t tmp; 1715 1716 trace_input ("min", OP_ACCUM, OP_DREG, OP_VOID); 1717 SET_PSW_F1 (PSW_F0); 1718 tmp = SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1); 1719 if (tmp < SEXT40(ACC (OP[0]))) 1720 { 1721 tmp = (tmp & MASK40); 1722 SET_PSW_F0 (1); 1723 } 1724 else 1725 { 1726 tmp = ACC (OP[0]); 1727 SET_PSW_F0 (0); 1728 } 1729 SET_ACC (OP[0], tmp); 1730 trace_output_40 (sd, tmp); 1731 } 1732 1733 /* min */ 1734 void 1735 OP_3603 (SIM_DESC sd, SIM_CPU *cpu) 1736 { 1737 int64_t tmp; 1738 trace_input ("min", OP_ACCUM, OP_ACCUM, OP_VOID); 1739 SET_PSW_F1 (PSW_F0); 1740 if (SEXT40(ACC (OP[1])) < SEXT40(ACC (OP[0]))) 1741 { 1742 tmp = ACC (OP[1]); 1743 SET_PSW_F0 (1); 1744 } 1745 else 1746 { 1747 tmp = ACC (OP[0]); 1748 SET_PSW_F0 (0); 1749 } 1750 SET_ACC (OP[0], tmp); 1751 trace_output_40 (sd, tmp); 1752 } 1753 1754 /* msb */ 1755 void 1756 OP_2800 (SIM_DESC sd, SIM_CPU *cpu) 1757 { 1758 int64_t tmp; 1759 1760 trace_input ("msb", OP_ACCUM, OP_REG, OP_REG); 1761 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2]))); 1762 1763 if (PSW_FX) 1764 tmp = SEXT40 ((tmp << 1) & MASK40); 1765 1766 if (PSW_ST && tmp > SEXT40(MAX32)) 1767 tmp = (MAX32); 1768 1769 tmp = SEXT40(ACC (OP[0])) - tmp; 1770 if (PSW_ST) 1771 { 1772 if (tmp > SEXT40(MAX32)) 1773 tmp = (MAX32); 1774 else if (tmp < SEXT40(MIN32)) 1775 tmp = (MIN32); 1776 else 1777 tmp = (tmp & MASK40); 1778 } 1779 else 1780 { 1781 tmp = (tmp & MASK40); 1782 } 1783 SET_ACC (OP[0], tmp); 1784 trace_output_40 (sd, tmp); 1785 } 1786 1787 /* msbsu */ 1788 void 1789 OP_1800 (SIM_DESC sd, SIM_CPU *cpu) 1790 { 1791 int64_t tmp; 1792 1793 trace_input ("msbsu", OP_ACCUM, OP_REG, OP_REG); 1794 tmp = SEXT40 ((int16_t)GPR (OP[1]) * GPR (OP[2])); 1795 if (PSW_FX) 1796 tmp = SEXT40( (tmp << 1) & MASK40); 1797 tmp = ((SEXT40 (ACC (OP[0])) - tmp) & MASK40); 1798 SET_ACC (OP[0], tmp); 1799 trace_output_40 (sd, tmp); 1800 } 1801 1802 /* msbu */ 1803 void 1804 OP_3800 (SIM_DESC sd, SIM_CPU *cpu) 1805 { 1806 uint64_t tmp; 1807 uint32_t src1; 1808 uint32_t src2; 1809 1810 trace_input ("msbu", OP_ACCUM, OP_REG, OP_REG); 1811 src1 = (uint16_t) GPR (OP[1]); 1812 src2 = (uint16_t) GPR (OP[2]); 1813 tmp = src1 * src2; 1814 if (PSW_FX) 1815 tmp = (tmp << 1); 1816 tmp = ((ACC (OP[0]) - tmp) & MASK40); 1817 SET_ACC (OP[0], tmp); 1818 trace_output_40 (sd, tmp); 1819 } 1820 1821 /* mul */ 1822 void 1823 OP_2E00 (SIM_DESC sd, SIM_CPU *cpu) 1824 { 1825 int16_t tmp; 1826 trace_input ("mul", OP_REG, OP_REG, OP_VOID); 1827 tmp = GPR (OP[0]) * GPR (OP[1]); 1828 SET_GPR (OP[0], tmp); 1829 trace_output_16 (sd, tmp); 1830 } 1831 1832 /* mulx */ 1833 void 1834 OP_2C00 (SIM_DESC sd, SIM_CPU *cpu) 1835 { 1836 int64_t tmp; 1837 1838 trace_input ("mulx", OP_ACCUM_OUTPUT, OP_REG, OP_REG); 1839 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * (int16_t)(GPR (OP[2]))); 1840 1841 if (PSW_FX) 1842 tmp = SEXT40 ((tmp << 1) & MASK40); 1843 1844 if (PSW_ST && tmp > SEXT40(MAX32)) 1845 tmp = (MAX32); 1846 else 1847 tmp = (tmp & MASK40); 1848 SET_ACC (OP[0], tmp); 1849 trace_output_40 (sd, tmp); 1850 } 1851 1852 /* mulxsu */ 1853 void 1854 OP_1C00 (SIM_DESC sd, SIM_CPU *cpu) 1855 { 1856 int64_t tmp; 1857 1858 trace_input ("mulxsu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); 1859 tmp = SEXT40 ((int16_t)(GPR (OP[1])) * GPR (OP[2])); 1860 1861 if (PSW_FX) 1862 tmp <<= 1; 1863 tmp = (tmp & MASK40); 1864 SET_ACC (OP[0], tmp); 1865 trace_output_40 (sd, tmp); 1866 } 1867 1868 /* mulxu */ 1869 void 1870 OP_3C00 (SIM_DESC sd, SIM_CPU *cpu) 1871 { 1872 uint64_t tmp; 1873 uint32_t src1; 1874 uint32_t src2; 1875 1876 trace_input ("mulxu", OP_ACCUM_OUTPUT, OP_REG, OP_REG); 1877 src1 = (uint16_t) GPR (OP[1]); 1878 src2 = (uint16_t) GPR (OP[2]); 1879 tmp = src1 * src2; 1880 if (PSW_FX) 1881 tmp <<= 1; 1882 tmp = (tmp & MASK40); 1883 SET_ACC (OP[0], tmp); 1884 trace_output_40 (sd, tmp); 1885 } 1886 1887 /* mv */ 1888 void 1889 OP_4000 (SIM_DESC sd, SIM_CPU *cpu) 1890 { 1891 int16_t tmp; 1892 trace_input ("mv", OP_REG_OUTPUT, OP_REG, OP_VOID); 1893 tmp = GPR (OP[1]); 1894 SET_GPR (OP[0], tmp); 1895 trace_output_16 (sd, tmp); 1896 } 1897 1898 /* mv2w */ 1899 void 1900 OP_5000 (SIM_DESC sd, SIM_CPU *cpu) 1901 { 1902 int32_t tmp; 1903 trace_input ("mv2w", OP_DREG_OUTPUT, OP_DREG, OP_VOID); 1904 tmp = GPR32 (OP[1]); 1905 SET_GPR32 (OP[0], tmp); 1906 trace_output_32 (sd, tmp); 1907 } 1908 1909 /* mv2wfac */ 1910 void 1911 OP_3E00 (SIM_DESC sd, SIM_CPU *cpu) 1912 { 1913 int32_t tmp; 1914 trace_input ("mv2wfac", OP_DREG_OUTPUT, OP_ACCUM, OP_VOID); 1915 tmp = ACC (OP[1]); 1916 SET_GPR32 (OP[0], tmp); 1917 trace_output_32 (sd, tmp); 1918 } 1919 1920 /* mv2wtac */ 1921 void 1922 OP_3E01 (SIM_DESC sd, SIM_CPU *cpu) 1923 { 1924 int64_t tmp; 1925 trace_input ("mv2wtac", OP_DREG, OP_ACCUM_OUTPUT, OP_VOID); 1926 tmp = ((SEXT16 (GPR (OP[0])) << 16 | GPR (OP[0] + 1)) & MASK40); 1927 SET_ACC (OP[1], tmp); 1928 trace_output_40 (sd, tmp); 1929 } 1930 1931 /* mvac */ 1932 void 1933 OP_3E03 (SIM_DESC sd, SIM_CPU *cpu) 1934 { 1935 int64_t tmp; 1936 trace_input ("mvac", OP_ACCUM_OUTPUT, OP_ACCUM, OP_VOID); 1937 tmp = ACC (OP[1]); 1938 SET_ACC (OP[0], tmp); 1939 trace_output_40 (sd, tmp); 1940 } 1941 1942 /* mvb */ 1943 void 1944 OP_5400 (SIM_DESC sd, SIM_CPU *cpu) 1945 { 1946 int16_t tmp; 1947 trace_input ("mvb", OP_REG_OUTPUT, OP_REG, OP_VOID); 1948 tmp = SEXT8 (GPR (OP[1]) & 0xff); 1949 SET_GPR (OP[0], tmp); 1950 trace_output_16 (sd, tmp); 1951 } 1952 1953 /* mvf0f */ 1954 void 1955 OP_4400 (SIM_DESC sd, SIM_CPU *cpu) 1956 { 1957 int16_t tmp; 1958 trace_input ("mvf0f", OP_REG_OUTPUT, OP_REG, OP_VOID); 1959 if (PSW_F0 == 0) 1960 { 1961 tmp = GPR (OP[1]); 1962 SET_GPR (OP[0], tmp); 1963 } 1964 else 1965 tmp = GPR (OP[0]); 1966 trace_output_16 (sd, tmp); 1967 } 1968 1969 /* mvf0t */ 1970 void 1971 OP_4401 (SIM_DESC sd, SIM_CPU *cpu) 1972 { 1973 int16_t tmp; 1974 trace_input ("mvf0t", OP_REG_OUTPUT, OP_REG, OP_VOID); 1975 if (PSW_F0) 1976 { 1977 tmp = GPR (OP[1]); 1978 SET_GPR (OP[0], tmp); 1979 } 1980 else 1981 tmp = GPR (OP[0]); 1982 trace_output_16 (sd, tmp); 1983 } 1984 1985 /* mvfacg */ 1986 void 1987 OP_1E04 (SIM_DESC sd, SIM_CPU *cpu) 1988 { 1989 int16_t tmp; 1990 trace_input ("mvfacg", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 1991 tmp = ((ACC (OP[1]) >> 32) & 0xff); 1992 SET_GPR (OP[0], tmp); 1993 trace_output_16 (sd, tmp); 1994 } 1995 1996 /* mvfachi */ 1997 void 1998 OP_1E00 (SIM_DESC sd, SIM_CPU *cpu) 1999 { 2000 int16_t tmp; 2001 trace_input ("mvfachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 2002 tmp = (ACC (OP[1]) >> 16); 2003 SET_GPR (OP[0], tmp); 2004 trace_output_16 (sd, tmp); 2005 } 2006 2007 /* mvfaclo */ 2008 void 2009 OP_1E02 (SIM_DESC sd, SIM_CPU *cpu) 2010 { 2011 int16_t tmp; 2012 trace_input ("mvfaclo", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 2013 tmp = ACC (OP[1]); 2014 SET_GPR (OP[0], tmp); 2015 trace_output_16 (sd, tmp); 2016 } 2017 2018 /* mvfc */ 2019 void 2020 OP_5200 (SIM_DESC sd, SIM_CPU *cpu) 2021 { 2022 int16_t tmp; 2023 trace_input ("mvfc", OP_REG_OUTPUT, OP_CR, OP_VOID); 2024 tmp = CREG (OP[1]); 2025 SET_GPR (OP[0], tmp); 2026 trace_output_16 (sd, tmp); 2027 } 2028 2029 /* mvtacg */ 2030 void 2031 OP_1E41 (SIM_DESC sd, SIM_CPU *cpu) 2032 { 2033 int64_t tmp; 2034 trace_input ("mvtacg", OP_REG, OP_ACCUM, OP_VOID); 2035 tmp = ((ACC (OP[1]) & MASK32) 2036 | ((int64_t)(GPR (OP[0]) & 0xff) << 32)); 2037 SET_ACC (OP[1], tmp); 2038 trace_output_40 (sd, tmp); 2039 } 2040 2041 /* mvtachi */ 2042 void 2043 OP_1E01 (SIM_DESC sd, SIM_CPU *cpu) 2044 { 2045 uint64_t tmp; 2046 trace_input ("mvtachi", OP_REG, OP_ACCUM, OP_VOID); 2047 tmp = ACC (OP[1]) & 0xffff; 2048 tmp = ((SEXT16 (GPR (OP[0])) << 16 | tmp) & MASK40); 2049 SET_ACC (OP[1], tmp); 2050 trace_output_40 (sd, tmp); 2051 } 2052 2053 /* mvtaclo */ 2054 void 2055 OP_1E21 (SIM_DESC sd, SIM_CPU *cpu) 2056 { 2057 int64_t tmp; 2058 trace_input ("mvtaclo", OP_REG, OP_ACCUM, OP_VOID); 2059 tmp = ((SEXT16 (GPR (OP[0]))) & MASK40); 2060 SET_ACC (OP[1], tmp); 2061 trace_output_40 (sd, tmp); 2062 } 2063 2064 /* mvtc */ 2065 void 2066 OP_5600 (SIM_DESC sd, SIM_CPU *cpu) 2067 { 2068 int16_t tmp; 2069 trace_input ("mvtc", OP_REG, OP_CR_OUTPUT, OP_VOID); 2070 tmp = GPR (OP[0]); 2071 tmp = SET_CREG (OP[1], tmp); 2072 trace_output_16 (sd, tmp); 2073 } 2074 2075 /* mvub */ 2076 void 2077 OP_5401 (SIM_DESC sd, SIM_CPU *cpu) 2078 { 2079 int16_t tmp; 2080 trace_input ("mvub", OP_REG_OUTPUT, OP_REG, OP_VOID); 2081 tmp = (GPR (OP[1]) & 0xff); 2082 SET_GPR (OP[0], tmp); 2083 trace_output_16 (sd, tmp); 2084 } 2085 2086 /* neg */ 2087 void 2088 OP_4605 (SIM_DESC sd, SIM_CPU *cpu) 2089 { 2090 int16_t tmp; 2091 trace_input ("neg", OP_REG, OP_VOID, OP_VOID); 2092 tmp = - GPR (OP[0]); 2093 SET_GPR (OP[0], tmp); 2094 trace_output_16 (sd, tmp); 2095 } 2096 2097 /* neg */ 2098 void 2099 OP_5605 (SIM_DESC sd, SIM_CPU *cpu) 2100 { 2101 int64_t tmp; 2102 2103 trace_input ("neg", OP_ACCUM, OP_VOID, OP_VOID); 2104 tmp = -SEXT40(ACC (OP[0])); 2105 if (PSW_ST) 2106 { 2107 if (tmp > SEXT40(MAX32)) 2108 tmp = (MAX32); 2109 else if (tmp < SEXT40(MIN32)) 2110 tmp = (MIN32); 2111 else 2112 tmp = (tmp & MASK40); 2113 } 2114 else 2115 tmp = (tmp & MASK40); 2116 SET_ACC (OP[0], tmp); 2117 trace_output_40 (sd, tmp); 2118 } 2119 2120 2121 /* nop */ 2122 void 2123 OP_5E00 (SIM_DESC sd, SIM_CPU *cpu) 2124 { 2125 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); 2126 2127 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ 2128 switch (State.ins_type) 2129 { 2130 default: 2131 ins_type_counters[ (int)INS_UNKNOWN ]++; 2132 break; 2133 2134 case INS_LEFT_PARALLEL: 2135 /* Don't count a parallel op that includes a NOP as a true parallel op */ 2136 ins_type_counters[ (int)INS_RIGHT_PARALLEL ]--; 2137 ins_type_counters[ (int)INS_RIGHT ]++; 2138 ins_type_counters[ (int)INS_LEFT_NOPS ]++; 2139 break; 2140 2141 case INS_LEFT: 2142 case INS_LEFT_COND_EXE: 2143 ins_type_counters[ (int)INS_LEFT_NOPS ]++; 2144 break; 2145 2146 case INS_RIGHT_PARALLEL: 2147 /* Don't count a parallel op that includes a NOP as a true parallel op */ 2148 ins_type_counters[ (int)INS_LEFT_PARALLEL ]--; 2149 ins_type_counters[ (int)INS_LEFT ]++; 2150 ins_type_counters[ (int)INS_RIGHT_NOPS ]++; 2151 break; 2152 2153 case INS_RIGHT: 2154 case INS_RIGHT_COND_EXE: 2155 ins_type_counters[ (int)INS_RIGHT_NOPS ]++; 2156 break; 2157 } 2158 2159 trace_output_void (sd); 2160 } 2161 2162 /* not */ 2163 void 2164 OP_4603 (SIM_DESC sd, SIM_CPU *cpu) 2165 { 2166 int16_t tmp; 2167 trace_input ("not", OP_REG, OP_VOID, OP_VOID); 2168 tmp = ~GPR (OP[0]); 2169 SET_GPR (OP[0], tmp); 2170 trace_output_16 (sd, tmp); 2171 } 2172 2173 /* or */ 2174 void 2175 OP_800 (SIM_DESC sd, SIM_CPU *cpu) 2176 { 2177 int16_t tmp; 2178 trace_input ("or", OP_REG, OP_REG, OP_VOID); 2179 tmp = (GPR (OP[0]) | GPR (OP[1])); 2180 SET_GPR (OP[0], tmp); 2181 trace_output_16 (sd, tmp); 2182 } 2183 2184 /* or3 */ 2185 void 2186 OP_4000000 (SIM_DESC sd, SIM_CPU *cpu) 2187 { 2188 int16_t tmp; 2189 trace_input ("or3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); 2190 tmp = (GPR (OP[1]) | OP[2]); 2191 SET_GPR (OP[0], tmp); 2192 trace_output_16 (sd, tmp); 2193 } 2194 2195 /* rac */ 2196 void 2197 OP_5201 (SIM_DESC sd, SIM_CPU *cpu) 2198 { 2199 int64_t tmp; 2200 int shift = SEXT3 (OP[2]); 2201 2202 trace_input ("rac", OP_DREG_OUTPUT, OP_ACCUM, OP_CONSTANT3); 2203 if (OP[1] != 0) 2204 { 2205 sim_io_printf (sd, 2206 "ERROR at PC 0x%x: instruction only valid for A0\n", 2207 PC<<2); 2208 EXCEPTION (SIM_SIGILL); 2209 } 2210 2211 SET_PSW_F1 (PSW_F0); 2212 tmp = SEXT56 ((ACC (0) << 16) | (ACC (1) & 0xffff)); 2213 if (shift >=0) 2214 tmp <<= shift; 2215 else 2216 tmp >>= -shift; 2217 tmp += 0x8000; 2218 tmp >>= 16; /* look at bits 0:43 */ 2219 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) 2220 { 2221 tmp = 0x7fffffff; 2222 SET_PSW_F0 (1); 2223 } 2224 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) 2225 { 2226 tmp = 0x80000000; 2227 SET_PSW_F0 (1); 2228 } 2229 else 2230 { 2231 SET_PSW_F0 (0); 2232 } 2233 SET_GPR32 (OP[0], tmp); 2234 trace_output_32 (sd, tmp); 2235 } 2236 2237 /* rachi */ 2238 void 2239 OP_4201 (SIM_DESC sd, SIM_CPU *cpu) 2240 { 2241 int64_t tmp; 2242 int shift = SEXT3 (OP[2]); 2243 2244 trace_input ("rachi", OP_REG_OUTPUT, OP_ACCUM, OP_CONSTANT3); 2245 SET_PSW_F1 (PSW_F0); 2246 if (shift >=0) 2247 tmp = SEXT40 (ACC (OP[1])) << shift; 2248 else 2249 tmp = SEXT40 (ACC (OP[1])) >> -shift; 2250 tmp += 0x8000; 2251 2252 if (tmp > SEXT44 (SIGNED64 (0x0007fffffff))) 2253 { 2254 tmp = 0x7fff; 2255 SET_PSW_F0 (1); 2256 } 2257 else if (tmp < SEXT44 (SIGNED64 (0xfff80000000))) 2258 { 2259 tmp = 0x8000; 2260 SET_PSW_F0 (1); 2261 } 2262 else 2263 { 2264 tmp = (tmp >> 16); 2265 SET_PSW_F0 (0); 2266 } 2267 SET_GPR (OP[0], tmp); 2268 trace_output_16 (sd, tmp); 2269 } 2270 2271 /* rep */ 2272 void 2273 OP_27000000 (SIM_DESC sd, SIM_CPU *cpu) 2274 { 2275 trace_input ("rep", OP_REG, OP_CONSTANT16, OP_VOID); 2276 SET_RPT_S (PC + 1); 2277 SET_RPT_E (PC + OP[1]); 2278 SET_RPT_C (GPR (OP[0])); 2279 SET_PSW_RP (1); 2280 if (GPR (OP[0]) == 0) 2281 { 2282 sim_io_printf (sd, "ERROR: rep with count=0 is illegal.\n"); 2283 EXCEPTION (SIM_SIGILL); 2284 } 2285 if (OP[1] < 4) 2286 { 2287 sim_io_printf (sd, "ERROR: rep must include at least 4 instructions.\n"); 2288 EXCEPTION (SIM_SIGILL); 2289 } 2290 trace_output_void (sd); 2291 } 2292 2293 /* repi */ 2294 void 2295 OP_2F000000 (SIM_DESC sd, SIM_CPU *cpu) 2296 { 2297 trace_input ("repi", OP_CONSTANT16, OP_CONSTANT16, OP_VOID); 2298 SET_RPT_S (PC + 1); 2299 SET_RPT_E (PC + OP[1]); 2300 SET_RPT_C (OP[0]); 2301 SET_PSW_RP (1); 2302 if (OP[0] == 0) 2303 { 2304 sim_io_printf (sd, "ERROR: repi with count=0 is illegal.\n"); 2305 EXCEPTION (SIM_SIGILL); 2306 } 2307 if (OP[1] < 4) 2308 { 2309 sim_io_printf (sd, "ERROR: repi must include at least 4 instructions.\n"); 2310 EXCEPTION (SIM_SIGILL); 2311 } 2312 trace_output_void (sd); 2313 } 2314 2315 /* rtd */ 2316 void 2317 OP_5F60 (SIM_DESC sd, SIM_CPU *cpu) 2318 { 2319 trace_input ("rtd", OP_VOID, OP_VOID, OP_VOID); 2320 SET_CREG (PSW_CR, DPSW); 2321 JMP(DPC); 2322 trace_output_void (sd); 2323 } 2324 2325 /* rte */ 2326 void 2327 OP_5F40 (SIM_DESC sd, SIM_CPU *cpu) 2328 { 2329 trace_input ("rte", OP_VOID, OP_VOID, OP_VOID); 2330 SET_CREG (PSW_CR, BPSW); 2331 JMP(BPC); 2332 trace_output_void (sd); 2333 } 2334 2335 /* sac */ 2336 void OP_5209 (SIM_DESC sd, SIM_CPU *cpu) 2337 { 2338 int64_t tmp; 2339 2340 trace_input ("sac", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 2341 2342 tmp = SEXT40(ACC (OP[1])); 2343 2344 SET_PSW_F1 (PSW_F0); 2345 2346 if (tmp > SEXT40(MAX32)) 2347 { 2348 tmp = (MAX32); 2349 SET_PSW_F0 (1); 2350 } 2351 else if (tmp < SEXT40(MIN32)) 2352 { 2353 tmp = 0x80000000; 2354 SET_PSW_F0 (1); 2355 } 2356 else 2357 { 2358 tmp = (tmp & MASK32); 2359 SET_PSW_F0 (0); 2360 } 2361 2362 SET_GPR32 (OP[0], tmp); 2363 2364 trace_output_40 (sd, tmp); 2365 } 2366 2367 /* sachi */ 2368 void 2369 OP_4209 (SIM_DESC sd, SIM_CPU *cpu) 2370 { 2371 int64_t tmp; 2372 2373 trace_input ("sachi", OP_REG_OUTPUT, OP_ACCUM, OP_VOID); 2374 2375 tmp = SEXT40(ACC (OP[1])); 2376 2377 SET_PSW_F1 (PSW_F0); 2378 2379 if (tmp > SEXT40(MAX32)) 2380 { 2381 tmp = 0x7fff; 2382 SET_PSW_F0 (1); 2383 } 2384 else if (tmp < SEXT40(MIN32)) 2385 { 2386 tmp = 0x8000; 2387 SET_PSW_F0 (1); 2388 } 2389 else 2390 { 2391 tmp >>= 16; 2392 SET_PSW_F0 (0); 2393 } 2394 2395 SET_GPR (OP[0], tmp); 2396 2397 trace_output_16 (sd, OP[0]); 2398 } 2399 2400 /* sadd */ 2401 void 2402 OP_1223 (SIM_DESC sd, SIM_CPU *cpu) 2403 { 2404 int64_t tmp; 2405 2406 trace_input ("sadd", OP_ACCUM, OP_ACCUM, OP_VOID); 2407 tmp = SEXT40(ACC (OP[0])) + (SEXT40(ACC (OP[1])) >> 16); 2408 if (PSW_ST) 2409 { 2410 if (tmp > SEXT40(MAX32)) 2411 tmp = (MAX32); 2412 else if (tmp < SEXT40(MIN32)) 2413 tmp = (MIN32); 2414 else 2415 tmp = (tmp & MASK40); 2416 } 2417 else 2418 tmp = (tmp & MASK40); 2419 SET_ACC (OP[0], tmp); 2420 trace_output_40 (sd, tmp); 2421 } 2422 2423 /* setf0f */ 2424 void 2425 OP_4611 (SIM_DESC sd, SIM_CPU *cpu) 2426 { 2427 int16_t tmp; 2428 trace_input ("setf0f", OP_REG_OUTPUT, OP_VOID, OP_VOID); 2429 tmp = ((PSW_F0 == 0) ? 1 : 0); 2430 SET_GPR (OP[0], tmp); 2431 trace_output_16 (sd, tmp); 2432 } 2433 2434 /* setf0t */ 2435 void 2436 OP_4613 (SIM_DESC sd, SIM_CPU *cpu) 2437 { 2438 int16_t tmp; 2439 trace_input ("setf0t", OP_REG_OUTPUT, OP_VOID, OP_VOID); 2440 tmp = ((PSW_F0 == 1) ? 1 : 0); 2441 SET_GPR (OP[0], tmp); 2442 trace_output_16 (sd, tmp); 2443 } 2444 2445 /* slae */ 2446 void 2447 OP_3220 (SIM_DESC sd, SIM_CPU *cpu) 2448 { 2449 int64_t tmp; 2450 int16_t reg; 2451 2452 trace_input ("slae", OP_ACCUM, OP_REG, OP_VOID); 2453 2454 reg = SEXT16 (GPR (OP[1])); 2455 2456 if (reg >= 17 || reg <= -17) 2457 { 2458 sim_io_printf (sd, "ERROR: shift value %d too large.\n", reg); 2459 EXCEPTION (SIM_SIGILL); 2460 } 2461 2462 tmp = SEXT40 (ACC (OP[0])); 2463 2464 if (PSW_ST && (tmp < SEXT40 (MIN32) || tmp > SEXT40 (MAX32))) 2465 { 2466 sim_io_printf (sd, "ERROR: accumulator value 0x%.2x%.8lx out of range\n", ((int)(tmp >> 32) & 0xff), ((unsigned long) tmp) & 0xffffffff); 2467 EXCEPTION (SIM_SIGILL); 2468 } 2469 2470 if (reg >= 0 && reg <= 16) 2471 { 2472 tmp = SEXT56 ((SEXT56 (tmp)) << (GPR (OP[1]))); 2473 if (PSW_ST) 2474 { 2475 if (tmp > SEXT40(MAX32)) 2476 tmp = (MAX32); 2477 else if (tmp < SEXT40(MIN32)) 2478 tmp = (MIN32); 2479 else 2480 tmp = (tmp & MASK40); 2481 } 2482 else 2483 tmp = (tmp & MASK40); 2484 } 2485 else 2486 { 2487 tmp = (SEXT40 (ACC (OP[0]))) >> (-GPR (OP[1])); 2488 } 2489 2490 SET_ACC(OP[0], tmp); 2491 2492 trace_output_40 (sd, tmp); 2493 } 2494 2495 /* sleep */ 2496 void 2497 OP_5FC0 (SIM_DESC sd, SIM_CPU *cpu) 2498 { 2499 trace_input ("sleep", OP_VOID, OP_VOID, OP_VOID); 2500 SET_PSW_IE (1); 2501 trace_output_void (sd); 2502 } 2503 2504 /* sll */ 2505 void 2506 OP_2200 (SIM_DESC sd, SIM_CPU *cpu) 2507 { 2508 int16_t tmp; 2509 trace_input ("sll", OP_REG, OP_REG, OP_VOID); 2510 tmp = (GPR (OP[0]) << (GPR (OP[1]) & 0xf)); 2511 SET_GPR (OP[0], tmp); 2512 trace_output_16 (sd, tmp); 2513 } 2514 2515 /* sll */ 2516 void 2517 OP_3200 (SIM_DESC sd, SIM_CPU *cpu) 2518 { 2519 int64_t tmp; 2520 trace_input ("sll", OP_ACCUM, OP_REG, OP_VOID); 2521 if ((GPR (OP[1]) & 31) <= 16) 2522 tmp = SEXT40 (ACC (OP[0])) << (GPR (OP[1]) & 31); 2523 else 2524 { 2525 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); 2526 EXCEPTION (SIM_SIGILL); 2527 } 2528 2529 if (PSW_ST) 2530 { 2531 if (tmp > SEXT40(MAX32)) 2532 tmp = (MAX32); 2533 else if (tmp < SEXT40(MIN32)) 2534 tmp = (MIN32); 2535 else 2536 tmp = (tmp & MASK40); 2537 } 2538 else 2539 tmp = (tmp & MASK40); 2540 SET_ACC (OP[0], tmp); 2541 trace_output_40 (sd, tmp); 2542 } 2543 2544 /* slli */ 2545 void 2546 OP_2201 (SIM_DESC sd, SIM_CPU *cpu) 2547 { 2548 int16_t tmp; 2549 trace_input ("slli", OP_REG, OP_CONSTANT16, OP_VOID); 2550 tmp = (GPR (OP[0]) << OP[1]); 2551 SET_GPR (OP[0], tmp); 2552 trace_output_16 (sd, tmp); 2553 } 2554 2555 /* slli */ 2556 void 2557 OP_3201 (SIM_DESC sd, SIM_CPU *cpu) 2558 { 2559 int64_t tmp; 2560 2561 if (OP[1] == 0) 2562 OP[1] = 16; 2563 2564 trace_input ("slli", OP_ACCUM, OP_CONSTANT16, OP_VOID); 2565 tmp = SEXT40(ACC (OP[0])) << OP[1]; 2566 2567 if (PSW_ST) 2568 { 2569 if (tmp > SEXT40(MAX32)) 2570 tmp = (MAX32); 2571 else if (tmp < SEXT40(MIN32)) 2572 tmp = (MIN32); 2573 else 2574 tmp = (tmp & MASK40); 2575 } 2576 else 2577 tmp = (tmp & MASK40); 2578 SET_ACC (OP[0], tmp); 2579 trace_output_40 (sd, tmp); 2580 } 2581 2582 /* slx */ 2583 void 2584 OP_460B (SIM_DESC sd, SIM_CPU *cpu) 2585 { 2586 int16_t tmp; 2587 trace_input ("slx", OP_REG, OP_VOID, OP_VOID); 2588 tmp = ((GPR (OP[0]) << 1) | PSW_F0); 2589 SET_GPR (OP[0], tmp); 2590 trace_output_16 (sd, tmp); 2591 } 2592 2593 /* sra */ 2594 void 2595 OP_2400 (SIM_DESC sd, SIM_CPU *cpu) 2596 { 2597 int16_t tmp; 2598 trace_input ("sra", OP_REG, OP_REG, OP_VOID); 2599 tmp = (((int16_t)(GPR (OP[0]))) >> (GPR (OP[1]) & 0xf)); 2600 SET_GPR (OP[0], tmp); 2601 trace_output_16 (sd, tmp); 2602 } 2603 2604 /* sra */ 2605 void 2606 OP_3400 (SIM_DESC sd, SIM_CPU *cpu) 2607 { 2608 trace_input ("sra", OP_ACCUM, OP_REG, OP_VOID); 2609 if ((GPR (OP[1]) & 31) <= 16) 2610 { 2611 int64_t tmp = ((SEXT40(ACC (OP[0])) >> (GPR (OP[1]) & 31)) & MASK40); 2612 SET_ACC (OP[0], tmp); 2613 trace_output_40 (sd, tmp); 2614 } 2615 else 2616 { 2617 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); 2618 EXCEPTION (SIM_SIGILL); 2619 } 2620 } 2621 2622 /* srai */ 2623 void 2624 OP_2401 (SIM_DESC sd, SIM_CPU *cpu) 2625 { 2626 int16_t tmp; 2627 trace_input ("srai", OP_REG, OP_CONSTANT16, OP_VOID); 2628 tmp = (((int16_t)(GPR (OP[0]))) >> OP[1]); 2629 SET_GPR (OP[0], tmp); 2630 trace_output_16 (sd, tmp); 2631 } 2632 2633 /* srai */ 2634 void 2635 OP_3401 (SIM_DESC sd, SIM_CPU *cpu) 2636 { 2637 int64_t tmp; 2638 if (OP[1] == 0) 2639 OP[1] = 16; 2640 2641 trace_input ("srai", OP_ACCUM, OP_CONSTANT16, OP_VOID); 2642 tmp = ((SEXT40(ACC (OP[0])) >> OP[1]) & MASK40); 2643 SET_ACC (OP[0], tmp); 2644 trace_output_40 (sd, tmp); 2645 } 2646 2647 /* srl */ 2648 void 2649 OP_2000 (SIM_DESC sd, SIM_CPU *cpu) 2650 { 2651 int16_t tmp; 2652 trace_input ("srl", OP_REG, OP_REG, OP_VOID); 2653 tmp = (GPR (OP[0]) >> (GPR (OP[1]) & 0xf)); 2654 SET_GPR (OP[0], tmp); 2655 trace_output_16 (sd, tmp); 2656 } 2657 2658 /* srl */ 2659 void 2660 OP_3000 (SIM_DESC sd, SIM_CPU *cpu) 2661 { 2662 trace_input ("srl", OP_ACCUM, OP_REG, OP_VOID); 2663 if ((GPR (OP[1]) & 31) <= 16) 2664 { 2665 int64_t tmp = ((uint64_t)((ACC (OP[0]) & MASK40) >> (GPR (OP[1]) & 31))); 2666 SET_ACC (OP[0], tmp); 2667 trace_output_40 (sd, tmp); 2668 } 2669 else 2670 { 2671 sim_io_printf (sd, "ERROR: shift value %d too large.\n", GPR (OP[1]) & 31); 2672 EXCEPTION (SIM_SIGILL); 2673 } 2674 2675 } 2676 2677 /* srli */ 2678 void 2679 OP_2001 (SIM_DESC sd, SIM_CPU *cpu) 2680 { 2681 int16_t tmp; 2682 trace_input ("srli", OP_REG, OP_CONSTANT16, OP_VOID); 2683 tmp = (GPR (OP[0]) >> OP[1]); 2684 SET_GPR (OP[0], tmp); 2685 trace_output_16 (sd, tmp); 2686 } 2687 2688 /* srli */ 2689 void 2690 OP_3001 (SIM_DESC sd, SIM_CPU *cpu) 2691 { 2692 int64_t tmp; 2693 if (OP[1] == 0) 2694 OP[1] = 16; 2695 2696 trace_input ("srli", OP_ACCUM, OP_CONSTANT16, OP_VOID); 2697 tmp = ((uint64_t)(ACC (OP[0]) & MASK40) >> OP[1]); 2698 SET_ACC (OP[0], tmp); 2699 trace_output_40 (sd, tmp); 2700 } 2701 2702 /* srx */ 2703 void 2704 OP_4609 (SIM_DESC sd, SIM_CPU *cpu) 2705 { 2706 uint16_t tmp; 2707 trace_input ("srx", OP_REG, OP_VOID, OP_VOID); 2708 tmp = PSW_F0 << 15; 2709 tmp = ((GPR (OP[0]) >> 1) | tmp); 2710 SET_GPR (OP[0], tmp); 2711 trace_output_16 (sd, tmp); 2712 } 2713 2714 /* st */ 2715 void 2716 OP_34000000 (SIM_DESC sd, SIM_CPU *cpu) 2717 { 2718 uint16_t addr = OP[1] + GPR (OP[2]); 2719 trace_input ("st", OP_REG, OP_MEMREF2, OP_VOID); 2720 if ((addr & 1)) 2721 { 2722 trace_output_void (sd); 2723 EXCEPTION (SIM_SIGBUS); 2724 } 2725 SW (addr, GPR (OP[0])); 2726 trace_output_void (sd); 2727 } 2728 2729 /* st */ 2730 void 2731 OP_6800 (SIM_DESC sd, SIM_CPU *cpu) 2732 { 2733 uint16_t addr = GPR (OP[1]); 2734 trace_input ("st", OP_REG, OP_MEMREF, OP_VOID); 2735 if ((addr & 1)) 2736 { 2737 trace_output_void (sd); 2738 EXCEPTION (SIM_SIGBUS); 2739 } 2740 SW (addr, GPR (OP[0])); 2741 trace_output_void (sd); 2742 } 2743 2744 /* st */ 2745 /* st Rsrc1,@-SP */ 2746 void 2747 OP_6C1F (SIM_DESC sd, SIM_CPU *cpu) 2748 { 2749 uint16_t addr = GPR (OP[1]) - 2; 2750 trace_input ("st", OP_REG, OP_PREDEC, OP_VOID); 2751 if (OP[1] != 15) 2752 { 2753 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); 2754 EXCEPTION (SIM_SIGILL); 2755 } 2756 if ((addr & 1)) 2757 { 2758 trace_output_void (sd); 2759 EXCEPTION (SIM_SIGBUS); 2760 } 2761 SW (addr, GPR (OP[0])); 2762 SET_GPR (OP[1], addr); 2763 trace_output_void (sd); 2764 } 2765 2766 /* st */ 2767 void 2768 OP_6801 (SIM_DESC sd, SIM_CPU *cpu) 2769 { 2770 uint16_t addr = GPR (OP[1]); 2771 trace_input ("st", OP_REG, OP_POSTINC, OP_VOID); 2772 if ((addr & 1)) 2773 { 2774 trace_output_void (sd); 2775 EXCEPTION (SIM_SIGBUS); 2776 } 2777 SW (addr, GPR (OP[0])); 2778 INC_ADDR (OP[1], 2); 2779 trace_output_void (sd); 2780 } 2781 2782 /* st */ 2783 void 2784 OP_6C01 (SIM_DESC sd, SIM_CPU *cpu) 2785 { 2786 uint16_t addr = GPR (OP[1]); 2787 trace_input ("st", OP_REG, OP_POSTDEC, OP_VOID); 2788 if ( OP[1] == 15 ) 2789 { 2790 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n"); 2791 EXCEPTION (SIM_SIGILL); 2792 } 2793 if ((addr & 1)) 2794 { 2795 trace_output_void (sd); 2796 EXCEPTION (SIM_SIGBUS); 2797 } 2798 SW (addr, GPR (OP[0])); 2799 INC_ADDR (OP[1], -2); 2800 trace_output_void (sd); 2801 } 2802 2803 /* st */ 2804 void 2805 OP_36010000 (SIM_DESC sd, SIM_CPU *cpu) 2806 { 2807 uint16_t addr = OP[1]; 2808 trace_input ("st", OP_REG, OP_MEMREF3, OP_VOID); 2809 if ((addr & 1)) 2810 { 2811 trace_output_void (sd); 2812 EXCEPTION (SIM_SIGBUS); 2813 } 2814 SW (addr, GPR (OP[0])); 2815 trace_output_void (sd); 2816 } 2817 2818 /* st2w */ 2819 void 2820 OP_35000000 (SIM_DESC sd, SIM_CPU *cpu) 2821 { 2822 uint16_t addr = GPR (OP[2])+ OP[1]; 2823 trace_input ("st2w", OP_DREG, OP_MEMREF2, OP_VOID); 2824 if ((addr & 1)) 2825 { 2826 trace_output_void (sd); 2827 EXCEPTION (SIM_SIGBUS); 2828 } 2829 SW (addr + 0, GPR (OP[0] + 0)); 2830 SW (addr + 2, GPR (OP[0] + 1)); 2831 trace_output_void (sd); 2832 } 2833 2834 /* st2w */ 2835 void 2836 OP_6A00 (SIM_DESC sd, SIM_CPU *cpu) 2837 { 2838 uint16_t addr = GPR (OP[1]); 2839 trace_input ("st2w", OP_DREG, OP_MEMREF, OP_VOID); 2840 if ((addr & 1)) 2841 { 2842 trace_output_void (sd); 2843 EXCEPTION (SIM_SIGBUS); 2844 } 2845 SW (addr + 0, GPR (OP[0] + 0)); 2846 SW (addr + 2, GPR (OP[0] + 1)); 2847 trace_output_void (sd); 2848 } 2849 2850 /* st2w */ 2851 void 2852 OP_6E1F (SIM_DESC sd, SIM_CPU *cpu) 2853 { 2854 uint16_t addr = GPR (OP[1]) - 4; 2855 trace_input ("st2w", OP_DREG, OP_PREDEC, OP_VOID); 2856 if ( OP[1] != 15 ) 2857 { 2858 sim_io_printf (sd, "ERROR: cannot pre-decrement any registers but r15 (SP).\n"); 2859 EXCEPTION (SIM_SIGILL); 2860 } 2861 if ((addr & 1)) 2862 { 2863 trace_output_void (sd); 2864 EXCEPTION (SIM_SIGBUS); 2865 } 2866 SW (addr + 0, GPR (OP[0] + 0)); 2867 SW (addr + 2, GPR (OP[0] + 1)); 2868 SET_GPR (OP[1], addr); 2869 trace_output_void (sd); 2870 } 2871 2872 /* st2w */ 2873 void 2874 OP_6A01 (SIM_DESC sd, SIM_CPU *cpu) 2875 { 2876 uint16_t addr = GPR (OP[1]); 2877 trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID); 2878 if ((addr & 1)) 2879 { 2880 trace_output_void (sd); 2881 EXCEPTION (SIM_SIGBUS); 2882 } 2883 SW (addr + 0, GPR (OP[0] + 0)); 2884 SW (addr + 2, GPR (OP[0] + 1)); 2885 INC_ADDR (OP[1], 4); 2886 trace_output_void (sd); 2887 } 2888 2889 /* st2w */ 2890 void 2891 OP_6E01 (SIM_DESC sd, SIM_CPU *cpu) 2892 { 2893 uint16_t addr = GPR (OP[1]); 2894 trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID); 2895 if ( OP[1] == 15 ) 2896 { 2897 sim_io_printf (sd, "ERROR: cannot post-decrement register r15 (SP).\n"); 2898 EXCEPTION (SIM_SIGILL); 2899 } 2900 if ((addr & 1)) 2901 { 2902 trace_output_void (sd); 2903 EXCEPTION (SIM_SIGBUS); 2904 } 2905 SW (addr + 0, GPR (OP[0] + 0)); 2906 SW (addr + 2, GPR (OP[0] + 1)); 2907 INC_ADDR (OP[1], -4); 2908 trace_output_void (sd); 2909 } 2910 2911 /* st2w */ 2912 void 2913 OP_37010000 (SIM_DESC sd, SIM_CPU *cpu) 2914 { 2915 uint16_t addr = OP[1]; 2916 trace_input ("st2w", OP_DREG, OP_MEMREF3, OP_VOID); 2917 if ((addr & 1)) 2918 { 2919 trace_output_void (sd); 2920 EXCEPTION (SIM_SIGBUS); 2921 } 2922 SW (addr + 0, GPR (OP[0] + 0)); 2923 SW (addr + 2, GPR (OP[0] + 1)); 2924 trace_output_void (sd); 2925 } 2926 2927 /* stb */ 2928 void 2929 OP_3C000000 (SIM_DESC sd, SIM_CPU *cpu) 2930 { 2931 trace_input ("stb", OP_REG, OP_MEMREF2, OP_VOID); 2932 SB (GPR (OP[2]) + OP[1], GPR (OP[0])); 2933 trace_output_void (sd); 2934 } 2935 2936 /* stb */ 2937 void 2938 OP_7800 (SIM_DESC sd, SIM_CPU *cpu) 2939 { 2940 trace_input ("stb", OP_REG, OP_MEMREF, OP_VOID); 2941 SB (GPR (OP[1]), GPR (OP[0])); 2942 trace_output_void (sd); 2943 } 2944 2945 /* stop */ 2946 void 2947 OP_5FE0 (SIM_DESC sd, SIM_CPU *cpu) 2948 { 2949 trace_input ("stop", OP_VOID, OP_VOID, OP_VOID); 2950 trace_output_void (sd); 2951 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0); 2952 } 2953 2954 /* sub */ 2955 void 2956 OP_0 (SIM_DESC sd, SIM_CPU *cpu) 2957 { 2958 uint16_t a = GPR (OP[0]); 2959 uint16_t b = GPR (OP[1]); 2960 uint16_t tmp = (a - b); 2961 trace_input ("sub", OP_REG, OP_REG, OP_VOID); 2962 /* see ../common/sim-alu.h for a more extensive discussion on how to 2963 compute the carry/overflow bits. */ 2964 SET_PSW_C (a >= b); 2965 SET_GPR (OP[0], tmp); 2966 trace_output_16 (sd, tmp); 2967 } 2968 2969 /* sub */ 2970 void 2971 OP_1001 (SIM_DESC sd, SIM_CPU *cpu) 2972 { 2973 int64_t tmp; 2974 2975 trace_input ("sub", OP_ACCUM, OP_DREG, OP_VOID); 2976 tmp = SEXT40(ACC (OP[0])) - (SEXT16 (GPR (OP[1])) << 16 | GPR (OP[1] + 1)); 2977 if (PSW_ST) 2978 { 2979 if (tmp > SEXT40(MAX32)) 2980 tmp = (MAX32); 2981 else if (tmp < SEXT40(MIN32)) 2982 tmp = (MIN32); 2983 else 2984 tmp = (tmp & MASK40); 2985 } 2986 else 2987 tmp = (tmp & MASK40); 2988 SET_ACC (OP[0], tmp); 2989 2990 trace_output_40 (sd, tmp); 2991 } 2992 2993 /* sub */ 2994 2995 void 2996 OP_1003 (SIM_DESC sd, SIM_CPU *cpu) 2997 { 2998 int64_t tmp; 2999 3000 trace_input ("sub", OP_ACCUM, OP_ACCUM, OP_VOID); 3001 tmp = SEXT40(ACC (OP[0])) - SEXT40(ACC (OP[1])); 3002 if (PSW_ST) 3003 { 3004 if (tmp > SEXT40(MAX32)) 3005 tmp = (MAX32); 3006 else if (tmp < SEXT40(MIN32)) 3007 tmp = (MIN32); 3008 else 3009 tmp = (tmp & MASK40); 3010 } 3011 else 3012 tmp = (tmp & MASK40); 3013 SET_ACC (OP[0], tmp); 3014 3015 trace_output_40 (sd, tmp); 3016 } 3017 3018 /* sub2w */ 3019 void 3020 OP_1000 (SIM_DESC sd, SIM_CPU *cpu) 3021 { 3022 uint32_t tmp, a, b; 3023 3024 trace_input ("sub2w", OP_DREG, OP_DREG, OP_VOID); 3025 a = (uint32_t)((GPR (OP[0]) << 16) | GPR (OP[0] + 1)); 3026 b = (uint32_t)((GPR (OP[1]) << 16) | GPR (OP[1] + 1)); 3027 /* see ../common/sim-alu.h for a more extensive discussion on how to 3028 compute the carry/overflow bits */ 3029 tmp = a - b; 3030 SET_PSW_C (a >= b); 3031 SET_GPR32 (OP[0], tmp); 3032 trace_output_32 (sd, tmp); 3033 } 3034 3035 /* subac3 */ 3036 void 3037 OP_17000000 (SIM_DESC sd, SIM_CPU *cpu) 3038 { 3039 int64_t tmp; 3040 3041 trace_input ("subac3", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); 3042 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40 (ACC (OP[2])); 3043 SET_GPR32 (OP[0], tmp); 3044 trace_output_32 (sd, tmp); 3045 } 3046 3047 /* subac3 */ 3048 void 3049 OP_17000002 (SIM_DESC sd, SIM_CPU *cpu) 3050 { 3051 int64_t tmp; 3052 3053 trace_input ("subac3", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); 3054 tmp = SEXT40 (ACC (OP[1])) - SEXT40(ACC (OP[2])); 3055 SET_GPR32 (OP[0], tmp); 3056 trace_output_32 (sd, tmp); 3057 } 3058 3059 /* subac3s */ 3060 void 3061 OP_17001000 (SIM_DESC sd, SIM_CPU *cpu) 3062 { 3063 int64_t tmp; 3064 3065 trace_input ("subac3s", OP_DREG_OUTPUT, OP_DREG, OP_ACCUM); 3066 SET_PSW_F1 (PSW_F0); 3067 tmp = SEXT40 ((GPR (OP[1]) << 16) | GPR (OP[1] + 1)) - SEXT40(ACC (OP[2])); 3068 if (tmp > SEXT40(MAX32)) 3069 { 3070 tmp = (MAX32); 3071 SET_PSW_F0 (1); 3072 } 3073 else if (tmp < SEXT40(MIN32)) 3074 { 3075 tmp = (MIN32); 3076 SET_PSW_F0 (1); 3077 } 3078 else 3079 { 3080 SET_PSW_F0 (0); 3081 } 3082 SET_GPR32 (OP[0], tmp); 3083 trace_output_32 (sd, tmp); 3084 } 3085 3086 /* subac3s */ 3087 void 3088 OP_17001002 (SIM_DESC sd, SIM_CPU *cpu) 3089 { 3090 int64_t tmp; 3091 3092 trace_input ("subac3s", OP_DREG_OUTPUT, OP_ACCUM, OP_ACCUM); 3093 SET_PSW_F1 (PSW_F0); 3094 tmp = SEXT40(ACC (OP[1])) - SEXT40(ACC (OP[2])); 3095 if (tmp > SEXT40(MAX32)) 3096 { 3097 tmp = (MAX32); 3098 SET_PSW_F0 (1); 3099 } 3100 else if (tmp < SEXT40(MIN32)) 3101 { 3102 tmp = (MIN32); 3103 SET_PSW_F0 (1); 3104 } 3105 else 3106 { 3107 SET_PSW_F0 (0); 3108 } 3109 SET_GPR32 (OP[0], tmp); 3110 trace_output_32 (sd, tmp); 3111 } 3112 3113 /* subi */ 3114 void 3115 OP_1 (SIM_DESC sd, SIM_CPU *cpu) 3116 { 3117 unsigned tmp; 3118 if (OP[1] == 0) 3119 OP[1] = 16; 3120 3121 trace_input ("subi", OP_REG, OP_CONSTANT16, OP_VOID); 3122 /* see ../common/sim-alu.h for a more extensive discussion on how to 3123 compute the carry/overflow bits. */ 3124 /* since OP[1] is never <= 0, -OP[1] == ~OP[1]+1 can never overflow */ 3125 tmp = ((unsigned)(uint16_t) GPR (OP[0]) 3126 + (unsigned)(uint16_t) ( - OP[1])); 3127 SET_PSW_C (tmp >= (1 << 16)); 3128 SET_GPR (OP[0], tmp); 3129 trace_output_16 (sd, tmp); 3130 } 3131 3132 /* trap */ 3133 void 3134 OP_5F00 (SIM_DESC sd, SIM_CPU *cpu) 3135 { 3136 host_callback *cb = STATE_CALLBACK (sd); 3137 3138 trace_input ("trap", OP_CONSTANT4, OP_VOID, OP_VOID); 3139 trace_output_void (sd); 3140 3141 switch (OP[0]) 3142 { 3143 default: 3144 #if (DEBUG & DEBUG_TRAP) == 0 3145 { 3146 uint16_t vec = OP[0] + TRAP_VECTOR_START; 3147 SET_BPC (PC + 1); 3148 SET_BPSW (PSW); 3149 SET_PSW (PSW & PSW_SM_BIT); 3150 JMP (vec); 3151 break; 3152 } 3153 #else /* if debugging use trap to print registers */ 3154 { 3155 int i; 3156 static int first_time = 1; 3157 3158 if (first_time) 3159 { 3160 first_time = 0; 3161 sim_io_printf (sd, "Trap # PC "); 3162 for (i = 0; i < 16; i++) 3163 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i); 3164 sim_io_printf (sd, " a0 a1 f0 f1 c\n"); 3165 } 3166 3167 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); 3168 3169 for (i = 0; i < 16; i++) 3170 sim_io_printf (sd, " %.4x", (int) GPR (i)); 3171 3172 for (i = 0; i < 2; i++) 3173 sim_io_printf (sd, " %.2x%.8lx", 3174 ((int)(ACC (i) >> 32) & 0xff), 3175 ((unsigned long) ACC (i)) & 0xffffffff); 3176 3177 sim_io_printf (sd, " %d %d %d\n", 3178 PSW_F0 != 0, PSW_F1 != 0, PSW_C != 0); 3179 sim_io_flush_stdout (sd); 3180 break; 3181 } 3182 #endif 3183 case 15: /* new system call trap */ 3184 /* Trap 15 is used for simulating low-level I/O */ 3185 { 3186 uint32_t result = 0; 3187 errno = 0; 3188 3189 /* Registers passed to trap 0 */ 3190 3191 #define FUNC GPR (4) /* function number */ 3192 #define PARM1 GPR (0) /* optional parm 1 */ 3193 #define PARM2 GPR (1) /* optional parm 2 */ 3194 #define PARM3 GPR (2) /* optional parm 3 */ 3195 #define PARM4 GPR (3) /* optional parm 3 */ 3196 3197 /* Registers set by trap 0 */ 3198 3199 #define RETVAL(X) do { result = (X); SET_GPR (0, result); } while (0) 3200 #define RETVAL32(X) do { result = (X); SET_GPR (0, result >> 16); SET_GPR (1, result); } while (0) 3201 #define RETERR(X) SET_GPR (4, (X)) /* return error code */ 3202 3203 /* Turn a pointer in a register into a pointer into real memory. */ 3204 3205 #define MEMPTR(x) ((char *)(dmem_addr (sd, cpu, x))) 3206 3207 switch (FUNC) 3208 { 3209 #if !defined(__GO32__) && !defined(_WIN32) 3210 case TARGET_NEWLIB_D10V_SYS_fork: 3211 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); 3212 RETVAL (fork ()); 3213 trace_output_16 (sd, result); 3214 break; 3215 3216 #define getpid() 47 3217 case TARGET_NEWLIB_D10V_SYS_getpid: 3218 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 3219 RETVAL (getpid ()); 3220 trace_output_16 (sd, result); 3221 break; 3222 3223 case TARGET_NEWLIB_D10V_SYS_kill: 3224 trace_input ("<kill>", OP_R0, OP_R1, OP_VOID); 3225 if (PARM1 == getpid ()) 3226 { 3227 trace_output_void (sd); 3228 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2); 3229 } 3230 else 3231 { 3232 int os_sig = -1; 3233 switch (PARM2) 3234 { 3235 #ifdef SIGHUP 3236 case 1: os_sig = SIGHUP; break; 3237 #endif 3238 #ifdef SIGINT 3239 case 2: os_sig = SIGINT; break; 3240 #endif 3241 #ifdef SIGQUIT 3242 case 3: os_sig = SIGQUIT; break; 3243 #endif 3244 #ifdef SIGILL 3245 case 4: os_sig = SIGILL; break; 3246 #endif 3247 #ifdef SIGTRAP 3248 case 5: os_sig = SIGTRAP; break; 3249 #endif 3250 #ifdef SIGABRT 3251 case 6: os_sig = SIGABRT; break; 3252 #elif defined(SIGIOT) 3253 case 6: os_sig = SIGIOT; break; 3254 #endif 3255 #ifdef SIGEMT 3256 case 7: os_sig = SIGEMT; break; 3257 #endif 3258 #ifdef SIGFPE 3259 case 8: os_sig = SIGFPE; break; 3260 #endif 3261 #ifdef SIGKILL 3262 case 9: os_sig = SIGKILL; break; 3263 #endif 3264 #ifdef SIGBUS 3265 case 10: os_sig = SIGBUS; break; 3266 #endif 3267 #ifdef SIGSEGV 3268 case 11: os_sig = SIGSEGV; break; 3269 #endif 3270 #ifdef SIGSYS 3271 case 12: os_sig = SIGSYS; break; 3272 #endif 3273 #ifdef SIGPIPE 3274 case 13: os_sig = SIGPIPE; break; 3275 #endif 3276 #ifdef SIGALRM 3277 case 14: os_sig = SIGALRM; break; 3278 #endif 3279 #ifdef SIGTERM 3280 case 15: os_sig = SIGTERM; break; 3281 #endif 3282 #ifdef SIGURG 3283 case 16: os_sig = SIGURG; break; 3284 #endif 3285 #ifdef SIGSTOP 3286 case 17: os_sig = SIGSTOP; break; 3287 #endif 3288 #ifdef SIGTSTP 3289 case 18: os_sig = SIGTSTP; break; 3290 #endif 3291 #ifdef SIGCONT 3292 case 19: os_sig = SIGCONT; break; 3293 #endif 3294 #ifdef SIGCHLD 3295 case 20: os_sig = SIGCHLD; break; 3296 #elif defined(SIGCLD) 3297 case 20: os_sig = SIGCLD; break; 3298 #endif 3299 #ifdef SIGTTIN 3300 case 21: os_sig = SIGTTIN; break; 3301 #endif 3302 #ifdef SIGTTOU 3303 case 22: os_sig = SIGTTOU; break; 3304 #endif 3305 #ifdef SIGIO 3306 case 23: os_sig = SIGIO; break; 3307 #elif defined (SIGPOLL) 3308 case 23: os_sig = SIGPOLL; break; 3309 #endif 3310 #ifdef SIGXCPU 3311 case 24: os_sig = SIGXCPU; break; 3312 #endif 3313 #ifdef SIGXFSZ 3314 case 25: os_sig = SIGXFSZ; break; 3315 #endif 3316 #ifdef SIGVTALRM 3317 case 26: os_sig = SIGVTALRM; break; 3318 #endif 3319 #ifdef SIGPROF 3320 case 27: os_sig = SIGPROF; break; 3321 #endif 3322 #ifdef SIGWINCH 3323 case 28: os_sig = SIGWINCH; break; 3324 #endif 3325 #ifdef SIGLOST 3326 case 29: os_sig = SIGLOST; break; 3327 #endif 3328 #ifdef SIGUSR1 3329 case 30: os_sig = SIGUSR1; break; 3330 #endif 3331 #ifdef SIGUSR2 3332 case 31: os_sig = SIGUSR2; break; 3333 #endif 3334 } 3335 3336 if (os_sig == -1) 3337 { 3338 trace_output_void (sd); 3339 sim_io_printf (sd, "Unknown signal %d\n", PARM2); 3340 sim_io_flush_stdout (sd); 3341 EXCEPTION (SIM_SIGILL); 3342 } 3343 else 3344 { 3345 RETVAL (kill (PARM1, PARM2)); 3346 trace_output_16 (sd, result); 3347 } 3348 } 3349 break; 3350 3351 case TARGET_NEWLIB_D10V_SYS_execve: 3352 trace_input ("<execve>", OP_R0, OP_R1, OP_R2); 3353 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), 3354 (char **)MEMPTR (PARM3))); 3355 trace_output_16 (sd, result); 3356 break; 3357 3358 case TARGET_NEWLIB_D10V_SYS_execv: 3359 trace_input ("<execv>", OP_R0, OP_R1, OP_VOID); 3360 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); 3361 trace_output_16 (sd, result); 3362 break; 3363 3364 case TARGET_NEWLIB_D10V_SYS_pipe: 3365 { 3366 reg_t buf; 3367 int host_fd[2]; 3368 3369 trace_input ("<pipe>", OP_R0, OP_VOID, OP_VOID); 3370 buf = PARM1; 3371 RETVAL (pipe (host_fd)); 3372 SW (buf, host_fd[0]); 3373 buf += sizeof(uint16_t); 3374 SW (buf, host_fd[1]); 3375 trace_output_16 (sd, result); 3376 } 3377 break; 3378 3379 #if 0 3380 case TARGET_NEWLIB_D10V_SYS_wait: 3381 { 3382 int status; 3383 trace_input ("<wait>", OP_R0, OP_VOID, OP_VOID); 3384 RETVAL (wait (&status)); 3385 if (PARM1) 3386 SW (PARM1, status); 3387 trace_output_16 (sd, result); 3388 } 3389 break; 3390 #endif 3391 #else 3392 case TARGET_NEWLIB_D10V_SYS_getpid: 3393 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 3394 RETVAL (1); 3395 trace_output_16 (sd, result); 3396 break; 3397 3398 case TARGET_NEWLIB_D10V_SYS_kill: 3399 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); 3400 trace_output_void (sd); 3401 sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, PARM2); 3402 break; 3403 #endif 3404 3405 case TARGET_NEWLIB_D10V_SYS_read: 3406 trace_input ("<read>", OP_R0, OP_R1, OP_R2); 3407 RETVAL (cb->read (cb, PARM1, MEMPTR (PARM2), PARM3)); 3408 trace_output_16 (sd, result); 3409 break; 3410 3411 case TARGET_NEWLIB_D10V_SYS_write: 3412 trace_input ("<write>", OP_R0, OP_R1, OP_R2); 3413 if (PARM1 == 1) 3414 RETVAL ((int)cb->write_stdout (cb, MEMPTR (PARM2), PARM3)); 3415 else 3416 RETVAL ((int)cb->write (cb, PARM1, MEMPTR (PARM2), PARM3)); 3417 trace_output_16 (sd, result); 3418 break; 3419 3420 case TARGET_NEWLIB_D10V_SYS_lseek: 3421 trace_input ("<lseek>", OP_R0, OP_R1, OP_R2); 3422 RETVAL32 (cb->lseek (cb, PARM1, 3423 ((((unsigned long) PARM2) << 16) 3424 || (unsigned long) PARM3), 3425 PARM4)); 3426 trace_output_32 (sd, result); 3427 break; 3428 3429 case TARGET_NEWLIB_D10V_SYS_close: 3430 trace_input ("<close>", OP_R0, OP_VOID, OP_VOID); 3431 RETVAL (cb->close (cb, PARM1)); 3432 trace_output_16 (sd, result); 3433 break; 3434 3435 case TARGET_NEWLIB_D10V_SYS_open: 3436 trace_input ("<open>", OP_R0, OP_R1, OP_R2); 3437 RETVAL (cb->open (cb, MEMPTR (PARM1), PARM2)); 3438 trace_output_16 (sd, result); 3439 break; 3440 3441 case TARGET_NEWLIB_D10V_SYS_exit: 3442 trace_input ("<exit>", OP_R0, OP_VOID, OP_VOID); 3443 trace_output_void (sd); 3444 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (0)); 3445 break; 3446 3447 case TARGET_NEWLIB_D10V_SYS_stat: 3448 trace_input ("<stat>", OP_R0, OP_R1, OP_VOID); 3449 /* stat system call */ 3450 { 3451 struct stat host_stat; 3452 reg_t buf; 3453 3454 RETVAL (stat (MEMPTR (PARM1), &host_stat)); 3455 3456 buf = PARM2; 3457 3458 /* The hard-coded offsets and sizes were determined by using 3459 * the D10V compiler on a test program that used struct stat. 3460 */ 3461 SW (buf, host_stat.st_dev); 3462 SW (buf+2, host_stat.st_ino); 3463 SW (buf+4, host_stat.st_mode); 3464 SW (buf+6, host_stat.st_nlink); 3465 SW (buf+8, host_stat.st_uid); 3466 SW (buf+10, host_stat.st_gid); 3467 SW (buf+12, host_stat.st_rdev); 3468 SLW (buf+16, host_stat.st_size); 3469 SLW (buf+20, host_stat.st_atime); 3470 SLW (buf+28, host_stat.st_mtime); 3471 SLW (buf+36, host_stat.st_ctime); 3472 } 3473 trace_output_16 (sd, result); 3474 break; 3475 3476 case TARGET_NEWLIB_D10V_SYS_chown: 3477 trace_input ("<chown>", OP_R0, OP_R1, OP_R2); 3478 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); 3479 trace_output_16 (sd, result); 3480 break; 3481 3482 case TARGET_NEWLIB_D10V_SYS_chmod: 3483 trace_input ("<chmod>", OP_R0, OP_R1, OP_R2); 3484 RETVAL (chmod (MEMPTR (PARM1), PARM2)); 3485 trace_output_16 (sd, result); 3486 break; 3487 3488 #if 0 3489 case TARGET_NEWLIB_D10V_SYS_utime: 3490 trace_input ("<utime>", OP_R0, OP_R1, OP_R2); 3491 /* Cast the second argument to void *, to avoid type mismatch 3492 if a prototype is present. */ 3493 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); 3494 trace_output_16 (sd, result); 3495 break; 3496 #endif 3497 3498 #if 0 3499 case TARGET_NEWLIB_D10V_SYS_time: 3500 trace_input ("<time>", OP_R0, OP_R1, OP_R2); 3501 RETVAL32 (time (PARM1 ? MEMPTR (PARM1) : NULL)); 3502 trace_output_32 (sd, result); 3503 break; 3504 #endif 3505 3506 default: 3507 cb->error (cb, "Unknown syscall %d", FUNC); 3508 } 3509 if ((uint16_t) result == (uint16_t) -1) 3510 RETERR (cb->get_errno (cb)); 3511 else 3512 RETERR (0); 3513 break; 3514 } 3515 } 3516 } 3517 3518 /* tst0i */ 3519 void 3520 OP_7000000 (SIM_DESC sd, SIM_CPU *cpu) 3521 { 3522 trace_input ("tst0i", OP_REG, OP_CONSTANT16, OP_VOID); 3523 SET_PSW_F1 (PSW_F0);; 3524 SET_PSW_F0 ((GPR (OP[0]) & OP[1]) ? 1 : 0); 3525 trace_output_flag (sd); 3526 } 3527 3528 /* tst1i */ 3529 void 3530 OP_F000000 (SIM_DESC sd, SIM_CPU *cpu) 3531 { 3532 trace_input ("tst1i", OP_REG, OP_CONSTANT16, OP_VOID); 3533 SET_PSW_F1 (PSW_F0); 3534 SET_PSW_F0 ((~(GPR (OP[0])) & OP[1]) ? 1 : 0); 3535 trace_output_flag (sd); 3536 } 3537 3538 /* wait */ 3539 void 3540 OP_5F80 (SIM_DESC sd, SIM_CPU *cpu) 3541 { 3542 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); 3543 SET_PSW_IE (1); 3544 trace_output_void (sd); 3545 } 3546 3547 /* xor */ 3548 void 3549 OP_A00 (SIM_DESC sd, SIM_CPU *cpu) 3550 { 3551 int16_t tmp; 3552 trace_input ("xor", OP_REG, OP_REG, OP_VOID); 3553 tmp = (GPR (OP[0]) ^ GPR (OP[1])); 3554 SET_GPR (OP[0], tmp); 3555 trace_output_16 (sd, tmp); 3556 } 3557 3558 /* xor3 */ 3559 void 3560 OP_5000000 (SIM_DESC sd, SIM_CPU *cpu) 3561 { 3562 int16_t tmp; 3563 trace_input ("xor3", OP_REG_OUTPUT, OP_REG, OP_CONSTANT16); 3564 tmp = (GPR (OP[1]) ^ OP[2]); 3565 SET_GPR (OP[0], tmp); 3566 trace_output_16 (sd, tmp); 3567 } 3568