1 /* Simulation code for the CR16 processor. 2 Copyright (C) 2008-2023 Free Software Foundation, Inc. 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 /* This must come before any other includes. */ 21 #include "defs.h" 22 23 #include <signal.h> 24 #include <errno.h> 25 #include <sys/types.h> 26 #include <sys/stat.h> 27 #ifdef HAVE_UNISTD_H 28 #include <unistd.h> 29 #endif 30 #include <string.h> 31 #include <time.h> 32 #include <sys/time.h> 33 34 #include "sim-main.h" 35 #include "sim-signal.h" 36 #include "simops.h" 37 #include "target-newlib-syscall.h" 38 39 #ifdef HAVE_UTIME_H 40 #include <utime.h> 41 #endif 42 #include <sys/wait.h> 43 44 #define EXCEPTION(sig) sim_engine_halt (sd, cpu, NULL, PC, sim_stopped, sig) 45 46 enum op_types { 47 OP_VOID, 48 OP_CONSTANT3, 49 OP_UCONSTANT3, 50 OP_CONSTANT4, 51 OP_CONSTANT4_1, 52 OP_CONSTANT5, 53 OP_CONSTANT6, 54 OP_CONSTANT16, 55 OP_UCONSTANT16, 56 OP_CONSTANT20, 57 OP_UCONSTANT20, 58 OP_CONSTANT32, 59 OP_UCONSTANT32, 60 OP_MEMREF, 61 OP_MEMREF2, 62 OP_MEMREF3, 63 64 OP_DISP5, 65 OP_DISP17, 66 OP_DISP25, 67 OP_DISPE9, 68 //OP_ABS20, 69 OP_ABS20_OUTPUT, 70 //OP_ABS24, 71 OP_ABS24_OUTPUT, 72 73 OP_R_BASE_DISPS16, 74 OP_R_BASE_DISP20, 75 OP_R_BASE_DISPS20, 76 OP_R_BASE_DISPE20, 77 78 OP_RP_BASE_DISPE0, 79 OP_RP_BASE_DISP4, 80 OP_RP_BASE_DISPE4, 81 OP_RP_BASE_DISP14, 82 OP_RP_BASE_DISP16, 83 OP_RP_BASE_DISP20, 84 OP_RP_BASE_DISPS20, 85 OP_RP_BASE_DISPE20, 86 87 OP_R_INDEX7_ABS20, 88 OP_R_INDEX8_ABS20, 89 90 OP_RP_INDEX_DISP0, 91 OP_RP_INDEX_DISP14, 92 OP_RP_INDEX_DISP20, 93 OP_RP_INDEX_DISPS20, 94 95 OP_REG, 96 OP_REGP, 97 OP_PROC_REG, 98 OP_PROC_REGP, 99 OP_COND, 100 OP_RA 101 }; 102 103 104 enum { 105 PSR_MASK = (PSR_I_BIT 106 | PSR_P_BIT 107 | PSR_E_BIT 108 | PSR_N_BIT 109 | PSR_Z_BIT 110 | PSR_F_BIT 111 | PSR_U_BIT 112 | PSR_L_BIT 113 | PSR_T_BIT 114 | PSR_C_BIT), 115 /* The following bits in the PSR _can't_ be set by instructions such 116 as mvtc. */ 117 PSR_HW_MASK = (PSR_MASK) 118 }; 119 120 /* cond Code Condition True State 121 * EQ Equal Z flag is 1 122 * NE Not Equal Z flag is 0 123 * CS Carry Set C flag is 1 124 * CC Carry Clear C flag is 0 125 * HI Higher L flag is 1 126 * LS Lower or Same L flag is 0 127 * GT Greater Than N flag is 1 128 * LE Less Than or Equal To N flag is 0 129 * FS Flag Set F flag is 1 130 * FC Flag Clear F flag is 0 131 * LO Lower Z and L flags are 0 132 * HS Higher or Same Z or L flag is 1 133 * LT Less Than Z and N flags are 0 134 * GE Greater Than or Equal To Z or N flag is 1. */ 135 136 static int cond_stat(int cc) 137 { 138 switch (cc) 139 { 140 case 0: return PSR_Z; break; 141 case 1: return !PSR_Z; break; 142 case 2: return PSR_C; break; 143 case 3: return !PSR_C; break; 144 case 4: return PSR_L; break; 145 case 5: return !PSR_L; break; 146 case 6: return PSR_N; break; 147 case 7: return !PSR_N; break; 148 case 8: return PSR_F; break; 149 case 9: return !PSR_F; break; 150 case 10: return !PSR_Z && !PSR_L; break; 151 case 11: return PSR_Z || PSR_L; break; 152 case 12: return !PSR_Z && !PSR_N; break; 153 case 13: return PSR_Z || PSR_N; break; 154 case 14: return 1; break; /*ALWAYS. */ 155 default: 156 // case NEVER: return false; break; 157 //case NO_COND_CODE: 158 //panic("Shouldn't have NO_COND_CODE in an actual instruction!"); 159 return 0; break; 160 } 161 return 0; 162 } 163 164 165 creg_t 166 move_to_cr (SIM_DESC sd, SIM_CPU *cpu, int cr, creg_t mask, creg_t val, int psw_hw_p) 167 { 168 /* A MASK bit is set when the corresponding bit in the CR should 169 be left alone. */ 170 /* This assumes that (VAL & MASK) == 0. */ 171 switch (cr) 172 { 173 case PSR_CR: 174 if (psw_hw_p) 175 val &= PSR_HW_MASK; 176 #if 0 177 else 178 val &= PSR_MASK; 179 sim_io_printf 180 (sd, 181 "ERROR at PC 0x%x: ST can only be set when FX is set.\n", PC); 182 EXCEPTION (SIM_SIGILL); 183 #endif 184 /* keep an up-to-date psw around for tracing. */ 185 State.trace.psw = (State.trace.psw & mask) | val; 186 break; 187 default: 188 break; 189 } 190 /* only issue an update if the register is being changed. */ 191 if ((State.cregs[cr] & ~mask) != val) 192 SLOT_PEND_MASK (State.cregs[cr], mask, val); 193 194 return val; 195 } 196 197 #ifdef DEBUG 198 static void trace_input_func (SIM_DESC sd, 199 const char *name, 200 enum op_types in1, 201 enum op_types in2, 202 enum op_types in3); 203 204 #define trace_input(name, in1, in2, in3) do { if (cr16_debug) trace_input_func (sd, name, in1, in2, in3); } while (0) 205 206 #ifndef SIZE_INSTRUCTION 207 #define SIZE_INSTRUCTION 8 208 #endif 209 210 #ifndef SIZE_OPERANDS 211 #define SIZE_OPERANDS 18 212 #endif 213 214 #ifndef SIZE_VALUES 215 #define SIZE_VALUES 13 216 #endif 217 218 #ifndef SIZE_LOCATION 219 #define SIZE_LOCATION 20 220 #endif 221 222 #ifndef SIZE_PC 223 #define SIZE_PC 4 224 #endif 225 226 #ifndef SIZE_LINE_NUMBER 227 #define SIZE_LINE_NUMBER 2 228 #endif 229 230 static void 231 trace_input_func (SIM_DESC sd, const char *name, enum op_types in1, enum op_types in2, enum op_types in3) 232 { 233 char *comma; 234 enum op_types in[3]; 235 int i; 236 char buf[1024]; 237 char *p; 238 long tmp; 239 char *type; 240 const char *filename; 241 const char *functionname; 242 unsigned int linenumber; 243 bfd_vma byte_pc; 244 245 if ((cr16_debug & DEBUG_TRACE) == 0) 246 return; 247 248 switch (State.ins_type) 249 { 250 default: 251 case INS_UNKNOWN: type = " ?"; break; 252 } 253 254 if ((cr16_debug & DEBUG_LINE_NUMBER) == 0) 255 sim_io_printf (sd, 256 "0x%.*x %s: %-*s ", 257 SIZE_PC, (unsigned)PC, 258 type, 259 SIZE_INSTRUCTION, name); 260 261 else 262 { 263 buf[0] = '\0'; 264 byte_pc = PC; 265 if (STATE_TEXT_SECTION (sd) 266 && byte_pc >= STATE_TEXT_START (sd) 267 && byte_pc < STATE_TEXT_END (sd)) 268 { 269 filename = (const char *)0; 270 functionname = (const char *)0; 271 linenumber = 0; 272 if (bfd_find_nearest_line (STATE_PROG_BFD (sd), 273 STATE_TEXT_SECTION (sd), 274 (struct bfd_symbol **)0, 275 byte_pc - STATE_TEXT_START (sd), 276 &filename, &functionname, &linenumber)) 277 { 278 p = buf; 279 if (linenumber) 280 { 281 sprintf (p, "#%-*d ", SIZE_LINE_NUMBER, linenumber); 282 p += strlen (p); 283 } 284 else 285 { 286 sprintf (p, "%-*s ", SIZE_LINE_NUMBER+1, "---"); 287 p += SIZE_LINE_NUMBER+2; 288 } 289 290 if (functionname) 291 { 292 sprintf (p, "%s ", functionname); 293 p += strlen (p); 294 } 295 else if (filename) 296 { 297 char *q = strrchr (filename, '/'); 298 sprintf (p, "%s ", (q) ? q+1 : filename); 299 p += strlen (p); 300 } 301 302 if (*p == ' ') 303 *p = '\0'; 304 } 305 } 306 307 sim_io_printf (sd, 308 "0x%.*x %s: %-*.*s %-*s ", 309 SIZE_PC, (unsigned)PC, 310 type, 311 SIZE_LOCATION, SIZE_LOCATION, buf, 312 SIZE_INSTRUCTION, name); 313 } 314 315 in[0] = in1; 316 in[1] = in2; 317 in[2] = in3; 318 comma = ""; 319 p = buf; 320 for (i = 0; i < 3; i++) 321 { 322 switch (in[i]) 323 { 324 case OP_VOID: 325 break; 326 327 case OP_REG: 328 case OP_REGP: 329 sprintf (p, "%sr%d", comma, OP[i]); 330 p += strlen (p); 331 comma = ","; 332 break; 333 334 case OP_PROC_REG: 335 sprintf (p, "%scr%d", comma, OP[i]); 336 p += strlen (p); 337 comma = ","; 338 break; 339 340 case OP_CONSTANT16: 341 sprintf (p, "%s%d", comma, OP[i]); 342 p += strlen (p); 343 comma = ","; 344 break; 345 346 case OP_CONSTANT4: 347 sprintf (p, "%s%d", comma, SEXT4(OP[i])); 348 p += strlen (p); 349 comma = ","; 350 break; 351 352 case OP_CONSTANT3: 353 sprintf (p, "%s%d", comma, SEXT3(OP[i])); 354 p += strlen (p); 355 comma = ","; 356 break; 357 358 case OP_MEMREF: 359 sprintf (p, "%s@r%d", comma, OP[i]); 360 p += strlen (p); 361 comma = ","; 362 break; 363 364 case OP_MEMREF2: 365 sprintf (p, "%s@(%d,r%d)", comma, (int16_t)OP[i], OP[i+1]); 366 p += strlen (p); 367 comma = ","; 368 break; 369 370 case OP_MEMREF3: 371 sprintf (p, "%s@%d", comma, OP[i]); 372 p += strlen (p); 373 comma = ","; 374 break; 375 } 376 } 377 378 if ((cr16_debug & DEBUG_VALUES) == 0) 379 { 380 *p++ = '\n'; 381 *p = '\0'; 382 sim_io_printf (sd, "%s", buf); 383 } 384 else 385 { 386 *p = '\0'; 387 sim_io_printf (sd, "%-*s", SIZE_OPERANDS, buf); 388 389 p = buf; 390 for (i = 0; i < 3; i++) 391 { 392 buf[0] = '\0'; 393 switch (in[i]) 394 { 395 case OP_VOID: 396 sim_io_printf (sd, "%*s", SIZE_VALUES, ""); 397 break; 398 399 case OP_REG: 400 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 401 (uint16_t) GPR (OP[i])); 402 break; 403 404 case OP_REGP: 405 tmp = (long)((((uint32_t) GPR (OP[i])) << 16) | ((uint32_t) GPR (OP[i] + 1))); 406 sim_io_printf (sd, "%*s0x%.8lx", SIZE_VALUES-10, "", tmp); 407 break; 408 409 case OP_PROC_REG: 410 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 411 (uint16_t) CREG (OP[i])); 412 break; 413 414 case OP_CONSTANT16: 415 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 416 (uint16_t)OP[i]); 417 break; 418 419 case OP_CONSTANT4: 420 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 421 (uint16_t)SEXT4(OP[i])); 422 break; 423 424 case OP_CONSTANT3: 425 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 426 (uint16_t)SEXT3(OP[i])); 427 break; 428 429 case OP_MEMREF2: 430 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 431 (uint16_t)OP[i]); 432 sim_io_printf (sd, "%*s0x%.4x", SIZE_VALUES-6, "", 433 (uint16_t)GPR (OP[i + 1])); 434 i++; 435 break; 436 } 437 } 438 } 439 440 sim_io_flush_stdout (sd); 441 } 442 443 static void 444 do_trace_output_flush (SIM_DESC sd) 445 { 446 sim_io_flush_stdout (sd); 447 } 448 449 static void 450 do_trace_output_finish (SIM_DESC sd) 451 { 452 sim_io_printf (sd, 453 " F0=%d F1=%d C=%d\n", 454 (State.trace.psw & PSR_F_BIT) != 0, 455 (State.trace.psw & PSR_F_BIT) != 0, 456 (State.trace.psw & PSR_C_BIT) != 0); 457 sim_io_flush_stdout (sd); 458 } 459 460 #if 0 461 static void 462 trace_output_40 (SIM_DESC sd, uint64_t val) 463 { 464 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 465 { 466 sim_io_printf (sd, 467 " :: %*s0x%.2x%.8lx", 468 SIZE_VALUES - 12, 469 "", 470 ((int)(val >> 32) & 0xff), 471 ((unsigned long) val) & 0xffffffff); 472 do_trace_output_finish (); 473 } 474 } 475 #endif 476 477 static void 478 trace_output_32 (SIM_DESC sd, uint32_t val) 479 { 480 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 481 { 482 sim_io_printf (sd, 483 " :: %*s0x%.8x", 484 SIZE_VALUES - 10, 485 "", 486 (int) val); 487 do_trace_output_finish (sd); 488 } 489 } 490 491 static void 492 trace_output_16 (SIM_DESC sd, uint16_t val) 493 { 494 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 495 { 496 sim_io_printf (sd, 497 " :: %*s0x%.4x", 498 SIZE_VALUES - 6, 499 "", 500 (int) val); 501 do_trace_output_finish (sd); 502 } 503 } 504 505 static void 506 trace_output_void (SIM_DESC sd) 507 { 508 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 509 { 510 sim_io_printf (sd, "\n"); 511 do_trace_output_flush (sd); 512 } 513 } 514 515 static void 516 trace_output_flag (SIM_DESC sd) 517 { 518 if ((cr16_debug & (DEBUG_TRACE | DEBUG_VALUES)) == (DEBUG_TRACE | DEBUG_VALUES)) 519 { 520 sim_io_printf (sd, 521 " :: %*s", 522 SIZE_VALUES, 523 ""); 524 do_trace_output_finish (sd); 525 } 526 } 527 528 529 530 531 #else 532 #define trace_input(NAME, IN1, IN2, IN3) 533 #define trace_output(RESULT) 534 #endif 535 536 /* addub. */ 537 void 538 OP_2C_8 (SIM_DESC sd, SIM_CPU *cpu) 539 { 540 uint8_t tmp; 541 uint8_t a = OP[0] & 0xff; 542 uint16_t b = (GPR (OP[1])) & 0xff; 543 trace_input ("addub", OP_CONSTANT4_1, OP_REG, OP_VOID); 544 tmp = (a + b) & 0xff; 545 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 546 trace_output_16 (sd, tmp); 547 } 548 549 /* addub. */ 550 void 551 OP_2CB_C (SIM_DESC sd, SIM_CPU *cpu) 552 { 553 uint16_t tmp; 554 uint8_t a = ((OP[0]) & 0xff), b = (GPR (OP[1])) & 0xff; 555 trace_input ("addub", OP_CONSTANT16, OP_REG, OP_VOID); 556 tmp = (a + b) & 0xff; 557 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 558 trace_output_16 (sd, tmp); 559 } 560 561 /* addub. */ 562 void 563 OP_2D_8 (SIM_DESC sd, SIM_CPU *cpu) 564 { 565 uint8_t a = (GPR (OP[0])) & 0xff; 566 uint8_t b = (GPR (OP[1])) & 0xff; 567 uint16_t tmp = (a + b) & 0xff; 568 trace_input ("addub", OP_REG, OP_REG, OP_VOID); 569 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 570 trace_output_16 (sd, tmp); 571 } 572 573 /* adduw. */ 574 void 575 OP_2E_8 (SIM_DESC sd, SIM_CPU *cpu) 576 { 577 uint16_t a = OP[0]; 578 uint16_t b = GPR (OP[1]); 579 uint16_t tmp = (a + b); 580 trace_input ("adduw", OP_CONSTANT4_1, OP_REG, OP_VOID); 581 SET_GPR (OP[1], tmp); 582 trace_output_16 (sd, tmp); 583 } 584 585 /* adduw. */ 586 void 587 OP_2EB_C (SIM_DESC sd, SIM_CPU *cpu) 588 { 589 uint16_t a = OP[0]; 590 uint16_t b = GPR (OP[1]); 591 uint16_t tmp = (a + b); 592 trace_input ("adduw", OP_CONSTANT16, OP_REG, OP_VOID); 593 SET_GPR (OP[1], tmp); 594 trace_output_16 (sd, tmp); 595 } 596 597 /* adduw. */ 598 void 599 OP_2F_8 (SIM_DESC sd, SIM_CPU *cpu) 600 { 601 uint16_t a = GPR (OP[0]); 602 uint16_t b = GPR (OP[1]); 603 uint16_t tmp = (a + b); 604 trace_input ("adduw", OP_REG, OP_REG, OP_VOID); 605 SET_GPR (OP[1], tmp); 606 trace_output_16 (sd, tmp); 607 } 608 609 /* addb. */ 610 void 611 OP_30_8 (SIM_DESC sd, SIM_CPU *cpu) 612 { 613 uint8_t a = OP[0]; 614 uint8_t b = (GPR (OP[1]) & 0xff); 615 uint16_t tmp = (a + b) & 0xff; 616 trace_input ("addb", OP_CONSTANT4_1, OP_REG, OP_VOID); 617 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 618 SET_PSR_C (tmp > 0xFF); 619 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 620 trace_output_16 (sd, tmp); 621 } 622 623 /* addb. */ 624 void 625 OP_30B_C (SIM_DESC sd, SIM_CPU *cpu) 626 { 627 uint8_t a = (OP[0]) & 0xff; 628 uint8_t b = (GPR (OP[1]) & 0xff); 629 uint16_t tmp = (a + b) & 0xff; 630 trace_input ("addb", OP_CONSTANT16, OP_REG, OP_VOID); 631 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 632 SET_PSR_C (tmp > 0xFF); 633 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 634 trace_output_16 (sd, tmp); 635 } 636 637 /* addb. */ 638 void 639 OP_31_8 (SIM_DESC sd, SIM_CPU *cpu) 640 { 641 uint8_t a = (GPR (OP[0]) & 0xff); 642 uint8_t b = (GPR (OP[1]) & 0xff); 643 uint16_t tmp = (a + b) & 0xff; 644 trace_input ("addb", OP_REG, OP_REG, OP_VOID); 645 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 646 SET_PSR_C (tmp > 0xFF); 647 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 648 trace_output_16 (sd, tmp); 649 } 650 651 /* addw. */ 652 void 653 OP_32_8 (SIM_DESC sd, SIM_CPU *cpu) 654 { 655 int16_t a = OP[0]; 656 uint16_t tmp, b = GPR (OP[1]); 657 tmp = (a + b); 658 trace_input ("addw", OP_CONSTANT4_1, OP_REG, OP_VOID); 659 SET_GPR (OP[1], tmp); 660 SET_PSR_C (tmp > 0xFFFF); 661 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 662 trace_output_16 (sd, tmp); 663 } 664 665 /* addw. */ 666 void 667 OP_32B_C (SIM_DESC sd, SIM_CPU *cpu) 668 { 669 int16_t a = OP[0]; 670 uint16_t tmp, b = GPR (OP[1]); 671 tmp = (a + b); 672 trace_input ("addw", OP_CONSTANT16, OP_REG, OP_VOID); 673 SET_GPR (OP[1], tmp); 674 SET_PSR_C (tmp > 0xFFFF); 675 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 676 trace_output_16 (sd, tmp); 677 } 678 679 /* addw. */ 680 void 681 OP_33_8 (SIM_DESC sd, SIM_CPU *cpu) 682 { 683 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 684 trace_input ("addw", OP_REG, OP_REG, OP_VOID); 685 tmp = (a + b); 686 SET_GPR (OP[1], tmp); 687 SET_PSR_C (tmp > 0xFFFF); 688 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 689 trace_output_16 (sd, tmp); 690 } 691 692 /* addcb. */ 693 void 694 OP_34_8 (SIM_DESC sd, SIM_CPU *cpu) 695 { 696 uint8_t tmp, a = OP[0] & 0xff, b = (GPR (OP[1])) & 0xff; 697 trace_input ("addcb", OP_CONSTANT4_1, OP_REG, OP_REG); 698 tmp = (a + b + PSR_C) & 0xff; 699 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 700 SET_PSR_C (tmp > 0xFF); 701 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 702 trace_output_16 (sd, tmp); 703 } 704 705 /* addcb. */ 706 void 707 OP_34B_C (SIM_DESC sd, SIM_CPU *cpu) 708 { 709 int8_t a = OP[0] & 0xff; 710 uint8_t b = (GPR (OP[1])) & 0xff; 711 uint8_t tmp = (a + b + PSR_C) & 0xff; 712 trace_input ("addcb", OP_CONSTANT16, OP_REG, OP_VOID); 713 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 714 SET_PSR_C (tmp > 0xFF); 715 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 716 trace_output_16 (sd, tmp); 717 } 718 719 /* addcb. */ 720 void 721 OP_35_8 (SIM_DESC sd, SIM_CPU *cpu) 722 { 723 uint8_t a = (GPR (OP[0])) & 0xff; 724 uint8_t b = (GPR (OP[1])) & 0xff; 725 uint8_t tmp = (a + b + PSR_C) & 0xff; 726 trace_input ("addcb", OP_REG, OP_REG, OP_VOID); 727 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 728 SET_PSR_C (tmp > 0xFF); 729 SET_PSR_F (((a & 0x80) == (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 730 trace_output_16 (sd, tmp); 731 } 732 733 /* addcw. */ 734 void 735 OP_36_8 (SIM_DESC sd, SIM_CPU *cpu) 736 { 737 uint16_t a = OP[0]; 738 uint16_t b = GPR (OP[1]); 739 uint16_t tmp = (a + b + PSR_C); 740 trace_input ("addcw", OP_CONSTANT4_1, OP_REG, OP_VOID); 741 SET_GPR (OP[1], tmp); 742 SET_PSR_C (tmp > 0xFFFF); 743 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 744 trace_output_16 (sd, tmp); 745 } 746 747 /* addcw. */ 748 void 749 OP_36B_C (SIM_DESC sd, SIM_CPU *cpu) 750 { 751 int16_t a = OP[0]; 752 uint16_t b = GPR (OP[1]); 753 uint16_t tmp = (a + b + PSR_C); 754 trace_input ("addcw", OP_CONSTANT16, OP_REG, OP_VOID); 755 SET_GPR (OP[1], tmp); 756 SET_PSR_C (tmp > 0xFFFF); 757 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 758 trace_output_16 (sd, tmp); 759 } 760 761 /* addcw. */ 762 void 763 OP_37_8 (SIM_DESC sd, SIM_CPU *cpu) 764 { 765 uint16_t a = GPR (OP[1]); 766 uint16_t b = GPR (OP[1]); 767 uint16_t tmp = (a + b + PSR_C); 768 trace_input ("addcw", OP_REG, OP_REG, OP_VOID); 769 SET_GPR (OP[1], tmp); 770 SET_PSR_C (tmp > 0xFFFF); 771 SET_PSR_F (((a & 0x8000) == (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 772 trace_output_16 (sd, tmp); 773 } 774 775 /* addd. */ 776 void 777 OP_60_8 (SIM_DESC sd, SIM_CPU *cpu) 778 { 779 int16_t a = (OP[0]); 780 uint32_t b = GPR32 (OP[1]); 781 uint32_t tmp = (a + b); 782 trace_input ("addd", OP_CONSTANT4_1, OP_REGP, OP_VOID); 783 SET_GPR32 (OP[1], tmp); 784 SET_PSR_C (tmp > 0xFFFFFFFF); 785 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 786 trace_output_32 (sd, tmp); 787 } 788 789 /* addd. */ 790 void 791 OP_60B_C (SIM_DESC sd, SIM_CPU *cpu) 792 { 793 int32_t a = (SEXT16(OP[0])); 794 uint32_t b = GPR32 (OP[1]); 795 uint32_t tmp = (a + b); 796 trace_input ("addd", OP_CONSTANT16, OP_REGP, OP_VOID); 797 SET_GPR32 (OP[1], tmp); 798 SET_PSR_C (tmp > 0xFFFFFFFF); 799 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 800 trace_output_32 (sd, tmp); 801 } 802 803 /* addd. */ 804 void 805 OP_61_8 (SIM_DESC sd, SIM_CPU *cpu) 806 { 807 uint32_t a = GPR32 (OP[0]); 808 uint32_t b = GPR32 (OP[1]); 809 uint32_t tmp = (a + b); 810 trace_input ("addd", OP_REGP, OP_REGP, OP_VOID); 811 SET_GPR32 (OP[1], tmp); 812 trace_output_32 (sd, tmp); 813 SET_PSR_C (tmp > 0xFFFFFFFF); 814 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 815 } 816 817 /* addd. */ 818 void 819 OP_4_8 (SIM_DESC sd, SIM_CPU *cpu) 820 { 821 uint32_t a = OP[0]; 822 uint32_t b = GPR32 (OP[1]); 823 uint32_t tmp; 824 trace_input ("addd", OP_CONSTANT20, OP_REGP, OP_VOID); 825 tmp = (a + b); 826 SET_GPR32 (OP[1], tmp); 827 SET_PSR_C (tmp > 0xFFFFFFFF); 828 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 829 trace_output_32 (sd, tmp); 830 } 831 832 /* addd. */ 833 void 834 OP_2_C (SIM_DESC sd, SIM_CPU *cpu) 835 { 836 int32_t a = OP[0]; 837 uint32_t b = GPR32 (OP[1]); 838 uint32_t tmp; 839 trace_input ("addd", OP_CONSTANT32, OP_REGP, OP_VOID); 840 tmp = (a + b); 841 SET_GPR32 (OP[1], tmp); 842 SET_PSR_C (tmp > 0xFFFFFFFF); 843 SET_PSR_F (((a & 0x80000000) == (b & 0x80000000)) && ((b & 0x80000000) != (tmp & 0x80000000))); 844 trace_output_32 (sd, tmp); 845 } 846 847 /* andb. */ 848 void 849 OP_20_8 (SIM_DESC sd, SIM_CPU *cpu) 850 { 851 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 852 trace_input ("andb", OP_CONSTANT4, OP_REG, OP_VOID); 853 tmp = a & b; 854 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 855 trace_output_16 (sd, tmp); 856 } 857 858 /* andb. */ 859 void 860 OP_20B_C (SIM_DESC sd, SIM_CPU *cpu) 861 { 862 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 863 trace_input ("andb", OP_CONSTANT16, OP_REG, OP_VOID); 864 tmp = a & b; 865 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 866 trace_output_16 (sd, tmp); 867 } 868 869 /* andb. */ 870 void 871 OP_21_8 (SIM_DESC sd, SIM_CPU *cpu) 872 { 873 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 874 trace_input ("andb", OP_REG, OP_REG, OP_VOID); 875 tmp = a & b; 876 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 877 trace_output_16 (sd, tmp); 878 } 879 880 /* andw. */ 881 void 882 OP_22_8 (SIM_DESC sd, SIM_CPU *cpu) 883 { 884 uint16_t tmp, a = OP[0], b = GPR (OP[1]); 885 trace_input ("andw", OP_CONSTANT4, OP_REG, OP_VOID); 886 tmp = a & b; 887 SET_GPR (OP[1], tmp); 888 trace_output_16 (sd, tmp); 889 } 890 891 /* andw. */ 892 void 893 OP_22B_C (SIM_DESC sd, SIM_CPU *cpu) 894 { 895 uint16_t tmp, a = OP[0], b = GPR (OP[1]); 896 trace_input ("andw", OP_CONSTANT16, OP_REG, OP_VOID); 897 tmp = a & b; 898 SET_GPR (OP[1], tmp); 899 trace_output_16 (sd, tmp); 900 } 901 902 /* andw. */ 903 void 904 OP_23_8 (SIM_DESC sd, SIM_CPU *cpu) 905 { 906 uint16_t tmp, a = GPR (OP[0]), b = GPR (OP[1]); 907 trace_input ("andw", OP_REG, OP_REG, OP_VOID); 908 tmp = a & b; 909 SET_GPR (OP[1], tmp); 910 trace_output_16 (sd, tmp); 911 } 912 913 /* andd. */ 914 void 915 OP_4_C (SIM_DESC sd, SIM_CPU *cpu) 916 { 917 uint32_t tmp, a = OP[0], b = GPR32 (OP[1]); 918 trace_input ("andd", OP_CONSTANT32, OP_REGP, OP_VOID); 919 tmp = a & b; 920 SET_GPR32 (OP[1], tmp); 921 trace_output_32 (sd, tmp); 922 } 923 924 /* andd. */ 925 void 926 OP_14B_14 (SIM_DESC sd, SIM_CPU *cpu) 927 { 928 uint32_t tmp, a = (GPR32 (OP[0])), b = (GPR32 (OP[1])); 929 trace_input ("andd", OP_REGP, OP_REGP, OP_VOID); 930 tmp = a & b; 931 SET_GPR32 (OP[1], tmp); 932 trace_output_32 (sd, tmp); 933 } 934 935 /* ord. */ 936 void 937 OP_5_C (SIM_DESC sd, SIM_CPU *cpu) 938 { 939 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]); 940 trace_input ("ord", OP_CONSTANT32, OP_REG, OP_VOID); 941 tmp = a | b; 942 SET_GPR32 (OP[1], tmp); 943 trace_output_32 (sd, tmp); 944 } 945 946 /* ord. */ 947 void 948 OP_149_14 (SIM_DESC sd, SIM_CPU *cpu) 949 { 950 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); 951 trace_input ("ord", OP_REGP, OP_REGP, OP_VOID); 952 tmp = a | b; 953 SET_GPR32 (OP[1], tmp); 954 trace_output_32 (sd, tmp); 955 } 956 957 /* xord. */ 958 void 959 OP_6_C (SIM_DESC sd, SIM_CPU *cpu) 960 { 961 uint32_t tmp, a = (OP[0]), b = GPR32 (OP[1]); 962 trace_input ("xord", OP_CONSTANT32, OP_REG, OP_VOID); 963 tmp = a ^ b; 964 SET_GPR32 (OP[1], tmp); 965 trace_output_32 (sd, tmp); 966 } 967 968 /* xord. */ 969 void 970 OP_14A_14 (SIM_DESC sd, SIM_CPU *cpu) 971 { 972 uint32_t tmp, a = GPR32 (OP[0]), b = GPR32 (OP[1]); 973 trace_input ("xord", OP_REGP, OP_REGP, OP_VOID); 974 tmp = a ^ b; 975 SET_GPR32 (OP[1], tmp); 976 trace_output_32 (sd, tmp); 977 } 978 979 980 /* b. */ 981 void 982 OP_1_4 (SIM_DESC sd, SIM_CPU *cpu) 983 { 984 uint32_t tmp = 0, cc = cond_stat (OP[0]); 985 trace_input ("b", OP_CONSTANT4, OP_DISPE9, OP_VOID); 986 if (cc) 987 { 988 if (sign_flag) 989 tmp = (PC - (OP[1])); 990 else 991 tmp = (PC + (OP[1])); 992 /* If the resulting PC value is less than 0x00_0000 or greater 993 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 994 995 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 996 { 997 trace_output_void (sd); 998 EXCEPTION (SIM_SIGBUS); 999 } 1000 else 1001 JMP (tmp); 1002 } 1003 sign_flag = 0; /* Reset sign_flag. */ 1004 trace_output_32 (sd, tmp); 1005 } 1006 1007 /* b. */ 1008 void 1009 OP_18_8 (SIM_DESC sd, SIM_CPU *cpu) 1010 { 1011 uint32_t tmp = 0, cc = cond_stat (OP[0]); 1012 trace_input ("b", OP_CONSTANT4, OP_DISP17, OP_VOID); 1013 if (cc) 1014 { 1015 if (sign_flag) 1016 tmp = (PC - OP[1]); 1017 else 1018 tmp = (PC + OP[1]); 1019 /* If the resulting PC value is less than 0x00_0000 or greater 1020 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1021 1022 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1023 { 1024 trace_output_void (sd); 1025 EXCEPTION (SIM_SIGBUS); 1026 } 1027 else 1028 JMP (tmp); 1029 } 1030 sign_flag = 0; /* Reset sign_flag. */ 1031 trace_output_32 (sd, tmp); 1032 } 1033 1034 /* b. */ 1035 void 1036 OP_10_10 (SIM_DESC sd, SIM_CPU *cpu) 1037 { 1038 uint32_t tmp = 0, cc = cond_stat (OP[0]); 1039 trace_input ("b", OP_CONSTANT4, OP_DISP25, OP_VOID); 1040 if (cc) 1041 { 1042 if (sign_flag) 1043 tmp = (PC - (OP[1])); 1044 else 1045 tmp = (PC + (OP[1])); 1046 /* If the resulting PC value is less than 0x00_0000 or greater 1047 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1048 1049 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1050 { 1051 trace_output_void (sd); 1052 EXCEPTION (SIM_SIGBUS); 1053 } 1054 else 1055 JMP (tmp); 1056 } 1057 sign_flag = 0; /* Reset sign_flag. */ 1058 trace_output_32 (sd, tmp); 1059 } 1060 1061 /* bal. */ 1062 void 1063 OP_C0_8 (SIM_DESC sd, SIM_CPU *cpu) 1064 { 1065 uint32_t tmp; 1066 trace_input ("bal", OP_REG, OP_DISP17, OP_VOID); 1067 tmp = ((PC + 4) >> 1); /* Store PC in RA register. */ 1068 SET_GPR32 (14, tmp); 1069 if (sign_flag) 1070 tmp = (PC - (OP[1])); 1071 else 1072 tmp = (PC + (OP[1])); 1073 1074 /* If the resulting PC value is less than 0x00_0000 or greater 1075 than 0xFF_FFFF, this instruction causes an IAD trap. */ 1076 1077 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1078 { 1079 trace_output_void (sd); 1080 EXCEPTION (SIM_SIGBUS); 1081 } 1082 else 1083 JMP (tmp); 1084 sign_flag = 0; /* Reset sign_flag. */ 1085 trace_output_32 (sd, tmp); 1086 } 1087 1088 1089 /* bal. */ 1090 void 1091 OP_102_14 (SIM_DESC sd, SIM_CPU *cpu) 1092 { 1093 uint32_t tmp; 1094 trace_input ("bal", OP_REGP, OP_DISP25, OP_VOID); 1095 tmp = (((PC) + 4) >> 1); /* Store PC in reg pair. */ 1096 SET_GPR32 (OP[0], tmp); 1097 if (sign_flag) 1098 tmp = ((PC) - (OP[1])); 1099 else 1100 tmp = ((PC) + (OP[1])); 1101 /* If the resulting PC value is less than 0x00_0000 or greater 1102 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1103 1104 if ((tmp < 0x000000) || (tmp > 0xFFFFFF)) 1105 { 1106 trace_output_void (sd); 1107 EXCEPTION (SIM_SIGBUS); 1108 } 1109 else 1110 JMP (tmp); 1111 sign_flag = 0; /* Reset sign_flag. */ 1112 trace_output_32 (sd, tmp); 1113 } 1114 1115 /* jal. */ 1116 void 1117 OP_148_14 (SIM_DESC sd, SIM_CPU *cpu) 1118 { 1119 uint32_t tmp; 1120 trace_input ("jal", OP_REGP, OP_REGP, OP_VOID); 1121 SET_GPR32 (OP[0], (((PC) + 4) >> 1)); /* Store next PC in RA */ 1122 tmp = GPR32 (OP[1]); 1123 tmp = SEXT24(tmp << 1); 1124 /* If the resulting PC value is less than 0x00_0000 or greater 1125 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1126 1127 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 1128 { 1129 trace_output_void (sd); 1130 EXCEPTION (SIM_SIGBUS); 1131 } 1132 else 1133 JMP (tmp); 1134 1135 trace_output_32 (sd, tmp); 1136 } 1137 1138 1139 /* jal. */ 1140 void 1141 OP_D_C (SIM_DESC sd, SIM_CPU *cpu) 1142 { 1143 uint32_t tmp; 1144 trace_input ("jal", OP_REGP, OP_VOID, OP_VOID); 1145 SET_GPR32 (14, (((PC) + 2) >> 1)); /* Store next PC in RA */ 1146 tmp = GPR32 (OP[0]); 1147 tmp = SEXT24(tmp << 1); 1148 /* If the resulting PC value is less than 0x00_0000 or greater 1149 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 1150 1151 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 1152 { 1153 trace_output_void (sd); 1154 EXCEPTION (SIM_SIGBUS); 1155 } 1156 else 1157 JMP (tmp); 1158 1159 trace_output_32 (sd, tmp); 1160 } 1161 1162 1163 /* beq0b. */ 1164 void 1165 OP_C_8 (SIM_DESC sd, SIM_CPU *cpu) 1166 { 1167 uint32_t addr; 1168 uint8_t a = (GPR (OP[0]) & 0xFF); 1169 trace_input ("beq0b", OP_REG, OP_DISP5, OP_VOID); 1170 addr = OP[1]; 1171 if (a == 0) 1172 { 1173 if (sign_flag) 1174 addr = (PC - OP[1]); 1175 else 1176 addr = (PC + OP[1]); 1177 1178 JMP (addr); 1179 } 1180 sign_flag = 0; /* Reset sign_flag. */ 1181 trace_output_void (sd); 1182 } 1183 1184 /* bne0b. */ 1185 void 1186 OP_D_8 (SIM_DESC sd, SIM_CPU *cpu) 1187 { 1188 uint32_t addr; 1189 uint8_t a = (GPR (OP[0]) & 0xFF); 1190 trace_input ("bne0b", OP_REG, OP_DISP5, OP_VOID); 1191 addr = OP[1]; 1192 if (a != 0) 1193 { 1194 if (sign_flag) 1195 addr = (PC - OP[1]); 1196 else 1197 addr = (PC + OP[1]); 1198 1199 JMP (addr); 1200 } 1201 sign_flag = 0; /* Reset sign_flag. */ 1202 trace_output_void (sd); 1203 } 1204 1205 /* beq0w. */ 1206 void 1207 OP_E_8 (SIM_DESC sd, SIM_CPU *cpu) 1208 { 1209 uint32_t addr; 1210 uint16_t a = GPR (OP[0]); 1211 trace_input ("beq0w", OP_REG, OP_DISP5, OP_VOID); 1212 addr = OP[1]; 1213 if (a == 0) 1214 { 1215 if (sign_flag) 1216 addr = (PC - OP[1]); 1217 else 1218 addr = (PC + OP[1]); 1219 1220 JMP (addr); 1221 } 1222 sign_flag = 0; /* Reset sign_flag. */ 1223 trace_output_void (sd); 1224 } 1225 1226 /* bne0w. */ 1227 void 1228 OP_F_8 (SIM_DESC sd, SIM_CPU *cpu) 1229 { 1230 uint32_t addr; 1231 uint16_t a = GPR (OP[0]); 1232 trace_input ("bne0w", OP_REG, OP_DISP5, OP_VOID); 1233 addr = OP[1]; 1234 if (a != 0) 1235 { 1236 if (sign_flag) 1237 addr = (PC - OP[1]); 1238 else 1239 addr = (PC + OP[1]); 1240 1241 JMP (addr); 1242 } 1243 sign_flag = 0; /* Reset sign_flag. */ 1244 trace_output_void (sd); 1245 } 1246 1247 1248 /* jeq. */ 1249 void 1250 OP_A0_C (SIM_DESC sd, SIM_CPU *cpu) 1251 { 1252 uint32_t tmp = 0; 1253 trace_input ("jeq", OP_REGP, OP_VOID, OP_VOID); 1254 if ((PSR_Z) == 1) 1255 { 1256 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ 1257 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ 1258 } 1259 trace_output_32 (sd, tmp); 1260 } 1261 1262 /* jne. */ 1263 void 1264 OP_A1_C (SIM_DESC sd, SIM_CPU *cpu) 1265 { 1266 uint32_t tmp = 0; 1267 trace_input ("jne", OP_REGP, OP_VOID, OP_VOID); 1268 if ((PSR_Z) == 0) 1269 { 1270 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits. */ 1271 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit. */ 1272 } 1273 trace_output_32 (sd, tmp); 1274 } 1275 1276 /* jcs. */ 1277 void 1278 OP_A2_C (SIM_DESC sd, SIM_CPU *cpu) 1279 { 1280 uint32_t tmp = 0; 1281 trace_input ("jcs", OP_REGP, OP_VOID, OP_VOID); 1282 if ((PSR_C) == 1) 1283 { 1284 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1285 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1286 } 1287 trace_output_32 (sd, tmp); 1288 } 1289 1290 /* jcc. */ 1291 void 1292 OP_A3_C (SIM_DESC sd, SIM_CPU *cpu) 1293 { 1294 uint32_t tmp = 0; 1295 trace_input ("jcc", OP_REGP, OP_VOID, OP_VOID); 1296 if ((PSR_C) == 0) 1297 { 1298 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1299 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1300 } 1301 trace_output_32 (sd, tmp); 1302 } 1303 1304 /* jhi. */ 1305 void 1306 OP_A4_C (SIM_DESC sd, SIM_CPU *cpu) 1307 { 1308 uint32_t tmp = 0; 1309 trace_input ("jhi", OP_REGP, OP_VOID, OP_VOID); 1310 if ((PSR_L) == 1) 1311 { 1312 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1313 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1314 } 1315 trace_output_32 (sd, tmp); 1316 } 1317 1318 /* jls. */ 1319 void 1320 OP_A5_C (SIM_DESC sd, SIM_CPU *cpu) 1321 { 1322 uint32_t tmp = 0; 1323 trace_input ("jls", OP_REGP, OP_VOID, OP_VOID); 1324 if ((PSR_L) == 0) 1325 { 1326 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1327 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1328 } 1329 trace_output_32 (sd, tmp); 1330 } 1331 1332 /* jgt. */ 1333 void 1334 OP_A6_C (SIM_DESC sd, SIM_CPU *cpu) 1335 { 1336 uint32_t tmp = 0; 1337 trace_input ("jgt", OP_REGP, OP_VOID, OP_VOID); 1338 if ((PSR_N) == 1) 1339 { 1340 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1341 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1342 } 1343 trace_output_32 (sd, tmp); 1344 } 1345 1346 /* jle. */ 1347 void 1348 OP_A7_C (SIM_DESC sd, SIM_CPU *cpu) 1349 { 1350 uint32_t tmp = 0; 1351 trace_input ("jle", OP_REGP, OP_VOID, OP_VOID); 1352 if ((PSR_N) == 0) 1353 { 1354 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1355 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1356 } 1357 trace_output_32 (sd, tmp); 1358 } 1359 1360 1361 /* jfs. */ 1362 void 1363 OP_A8_C (SIM_DESC sd, SIM_CPU *cpu) 1364 { 1365 uint32_t tmp = 0; 1366 trace_input ("jfs", OP_REGP, OP_VOID, OP_VOID); 1367 if ((PSR_F) == 1) 1368 { 1369 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1370 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1371 } 1372 trace_output_32 (sd, tmp); 1373 } 1374 1375 /* jfc. */ 1376 void 1377 OP_A9_C (SIM_DESC sd, SIM_CPU *cpu) 1378 { 1379 uint32_t tmp = 0; 1380 trace_input ("jfc", OP_REGP, OP_VOID, OP_VOID); 1381 if ((PSR_F) == 0) 1382 { 1383 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1384 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1385 } 1386 trace_output_32 (sd, tmp); 1387 } 1388 1389 /* jlo. */ 1390 void 1391 OP_AA_C (SIM_DESC sd, SIM_CPU *cpu) 1392 { 1393 uint32_t tmp = 0; 1394 trace_input ("jlo", OP_REGP, OP_VOID, OP_VOID); 1395 if (((PSR_Z) == 0) & ((PSR_L) == 0)) 1396 { 1397 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1398 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1399 } 1400 trace_output_32 (sd, tmp); 1401 } 1402 1403 /* jhs. */ 1404 void 1405 OP_AB_C (SIM_DESC sd, SIM_CPU *cpu) 1406 { 1407 uint32_t tmp = 0; 1408 trace_input ("jhs", OP_REGP, OP_VOID, OP_VOID); 1409 if (((PSR_Z) == 1) | ((PSR_L) == 1)) 1410 { 1411 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1412 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1413 } 1414 trace_output_32 (sd, tmp); 1415 } 1416 1417 /* jlt. */ 1418 void 1419 OP_AC_C (SIM_DESC sd, SIM_CPU *cpu) 1420 { 1421 uint32_t tmp = 0; 1422 trace_input ("jlt", OP_REGP, OP_VOID, OP_VOID); 1423 if (((PSR_Z) == 0) & ((PSR_N) == 0)) 1424 { 1425 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1426 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1427 } 1428 trace_output_32 (sd, tmp); 1429 } 1430 1431 /* jge. */ 1432 void 1433 OP_AD_C (SIM_DESC sd, SIM_CPU *cpu) 1434 { 1435 uint32_t tmp = 0; 1436 trace_input ("jge", OP_REGP, OP_VOID, OP_VOID); 1437 if (((PSR_Z) == 1) | ((PSR_N) == 1)) 1438 { 1439 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1440 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1441 } 1442 trace_output_32 (sd, tmp); 1443 } 1444 1445 /* jump. */ 1446 void 1447 OP_AE_C (SIM_DESC sd, SIM_CPU *cpu) 1448 { 1449 uint32_t tmp; 1450 trace_input ("jump", OP_REGP, OP_VOID, OP_VOID); 1451 tmp = GPR32 (OP[0]) /*& 0x3fffff*/; /* Use only 0 - 22 bits */ 1452 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1453 trace_output_32 (sd, tmp); 1454 } 1455 1456 /* jusr. */ 1457 void 1458 OP_AF_C (SIM_DESC sd, SIM_CPU *cpu) 1459 { 1460 uint32_t tmp; 1461 trace_input ("jusr", OP_REGP, OP_VOID, OP_VOID); 1462 tmp = (GPR32 (OP[0])) & 0x3fffff; /* Use only 0 - 22 bits */ 1463 JMP (tmp << 1); /* Set PC's 1 - 23 bits and clear 0th bit*/ 1464 SET_PSR_U(1); 1465 trace_output_32 (sd, tmp); 1466 } 1467 1468 /* seq. */ 1469 void 1470 OP_80_C (SIM_DESC sd, SIM_CPU *cpu) 1471 { 1472 trace_input ("seq", OP_REG, OP_VOID, OP_VOID); 1473 if ((PSR_Z) == 1) 1474 SET_GPR (OP[0], 1); 1475 else 1476 SET_GPR (OP[0], 0); 1477 trace_output_void (sd); 1478 } 1479 /* sne. */ 1480 void 1481 OP_81_C (SIM_DESC sd, SIM_CPU *cpu) 1482 { 1483 trace_input ("sne", OP_REG, OP_VOID, OP_VOID); 1484 if ((PSR_Z) == 0) 1485 SET_GPR (OP[0], 1); 1486 else 1487 SET_GPR (OP[0], 0); 1488 trace_output_void (sd); 1489 } 1490 1491 /* scs. */ 1492 void 1493 OP_82_C (SIM_DESC sd, SIM_CPU *cpu) 1494 { 1495 trace_input ("scs", OP_REG, OP_VOID, OP_VOID); 1496 if ((PSR_C) == 1) 1497 SET_GPR (OP[0], 1); 1498 else 1499 SET_GPR (OP[0], 0); 1500 trace_output_void (sd); 1501 } 1502 1503 /* scc. */ 1504 void 1505 OP_83_C (SIM_DESC sd, SIM_CPU *cpu) 1506 { 1507 trace_input ("scc", OP_REG, OP_VOID, OP_VOID); 1508 if ((PSR_C) == 0) 1509 SET_GPR (OP[0], 1); 1510 else 1511 SET_GPR (OP[0], 0); 1512 trace_output_void (sd); 1513 } 1514 1515 /* shi. */ 1516 void 1517 OP_84_C (SIM_DESC sd, SIM_CPU *cpu) 1518 { 1519 trace_input ("shi", OP_REG, OP_VOID, OP_VOID); 1520 if ((PSR_L) == 1) 1521 SET_GPR (OP[0], 1); 1522 else 1523 SET_GPR (OP[0], 0); 1524 trace_output_void (sd); 1525 } 1526 1527 /* sls. */ 1528 void 1529 OP_85_C (SIM_DESC sd, SIM_CPU *cpu) 1530 { 1531 trace_input ("sls", OP_REG, OP_VOID, OP_VOID); 1532 if ((PSR_L) == 0) 1533 SET_GPR (OP[0], 1); 1534 else 1535 SET_GPR (OP[0], 0); 1536 trace_output_void (sd); 1537 } 1538 1539 /* sgt. */ 1540 void 1541 OP_86_C (SIM_DESC sd, SIM_CPU *cpu) 1542 { 1543 trace_input ("sgt", OP_REG, OP_VOID, OP_VOID); 1544 if ((PSR_N) == 1) 1545 SET_GPR (OP[0], 1); 1546 else 1547 SET_GPR (OP[0], 0); 1548 trace_output_void (sd); 1549 } 1550 1551 /* sle. */ 1552 void 1553 OP_87_C (SIM_DESC sd, SIM_CPU *cpu) 1554 { 1555 trace_input ("sle", OP_REG, OP_VOID, OP_VOID); 1556 if ((PSR_N) == 0) 1557 SET_GPR (OP[0], 1); 1558 else 1559 SET_GPR (OP[0], 0); 1560 trace_output_void (sd); 1561 } 1562 1563 /* sfs. */ 1564 void 1565 OP_88_C (SIM_DESC sd, SIM_CPU *cpu) 1566 { 1567 trace_input ("sfs", OP_REG, OP_VOID, OP_VOID); 1568 if ((PSR_F) == 1) 1569 SET_GPR (OP[0], 1); 1570 else 1571 SET_GPR (OP[0], 0); 1572 trace_output_void (sd); 1573 } 1574 1575 /* sfc. */ 1576 void 1577 OP_89_C (SIM_DESC sd, SIM_CPU *cpu) 1578 { 1579 trace_input ("sfc", OP_REG, OP_VOID, OP_VOID); 1580 if ((PSR_F) == 0) 1581 SET_GPR (OP[0], 1); 1582 else 1583 SET_GPR (OP[0], 0); 1584 trace_output_void (sd); 1585 } 1586 1587 1588 /* slo. */ 1589 void 1590 OP_8A_C (SIM_DESC sd, SIM_CPU *cpu) 1591 { 1592 trace_input ("slo", OP_REG, OP_VOID, OP_VOID); 1593 if (((PSR_Z) == 0) & ((PSR_L) == 0)) 1594 SET_GPR (OP[0], 1); 1595 else 1596 SET_GPR (OP[0], 0); 1597 trace_output_void (sd); 1598 } 1599 1600 /* shs. */ 1601 void 1602 OP_8B_C (SIM_DESC sd, SIM_CPU *cpu) 1603 { 1604 trace_input ("shs", OP_REG, OP_VOID, OP_VOID); 1605 if ( ((PSR_Z) == 1) | ((PSR_L) == 1)) 1606 SET_GPR (OP[0], 1); 1607 else 1608 SET_GPR (OP[0], 0); 1609 trace_output_void (sd); 1610 } 1611 1612 /* slt. */ 1613 void 1614 OP_8C_C (SIM_DESC sd, SIM_CPU *cpu) 1615 { 1616 trace_input ("slt", OP_REG, OP_VOID, OP_VOID); 1617 if (((PSR_Z) == 0) & ((PSR_N) == 0)) 1618 SET_GPR (OP[0], 1); 1619 else 1620 SET_GPR (OP[0], 0); 1621 trace_output_void (sd); 1622 } 1623 1624 /* sge. */ 1625 void 1626 OP_8D_C (SIM_DESC sd, SIM_CPU *cpu) 1627 { 1628 trace_input ("sge", OP_REG, OP_VOID, OP_VOID); 1629 if (((PSR_Z) == 1) | ((PSR_N) == 1)) 1630 SET_GPR (OP[0], 1); 1631 else 1632 SET_GPR (OP[0], 0); 1633 trace_output_void (sd); 1634 } 1635 1636 /* cbitb. */ 1637 void 1638 OP_D7_9 (SIM_DESC sd, SIM_CPU *cpu) 1639 { 1640 uint8_t a = OP[0] & 0xff; 1641 uint32_t addr = OP[1], tmp; 1642 trace_input ("cbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1643 tmp = RB (addr); 1644 SET_PSR_F (tmp & (1 << a)); 1645 tmp = tmp & ~(1 << a); 1646 SB (addr, tmp); 1647 trace_output_32 (sd, tmp); 1648 } 1649 1650 /* cbitb. */ 1651 void 1652 OP_107_14 (SIM_DESC sd, SIM_CPU *cpu) 1653 { 1654 uint8_t a = OP[0] & 0xff; 1655 uint32_t addr = OP[1], tmp; 1656 trace_input ("cbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1657 tmp = RB (addr); 1658 SET_PSR_F (tmp & (1 << a)); 1659 tmp = tmp & ~(1 << a); 1660 SB (addr, tmp); 1661 trace_output_32 (sd, tmp); 1662 } 1663 1664 /* cbitb. */ 1665 void 1666 OP_68_8 (SIM_DESC sd, SIM_CPU *cpu) 1667 { 1668 uint8_t a = (OP[0]) & 0xff; 1669 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 1670 trace_input ("cbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 1671 tmp = RB (addr); 1672 SET_PSR_F (tmp & (1 << a)); 1673 tmp = tmp & ~(1 << a); 1674 SB (addr, tmp); 1675 trace_output_32 (sd, addr); 1676 } 1677 1678 /* cbitb. */ 1679 void 1680 OP_1AA_A (SIM_DESC sd, SIM_CPU *cpu) 1681 { 1682 uint8_t a = (OP[0]) & 0xff; 1683 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1684 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1685 tmp = RB (addr); 1686 SET_PSR_F (tmp & (1 << a)); 1687 tmp = tmp & ~(1 << a); 1688 SB (addr, tmp); 1689 trace_output_32 (sd, addr); 1690 } 1691 1692 /* cbitb. */ 1693 void 1694 OP_104_14 (SIM_DESC sd, SIM_CPU *cpu) 1695 { 1696 uint8_t a = (OP[0]) & 0xff; 1697 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 1698 trace_input ("cbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1699 tmp = RB (addr); 1700 SET_PSR_F (tmp & (1 << a)); 1701 tmp = tmp & ~(1 << a); 1702 SB (addr, tmp); 1703 trace_output_32 (sd, addr); 1704 } 1705 1706 /* cbitb. */ 1707 void 1708 OP_D4_9 (SIM_DESC sd, SIM_CPU *cpu) 1709 { 1710 uint8_t a = (OP[0]) & 0xff; 1711 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1712 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1713 tmp = RB (addr); 1714 SET_PSR_F (tmp & (1 << a)); 1715 tmp = tmp & ~(1 << a); 1716 SB (addr, tmp); 1717 trace_output_32 (sd, addr); 1718 } 1719 1720 /* cbitb. */ 1721 void 1722 OP_D6_9 (SIM_DESC sd, SIM_CPU *cpu) 1723 { 1724 uint8_t a = (OP[0]) & 0xff; 1725 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1726 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1727 tmp = RB (addr); 1728 SET_PSR_F (tmp & (1 << a)); 1729 tmp = tmp & ~(1 << a); 1730 SB (addr, tmp); 1731 trace_output_32 (sd, addr); 1732 1733 } 1734 1735 /* cbitb. */ 1736 void 1737 OP_105_14 (SIM_DESC sd, SIM_CPU *cpu) 1738 { 1739 uint8_t a = (OP[0]) & 0xff; 1740 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1741 trace_input ("cbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 1742 tmp = RB (addr); 1743 SET_PSR_F (tmp & (1 << a)); 1744 tmp = tmp & ~(1 << a); 1745 SB (addr, tmp); 1746 trace_output_32 (sd, addr); 1747 } 1748 1749 /* cbitb. */ 1750 void 1751 OP_106_14 (SIM_DESC sd, SIM_CPU *cpu) 1752 { 1753 uint8_t a = (OP[0]) & 0xff; 1754 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1755 trace_input ("cbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 1756 tmp = RB (addr); 1757 SET_PSR_F (tmp & (1 << a)); 1758 tmp = tmp & ~(1 << a); 1759 SB (addr, tmp); 1760 trace_output_32 (sd, addr); 1761 } 1762 1763 1764 /* cbitw. */ 1765 void 1766 OP_6F_8 (SIM_DESC sd, SIM_CPU *cpu) 1767 { 1768 uint16_t a = OP[0]; 1769 uint32_t addr = OP[1], tmp; 1770 trace_input ("cbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1771 tmp = RW (addr); 1772 SET_PSR_F (tmp & (1 << a)); 1773 tmp = tmp & ~(1 << a); 1774 SW (addr, tmp); 1775 trace_output_32 (sd, tmp); 1776 } 1777 1778 /* cbitw. */ 1779 void 1780 OP_117_14 (SIM_DESC sd, SIM_CPU *cpu) 1781 { 1782 uint16_t a = OP[0]; 1783 uint32_t addr = OP[1], tmp; 1784 trace_input ("cbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1785 tmp = RW (addr); 1786 SET_PSR_F (tmp & (1 << a)); 1787 tmp = tmp & ~(1 << a); 1788 SW (addr, tmp); 1789 trace_output_32 (sd, tmp); 1790 } 1791 1792 /* cbitw. */ 1793 void 1794 OP_36_7 (SIM_DESC sd, SIM_CPU *cpu) 1795 { 1796 uint32_t addr; 1797 uint16_t a = (OP[0]), tmp; 1798 trace_input ("cbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 1799 1800 if (OP[1] == 0) 1801 addr = (GPR32 (12)) + OP[2]; 1802 else 1803 addr = (GPR32 (13)) + OP[2]; 1804 1805 tmp = RW (addr); 1806 SET_PSR_F (tmp & (1 << a)); 1807 tmp = tmp & ~(1 << a); 1808 SW (addr, tmp); 1809 trace_output_32 (sd, addr); 1810 1811 } 1812 1813 /* cbitw. */ 1814 void 1815 OP_1AB_A (SIM_DESC sd, SIM_CPU *cpu) 1816 { 1817 uint16_t a = (OP[0]); 1818 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1819 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1820 tmp = RW (addr); 1821 SET_PSR_F (tmp & (1 << a)); 1822 tmp = tmp & ~(1 << a); 1823 SW (addr, tmp); 1824 trace_output_32 (sd, addr); 1825 } 1826 1827 /* cbitw. */ 1828 void 1829 OP_114_14 (SIM_DESC sd, SIM_CPU *cpu) 1830 { 1831 uint16_t a = (OP[0]); 1832 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 1833 trace_input ("cbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1834 tmp = RW (addr); 1835 SET_PSR_F (tmp & (1 << a)); 1836 tmp = tmp & ~(1 << a); 1837 SW (addr, tmp); 1838 trace_output_32 (sd, addr); 1839 } 1840 1841 1842 /* cbitw. */ 1843 void 1844 OP_6E_8 (SIM_DESC sd, SIM_CPU *cpu) 1845 { 1846 uint16_t a = (OP[0]); 1847 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1848 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1849 tmp = RW (addr); 1850 SET_PSR_F (tmp & (1 << a)); 1851 tmp = tmp & ~(1 << a); 1852 SW (addr, tmp); 1853 trace_output_32 (sd, addr); 1854 } 1855 1856 /* cbitw. */ 1857 void 1858 OP_69_8 (SIM_DESC sd, SIM_CPU *cpu) 1859 { 1860 uint16_t a = (OP[0]); 1861 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1862 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1863 tmp = RW (addr); 1864 SET_PSR_F (tmp & (1 << a)); 1865 tmp = tmp & ~(1 << a); 1866 SW (addr, tmp); 1867 trace_output_32 (sd, addr); 1868 } 1869 1870 1871 /* cbitw. */ 1872 void 1873 OP_115_14 (SIM_DESC sd, SIM_CPU *cpu) 1874 { 1875 uint16_t a = (OP[0]); 1876 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1877 trace_input ("cbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 1878 tmp = RW (addr); 1879 SET_PSR_F (tmp & (1 << a)); 1880 tmp = tmp & ~(1 << a); 1881 SW (addr, tmp); 1882 trace_output_32 (sd, addr); 1883 } 1884 1885 /* cbitw. */ 1886 void 1887 OP_116_14 (SIM_DESC sd, SIM_CPU *cpu) 1888 { 1889 uint16_t a = (OP[0]); 1890 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1891 trace_input ("cbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 1892 tmp = RW (addr); 1893 SET_PSR_F (tmp & (1 << a)); 1894 tmp = tmp & ~(1 << a); 1895 SW (addr, tmp); 1896 trace_output_32 (sd, addr); 1897 } 1898 1899 /* sbitb. */ 1900 void 1901 OP_E7_9 (SIM_DESC sd, SIM_CPU *cpu) 1902 { 1903 uint8_t a = OP[0] & 0xff; 1904 uint32_t addr = OP[1], tmp; 1905 trace_input ("sbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 1906 tmp = RB (addr); 1907 SET_PSR_F (tmp & (1 << a)); 1908 tmp = tmp | (1 << a); 1909 SB (addr, tmp); 1910 trace_output_32 (sd, tmp); 1911 } 1912 1913 /* sbitb. */ 1914 void 1915 OP_10B_14 (SIM_DESC sd, SIM_CPU *cpu) 1916 { 1917 uint8_t a = OP[0] & 0xff; 1918 uint32_t addr = OP[1], tmp; 1919 trace_input ("sbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 1920 tmp = RB (addr); 1921 SET_PSR_F (tmp & (1 << a)); 1922 tmp = tmp | (1 << a); 1923 SB (addr, tmp); 1924 trace_output_32 (sd, tmp); 1925 } 1926 1927 /* sbitb. */ 1928 void 1929 OP_70_8 (SIM_DESC sd, SIM_CPU *cpu) 1930 { 1931 uint8_t a = OP[0] & 0xff; 1932 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 1933 trace_input ("sbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 1934 tmp = RB (addr); 1935 SET_PSR_F (tmp & (1 << a)); 1936 tmp = tmp | (1 << a); 1937 SB (addr, tmp); 1938 trace_output_32 (sd, tmp); 1939 } 1940 1941 /* sbitb. */ 1942 void 1943 OP_1CA_A (SIM_DESC sd, SIM_CPU *cpu) 1944 { 1945 uint8_t a = OP[0] & 0xff; 1946 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1947 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 1948 tmp = RB (addr); 1949 SET_PSR_F (tmp & (1 << a)); 1950 tmp = tmp | (1 << a); 1951 SB (addr, tmp); 1952 trace_output_32 (sd, tmp); 1953 } 1954 1955 /* sbitb. */ 1956 void 1957 OP_108_14 (SIM_DESC sd, SIM_CPU *cpu) 1958 { 1959 uint8_t a = OP[0] & 0xff; 1960 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 1961 trace_input ("sbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 1962 tmp = RB (addr); 1963 SET_PSR_F (tmp & (1 << a)); 1964 tmp = tmp | (1 << a); 1965 SB (addr, tmp); 1966 trace_output_32 (sd, tmp); 1967 } 1968 1969 1970 /* sbitb. */ 1971 void 1972 OP_E4_9 (SIM_DESC sd, SIM_CPU *cpu) 1973 { 1974 uint8_t a = OP[0] & 0xff; 1975 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1976 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 1977 tmp = RB (addr); 1978 SET_PSR_F (tmp & (1 << a)); 1979 tmp = tmp | (1 << a); 1980 SB (addr, tmp); 1981 trace_output_32 (sd, tmp); 1982 } 1983 1984 /* sbitb. */ 1985 void 1986 OP_E6_9 (SIM_DESC sd, SIM_CPU *cpu) 1987 { 1988 uint8_t a = OP[0] & 0xff; 1989 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 1990 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 1991 tmp = RB (addr); 1992 SET_PSR_F (tmp & (1 << a)); 1993 tmp = tmp | (1 << a); 1994 SB (addr, tmp); 1995 trace_output_32 (sd, tmp); 1996 } 1997 1998 1999 /* sbitb. */ 2000 void 2001 OP_109_14 (SIM_DESC sd, SIM_CPU *cpu) 2002 { 2003 uint8_t a = OP[0] & 0xff; 2004 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2005 trace_input ("sbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2006 tmp = RB (addr); 2007 SET_PSR_F (tmp & (1 << a)); 2008 tmp = tmp | (1 << a); 2009 SB (addr, tmp); 2010 trace_output_32 (sd, tmp); 2011 } 2012 2013 2014 /* sbitb. */ 2015 void 2016 OP_10A_14 (SIM_DESC sd, SIM_CPU *cpu) 2017 { 2018 uint8_t a = OP[0] & 0xff; 2019 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2020 trace_input ("sbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2021 tmp = RB (addr); 2022 SET_PSR_F (tmp & (1 << a)); 2023 tmp = tmp | (1 << a); 2024 SB (addr, tmp); 2025 trace_output_32 (sd, tmp); 2026 } 2027 2028 2029 /* sbitw. */ 2030 void 2031 OP_77_8 (SIM_DESC sd, SIM_CPU *cpu) 2032 { 2033 uint16_t a = OP[0]; 2034 uint32_t addr = OP[1], tmp; 2035 trace_input ("sbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2036 tmp = RW (addr); 2037 SET_PSR_F (tmp & (1 << a)); 2038 tmp = tmp | (1 << a); 2039 SW (addr, tmp); 2040 trace_output_32 (sd, tmp); 2041 } 2042 2043 /* sbitw. */ 2044 void 2045 OP_11B_14 (SIM_DESC sd, SIM_CPU *cpu) 2046 { 2047 uint16_t a = OP[0]; 2048 uint32_t addr = OP[1], tmp; 2049 trace_input ("sbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2050 tmp = RW (addr); 2051 SET_PSR_F (tmp & (1 << a)); 2052 tmp = tmp | (1 << a); 2053 SW (addr, tmp); 2054 trace_output_32 (sd, tmp); 2055 } 2056 2057 /* sbitw. */ 2058 void 2059 OP_3A_7 (SIM_DESC sd, SIM_CPU *cpu) 2060 { 2061 uint32_t addr; 2062 uint16_t a = (OP[0]), tmp; 2063 trace_input ("sbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 2064 2065 if (OP[1] == 0) 2066 addr = (GPR32 (12)) + OP[2]; 2067 else 2068 addr = (GPR32 (13)) + OP[2]; 2069 2070 tmp = RW (addr); 2071 SET_PSR_F (tmp & (1 << a)); 2072 tmp = tmp | (1 << a); 2073 SW (addr, tmp); 2074 trace_output_32 (sd, addr); 2075 } 2076 2077 /* sbitw. */ 2078 void 2079 OP_1CB_A (SIM_DESC sd, SIM_CPU *cpu) 2080 { 2081 uint16_t a = (OP[0]); 2082 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2083 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2084 tmp = RW (addr); 2085 SET_PSR_F (tmp & (1 << a)); 2086 tmp = tmp | (1 << a); 2087 SW (addr, tmp); 2088 trace_output_32 (sd, addr); 2089 } 2090 2091 /* sbitw. */ 2092 void 2093 OP_118_14 (SIM_DESC sd, SIM_CPU *cpu) 2094 { 2095 uint16_t a = (OP[0]); 2096 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 2097 trace_input ("sbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2098 tmp = RW (addr); 2099 SET_PSR_F (tmp & (1 << a)); 2100 tmp = tmp | (1 << a); 2101 SW (addr, tmp); 2102 trace_output_32 (sd, addr); 2103 } 2104 2105 /* sbitw. */ 2106 void 2107 OP_76_8 (SIM_DESC sd, SIM_CPU *cpu) 2108 { 2109 uint16_t a = (OP[0]); 2110 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2111 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2112 tmp = RW (addr); 2113 SET_PSR_F (tmp & (1 << a)); 2114 tmp = tmp | (1 << a); 2115 SW (addr, tmp); 2116 trace_output_32 (sd, addr); 2117 } 2118 2119 /* sbitw. */ 2120 void 2121 OP_71_8 (SIM_DESC sd, SIM_CPU *cpu) 2122 { 2123 uint16_t a = (OP[0]); 2124 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2125 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2126 tmp = RW (addr); 2127 SET_PSR_F (tmp & (1 << a)); 2128 tmp = tmp | (1 << a); 2129 SW (addr, tmp); 2130 trace_output_32 (sd, addr); 2131 } 2132 2133 /* sbitw. */ 2134 void 2135 OP_119_14 (SIM_DESC sd, SIM_CPU *cpu) 2136 { 2137 uint16_t a = (OP[0]); 2138 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2139 trace_input ("sbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2140 tmp = RW (addr); 2141 SET_PSR_F (tmp & (1 << a)); 2142 tmp = tmp | (1 << a); 2143 SW (addr, tmp); 2144 trace_output_32 (sd, addr); 2145 } 2146 2147 /* sbitw. */ 2148 void 2149 OP_11A_14 (SIM_DESC sd, SIM_CPU *cpu) 2150 { 2151 uint16_t a = (OP[0]); 2152 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2153 trace_input ("sbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2154 tmp = RW (addr); 2155 SET_PSR_F (tmp & (1 << a)); 2156 tmp = tmp | (1 << a); 2157 SW (addr, tmp); 2158 trace_output_32 (sd, addr); 2159 } 2160 2161 2162 /* tbitb. */ 2163 void 2164 OP_F7_9 (SIM_DESC sd, SIM_CPU *cpu) 2165 { 2166 uint8_t a = OP[0] & 0xff; 2167 uint32_t addr = OP[1], tmp; 2168 trace_input ("tbitb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2169 tmp = RB (addr); 2170 SET_PSR_F (tmp & (1 << a)); 2171 trace_output_32 (sd, tmp); 2172 } 2173 2174 /* tbitb. */ 2175 void 2176 OP_10F_14 (SIM_DESC sd, SIM_CPU *cpu) 2177 { 2178 uint8_t a = OP[0] & 0xff; 2179 uint32_t addr = OP[1], tmp; 2180 trace_input ("tbitb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2181 tmp = RB (addr); 2182 SET_PSR_F (tmp & (1 << a)); 2183 trace_output_32 (sd, tmp); 2184 } 2185 2186 /* tbitb. */ 2187 void 2188 OP_78_8 (SIM_DESC sd, SIM_CPU *cpu) 2189 { 2190 uint8_t a = (OP[0]) & 0xff; 2191 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 2192 trace_input ("tbitb", OP_CONSTANT4, OP_R_INDEX7_ABS20, OP_VOID); 2193 tmp = RB (addr); 2194 SET_PSR_F (tmp & (1 << a)); 2195 trace_output_32 (sd, addr); 2196 } 2197 2198 /* tbitb. */ 2199 void 2200 OP_1EA_A (SIM_DESC sd, SIM_CPU *cpu) 2201 { 2202 uint8_t a = (OP[0]) & 0xff; 2203 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2204 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2205 tmp = RB (addr); 2206 SET_PSR_F (tmp & (1 << a)); 2207 trace_output_32 (sd, addr); 2208 } 2209 2210 /* tbitb. */ 2211 void 2212 OP_10C_14 (SIM_DESC sd, SIM_CPU *cpu) 2213 { 2214 uint8_t a = (OP[0]) & 0xff; 2215 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 2216 trace_input ("tbitb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2217 tmp = RB (addr); 2218 SET_PSR_F (tmp & (1 << a)); 2219 trace_output_32 (sd, addr); 2220 } 2221 2222 /* tbitb. */ 2223 void 2224 OP_F4_9 (SIM_DESC sd, SIM_CPU *cpu) 2225 { 2226 uint8_t a = (OP[0]) & 0xff; 2227 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2228 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2229 tmp = RB (addr); 2230 SET_PSR_F (tmp & (1 << a)); 2231 trace_output_32 (sd, addr); 2232 } 2233 2234 /* tbitb. */ 2235 void 2236 OP_F6_9 (SIM_DESC sd, SIM_CPU *cpu) 2237 { 2238 uint8_t a = (OP[0]) & 0xff; 2239 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2240 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2241 tmp = RB (addr); 2242 SET_PSR_F (tmp & (1 << a)); 2243 trace_output_32 (sd, addr); 2244 } 2245 2246 /* tbitb. */ 2247 void 2248 OP_10D_14 (SIM_DESC sd, SIM_CPU *cpu) 2249 { 2250 uint8_t a = (OP[0]) & 0xff; 2251 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2252 trace_input ("tbitb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2253 tmp = RB (addr); 2254 SET_PSR_F (tmp & (1 << a)); 2255 trace_output_32 (sd, addr); 2256 } 2257 2258 /* tbitb. */ 2259 void 2260 OP_10E_14 (SIM_DESC sd, SIM_CPU *cpu) 2261 { 2262 uint8_t a = (OP[0]) & 0xff; 2263 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2264 trace_input ("tbitb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2265 tmp = RB (addr); 2266 SET_PSR_F (tmp & (1 << a)); 2267 trace_output_32 (sd, addr); 2268 } 2269 2270 2271 /* tbitw. */ 2272 void 2273 OP_7F_8 (SIM_DESC sd, SIM_CPU *cpu) 2274 { 2275 uint16_t a = OP[0]; 2276 uint32_t addr = OP[1], tmp; 2277 trace_input ("tbitw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 2278 tmp = RW (addr); 2279 SET_PSR_F (tmp & (1 << a)); 2280 trace_output_32 (sd, tmp); 2281 } 2282 2283 /* tbitw. */ 2284 void 2285 OP_11F_14 (SIM_DESC sd, SIM_CPU *cpu) 2286 { 2287 uint16_t a = OP[0]; 2288 uint32_t addr = OP[1], tmp; 2289 trace_input ("tbitw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 2290 tmp = RW (addr); 2291 SET_PSR_F (tmp & (1 << a)); 2292 trace_output_32 (sd, tmp); 2293 } 2294 2295 2296 /* tbitw. */ 2297 void 2298 OP_3E_7 (SIM_DESC sd, SIM_CPU *cpu) 2299 { 2300 uint32_t addr; 2301 uint16_t a = (OP[0]), tmp; 2302 trace_input ("tbitw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 2303 2304 if (OP[1] == 0) 2305 addr = (GPR32 (12)) + OP[2]; 2306 else 2307 addr = (GPR32 (13)) + OP[2]; 2308 2309 tmp = RW (addr); 2310 SET_PSR_F (tmp & (1 << a)); 2311 trace_output_32 (sd, addr); 2312 } 2313 2314 /* tbitw. */ 2315 void 2316 OP_1EB_A (SIM_DESC sd, SIM_CPU *cpu) 2317 { 2318 uint16_t a = (OP[0]); 2319 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2320 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP14, OP_VOID); 2321 tmp = RW (addr); 2322 SET_PSR_F (tmp & (1 << a)); 2323 trace_output_32 (sd, addr); 2324 } 2325 2326 /* tbitw. */ 2327 void 2328 OP_11C_14 (SIM_DESC sd, SIM_CPU *cpu) 2329 { 2330 uint16_t a = (OP[0]); 2331 uint32_t addr = (GPR (OP[2])) + OP[1], tmp; 2332 trace_input ("tbitw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 2333 tmp = RW (addr); 2334 SET_PSR_F (tmp & (1 << a)); 2335 trace_output_32 (sd, addr); 2336 } 2337 2338 /* tbitw. */ 2339 void 2340 OP_7E_8 (SIM_DESC sd, SIM_CPU *cpu) 2341 { 2342 uint16_t a = (OP[0]); 2343 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2344 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 2345 tmp = RW (addr); 2346 SET_PSR_F (tmp & (1 << a)); 2347 trace_output_32 (sd, addr); 2348 } 2349 2350 /* tbitw. */ 2351 void 2352 OP_79_8 (SIM_DESC sd, SIM_CPU *cpu) 2353 { 2354 uint16_t a = (OP[0]); 2355 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2356 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 2357 tmp = RW (addr); 2358 SET_PSR_F (tmp & (1 << a)); 2359 trace_output_32 (sd, addr); 2360 } 2361 2362 /* tbitw. */ 2363 void 2364 OP_11D_14 (SIM_DESC sd, SIM_CPU *cpu) 2365 { 2366 uint16_t a = (OP[0]); 2367 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2368 trace_input ("tbitw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 2369 tmp = RW (addr); 2370 SET_PSR_F (tmp & (1 << a)); 2371 trace_output_32 (sd, addr); 2372 } 2373 2374 2375 /* tbitw. */ 2376 void 2377 OP_11E_14 (SIM_DESC sd, SIM_CPU *cpu) 2378 { 2379 uint16_t a = (OP[0]); 2380 uint32_t addr = (GPR32 (OP[2])) + OP[1], tmp; 2381 trace_input ("tbitw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 2382 tmp = RW (addr); 2383 SET_PSR_F (tmp & (1 << a)); 2384 trace_output_32 (sd, addr); 2385 } 2386 2387 2388 /* tbit. */ 2389 void 2390 OP_6_8 (SIM_DESC sd, SIM_CPU *cpu) 2391 { 2392 uint16_t a = OP[0]; 2393 uint16_t b = (GPR (OP[1])); 2394 trace_input ("tbit", OP_CONSTANT4, OP_REG, OP_VOID); 2395 SET_PSR_F (b & (1 << a)); 2396 trace_output_16 (sd, b); 2397 } 2398 2399 /* tbit. */ 2400 void 2401 OP_7_8 (SIM_DESC sd, SIM_CPU *cpu) 2402 { 2403 uint16_t a = GPR (OP[0]); 2404 uint16_t b = (GPR (OP[1])); 2405 trace_input ("tbit", OP_REG, OP_REG, OP_VOID); 2406 SET_PSR_F (b & (1 << a)); 2407 trace_output_16 (sd, b); 2408 } 2409 2410 2411 /* cmpb. */ 2412 void 2413 OP_50_8 (SIM_DESC sd, SIM_CPU *cpu) 2414 { 2415 uint8_t a = (OP[0]) & 0xFF; 2416 uint8_t b = (GPR (OP[1])) & 0xFF; 2417 trace_input ("cmpb", OP_CONSTANT4, OP_REG, OP_VOID); 2418 SET_PSR_Z (a == b); 2419 SET_PSR_N ((int8_t)a > (int8_t)b); 2420 SET_PSR_L (a > b); 2421 trace_output_flag (sd); 2422 } 2423 2424 /* cmpb. */ 2425 void 2426 OP_50B_C (SIM_DESC sd, SIM_CPU *cpu) 2427 { 2428 uint8_t a = (OP[0]) & 0xFF; 2429 uint8_t b = (GPR (OP[1])) & 0xFF; 2430 trace_input ("cmpb", OP_CONSTANT16, OP_REG, OP_VOID); 2431 SET_PSR_Z (a == b); 2432 SET_PSR_N ((int8_t)a > (int8_t)b); 2433 SET_PSR_L (a > b); 2434 trace_output_flag (sd); 2435 } 2436 2437 /* cmpb. */ 2438 void 2439 OP_51_8 (SIM_DESC sd, SIM_CPU *cpu) 2440 { 2441 uint8_t a = (GPR (OP[0])) & 0xFF; 2442 uint8_t b = (GPR (OP[1])) & 0xFF; 2443 trace_input ("cmpb", OP_REG, OP_REG, OP_VOID); 2444 SET_PSR_Z (a == b); 2445 SET_PSR_N ((int8_t)a > (int8_t)b); 2446 SET_PSR_L (a > b); 2447 trace_output_flag (sd); 2448 } 2449 2450 /* cmpw. */ 2451 void 2452 OP_52_8 (SIM_DESC sd, SIM_CPU *cpu) 2453 { 2454 uint16_t a = (OP[0]); 2455 uint16_t b = GPR (OP[1]); 2456 trace_input ("cmpw", OP_CONSTANT4, OP_REG, OP_VOID); 2457 SET_PSR_Z (a == b); 2458 SET_PSR_N ((int16_t)a > (int16_t)b); 2459 SET_PSR_L (a > b); 2460 trace_output_flag (sd); 2461 } 2462 2463 /* cmpw. */ 2464 void 2465 OP_52B_C (SIM_DESC sd, SIM_CPU *cpu) 2466 { 2467 uint16_t a = (OP[0]); 2468 uint16_t b = GPR (OP[1]); 2469 trace_input ("cmpw", OP_CONSTANT16, OP_REG, OP_VOID); 2470 SET_PSR_Z (a == b); 2471 SET_PSR_N ((int16_t)a > (int16_t)b); 2472 SET_PSR_L (a > b); 2473 trace_output_flag (sd); 2474 } 2475 2476 /* cmpw. */ 2477 void 2478 OP_53_8 (SIM_DESC sd, SIM_CPU *cpu) 2479 { 2480 uint16_t a = GPR (OP[0]) ; 2481 uint16_t b = GPR (OP[1]) ; 2482 trace_input ("cmpw", OP_REG, OP_REG, OP_VOID); 2483 SET_PSR_Z (a == b); 2484 SET_PSR_N ((int16_t)a > (int16_t)b); 2485 SET_PSR_L (a > b); 2486 trace_output_flag (sd); 2487 } 2488 2489 /* cmpd. */ 2490 void 2491 OP_56_8 (SIM_DESC sd, SIM_CPU *cpu) 2492 { 2493 uint32_t a = (OP[0]); 2494 uint32_t b = GPR32 (OP[1]); 2495 trace_input ("cmpd", OP_CONSTANT4, OP_REGP, OP_VOID); 2496 SET_PSR_Z (a == b); 2497 SET_PSR_N ((int32_t)a > (int32_t)b); 2498 SET_PSR_L (a > b); 2499 trace_output_flag (sd); 2500 } 2501 2502 /* cmpd. */ 2503 void 2504 OP_56B_C (SIM_DESC sd, SIM_CPU *cpu) 2505 { 2506 uint32_t a = (SEXT16(OP[0])); 2507 uint32_t b = GPR32 (OP[1]); 2508 trace_input ("cmpd", OP_CONSTANT16, OP_REGP, OP_VOID); 2509 SET_PSR_Z (a == b); 2510 SET_PSR_N ((int32_t)a > (int32_t)b); 2511 SET_PSR_L (a > b); 2512 trace_output_flag (sd); 2513 } 2514 2515 /* cmpd. */ 2516 void 2517 OP_57_8 (SIM_DESC sd, SIM_CPU *cpu) 2518 { 2519 uint32_t a = GPR32 (OP[0]) ; 2520 uint32_t b = GPR32 (OP[1]) ; 2521 trace_input ("cmpd", OP_REGP, OP_REGP, OP_VOID); 2522 SET_PSR_Z (a == b); 2523 SET_PSR_N ((int32_t)a > (int32_t)b); 2524 SET_PSR_L (a > b); 2525 trace_output_flag (sd); 2526 } 2527 2528 /* cmpd. */ 2529 void 2530 OP_9_C (SIM_DESC sd, SIM_CPU *cpu) 2531 { 2532 uint32_t a = (OP[0]); 2533 uint32_t b = GPR32 (OP[1]); 2534 trace_input ("cmpd", OP_CONSTANT32, OP_REGP, OP_VOID); 2535 SET_PSR_Z (a == b); 2536 SET_PSR_N ((int32_t)a > (int32_t)b); 2537 SET_PSR_L (a > b); 2538 trace_output_flag (sd); 2539 } 2540 2541 2542 /* movb. */ 2543 void 2544 OP_58_8 (SIM_DESC sd, SIM_CPU *cpu) 2545 { 2546 uint8_t tmp = OP[0] & 0xFF; 2547 uint16_t a = (GPR (OP[1])) & 0xFF00; 2548 trace_input ("movb", OP_CONSTANT4, OP_REG, OP_VOID); 2549 SET_GPR (OP[1], (a | tmp)); 2550 trace_output_16 (sd, tmp); 2551 } 2552 2553 /* movb. */ 2554 void 2555 OP_58B_C (SIM_DESC sd, SIM_CPU *cpu) 2556 { 2557 uint8_t tmp = OP[0] & 0xFF; 2558 uint16_t a = (GPR (OP[1])) & 0xFF00; 2559 trace_input ("movb", OP_CONSTANT16, OP_REG, OP_VOID); 2560 SET_GPR (OP[1], (a | tmp)); 2561 trace_output_16 (sd, tmp); 2562 } 2563 2564 /* movb. */ 2565 void 2566 OP_59_8 (SIM_DESC sd, SIM_CPU *cpu) 2567 { 2568 uint8_t tmp = (GPR (OP[0])) & 0xFF; 2569 uint16_t a = (GPR (OP[1])) & 0xFF00; 2570 trace_input ("movb", OP_REG, OP_REG, OP_VOID); 2571 SET_GPR (OP[1], (a | tmp)); 2572 trace_output_16 (sd, tmp); 2573 } 2574 2575 /* movw. */ 2576 void 2577 OP_5A_8 (SIM_DESC sd, SIM_CPU *cpu) 2578 { 2579 uint16_t tmp = OP[0]; 2580 trace_input ("movw", OP_CONSTANT4_1, OP_REG, OP_VOID); 2581 SET_GPR (OP[1], (tmp & 0xffff)); 2582 trace_output_16 (sd, tmp); 2583 } 2584 2585 /* movw. */ 2586 void 2587 OP_5AB_C (SIM_DESC sd, SIM_CPU *cpu) 2588 { 2589 int16_t tmp = OP[0]; 2590 trace_input ("movw", OP_CONSTANT16, OP_REG, OP_VOID); 2591 SET_GPR (OP[1], (tmp & 0xffff)); 2592 trace_output_16 (sd, tmp); 2593 } 2594 2595 /* movw. */ 2596 void 2597 OP_5B_8 (SIM_DESC sd, SIM_CPU *cpu) 2598 { 2599 uint16_t tmp = GPR (OP[0]); 2600 uint32_t a = GPR32 (OP[1]); 2601 trace_input ("movw", OP_REG, OP_REGP, OP_VOID); 2602 a = (a & 0xffff0000) | tmp; 2603 SET_GPR32 (OP[1], a); 2604 trace_output_16 (sd, tmp); 2605 } 2606 2607 /* movxb. */ 2608 void 2609 OP_5C_8 (SIM_DESC sd, SIM_CPU *cpu) 2610 { 2611 uint8_t tmp = (GPR (OP[0])) & 0xFF; 2612 trace_input ("movxb", OP_REG, OP_REG, OP_VOID); 2613 SET_GPR (OP[1], ((SEXT8(tmp)) & 0xffff)); 2614 trace_output_16 (sd, tmp); 2615 } 2616 2617 /* movzb. */ 2618 void 2619 OP_5D_8 (SIM_DESC sd, SIM_CPU *cpu) 2620 { 2621 uint8_t tmp = (GPR (OP[0])) & 0xFF; 2622 trace_input ("movzb", OP_REG, OP_REG, OP_VOID); 2623 SET_GPR (OP[1], tmp); 2624 trace_output_16 (sd, tmp); 2625 } 2626 2627 /* movxw. */ 2628 void 2629 OP_5E_8 (SIM_DESC sd, SIM_CPU *cpu) 2630 { 2631 uint16_t tmp = GPR (OP[0]); 2632 trace_input ("movxw", OP_REG, OP_REGP, OP_VOID); 2633 SET_GPR32 (OP[1], SEXT16(tmp)); 2634 trace_output_16 (sd, tmp); 2635 } 2636 2637 /* movzw. */ 2638 void 2639 OP_5F_8 (SIM_DESC sd, SIM_CPU *cpu) 2640 { 2641 uint16_t tmp = GPR (OP[0]); 2642 trace_input ("movzw", OP_REG, OP_REGP, OP_VOID); 2643 SET_GPR32 (OP[1], (tmp & 0x0000FFFF)); 2644 trace_output_16 (sd, tmp); 2645 } 2646 2647 /* movd. */ 2648 void 2649 OP_54_8 (SIM_DESC sd, SIM_CPU *cpu) 2650 { 2651 int32_t tmp = OP[0]; 2652 trace_input ("movd", OP_CONSTANT4, OP_REGP, OP_VOID); 2653 SET_GPR32 (OP[1], tmp); 2654 trace_output_32 (sd, tmp); 2655 } 2656 2657 /* movd. */ 2658 void 2659 OP_54B_C (SIM_DESC sd, SIM_CPU *cpu) 2660 { 2661 int32_t tmp = SEXT16(OP[0]); 2662 trace_input ("movd", OP_CONSTANT16, OP_REGP, OP_VOID); 2663 SET_GPR32 (OP[1], tmp); 2664 trace_output_32 (sd, tmp); 2665 } 2666 2667 /* movd. */ 2668 void 2669 OP_55_8 (SIM_DESC sd, SIM_CPU *cpu) 2670 { 2671 uint32_t tmp = GPR32 (OP[0]); 2672 trace_input ("movd", OP_REGP, OP_REGP, OP_VOID); 2673 SET_GPR32 (OP[1], tmp); 2674 trace_output_32 (sd, tmp); 2675 } 2676 2677 /* movd. */ 2678 void 2679 OP_5_8 (SIM_DESC sd, SIM_CPU *cpu) 2680 { 2681 uint32_t tmp = OP[0]; 2682 trace_input ("movd", OP_CONSTANT20, OP_REGP, OP_VOID); 2683 SET_GPR32 (OP[1], tmp); 2684 trace_output_32 (sd, tmp); 2685 } 2686 2687 /* movd. */ 2688 void 2689 OP_7_C (SIM_DESC sd, SIM_CPU *cpu) 2690 { 2691 int32_t tmp = OP[0]; 2692 trace_input ("movd", OP_CONSTANT32, OP_REGP, OP_VOID); 2693 SET_GPR32 (OP[1], tmp); 2694 trace_output_32 (sd, tmp); 2695 } 2696 2697 /* loadm. */ 2698 void 2699 OP_14_D (SIM_DESC sd, SIM_CPU *cpu) 2700 { 2701 uint32_t addr = GPR (0); 2702 uint16_t count = OP[0], reg = 2, tmp; 2703 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); 2704 if ((addr & 1)) 2705 { 2706 trace_output_void (sd); 2707 EXCEPTION (SIM_SIGBUS); 2708 } 2709 2710 while (count) 2711 { 2712 tmp = RW (addr); 2713 SET_GPR (reg, tmp); 2714 addr +=2; 2715 --count; 2716 reg++; 2717 if (reg == 6) reg = 8; 2718 }; 2719 2720 SET_GPR (0, addr); 2721 trace_output_void (sd); 2722 } 2723 2724 2725 /* loadmp. */ 2726 void 2727 OP_15_D (SIM_DESC sd, SIM_CPU *cpu) 2728 { 2729 uint32_t addr = GPR32 (0); 2730 uint16_t count = OP[0], reg = 2, tmp; 2731 trace_input ("loadm", OP_CONSTANT4, OP_VOID, OP_VOID); 2732 if ((addr & 1)) 2733 { 2734 trace_output_void (sd); 2735 EXCEPTION (SIM_SIGBUS); 2736 } 2737 2738 while (count) 2739 { 2740 tmp = RW (addr); 2741 SET_GPR (reg, tmp); 2742 addr +=2; 2743 --count; 2744 reg++; 2745 if (reg == 6) reg = 8; 2746 }; 2747 2748 SET_GPR32 (0, addr); 2749 trace_output_void (sd); 2750 } 2751 2752 2753 /* loadb. */ 2754 void 2755 OP_88_8 (SIM_DESC sd, SIM_CPU *cpu) 2756 { 2757 /* loadb ABS20, REG 2758 * ADDR = zext24(abs20) | remap (ie 0xF00000) 2759 * REG = [ADDR] 2760 * NOTE: remap is 2761 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 2762 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 2763 * by the core to 16M-64k to 16M. */ 2764 2765 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00; 2766 uint32_t addr = OP[0]; 2767 trace_input ("loadb", OP_ABS20, OP_REG, OP_VOID); 2768 if (addr > 0xEFFFF) addr |= 0xF00000; 2769 tmp = (RB (addr)); 2770 SET_GPR (OP[1], (a | tmp)); 2771 trace_output_16 (sd, tmp); 2772 } 2773 2774 /* loadb. */ 2775 void 2776 OP_127_14 (SIM_DESC sd, SIM_CPU *cpu) 2777 { 2778 /* loadb ABS24, REG 2779 * ADDR = abs24 2780 * REGR = [ADDR]. */ 2781 2782 uint16_t tmp, a = (GPR (OP[1])) & 0xFF00; 2783 uint32_t addr = OP[0]; 2784 trace_input ("loadb", OP_ABS24, OP_REG, OP_VOID); 2785 tmp = (RB (addr)); 2786 SET_GPR (OP[1], (a | tmp)); 2787 trace_output_16 (sd, tmp); 2788 } 2789 2790 /* loadb. */ 2791 void 2792 OP_45_7 (SIM_DESC sd, SIM_CPU *cpu) 2793 { 2794 /* loadb [Rindex]ABS20 REG 2795 * ADDR = Rindex + zext24(disp20) 2796 * REGR = [ADDR]. */ 2797 2798 uint32_t addr; 2799 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00; 2800 trace_input ("loadb", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); 2801 2802 if (OP[0] == 0) 2803 addr = (GPR32 (12)) + OP[1]; 2804 else 2805 addr = (GPR32 (13)) + OP[1]; 2806 2807 tmp = (RB (addr)); 2808 SET_GPR (OP[2], (a | tmp)); 2809 trace_output_16 (sd, tmp); 2810 } 2811 2812 2813 /* loadb. */ 2814 void 2815 OP_B_4 (SIM_DESC sd, SIM_CPU *cpu) 2816 { 2817 /* loadb DIPS4(REGP) REG 2818 * ADDR = RPBASE + zext24(DISP4) 2819 * REG = [ADDR]. */ 2820 uint16_t tmp, a = (GPR (OP[2])) & 0xFF00; 2821 uint32_t addr = (GPR32 (OP[1])) + OP[0]; 2822 trace_input ("loadb", OP_RP_BASE_DISP4, OP_REG, OP_VOID); 2823 tmp = (RB (addr)); 2824 SET_GPR (OP[2], (a | tmp)); 2825 trace_output_16 (sd, tmp); 2826 } 2827 2828 /* loadb. */ 2829 void 2830 OP_BE_8 (SIM_DESC sd, SIM_CPU *cpu) 2831 { 2832 /* loadb [Rindex]disp0(RPbasex) REG 2833 * ADDR = Rpbasex + Rindex 2834 * REGR = [ADDR] */ 2835 2836 uint32_t addr; 2837 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00; 2838 trace_input ("loadb", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); 2839 2840 addr = (GPR32 (OP[2])) + OP[1]; 2841 2842 if (OP[0] == 0) 2843 addr = (GPR32 (12)) + addr; 2844 else 2845 addr = (GPR32 (13)) + addr; 2846 2847 tmp = (RB (addr)); 2848 SET_GPR (OP[3], (a | tmp)); 2849 trace_output_16 (sd, tmp); 2850 } 2851 2852 /* loadb. */ 2853 void 2854 OP_219_A (SIM_DESC sd, SIM_CPU *cpu) 2855 { 2856 /* loadb [Rindex]disp14(RPbasex) REG 2857 * ADDR = Rpbasex + Rindex + zext24(disp14) 2858 * REGR = [ADDR] */ 2859 2860 uint32_t addr; 2861 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00; 2862 2863 addr = (GPR32 (OP[2])) + OP[1]; 2864 2865 if (OP[0] == 0) 2866 addr = (GPR32 (12)) + addr; 2867 else 2868 addr = (GPR32 (13)) + addr; 2869 2870 trace_input ("loadb", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); 2871 tmp = (RB (addr)); 2872 SET_GPR (OP[3], (a | tmp)); 2873 trace_output_16 (sd, tmp); 2874 } 2875 2876 2877 /* loadb. */ 2878 void 2879 OP_184_14 (SIM_DESC sd, SIM_CPU *cpu) 2880 { 2881 /* loadb DISPE20(REG) REG 2882 * zext24(Rbase) + zext24(dispe20) 2883 * REG = [ADDR] */ 2884 2885 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00; 2886 uint32_t addr = OP[0] + (GPR (OP[1])); 2887 trace_input ("loadb", OP_R_BASE_DISPE20, OP_REG, OP_VOID); 2888 tmp = (RB (addr)); 2889 SET_GPR (OP[2], (a | tmp)); 2890 trace_output_16 (sd, tmp); 2891 } 2892 2893 /* loadb. */ 2894 void 2895 OP_124_14 (SIM_DESC sd, SIM_CPU *cpu) 2896 { 2897 /* loadb DISP20(REG) REG 2898 * ADDR = zext24(Rbase) + zext24(disp20) 2899 * REG = [ADDR] */ 2900 2901 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00; 2902 uint32_t addr = OP[0] + (GPR (OP[1])); 2903 trace_input ("loadb", OP_R_BASE_DISP20, OP_REG, OP_VOID); 2904 tmp = (RB (addr)); 2905 SET_GPR (OP[2], (a | tmp)); 2906 trace_output_16 (sd, tmp); 2907 } 2908 2909 /* loadb. */ 2910 void 2911 OP_BF_8 (SIM_DESC sd, SIM_CPU *cpu) 2912 { 2913 /* loadb disp16(REGP) REG 2914 * ADDR = RPbase + zext24(disp16) 2915 * REGR = [ADDR] */ 2916 2917 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00; 2918 uint32_t addr = (GPR32 (OP[1])) + OP[0]; 2919 trace_input ("loadb", OP_RP_BASE_DISP16, OP_REG, OP_VOID); 2920 tmp = (RB (addr)); 2921 SET_GPR (OP[2], (a | tmp)); 2922 trace_output_16 (sd, tmp); 2923 } 2924 2925 /* loadb. */ 2926 void 2927 OP_125_14 (SIM_DESC sd, SIM_CPU *cpu) 2928 { 2929 /* loadb disp20(REGP) REG 2930 * ADDR = RPbase + zext24(disp20) 2931 * REGR = [ADDR] */ 2932 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00; 2933 uint32_t addr = (GPR32 (OP[1])) + OP[0]; 2934 trace_input ("loadb", OP_RP_BASE_DISP20, OP_REG, OP_VOID); 2935 tmp = (RB (addr)); 2936 SET_GPR (OP[2], (a | tmp)); 2937 trace_output_16 (sd, tmp); 2938 } 2939 2940 2941 /* loadb. */ 2942 void 2943 OP_185_14 (SIM_DESC sd, SIM_CPU *cpu) 2944 { 2945 /* loadb -disp20(REGP) REG 2946 * ADDR = RPbase + zext24(-disp20) 2947 * REGR = [ADDR] */ 2948 uint16_t tmp,a = (GPR (OP[2])) & 0xFF00; 2949 uint32_t addr = (GPR32 (OP[1])) + OP[1]; 2950 trace_input ("loadb", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); 2951 tmp = (RB (addr)); 2952 SET_GPR (OP[2], (a | tmp)); 2953 trace_output_16 (sd, tmp); 2954 } 2955 2956 /* loadb. */ 2957 void 2958 OP_126_14 (SIM_DESC sd, SIM_CPU *cpu) 2959 { 2960 /* loadb [Rindex]disp20(RPbasexb) REG 2961 * ADDR = RPbasex + Rindex + zext24(disp20) 2962 * REGR = [ADDR] */ 2963 2964 uint32_t addr; 2965 uint16_t tmp, a = (GPR (OP[3])) & 0xFF00; 2966 trace_input ("loadb", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); 2967 2968 addr = (GPR32 (OP[2])) + OP[1]; 2969 2970 if (OP[0] == 0) 2971 addr = (GPR32 (12)) + addr; 2972 else 2973 addr = (GPR32 (13)) + addr; 2974 2975 tmp = (RB (addr)); 2976 SET_GPR (OP[3], (a | tmp)); 2977 trace_output_16 (sd, tmp); 2978 } 2979 2980 2981 /* loadw. */ 2982 void 2983 OP_89_8 (SIM_DESC sd, SIM_CPU *cpu) 2984 { 2985 /* loadw ABS20, REG 2986 * ADDR = zext24(abs20) | remap 2987 * REGR = [ADDR] 2988 * NOTE: remap is 2989 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 2990 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 2991 * by the core to 16M-64k to 16M. */ 2992 2993 uint16_t tmp; 2994 uint32_t addr = OP[0]; 2995 trace_input ("loadw", OP_ABS20, OP_REG, OP_VOID); 2996 if (addr > 0xEFFFF) addr |= 0xF00000; 2997 tmp = (RW (addr)); 2998 SET_GPR (OP[1], tmp); 2999 trace_output_16 (sd, tmp); 3000 } 3001 3002 3003 /* loadw. */ 3004 void 3005 OP_12F_14 (SIM_DESC sd, SIM_CPU *cpu) 3006 { 3007 /* loadw ABS24, REG 3008 * ADDR = abs24 3009 * REGR = [ADDR] */ 3010 uint16_t tmp; 3011 uint32_t addr = OP[0]; 3012 trace_input ("loadw", OP_ABS24, OP_REG, OP_VOID); 3013 tmp = (RW (addr)); 3014 SET_GPR (OP[1], tmp); 3015 trace_output_16 (sd, tmp); 3016 } 3017 3018 /* loadw. */ 3019 void 3020 OP_47_7 (SIM_DESC sd, SIM_CPU *cpu) 3021 { 3022 /* loadw [Rindex]ABS20 REG 3023 * ADDR = Rindex + zext24(disp20) 3024 * REGR = [ADDR] */ 3025 3026 uint32_t addr; 3027 uint16_t tmp; 3028 trace_input ("loadw", OP_R_INDEX8_ABS20, OP_REG, OP_VOID); 3029 3030 if (OP[0] == 0) 3031 addr = (GPR32 (12)) + OP[1]; 3032 else 3033 addr = (GPR32 (13)) + OP[1]; 3034 3035 tmp = (RW (addr)); 3036 SET_GPR (OP[2], tmp); 3037 trace_output_16 (sd, tmp); 3038 } 3039 3040 3041 /* loadw. */ 3042 void 3043 OP_9_4 (SIM_DESC sd, SIM_CPU *cpu) 3044 { 3045 /* loadw DIPS4(REGP) REGP 3046 * ADDR = RPBASE + zext24(DISP4) 3047 * REGP = [ADDR]. */ 3048 uint16_t tmp; 3049 uint32_t addr, a; 3050 trace_input ("loadw", OP_RP_BASE_DISP4, OP_REG, OP_VOID); 3051 addr = (GPR32 (OP[1])) + OP[0]; 3052 tmp = (RW (addr)); 3053 if (OP[2] > 11) 3054 { 3055 a = (GPR32 (OP[2])) & 0xffff0000; 3056 SET_GPR32 (OP[2], (a | tmp)); 3057 } 3058 else 3059 SET_GPR (OP[2], tmp); 3060 3061 trace_output_16 (sd, tmp); 3062 } 3063 3064 3065 /* loadw. */ 3066 void 3067 OP_9E_8 (SIM_DESC sd, SIM_CPU *cpu) 3068 { 3069 /* loadw [Rindex]disp0(RPbasex) REG 3070 * ADDR = Rpbasex + Rindex 3071 * REGR = [ADDR] */ 3072 3073 uint32_t addr; 3074 uint16_t tmp; 3075 trace_input ("loadw", OP_RP_INDEX_DISP0, OP_REG, OP_VOID); 3076 3077 addr = (GPR32 (OP[2])) + OP[1]; 3078 3079 if (OP[0] == 0) 3080 addr = (GPR32 (12)) + addr; 3081 else 3082 addr = (GPR32 (13)) + addr; 3083 3084 tmp = RW (addr); 3085 SET_GPR (OP[3], tmp); 3086 trace_output_16 (sd, tmp); 3087 } 3088 3089 3090 /* loadw. */ 3091 void 3092 OP_21B_A (SIM_DESC sd, SIM_CPU *cpu) 3093 { 3094 /* loadw [Rindex]disp14(RPbasex) REG 3095 * ADDR = Rpbasex + Rindex + zext24(disp14) 3096 * REGR = [ADDR] */ 3097 3098 uint32_t addr; 3099 uint16_t tmp; 3100 trace_input ("loadw", OP_RP_INDEX_DISP14, OP_REG, OP_VOID); 3101 addr = (GPR32 (OP[2])) + OP[1]; 3102 3103 if (OP[0] == 0) 3104 addr = (GPR32 (12)) + addr; 3105 else 3106 addr = (GPR32 (13)) + addr; 3107 3108 tmp = (RW (addr)); 3109 SET_GPR (OP[3], tmp); 3110 trace_output_16 (sd, tmp); 3111 } 3112 3113 /* loadw. */ 3114 void 3115 OP_18C_14 (SIM_DESC sd, SIM_CPU *cpu) 3116 { 3117 /* loadw dispe20(REG) REGP 3118 * REGP = [DISPE20+[REG]] */ 3119 3120 uint16_t tmp; 3121 uint32_t addr, a; 3122 trace_input ("loadw", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); 3123 addr = OP[0] + (GPR (OP[1])); 3124 tmp = (RW (addr)); 3125 if (OP[2] > 11) 3126 { 3127 a = (GPR32 (OP[2])) & 0xffff0000; 3128 SET_GPR32 (OP[2], (a | tmp)); 3129 } 3130 else 3131 SET_GPR (OP[2], tmp); 3132 3133 trace_output_16 (sd, tmp); 3134 } 3135 3136 3137 /* loadw. */ 3138 void 3139 OP_12C_14 (SIM_DESC sd, SIM_CPU *cpu) 3140 { 3141 /* loadw DISP20(REG) REGP 3142 * ADDR = zext24(Rbase) + zext24(disp20) 3143 * REGP = [ADDR] */ 3144 3145 uint16_t tmp; 3146 uint32_t addr, a; 3147 trace_input ("loadw", OP_R_BASE_DISP20, OP_REGP, OP_VOID); 3148 addr = OP[0] + (GPR (OP[1])); 3149 tmp = (RW (addr)); 3150 if (OP[2] > 11) 3151 { 3152 a = (GPR32 (OP[2])) & 0xffff0000; 3153 SET_GPR32 (OP[2], (a | tmp)); 3154 } 3155 else 3156 SET_GPR (OP[2], tmp); 3157 3158 trace_output_16 (sd, tmp); 3159 } 3160 3161 /* loadw. */ 3162 void 3163 OP_9F_8 (SIM_DESC sd, SIM_CPU *cpu) 3164 { 3165 /* loadw disp16(REGP) REGP 3166 * ADDR = RPbase + zext24(disp16) 3167 * REGP = [ADDR] */ 3168 uint16_t tmp; 3169 uint32_t addr, a; 3170 trace_input ("loadw", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); 3171 addr = (GPR32 (OP[1])) + OP[0]; 3172 tmp = (RW (addr)); 3173 if (OP[2] > 11) 3174 { 3175 a = (GPR32 (OP[2])) & 0xffff0000; 3176 SET_GPR32 (OP[2], (a | tmp)); 3177 } 3178 else 3179 SET_GPR (OP[2], tmp); 3180 3181 trace_output_16 (sd, tmp); 3182 } 3183 3184 /* loadw. */ 3185 void 3186 OP_12D_14 (SIM_DESC sd, SIM_CPU *cpu) 3187 { 3188 /* loadw disp20(REGP) REGP 3189 * ADDR = RPbase + zext24(disp20) 3190 * REGP = [ADDR] */ 3191 uint16_t tmp; 3192 uint32_t addr, a; 3193 trace_input ("loadw", OP_RP_BASE_DISP20, OP_REG, OP_VOID); 3194 addr = (GPR32 (OP[1])) + OP[0]; 3195 tmp = (RW (addr)); 3196 if (OP[2] > 11) 3197 { 3198 a = (GPR32 (OP[2])) & 0xffff0000; 3199 SET_GPR32 (OP[2], (a | tmp)); 3200 } 3201 else 3202 SET_GPR (OP[2], tmp); 3203 3204 trace_output_16 (sd, tmp); 3205 } 3206 3207 /* loadw. */ 3208 void 3209 OP_18D_14 (SIM_DESC sd, SIM_CPU *cpu) 3210 { 3211 /* loadw -disp20(REGP) REG 3212 * ADDR = RPbase + zext24(-disp20) 3213 * REGR = [ADDR] */ 3214 3215 uint16_t tmp; 3216 uint32_t addr, a; 3217 trace_input ("loadw", OP_RP_BASE_DISPE20, OP_REG, OP_VOID); 3218 addr = (GPR32 (OP[1])) + OP[0]; 3219 tmp = (RB (addr)); 3220 if (OP[2] > 11) 3221 { 3222 a = (GPR32 (OP[2])) & 0xffff0000; 3223 SET_GPR32 (OP[2], (a | tmp)); 3224 } 3225 else 3226 SET_GPR (OP[2], tmp); 3227 3228 trace_output_16 (sd, tmp); 3229 } 3230 3231 3232 /* loadw. */ 3233 void 3234 OP_12E_14 (SIM_DESC sd, SIM_CPU *cpu) 3235 { 3236 /* loadw [Rindex]disp20(RPbasexb) REG 3237 * ADDR = RPbasex + Rindex + zext24(disp20) 3238 * REGR = [ADDR] */ 3239 3240 uint32_t addr; 3241 uint16_t tmp; 3242 trace_input ("loadw", OP_RP_INDEX_DISP20, OP_REG, OP_VOID); 3243 3244 if (OP[0] == 0) 3245 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3246 else 3247 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3248 3249 tmp = (RW (addr)); 3250 SET_GPR (OP[3], tmp); 3251 trace_output_16 (sd, tmp); 3252 } 3253 3254 3255 /* loadd. */ 3256 void 3257 OP_87_8 (SIM_DESC sd, SIM_CPU *cpu) 3258 { 3259 /* loadd ABS20, REGP 3260 * ADDR = zext24(abs20) | remap 3261 * REGP = [ADDR] 3262 * NOTE: remap is 3263 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 3264 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 3265 * by the core to 16M-64k to 16M. */ 3266 3267 uint32_t addr, tmp; 3268 addr = OP[0]; 3269 trace_input ("loadd", OP_ABS20, OP_REGP, OP_VOID); 3270 if (addr > 0xEFFFF) addr |= 0xF00000; 3271 tmp = RLW (addr); 3272 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); 3273 SET_GPR32 (OP[1], tmp); 3274 trace_output_32 (sd, tmp); 3275 } 3276 3277 /* loadd. */ 3278 void 3279 OP_12B_14 (SIM_DESC sd, SIM_CPU *cpu) 3280 { 3281 /* loadd ABS24, REGP 3282 * ADDR = abs24 3283 * REGP = [ADDR] */ 3284 3285 uint32_t addr = OP[0]; 3286 uint32_t tmp; 3287 trace_input ("loadd", OP_ABS24, OP_REGP, OP_VOID); 3288 tmp = RLW (addr); 3289 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3290 SET_GPR32 (OP[1],tmp); 3291 trace_output_32 (sd, tmp); 3292 } 3293 3294 3295 /* loadd. */ 3296 void 3297 OP_46_7 (SIM_DESC sd, SIM_CPU *cpu) 3298 { 3299 /* loadd [Rindex]ABS20 REGP 3300 * ADDR = Rindex + zext24(disp20) 3301 * REGP = [ADDR] */ 3302 3303 uint32_t addr, tmp; 3304 trace_input ("loadd", OP_R_INDEX8_ABS20, OP_REGP, OP_VOID); 3305 3306 if (OP[0] == 0) 3307 addr = (GPR32 (12)) + OP[1]; 3308 else 3309 addr = (GPR32 (13)) + OP[1]; 3310 3311 tmp = RLW (addr); 3312 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3313 SET_GPR32 (OP[2], tmp); 3314 trace_output_32 (sd, tmp); 3315 } 3316 3317 3318 /* loadd. */ 3319 void 3320 OP_A_4 (SIM_DESC sd, SIM_CPU *cpu) 3321 { 3322 /* loadd dips4(regp) REGP 3323 * ADDR = Rpbase + zext24(disp4) 3324 * REGP = [ADDR] */ 3325 3326 uint32_t tmp, addr = (GPR32 (OP[1])) + OP[0]; 3327 trace_input ("loadd", OP_RP_BASE_DISP4, OP_REGP, OP_VOID); 3328 tmp = RLW (addr); 3329 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3330 SET_GPR32 (OP[2], tmp); 3331 trace_output_32 (sd, tmp); 3332 } 3333 3334 3335 /* loadd. */ 3336 void 3337 OP_AE_8 (SIM_DESC sd, SIM_CPU *cpu) 3338 { 3339 /* loadd [Rindex]disp0(RPbasex) REGP 3340 * ADDR = Rpbasex + Rindex 3341 * REGP = [ADDR] */ 3342 3343 uint32_t addr, tmp; 3344 trace_input ("loadd", OP_RP_INDEX_DISP0, OP_REGP, OP_VOID); 3345 3346 if (OP[0] == 0) 3347 addr = (GPR32 (12)) + (GPR32 (OP[2])) + OP[1]; 3348 else 3349 addr = (GPR32 (13)) + (GPR32 (OP[2])) + OP[1]; 3350 3351 tmp = RLW (addr); 3352 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3353 SET_GPR32 (OP[3], tmp); 3354 trace_output_32 (sd, tmp); 3355 } 3356 3357 3358 /* loadd. */ 3359 void 3360 OP_21A_A (SIM_DESC sd, SIM_CPU *cpu) 3361 { 3362 /* loadd [Rindex]disp14(RPbasex) REGP 3363 * ADDR = Rpbasex + Rindex + zext24(disp14) 3364 * REGR = [ADDR] */ 3365 3366 uint32_t addr, tmp; 3367 trace_input ("loadd", OP_RP_INDEX_DISP14, OP_REGP, OP_VOID); 3368 3369 if (OP[0] == 0) 3370 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3371 else 3372 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3373 3374 tmp = RLW (addr); 3375 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3376 SET_GPR (OP[3],tmp); 3377 trace_output_32 (sd, tmp); 3378 } 3379 3380 3381 /* loadd. */ 3382 void 3383 OP_188_14 (SIM_DESC sd, SIM_CPU *cpu) 3384 { 3385 /* loadd dispe20(REG) REG 3386 * zext24(Rbase) + zext24(dispe20) 3387 * REG = [ADDR] */ 3388 3389 uint32_t tmp, addr = OP[0] + (GPR (OP[1])); 3390 trace_input ("loadd", OP_R_BASE_DISPE20, OP_REGP, OP_VOID); 3391 tmp = RLW (addr); 3392 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3393 SET_GPR32 (OP[2], tmp); 3394 trace_output_32 (sd, tmp); 3395 } 3396 3397 3398 /* loadd. */ 3399 void 3400 OP_128_14 (SIM_DESC sd, SIM_CPU *cpu) 3401 { 3402 /* loadd DISP20(REG) REG 3403 * ADDR = zext24(Rbase) + zext24(disp20) 3404 * REG = [ADDR] */ 3405 3406 uint32_t tmp, addr = OP[0] + (GPR (OP[1])); 3407 trace_input ("loadd", OP_R_BASE_DISP20, OP_REGP, OP_VOID); 3408 tmp = RLW (addr); 3409 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3410 SET_GPR32 (OP[2], tmp); 3411 trace_output_32 (sd, tmp); 3412 } 3413 3414 /* loadd. */ 3415 void 3416 OP_AF_8 (SIM_DESC sd, SIM_CPU *cpu) 3417 { 3418 /* loadd disp16(REGP) REGP 3419 * ADDR = RPbase + zext24(disp16) 3420 * REGR = [ADDR] */ 3421 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1])); 3422 trace_input ("loadd", OP_RP_BASE_DISP16, OP_REGP, OP_VOID); 3423 tmp = RLW (addr); 3424 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3425 SET_GPR32 (OP[2], tmp); 3426 trace_output_32 (sd, tmp); 3427 } 3428 3429 3430 /* loadd. */ 3431 void 3432 OP_129_14 (SIM_DESC sd, SIM_CPU *cpu) 3433 { 3434 /* loadd disp20(REGP) REGP 3435 * ADDR = RPbase + zext24(disp20) 3436 * REGP = [ADDR] */ 3437 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1])); 3438 trace_input ("loadd", OP_RP_BASE_DISP20, OP_REGP, OP_VOID); 3439 tmp = RLW (addr); 3440 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3441 SET_GPR32 (OP[2], tmp); 3442 trace_output_32 (sd, tmp); 3443 } 3444 3445 /* loadd. */ 3446 void 3447 OP_189_14 (SIM_DESC sd, SIM_CPU *cpu) 3448 { 3449 /* loadd -disp20(REGP) REGP 3450 * ADDR = RPbase + zext24(-disp20) 3451 * REGP = [ADDR] */ 3452 3453 uint32_t tmp, addr = OP[0] + (GPR32 (OP[1])); 3454 trace_input ("loadd", OP_RP_BASE_DISPE20, OP_REGP, OP_VOID); 3455 tmp = RLW (addr); 3456 tmp = ((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff); 3457 SET_GPR32 (OP[2], tmp); 3458 trace_output_32 (sd, tmp); 3459 } 3460 3461 /* loadd. */ 3462 void 3463 OP_12A_14 (SIM_DESC sd, SIM_CPU *cpu) 3464 { 3465 /* loadd [Rindex]disp20(RPbasexb) REGP 3466 * ADDR = RPbasex + Rindex + zext24(disp20) 3467 * REGP = [ADDR] */ 3468 3469 uint32_t addr, tmp; 3470 trace_input ("loadd", OP_RP_INDEX_DISP20, OP_REGP, OP_VOID); 3471 3472 if (OP[0] == 0) 3473 addr = (GPR32 (12)) + OP[1] + (GPR32 (OP[2])); 3474 else 3475 addr = (GPR32 (13)) + OP[1] + (GPR32 (OP[2])); 3476 3477 tmp = RLW (addr); 3478 tmp = ((tmp << 16) & 0xffff)| ((tmp >> 16) & 0xffff); 3479 SET_GPR32 (OP[3], tmp); 3480 trace_output_32 (sd, tmp); 3481 } 3482 3483 3484 /* storb. */ 3485 void 3486 OP_C8_8 (SIM_DESC sd, SIM_CPU *cpu) 3487 { 3488 /* storb REG, ABS20 3489 * ADDR = zext24(abs20) | remap 3490 * [ADDR] = REGR 3491 * NOTE: remap is 3492 * If (abs20 > 0xEFFFF) the resulting address is logically ORed 3493 * with 0xF00000 i.e. addresses from 1M-64k to 1M are re-mapped 3494 * by the core to 16M-64k to 16M. */ 3495 3496 uint8_t a = ((GPR (OP[0])) & 0xff); 3497 uint32_t addr = OP[1]; 3498 trace_input ("storb", OP_REG, OP_ABS20_OUTPUT, OP_VOID); 3499 SB (addr, a); 3500 trace_output_32 (sd, addr); 3501 } 3502 3503 /* storb. */ 3504 void 3505 OP_137_14 (SIM_DESC sd, SIM_CPU *cpu) 3506 { 3507 /* storb REG, ABS24 3508 * ADDR = abs24 3509 * [ADDR] = REGR. */ 3510 3511 uint8_t a = ((GPR (OP[0])) & 0xff); 3512 uint32_t addr = OP[1]; 3513 trace_input ("storb", OP_REG, OP_ABS24_OUTPUT, OP_VOID); 3514 SB (addr, a); 3515 trace_output_32 (sd, addr); 3516 } 3517 3518 /* storb. */ 3519 void 3520 OP_65_7 (SIM_DESC sd, SIM_CPU *cpu) 3521 { 3522 /* storb REG, [Rindex]ABS20 3523 * ADDR = Rindex + zext24(disp20) 3524 * [ADDR] = REGR */ 3525 3526 uint32_t addr; 3527 uint8_t a = ((GPR (OP[0])) & 0xff); 3528 trace_input ("storb", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); 3529 3530 if (OP[1] == 0) 3531 addr = (GPR32 (12)) + OP[2]; 3532 else 3533 addr = (GPR32 (13)) + OP[2]; 3534 3535 SB (addr, a); 3536 trace_output_32 (sd, addr); 3537 } 3538 3539 /* storb. */ 3540 void 3541 OP_F_4 (SIM_DESC sd, SIM_CPU *cpu) 3542 { 3543 /* storb REG, DIPS4(REGP) 3544 * ADDR = RPBASE + zext24(DISP4) 3545 * [ADDR] = REG. */ 3546 3547 uint16_t a = ((GPR (OP[0])) & 0xff); 3548 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3549 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE4, OP_VOID); 3550 SB (addr, a); 3551 trace_output_32 (sd, addr); 3552 } 3553 3554 /* storb. */ 3555 void 3556 OP_FE_8 (SIM_DESC sd, SIM_CPU *cpu) 3557 { 3558 /* storb [Rindex]disp0(RPbasex) REG 3559 * ADDR = Rpbasex + Rindex 3560 * [ADDR] = REGR */ 3561 3562 uint32_t addr; 3563 uint8_t a = ((GPR (OP[0])) & 0xff); 3564 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); 3565 3566 if (OP[1] == 0) 3567 addr = (GPR32 (12)) + (GPR32 (OP[3])) + OP[2]; 3568 else 3569 addr = (GPR32 (13)) + (GPR32 (OP[3])) + OP[2]; 3570 3571 SB (addr, a); 3572 trace_output_32 (sd, addr); 3573 } 3574 3575 /* storb. */ 3576 void 3577 OP_319_A (SIM_DESC sd, SIM_CPU *cpu) 3578 { 3579 /* storb REG, [Rindex]disp14(RPbasex) 3580 * ADDR = Rpbasex + Rindex + zext24(disp14) 3581 * [ADDR] = REGR */ 3582 3583 uint8_t a = ((GPR (OP[0])) & 0xff); 3584 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3585 trace_input ("storb", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); 3586 SB (addr, a); 3587 trace_output_32 (sd, addr); 3588 } 3589 3590 /* storb. */ 3591 void 3592 OP_194_14 (SIM_DESC sd, SIM_CPU *cpu) 3593 { 3594 /* storb REG, DISPE20(REG) 3595 * zext24(Rbase) + zext24(dispe20) 3596 * [ADDR] = REG */ 3597 3598 uint8_t a = ((GPR (OP[0])) & 0xff); 3599 uint32_t addr = OP[1] + (GPR (OP[2])); 3600 trace_input ("storb", OP_REG, OP_R_BASE_DISPE20, OP_VOID); 3601 SB (addr, a); 3602 trace_output_32 (sd, addr); 3603 } 3604 3605 /* storb. */ 3606 void 3607 OP_134_14 (SIM_DESC sd, SIM_CPU *cpu) 3608 { 3609 /* storb REG, DISP20(REG) 3610 * ADDR = zext24(Rbase) + zext24(disp20) 3611 * [ADDR] = REG */ 3612 3613 uint8_t a = (GPR (OP[0]) & 0xff); 3614 uint32_t addr = OP[1] + (GPR (OP[2])); 3615 trace_input ("storb", OP_REG, OP_R_BASE_DISPS20, OP_VOID); 3616 SB (addr, a); 3617 trace_output_32 (sd, addr); 3618 } 3619 3620 /* storb. */ 3621 void 3622 OP_FF_8 (SIM_DESC sd, SIM_CPU *cpu) 3623 { 3624 /* storb REG, disp16(REGP) 3625 * ADDR = RPbase + zext24(disp16) 3626 * [ADDR] = REGP */ 3627 3628 uint8_t a = ((GPR (OP[0])) & 0xff); 3629 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3630 trace_input ("storb", OP_REG, OP_RP_BASE_DISP16, OP_VOID); 3631 SB (addr, a); 3632 trace_output_32 (sd, addr); 3633 } 3634 3635 /* storb. */ 3636 void 3637 OP_135_14 (SIM_DESC sd, SIM_CPU *cpu) 3638 { 3639 /* storb REG, disp20(REGP) 3640 * ADDR = RPbase + zext24(disp20) 3641 * [ADDR] = REGP */ 3642 3643 uint8_t a = ((GPR (OP[0])) & 0xff); 3644 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3645 trace_input ("storb", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); 3646 SB (addr, a); 3647 trace_output_32 (sd, addr); 3648 } 3649 3650 /* storb. */ 3651 void 3652 OP_195_14 (SIM_DESC sd, SIM_CPU *cpu) 3653 { 3654 /* storb REG, -disp20(REGP) 3655 * ADDR = RPbase + zext24(-disp20) 3656 * [ADDR] = REGP */ 3657 3658 uint8_t a = (GPR (OP[0]) & 0xff); 3659 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3660 trace_input ("storb", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); 3661 SB (addr, a); 3662 trace_output_32 (sd, addr); 3663 } 3664 3665 /* storb. */ 3666 void 3667 OP_136_14 (SIM_DESC sd, SIM_CPU *cpu) 3668 { 3669 /* storb REG, [Rindex]disp20(RPbase) 3670 * ADDR = RPbasex + Rindex + zext24(disp20) 3671 * [ADDR] = REGP */ 3672 3673 uint8_t a = (GPR (OP[0])) & 0xff; 3674 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3675 trace_input ("storb", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); 3676 SB (addr, a); 3677 trace_output_32 (sd, addr); 3678 } 3679 3680 /* STR_IMM instructions. */ 3681 /* storb . */ 3682 void 3683 OP_81_8 (SIM_DESC sd, SIM_CPU *cpu) 3684 { 3685 uint8_t a = (OP[0]) & 0xff; 3686 uint32_t addr = OP[1]; 3687 trace_input ("storb", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 3688 SB (addr, a); 3689 trace_output_32 (sd, addr); 3690 } 3691 3692 /* storb. */ 3693 void 3694 OP_123_14 (SIM_DESC sd, SIM_CPU *cpu) 3695 { 3696 uint8_t a = (OP[0]) & 0xff; 3697 uint32_t addr = OP[1]; 3698 trace_input ("storb", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 3699 SB (addr, a); 3700 trace_output_32 (sd, addr); 3701 } 3702 3703 /* storb. */ 3704 void 3705 OP_42_7 (SIM_DESC sd, SIM_CPU *cpu) 3706 { 3707 uint32_t addr; 3708 uint8_t a = (OP[0]) & 0xff; 3709 trace_input ("storb", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 3710 3711 if (OP[1] == 0) 3712 addr = (GPR32 (12)) + OP[2]; 3713 else 3714 addr = (GPR32 (13)) + OP[2]; 3715 3716 SB (addr, a); 3717 trace_output_32 (sd, addr); 3718 } 3719 3720 /* storb. */ 3721 void 3722 OP_218_A (SIM_DESC sd, SIM_CPU *cpu) 3723 { 3724 uint8_t a = (OP[0]) & 0xff; 3725 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3726 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); 3727 SB (addr, a); 3728 trace_output_32 (sd, addr); 3729 } 3730 3731 /* storb. */ 3732 void 3733 OP_82_8 (SIM_DESC sd, SIM_CPU *cpu) 3734 { 3735 uint8_t a = (OP[0]) & 0xff; 3736 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3737 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 3738 SB (addr, a); 3739 trace_output_32 (sd, addr); 3740 } 3741 3742 /* storb. */ 3743 void 3744 OP_120_14 (SIM_DESC sd, SIM_CPU *cpu) 3745 { 3746 uint8_t a = (OP[0]) & 0xff; 3747 uint32_t addr = (GPR (OP[2])) + OP[1]; 3748 trace_input ("storb", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 3749 SB (addr, a); 3750 trace_output_32 (sd, addr); 3751 } 3752 3753 /* storb. */ 3754 void 3755 OP_83_8 (SIM_DESC sd, SIM_CPU *cpu) 3756 { 3757 uint8_t a = (OP[0]) & 0xff; 3758 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3759 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 3760 SB (addr, a); 3761 trace_output_32 (sd, addr); 3762 } 3763 3764 /* storb. */ 3765 void 3766 OP_121_14 (SIM_DESC sd, SIM_CPU *cpu) 3767 { 3768 uint8_t a = (OP[0]) & 0xff; 3769 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3770 trace_input ("storb", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 3771 SB (addr, a); 3772 trace_output_32 (sd, addr); 3773 } 3774 3775 /* storb. */ 3776 void 3777 OP_122_14 (SIM_DESC sd, SIM_CPU *cpu) 3778 { 3779 uint8_t a = (OP[0]) & 0xff; 3780 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3781 trace_input ("storb", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 3782 SB (addr, a); 3783 trace_output_32 (sd, addr); 3784 } 3785 /* endif for STR_IMM. */ 3786 3787 /* storw . */ 3788 void 3789 OP_C9_8 (SIM_DESC sd, SIM_CPU *cpu) 3790 { 3791 uint16_t a = GPR (OP[0]); 3792 uint32_t addr = OP[1]; 3793 trace_input ("storw", OP_REG, OP_ABS20_OUTPUT, OP_VOID); 3794 SW (addr, a); 3795 trace_output_32 (sd, addr); 3796 } 3797 3798 /* storw. */ 3799 void 3800 OP_13F_14 (SIM_DESC sd, SIM_CPU *cpu) 3801 { 3802 uint16_t a = GPR (OP[0]); 3803 uint32_t addr = OP[1]; 3804 trace_input ("storw", OP_REG, OP_ABS24_OUTPUT, OP_VOID); 3805 SW (addr, a); 3806 trace_output_32 (sd, addr); 3807 } 3808 3809 /* storw. */ 3810 void 3811 OP_67_7 (SIM_DESC sd, SIM_CPU *cpu) 3812 { 3813 uint32_t addr; 3814 uint16_t a = GPR (OP[0]); 3815 trace_input ("storw", OP_REG, OP_R_INDEX8_ABS20, OP_VOID); 3816 3817 if (OP[1] == 0) 3818 addr = (GPR32 (12)) + OP[2]; 3819 else 3820 addr = (GPR32 (13)) + OP[2]; 3821 3822 SW (addr, a); 3823 trace_output_32 (sd, addr); 3824 } 3825 3826 3827 /* storw. */ 3828 void 3829 OP_D_4 (SIM_DESC sd, SIM_CPU *cpu) 3830 { 3831 uint16_t a = (GPR (OP[0])); 3832 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3833 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); 3834 SW (addr, a); 3835 trace_output_32 (sd, addr); 3836 } 3837 3838 /* storw. */ 3839 void 3840 OP_DE_8 (SIM_DESC sd, SIM_CPU *cpu) 3841 { 3842 uint16_t a = GPR (OP[0]); 3843 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3844 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP0, OP_VOID); 3845 SW (addr, a); 3846 trace_output_32 (sd, addr); 3847 } 3848 3849 /* storw. */ 3850 void 3851 OP_31B_A (SIM_DESC sd, SIM_CPU *cpu) 3852 { 3853 uint16_t a = GPR (OP[0]); 3854 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3855 trace_input ("storw", OP_REG, OP_RP_INDEX_DISP14, OP_VOID); 3856 SW (addr, a); 3857 trace_output_32 (sd, addr); 3858 } 3859 3860 /* storw. */ 3861 void 3862 OP_19C_14 (SIM_DESC sd, SIM_CPU *cpu) 3863 { 3864 uint16_t a = (GPR (OP[0])); 3865 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3866 trace_input ("storw", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); 3867 SW (addr, a); 3868 trace_output_32 (sd, addr); 3869 } 3870 3871 /* storw. */ 3872 void 3873 OP_13C_14 (SIM_DESC sd, SIM_CPU *cpu) 3874 { 3875 uint16_t a = (GPR (OP[0])); 3876 uint32_t addr = (GPR (OP[2])) + OP[1]; 3877 trace_input ("storw", OP_REG, OP_R_BASE_DISPS20, OP_VOID); 3878 SW (addr, a); 3879 trace_output_32 (sd, addr); 3880 } 3881 3882 /* storw. */ 3883 void 3884 OP_DF_8 (SIM_DESC sd, SIM_CPU *cpu) 3885 { 3886 uint16_t a = (GPR (OP[0])); 3887 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3888 trace_input ("storw", OP_REG, OP_RP_BASE_DISP16, OP_VOID); 3889 SW (addr, a); 3890 trace_output_32 (sd, addr); 3891 } 3892 3893 /* storw. */ 3894 void 3895 OP_13D_14 (SIM_DESC sd, SIM_CPU *cpu) 3896 { 3897 uint16_t a = (GPR (OP[0])); 3898 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3899 trace_input ("storw", OP_REG, OP_RP_BASE_DISPS20, OP_VOID); 3900 SW (addr, a); 3901 trace_output_32 (sd, addr); 3902 } 3903 3904 /* storw. */ 3905 void 3906 OP_19D_14 (SIM_DESC sd, SIM_CPU *cpu) 3907 { 3908 uint16_t a = (GPR (OP[0])); 3909 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3910 trace_input ("storw", OP_REG, OP_RP_BASE_DISPE20, OP_VOID); 3911 SW (addr, a); 3912 trace_output_32 (sd, addr); 3913 } 3914 3915 /* storw. */ 3916 void 3917 OP_13E_14 (SIM_DESC sd, SIM_CPU *cpu) 3918 { 3919 uint16_t a = (GPR (OP[0])); 3920 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3921 trace_input ("storw", OP_REG, OP_RP_INDEX_DISPS20, OP_VOID); 3922 SW (addr, a); 3923 trace_output_32 (sd, addr); 3924 } 3925 3926 /* STORE-w IMM instruction *****/ 3927 /* storw . */ 3928 void 3929 OP_C1_8 (SIM_DESC sd, SIM_CPU *cpu) 3930 { 3931 uint16_t a = OP[0]; 3932 uint32_t addr = OP[1]; 3933 trace_input ("storw", OP_CONSTANT4, OP_ABS20_OUTPUT, OP_VOID); 3934 SW (addr, a); 3935 trace_output_32 (sd, addr); 3936 } 3937 3938 /* storw. */ 3939 void 3940 OP_133_14 (SIM_DESC sd, SIM_CPU *cpu) 3941 { 3942 uint16_t a = OP[0]; 3943 uint32_t addr = OP[1]; 3944 trace_input ("storw", OP_CONSTANT4, OP_ABS24_OUTPUT, OP_VOID); 3945 SW (addr, a); 3946 trace_output_32 (sd, addr); 3947 } 3948 3949 /* storw. */ 3950 void 3951 OP_62_7 (SIM_DESC sd, SIM_CPU *cpu) 3952 { 3953 uint32_t addr; 3954 uint16_t a = OP[0]; 3955 trace_input ("storw", OP_CONSTANT4, OP_R_INDEX8_ABS20, OP_VOID); 3956 3957 if (OP[1] == 0) 3958 addr = (GPR32 (12)) + OP[2]; 3959 else 3960 addr = (GPR32 (13)) + OP[2]; 3961 3962 SW (addr, a); 3963 trace_output_32 (sd, addr); 3964 } 3965 3966 /* storw. */ 3967 void 3968 OP_318_A (SIM_DESC sd, SIM_CPU *cpu) 3969 { 3970 uint16_t a = OP[0]; 3971 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3972 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP14, OP_VOID); 3973 SW (addr, a); 3974 trace_output_32 (sd, addr); 3975 } 3976 3977 /* storw. */ 3978 void 3979 OP_C2_8 (SIM_DESC sd, SIM_CPU *cpu) 3980 { 3981 uint16_t a = OP[0]; 3982 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3983 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISP0, OP_VOID); 3984 SW (addr, a); 3985 trace_output_32 (sd, addr); 3986 } 3987 3988 /* storw. */ 3989 void 3990 OP_130_14 (SIM_DESC sd, SIM_CPU *cpu) 3991 { 3992 uint16_t a = OP[0]; 3993 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 3994 trace_input ("storw", OP_CONSTANT4, OP_R_BASE_DISPS20, OP_VOID); 3995 SW (addr, a); 3996 trace_output_32 (sd, addr); 3997 } 3998 3999 /* storw. */ 4000 void 4001 OP_C3_8 (SIM_DESC sd, SIM_CPU *cpu) 4002 { 4003 uint16_t a = OP[0]; 4004 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4005 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISP16, OP_VOID); 4006 SW (addr, a); 4007 trace_output_32 (sd, addr); 4008 } 4009 4010 4011 /* storw. */ 4012 void 4013 OP_131_14 (SIM_DESC sd, SIM_CPU *cpu) 4014 { 4015 uint16_t a = OP[0]; 4016 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4017 trace_input ("storw", OP_CONSTANT4, OP_RP_BASE_DISPS20, OP_VOID); 4018 SW (addr, a); 4019 trace_output_32 (sd, addr); 4020 } 4021 4022 /* storw. */ 4023 void 4024 OP_132_14 (SIM_DESC sd, SIM_CPU *cpu) 4025 { 4026 uint16_t a = OP[0]; 4027 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4028 trace_input ("storw", OP_CONSTANT4, OP_RP_INDEX_DISPS20, OP_VOID); 4029 SW (addr, a); 4030 trace_output_32 (sd, addr); 4031 } 4032 4033 4034 /* stord. */ 4035 void 4036 OP_C7_8 (SIM_DESC sd, SIM_CPU *cpu) 4037 { 4038 uint32_t a = GPR32 (OP[0]); 4039 uint32_t addr = OP[1]; 4040 trace_input ("stord", OP_REGP, OP_ABS20_OUTPUT, OP_VOID); 4041 SLW (addr, a); 4042 trace_output_32 (sd, addr); 4043 } 4044 4045 /* stord. */ 4046 void 4047 OP_13B_14 (SIM_DESC sd, SIM_CPU *cpu) 4048 { 4049 uint32_t a = GPR32 (OP[0]); 4050 uint32_t addr = OP[1]; 4051 trace_input ("stord", OP_REGP, OP_ABS24_OUTPUT, OP_VOID); 4052 SLW (addr, a); 4053 trace_output_32 (sd, addr); 4054 } 4055 4056 /* stord. */ 4057 void 4058 OP_66_7 (SIM_DESC sd, SIM_CPU *cpu) 4059 { 4060 uint32_t addr, a = GPR32 (OP[0]); 4061 trace_input ("stord", OP_REGP, OP_R_INDEX8_ABS20, OP_VOID); 4062 4063 if (OP[1] == 0) 4064 addr = (GPR32 (12)) + OP[2]; 4065 else 4066 addr = (GPR32 (13)) + OP[2]; 4067 4068 SLW (addr, a); 4069 trace_output_32 (sd, addr); 4070 } 4071 4072 /* stord. */ 4073 void 4074 OP_E_4 (SIM_DESC sd, SIM_CPU *cpu) 4075 { 4076 uint32_t a = GPR32 (OP[0]); 4077 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4078 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE4, OP_VOID); 4079 SLW (addr, a); 4080 trace_output_32 (sd, addr); 4081 } 4082 4083 /* stord. */ 4084 void 4085 OP_EE_8 (SIM_DESC sd, SIM_CPU *cpu) 4086 { 4087 uint32_t a = GPR32 (OP[0]); 4088 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4089 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP0, OP_VOID); 4090 SLW (addr, a); 4091 trace_output_32 (sd, addr); 4092 } 4093 4094 /* stord. */ 4095 void 4096 OP_31A_A (SIM_DESC sd, SIM_CPU *cpu) 4097 { 4098 uint32_t a = GPR32 (OP[0]); 4099 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4100 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISP14, OP_VOID); 4101 SLW (addr, a); 4102 trace_output_32 (sd, addr); 4103 } 4104 4105 /* stord. */ 4106 void 4107 OP_198_14 (SIM_DESC sd, SIM_CPU *cpu) 4108 { 4109 uint32_t a = GPR32 (OP[0]); 4110 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4111 trace_input ("stord", OP_REGP, OP_R_BASE_DISPE20, OP_VOID); 4112 SLW (addr, a); 4113 trace_output_32 (sd, addr); 4114 } 4115 4116 /* stord. */ 4117 void 4118 OP_138_14 (SIM_DESC sd, SIM_CPU *cpu) 4119 { 4120 uint32_t a = GPR32 (OP[0]); 4121 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4122 trace_input ("stord", OP_REGP, OP_R_BASE_DISPS20, OP_VOID); 4123 SLW (addr, a); 4124 trace_output_32 (sd, addr); 4125 } 4126 4127 /* stord. */ 4128 void 4129 OP_EF_8 (SIM_DESC sd, SIM_CPU *cpu) 4130 { 4131 uint32_t a = GPR32 (OP[0]); 4132 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4133 trace_input ("stord", OP_REGP, OP_RP_BASE_DISP16, OP_VOID); 4134 SLW (addr, a); 4135 trace_output_32 (sd, addr); 4136 } 4137 4138 /* stord. */ 4139 void 4140 OP_139_14 (SIM_DESC sd, SIM_CPU *cpu) 4141 { 4142 uint32_t a = GPR32 (OP[0]); 4143 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4144 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPS20, OP_VOID); 4145 SLW (addr, a); 4146 trace_output_32 (sd, addr); 4147 } 4148 4149 /* stord. */ 4150 void 4151 OP_199_14 (SIM_DESC sd, SIM_CPU *cpu) 4152 { 4153 uint32_t a = GPR32 (OP[0]); 4154 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4155 trace_input ("stord", OP_REGP, OP_RP_BASE_DISPE20, OP_VOID); 4156 SLW (addr, a); 4157 trace_output_32 (sd, addr); 4158 } 4159 4160 /* stord. */ 4161 void 4162 OP_13A_14 (SIM_DESC sd, SIM_CPU *cpu) 4163 { 4164 uint32_t a = GPR32 (OP[0]); 4165 uint32_t addr = (GPR32 (OP[2])) + OP[1]; 4166 trace_input ("stord", OP_REGP, OP_RP_INDEX_DISPS20, OP_VOID); 4167 SLW (addr, a); 4168 trace_output_32 (sd, addr); 4169 } 4170 4171 /* macqu. */ 4172 void 4173 OP_14D_14 (SIM_DESC sd, SIM_CPU *cpu) 4174 { 4175 int32_t tmp; 4176 int16_t src1, src2; 4177 trace_input ("macuw", OP_REG, OP_REG, OP_REGP); 4178 src1 = GPR (OP[0]); 4179 src2 = GPR (OP[1]); 4180 tmp = src1 * src2; 4181 /*REVISIT FOR SATURATION and Q FORMAT. */ 4182 SET_GPR32 (OP[2], tmp); 4183 trace_output_32 (sd, tmp); 4184 } 4185 4186 /* macuw. */ 4187 void 4188 OP_14E_14 (SIM_DESC sd, SIM_CPU *cpu) 4189 { 4190 uint32_t tmp; 4191 uint16_t src1, src2; 4192 trace_input ("macuw", OP_REG, OP_REG, OP_REGP); 4193 src1 = GPR (OP[0]); 4194 src2 = GPR (OP[1]); 4195 tmp = src1 * src2; 4196 /*REVISIT FOR SATURATION. */ 4197 SET_GPR32 (OP[2], tmp); 4198 trace_output_32 (sd, tmp); 4199 } 4200 4201 /* macsw. */ 4202 void 4203 OP_14F_14 (SIM_DESC sd, SIM_CPU *cpu) 4204 { 4205 int32_t tmp; 4206 int16_t src1, src2; 4207 trace_input ("macsw", OP_REG, OP_REG, OP_REGP); 4208 src1 = GPR (OP[0]); 4209 src2 = GPR (OP[1]); 4210 tmp = src1 * src2; 4211 /*REVISIT FOR SATURATION. */ 4212 SET_GPR32 (OP[2], tmp); 4213 trace_output_32 (sd, tmp); 4214 } 4215 4216 4217 /* mulb. */ 4218 void 4219 OP_64_8 (SIM_DESC sd, SIM_CPU *cpu) 4220 { 4221 int16_t tmp; 4222 int8_t a = (OP[0]) & 0xff; 4223 int8_t b = (GPR (OP[1])) & 0xff; 4224 trace_input ("mulb", OP_CONSTANT4_1, OP_REG, OP_VOID); 4225 tmp = (a * b) & 0xff; 4226 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4227 trace_output_16 (sd, tmp); 4228 } 4229 4230 /* mulb. */ 4231 void 4232 OP_64B_C (SIM_DESC sd, SIM_CPU *cpu) 4233 { 4234 int16_t tmp; 4235 int8_t a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4236 trace_input ("mulb", OP_CONSTANT4, OP_REG, OP_VOID); 4237 tmp = (a * b) & 0xff; 4238 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4239 trace_output_16 (sd, tmp); 4240 } 4241 4242 4243 /* mulb. */ 4244 void 4245 OP_65_8 (SIM_DESC sd, SIM_CPU *cpu) 4246 { 4247 int16_t tmp; 4248 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4249 trace_input ("mulb", OP_REG, OP_REG, OP_VOID); 4250 tmp = (a * b) & 0xff; 4251 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4252 trace_output_16 (sd, tmp); 4253 } 4254 4255 4256 /* mulw. */ 4257 void 4258 OP_66_8 (SIM_DESC sd, SIM_CPU *cpu) 4259 { 4260 int32_t tmp; 4261 uint16_t a = OP[0]; 4262 int16_t b = (GPR (OP[1])); 4263 trace_input ("mulw", OP_CONSTANT4_1, OP_REG, OP_VOID); 4264 tmp = (a * b) & 0xffff; 4265 SET_GPR (OP[1], tmp); 4266 trace_output_32 (sd, tmp); 4267 } 4268 4269 /* mulw. */ 4270 void 4271 OP_66B_C (SIM_DESC sd, SIM_CPU *cpu) 4272 { 4273 int32_t tmp; 4274 int16_t a = OP[0], b = (GPR (OP[1])); 4275 trace_input ("mulw", OP_CONSTANT4, OP_REG, OP_VOID); 4276 tmp = (a * b) & 0xffff; 4277 SET_GPR (OP[1], tmp); 4278 trace_output_32 (sd, tmp); 4279 } 4280 4281 4282 /* mulw. */ 4283 void 4284 OP_67_8 (SIM_DESC sd, SIM_CPU *cpu) 4285 { 4286 int32_t tmp; 4287 int16_t a = (GPR (OP[0])), b = (GPR (OP[1])); 4288 trace_input ("mulw", OP_REG, OP_REG, OP_VOID); 4289 tmp = (a * b) & 0xffff; 4290 SET_GPR (OP[1], tmp); 4291 trace_output_32 (sd, tmp); 4292 } 4293 4294 4295 /* mulsb. */ 4296 void 4297 OP_B_8 (SIM_DESC sd, SIM_CPU *cpu) 4298 { 4299 int16_t tmp; 4300 int8_t a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4301 trace_input ("mulsb", OP_REG, OP_REG, OP_VOID); 4302 tmp = a * b; 4303 SET_GPR (OP[1], tmp); 4304 trace_output_32 (sd, tmp); 4305 } 4306 4307 /* mulsw. */ 4308 void 4309 OP_62_8 (SIM_DESC sd, SIM_CPU *cpu) 4310 { 4311 int32_t tmp; 4312 int16_t a = (GPR (OP[0])), b = (GPR (OP[1])); 4313 trace_input ("mulsw", OP_REG, OP_REGP, OP_VOID); 4314 tmp = a * b; 4315 SET_GPR32 (OP[1], tmp); 4316 trace_output_32 (sd, tmp); 4317 } 4318 4319 /* muluw. */ 4320 void 4321 OP_63_8 (SIM_DESC sd, SIM_CPU *cpu) 4322 { 4323 uint32_t tmp; 4324 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1])); 4325 trace_input ("muluw", OP_REG, OP_REGP, OP_VOID); 4326 tmp = a * b; 4327 SET_GPR32 (OP[1], tmp); 4328 trace_output_32 (sd, tmp); 4329 } 4330 4331 4332 /* nop. */ 4333 void 4334 OP_2C00_10 (SIM_DESC sd, SIM_CPU *cpu) 4335 { 4336 trace_input ("nop", OP_VOID, OP_VOID, OP_VOID); 4337 4338 #if 0 4339 ins_type_counters[ (int)State.ins_type ]--; /* don't count nops as normal instructions */ 4340 switch (State.ins_type) 4341 { 4342 default: 4343 ins_type_counters[ (int)INS_UNKNOWN ]++; 4344 break; 4345 4346 } 4347 EXCEPTION (SIM_SIGTRAP); 4348 #endif 4349 trace_output_void (sd); 4350 } 4351 4352 4353 /* orb. */ 4354 void 4355 OP_24_8 (SIM_DESC sd, SIM_CPU *cpu) 4356 { 4357 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4358 trace_input ("orb", OP_CONSTANT4, OP_REG, OP_VOID); 4359 tmp = a | b; 4360 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4361 trace_output_16 (sd, tmp); 4362 } 4363 4364 /* orb. */ 4365 void 4366 OP_24B_C (SIM_DESC sd, SIM_CPU *cpu) 4367 { 4368 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 4369 trace_input ("orb", OP_CONSTANT16, OP_REG, OP_VOID); 4370 tmp = a | b; 4371 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4372 trace_output_16 (sd, tmp); 4373 } 4374 4375 /* orb. */ 4376 void 4377 OP_25_8 (SIM_DESC sd, SIM_CPU *cpu) 4378 { 4379 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 4380 trace_input ("orb", OP_REG, OP_REG, OP_VOID); 4381 tmp = a | b; 4382 SET_GPR (OP[1], ((GPR (OP[1]) | tmp))); 4383 trace_output_16 (sd, tmp); 4384 } 4385 4386 /* orw. */ 4387 void 4388 OP_26_8 (SIM_DESC sd, SIM_CPU *cpu) 4389 { 4390 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1])); 4391 trace_input ("orw", OP_CONSTANT4, OP_REG, OP_VOID); 4392 tmp = a | b; 4393 SET_GPR (OP[1], tmp); 4394 trace_output_16 (sd, tmp); 4395 } 4396 4397 4398 /* orw. */ 4399 void 4400 OP_26B_C (SIM_DESC sd, SIM_CPU *cpu) 4401 { 4402 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1])); 4403 trace_input ("orw", OP_CONSTANT16, OP_REG, OP_VOID); 4404 tmp = a | b; 4405 SET_GPR (OP[1], tmp); 4406 trace_output_16 (sd, tmp); 4407 } 4408 4409 /* orw. */ 4410 void 4411 OP_27_8 (SIM_DESC sd, SIM_CPU *cpu) 4412 { 4413 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 4414 trace_input ("orw", OP_REG, OP_REG, OP_VOID); 4415 tmp = a | b; 4416 SET_GPR (OP[1], tmp); 4417 trace_output_16 (sd, tmp); 4418 } 4419 4420 4421 /* lshb. */ 4422 void 4423 OP_13_9 (SIM_DESC sd, SIM_CPU *cpu) 4424 { 4425 uint16_t a = OP[0]; 4426 uint16_t tmp, b = (GPR (OP[1])) & 0xFF; 4427 trace_input ("lshb", OP_CONSTANT4, OP_REG, OP_VOID); 4428 /* A positive count specifies a shift to the left; 4429 * A negative count specifies a shift to the right. */ 4430 if (sign_flag) 4431 tmp = b >> a; 4432 else 4433 tmp = b << a; 4434 4435 sign_flag = 0; /* Reset sign_flag. */ 4436 4437 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4438 trace_output_16 (sd, tmp); 4439 } 4440 4441 /* lshb. */ 4442 void 4443 OP_44_8 (SIM_DESC sd, SIM_CPU *cpu) 4444 { 4445 uint16_t a = (GPR (OP[0])) & 0xff; 4446 uint16_t tmp, b = (GPR (OP[1])) & 0xFF; 4447 trace_input ("lshb", OP_REG, OP_REG, OP_VOID); 4448 if (a & ((long)1 << 3)) 4449 { 4450 sign_flag = 1; 4451 a = ~(a) + 1; 4452 } 4453 a = (unsigned int) (a & 0x7); 4454 4455 /* A positive count specifies a shift to the left; 4456 * A negative count specifies a shift to the right. */ 4457 if (sign_flag) 4458 tmp = b >> a; 4459 else 4460 tmp = b << a; 4461 4462 sign_flag = 0; /* Reset sign_flag. */ 4463 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4464 trace_output_16 (sd, tmp); 4465 } 4466 4467 /* lshw. */ 4468 void 4469 OP_46_8 (SIM_DESC sd, SIM_CPU *cpu) 4470 { 4471 uint16_t tmp, b = GPR (OP[1]); 4472 int16_t a = GPR (OP[0]); 4473 trace_input ("lshw", OP_REG, OP_REG, OP_VOID); 4474 if (a & ((long)1 << 4)) 4475 { 4476 sign_flag = 1; 4477 a = ~(a) + 1; 4478 } 4479 a = (unsigned int) (a & 0xf); 4480 4481 /* A positive count specifies a shift to the left; 4482 * A negative count specifies a shift to the right. */ 4483 if (sign_flag) 4484 tmp = b >> a; 4485 else 4486 tmp = b << a; 4487 4488 sign_flag = 0; /* Reset sign_flag. */ 4489 SET_GPR (OP[1], (tmp & 0xffff)); 4490 trace_output_16 (sd, tmp); 4491 } 4492 4493 /* lshw. */ 4494 void 4495 OP_49_8 (SIM_DESC sd, SIM_CPU *cpu) 4496 { 4497 uint16_t tmp, b = GPR (OP[1]); 4498 uint16_t a = OP[0]; 4499 trace_input ("lshw", OP_CONSTANT5, OP_REG, OP_VOID); 4500 /* A positive count specifies a shift to the left; 4501 * A negative count specifies a shift to the right. */ 4502 if (sign_flag) 4503 tmp = b >> a; 4504 else 4505 tmp = b << a; 4506 4507 sign_flag = 0; /* Reset sign_flag. */ 4508 SET_GPR (OP[1], (tmp & 0xffff)); 4509 trace_output_16 (sd, tmp); 4510 } 4511 4512 /* lshd. */ 4513 void 4514 OP_25_7 (SIM_DESC sd, SIM_CPU *cpu) 4515 { 4516 uint32_t tmp, b = GPR32 (OP[1]); 4517 uint16_t a = OP[0]; 4518 trace_input ("lshd", OP_CONSTANT6, OP_REGP, OP_VOID); 4519 /* A positive count specifies a shift to the left; 4520 * A negative count specifies a shift to the right. */ 4521 if (sign_flag) 4522 tmp = b >> a; 4523 else 4524 tmp = b << a; 4525 4526 sign_flag = 0; /* Reset sign flag. */ 4527 4528 SET_GPR32 (OP[1], tmp); 4529 trace_output_32 (sd, tmp); 4530 } 4531 4532 /* lshd. */ 4533 void 4534 OP_47_8 (SIM_DESC sd, SIM_CPU *cpu) 4535 { 4536 uint32_t tmp, b = GPR32 (OP[1]); 4537 uint16_t a = GPR (OP[0]); 4538 trace_input ("lshd", OP_REG, OP_REGP, OP_VOID); 4539 if (a & ((long)1 << 5)) 4540 { 4541 sign_flag = 1; 4542 a = ~(a) + 1; 4543 } 4544 a = (unsigned int) (a & 0x1f); 4545 /* A positive count specifies a shift to the left; 4546 * A negative count specifies a shift to the right. */ 4547 if (sign_flag) 4548 tmp = b >> a; 4549 else 4550 tmp = b << a; 4551 4552 sign_flag = 0; /* Reset sign flag. */ 4553 4554 SET_GPR32 (OP[1], tmp); 4555 trace_output_32 (sd, tmp); 4556 } 4557 4558 /* ashub. */ 4559 void 4560 OP_80_9 (SIM_DESC sd, SIM_CPU *cpu) 4561 { 4562 uint16_t a = OP[0]; 4563 int8_t tmp, b = (GPR (OP[1])) & 0xFF; 4564 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); 4565 /* A positive count specifies a shift to the left; 4566 * A negative count specifies a shift to the right. */ 4567 if (sign_flag) 4568 tmp = b >> a; 4569 else 4570 tmp = b << a; 4571 4572 sign_flag = 0; /* Reset sign flag. */ 4573 4574 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xff00))); 4575 trace_output_16 (sd, tmp); 4576 } 4577 4578 /* ashub. */ 4579 void 4580 OP_81_9 (SIM_DESC sd, SIM_CPU *cpu) 4581 { 4582 uint16_t a = OP[0]; 4583 int8_t tmp, b = (GPR (OP[1])) & 0xFF; 4584 trace_input ("ashub", OP_CONSTANT4, OP_REG, OP_VOID); 4585 /* A positive count specifies a shift to the left; 4586 * A negative count specifies a shift to the right. */ 4587 if (sign_flag) 4588 tmp = b >> a; 4589 else 4590 tmp = b << a; 4591 4592 sign_flag = 0; /* Reset sign flag. */ 4593 4594 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4595 trace_output_16 (sd, tmp); 4596 } 4597 4598 4599 /* ashub. */ 4600 void 4601 OP_41_8 (SIM_DESC sd, SIM_CPU *cpu) 4602 { 4603 int16_t a = (GPR (OP[0])); 4604 int8_t tmp, b = (GPR (OP[1])) & 0xFF; 4605 trace_input ("ashub", OP_REG, OP_REG, OP_VOID); 4606 4607 if (a & ((long)1 << 3)) 4608 { 4609 sign_flag = 1; 4610 a = ~(a) + 1; 4611 } 4612 a = (unsigned int) (a & 0x7); 4613 4614 /* A positive count specifies a shift to the left; 4615 * A negative count specifies a shift to the right. */ 4616 if (sign_flag) 4617 tmp = b >> a; 4618 else 4619 tmp = b << a; 4620 4621 sign_flag = 0; /* Reset sign flag. */ 4622 4623 SET_GPR (OP[1], ((tmp & 0xFF) | ((GPR (OP[1])) & 0xFF00))); 4624 trace_output_16 (sd, tmp); 4625 } 4626 4627 4628 /* ashuw. */ 4629 void 4630 OP_42_8 (SIM_DESC sd, SIM_CPU *cpu) 4631 { 4632 int16_t tmp, b = GPR (OP[1]); 4633 uint16_t a = OP[0]; 4634 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); 4635 /* A positive count specifies a shift to the left; 4636 * A negative count specifies a shift to the right. */ 4637 if (sign_flag) 4638 tmp = b >> a; 4639 else 4640 tmp = b << a; 4641 4642 sign_flag = 0; /* Reset sign flag. */ 4643 4644 SET_GPR (OP[1], (tmp & 0xffff)); 4645 trace_output_16 (sd, tmp); 4646 } 4647 4648 /* ashuw. */ 4649 void 4650 OP_43_8 (SIM_DESC sd, SIM_CPU *cpu) 4651 { 4652 int16_t tmp, b = GPR (OP[1]); 4653 uint16_t a = OP[0]; 4654 trace_input ("ashuw", OP_CONSTANT5, OP_REG, OP_VOID); 4655 /* A positive count specifies a shift to the left; 4656 * A negative count specifies a shift to the right. */ 4657 if (sign_flag) 4658 tmp = b >> a; 4659 else 4660 tmp = b << a; 4661 4662 sign_flag = 0; /* Reset sign flag. */ 4663 SET_GPR (OP[1], (tmp & 0xffff)); 4664 trace_output_16 (sd, tmp); 4665 } 4666 4667 /* ashuw. */ 4668 void 4669 OP_45_8 (SIM_DESC sd, SIM_CPU *cpu) 4670 { 4671 int16_t tmp; 4672 int16_t a = GPR (OP[0]), b = GPR (OP[1]); 4673 trace_input ("ashuw", OP_REG, OP_REG, OP_VOID); 4674 4675 if (a & ((long)1 << 4)) 4676 { 4677 sign_flag = 1; 4678 a = ~(a) + 1; 4679 } 4680 a = (unsigned int) (a & 0xf); 4681 /* A positive count specifies a shift to the left; 4682 * A negative count specifies a shift to the right. */ 4683 4684 if (sign_flag) 4685 tmp = b >> a; 4686 else 4687 tmp = b << a; 4688 4689 sign_flag = 0; /* Reset sign flag. */ 4690 SET_GPR (OP[1], (tmp & 0xffff)); 4691 trace_output_16 (sd, tmp); 4692 } 4693 4694 /* ashud. */ 4695 void 4696 OP_26_7 (SIM_DESC sd, SIM_CPU *cpu) 4697 { 4698 int32_t tmp,b = GPR32 (OP[1]); 4699 uint32_t a = OP[0]; 4700 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); 4701 /* A positive count specifies a shift to the left; 4702 * A negative count specifies a shift to the right. */ 4703 if (sign_flag) 4704 tmp = b >> a; 4705 else 4706 tmp = b << a; 4707 4708 sign_flag = 0; /* Reset sign flag. */ 4709 SET_GPR32 (OP[1], tmp); 4710 trace_output_32 (sd, tmp); 4711 } 4712 4713 /* ashud. */ 4714 void 4715 OP_27_7 (SIM_DESC sd, SIM_CPU *cpu) 4716 { 4717 int32_t tmp; 4718 int32_t a = OP[0], b = GPR32 (OP[1]); 4719 trace_input ("ashud", OP_CONSTANT6, OP_REGP, OP_VOID); 4720 /* A positive count specifies a shift to the left; 4721 * A negative count specifies a shift to the right. */ 4722 if (sign_flag) 4723 tmp = b >> a; 4724 else 4725 tmp = b << a; 4726 4727 sign_flag = 0; /* Reset sign flag. */ 4728 SET_GPR32 (OP[1], tmp); 4729 trace_output_32 (sd, tmp); 4730 } 4731 4732 /* ashud. */ 4733 void 4734 OP_48_8 (SIM_DESC sd, SIM_CPU *cpu) 4735 { 4736 int32_t tmp; 4737 int32_t a = GPR32 (OP[0]), b = GPR32 (OP[1]); 4738 trace_input ("ashud", OP_REGP, OP_REGP, OP_VOID); 4739 4740 if (a & ((long)1 << 5)) 4741 { 4742 sign_flag = 1; 4743 a = ~(a) + 1; 4744 } 4745 a = (unsigned int) (a & 0x1f); 4746 /* A positive count specifies a shift to the left; 4747 * A negative count specifies a shift to the right. */ 4748 if (sign_flag) 4749 tmp = b >> a; 4750 else 4751 tmp = b << a; 4752 4753 sign_flag = 0; /* Reset sign flag. */ 4754 SET_GPR32 (OP[1], tmp); 4755 trace_output_32 (sd, tmp); 4756 } 4757 4758 4759 /* storm. */ 4760 void 4761 OP_16_D (SIM_DESC sd, SIM_CPU *cpu) 4762 { 4763 uint32_t addr = GPR (1); 4764 uint16_t count = OP[0], reg = 2; 4765 trace_input ("storm", OP_CONSTANT4, OP_VOID, OP_VOID); 4766 if ((addr & 1)) 4767 { 4768 trace_output_void (sd); 4769 EXCEPTION (SIM_SIGBUS); 4770 } 4771 4772 while (count) 4773 { 4774 SW (addr, (GPR (reg))); 4775 addr +=2; 4776 --count; 4777 reg++; 4778 if (reg == 6) reg = 8; 4779 }; 4780 4781 SET_GPR (1, addr); 4782 4783 trace_output_void (sd); 4784 } 4785 4786 4787 /* stormp. */ 4788 void 4789 OP_17_D (SIM_DESC sd, SIM_CPU *cpu) 4790 { 4791 uint32_t addr = GPR32 (6); 4792 uint16_t count = OP[0], reg = 2; 4793 trace_input ("stormp", OP_CONSTANT4, OP_VOID, OP_VOID); 4794 if ((addr & 1)) 4795 { 4796 trace_output_void (sd); 4797 EXCEPTION (SIM_SIGBUS); 4798 } 4799 4800 while (count) 4801 { 4802 SW (addr, (GPR (reg))); 4803 addr +=2; 4804 --count; 4805 reg++; 4806 if (reg == 6) reg = 8; 4807 }; 4808 4809 SET_GPR32 (6, addr); 4810 trace_output_void (sd); 4811 } 4812 4813 /* subb. */ 4814 void 4815 OP_38_8 (SIM_DESC sd, SIM_CPU *cpu) 4816 { 4817 uint8_t a = OP[0]; 4818 uint8_t b = (GPR (OP[1])) & 0xff; 4819 uint16_t tmp = (~a + 1 + b) & 0xff; 4820 trace_input ("subb", OP_CONSTANT4, OP_REG, OP_VOID); 4821 /* see ../common/sim-alu.h for a more extensive discussion on how to 4822 compute the carry/overflow bits. */ 4823 SET_PSR_C (tmp > 0xff); 4824 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4825 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4826 trace_output_16 (sd, tmp); 4827 } 4828 4829 /* subb. */ 4830 void 4831 OP_38B_C (SIM_DESC sd, SIM_CPU *cpu) 4832 { 4833 uint8_t a = OP[0] & 0xFF; 4834 uint8_t b = (GPR (OP[1])) & 0xFF; 4835 uint16_t tmp = (~a + 1 + b) & 0xFF; 4836 trace_input ("subb", OP_CONSTANT16, OP_REG, OP_VOID); 4837 /* see ../common/sim-alu.h for a more extensive discussion on how to 4838 compute the carry/overflow bits. */ 4839 SET_PSR_C (tmp > 0xff); 4840 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4841 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4842 trace_output_16 (sd, tmp); 4843 } 4844 4845 /* subb. */ 4846 void 4847 OP_39_8 (SIM_DESC sd, SIM_CPU *cpu) 4848 { 4849 uint8_t a = (GPR (OP[0])) & 0xFF; 4850 uint8_t b = (GPR (OP[1])) & 0xFF; 4851 uint16_t tmp = (~a + 1 + b) & 0xff; 4852 trace_input ("subb", OP_REG, OP_REG, OP_VOID); 4853 /* see ../common/sim-alu.h for a more extensive discussion on how to 4854 compute the carry/overflow bits. */ 4855 SET_PSR_C (tmp > 0xff); 4856 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4857 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 4858 trace_output_16 (sd, tmp); 4859 } 4860 4861 /* subw. */ 4862 void 4863 OP_3A_8 (SIM_DESC sd, SIM_CPU *cpu) 4864 { 4865 uint16_t a = OP[0]; 4866 uint16_t b = GPR (OP[1]); 4867 uint16_t tmp = (~a + 1 + b); 4868 trace_input ("subw", OP_CONSTANT4, OP_REG, OP_VOID); 4869 /* see ../common/sim-alu.h for a more extensive discussion on how to 4870 compute the carry/overflow bits. */ 4871 SET_PSR_C (tmp > 0xffff); 4872 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4873 SET_GPR (OP[1], tmp); 4874 trace_output_16 (sd, tmp); 4875 } 4876 4877 /* subw. */ 4878 void 4879 OP_3AB_C (SIM_DESC sd, SIM_CPU *cpu) 4880 { 4881 uint16_t a = OP[0]; 4882 uint16_t b = GPR (OP[1]); 4883 uint32_t tmp = (~a + 1 + b); 4884 trace_input ("subw", OP_CONSTANT16, OP_REG, OP_VOID); 4885 /* see ../common/sim-alu.h for a more extensive discussion on how to 4886 compute the carry/overflow bits. */ 4887 SET_PSR_C (tmp > 0xffff); 4888 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4889 SET_GPR (OP[1], tmp & 0xffff); 4890 trace_output_16 (sd, tmp); 4891 } 4892 4893 /* subw. */ 4894 void 4895 OP_3B_8 (SIM_DESC sd, SIM_CPU *cpu) 4896 { 4897 uint16_t a = GPR (OP[0]); 4898 uint16_t b = GPR (OP[1]); 4899 uint32_t tmp = (~a + 1 + b); 4900 trace_input ("subw", OP_REG, OP_REG, OP_VOID); 4901 /* see ../common/sim-alu.h for a more extensive discussion on how to 4902 compute the carry/overflow bits. */ 4903 SET_PSR_C (tmp > 0xffff); 4904 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4905 SET_GPR (OP[1], tmp & 0xffff); 4906 trace_output_16 (sd, tmp); 4907 } 4908 4909 /* subcb. */ 4910 void 4911 OP_3C_8 (SIM_DESC sd, SIM_CPU *cpu) 4912 { 4913 uint8_t a = OP[0]; 4914 uint8_t b = (GPR (OP[1])) & 0xff; 4915 //uint16_t tmp1 = a + 1; 4916 uint16_t tmp1 = a + (PSR_C); 4917 uint16_t tmp = (~tmp1 + 1 + b); 4918 trace_input ("subcb", OP_CONSTANT4, OP_REG, OP_VOID); 4919 /* see ../common/sim-alu.h for a more extensive discussion on how to 4920 compute the carry/overflow bits. */ 4921 SET_PSR_C (tmp > 0xff); 4922 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4923 SET_GPR (OP[1], tmp); 4924 trace_output_16 (sd, tmp); 4925 } 4926 4927 /* subcb. */ 4928 void 4929 OP_3CB_C (SIM_DESC sd, SIM_CPU *cpu) 4930 { 4931 uint16_t a = OP[0]; 4932 uint16_t b = (GPR (OP[1])) & 0xff; 4933 //uint16_t tmp1 = a + 1; 4934 uint16_t tmp1 = a + (PSR_C); 4935 uint16_t tmp = (~tmp1 + 1 + b); 4936 trace_input ("subcb", OP_CONSTANT16, OP_REG, OP_VOID); 4937 /* see ../common/sim-alu.h for a more extensive discussion on how to 4938 compute the carry/overflow bits. */ 4939 SET_PSR_C (tmp > 0xff); 4940 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4941 SET_GPR (OP[1], tmp); 4942 trace_output_16 (sd, tmp); 4943 } 4944 4945 /* subcb. */ 4946 void 4947 OP_3D_8 (SIM_DESC sd, SIM_CPU *cpu) 4948 { 4949 uint16_t a = (GPR (OP[0])) & 0xff; 4950 uint16_t b = (GPR (OP[1])) & 0xff; 4951 uint16_t tmp1 = a + (PSR_C); 4952 uint16_t tmp = (~tmp1 + 1 + b); 4953 trace_input ("subcb", OP_REG, OP_REG, OP_VOID); 4954 /* see ../common/sim-alu.h for a more extensive discussion on how to 4955 compute the carry/overflow bits. */ 4956 SET_PSR_C (tmp > 0xff); 4957 SET_PSR_F (((a & 0x80) != (b & 0x80)) && ((b & 0x80) != (tmp & 0x80))); 4958 SET_GPR (OP[1], tmp); 4959 trace_output_16 (sd, tmp); 4960 } 4961 4962 /* subcw. */ 4963 void 4964 OP_3E_8 (SIM_DESC sd, SIM_CPU *cpu) 4965 { 4966 uint16_t a = OP[0], b = (GPR (OP[1])); 4967 uint16_t tmp1 = a + (PSR_C); 4968 uint16_t tmp = (~tmp1 + 1 + b); 4969 trace_input ("subcw", OP_CONSTANT4, OP_REG, OP_VOID); 4970 /* see ../common/sim-alu.h for a more extensive discussion on how to 4971 compute the carry/overflow bits. */ 4972 SET_PSR_C (tmp > 0xffff); 4973 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4974 SET_GPR (OP[1], tmp); 4975 trace_output_16 (sd, tmp); 4976 } 4977 4978 /* subcw. */ 4979 void 4980 OP_3EB_C (SIM_DESC sd, SIM_CPU *cpu) 4981 { 4982 int16_t a = OP[0]; 4983 uint16_t b = GPR (OP[1]); 4984 uint16_t tmp1 = a + (PSR_C); 4985 uint16_t tmp = (~tmp1 + 1 + b); 4986 trace_input ("subcw", OP_CONSTANT16, OP_REG, OP_VOID); 4987 /* see ../common/sim-alu.h for a more extensive discussion on how to 4988 compute the carry/overflow bits. */ 4989 SET_PSR_C (tmp > 0xffff); 4990 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 4991 SET_GPR (OP[1], tmp); 4992 trace_output_16 (sd, tmp); 4993 } 4994 4995 /* subcw. */ 4996 void 4997 OP_3F_8 (SIM_DESC sd, SIM_CPU *cpu) 4998 { 4999 uint16_t a = (GPR (OP[0])), b = (GPR (OP[1])); 5000 uint16_t tmp1 = a + (PSR_C); 5001 uint16_t tmp = (~tmp1 + 1 + b); 5002 trace_input ("subcw", OP_REG, OP_REG, OP_VOID); 5003 /* see ../common/sim-alu.h for a more extensive discussion on how to 5004 compute the carry/overflow bits. */ 5005 SET_PSR_C (tmp > 0xffff); 5006 SET_PSR_F (((a & 0x8000) != (b & 0x8000)) && ((b & 0x8000) != (tmp & 0x8000))); 5007 SET_GPR (OP[1], tmp); 5008 trace_output_16 (sd, tmp); 5009 } 5010 5011 /* subd. */ 5012 void 5013 OP_3_C (SIM_DESC sd, SIM_CPU *cpu) 5014 { 5015 int32_t a = OP[0]; 5016 uint32_t b = GPR32 (OP[1]); 5017 uint32_t tmp = (~a + 1 + b); 5018 trace_input ("subd", OP_CONSTANT32, OP_REGP, OP_VOID); 5019 /* see ../common/sim-alu.h for a more extensive discussion on how to 5020 compute the carry/overflow bits. */ 5021 SET_PSR_C (tmp > 0xffffffff); 5022 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && 5023 ((b & 0x80000000) != (tmp & 0x80000000))); 5024 SET_GPR32 (OP[1], tmp); 5025 trace_output_32 (sd, tmp); 5026 } 5027 5028 /* subd. */ 5029 void 5030 OP_14C_14 (SIM_DESC sd, SIM_CPU *cpu) 5031 { 5032 uint32_t a = GPR32 (OP[0]); 5033 uint32_t b = GPR32 (OP[1]); 5034 uint32_t tmp = (~a + 1 + b); 5035 trace_input ("subd", OP_REGP, OP_REGP, OP_VOID); 5036 /* see ../common/sim-alu.h for a more extensive discussion on how to 5037 compute the carry/overflow bits. */ 5038 SET_PSR_C (tmp > 0xffffffff); 5039 SET_PSR_F (((a & 0x80000000) != (b & 0x80000000)) && 5040 ((b & 0x80000000) != (tmp & 0x80000000))); 5041 SET_GPR32 (OP[1], tmp); 5042 trace_output_32 (sd, tmp); 5043 } 5044 5045 /* excp. */ 5046 void 5047 OP_C_C (SIM_DESC sd, SIM_CPU *cpu) 5048 { 5049 host_callback *cb = STATE_CALLBACK (sd); 5050 uint32_t tmp; 5051 uint16_t a; 5052 trace_input ("excp", OP_CONSTANT4, OP_VOID, OP_VOID); 5053 switch (OP[0]) 5054 { 5055 default: 5056 #if (DEBUG & DEBUG_TRAP) == 0 5057 { 5058 #if 0 5059 uint16_t vec = OP[0] + TRAP_VECTOR_START; 5060 SET_BPC (PC + 1); 5061 SET_BPSR (PSR); 5062 SET_PSR (PSR & PSR_SM_BIT); 5063 JMP (vec); 5064 break; 5065 #endif 5066 } 5067 #else /* if debugging use trap to print registers */ 5068 { 5069 int i; 5070 static int first_time = 1; 5071 5072 if (first_time) 5073 { 5074 first_time = 0; 5075 sim_io_printf (sd, "Trap # PC "); 5076 for (i = 0; i < 16; i++) 5077 sim_io_printf (sd, " %sr%d", (i > 9) ? "" : " ", i); 5078 sim_io_printf (sd, " a0 a1 f0 f1 c\n"); 5079 } 5080 5081 sim_io_printf (sd, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC); 5082 5083 for (i = 0; i < 16; i++) 5084 sim_io_printf (sd, " %.4x", (int) GPR (i)); 5085 5086 for (i = 0; i < 2; i++) 5087 sim_io_printf (sd, " %.2x%.8lx", 5088 ((int)(ACC (i) >> 32) & 0xff), 5089 ((unsigned long) ACC (i)) & 0xffffffff); 5090 5091 sim_io_printf (sd, " %d %d %d\n", 5092 PSR_F != 0, PSR_F != 0, PSR_C != 0); 5093 sim_io_flush_stdout (sd); 5094 break; 5095 } 5096 #endif 5097 case 8: /* new system call trap */ 5098 /* Trap 8 is used for simulating low-level I/O */ 5099 { 5100 uint32_t result = 0; 5101 errno = 0; 5102 5103 /* Registers passed to trap 0. */ 5104 5105 #define FUNC GPR (0) /* function number. */ 5106 #define PARM1 GPR (2) /* optional parm 1. */ 5107 #define PARM2 GPR (3) /* optional parm 2. */ 5108 #define PARM3 GPR (4) /* optional parm 3. */ 5109 #define PARM4 GPR (5) /* optional parm 4. */ 5110 5111 /* Registers set by trap 0 */ 5112 5113 #define RETVAL(X) do { result = (0xffff & (X));SET_GPR (0, result);} while (0) 5114 #define RETVAL32(X) do { result = (X); SET_GPR32 (0, result);} while (0) 5115 #define RETERR(X) SET_GPR (4, (X)) /* return error code. */ 5116 5117 /* Turn a pointer in a register into a pointer into real memory. */ 5118 5119 #define MEMPTR(x) sim_core_trans_addr (sd, cpu, read_map, x) 5120 5121 switch (FUNC) 5122 { 5123 #if !defined(__GO32__) && !defined(_WIN32) 5124 case TARGET_NEWLIB_CR16_SYS_fork: 5125 trace_input ("<fork>", OP_VOID, OP_VOID, OP_VOID); 5126 RETVAL (fork ()); 5127 trace_output_16 (sd, result); 5128 break; 5129 5130 #define getpid() 47 5131 case TARGET_NEWLIB_CR16_SYS_getpid: 5132 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 5133 RETVAL (getpid ()); 5134 trace_output_16 (sd, result); 5135 break; 5136 5137 case TARGET_NEWLIB_CR16_SYS_kill: 5138 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); 5139 if (PARM1 == getpid ()) 5140 { 5141 trace_output_void (sd); 5142 EXCEPTION (PARM2); 5143 } 5144 else 5145 { 5146 int os_sig = -1; 5147 switch (PARM2) 5148 { 5149 #ifdef SIGHUP 5150 case 1: os_sig = SIGHUP; break; 5151 #endif 5152 #ifdef SIGINT 5153 case 2: os_sig = SIGINT; break; 5154 #endif 5155 #ifdef SIGQUIT 5156 case 3: os_sig = SIGQUIT; break; 5157 #endif 5158 #ifdef SIGILL 5159 case 4: os_sig = SIGILL; break; 5160 #endif 5161 #ifdef SIGTRAP 5162 case 5: os_sig = SIGTRAP; break; 5163 #endif 5164 #ifdef SIGABRT 5165 case 6: os_sig = SIGABRT; break; 5166 #elif defined(SIGIOT) 5167 case 6: os_sig = SIGIOT; break; 5168 #endif 5169 #ifdef SIGEMT 5170 case 7: os_sig = SIGEMT; break; 5171 #endif 5172 #ifdef SIGFPE 5173 case 8: os_sig = SIGFPE; break; 5174 #endif 5175 #ifdef SIGKILL 5176 case 9: os_sig = SIGKILL; break; 5177 #endif 5178 #ifdef SIGBUS 5179 case 10: os_sig = SIGBUS; break; 5180 #endif 5181 #ifdef SIGSEGV 5182 case 11: os_sig = SIGSEGV; break; 5183 #endif 5184 #ifdef SIGSYS 5185 case 12: os_sig = SIGSYS; break; 5186 #endif 5187 #ifdef SIGPIPE 5188 case 13: os_sig = SIGPIPE; break; 5189 #endif 5190 #ifdef SIGALRM 5191 case 14: os_sig = SIGALRM; break; 5192 #endif 5193 #ifdef SIGTERM 5194 case 15: os_sig = SIGTERM; break; 5195 #endif 5196 #ifdef SIGURG 5197 case 16: os_sig = SIGURG; break; 5198 #endif 5199 #ifdef SIGSTOP 5200 case 17: os_sig = SIGSTOP; break; 5201 #endif 5202 #ifdef SIGTSTP 5203 case 18: os_sig = SIGTSTP; break; 5204 #endif 5205 #ifdef SIGCONT 5206 case 19: os_sig = SIGCONT; break; 5207 #endif 5208 #ifdef SIGCHLD 5209 case 20: os_sig = SIGCHLD; break; 5210 #elif defined(SIGCLD) 5211 case 20: os_sig = SIGCLD; break; 5212 #endif 5213 #ifdef SIGTTIN 5214 case 21: os_sig = SIGTTIN; break; 5215 #endif 5216 #ifdef SIGTTOU 5217 case 22: os_sig = SIGTTOU; break; 5218 #endif 5219 #ifdef SIGIO 5220 case 23: os_sig = SIGIO; break; 5221 #elif defined (SIGPOLL) 5222 case 23: os_sig = SIGPOLL; break; 5223 #endif 5224 #ifdef SIGXCPU 5225 case 24: os_sig = SIGXCPU; break; 5226 #endif 5227 #ifdef SIGXFSZ 5228 case 25: os_sig = SIGXFSZ; break; 5229 #endif 5230 #ifdef SIGVTALRM 5231 case 26: os_sig = SIGVTALRM; break; 5232 #endif 5233 #ifdef SIGPROF 5234 case 27: os_sig = SIGPROF; break; 5235 #endif 5236 #ifdef SIGWINCH 5237 case 28: os_sig = SIGWINCH; break; 5238 #endif 5239 #ifdef SIGLOST 5240 case 29: os_sig = SIGLOST; break; 5241 #endif 5242 #ifdef SIGUSR1 5243 case 30: os_sig = SIGUSR1; break; 5244 #endif 5245 #ifdef SIGUSR2 5246 case 31: os_sig = SIGUSR2; break; 5247 #endif 5248 } 5249 5250 if (os_sig == -1) 5251 { 5252 trace_output_void (sd); 5253 sim_io_printf (sd, "Unknown signal %d\n", PARM2); 5254 sim_io_flush_stdout (sd); 5255 EXCEPTION (SIM_SIGILL); 5256 } 5257 else 5258 { 5259 RETVAL (kill (PARM1, PARM2)); 5260 trace_output_16 (sd, result); 5261 } 5262 } 5263 break; 5264 5265 case TARGET_NEWLIB_CR16_SYS_execve: 5266 trace_input ("<execve>", OP_VOID, OP_VOID, OP_VOID); 5267 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2<<16|PARM3), 5268 (char **)MEMPTR (PARM4))); 5269 trace_output_16 (sd, result); 5270 break; 5271 5272 case TARGET_NEWLIB_CR16_SYS_execv: 5273 trace_input ("<execv>", OP_VOID, OP_VOID, OP_VOID); 5274 RETVAL (execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL)); 5275 trace_output_16 (sd, result); 5276 break; 5277 5278 case TARGET_NEWLIB_CR16_SYS_pipe: 5279 { 5280 reg_t buf; 5281 int host_fd[2]; 5282 5283 trace_input ("<pipe>", OP_VOID, OP_VOID, OP_VOID); 5284 buf = PARM1; 5285 RETVAL (pipe (host_fd)); 5286 SW (buf, host_fd[0]); 5287 buf += sizeof(uint16_t); 5288 SW (buf, host_fd[1]); 5289 trace_output_16 (sd, result); 5290 } 5291 break; 5292 5293 case TARGET_NEWLIB_CR16_SYS_wait: 5294 { 5295 int status; 5296 trace_input ("<wait>", OP_REG, OP_VOID, OP_VOID); 5297 RETVAL (wait (&status)); 5298 if (PARM1) 5299 SW (PARM1, status); 5300 trace_output_16 (sd, result); 5301 } 5302 break; 5303 #else 5304 case TARGET_NEWLIB_CR16_SYS_getpid: 5305 trace_input ("<getpid>", OP_VOID, OP_VOID, OP_VOID); 5306 RETVAL (1); 5307 trace_output_16 (sd, result); 5308 break; 5309 5310 case TARGET_NEWLIB_CR16_SYS_kill: 5311 trace_input ("<kill>", OP_REG, OP_REG, OP_VOID); 5312 trace_output_void (sd); 5313 EXCEPTION (PARM2); 5314 break; 5315 #endif 5316 5317 case TARGET_NEWLIB_CR16_SYS_read: 5318 trace_input ("<read>", OP_REG, OP_MEMREF, OP_REG); 5319 RETVAL (cb->read (cb, PARM1, 5320 MEMPTR (((unsigned long)PARM3 << 16) 5321 | ((unsigned long)PARM2)), PARM4)); 5322 trace_output_16 (sd, result); 5323 break; 5324 5325 case TARGET_NEWLIB_CR16_SYS_write: 5326 trace_input ("<write>", OP_REG, OP_MEMREF, OP_REG); 5327 RETVAL ((int)cb->write (cb, PARM1, 5328 MEMPTR (((unsigned long)PARM3 << 16) 5329 | PARM2), PARM4)); 5330 trace_output_16 (sd, result); 5331 break; 5332 5333 case TARGET_NEWLIB_CR16_SYS_lseek: 5334 trace_input ("<lseek>", OP_REG, OP_REGP, OP_REG); 5335 RETVAL32 (cb->lseek (cb, PARM1, ((((long) PARM3) << 16) | PARM2), 5336 PARM4)); 5337 trace_output_32 (sd, result); 5338 break; 5339 5340 case TARGET_NEWLIB_CR16_SYS_close: 5341 trace_input ("<close>", OP_REG, OP_VOID, OP_VOID); 5342 RETVAL (cb->close (cb, PARM1)); 5343 trace_output_16 (sd, result); 5344 break; 5345 5346 case TARGET_NEWLIB_CR16_SYS_open: 5347 trace_input ("<open>", OP_MEMREF, OP_REG, OP_VOID); 5348 RETVAL32 (cb->open (cb, MEMPTR ((((unsigned long)PARM2) << 16) 5349 | PARM1), PARM3)); 5350 trace_output_32 (sd, result); 5351 break; 5352 5353 case TARGET_NEWLIB_CR16_SYS_rename: 5354 trace_input ("<rename>", OP_MEMREF, OP_MEMREF, OP_VOID); 5355 RETVAL (cb->rename (cb, MEMPTR ((((unsigned long)PARM2) << 16) | PARM1), 5356 MEMPTR ((((unsigned long)PARM4) << 16) | PARM3))); 5357 trace_output_16 (sd, result); 5358 break; 5359 5360 case 0x408: /* REVISIT: Added a dummy getenv call. */ 5361 trace_input ("<getenv>", OP_MEMREF, OP_MEMREF, OP_VOID); 5362 RETVAL32 (0); 5363 trace_output_32 (sd, result); 5364 break; 5365 5366 case TARGET_NEWLIB_CR16_SYS_exit: 5367 trace_input ("<exit>", OP_VOID, OP_VOID, OP_VOID); 5368 trace_output_void (sd); 5369 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2)); 5370 break; 5371 5372 case TARGET_NEWLIB_CR16_SYS_unlink: 5373 trace_input ("<unlink>", OP_MEMREF, OP_VOID, OP_VOID); 5374 RETVAL (cb->unlink (cb, MEMPTR (((unsigned long)PARM2 << 16) | PARM1))); 5375 trace_output_16 (sd, result); 5376 break; 5377 5378 case TARGET_NEWLIB_CR16_SYS_stat: 5379 trace_input ("<stat>", OP_VOID, OP_VOID, OP_VOID); 5380 /* stat system call. */ 5381 { 5382 struct stat host_stat; 5383 reg_t buf; 5384 5385 RETVAL (stat (MEMPTR ((((unsigned long)PARM2) << 16)|PARM1), &host_stat)); 5386 5387 buf = PARM2; 5388 5389 /* The hard-coded offsets and sizes were determined by using 5390 * the CR16 compiler on a test program that used struct stat. 5391 */ 5392 SW (buf, host_stat.st_dev); 5393 SW (buf+2, host_stat.st_ino); 5394 SW (buf+4, host_stat.st_mode); 5395 SW (buf+6, host_stat.st_nlink); 5396 SW (buf+8, host_stat.st_uid); 5397 SW (buf+10, host_stat.st_gid); 5398 SW (buf+12, host_stat.st_rdev); 5399 SLW (buf+16, host_stat.st_size); 5400 SLW (buf+20, host_stat.st_atime); 5401 SLW (buf+28, host_stat.st_mtime); 5402 SLW (buf+36, host_stat.st_ctime); 5403 } 5404 trace_output_16 (sd, result); 5405 break; 5406 5407 case TARGET_NEWLIB_CR16_SYS_chown: 5408 trace_input ("<chown>", OP_VOID, OP_VOID, OP_VOID); 5409 RETVAL (chown (MEMPTR (PARM1), PARM2, PARM3)); 5410 trace_output_16 (sd, result); 5411 break; 5412 5413 case TARGET_NEWLIB_CR16_SYS_chmod: 5414 trace_input ("<chmod>", OP_VOID, OP_VOID, OP_VOID); 5415 RETVAL (chmod (MEMPTR (PARM1), PARM2)); 5416 trace_output_16 (sd, result); 5417 break; 5418 5419 case TARGET_NEWLIB_CR16_SYS_utime: 5420 trace_input ("<utime>", OP_REG, OP_REG, OP_REG); 5421 /* Cast the second argument to void *, to avoid type mismatch 5422 if a prototype is present. */ 5423 RETVAL (utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2))); 5424 trace_output_16 (sd, result); 5425 break; 5426 5427 case TARGET_NEWLIB_CR16_SYS_time: 5428 trace_input ("<time>", OP_VOID, OP_VOID, OP_REG); 5429 RETVAL32 (time (NULL)); 5430 trace_output_32 (sd, result); 5431 break; 5432 5433 default: 5434 a = OP[0]; 5435 switch (a) 5436 { 5437 case TRAP_BREAKPOINT: 5438 tmp = (PC); 5439 JMP(tmp); 5440 trace_output_void (sd); 5441 EXCEPTION (SIM_SIGTRAP); 5442 break; 5443 case SIGTRAP: /* supervisor call ? */ 5444 trace_output_void (sd); 5445 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, GPR (2)); 5446 break; 5447 default: 5448 cb->error (cb, "Unknown syscall %d", FUNC); 5449 break; 5450 } 5451 } 5452 if ((uint16_t) result == (uint16_t) -1) 5453 RETERR (cb->get_errno (cb)); 5454 else 5455 RETERR (0); 5456 break; 5457 } 5458 } 5459 } 5460 5461 5462 /* push. */ 5463 void 5464 OP_3_9 (SIM_DESC sd, SIM_CPU *cpu) 5465 { 5466 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5467 uint32_t tmp, sp_addr = (GPR32 (15)) - (a * 2) - 4, is_regp = 0; 5468 trace_input ("push", OP_CONSTANT3, OP_REG, OP_REG); 5469 5470 for (; i < a; ++i) 5471 { 5472 if ((b+i) <= 11) 5473 { 5474 SW (sp_addr, (GPR (b+i))); 5475 sp_addr +=2; 5476 } 5477 else 5478 { 5479 if (is_regp == 0) 5480 tmp = (GPR32 (b+i)); 5481 else 5482 tmp = (GPR32 (b+i-1)); 5483 5484 if ((a-i) > 1) 5485 { 5486 SLW (sp_addr, tmp); 5487 sp_addr +=4; 5488 } 5489 else 5490 { 5491 SW (sp_addr, tmp); 5492 sp_addr +=2; 5493 } 5494 ++i; 5495 is_regp = 1; 5496 } 5497 } 5498 5499 sp_addr +=4; 5500 5501 /* Store RA address. */ 5502 tmp = (GPR32 (14)); 5503 SLW(sp_addr,tmp); 5504 5505 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5506 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5507 5508 trace_output_void (sd); 5509 } 5510 5511 /* push. */ 5512 void 5513 OP_1_8 (SIM_DESC sd, SIM_CPU *cpu) 5514 { 5515 uint32_t sp_addr, tmp, is_regp = 0; 5516 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5517 trace_input ("push", OP_CONSTANT3, OP_REG, OP_VOID); 5518 5519 if (c == 1) 5520 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5521 else 5522 sp_addr = (GPR32 (15)) - (a * 2); 5523 5524 for (; i < a; ++i) 5525 { 5526 if ((b+i) <= 11) 5527 { 5528 SW (sp_addr, (GPR (b+i))); 5529 sp_addr +=2; 5530 } 5531 else 5532 { 5533 if (is_regp == 0) 5534 tmp = (GPR32 (b+i)); 5535 else 5536 tmp = (GPR32 (b+i-1)); 5537 5538 if ((a-i) > 1) 5539 { 5540 SLW (sp_addr, tmp); 5541 sp_addr +=4; 5542 } 5543 else 5544 { 5545 SW (sp_addr, tmp); 5546 sp_addr +=2; 5547 } 5548 ++i; 5549 is_regp = 1; 5550 } 5551 } 5552 5553 if (c == 1) 5554 { 5555 /* Store RA address. */ 5556 tmp = (GPR32 (14)); 5557 SLW(sp_addr,tmp); 5558 sp_addr = (GPR32 (15)) - (a * 2) - 4; 5559 } 5560 else 5561 sp_addr = (GPR32 (15)) - (a * 2); 5562 5563 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5564 5565 trace_output_void (sd); 5566 } 5567 5568 5569 /* push. */ 5570 void 5571 OP_11E_10 (SIM_DESC sd, SIM_CPU *cpu) 5572 { 5573 uint32_t sp_addr = (GPR32 (15)), tmp; 5574 trace_input ("push", OP_VOID, OP_VOID, OP_VOID); 5575 tmp = (GPR32 (14)); 5576 SLW(sp_addr-4,tmp); /* Store RA address. */ 5577 SET_GPR32 (15, (sp_addr - 4)); /* Update SP address. */ 5578 trace_output_void (sd); 5579 } 5580 5581 5582 /* pop. */ 5583 void 5584 OP_5_9 (SIM_DESC sd, SIM_CPU *cpu) 5585 { 5586 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5587 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0;; 5588 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_REG); 5589 5590 for (; i < a; ++i) 5591 { 5592 if ((b+i) <= 11) 5593 { 5594 SET_GPR ((b+i), RW(sp_addr)); 5595 sp_addr +=2; 5596 } 5597 else 5598 { 5599 if ((a-i) > 1) 5600 { 5601 tmp = RLW(sp_addr); 5602 sp_addr +=4; 5603 } 5604 else 5605 { 5606 tmp = RW(sp_addr); 5607 sp_addr +=2; 5608 5609 if (is_regp == 0) 5610 tmp = (tmp << 16) | (GPR32 (b+i)); 5611 else 5612 tmp = (tmp << 16) | (GPR32 (b+i-1)); 5613 } 5614 5615 if (is_regp == 0) 5616 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16) 5617 | ((tmp >> 16) & 0xffff))); 5618 else 5619 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16) 5620 | ((tmp >> 16) & 0xffff))); 5621 5622 ++i; 5623 is_regp = 1; 5624 } 5625 } 5626 5627 tmp = RLW(sp_addr); /* store RA also. */ 5628 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5629 5630 SET_GPR32 (15, (sp_addr + 4)); /* Update SP address. */ 5631 5632 trace_output_void (sd); 5633 } 5634 5635 /* pop. */ 5636 void 5637 OP_2_8 (SIM_DESC sd, SIM_CPU *cpu) 5638 { 5639 uint16_t a = OP[0] + 1, b = OP[1], c = OP[2], i = 0; 5640 uint32_t tmp, sp_addr = (GPR32 (15)), is_regp = 0; 5641 trace_input ("pop", OP_CONSTANT3, OP_REG, OP_VOID); 5642 5643 for (; i < a; ++i) 5644 { 5645 if ((b+i) <= 11) 5646 { 5647 SET_GPR ((b+i), RW(sp_addr)); 5648 sp_addr +=2; 5649 } 5650 else 5651 { 5652 if ((a-i) > 1) 5653 { 5654 tmp = RLW(sp_addr); 5655 sp_addr +=4; 5656 } 5657 else 5658 { 5659 tmp = RW(sp_addr); 5660 sp_addr +=2; 5661 5662 if (is_regp == 0) 5663 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i)); 5664 else 5665 tmp = ((tmp << 16) & 0xffffffff) | (GPR32 (b+i-1)); 5666 } 5667 5668 if (is_regp == 0) 5669 SET_GPR32 ((b+i), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5670 else 5671 SET_GPR32 ((b+i-1), (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5672 ++i; 5673 is_regp = 1; 5674 } 5675 } 5676 5677 if (c == 1) 5678 { 5679 tmp = RLW(sp_addr); /* Store RA Reg. */ 5680 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5681 sp_addr +=4; 5682 } 5683 5684 SET_GPR32 (15, sp_addr); /* Update SP address. */ 5685 5686 trace_output_void (sd); 5687 } 5688 5689 /* pop. */ 5690 void 5691 OP_21E_10 (SIM_DESC sd, SIM_CPU *cpu) 5692 { 5693 uint32_t sp_addr = GPR32 (15); 5694 uint32_t tmp; 5695 trace_input ("pop", OP_VOID, OP_VOID, OP_VOID); 5696 5697 tmp = RLW(sp_addr); 5698 SET_GPR32 (14, (((tmp & 0xffff) << 16)| ((tmp >> 16) & 0xffff))); 5699 SET_GPR32 (15, (sp_addr+4)); /* Update SP address. */ 5700 5701 trace_output_void (sd); 5702 } 5703 5704 /* popret. */ 5705 void 5706 OP_7_9 (SIM_DESC sd, SIM_CPU *cpu) 5707 { 5708 uint16_t a = OP[0], b = OP[1]; 5709 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_REG); 5710 OP_5_9 (sd, cpu); 5711 JMP(((GPR32(14)) << 1) & 0xffffff); 5712 5713 trace_output_void (sd); 5714 } 5715 5716 /* popret. */ 5717 void 5718 OP_3_8 (SIM_DESC sd, SIM_CPU *cpu) 5719 { 5720 uint16_t a = OP[0], b = OP[1]; 5721 trace_input ("popret", OP_CONSTANT3, OP_REG, OP_VOID); 5722 OP_2_8 (sd, cpu); 5723 JMP(((GPR32(14)) << 1) & 0xffffff); 5724 5725 trace_output_void (sd); 5726 } 5727 5728 /* popret. */ 5729 void 5730 OP_31E_10 (SIM_DESC sd, SIM_CPU *cpu) 5731 { 5732 uint32_t tmp; 5733 trace_input ("popret", OP_VOID, OP_VOID, OP_VOID); 5734 OP_21E_10 (sd, cpu); 5735 tmp = (((GPR32(14)) << 1) & 0xffffff); 5736 /* If the resulting PC value is less than 0x00_0000 or greater 5737 than 0xFF_FFFF, this instruction causes an IAD trap.*/ 5738 5739 if ((tmp < 0x0) || (tmp > 0xFFFFFF)) 5740 { 5741 trace_output_void (sd); 5742 EXCEPTION (SIM_SIGBUS); 5743 } 5744 else 5745 JMP (tmp); 5746 5747 trace_output_32 (sd, tmp); 5748 } 5749 5750 5751 /* cinv[i]. */ 5752 void 5753 OP_A_10 (SIM_DESC sd, SIM_CPU *cpu) 5754 { 5755 trace_input ("cinv[i]", OP_VOID, OP_VOID, OP_VOID); 5756 SET_PSR_I (1); 5757 trace_output_void (sd); 5758 } 5759 5760 /* cinv[i,u]. */ 5761 void 5762 OP_B_10 (SIM_DESC sd, SIM_CPU *cpu) 5763 { 5764 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); 5765 SET_PSR_I (1); 5766 trace_output_void (sd); 5767 } 5768 5769 /* cinv[d]. */ 5770 void 5771 OP_C_10 (SIM_DESC sd, SIM_CPU *cpu) 5772 { 5773 trace_input ("cinv[d]", OP_VOID, OP_VOID, OP_VOID); 5774 SET_PSR_I (1); 5775 trace_output_void (sd); 5776 } 5777 5778 /* cinv[d,u]. */ 5779 void 5780 OP_D_10 (SIM_DESC sd, SIM_CPU *cpu) 5781 { 5782 trace_input ("cinv[i,u]", OP_VOID, OP_VOID, OP_VOID); 5783 SET_PSR_I (1); 5784 trace_output_void (sd); 5785 } 5786 5787 /* cinv[d,i]. */ 5788 void 5789 OP_E_10 (SIM_DESC sd, SIM_CPU *cpu) 5790 { 5791 trace_input ("cinv[d,i]", OP_VOID, OP_VOID, OP_VOID); 5792 SET_PSR_I (1); 5793 trace_output_void (sd); 5794 } 5795 5796 /* cinv[d,i,u]. */ 5797 void 5798 OP_F_10 (SIM_DESC sd, SIM_CPU *cpu) 5799 { 5800 trace_input ("cinv[d,i,u]", OP_VOID, OP_VOID, OP_VOID); 5801 SET_PSR_I (1); 5802 trace_output_void (sd); 5803 } 5804 5805 /* retx. */ 5806 void 5807 OP_3_10 (SIM_DESC sd, SIM_CPU *cpu) 5808 { 5809 trace_input ("retx", OP_VOID, OP_VOID, OP_VOID); 5810 SET_PSR_I (1); 5811 trace_output_void (sd); 5812 } 5813 5814 /* di. */ 5815 void 5816 OP_4_10 (SIM_DESC sd, SIM_CPU *cpu) 5817 { 5818 trace_input ("di", OP_VOID, OP_VOID, OP_VOID); 5819 SET_PSR_I (1); 5820 trace_output_void (sd); 5821 } 5822 5823 /* ei. */ 5824 void 5825 OP_5_10 (SIM_DESC sd, SIM_CPU *cpu) 5826 { 5827 trace_input ("ei", OP_VOID, OP_VOID, OP_VOID); 5828 SET_PSR_I (1); 5829 trace_output_void (sd); 5830 } 5831 5832 /* wait. */ 5833 void 5834 OP_6_10 (SIM_DESC sd, SIM_CPU *cpu) 5835 { 5836 trace_input ("wait", OP_VOID, OP_VOID, OP_VOID); 5837 trace_output_void (sd); 5838 EXCEPTION (SIM_SIGTRAP); 5839 } 5840 5841 /* ewait. */ 5842 void 5843 OP_7_10 (SIM_DESC sd, SIM_CPU *cpu) 5844 { 5845 trace_input ("ewait", OP_VOID, OP_VOID, OP_VOID); 5846 SET_PSR_I (1); 5847 trace_output_void (sd); 5848 } 5849 5850 /* xorb. */ 5851 void 5852 OP_28_8 (SIM_DESC sd, SIM_CPU *cpu) 5853 { 5854 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 5855 trace_input ("xorb", OP_CONSTANT4, OP_REG, OP_VOID); 5856 tmp = a ^ b; 5857 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5858 trace_output_16 (sd, tmp); 5859 } 5860 5861 /* xorb. */ 5862 void 5863 OP_28B_C (SIM_DESC sd, SIM_CPU *cpu) 5864 { 5865 uint8_t tmp, a = (OP[0]) & 0xff, b = (GPR (OP[1])) & 0xff; 5866 trace_input ("xorb", OP_CONSTANT16, OP_REG, OP_VOID); 5867 tmp = a ^ b; 5868 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5869 trace_output_16 (sd, tmp); 5870 } 5871 5872 /* xorb. */ 5873 void 5874 OP_29_8 (SIM_DESC sd, SIM_CPU *cpu) 5875 { 5876 uint8_t tmp, a = (GPR (OP[0])) & 0xff, b = (GPR (OP[1])) & 0xff; 5877 trace_input ("xorb", OP_REG, OP_REG, OP_VOID); 5878 tmp = a ^ b; 5879 SET_GPR (OP[1], (tmp | ((GPR (OP[1])) & 0xff00))); 5880 trace_output_16 (sd, tmp); 5881 } 5882 5883 /* xorw. */ 5884 void 5885 OP_2A_8 (SIM_DESC sd, SIM_CPU *cpu) 5886 { 5887 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1])); 5888 trace_input ("xorw", OP_CONSTANT4, OP_REG, OP_VOID); 5889 tmp = a ^ b; 5890 SET_GPR (OP[1], tmp); 5891 trace_output_16 (sd, tmp); 5892 } 5893 5894 /* xorw. */ 5895 void 5896 OP_2AB_C (SIM_DESC sd, SIM_CPU *cpu) 5897 { 5898 uint16_t tmp, a = (OP[0]), b = (GPR (OP[1])); 5899 trace_input ("xorw", OP_CONSTANT16, OP_REG, OP_VOID); 5900 tmp = a ^ b; 5901 SET_GPR (OP[1], tmp); 5902 trace_output_16 (sd, tmp); 5903 } 5904 5905 /* xorw. */ 5906 void 5907 OP_2B_8 (SIM_DESC sd, SIM_CPU *cpu) 5908 { 5909 uint16_t tmp, a = (GPR (OP[0])), b = (GPR (OP[1])); 5910 trace_input ("xorw", OP_REG, OP_REG, OP_VOID); 5911 tmp = a ^ b; 5912 SET_GPR (OP[1], tmp); 5913 trace_output_16 (sd, tmp); 5914 } 5915 5916 /*REVISIT FOR LPR/SPR . */ 5917 5918 /* lpr. */ 5919 void 5920 OP_140_14 (SIM_DESC sd, SIM_CPU *cpu) 5921 { 5922 uint16_t a = GPR (OP[0]); 5923 trace_input ("lpr", OP_REG, OP_REG, OP_VOID); 5924 SET_CREG (OP[1], a); 5925 trace_output_16 (sd, a); 5926 } 5927 5928 /* lprd. */ 5929 void 5930 OP_141_14 (SIM_DESC sd, SIM_CPU *cpu) 5931 { 5932 uint32_t a = GPR32 (OP[0]); 5933 trace_input ("lprd", OP_REGP, OP_REG, OP_VOID); 5934 SET_CREG (OP[1], a); 5935 trace_output_flag (sd); 5936 } 5937 5938 /* spr. */ 5939 void 5940 OP_142_14 (SIM_DESC sd, SIM_CPU *cpu) 5941 { 5942 uint16_t a = CREG (OP[0]); 5943 trace_input ("spr", OP_REG, OP_REG, OP_VOID); 5944 SET_GPR (OP[1], a); 5945 trace_output_16 (sd, a); 5946 } 5947 5948 /* sprd. */ 5949 void 5950 OP_143_14 (SIM_DESC sd, SIM_CPU *cpu) 5951 { 5952 uint32_t a = CREG (OP[0]); 5953 trace_input ("sprd", OP_REGP, OP_REGP, OP_VOID); 5954 SET_GPR32 (OP[1], a); 5955 trace_output_32 (sd, a); 5956 } 5957 5958 /* null. */ 5959 void 5960 OP_0_20 (SIM_DESC sd, SIM_CPU *cpu) 5961 { 5962 trace_input ("null", OP_VOID, OP_VOID, OP_VOID); 5963 sim_engine_halt (sd, cpu, NULL, PC, sim_exited, 0); 5964 } 5965