1 /* Simulation code for the CR16 processor. 2 Copyright (C) 2008-2023 Free Software Foundation, Inc. 3 Contributed by M Ranga Swami Reddy <MR.Swami.Reddy@nsc.com> 4 5 This file is part of GDB, the GNU debugger. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 21 #include <stdio.h> 22 #include <ctype.h> 23 #include <limits.h> 24 #include "ansidecl.h" 25 #include "sim/callback.h" 26 #include "opcode/cr16.h" 27 #include "bfd.h" 28 29 #define DEBUG_TRACE 0x00000001 30 #define DEBUG_VALUES 0x00000002 31 #define DEBUG_LINE_NUMBER 0x00000004 32 #define DEBUG_MEMSIZE 0x00000008 33 #define DEBUG_INSTRUCTION 0x00000010 34 #define DEBUG_TRAP 0x00000020 35 #define DEBUG_MEMORY 0x00000040 36 37 #ifndef DEBUG 38 #define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER) 39 #endif 40 41 extern int cr16_debug; 42 43 #include "sim/sim.h" 44 #include "sim-config.h" 45 #include "sim-types.h" 46 47 /* FIXME: CR16 defines */ 48 typedef uint16_t reg_t; 49 typedef uint32_t creg_t; 50 51 struct simops 52 { 53 char mnemonic[12]; 54 uint32_t size; 55 uint32_t mask; 56 uint32_t opcode; 57 int format; 58 char fname[12]; 59 void (*func)(SIM_DESC, SIM_CPU *); 60 int numops; 61 operand_desc operands[4]; 62 }; 63 64 enum _ins_type 65 { 66 INS_UNKNOWN, /* unknown instruction */ 67 INS_NO_TYPE_INS, 68 INS_ARITH_INS, 69 INS_LD_STOR_INS, 70 INS_BRANCH_INS, 71 INS_ARITH_BYTE_INS, 72 INS_SHIFT_INS, 73 INS_BRANCH_NEQ_INS, 74 INS_STOR_IMM_INS, 75 INS_CSTBIT_INS, 76 INS_MAX 77 }; 78 79 extern unsigned long ins_type_counters[ (int)INS_MAX ]; 80 81 enum { 82 SP_IDX = 15, 83 }; 84 85 /* Write-back slots */ 86 union slot_data { 87 unsigned_1 _1; 88 unsigned_2 _2; 89 unsigned_4 _4; 90 }; 91 struct slot { 92 void *dest; 93 int size; 94 union slot_data data; 95 union slot_data mask; 96 }; 97 enum { 98 NR_SLOTS = 16 99 }; 100 #define SLOT (State.slot) 101 #define SLOT_NR (State.slot_nr) 102 #define SLOT_PEND_MASK(DEST, MSK, VAL) \ 103 do \ 104 { \ 105 SLOT[SLOT_NR].dest = &(DEST); \ 106 SLOT[SLOT_NR].size = sizeof (DEST); \ 107 switch (sizeof (DEST)) \ 108 { \ 109 case 1: \ 110 SLOT[SLOT_NR].data._1 = (unsigned_1) (VAL); \ 111 SLOT[SLOT_NR].mask._1 = (unsigned_1) (MSK); \ 112 break; \ 113 case 2: \ 114 SLOT[SLOT_NR].data._2 = (unsigned_2) (VAL); \ 115 SLOT[SLOT_NR].mask._2 = (unsigned_2) (MSK); \ 116 break; \ 117 case 4: \ 118 SLOT[SLOT_NR].data._4 = (unsigned_4) (VAL); \ 119 SLOT[SLOT_NR].mask._4 = (unsigned_4) (MSK); \ 120 break; \ 121 } \ 122 SLOT_NR = (SLOT_NR + 1); \ 123 } \ 124 while (0) 125 #define SLOT_PEND(DEST, VAL) SLOT_PEND_MASK(DEST, 0, VAL) 126 #define SLOT_DISCARD() (SLOT_NR = 0) 127 #define SLOT_FLUSH() \ 128 do \ 129 { \ 130 int i; \ 131 for (i = 0; i < SLOT_NR; i++) \ 132 { \ 133 switch (SLOT[i].size) \ 134 { \ 135 case 1: \ 136 *(unsigned_1*) SLOT[i].dest &= SLOT[i].mask._1; \ 137 *(unsigned_1*) SLOT[i].dest |= SLOT[i].data._1; \ 138 break; \ 139 case 2: \ 140 *(unsigned_2*) SLOT[i].dest &= SLOT[i].mask._2; \ 141 *(unsigned_2*) SLOT[i].dest |= SLOT[i].data._2; \ 142 break; \ 143 case 4: \ 144 *(unsigned_4*) SLOT[i].dest &= SLOT[i].mask._4; \ 145 *(unsigned_4*) SLOT[i].dest |= SLOT[i].data._4; \ 146 break; \ 147 } \ 148 } \ 149 SLOT_NR = 0; \ 150 } \ 151 while (0) 152 #define SLOT_DUMP() \ 153 do \ 154 { \ 155 int i; \ 156 for (i = 0; i < SLOT_NR; i++) \ 157 { \ 158 switch (SLOT[i].size) \ 159 { \ 160 case 1: \ 161 printf ("SLOT %d *0x%08lx & 0x%02x | 0x%02x\n", i, \ 162 (long) SLOT[i].dest, \ 163 (unsigned) SLOT[i].mask._1, \ 164 (unsigned) SLOT[i].data._1); \ 165 break; \ 166 case 2: \ 167 printf ("SLOT %d *0x%08lx & 0x%04x | 0x%04x\n", i, \ 168 (long) SLOT[i].dest, \ 169 (unsigned) SLOT[i].mask._2, \ 170 (unsigned) SLOT[i].data._2); \ 171 break; \ 172 case 4: \ 173 printf ("SLOT %d *0x%08lx & 0x%08x | 0x%08x\n", i, \ 174 (long) SLOT[i].dest, \ 175 (unsigned) SLOT[i].mask._4, \ 176 (unsigned) SLOT[i].data._4); \ 177 break; \ 178 case 8: \ 179 printf ("SLOT %d *0x%08lx & 0x%08x%08x | 0x%08x%08x\n", i, \ 180 (long) SLOT[i].dest, \ 181 (unsigned) (SLOT[i].mask._8 >> 32), \ 182 (unsigned) SLOT[i].mask._8, \ 183 (unsigned) (SLOT[i].data._8 >> 32), \ 184 (unsigned) SLOT[i].data._8); \ 185 break; \ 186 } \ 187 } \ 188 } \ 189 while (0) 190 191 struct _state 192 { 193 creg_t regs[16]; /* general-purpose registers */ 194 #define GPR(N) (State.regs[(N)] + 0) 195 #define SET_GPR(N,VAL) (State.regs[(N)] = (VAL)) 196 197 #define GPR32(N) \ 198 (N < 12) ? \ 199 ((((uint16_t) State.regs[(N) + 1]) << 16) | (uint16_t) State.regs[(N)]) \ 200 : GPR (N) 201 202 #define SET_GPR32(N,VAL) do { \ 203 if (N < 11) \ 204 { SET_GPR (N + 1, (VAL) >> 16); SET_GPR (N, ((VAL) & 0xffff));} \ 205 else { if ( N == 11) \ 206 { SET_GPR (N + 1, ((GPR32 (12)) & 0xffff0000)|((VAL) >> 16)); \ 207 SET_GPR (N, ((VAL) & 0xffff));} \ 208 else SET_GPR (N, (VAL));} \ 209 } while (0) 210 211 creg_t cregs[16]; /* control registers */ 212 #define CREG(N) (State.cregs[(N)] + 0) 213 #define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0) 214 #define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1) 215 216 reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */ 217 #define HELD_SP(N) (State.sp[(N)] + 0) 218 #define SET_HELD_SP(N,VAL) SLOT_PEND (State.sp[(N)], (VAL)) 219 220 /* writeback info */ 221 struct slot slot[NR_SLOTS]; 222 int slot_nr; 223 224 /* trace data */ 225 struct { 226 uint16_t psw; 227 } trace; 228 229 int pc_changed; 230 231 /* NOTE: everything below this line is not reset by 232 sim_create_inferior() */ 233 234 enum _ins_type ins_type; 235 236 }; 237 238 extern struct _state State; 239 240 241 extern uint32_t OP[4]; 242 extern uint32_t sign_flag; 243 extern struct simops Simops[]; 244 245 enum 246 { 247 PC_CR = 0, 248 BDS_CR = 1, 249 BSR_CR = 2, 250 DCR_CR = 3, 251 CAR0_CR = 5, 252 CAR1_CR = 7, 253 CFG_CR = 9, 254 PSR_CR = 10, 255 INTBASE_CR = 11, 256 ISP_CR = 13, 257 USP_CR = 15 258 }; 259 260 enum 261 { 262 PSR_I_BIT = 0x0800, 263 PSR_P_BIT = 0x0400, 264 PSR_E_BIT = 0x0200, 265 PSR_N_BIT = 0x0080, 266 PSR_Z_BIT = 0x0040, 267 PSR_F_BIT = 0x0020, 268 PSR_U_BIT = 0x0008, 269 PSR_L_BIT = 0x0004, 270 PSR_T_BIT = 0x0002, 271 PSR_C_BIT = 0x0001 272 }; 273 274 #define PSR CREG (PSR_CR) 275 #define SET_PSR(VAL) SET_CREG (PSR_CR, (VAL)) 276 #define SET_HW_PSR(VAL) SET_HW_CREG (PSR_CR, (VAL)) 277 #define SET_PSR_BIT(MASK,VAL) move_to_cr (sd, cpu, PSR_CR, ~((creg_t) MASK), (VAL) ? (MASK) : 0, 1) 278 279 #define PSR_SM ((PSR & PSR_SM_BIT) != 0) 280 #define SET_PSR_SM(VAL) SET_PSR_BIT (PSR_SM_BIT, (VAL)) 281 282 #define PSR_I ((PSR & PSR_I_BIT) != 0) 283 #define SET_PSR_I(VAL) SET_PSR_BIT (PSR_I_BIT, (VAL)) 284 285 #define PSR_DB ((PSR & PSR_DB_BIT) != 0) 286 #define SET_PSR_DB(VAL) SET_PSR_BIT (PSR_DB_BIT, (VAL)) 287 288 #define PSR_P ((PSR & PSR_P_BIT) != 0) 289 #define SET_PSR_P(VAL) SET_PSR_BIT (PSR_P_BIT, (VAL)) 290 291 #define PSR_E ((PSR & PSR_E_BIT) != 0) 292 #define SET_PSR_E(VAL) SET_PSR_BIT (PSR_E_BIT, (VAL)) 293 294 #define PSR_N ((PSR & PSR_N_BIT) != 0) 295 #define SET_PSR_N(VAL) SET_PSR_BIT (PSR_N_BIT, (VAL)) 296 297 #define PSR_Z ((PSR & PSR_Z_BIT) != 0) 298 #define SET_PSR_Z(VAL) SET_PSR_BIT (PSR_Z_BIT, (VAL)) 299 300 #define PSR_F ((PSR & PSR_F_BIT) != 0) 301 #define SET_PSR_F(VAL) SET_PSR_BIT (PSR_F_BIT, (VAL)) 302 303 #define PSR_U ((PSR & PSR_U_BIT) != 0) 304 #define SET_PSR_U(VAL) SET_PSR_BIT (PSR_U_BIT, (VAL)) 305 306 #define PSR_L ((PSR & PSR_L_BIT) != 0) 307 #define SET_PSR_L(VAL) SET_PSR_BIT (PSR_L_BIT, (VAL)) 308 309 #define PSR_T ((PSR & PSR_T_BIT) != 0) 310 #define SET_PSR_T(VAL) SET_PSR_BIT (PSR_T_BIT, (VAL)) 311 312 #define PSR_C ((PSR & PSR_C_BIT) != 0) 313 #define SET_PSR_C(VAL) SET_PSR_BIT (PSR_C_BIT, (VAL)) 314 315 /* See simopsc.:move_to_cr() for registers that can not be read-from 316 or assigned-to directly */ 317 318 #define PC CREG (PC_CR) 319 #define SET_PC(VAL) SET_CREG (PC_CR, (VAL)) 320 //#define SET_PC(VAL) (State.cregs[PC_CR] = (VAL)) 321 322 #define BPSR CREG (BPSR_CR) 323 #define SET_BPSR(VAL) SET_CREG (BPSR_CR, (VAL)) 324 325 #define BPC CREG (BPC_CR) 326 #define SET_BPC(VAL) SET_CREG (BPC_CR, (VAL)) 327 328 #define DPSR CREG (DPSR_CR) 329 #define SET_DPSR(VAL) SET_CREG (DPSR_CR, (VAL)) 330 331 #define DPC CREG (DPC_CR) 332 #define SET_DPC(VAL) SET_CREG (DPC_CR, (VAL)) 333 334 #define RPT_C CREG (RPT_C_CR) 335 #define SET_RPT_C(VAL) SET_CREG (RPT_C_CR, (VAL)) 336 337 #define RPT_S CREG (RPT_S_CR) 338 #define SET_RPT_S(VAL) SET_CREG (RPT_S_CR, (VAL)) 339 340 #define RPT_E CREG (RPT_E_CR) 341 #define SET_RPT_E(VAL) SET_CREG (RPT_E_CR, (VAL)) 342 343 #define MOD_S CREG (MOD_S_CR) 344 #define SET_MOD_S(VAL) SET_CREG (MOD_S_CR, (VAL)) 345 346 #define MOD_E CREG (MOD_E_CR) 347 #define SET_MOD_E(VAL) SET_CREG (MOD_E_CR, (VAL)) 348 349 #define IBA CREG (IBA_CR) 350 #define SET_IBA(VAL) SET_CREG (IBA_CR, (VAL)) 351 352 353 #define SIG_CR16_STOP -1 354 #define SIG_CR16_EXIT -2 355 #define SIG_CR16_BUS -3 356 #define SIG_CR16_IAD -4 357 358 /* TODO: Resolve conflicts with common headers. */ 359 #undef SEXT8 360 #undef SEXT16 361 #undef SEXT32 362 363 #define SEXT3(x) ((((x)&0x7)^(~3))+4) 364 365 /* sign-extend a 4-bit number */ 366 #define SEXT4(x) ((((x)&0xf)^(~7))+8) 367 368 /* sign-extend an 8-bit number */ 369 #define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80) 370 371 /* sign-extend a 16-bit number */ 372 #define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000) 373 374 /* sign-extend a 24-bit number */ 375 #define SEXT24(x) ((((x)&0xffffff)^(~0x7fffff))+0x800000) 376 377 /* sign-extend a 32-bit number */ 378 #define SEXT32(x) ((((x)&0xffffffff)^(~0x7fffffff))+0x80000000) 379 380 #define SB(addr, data) sim_core_write_1 (cpu, PC, read_map, addr, data) 381 #define RB(addr) sim_core_read_1 (cpu, PC, read_map, addr) 382 #define SW(addr, data) sim_core_write_unaligned_2 (cpu, PC, read_map, addr, data) 383 #define RW(addr) sim_core_read_unaligned_2 (cpu, PC, read_map, addr) 384 #define SLW(addr, data) sim_core_write_unaligned_4 (cpu, PC, read_map, addr, data) 385 386 /* Yes, this is as whacked as it looks. The sim currently reads little endian 387 for 16 bits, but then merge them like big endian to get 32 bits. */ 388 static inline uint32_t get_longword (SIM_CPU *cpu, address_word addr) 389 { 390 return (RW (addr) << 16) | RW (addr + 2); 391 } 392 #define RLW(addr) get_longword (cpu, addr) 393 394 #define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0) 395 396 #define RIE_VECTOR_START 0xffc2 397 #define AE_VECTOR_START 0xffc3 398 #define TRAP_VECTOR_START 0xffc4 /* vector for trap 0 */ 399 #define DBT_VECTOR_START 0xffd4 400 #define SDBT_VECTOR_START 0xffd5 401 402 #define INT_VECTOR_START 0xFFFE00 /*maskable interrupt - mapped to ICU */ 403 #define NMI_VECTOR_START 0xFFFF00 /*non-maskable interrupt;for observability*/ 404 #define ISE_VECTOR_START 0xFFFC00 /*in-system emulation trap */ 405 #define ADBG_VECTOR_START 0xFFFC02 /*alternate debug trap */ 406 #define ATRC_VECTOR_START 0xFFFC0C /*alternate trace trap */ 407 #define ABPT_VECTOR_START 0xFFFC0E /*alternate break point trap */ 408 409 410 /* Scedule a store of VAL into cr[CR]. MASK indicates the bits in 411 cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) | 412 (VAL & ~MASK)). In addition, unless PSR_HW_P, a VAL intended for 413 PSR is masked for zero bits. */ 414 415 extern creg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, creg_t mask, creg_t val, int psw_hw_p); 416 417 #ifndef SIGTRAP 418 #define SIGTRAP 5 419 #endif 420 /* Special purpose trap */ 421 #define TRAP_BREAKPOINT 8 422