12015-07-03 Alan Modra <amodra@gmail.com> 2 3 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. 4 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add 5 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. 6 72015-07-01 Sandra Loosemore <sandra@codesourcery.com> 8 Cesar Philippidis <cesar@codesourcery.com> 9 10 * nios2-dis.c (nios2_extract_opcode): New. 11 (nios2_disassembler_state): New. 12 (nios2_find_opcode_hash): Use mach parameter to select correct 13 disassembler state. 14 (nios2_print_insn_arg): Extend to support new R2 argument letters 15 and formats. 16 (print_insn_nios2): Check for 16-bit instruction at end of memory. 17 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. 18 (NIOS2_NUM_OPCODES): Rename to... 19 (NIOS2_NUM_R1_OPCODES): This. 20 (nios2_r2_opcodes): New. 21 (NIOS2_NUM_R2_OPCODES): New. 22 (nios2_num_r2_opcodes): New. 23 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. 24 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. 25 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. 26 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. 27 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. 28 292015-06-30 Amit Pawar <Amit.Pawar@amd.com> 30 31 * i386-dis.c (OP_Mwaitx): New. 32 (rm_table): Add monitorx/mwaitx. 33 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS 34 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. 35 (operand_type_init): Add CpuMWAITX. 36 * i386-opc.h (CpuMWAITX): New. 37 (i386_cpu_flags): Add cpumwaitx. 38 * i386-opc.tbl: Add monitorx and mwaitx. 39 * i386-init.h: Regenerated. 40 * i386-tbl.h: Likewise. 41 422015-06-22 Peter Bergner <bergner@vnet.ibm.com> 43 44 * ppc-opc.c (insert_ls): Test for invalid LS operands. 45 (insert_esync): New function. 46 (LS, WC): Use insert_ls. 47 (ESYNC): Use insert_esync. 48 492015-06-22 Nick Clifton <nickc@redhat.com> 50 51 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the 52 requested region lies beyond it. 53 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when 54 looking for 32-bit insns. 55 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading 56 data. 57 * sh-dis.c (print_insn_sh): Likewise. 58 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading 59 blocks of instructions. 60 * vax-dis.c (print_insn_vax): Check that the requested address 61 does not clash with the stop_vma. 62 632015-06-19 Peter Bergner <bergner@vnet.ibm.com> 64 65 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. 66 * ppc-opc.c (FXM4): Add non-zero optional value. 67 (TBR): Likewise. 68 (SXL): Likewise. 69 (insert_fxm): Handle new default operand value. 70 (extract_fxm): Likewise. 71 (insert_tbr): Likewise. 72 (extract_tbr): Likewise. 73 742015-06-16 Matthew Wahab <matthew.wahab@arm.com> 75 76 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". 77 782015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> 79 80 * arm-dis.c (print_insn_coprocessor): Avoid negative shift. 81 822015-06-12 Peter Bergner <bergner@vnet.ibm.com> 83 84 * ppc-opc.c: Add comment accidentally removed by old commit. 85 (MTMSRD_L): Delete. 86 872015-06-04 Nick Clifton <nickc@redhat.com> 88 89 PR 18474 90 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. 91 922015-06-02 Matthew Wahab <matthew.wahab@arm.com> 93 94 * arm-dis.c (arm_opcodes): Add "setpan". 95 (thumb_opcodes): Add "setpan". 96 972015-06-02 Matthew Wahab <matthew.wahab@arm.com> 98 99 * arm-dis.c (select_arm_features): Rework to avoid used of redefined 100 macros. 101 1022015-06-02 Matthew Wahab <matthew.wahab@arm.com> 103 104 * aarch64-tbl.h (aarch64_feature_rdma): New. 105 (RDMA): New. 106 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. 107 * aarch64-asm-2.c: Regenerate. 108 * aarch64-dis-2.c: Regenerate. 109 * aarch64-opc-2.c: Regenerate. 110 1112015-06-02 Matthew Wahab <matthew.wahab@arm.com> 112 113 * aarch64-tbl.h (aarch64_feature_lor): New. 114 (LOR): New. 115 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", 116 "stllrb", "stllrh". 117 * aarch64-asm-2.c: Regenerate. 118 * aarch64-dis-2.c: Regenerate. 119 * aarch64-opc-2.c: Regenerate. 120 1212015-06-01 Matthew Wahab <matthew.wahab@arm.com> 122 123 * aarch64-opc.c (F_ARCHEXT): New. 124 (aarch64_sys_regs): Add "pan". 125 (aarch64_sys_reg_supported_p): New. 126 (aarch64_pstatefields): Add "pan". 127 (aarch64_pstatefield_supported_p): New. 128 1292015-06-01 Jan Beulich <jbeulich@suse.com> 130 131 * i386-tbl.h: Regenerate. 132 1332015-06-01 Jan Beulich <jbeulich@suse.com> 134 135 * i386-dis.c (print_insn): Swap rounding mode specifier and 136 general purpose register in Intel mode. 137 1382015-06-01 Jan Beulich <jbeulich@suse.com> 139 140 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. 141 * i386-tbl.h: Regenerate. 142 1432015-05-18 H.J. Lu <hongjiu.lu@intel.com> 144 145 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. 146 * i386-init.h: Regenerated. 147 1482015-05-15 H.J. Lu <hongjiu.lu@intel.com> 149 150 PR binutis/18386 151 * i386-dis.c: Add comments for '@'. 152 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. 153 (enum x86_64_isa): New. 154 (isa64): Likewise. 155 (print_i386_disassembler_options): Add amd64 and intel64. 156 (print_insn): Handle amd64 and intel64. 157 (putop): Handle '@'. 158 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. 159 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. 160 * i386-opc.h (AMD64): New. 161 (CpuIntel64): Likewise. 162 (i386_cpu_flags): Add cpuamd64 and cpuintel64. 163 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. 164 Mark direct call/jmp without Disp16|Disp32 as Intel64. 165 * i386-init.h: Regenerated. 166 * i386-tbl.h: Likewise. 167 1682015-05-14 Peter Bergner <bergner@vnet.ibm.com> 169 170 * ppc-opc.c (IH) New define. 171 (powerpc_opcodes) <wait>: Do not enable for POWER7. 172 <tlbie>: Add RS operand for POWER7. 173 <slbia>: Add IH operand for POWER6. 174 1752015-05-11 H.J. Lu <hongjiu.lu@intel.com> 176 177 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit 178 direct branch. 179 (jmp): Likewise. 180 * i386-tbl.h: Regenerated. 181 1822015-05-11 H.J. Lu <hongjiu.lu@intel.com> 183 184 * configure.ac: Support bfd_iamcu_arch. 185 * disassemble.c (disassembler): Support bfd_iamcu_arch. 186 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and 187 CPU_IAMCU_COMPAT_FLAGS. 188 (cpu_flags): Add CpuIAMCU. 189 * i386-opc.h (CpuIAMCU): New. 190 (i386_cpu_flags): Add cpuiamcu. 191 * configure: Regenerated. 192 * i386-init.h: Likewise. 193 * i386-tbl.h: Likewise. 194 1952015-05-08 H.J. Lu <hongjiu.lu@intel.com> 196 197 PR binutis/18386 198 * i386-dis.c (X86_64_E8): New. 199 (X86_64_E9): Likewise. 200 Update comments on 'T', 'U', 'V'. Add comments for '^'. 201 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. 202 (x86_64_table): Add X86_64_E8 and X86_64_E9. 203 (mod_table): Replace {T|} with ^ on Jcall/Jmp. 204 (putop): Handle '^'. 205 (OP_J): Ignore the operand size prefix in 64-bit. Don't check 206 REX_W. 207 2082015-04-30 DJ Delorie <dj@redhat.com> 209 210 * disassemble.c (disassembler): Choose suitable disassembler based 211 on E_ABI. 212 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use 213 it to decode mul/div insns. 214 * rl78-decode.c: Regenerate. 215 * rl78-dis.c (print_insn_rl78): Rename to... 216 (print_insn_rl78_common): ...this, take ISA parameter. 217 (print_insn_rl78): New. 218 (print_insn_rl78_g10): New. 219 (print_insn_rl78_g13): New. 220 (print_insn_rl78_g14): New. 221 (rl78_get_disassembler): New. 222 2232015-04-29 Nick Clifton <nickc@redhat.com> 224 225 * po/fr.po: Updated French translation. 226 2272015-04-27 Peter Bergner <bergner@vnet.ibm.com> 228 229 * ppc-opc.c (DCBT_EO): New define. 230 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. 231 <lharx>: Likewise. 232 <stbcx.>: Likewise. 233 <sthcx.>: Likewise. 234 <waitrsv>: Do not enable for POWER7 and later. 235 <waitimpl>: Likewise. 236 <dcbt>: Default to the two operand form of the instruction for all 237 "old" cpus. For "new" cpus, use the operand ordering that matches 238 whether the cpu is server or embedded. 239 <dcbtst>: Likewise. 240 2412015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 242 243 * s390-opc.c: New instruction type VV0UU2. 244 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, 245 and WFC. 246 2472015-04-23 Jan Beulich <jbeulich@suse.com> 248 249 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". 250 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, 251 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. 252 (vfpclasspd, vfpclassps): Add %XZ. 253 2542015-04-15 H.J. Lu <hongjiu.lu@intel.com> 255 256 * i386-dis.c (PREFIX_UD_SHIFT): Removed. 257 (PREFIX_UD_REPZ): Likewise. 258 (PREFIX_UD_REPNZ): Likewise. 259 (PREFIX_UD_DATA): Likewise. 260 (PREFIX_UD_ADDR): Likewise. 261 (PREFIX_UD_LOCK): Likewise. 262 2632015-04-15 H.J. Lu <hongjiu.lu@intel.com> 264 265 * i386-dis.c (prefix_requirement): Removed. 266 (print_insn): Don't set prefix_requirement. Check 267 dp->prefix_requirement instead of prefix_requirement. 268 2692015-04-15 H.J. Lu <hongjiu.lu@intel.com> 270 271 PR binutils/17898 272 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... 273 (PREFIX_MOD_0_0FC7_REG_6): This. 274 (PREFIX_MOD_3_0FC7_REG_6): New. 275 (PREFIX_MOD_3_0FC7_REG_7): Likewise. 276 (prefix_table): Replace PREFIX_0FC7_REG_6 with 277 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and 278 PREFIX_MOD_3_0FC7_REG_7. 279 (mod_table): Replace PREFIX_0FC7_REG_6 with 280 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and 281 PREFIX_MOD_3_0FC7_REG_7. 282 2832015-04-15 H.J. Lu <hongjiu.lu@intel.com> 284 285 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. 286 (PREFIX_MANDATORY_REPNZ): Likewise. 287 (PREFIX_MANDATORY_DATA): Likewise. 288 (PREFIX_MANDATORY_ADDR): Likewise. 289 (PREFIX_MANDATORY_LOCK): Likewise. 290 (PREFIX_MANDATORY): Likewise. 291 (PREFIX_UD_SHIFT): Set to 8 292 (PREFIX_UD_REPZ): Updated. 293 (PREFIX_UD_REPNZ): Likewise. 294 (PREFIX_UD_DATA): Likewise. 295 (PREFIX_UD_ADDR): Likewise. 296 (PREFIX_UD_LOCK): Likewise. 297 (PREFIX_IGNORED_SHIFT): New. 298 (PREFIX_IGNORED_REPZ): Likewise. 299 (PREFIX_IGNORED_REPNZ): Likewise. 300 (PREFIX_IGNORED_DATA): Likewise. 301 (PREFIX_IGNORED_ADDR): Likewise. 302 (PREFIX_IGNORED_LOCK): Likewise. 303 (PREFIX_OPCODE): Likewise. 304 (PREFIX_IGNORED): Likewise. 305 (Bad_Opcode): Replace PREFIX_MANDATORY with 0. 306 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. 307 (three_byte_table): Likewise. 308 (mod_table): Likewise. 309 (mandatory_prefix): Renamed to ... 310 (prefix_requirement): This. 311 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. 312 Update PREFIX_90 entry. 313 (get_valid_dis386): Check prefix_requirement to see if a prefix 314 should be ignored. 315 (print_insn): Replace mandatory_prefix with prefix_requirement. 316 3172015-04-15 Renlin Li <renlin.li@arm.com> 318 319 * arm-dis.c (thumb32_opcodes): Define 'D' format control code, 320 use it for ssat and ssat16. 321 (print_insn_thumb32): Add handle case for 'D' control code. 322 3232015-04-06 Ilya Tocar <ilya.tocar@intel.com> 324 H.J. Lu <hongjiu.lu@intel.com> 325 326 * i386-dis-evex.h (evex_table): Fill prefix_requirement field. 327 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, 328 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, 329 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, 330 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. 331 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): 332 Fill prefix_requirement field. 333 (struct dis386): Add prefix_requirement field. 334 (dis386): Fill prefix_requirement field. 335 (dis386_twobyte): Ditto. 336 (twobyte_has_mandatory_prefix_: Remove. 337 (reg_table): Fill prefix_requirement field. 338 (prefix_table): Ditto. 339 (x86_64_table): Ditto. 340 (three_byte_table): Ditto. 341 (xop_table): Ditto. 342 (vex_table): Ditto. 343 (vex_len_table): Ditto. 344 (vex_w_table): Ditto. 345 (mod_table): Ditto. 346 (bad_opcode): Ditto. 347 (print_insn): Use prefix_requirement. 348 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, 349 FGRPde_3, FGRPdf_4): Fill prefix_requirement field. 350 (float_reg): Ditto. 351 3522015-03-30 Mike Frysinger <vapier@gentoo.org> 353 354 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. 355 3562015-03-29 H.J. Lu <hongjiu.lu@intel.com> 357 358 * Makefile.in: Regenerated. 359 3602015-03-25 Anton Blanchard <anton@samba.org> 361 362 * ppc-dis.c (disassemble_init_powerpc): Only initialise 363 powerpc_opcd_indices and vle_opcd_indices once. 364 3652015-03-25 Anton Blanchard <anton@samba.org> 366 367 * ppc-opc.c (powerpc_opcodes): Add slbfee. 368 3692015-03-24 Terry Guo <terry.guo@arm.com> 370 371 * arm-dis.c (opcode32): Updated to use new arm feature struct. 372 (opcode16): Likewise. 373 (coprocessor_opcodes): Replace bit with feature struct. 374 (neon_opcodes): Likewise. 375 (arm_opcodes): Likewise. 376 (thumb_opcodes): Likewise. 377 (thumb32_opcodes): Likewise. 378 (print_insn_coprocessor): Likewise. 379 (print_insn_arm): Likewise. 380 (select_arm_features): Follow new feature struct. 381 3822015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> 383 384 * i386-dis.c (rm_table): Add clzero. 385 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. 386 Add CPU_CLZERO_FLAGS. 387 (cpu_flags): Add CpuCLZERO. 388 * i386-opc.h: Add CpuCLZERO. 389 * i386-opc.tbl: Add clzero. 390 * i386-init.h: Re-generated. 391 * i386-tbl.h: Re-generated. 392 3932015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> 394 395 * mips-opc.c (decode_mips_operand): Fix constraint issues 396 with u and y operands. 397 3982015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> 399 400 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. 401 4022015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 403 404 * s390-opc.c: Add new IBM z13 instructions. 405 * s390-opc.txt: Likewise. 406 4072015-03-10 Renlin Li <renlin.li@arm.com> 408 409 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, 410 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and 411 related alias. 412 * aarch64-asm-2.c: Regenerate. 413 * aarch64-dis-2.c: Likewise. 414 * aarch64-opc-2.c: Likewise. 415 4162015-03-03 Jiong Wang <jiong.wang@arm.com> 417 418 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. 419 4202015-02-25 Oleg Endo <olegendo@gcc.gnu.org> 421 422 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of 423 arch_sh_up. 424 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of 425 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. 426 4272015-02-23 Vinay <Vinay.G@kpit.com> 428 429 * rl78-decode.opc (MOV): Added space between two operands for 430 'mov' instruction in index addressing mode. 431 * rl78-decode.c: Regenerate. 432 4332015-02-19 Pedro Alves <palves@redhat.com> 434 435 * microblaze-dis.h [__cplusplus]: Wrap in extern "C". 436 4372015-02-10 Pedro Alves <palves@redhat.com> 438 Tom Tromey <tromey@redhat.com> 439 440 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, 441 microblaze_and, microblaze_xor. 442 * microblaze-opc.h (opcodes): Adjust. 443 4442015-01-28 James Bowman <james.bowman@ftdichip.com> 445 446 * Makefile.am: Add FT32 files. 447 * configure.ac: Handle FT32. 448 * disassemble.c (disassembler): Call print_insn_ft32. 449 * ft32-dis.c: New file. 450 * ft32-opc.c: New file. 451 * Makefile.in: Regenerate. 452 * configure: Regenerate. 453 * po/POTFILES.in: Regenerate. 454 4552015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> 456 457 * nds32-asm.c (keyword_sr): Add new system registers. 458 4592015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> 460 461 * s390-dis.c (s390_extract_operand): Support vector register 462 operands. 463 (s390_print_insn_with_opcode): Support new operands types and add 464 new handling of optional operands. 465 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove 466 and include opcode/s390.h instead. 467 (struct op_struct): New field `flags'. 468 (insertOpcode, insertExpandedMnemonic): New parameter `flags'. 469 (dumpTable): Dump flags. 470 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu 471 string. 472 * s390-opc.c: Add new operands types, instruction formats, and 473 instruction masks. 474 (s390_opformats): Add new formats for .insn. 475 * s390-opc.txt: Add new instructions. 476 4772015-01-01 Alan Modra <amodra@gmail.com> 478 479 Update year range in copyright notice of all files. 480 481For older changes see ChangeLog-2014 482 483Copyright (C) 2015 Free Software Foundation, Inc. 484 485Copying and distribution of this file, with or without modification, 486are permitted in any medium without royalty provided the copyright 487notice and this notice are preserved. 488 489Local Variables: 490mode: change-log 491left-margin: 8 492fill-column: 74 493version-control: never 494End: 495