12022-11-22 Shahab Vahedi <shahab@synopsys.com> 2 3 * arc-regs.h: Change isa_config address to 0xc1. 4 isa_config exists for ARC700 and ARCV2 and not ARCALL. 5 62022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp> 7 8 * rx-decode.opc: Switch arguments of the MVTACGU insn. 9 * rx-decode.c: Regenerate. 10 112022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp> 12 13 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC 14 Rm_BANK,Rn is always 1. 15 162022-07-21 Peter Bergner <bergner@linux.ibm.com> 17 18 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines. 19 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4, 20 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8, 21 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp, 22 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp, 23 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, 24 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them. 25 262022-07-18 Claudiu Zissulescu <claziss@synopsys.com> 27 28 * disassemble.c (disassemble_init_for_target): Set 29 created_styled_output for ARC based targets. 30 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype 31 instead of fprintf_ftype throughout. 32 (find_format): Likewise. 33 (print_flags): Likewise. 34 (print_insn_arc): Likewise. 35 362022-07-08 Nick Clifton <nickc@redhat.com> 37 38 * 2.39 branch created. 39 402022-07-04 Marcus Nilsson <brainbomb@gmail.com> 41 42 * disassemble.c: (disassemble_init_for_target): Set 43 created_styled_output for AVR based targets. 44 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype 45 instead of fprintf_ftype throughout. 46 (avr_operand): Pass in and fill disassembler_style when 47 parsing operands. 48 492022-04-07 Andreas Krebbel <krebbel@linux.ibm.com> 50 51 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode 52 table. 53 542022-03-16 Simon Marchi <simon.marchi@efficios.com> 55 56 * configure.ac: Handle bfd_amdgcn_arch. 57 * configure: Re-generate. 58 592022-03-06 Sagar Patel <sagarmp@cs.unc.edu> 60 Maciej W. Rozycki <macro@orcam.me.uk> 61 62 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation 63 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions. 64 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and 65 "bnez" instructions. 66 672022-02-17 Nick Clifton <nickc@redhat.com> 68 69 * po/sr.po: Updated Serbian translation. 70 712022-02-14 Sergei Trofimovich <siarheit@google.com> 72 73 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'. 74 * microblaze-opc.h: Follow 'fsqrt' rename. 75 762022-01-24 Nick Clifton <nickc@redhat.com> 77 78 * po/ro.po: Updated Romanian translation. 79 * po/uk.po: Updated Ukranian translation. 80 812022-01-22 Nick Clifton <nickc@redhat.com> 82 83 * configure: Regenerate. 84 * po/opcodes.pot: Regenerate. 85 862022-01-22 Nick Clifton <nickc@redhat.com> 87 88 * 2.38 release branch created. 89 902022-01-17 Nick Clifton <nickc@redhat.com> 91 92 * Makefile.in: Regenerate. 93 * po/opcodes.pot: Regenerate. 94 952021-12-02 Marcus Nilsson <brainbomb@gmail.com> 96 97 * avr-dis.c (avr_operand); Pass in disassemble_info and fill 98 in insn_type on branching instructions. 99 1002021-11-25 Andrew Burgess <aburgess@redhat.com> 101 Simon Cook <simon.cook@embecosm.com> 102 103 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef. 104 (riscv_options): New static global. 105 (disassembler_options_riscv): New function. 106 (print_riscv_disassembler_options): Rewrite to use 107 disassembler_options_riscv. 108 1092021-11-25 Nick Clifton <nickc@redhat.com> 110 111 PR 28614 112 * aarch64-asm.c: Replace assert(0) with real code. 113 * aarch64-dis.c: Likewise. 114 * aarch64-opc.c: Likewise. 115 1162021-11-25 Nick Clifton <nickc@redhat.com> 117 118 * po/fr.po; Updated French translation. 119 1202021-10-27 Maciej W. Rozycki <macro@embecosm.com> 121 122 * Makefile.am: Remove obsolete comment. 123 * configure.ac: Refer `libbfd.la' to link shared BFD library 124 except for Cygwin. 125 * Makefile.in: Regenerate. 126 * configure: Regenerate. 127 1282021-09-27 Nick Alcock <nick.alcock@oracle.com> 129 130 * configure: Regenerate. 131 1322021-09-25 Peter Bergner <bergner@linux.ibm.com> 133 134 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable 135 on POWER5 and later. 136 1372021-09-20 Andrew Burgess <andrew.burgess@embecosm.com> 138 139 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode 140 before an unknown instruction, '%d' is replaced with the 141 instruction length. 142 1432021-09-02 Nick Clifton <nickc@redhat.com> 144 145 PR 28292 146 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place 147 of BFD_RELOC_16. 148 1492021-08-17 Shahab Vahedi <shahab@synopsys.com> 150 151 * arc-regs.h (DEF): Fix the register numbers. 152 1532021-08-10 Nick Clifton <nickc@redhat.com> 154 155 * po/sr.po: Updated Serbian translation. 156 1572021-07-26 Chenghua Xu <xuchenghua@loongson.cn> 158 159 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach. 160 1612021-06-07 Andreas Krebbel <krebbel@linux.ibm.com> 162 163 * s390-opc.txt: Add qpaci. 164 1652021-07-03 Nick Clifton <nickc@redhat.com> 166 167 * configure: Regenerate. 168 * po/opcodes.pot: Regenerate. 169 1702021-07-03 Nick Clifton <nickc@redhat.com> 171 172 * 2.37 release branch created. 173 1742021-07-02 Alan Modra <amodra@gmail.com> 175 176 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return. 177 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg. 178 (nds32_field_table, nds32_opcode_table, nds32_keyword_table), 179 (nds32_opcodes, nds32_operand_fields, nds32_keywords), 180 (nds32_keyword_gpr): Move declarations to.. 181 * nds32-asm.h: ..here, constifying to match definitions. 182 1832021-07-01 Mike Frysinger <vapier@gentoo.org> 184 185 * Makefile.am (GUILE): New variable. 186 (CGEN): Use $(GUILE). 187 * Makefile.in: Regenerate. 188 1892021-07-01 Mike Frysinger <vapier@gentoo.org> 190 191 * mep-asm.c (macros): Mark static & const. 192 (lookup_macro): Change return & m to const. 193 (expand_macro): Change mac to const. 194 (expand_string): Change pmacro to const. 195 1962021-07-01 Mike Frysinger <vapier@gentoo.org> 197 198 * nds32-asm.c (operand_fields): Rename to ... 199 (nds32_operand_fields): ... this. 200 (keyword_gpr): Rename to ... 201 (nds32_keyword_gpr): ... this. 202 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr, 203 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, 204 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st, 205 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator, 206 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx): 207 Mark static. 208 (keywords): Rename to ... 209 (nds32_keywords): ... this. 210 * nds32-dis.c: Rename operand_fields to nds32_operand_fields, 211 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr. 212 2132021-07-01 Mike Frysinger <vapier@gentoo.org> 214 215 * z80-dis.c (opc_ed): Make const. 216 (pref_ed): Make p const. 217 2182021-07-01 Mike Frysinger <vapier@gentoo.org> 219 220 * microblaze-dis.c (get_field_special): Make op const. 221 (read_insn_microblaze): Make opr & op const. Rename opcodes to 222 microblaze_opcodes. 223 (print_insn_microblaze): Make op & pop const. 224 (get_insn_microblaze): Make op const. Rename opcodes to 225 microblaze_opcodes. 226 (microblaze_get_target_address): Likewise. 227 * microblaze-opc.h (struct op_code_struct): Make const. 228 Rename opcodes to microblaze_opcodes. 229 2302021-07-01 Mike Frysinger <vapier@gentoo.org> 231 232 * aarch64-gen.c (aarch64_opcode_table): Add const. 233 * aarch64-tbl.h (aarch64_opcode_table): Likewise. 234 2352021-06-22 Andrew Burgess <andrew.burgess@embecosm.com> 236 237 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when 238 available. 239 2402021-06-22 Alan Modra <amodra@gmail.com> 241 242 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do 243 print separator for pcrel insns. 244 2452021-06-19 Alan Modra <amodra@gmail.com> 246 247 * vax-dis.c (print_insn_vax): Avoid pointer overflow. 248 2492021-06-19 Alan Modra <amodra@gmail.com> 250 251 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill 252 entire buffer. 253 2542021-06-17 Alan Modra <amodra@gmail.com> 255 256 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location 257 in table. 258 2592021-06-03 Alan Modra <amodra@gmail.com> 260 261 PR 1202 262 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly. 263 Use unsigned int for inst. 264 2652021-06-02 Shahab Vahedi <shahab@synopsys.com> 266 267 * arc-dis.c (arc_option_arg_t): New enumeration. 268 (arc_options): New variable. 269 (disassembler_options_arc): New function. 270 (print_arc_disassembler_options): Reimplement in terms of 271 "disassembler_options_arc". 272 2732021-05-29 Alan Modra <amodra@gmail.com> 274 275 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many. 276 Don't special case PPC_OPCODE_RAW. 277 (lookup_prefix): Likewise. 278 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and.. 279 (print_insn_powerpc): ..update caller. 280 * ppc-opc.c (EXT): Define. 281 (powerpc_opcodes): Mark extended mnemonics with EXT. 282 (prefix_opcodes, vle_opcodes): Likewise. 283 (XISEL, XISEL_MASK): Add cr field and simplify. 284 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort 285 all isel variants to where the base mnemonic belongs. Sort dstt, 286 dststt and dssall. 287 2882021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 289 290 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2, 291 COP3 opcode instructions. 292 2932021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 294 295 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for 296 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0", 297 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t", 298 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2", 299 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3", 300 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3", 301 "cop2", and "cop3" entries. 302 3032021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 304 305 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3" 306 entries and associated comments. 307 3082021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 309 310 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead 311 of "c0". 312 3132021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 314 315 * mips-dis.c (mips_cp1_names_mips): New variable. 316 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric' 317 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120", 318 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500", 319 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000", 320 "r12000", "r14000", "r16000", "mips5", "loongson2e", and 321 "loongson2f". 322 3232021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 324 325 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register 326 handling code over to... 327 <OP_REG_CONTROL>: ... this new case. 328 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases. 329 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2", 330 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries 331 replacing the `G' operand code with `g'. Update "cftc1" and 332 "cftc2" entries replacing the `E' operand code with `y'. 333 * micromips-opc.c (decode_micromips_operand) <'g'>: New case. 334 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2" 335 entries replacing the `G' operand code with `g'. 336 3372021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 338 339 * mips-dis.c (mips_cp0_names_r3900): New variable. 340 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric' 341 for "r3900". 342 3432021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 344 345 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2", 346 and "mtthc2" to using the `G' rather than `g' operand code for 347 the coprocessor control register referred. 348 3492021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> 350 351 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1" 352 entries with each other. 353 3542021-05-27 Peter Bergner <bergner@linux.ibm.com> 355 356 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics. 357 3582021-05-25 Alan Modra <amodra@gmail.com> 359 360 * cris-desc.c: Regenerate. 361 * cris-desc.h: Regenerate. 362 * cris-opc.h: Regenerate. 363 * po/POTFILES.in: Regenerate. 364 3652021-05-24 Mike Frysinger <vapier@gentoo.org> 366 367 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h. 368 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c. 369 (CGEN_CPUS): Add cris. 370 (CRIS_DEPS): Define. 371 (stamp-cris): New rule. 372 * cgen.sh: Handle desc action. 373 * configure.ac (bfd_cris_arch): Add cris-desc.lo. 374 * Makefile.in, configure: Regenerate. 375 3762021-05-18 Job Noorman <mtvec@pm.me> 377 378 PR 27814 379 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for 380 the elf objects. 381 3822021-05-17 Alex Coplan <alex.coplan@arm.com> 383 384 * arm-dis.c (mve_opcodes): Fix disassembly of 385 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1. 386 (is_mve_encoding_conflict): MVE vector loads should not match 387 when P = W = 0. 388 (is_mve_unpredictable): It's not unpredictable to use the same 389 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE). 390 3912021-05-11 Nick Clifton <nickc@redhat.com> 392 393 PR 27840 394 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond 395 the end of the code buffer. 396 3972021-05-06 Stafford Horne <shorne@gmail.com> 398 399 PR 21464 400 * or1k-asm.c: Regenerate. 401 4022021-05-01 Max Filippov <jcmvbkbc@gmail.com> 403 404 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and 405 info->insn_info_valid. 406 4072021-04-26 Jan Beulich <jbeulich@suse.com> 408 409 * i386-opc.tbl (lea): Add Optimize. 410 * opcodes/i386-tbl.h: Re-generate. 411 4122020-04-23 Max Filippov <jcmvbkbc@gmail.com> 413 414 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand 415 of l32r fetch and display referenced literal value. 416 4172021-04-23 Max Filippov <jcmvbkbc@gmail.com> 418 419 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk 420 to 4 for literal disassembly. 421 4222021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 423 424 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support 425 for TLBI instruction. 426 4272021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 428 429 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for 430 DC instruction. 431 4322021-04-19 Jan Beulich <jbeulich@suse.com> 433 434 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for 435 "qualifier". 436 (convert_mov_to_movewide): Add initializer for "value". 437 4382021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 439 440 * aarch64-opc.c: Add RME system registers. 441 4422021-04-16 Lifang Xia <lifang_xia@c-sky.com> 443 444 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress 445 "addi d,CV,z" to "c.mv d,CV". 446 4472021-04-12 Alan Modra <amodra@gmail.com> 448 449 * configure.ac (--enable-checking): Add support. 450 * config.in: Regenerate. 451 * configure: Regenerate. 452 4532021-04-09 Tejas Belagod <tejas.belagod@arm.com> 454 455 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify 456 LD64/ST64 instructions to lse_atomic instead of ldstexcl. 457 4582021-04-09 Alan Modra <amodra@gmail.com> 459 460 * ppc-dis.c (struct dis_private): Add "special". 461 (POWERPC_DIALECT): Delete. Replace uses with.. 462 (private_data): ..this. New inline function. 463 (disassemble_init_powerpc): Init "special" names. 464 (skip_optional_operands): Add is_pcrel arg, set when detecting R 465 field of prefix instructions. 466 (bsearch_reloc, print_got_plt): New functions. 467 (print_insn_powerpc): For pcrel instructions, print target address 468 and symbol if known, and decode plt and got loads too. 469 4702021-04-08 Alan Modra <amodra@gmail.com> 471 472 PR 27684 473 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir. 474 4752021-04-08 Alan Modra <amodra@gmail.com> 476 477 PR 27676 478 * ppc-opc.c (DCBT_EO): Move earlier. 479 (insert_thct, extract_thct, insert_thds, extract_thds): New functions. 480 (powerpc_operands): Add THCT and THDS entries. 481 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds. 482 4832021-04-06 Alan Modra <amodra@gmail.com> 484 485 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL. 486 * s12z-dis.c (decode_possible_symbol): Use symbol returned from 487 symbol_at_address_func. 488 4892021-04-05 Alan Modra <amodra@gmail.com> 490 491 * configure.ac: Don't check for limits.h, string.h, strings.h or 492 stdlib.h. 493 (AC_ISC_POSIX): Don't invoke. 494 * sysdep.h: Include stdlib.h and string.h unconditionally. 495 * i386-opc.h: Include limits.h unconditionally. 496 * wasm32-dis.c: Likewise. 497 * cgen-opc.c: Don't include alloca-conf.h. 498 * config.in: Regenerate. 499 * configure: Regenerate. 500 5012021-04-01 Martin Liska <mliska@suse.cz> 502 503 * arm-dis.c (strneq): Remove strneq and use startswith. 504 * cr16-dis.c (print_insn_cr16): Likewise. 505 * score-dis.c (streq): Likewise. 506 (strneq): Likewise. 507 * score7-dis.c (strneq): Likewise. 508 5092021-04-01 Alan Modra <amodra@gmail.com> 510 511 PR 27675 512 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2. 513 5142021-03-31 Alan Modra <amodra@gmail.com> 515 516 * sysdep.h (POISON_BFD_BOOLEAN): Define. 517 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h, 518 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h, 519 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c, 520 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c, 521 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c, 522 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c, 523 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c, 524 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c, 525 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c, 526 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c, 527 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c, 528 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c, 529 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false, 530 and TRUE with true throughout. 531 5322021-03-31 Alan Modra <amodra@gmail.com> 533 534 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h. 535 * aarch64-dis.h: Likewise. 536 * aarch64-opc.c: Likewise. 537 * avr-dis.c: Likewise. 538 * csky-dis.c: Likewise. 539 * nds32-asm.c: Likewise. 540 * nds32-dis.c: Likewise. 541 * nfp-dis.c: Likewise. 542 * riscv-dis.c: Likewise. 543 * s12z-dis.c: Likewise. 544 * wasm32-dis.c: Likewise. 545 5462021-03-30 Jan Beulich <jbeulich@suse.com> 547 548 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete. 549 (i386_seg_prefixes): New. 550 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete. 551 (i386_seg_prefixes): Declare. 552 5532021-03-30 Jan Beulich <jbeulich@suse.com> 554 555 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete. 556 5572021-03-30 Jan Beulich <jbeulich@suse.com> 558 559 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values. 560 * i386-reg.tbl (st): Move down. 561 (st(0)): Delete. Extend comment. 562 * i386-tbl.h: Re-generate. 563 5642021-03-29 Jan Beulich <jbeulich@suse.com> 565 566 * i386-opc.tbl (movq, movabs): Move next to mov counterparts. 567 (cmpsd): Move next to cmps. 568 (movsd): Move next to movs. 569 (cmpxchg16b): Move to separate section. 570 (fisttp, fisttpll): Likewise. 571 (monitor, mwait): Likewise. 572 * i386-tbl.h: Re-generate. 573 5742021-03-29 Jan Beulich <jbeulich@suse.com> 575 576 * i386-opc.tbl (psadbw): Add <sse2:comm>. 577 (vpsadbw): Add C. 578 * i386-tbl.h: Re-generate. 579 5802021-03-29 Jan Beulich <jbeulich@suse.com> 581 582 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes, 583 pclmul, gfni): New templates. Use them wherever possible. Move 584 SSE4.1 pextrw into respective section. 585 * i386-tbl.h: Re-generate. 586 5872021-03-29 Jan Beulich <jbeulich@suse.com> 588 589 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use 590 strtoull(). Bump upper loop bound. Widen masks. Sanity check 591 "length". 592 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete. 593 Convert all of their uses to representation in opcode. 594 5952021-03-29 Jan Beulich <jbeulich@suse.com> 596 597 * i386-opc.h (struct insn_template): Shrink base_opcode to 16 598 bits. Shrink extension_opcode to 9 bits. Make it signed. Change 599 value of None. Shrink operands to 3 bits. 600 6012021-03-29 Jan Beulich <jbeulich@suse.com> 602 603 * i386-gen.c (process_i386_opcode_modifier): New parameter 604 "space". 605 (output_i386_opcode): New local variable "space". Adjust 606 process_i386_opcode_modifier() invocation. 607 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 608 invocation. 609 * i386-tbl.h: Re-generate. 610 6112021-03-29 Alan Modra <amodra@gmail.com> 612 613 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. 614 (fp_qualifier_p, get_data_pattern): Likewise. 615 (aarch64_get_operand_modifier_from_value): Likewise. 616 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. 617 (operand_variant_qualifier_p): Likewise. 618 (qualifier_value_in_range_constraint_p): Likewise. 619 (aarch64_get_qualifier_esize): Likewise. 620 (aarch64_get_qualifier_nelem): Likewise. 621 (aarch64_get_qualifier_standard_value): Likewise. 622 (get_lower_bound, get_upper_bound): Likewise. 623 (aarch64_find_best_match, match_operands_qualifier): Likewise. 624 (aarch64_print_operand): Likewise. 625 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. 626 (operand_need_sign_extension, operand_need_shift_by_two): Likewise. 627 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. 628 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. 629 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. 630 (print_insn_tic6x): Likewise. 631 6322021-03-29 Alan Modra <amodra@gmail.com> 633 634 * arc-dis.c (extract_operand_value): Correct NULL cast. 635 * frv-opc.h: Regenerate. 636 6372021-03-26 Jan Beulich <jbeulich@suse.com> 638 639 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to 640 MMX form. 641 * i386-tbl.h: Re-generate. 642 6432021-03-25 Abid Qadeer <abidh@codesourcery.com> 644 645 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of 646 immediate in br.n instruction. 647 6482021-03-25 Jan Beulich <jbeulich@suse.com> 649 650 * i386-dis.c (XMGatherD, VexGatherD): New. 651 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*. 652 (print_insn): Check masking for S/G insns. 653 (OP_E_memory): New local variable check_gather. Extend mandatory 654 SIB check. Check register conflicts for (EVEX-encoded) gathers. 655 Extend check for disallowed 16-bit addressing. 656 (OP_VEX): New local variables modrm_reg and sib_index. Convert 657 if()s to switch(). Check register conflicts for (VEX-encoded) 658 gathers. Drop no longer reachable cases. 659 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and 660 vgatherdp*. 661 6622021-03-25 Jan Beulich <jbeulich@suse.com> 663 664 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying 665 zeroing-masking without masking. 666 6672021-03-25 Jan Beulich <jbeulich@suse.com> 668 669 * i386-opc.tbl (invlpgb): Fix multi-operand form. 670 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark 671 single-operand forms as deprecated. 672 * i386-tbl.h: Re-generate. 673 6742021-03-25 Alan Modra <amodra@gmail.com> 675 676 PR 27647 677 * ppc-opc.c (XLOCB_MASK): Delete. 678 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using 679 XLBH_MASK. 680 (powerpc_opcodes): Accept a BH field on all extended forms of 681 bclr, bclrl, bcctr, bcctrl, bctar, bctarl. 682 6832021-03-24 Jan Beulich <jbeulich@suse.com> 684 685 * i386-gen.c (output_i386_opcode): Drop processing of 686 opcode_length. Calculate length from base_opcode. Adjust prefix 687 encoding determination. 688 (process_i386_opcodes): Drop output of fake opcode_length. 689 * i386-opc.h (struct insn_template): Drop opcode_length field. 690 * i386-opc.tbl: Drop opcode length field from all templates. 691 * i386-tbl.h: Re-generate. 692 6932021-03-24 Jan Beulich <jbeulich@suse.com> 694 695 * i386-gen.c (process_i386_opcode_modifier): Return void. New 696 parameter "prefix". Drop local variable "regular_encoding". 697 Record prefix setting / check for consistency. 698 (output_i386_opcode): Parse opcode_length and base_opcode 699 earlier. Derive prefix encoding. Drop no longer applicable 700 consistency checking. Adjust process_i386_opcode_modifier() 701 invocation. 702 (process_i386_opcodes): Adjust process_i386_opcode_modifier() 703 invocation. 704 * i386-tbl.h: Re-generate. 705 7062021-03-24 Jan Beulich <jbeulich@suse.com> 707 708 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix 709 check. 710 * i386-opc.h (Prefix_*): Move #define-s. 711 * i386-opc.tbl: Move pseudo prefix enumerator values to 712 extension opcode field. Introduce pseudopfx template. 713 * i386-tbl.h: Re-generate. 714 7152021-03-23 Jan Beulich <jbeulich@suse.com> 716 717 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend 718 comment. 719 * i386-tbl.h: Re-generate. 720 7212021-03-23 Jan Beulich <jbeulich@suse.com> 722 723 * i386-opc.h (struct insn_template): Move cpu_flags field past 724 opcode_modifier one. 725 * i386-tbl.h: Re-generate. 726 7272021-03-23 Jan Beulich <jbeulich@suse.com> 728 729 * i386-gen.c (opcode_modifiers): New OpcodeSpace element. 730 * i386-opc.h (OpcodeSpace): New enumerator. 731 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ... 732 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08, 733 SPACE_XOP09, SPACE_XOP0A): ... respectively. 734 (struct i386_opcode_modifier): New field opcodespace. Shrink 735 opcodeprefix field. 736 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08, 737 SpaceXOP09, SpaceXOP0A): Define. Use them to replace 738 OpcodePrefix uses. 739 * i386-tbl.h: Re-generate. 740 7412021-03-22 Martin Liska <mliska@suse.cz> 742 743 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. 744 * arc-dis.c (parse_option): Likewise. 745 * arm-dis.c (parse_arm_disassembler_options): Likewise. 746 * cris-dis.c (print_with_operands): Likewise. 747 * h8300-dis.c (bfd_h8_disassemble): Likewise. 748 * i386-dis.c (print_insn): Likewise. 749 * ia64-gen.c (fetch_insn_class): Likewise. 750 (parse_resource_users): Likewise. 751 (in_iclass): Likewise. 752 (lookup_specifier): Likewise. 753 (insert_opcode_dependencies): Likewise. 754 * mips-dis.c (parse_mips_ase_option): Likewise. 755 (parse_mips_dis_option): Likewise. 756 * s390-dis.c (disassemble_init_s390): Likewise. 757 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise. 758 7592021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> 760 761 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. 762 7632021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> 764 765 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, 766 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. 767 7682021-03-12 Alan Modra <amodra@gmail.com> 769 770 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo. 771 7722021-03-11 Jan Beulich <jbeulich@suse.com> 773 774 * i386-dis.c (OP_XMM): Re-order checks. 775 7762021-03-11 Jan Beulich <jbeulich@suse.com> 777 778 * i386-dis.c (putop): Drop need_vex check when also checking 779 vex.evex. 780 (intel_operand_size, OP_E_memory): Drop vex.evex check when also 781 checking vex.b. 782 7832021-03-11 Jan Beulich <jbeulich@suse.com> 784 785 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast 786 checks. Move case label past broadcast check. 787 7882021-03-10 Jan Beulich <jbeulich@suse.com> 789 790 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX, 791 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode, 792 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1, 793 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3, 794 EVEX_W_0F38C7_M_0_L_2): Delete. 795 (REG_EVEX_0F38C7_M_0_L_2): New. 796 (intel_operand_size): Handle VEX and EVEX the same for 797 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop 798 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases. 799 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and 800 vex_vsib_q_w_d_mode uses. 801 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893, 802 0F38A1, and 0F38A3 entries. 803 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7 804 entry. 805 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries. 806 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and 807 0F38A3 entries. 808 8092021-03-10 Jan Beulich <jbeulich@suse.com> 810 811 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, 812 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, 813 MOD_VEX_0FXOP_09_12): Rename to ... 814 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, 815 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. 816 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, 817 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, 818 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 819 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. 820 (reg_table): Adjust comments. 821 (x86_64_table): Move X86_64_0F24, X86_64_0F26, 822 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, 823 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. 824 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. 825 (vex_len_table): Adjust opcode 0A_12 entry. 826 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, 827 MOD_C5_32BIT, and MOD_XOP_09_12 entries. 828 (rm_table): Move hreset entry. 829 8302021-03-10 Jan Beulich <jbeulich@suse.com> 831 832 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, 833 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, 834 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, 835 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, 836 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. 837 (EVEX_LEN_0F3816, EVEX_W_0FD6): New. 838 (get_valid_dis386): Also handle 512-bit vector length when 839 vectoring into vex_len_table[]. 840 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, 841 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 842 entries. 843 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, 844 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. 845 * i386-dis-evex-prefix.h: Adjust 0F7E entry. 846 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 847 entries. 848 8492021-03-10 Jan Beulich <jbeulich@suse.com> 850 851 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): 852 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. 853 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. 854 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 855 entries. 856 * i386-dis-evex-len.h (evex_len_table): Likewise. 857 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. 858 8592021-03-10 Jan Beulich <jbeulich@suse.com> 860 861 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, 862 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, 863 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, 864 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, 865 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, 866 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, 867 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, 868 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 869 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, 870 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, 871 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, 872 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, 873 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, 874 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, 875 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, 876 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, 877 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, 878 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, 879 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, 880 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, 881 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, 882 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, 883 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, 884 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, 885 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, 886 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, 887 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, 888 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, 889 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, 890 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, 891 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, 892 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. 893 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, 894 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, 895 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, 896 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, 897 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, 898 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, 899 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, 900 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, 901 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, 902 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, 903 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, 904 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, 905 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, 906 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, 907 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, 908 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, 909 EVEX_W_0F3A43_L_n): New. 910 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, 911 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 912 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. 913 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] 914 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, 915 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 916 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. 917 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, 918 0F385B, 0F38C6, and 0F38C7 entries. 919 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes 920 0F38C6 and 0F38C7. 921 * i386-dis-evex-w.h: No longer link to evex_len_table[] for 922 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 923 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to 924 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. 925 9262021-03-10 Jan Beulich <jbeulich@suse.com> 927 928 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, 929 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, 930 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, 931 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, 932 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, 933 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, 934 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, 935 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, 936 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, 937 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, 938 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, 939 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, 940 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, 941 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, 942 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, 943 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, 944 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, 945 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, 946 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, 947 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, 948 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, 949 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, 950 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, 951 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, 952 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, 953 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, 954 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, 955 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, 956 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, 957 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, 958 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, 959 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, 960 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, 961 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, 962 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, 963 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, 964 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, 965 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, 966 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, 967 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, 968 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, 969 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, 970 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, 971 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, 972 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, 973 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, 974 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, 975 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, 976 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, 977 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, 978 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, 979 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, 980 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, 981 VEX_W_0F99_P_2_LEN_0): Delete. 982 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, 983 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, 984 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, 985 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, 986 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, 987 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, 988 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, 989 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, 990 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, 991 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, 992 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, 993 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, 994 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, 995 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, 996 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, 997 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, 998 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, 999 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, 1000 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, 1001 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, 1002 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, 1003 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, 1004 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, 1005 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, 1006 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, 1007 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, 1008 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. 1009 (prefix_table): No longer link to vex_len_table[] for opcodes 1010 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 1011 0F92, 0F93, 0F98, and 0F99. 1012 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, 1013 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1014 0F98, and 0F99. 1015 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, 1016 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1017 0F98, and 0F99. 1018 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, 1019 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1020 0F98, and 0F99. 1021 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, 1022 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, 1023 0F98, and 0F99. 1024 10252021-03-10 Jan Beulich <jbeulich@suse.com> 1026 1027 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): 1028 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and 1029 REG_VEX_0F73_M_0 respectively. 1030 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, 1031 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, 1032 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, 1033 MOD_VEX_0F73_REG_7): Delete. 1034 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. 1035 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, 1036 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, 1037 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, 1038 PREFIX_VEX_0F3AF0_L_0 respectively. 1039 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, 1040 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, 1041 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, 1042 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. 1043 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, 1044 VEX_LEN_0F38F7): New. 1045 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. 1046 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, 1047 0F72, and 0F73. No longer link to vex_len_table[] for opcode 1048 0F38F3. 1049 (prefix_table): No longer link to vex_len_table[] for opcodes 1050 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1051 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and 1052 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, 1053 0F38F6, 0F38F7, and 0F3AF0. 1054 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to 1055 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. 1056 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and 1057 0F73. 1058 10592021-03-10 Jan Beulich <jbeulich@suse.com> 1060 1061 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to 1062 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. 1063 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, 1064 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, 1065 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. 1066 (MOD_0F71, MOD_0F72, MOD_0F73): New. 1067 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and 1068 73. 1069 (reg_table): No longer link to mod_table[] for opcodes 0F71, 1070 0F72, and 0F73. 1071 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and 1072 0F73. 1073 10742021-03-10 Jan Beulich <jbeulich@suse.com> 1075 1076 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, 1077 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. 1078 (reg_table): Don't link to mod_table[] where not needed. Add 1079 PREFIX_IGNORED to nop entries. 1080 (prefix_table): Replace PREFIX_OPCODE in nop entries. 1081 (mod_table): Add nop entries next to prefetch ones. Drop 1082 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and 1083 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. 1084 (rm_table): Add PREFIX_IGNORED to nop entries. Drop 1085 PREFIX_OPCODE from endbr* entries. 1086 (get_valid_dis386): Also consider entry's name when zapping 1087 vindex. 1088 (print_insn): Handle PREFIX_IGNORED. 1089 10902021-03-09 Jan Beulich <jbeulich@suse.com> 1091 1092 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, 1093 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk 1094 element. 1095 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, 1096 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. 1097 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, 1098 PrefixLock, PrefixHLELock, PrefixHLEAny): Define. 1099 (struct i386_opcode_modifier): Delete notrackprefixok, 1100 islockable, hleprefixok, and repprefixok fields. Add prefixok 1101 field. 1102 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, 1103 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. 1104 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, 1105 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): 1106 Replace HLEPrefixOk. 1107 * opcodes/i386-tbl.h: Re-generate. 1108 11092021-03-09 Jan Beulich <jbeulich@suse.com> 1110 1111 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. 1112 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from 1113 64-bit form. 1114 * opcodes/i386-tbl.h: Re-generate. 1115 11162021-03-03 Jan Beulich <jbeulich@suse.com> 1117 1118 * i386-gen.c (output_i386_opcode): Don't get operand count. Look 1119 for {} instead of {0}. Don't look for '0'. 1120 * i386-opc.tbl: Drop operand count field. Drop redundant operand 1121 size specifiers. 1122 11232021-02-19 Nelson Chu <nelson.chu@sifive.com> 1124 1125 PR 27158 1126 * riscv-dis.c (print_insn_args): Updated encoding macros. 1127 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. 1128 (match_c_addi16sp): Updated encoding macros. 1129 (match_c_lui): Likewise. 1130 (match_c_lui_with_hint): Likewise. 1131 (match_c_addi4spn): Likewise. 1132 (match_c_slli): Likewise. 1133 (match_slli_as_c_slli): Likewise. 1134 (match_c_slli64): Likewise. 1135 (match_srxi_as_c_srxi): Likewise. 1136 (riscv_insn_types): Added .insn css/cl/cs. 1137 11382021-02-18 Nelson Chu <nelson.chu@sifive.com> 1139 1140 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. 1141 (default_priv_spec): Updated type to riscv_spec_class. 1142 (parse_riscv_dis_option): Updated. 1143 * riscv-opc.c: Moved stuff and make the file tidy. 1144 11452021-02-17 Alan Modra <amodra@gmail.com> 1146 1147 * wasm32-dis.c: Include limits.h. 1148 (CHAR_BIT): Provide backup define. 1149 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. 1150 Correct signed overflow checking. 1151 11522021-02-16 Jan Beulich <jbeulich@suse.com> 1153 1154 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. 1155 * i386-tbl.h: Re-generate. 1156 11572021-02-16 Jan Beulich <jbeulich@suse.com> 1158 1159 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor 1160 Oword. 1161 * i386-opc.tbl (CpuFP, Mmword, Oword): Define. 1162 11632021-02-15 Andreas Krebbel <krebbel@linux.ibm.com> 1164 1165 * s390-mkopc.c (main): Accept arch14 as cpu string. 1166 * s390-opc.txt: Add new arch14 instructions. 1167 11682021-02-04 Nick Alcock <nick.alcock@oracle.com> 1169 1170 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in 1171 favour of LIBINTL. 1172 * configure: Regenerated. 1173 11742021-02-08 Mike Frysinger <vapier@gentoo.org> 1175 1176 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. 1177 * tic54x-opc.c (regs): Rename to ... 1178 (tic54x_regs): ... this. 1179 (mmregs): Rename to ... 1180 (tic54x_mmregs): ... this. 1181 (condition_codes): Rename to ... 1182 (tic54x_condition_codes): ... this. 1183 (cc2_codes): Rename to ... 1184 (tic54x_cc2_codes): ... this. 1185 (cc3_codes): Rename to ... 1186 (tic54x_cc3_codes): ... this. 1187 (status_bits): Rename to ... 1188 (tic54x_status_bits): ... this. 1189 (misc_symbols): Rename to ... 1190 (tic54x_misc_symbols): ... this. 1191 11922021-02-04 Nelson Chu <nelson.chu@sifive.com> 1193 1194 * riscv-opc.c (MASK_RVB_IMM): Removed. 1195 (riscv_opcodes): Removed zb* instructions. 1196 (riscv_ext_version_table): Removed versions for zb*. 1197 11982021-01-26 Alan Modra <amodra@gmail.com> 1199 1200 * i386-gen.c (parse_template): Ensure entire template_instance 1201 is initialised. 1202 12032021-01-15 Nelson Chu <nelson.chu@sifive.com> 1204 1205 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. 1206 (riscv_fpr_names_abi): Likewise. 1207 (riscv_opcodes): Likewise. 1208 (riscv_insn_types): Likewise. 1209 12102021-01-15 Nelson Chu <nelson.chu@sifive.com> 1211 1212 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. 1213 12142021-01-15 Nelson Chu <nelson.chu@sifive.com> 1215 1216 * riscv-dis.c: Comments tidy and improvement. 1217 * riscv-opc.c: Likewise. 1218 12192021-01-13 Alan Modra <amodra@gmail.com> 1220 1221 * Makefile.in: Regenerate. 1222 12232021-01-12 H.J. Lu <hongjiu.lu@intel.com> 1224 1225 PR binutils/26792 1226 * configure.ac: Use GNU_MAKE_JOBSERVER. 1227 * aclocal.m4: Regenerated. 1228 * configure: Likewise. 1229 12302021-01-12 Nick Clifton <nickc@redhat.com> 1231 1232 * po/sr.po: Updated Serbian translation. 1233 12342021-01-11 H.J. Lu <hongjiu.lu@intel.com> 1235 1236 PR ld/27173 1237 * configure: Regenerated. 1238 12392021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> 1240 1241 * aarch64-asm-2.c: Regenerate. 1242 * aarch64-dis-2.c: Likewise. 1243 * aarch64-opc-2.c: Likewise. 1244 * aarch64-opc.c (aarch64_print_operand): 1245 Delete handling of AARCH64_OPND_CSRE_CSR. 1246 * aarch64-tbl.h (aarch64_feature_csre): Delete. 1247 (CSRE): Likewise. 1248 (_CSRE_INSN): Likewise. 1249 (aarch64_opcode_table): Delete csr. 1250 12512021-01-11 Nick Clifton <nickc@redhat.com> 1252 1253 * po/de.po: Updated German translation. 1254 * po/fr.po: Updated French translation. 1255 * po/pt_BR.po: Updated Brazilian Portuguese translation. 1256 * po/sv.po: Updated Swedish translation. 1257 * po/uk.po: Updated Ukranian translation. 1258 12592021-01-09 H.J. Lu <hongjiu.lu@intel.com> 1260 1261 * configure: Regenerated. 1262 12632021-01-09 Nick Clifton <nickc@redhat.com> 1264 1265 * configure: Regenerate. 1266 * po/opcodes.pot: Regenerate. 1267 12682021-01-09 Nick Clifton <nickc@redhat.com> 1269 1270 * 2.36 release branch crated. 1271 12722021-01-08 Peter Bergner <bergner@linux.ibm.com> 1273 1274 * ppc-opc.c (insert_dw, (extract_dw): New functions. 1275 (DW, (XRC_MASK): Define. 1276 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. 1277 12782021-01-09 Alan Modra <amodra@gmail.com> 1279 1280 * configure: Regenerate. 1281 12822021-01-08 Nick Clifton <nickc@redhat.com> 1283 1284 * po/sv.po: Updated Swedish translation. 1285 12862021-01-08 Nick Clifton <nickc@redhat.com> 1287 1288 PR 27129 1289 * aarch64-dis.c (determine_disassembling_preference): Move call to 1290 aarch64_match_operands_constraint outside of the assertion. 1291 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. 1292 Replace with a return of FALSE. 1293 1294 PR 27139 1295 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a 1296 core system register. 1297 12982021-01-07 Samuel Thibault <samuel.thibault@gnu.org> 1299 1300 * configure: Regenerate. 1301 13022021-01-07 Nick Clifton <nickc@redhat.com> 1303 1304 * po/fr.po: Updated French translation. 1305 13062021-01-07 Fredrik Noring <noring@nocrew.org> 1307 1308 * m68k-opc.c (chkl): Change minimum architecture requirement to 1309 m68020. 1310 13112021-01-07 Philipp Tomsich <prt@gnu.org> 1312 1313 * riscv-opc.c (riscv_opcodes): Add pause hint instruction. 1314 13152021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> 1316 Jim Wilson <jimw@sifive.com> 1317 Andrew Waterman <andrew@sifive.com> 1318 Maxim Blinov <maxim.blinov@embecosm.com> 1319 Kito Cheng <kito.cheng@sifive.com> 1320 Nelson Chu <nelson.chu@sifive.com> 1321 1322 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. 1323 (MASK_RVB_IMM): Used for rev8 and orc.b encoding. 1324 13252021-01-01 Alan Modra <amodra@gmail.com> 1326 1327 Update year range in copyright notice of all files. 1328 1329For older changes see ChangeLog-2020 1330 1331Copyright (C) 2021-2022 Free Software Foundation, Inc. 1332 1333Copying and distribution of this file, with or without modification, 1334are permitted in any medium without royalty provided the copyright 1335notice and this notice are preserved. 1336 1337Local Variables: 1338mode: change-log 1339left-margin: 8 1340fill-column: 74 1341version-control: never 1342End: 1343