1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003-2017 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 21 #include "arch/xtensa.h" 22 23 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 24 whenever the "tdep" structure changes in an incompatible way. */ 25 26 #define XTENSA_TDEP_VERSION 0x60 27 28 /* Xtensa register type. */ 29 30 typedef enum 31 { 32 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 33 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 34 xtRegisterTypeUserReg, /* User defined registers (rur). */ 35 xtRegisterTypeTieRegfile, /* User define register files. */ 36 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 37 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 38 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 39 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 40 xtRegisterTypeVirtual, /* PC, FP. */ 41 xtRegisterTypeUnknown 42 } xtensa_register_type_t; 43 44 45 /* Xtensa register group. */ 46 47 #define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ 48 49 typedef enum 50 { 51 xtRegisterGroupUnknown = 0, 52 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 53 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 54 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 55 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 56 xtRegisterGroupState = 0x0010, /* States. */ 57 58 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 59 xtRegisterGroupUser = 0x0200, /* User registers. */ 60 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 61 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 62 xtRegisterGroupSystem = 0x1000, /* System. */ 63 64 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ 65 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 66 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 67 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 68 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 69 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 70 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 71 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 72 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 73 74 } xtensa_register_group_t; 75 76 77 /* Xtensa target flags. */ 78 79 typedef enum 80 { 81 xtTargetFlagsNonVisibleRegs = 0x0001, 82 xtTargetFlagsUseFetchStore = 0x0002, 83 } xtensa_target_flags_t; 84 85 86 /* Mask. */ 87 88 typedef struct 89 { 90 int reg_num; 91 int bit_start; 92 int bit_size; 93 } xtensa_reg_mask_t; 94 95 typedef struct 96 { 97 int count; 98 xtensa_reg_mask_t *mask; 99 } xtensa_mask_t; 100 101 102 /* Xtensa register representation. */ 103 104 typedef struct 105 { 106 const char *name; /* Register name. */ 107 int offset; /* Offset. */ 108 xtensa_register_type_t type; /* Register type. */ 109 xtensa_register_group_t group;/* Register group. */ 110 struct type* ctype; /* C-type. */ 111 int bit_size; /* The actual bit size in the target. */ 112 int byte_size; /* Actual space allocated in registers[]. */ 113 int align; /* Alignment for this register. */ 114 115 unsigned int target_number; /* Register target number. */ 116 117 int flags; /* Flags. */ 118 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ 119 120 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 121 const char *fetch; /* Instruction sequence to fetch register. */ 122 const char *store; /* Instruction sequence to store register. */ 123 } xtensa_register_t; 124 125 /* For xtensa-config.c to expand to the structure above. */ 126 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ 127 {#name, ofs, (xtensa_register_type_t) (ty), \ 128 ((xtensa_register_group_t) \ 129 ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \ 130 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, 131 #define XTREG_END \ 132 {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \ 133 0, 0, 0, 0, -1, 0, 0, 0, 0, 0}, 134 135 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 136 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 137 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 138 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 139 140 /* Call-ABI for stack frame. */ 141 142 typedef enum 143 { 144 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 145 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 146 } call_abi_t; 147 148 149 struct ctype_cache 150 { 151 struct ctype_cache *next; 152 int size; 153 struct type *virtual_type; 154 }; 155 156 /* Xtensa-specific target dependencies. */ 157 158 struct gdbarch_tdep 159 { 160 unsigned int target_flags; 161 162 /* Spill location for TIE register files under ocd. */ 163 164 unsigned int spill_location; 165 unsigned int spill_size; 166 167 char *unused; /* Placeholder for compatibility. */ 168 call_abi_t call_abi; /* Calling convention. */ 169 170 /* CPU configuration. */ 171 172 unsigned int debug_interrupt_level; 173 174 unsigned int icache_line_bytes; 175 unsigned int dcache_line_bytes; 176 unsigned int dcache_writeback; 177 178 unsigned int isa_use_windowed_registers; 179 unsigned int isa_use_density_instructions; 180 unsigned int isa_use_exceptions; 181 unsigned int isa_use_ext_l32r; 182 unsigned int isa_max_insn_size; /* Maximum instruction length. */ 183 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ 184 unsigned int debug_num_dbreaks; 185 186 /* Register map. */ 187 188 xtensa_register_t* regmap; 189 190 unsigned int num_regs; /* Number of registers in register map. */ 191 unsigned int num_nopriv_regs; /* Number of non-privileged registers. */ 192 unsigned int num_pseudo_regs; /* Number of pseudo registers. */ 193 unsigned int num_aregs; /* Size of register file. */ 194 unsigned int num_contexts; 195 196 int ar_base; /* Register number for AR0. */ 197 int a0_base; /* Register number for A0 (pseudo). */ 198 int wb_regnum; /* Register number for WB. */ 199 int ws_regnum; /* Register number for WS. */ 200 int pc_regnum; /* Register number for PC. */ 201 int ps_regnum; /* Register number for PS. */ 202 int lbeg_regnum; /* Register numbers for count regs. */ 203 int lend_regnum; 204 int lcount_regnum; 205 int sar_regnum; /* Register number of SAR. */ 206 int litbase_regnum; /* Register number of LITBASE. */ 207 int threadptr_regnum; /* Register number of THREADPTR. */ 208 209 int interrupt_regnum; /* Register number for interrupt. */ 210 int interrupt2_regnum; /* Register number for interrupt2. */ 211 int cpenable_regnum; /* Register number for cpenable. */ 212 int debugcause_regnum; /* Register number for debugcause. */ 213 int exccause_regnum; /* Register number for exccause. */ 214 int excvaddr_regnum; /* Register number for excvaddr. */ 215 216 int max_register_raw_size; 217 int max_register_virtual_size; 218 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ 219 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ 220 unsigned long *gregmap; 221 222 /* Cached register types. */ 223 struct ctype_cache *type_entries; 224 }; 225 226 /* Macro to instantiate a gdbarch_tdep structure. */ 227 228 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ 229 { \ 230 0, /* target_flags */ \ 231 -1, /* spill_location */ \ 232 (spillsz), /* spill_size */ \ 233 0, /* unused */ \ 234 (XSHAL_ABI == XTHAL_ABI_CALL0 \ 235 ? CallAbiCall0Only \ 236 : CallAbiDefault), /* call_abi */ \ 237 XCHAL_DEBUGLEVEL, /* debug_interrupt_level */ \ 238 XCHAL_ICACHE_LINESIZE, /* icache_line_bytes */ \ 239 XCHAL_DCACHE_LINESIZE, /* dcache_line_bytes */ \ 240 XCHAL_DCACHE_IS_WRITEBACK, /* dcache_writeback */ \ 241 (XSHAL_ABI != XTHAL_ABI_CALL0), /* isa_use_windowed_registers */ \ 242 XCHAL_HAVE_DENSITY, /* isa_use_density_instructions */ \ 243 XCHAL_HAVE_EXCEPTIONS, /* isa_use_exceptions */ \ 244 XSHAL_USE_ABSOLUTE_LITERALS, /* isa_use_ext_l32r */ \ 245 XCHAL_MAX_INSTRUCTION_SIZE, /* isa_max_insn_size */ \ 246 XCHAL_NUM_IBREAK, /* debug_num_ibreaks */ \ 247 XCHAL_NUM_DBREAK, /* debug_num_dbreaks */ \ 248 rmap, /* regmap */ \ 249 0, /* num_regs */ \ 250 0, /* num_nopriv_regs */ \ 251 0, /* num_pseudo_regs */ \ 252 XCHAL_NUM_AREGS, /* num_aregs */ \ 253 XCHAL_NUM_CONTEXTS, /* num_contexts */ \ 254 -1, /* ar_base */ \ 255 -1, /* a0_base */ \ 256 -1, /* wb_regnum */ \ 257 -1, /* ws_regnum */ \ 258 -1, /* pc_regnum */ \ 259 -1, /* ps_regnum */ \ 260 -1, /* lbeg_regnum */ \ 261 -1, /* lend_regnum */ \ 262 -1, /* lcount_regnum */ \ 263 -1, /* sar_regnum */ \ 264 -1, /* litbase_regnum */ \ 265 -1, /* interrupt_regnum */ \ 266 -1, /* interrupt2_regnum */ \ 267 -1, /* cpenable_regnum */ \ 268 -1, /* debugcause_regnum */ \ 269 -1, /* exccause_regnum */ \ 270 -1, /* excvaddr_regnum */ \ 271 0, /* max_register_raw_size */ \ 272 0, /* max_register_virtual_size */ \ 273 0, /* fp_layout */ \ 274 0, /* fp_layout_bytes */ \ 275 0, /* gregmap */ \ 276 } 277 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ 278 struct gdbarch_tdep xtensa_tdep = \ 279 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); 280 281 #ifndef XCHAL_NUM_CONTEXTS 282 #define XCHAL_NUM_CONTEXTS 0 283 #endif 284 #ifndef XCHAL_HAVE_EXCEPTIONS 285 #define XCHAL_HAVE_EXCEPTIONS 1 286 #endif 287 #define WB_SHIFT 2 288 289 /* We assign fixed numbers to the registers of the "current" window 290 (i.e., relative to WB). The registers get remapped via the reg_map 291 data structure to their corresponding register in the AR register 292 file (see xtensa-tdep.c). */ 293 294