1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef XTENSA_TDEP_H 21 #define XTENSA_TDEP_H 22 23 #include "arch/xtensa.h" 24 #include "gdbarch.h" 25 #include "xtensa-config.h" 26 27 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 28 whenever the "tdep" structure changes in an incompatible way. */ 29 30 #define XTENSA_TDEP_VERSION 0x60 31 32 /* Xtensa register type. */ 33 34 enum xtensa_register_type_t 35 { 36 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 37 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 38 xtRegisterTypeUserReg, /* User defined registers (rur). */ 39 xtRegisterTypeTieRegfile, /* User define register files. */ 40 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 41 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 42 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 43 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 44 xtRegisterTypeVirtual, /* PC, FP. */ 45 xtRegisterTypeUnknown 46 }; 47 48 49 /* Xtensa register group. */ 50 51 #define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ 52 53 enum xtensa_register_group_t 54 { 55 xtRegisterGroupUnknown = 0, 56 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 57 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 58 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 59 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 60 xtRegisterGroupState = 0x0010, /* States. */ 61 62 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 63 xtRegisterGroupUser = 0x0200, /* User registers. */ 64 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 65 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 66 xtRegisterGroupSystem = 0x1000, /* System. */ 67 68 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ 69 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 70 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 71 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 72 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 73 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 74 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 75 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 76 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 77 78 }; 79 80 81 /* Xtensa target flags. */ 82 83 enum xtensa_target_flags_t 84 { 85 xtTargetFlagsNonVisibleRegs = 0x0001, 86 xtTargetFlagsUseFetchStore = 0x0002, 87 }; 88 89 90 /* Mask. */ 91 92 typedef struct 93 { 94 int reg_num; 95 int bit_start; 96 int bit_size; 97 } xtensa_reg_mask_t; 98 99 typedef struct 100 { 101 int count; 102 xtensa_reg_mask_t *mask; 103 } xtensa_mask_t; 104 105 106 /* Xtensa register representation. */ 107 108 typedef struct 109 { 110 const char *name; /* Register name. */ 111 int offset; /* Offset. */ 112 xtensa_register_type_t type; /* Register type. */ 113 xtensa_register_group_t group;/* Register group. */ 114 struct type* ctype; /* C-type. */ 115 int bit_size; /* The actual bit size in the target. */ 116 int byte_size; /* Actual space allocated in registers[]. */ 117 int align; /* Alignment for this register. */ 118 119 unsigned int target_number; /* Register target number. */ 120 121 int flags; /* Flags. */ 122 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ 123 124 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 125 const char *fetch; /* Instruction sequence to fetch register. */ 126 const char *store; /* Instruction sequence to store register. */ 127 } xtensa_register_t; 128 129 /* For xtensa-config.c to expand to the structure above. */ 130 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ 131 {#name, ofs, (xtensa_register_type_t) (ty), \ 132 ((xtensa_register_group_t) \ 133 ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \ 134 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, 135 #define XTREG_END \ 136 {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \ 137 0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0}, 138 139 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 140 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 141 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 142 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 143 144 /* Call-ABI for stack frame. */ 145 146 enum call_abi_t 147 { 148 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 149 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 150 }; 151 152 153 struct ctype_cache 154 { 155 struct ctype_cache *next; 156 int size; 157 struct type *virtual_type; 158 }; 159 160 #ifndef XCHAL_NUM_CONTEXTS 161 # define XCHAL_NUM_CONTEXTS 0 162 #endif 163 164 #ifndef XCHAL_HAVE_EXCEPTIONS 165 # define XCHAL_HAVE_EXCEPTIONS 1 166 #endif 167 168 /* Xtensa-specific target dependencies. */ 169 170 struct xtensa_gdbarch_tdep : gdbarch_tdep_base 171 { 172 xtensa_gdbarch_tdep (xtensa_register_t *regmap) 173 : regmap (regmap) 174 {} 175 176 unsigned int target_flags = 0; 177 178 /* Spill location for TIE register files under ocd. */ 179 180 unsigned int spill_location = (unsigned int) -1; 181 unsigned int spill_size = 0; 182 183 char *unused = nullptr; /* Placeholder for compatibility. */ 184 185 /* Calling convention. */ 186 call_abi_t call_abi = (XSHAL_ABI == XTHAL_ABI_CALL0 187 ? CallAbiCall0Only : CallAbiDefault); 188 189 /* CPU configuration. */ 190 191 unsigned int debug_interrupt_level = XCHAL_DEBUGLEVEL; 192 193 unsigned int icache_line_bytes = XCHAL_ICACHE_LINESIZE; 194 unsigned int dcache_line_bytes = XCHAL_DCACHE_LINESIZE; 195 unsigned int dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK; 196 197 unsigned int isa_use_windowed_registers = XSHAL_ABI != XTHAL_ABI_CALL0; 198 unsigned int isa_use_density_instructions = XCHAL_HAVE_DENSITY; 199 unsigned int isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS; 200 unsigned int isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS; 201 unsigned int isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE; /* Maximum instruction length. */ 202 unsigned int debug_num_ibreaks = XCHAL_NUM_IBREAK; /* Number of IBREAKs. */ 203 unsigned int debug_num_dbreaks = XCHAL_NUM_DBREAK; 204 205 /* Register map. */ 206 207 xtensa_register_t *regmap; 208 209 unsigned int num_regs = 0; /* Number of registers in register map. */ 210 unsigned int num_nopriv_regs = 0; /* Number of non-privileged registers. */ 211 unsigned int num_pseudo_regs = 0; /* Number of pseudo registers. */ 212 unsigned int num_aregs = XCHAL_NUM_AREGS; /* Size of register file. */ 213 unsigned int num_contexts = XCHAL_NUM_CONTEXTS; 214 215 int ar_base = -1; /* Register number for AR0. */ 216 int a0_base = -1; /* Register number for A0 (pseudo). */ 217 int wb_regnum = -1; /* Register number for WB. */ 218 int ws_regnum = -1; /* Register number for WS. */ 219 int pc_regnum = -1; /* Register number for PC. */ 220 int ps_regnum = -1; /* Register number for PS. */ 221 int lbeg_regnum = -1; /* Register numbers for count regs. */ 222 int lend_regnum = -1; 223 int lcount_regnum = -1; 224 int sar_regnum = -1; /* Register number of SAR. */ 225 int litbase_regnum = -1; /* Register number of LITBASE. */ 226 int threadptr_regnum = -1; /* Register number of THREADPTR. */ 227 228 int interrupt_regnum = -1; /* Register number for interrupt. */ 229 int interrupt2_regnum = -1; /* Register number for interrupt2. */ 230 int cpenable_regnum = -1; /* Register number for cpenable. */ 231 int debugcause_regnum = -1; /* Register number for debugcause. */ 232 int exccause_regnum = -1; /* Register number for exccause. */ 233 int excvaddr_regnum = -1; /* Register number for excvaddr. */ 234 235 int max_register_raw_size = 0; 236 int max_register_virtual_size = 0; 237 unsigned long *fp_layout = nullptr; /* Layout of custom/TIE regs in 'FP' area. */ 238 unsigned int fp_layout_bytes = 0; /* Size of layout information (in bytes). */ 239 unsigned long *gregmap = nullptr; 240 241 /* Cached register types. */ 242 struct ctype_cache *type_entries = nullptr; 243 }; 244 245 #define WB_SHIFT 2 246 247 /* We assign fixed numbers to the registers of the "current" window 248 (i.e., relative to WB). The registers get remapped via the reg_map 249 data structure to their corresponding register in the AR register 250 file (see xtensa-tdep.c). */ 251 252 #endif /* XTENSA_TDEP_H */ 253