1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003-2015 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 21 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 22 whenever the "tdep" structure changes in an incompatible way. */ 23 24 #define XTENSA_TDEP_VERSION 0x60 25 26 /* Xtensa register type. */ 27 28 typedef enum 29 { 30 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 31 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 32 xtRegisterTypeUserReg, /* User defined registers (rur). */ 33 xtRegisterTypeTieRegfile, /* User define register files. */ 34 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 35 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 36 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 37 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 38 xtRegisterTypeVirtual, /* PC, FP. */ 39 xtRegisterTypeUnknown 40 } xtensa_register_type_t; 41 42 43 /* Xtensa register group. */ 44 45 #define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ 46 47 typedef enum 48 { 49 xtRegisterGroupUnknown = 0, 50 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 51 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 52 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 53 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 54 xtRegisterGroupState = 0x0010, /* States. */ 55 56 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 57 xtRegisterGroupUser = 0x0200, /* User registers. */ 58 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 59 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 60 xtRegisterGroupSystem = 0x1000, /* System. */ 61 62 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ 63 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 64 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 65 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 66 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 67 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 68 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 69 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 70 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 71 72 } xtensa_register_group_t; 73 74 75 /* Xtensa target flags. */ 76 77 typedef enum 78 { 79 xtTargetFlagsNonVisibleRegs = 0x0001, 80 xtTargetFlagsUseFetchStore = 0x0002, 81 } xtensa_target_flags_t; 82 83 84 /* Xtensa ELF core file register set representation ('.reg' section). 85 Copied from target-side ELF header <xtensa/elf.h>. */ 86 87 typedef uint32_t xtensa_elf_greg_t; 88 89 typedef struct 90 { 91 xtensa_elf_greg_t pc; 92 xtensa_elf_greg_t ps; 93 xtensa_elf_greg_t lbeg; 94 xtensa_elf_greg_t lend; 95 xtensa_elf_greg_t lcount; 96 xtensa_elf_greg_t sar; 97 xtensa_elf_greg_t windowstart; 98 xtensa_elf_greg_t windowbase; 99 xtensa_elf_greg_t reserved[8+48]; 100 xtensa_elf_greg_t ar[64]; 101 } xtensa_elf_gregset_t; 102 103 #define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \ 104 / sizeof (xtensa_elf_greg_t)) 105 106 /* Mask. */ 107 108 typedef struct 109 { 110 int reg_num; 111 int bit_start; 112 int bit_size; 113 } xtensa_reg_mask_t; 114 115 typedef struct 116 { 117 int count; 118 xtensa_reg_mask_t *mask; 119 } xtensa_mask_t; 120 121 122 /* Xtensa register representation. */ 123 124 typedef struct 125 { 126 char* name; /* Register name. */ 127 int offset; /* Offset. */ 128 xtensa_register_type_t type; /* Register type. */ 129 xtensa_register_group_t group;/* Register group. */ 130 struct type* ctype; /* C-type. */ 131 int bit_size; /* The actual bit size in the target. */ 132 int byte_size; /* Actual space allocated in registers[]. */ 133 int align; /* Alignment for this register. */ 134 135 unsigned int target_number; /* Register target number. */ 136 137 int flags; /* Flags. */ 138 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ 139 140 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 141 const char *fetch; /* Instruction sequence to fetch register. */ 142 const char *store; /* Instruction sequence to store register. */ 143 } xtensa_register_t; 144 145 /* For xtensa-config.c to expand to the structure above. */ 146 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ 147 {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \ 148 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, 149 #define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0}, 150 151 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 152 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 153 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 154 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 155 156 /* Call-ABI for stack frame. */ 157 158 typedef enum 159 { 160 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 161 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 162 } call_abi_t; 163 164 165 struct ctype_cache 166 { 167 struct ctype_cache *next; 168 int size; 169 struct type *virtual_type; 170 }; 171 172 /* Xtensa-specific target dependencies. */ 173 174 struct gdbarch_tdep 175 { 176 unsigned int target_flags; 177 178 /* Spill location for TIE register files under ocd. */ 179 180 unsigned int spill_location; 181 unsigned int spill_size; 182 183 char *unused; /* Placeholder for compatibility. */ 184 call_abi_t call_abi; /* Calling convention. */ 185 186 /* CPU configuration. */ 187 188 unsigned int debug_interrupt_level; 189 190 unsigned int icache_line_bytes; 191 unsigned int dcache_line_bytes; 192 unsigned int dcache_writeback; 193 194 unsigned int isa_use_windowed_registers; 195 unsigned int isa_use_density_instructions; 196 unsigned int isa_use_exceptions; 197 unsigned int isa_use_ext_l32r; 198 unsigned int isa_max_insn_size; /* Maximum instruction length. */ 199 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ 200 unsigned int debug_num_dbreaks; 201 202 /* Register map. */ 203 204 xtensa_register_t* regmap; 205 206 unsigned int num_regs; /* Number of registers in register map. */ 207 unsigned int num_nopriv_regs; /* Number of non-privileged registers. */ 208 unsigned int num_pseudo_regs; /* Number of pseudo registers. */ 209 unsigned int num_aregs; /* Size of register file. */ 210 unsigned int num_contexts; 211 212 int ar_base; /* Register number for AR0. */ 213 int a0_base; /* Register number for A0 (pseudo). */ 214 int wb_regnum; /* Register number for WB. */ 215 int ws_regnum; /* Register number for WS. */ 216 int pc_regnum; /* Register number for PC. */ 217 int ps_regnum; /* Register number for PS. */ 218 int lbeg_regnum; /* Register numbers for count regs. */ 219 int lend_regnum; 220 int lcount_regnum; 221 int sar_regnum; /* Register number of SAR. */ 222 int litbase_regnum; /* Register number of LITBASE. */ 223 224 int interrupt_regnum; /* Register number for interrupt. */ 225 int interrupt2_regnum; /* Register number for interrupt2. */ 226 int cpenable_regnum; /* Register number for cpenable. */ 227 int debugcause_regnum; /* Register number for debugcause. */ 228 int exccause_regnum; /* Register number for exccause. */ 229 int excvaddr_regnum; /* Register number for excvaddr. */ 230 231 int max_register_raw_size; 232 int max_register_virtual_size; 233 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ 234 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ 235 unsigned long *gregmap; 236 237 /* Cached register types. */ 238 struct ctype_cache *type_entries; 239 }; 240 241 /* Macro to instantiate a gdbarch_tdep structure. */ 242 243 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ 244 { \ 245 .target_flags = 0, \ 246 .spill_location = -1, \ 247 .spill_size = (spillsz), \ 248 .unused = 0, \ 249 .call_abi = 0, \ 250 .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ 251 .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ 252 .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ 253 .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \ 254 .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \ 255 .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \ 256 .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \ 257 .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \ 258 .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ 259 .debug_num_ibreaks = XCHAL_NUM_IBREAK, \ 260 .debug_num_dbreaks = XCHAL_NUM_DBREAK, \ 261 .regmap = rmap, \ 262 .num_regs = 0, \ 263 .num_nopriv_regs = 0, \ 264 .num_pseudo_regs = 0, \ 265 .num_aregs = XCHAL_NUM_AREGS, \ 266 .num_contexts = XCHAL_NUM_CONTEXTS, \ 267 .ar_base = -1, \ 268 .a0_base = -1, \ 269 .wb_regnum = -1, \ 270 .ws_regnum = -1, \ 271 .pc_regnum = -1, \ 272 .ps_regnum = -1, \ 273 .lbeg_regnum = -1, \ 274 .lend_regnum = -1, \ 275 .lcount_regnum = -1, \ 276 .sar_regnum = -1, \ 277 .litbase_regnum = -1, \ 278 .interrupt_regnum = -1, \ 279 .interrupt2_regnum = -1, \ 280 .cpenable_regnum = -1, \ 281 .debugcause_regnum = -1, \ 282 .exccause_regnum = -1, \ 283 .excvaddr_regnum = -1, \ 284 .max_register_raw_size = 0, \ 285 .max_register_virtual_size = 0, \ 286 .fp_layout = 0, \ 287 .fp_layout_bytes = 0, \ 288 .gregmap = 0, \ 289 } 290 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ 291 struct gdbarch_tdep xtensa_tdep = \ 292 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); 293 294 #ifndef XCHAL_NUM_CONTEXTS 295 #define XCHAL_NUM_CONTEXTS 0 296 #endif 297 #ifndef XCHAL_HAVE_EXCEPTIONS 298 #define XCHAL_HAVE_EXCEPTIONS 1 299 #endif 300 #define WB_SHIFT 2 301 302 /* We assign fixed numbers to the registers of the "current" window 303 (i.e., relative to WB). The registers get remapped via the reg_map 304 data structure to their corresponding register in the AR register 305 file (see xtensa-tdep.c). */ 306 307