1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003-2019 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #ifndef XTENSA_TDEP_H 21 #define XTENSA_TDEP_H 22 23 #include "arch/xtensa.h" 24 25 /* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 26 whenever the "tdep" structure changes in an incompatible way. */ 27 28 #define XTENSA_TDEP_VERSION 0x60 29 30 /* Xtensa register type. */ 31 32 typedef enum 33 { 34 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 35 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 36 xtRegisterTypeUserReg, /* User defined registers (rur). */ 37 xtRegisterTypeTieRegfile, /* User define register files. */ 38 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 39 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 40 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 41 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 42 xtRegisterTypeVirtual, /* PC, FP. */ 43 xtRegisterTypeUnknown 44 } xtensa_register_type_t; 45 46 47 /* Xtensa register group. */ 48 49 #define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ 50 51 typedef enum 52 { 53 xtRegisterGroupUnknown = 0, 54 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 55 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 56 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 57 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 58 xtRegisterGroupState = 0x0010, /* States. */ 59 60 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 61 xtRegisterGroupUser = 0x0200, /* User registers. */ 62 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 63 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 64 xtRegisterGroupSystem = 0x1000, /* System. */ 65 66 xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ 67 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 68 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 69 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 70 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 71 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 72 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 73 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 74 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 75 76 } xtensa_register_group_t; 77 78 79 /* Xtensa target flags. */ 80 81 typedef enum 82 { 83 xtTargetFlagsNonVisibleRegs = 0x0001, 84 xtTargetFlagsUseFetchStore = 0x0002, 85 } xtensa_target_flags_t; 86 87 88 /* Mask. */ 89 90 typedef struct 91 { 92 int reg_num; 93 int bit_start; 94 int bit_size; 95 } xtensa_reg_mask_t; 96 97 typedef struct 98 { 99 int count; 100 xtensa_reg_mask_t *mask; 101 } xtensa_mask_t; 102 103 104 /* Xtensa register representation. */ 105 106 typedef struct 107 { 108 const char *name; /* Register name. */ 109 int offset; /* Offset. */ 110 xtensa_register_type_t type; /* Register type. */ 111 xtensa_register_group_t group;/* Register group. */ 112 struct type* ctype; /* C-type. */ 113 int bit_size; /* The actual bit size in the target. */ 114 int byte_size; /* Actual space allocated in registers[]. */ 115 int align; /* Alignment for this register. */ 116 117 unsigned int target_number; /* Register target number. */ 118 119 int flags; /* Flags. */ 120 int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ 121 122 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 123 const char *fetch; /* Instruction sequence to fetch register. */ 124 const char *store; /* Instruction sequence to store register. */ 125 } xtensa_register_t; 126 127 /* For xtensa-config.c to expand to the structure above. */ 128 #define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ 129 {#name, ofs, (xtensa_register_type_t) (ty), \ 130 ((xtensa_register_group_t) \ 131 ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2)))), \ 132 ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, 133 #define XTREG_END \ 134 {0, 0, (xtensa_register_type_t) 0, (xtensa_register_group_t) 0, \ 135 0, 0, 0, 0, (unsigned) -1, 0, 0, 0, 0, 0}, 136 137 #define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 138 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 139 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 140 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 141 142 /* Call-ABI for stack frame. */ 143 144 typedef enum 145 { 146 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 147 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 148 } call_abi_t; 149 150 151 struct ctype_cache 152 { 153 struct ctype_cache *next; 154 int size; 155 struct type *virtual_type; 156 }; 157 158 /* Xtensa-specific target dependencies. */ 159 160 struct gdbarch_tdep 161 { 162 unsigned int target_flags; 163 164 /* Spill location for TIE register files under ocd. */ 165 166 unsigned int spill_location; 167 unsigned int spill_size; 168 169 char *unused; /* Placeholder for compatibility. */ 170 call_abi_t call_abi; /* Calling convention. */ 171 172 /* CPU configuration. */ 173 174 unsigned int debug_interrupt_level; 175 176 unsigned int icache_line_bytes; 177 unsigned int dcache_line_bytes; 178 unsigned int dcache_writeback; 179 180 unsigned int isa_use_windowed_registers; 181 unsigned int isa_use_density_instructions; 182 unsigned int isa_use_exceptions; 183 unsigned int isa_use_ext_l32r; 184 unsigned int isa_max_insn_size; /* Maximum instruction length. */ 185 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ 186 unsigned int debug_num_dbreaks; 187 188 /* Register map. */ 189 190 xtensa_register_t* regmap; 191 192 unsigned int num_regs; /* Number of registers in register map. */ 193 unsigned int num_nopriv_regs; /* Number of non-privileged registers. */ 194 unsigned int num_pseudo_regs; /* Number of pseudo registers. */ 195 unsigned int num_aregs; /* Size of register file. */ 196 unsigned int num_contexts; 197 198 int ar_base; /* Register number for AR0. */ 199 int a0_base; /* Register number for A0 (pseudo). */ 200 int wb_regnum; /* Register number for WB. */ 201 int ws_regnum; /* Register number for WS. */ 202 int pc_regnum; /* Register number for PC. */ 203 int ps_regnum; /* Register number for PS. */ 204 int lbeg_regnum; /* Register numbers for count regs. */ 205 int lend_regnum; 206 int lcount_regnum; 207 int sar_regnum; /* Register number of SAR. */ 208 int litbase_regnum; /* Register number of LITBASE. */ 209 int threadptr_regnum; /* Register number of THREADPTR. */ 210 211 int interrupt_regnum; /* Register number for interrupt. */ 212 int interrupt2_regnum; /* Register number for interrupt2. */ 213 int cpenable_regnum; /* Register number for cpenable. */ 214 int debugcause_regnum; /* Register number for debugcause. */ 215 int exccause_regnum; /* Register number for exccause. */ 216 int excvaddr_regnum; /* Register number for excvaddr. */ 217 218 int max_register_raw_size; 219 int max_register_virtual_size; 220 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ 221 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ 222 unsigned long *gregmap; 223 224 /* Cached register types. */ 225 struct ctype_cache *type_entries; 226 }; 227 228 /* Macro to instantiate a gdbarch_tdep structure. */ 229 230 #define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ 231 { \ 232 0, /* target_flags */ \ 233 (unsigned) -1, /* spill_location */ \ 234 (spillsz), /* spill_size */ \ 235 0, /* unused */ \ 236 (XSHAL_ABI == XTHAL_ABI_CALL0 \ 237 ? CallAbiCall0Only \ 238 : CallAbiDefault), /* call_abi */ \ 239 XCHAL_DEBUGLEVEL, /* debug_interrupt_level */ \ 240 XCHAL_ICACHE_LINESIZE, /* icache_line_bytes */ \ 241 XCHAL_DCACHE_LINESIZE, /* dcache_line_bytes */ \ 242 XCHAL_DCACHE_IS_WRITEBACK, /* dcache_writeback */ \ 243 (XSHAL_ABI != XTHAL_ABI_CALL0), /* isa_use_windowed_registers */ \ 244 XCHAL_HAVE_DENSITY, /* isa_use_density_instructions */ \ 245 XCHAL_HAVE_EXCEPTIONS, /* isa_use_exceptions */ \ 246 XSHAL_USE_ABSOLUTE_LITERALS, /* isa_use_ext_l32r */ \ 247 XCHAL_MAX_INSTRUCTION_SIZE, /* isa_max_insn_size */ \ 248 XCHAL_NUM_IBREAK, /* debug_num_ibreaks */ \ 249 XCHAL_NUM_DBREAK, /* debug_num_dbreaks */ \ 250 rmap, /* regmap */ \ 251 0, /* num_regs */ \ 252 0, /* num_nopriv_regs */ \ 253 0, /* num_pseudo_regs */ \ 254 XCHAL_NUM_AREGS, /* num_aregs */ \ 255 XCHAL_NUM_CONTEXTS, /* num_contexts */ \ 256 -1, /* ar_base */ \ 257 -1, /* a0_base */ \ 258 -1, /* wb_regnum */ \ 259 -1, /* ws_regnum */ \ 260 -1, /* pc_regnum */ \ 261 -1, /* ps_regnum */ \ 262 -1, /* lbeg_regnum */ \ 263 -1, /* lend_regnum */ \ 264 -1, /* lcount_regnum */ \ 265 -1, /* sar_regnum */ \ 266 -1, /* litbase_regnum */ \ 267 -1, /* interrupt_regnum */ \ 268 -1, /* interrupt2_regnum */ \ 269 -1, /* cpenable_regnum */ \ 270 -1, /* debugcause_regnum */ \ 271 -1, /* exccause_regnum */ \ 272 -1, /* excvaddr_regnum */ \ 273 0, /* max_register_raw_size */ \ 274 0, /* max_register_virtual_size */ \ 275 0, /* fp_layout */ \ 276 0, /* fp_layout_bytes */ \ 277 0, /* gregmap */ \ 278 } 279 #define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ 280 struct gdbarch_tdep xtensa_tdep = \ 281 XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); 282 283 #ifndef XCHAL_NUM_CONTEXTS 284 #define XCHAL_NUM_CONTEXTS 0 285 #endif 286 #ifndef XCHAL_HAVE_EXCEPTIONS 287 #define XCHAL_HAVE_EXCEPTIONS 1 288 #endif 289 #define WB_SHIFT 2 290 291 /* We assign fixed numbers to the registers of the "current" window 292 (i.e., relative to WB). The registers get remapped via the reg_map 293 data structure to their corresponding register in the AR register 294 file (see xtensa-tdep.c). */ 295 296 #endif /* XTENSA_TDEP_H */ 297