1 /* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 1986-2016 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "frame.h" 22 #include "inferior.h" 23 #include "infrun.h" 24 #include "symtab.h" 25 #include "target.h" 26 #include "gdbcore.h" 27 #include "gdbcmd.h" 28 #include "objfiles.h" 29 #include "arch-utils.h" 30 #include "regcache.h" 31 #include "regset.h" 32 #include "doublest.h" 33 #include "value.h" 34 #include "parser-defs.h" 35 #include "osabi.h" 36 #include "infcall.h" 37 #include "sim-regno.h" 38 #include "gdb/sim-ppc.h" 39 #include "reggroups.h" 40 #include "dwarf2-frame.h" 41 #include "target-descriptions.h" 42 #include "user-regs.h" 43 #include "record-full.h" 44 #include "auxv.h" 45 46 #include "coff/internal.h" /* for libcoff.h */ 47 #include "libcoff.h" /* for xcoff_data */ 48 #include "coff/xcoff.h" 49 #include "libxcoff.h" 50 51 #include "elf-bfd.h" 52 #include "elf/ppc.h" 53 #include "elf/ppc64.h" 54 55 #include "solib-svr4.h" 56 #include "ppc-tdep.h" 57 #include "ppc-ravenscar-thread.h" 58 59 #include "dis-asm.h" 60 61 #include "trad-frame.h" 62 #include "frame-unwind.h" 63 #include "frame-base.h" 64 65 #include "ax.h" 66 #include "ax-gdb.h" 67 68 #include "features/rs6000/powerpc-32.c" 69 #include "features/rs6000/powerpc-altivec32.c" 70 #include "features/rs6000/powerpc-vsx32.c" 71 #include "features/rs6000/powerpc-403.c" 72 #include "features/rs6000/powerpc-403gc.c" 73 #include "features/rs6000/powerpc-405.c" 74 #include "features/rs6000/powerpc-505.c" 75 #include "features/rs6000/powerpc-601.c" 76 #include "features/rs6000/powerpc-602.c" 77 #include "features/rs6000/powerpc-603.c" 78 #include "features/rs6000/powerpc-604.c" 79 #include "features/rs6000/powerpc-64.c" 80 #include "features/rs6000/powerpc-altivec64.c" 81 #include "features/rs6000/powerpc-vsx64.c" 82 #include "features/rs6000/powerpc-7400.c" 83 #include "features/rs6000/powerpc-750.c" 84 #include "features/rs6000/powerpc-860.c" 85 #include "features/rs6000/powerpc-e500.c" 86 #include "features/rs6000/rs6000.c" 87 88 /* Determine if regnum is an SPE pseudo-register. */ 89 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ 90 && (regnum) >= (tdep)->ppc_ev0_regnum \ 91 && (regnum) < (tdep)->ppc_ev0_regnum + 32) 92 93 /* Determine if regnum is a decimal float pseudo-register. */ 94 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ 95 && (regnum) >= (tdep)->ppc_dl0_regnum \ 96 && (regnum) < (tdep)->ppc_dl0_regnum + 16) 97 98 /* Determine if regnum is a POWER7 VSX register. */ 99 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ 100 && (regnum) >= (tdep)->ppc_vsr0_regnum \ 101 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) 102 103 /* Determine if regnum is a POWER7 Extended FP register. */ 104 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ 105 && (regnum) >= (tdep)->ppc_efpr0_regnum \ 106 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) 107 108 /* The list of available "set powerpc ..." and "show powerpc ..." 109 commands. */ 110 static struct cmd_list_element *setpowerpccmdlist = NULL; 111 static struct cmd_list_element *showpowerpccmdlist = NULL; 112 113 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; 114 115 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ 116 static const char *const powerpc_vector_strings[] = 117 { 118 "auto", 119 "generic", 120 "altivec", 121 "spe", 122 NULL 123 }; 124 125 /* A variable that can be configured by the user. */ 126 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; 127 static const char *powerpc_vector_abi_string = "auto"; 128 129 /* To be used by skip_prologue. */ 130 131 struct rs6000_framedata 132 { 133 int offset; /* total size of frame --- the distance 134 by which we decrement sp to allocate 135 the frame */ 136 int saved_gpr; /* smallest # of saved gpr */ 137 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ 138 int saved_fpr; /* smallest # of saved fpr */ 139 int saved_vr; /* smallest # of saved vr */ 140 int saved_ev; /* smallest # of saved ev */ 141 int alloca_reg; /* alloca register number (frame ptr) */ 142 char frameless; /* true if frameless functions. */ 143 char nosavedpc; /* true if pc not saved. */ 144 char used_bl; /* true if link register clobbered */ 145 int gpr_offset; /* offset of saved gprs from prev sp */ 146 int fpr_offset; /* offset of saved fprs from prev sp */ 147 int vr_offset; /* offset of saved vrs from prev sp */ 148 int ev_offset; /* offset of saved evs from prev sp */ 149 int lr_offset; /* offset of saved lr */ 150 int lr_register; /* register of saved lr, if trustworthy */ 151 int cr_offset; /* offset of saved cr */ 152 int vrsave_offset; /* offset of saved vrsave register */ 153 }; 154 155 156 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ 157 int 158 vsx_register_p (struct gdbarch *gdbarch, int regno) 159 { 160 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 161 if (tdep->ppc_vsr0_regnum < 0) 162 return 0; 163 else 164 return (regno >= tdep->ppc_vsr0_upper_regnum && regno 165 <= tdep->ppc_vsr0_upper_regnum + 31); 166 } 167 168 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 169 int 170 altivec_register_p (struct gdbarch *gdbarch, int regno) 171 { 172 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 173 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 174 return 0; 175 else 176 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 177 } 178 179 180 /* Return true if REGNO is an SPE register, false otherwise. */ 181 int 182 spe_register_p (struct gdbarch *gdbarch, int regno) 183 { 184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 185 186 /* Is it a reference to EV0 -- EV31, and do we have those? */ 187 if (IS_SPE_PSEUDOREG (tdep, regno)) 188 return 1; 189 190 /* Is it a reference to one of the raw upper GPR halves? */ 191 if (tdep->ppc_ev0_upper_regnum >= 0 192 && tdep->ppc_ev0_upper_regnum <= regno 193 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 194 return 1; 195 196 /* Is it a reference to the 64-bit accumulator, and do we have that? */ 197 if (tdep->ppc_acc_regnum >= 0 198 && tdep->ppc_acc_regnum == regno) 199 return 1; 200 201 /* Is it a reference to the SPE floating-point status and control register, 202 and do we have that? */ 203 if (tdep->ppc_spefscr_regnum >= 0 204 && tdep->ppc_spefscr_regnum == regno) 205 return 1; 206 207 return 0; 208 } 209 210 211 /* Return non-zero if the architecture described by GDBARCH has 212 floating-point registers (f0 --- f31 and fpscr). */ 213 int 214 ppc_floating_point_unit_p (struct gdbarch *gdbarch) 215 { 216 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 217 218 return (tdep->ppc_fp0_regnum >= 0 219 && tdep->ppc_fpscr_regnum >= 0); 220 } 221 222 /* Return non-zero if the architecture described by GDBARCH has 223 VSX registers (vsr0 --- vsr63). */ 224 static int 225 ppc_vsx_support_p (struct gdbarch *gdbarch) 226 { 227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 228 229 return tdep->ppc_vsr0_regnum >= 0; 230 } 231 232 /* Return non-zero if the architecture described by GDBARCH has 233 Altivec registers (vr0 --- vr31, vrsave and vscr). */ 234 int 235 ppc_altivec_support_p (struct gdbarch *gdbarch) 236 { 237 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 238 239 return (tdep->ppc_vr0_regnum >= 0 240 && tdep->ppc_vrsave_regnum >= 0); 241 } 242 243 /* Check that TABLE[GDB_REGNO] is not already initialized, and then 244 set it to SIM_REGNO. 245 246 This is a helper function for init_sim_regno_table, constructing 247 the table mapping GDB register numbers to sim register numbers; we 248 initialize every element in that table to -1 before we start 249 filling it in. */ 250 static void 251 set_sim_regno (int *table, int gdb_regno, int sim_regno) 252 { 253 /* Make sure we don't try to assign any given GDB register a sim 254 register number more than once. */ 255 gdb_assert (table[gdb_regno] == -1); 256 table[gdb_regno] = sim_regno; 257 } 258 259 260 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register 261 numbers to simulator register numbers, based on the values placed 262 in the ARCH->tdep->ppc_foo_regnum members. */ 263 static void 264 init_sim_regno_table (struct gdbarch *arch) 265 { 266 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 267 int total_regs = gdbarch_num_regs (arch); 268 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); 269 int i; 270 static const char *const segment_regs[] = { 271 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", 272 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" 273 }; 274 275 /* Presume that all registers not explicitly mentioned below are 276 unavailable from the sim. */ 277 for (i = 0; i < total_regs; i++) 278 sim_regno[i] = -1; 279 280 /* General-purpose registers. */ 281 for (i = 0; i < ppc_num_gprs; i++) 282 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); 283 284 /* Floating-point registers. */ 285 if (tdep->ppc_fp0_regnum >= 0) 286 for (i = 0; i < ppc_num_fprs; i++) 287 set_sim_regno (sim_regno, 288 tdep->ppc_fp0_regnum + i, 289 sim_ppc_f0_regnum + i); 290 if (tdep->ppc_fpscr_regnum >= 0) 291 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); 292 293 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); 294 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); 295 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); 296 297 /* Segment registers. */ 298 for (i = 0; i < ppc_num_srs; i++) 299 { 300 int gdb_regno; 301 302 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); 303 if (gdb_regno >= 0) 304 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); 305 } 306 307 /* Altivec registers. */ 308 if (tdep->ppc_vr0_regnum >= 0) 309 { 310 for (i = 0; i < ppc_num_vrs; i++) 311 set_sim_regno (sim_regno, 312 tdep->ppc_vr0_regnum + i, 313 sim_ppc_vr0_regnum + i); 314 315 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, 316 we can treat this more like the other cases. */ 317 set_sim_regno (sim_regno, 318 tdep->ppc_vr0_regnum + ppc_num_vrs, 319 sim_ppc_vscr_regnum); 320 } 321 /* vsave is a special-purpose register, so the code below handles it. */ 322 323 /* SPE APU (E500) registers. */ 324 if (tdep->ppc_ev0_upper_regnum >= 0) 325 for (i = 0; i < ppc_num_gprs; i++) 326 set_sim_regno (sim_regno, 327 tdep->ppc_ev0_upper_regnum + i, 328 sim_ppc_rh0_regnum + i); 329 if (tdep->ppc_acc_regnum >= 0) 330 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); 331 /* spefscr is a special-purpose register, so the code below handles it. */ 332 333 #ifdef WITH_PPC_SIM 334 /* Now handle all special-purpose registers. Verify that they 335 haven't mistakenly been assigned numbers by any of the above 336 code. */ 337 for (i = 0; i < sim_ppc_num_sprs; i++) 338 { 339 const char *spr_name = sim_spr_register_name (i); 340 int gdb_regno = -1; 341 342 if (spr_name != NULL) 343 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); 344 345 if (gdb_regno != -1) 346 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); 347 } 348 #endif 349 350 /* Drop the initialized array into place. */ 351 tdep->sim_regno = sim_regno; 352 } 353 354 355 /* Given a GDB register number REG, return the corresponding SIM 356 register number. */ 357 static int 358 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) 359 { 360 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 361 int sim_regno; 362 363 if (tdep->sim_regno == NULL) 364 init_sim_regno_table (gdbarch); 365 366 gdb_assert (0 <= reg 367 && reg <= gdbarch_num_regs (gdbarch) 368 + gdbarch_num_pseudo_regs (gdbarch)); 369 sim_regno = tdep->sim_regno[reg]; 370 371 if (sim_regno >= 0) 372 return sim_regno; 373 else 374 return LEGACY_SIM_REGNO_IGNORE; 375 } 376 377 378 379 /* Register set support functions. */ 380 381 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. 382 Write the register to REGCACHE. */ 383 384 void 385 ppc_supply_reg (struct regcache *regcache, int regnum, 386 const gdb_byte *regs, size_t offset, int regsize) 387 { 388 if (regnum != -1 && offset != -1) 389 { 390 if (regsize > 4) 391 { 392 struct gdbarch *gdbarch = get_regcache_arch (regcache); 393 int gdb_regsize = register_size (gdbarch, regnum); 394 if (gdb_regsize < regsize 395 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 396 offset += regsize - gdb_regsize; 397 } 398 regcache_raw_supply (regcache, regnum, regs + offset); 399 } 400 } 401 402 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET 403 in a field REGSIZE wide. Zero pad as necessary. */ 404 405 void 406 ppc_collect_reg (const struct regcache *regcache, int regnum, 407 gdb_byte *regs, size_t offset, int regsize) 408 { 409 if (regnum != -1 && offset != -1) 410 { 411 if (regsize > 4) 412 { 413 struct gdbarch *gdbarch = get_regcache_arch (regcache); 414 int gdb_regsize = register_size (gdbarch, regnum); 415 if (gdb_regsize < regsize) 416 { 417 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 418 { 419 memset (regs + offset, 0, regsize - gdb_regsize); 420 offset += regsize - gdb_regsize; 421 } 422 else 423 memset (regs + offset + regsize - gdb_regsize, 0, 424 regsize - gdb_regsize); 425 } 426 } 427 regcache_raw_collect (regcache, regnum, regs + offset); 428 } 429 } 430 431 static int 432 ppc_greg_offset (struct gdbarch *gdbarch, 433 struct gdbarch_tdep *tdep, 434 const struct ppc_reg_offsets *offsets, 435 int regnum, 436 int *regsize) 437 { 438 *regsize = offsets->gpr_size; 439 if (regnum >= tdep->ppc_gp0_regnum 440 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) 441 return (offsets->r0_offset 442 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); 443 444 if (regnum == gdbarch_pc_regnum (gdbarch)) 445 return offsets->pc_offset; 446 447 if (regnum == tdep->ppc_ps_regnum) 448 return offsets->ps_offset; 449 450 if (regnum == tdep->ppc_lr_regnum) 451 return offsets->lr_offset; 452 453 if (regnum == tdep->ppc_ctr_regnum) 454 return offsets->ctr_offset; 455 456 *regsize = offsets->xr_size; 457 if (regnum == tdep->ppc_cr_regnum) 458 return offsets->cr_offset; 459 460 if (regnum == tdep->ppc_xer_regnum) 461 return offsets->xer_offset; 462 463 if (regnum == tdep->ppc_mq_regnum) 464 return offsets->mq_offset; 465 466 return -1; 467 } 468 469 static int 470 ppc_fpreg_offset (struct gdbarch_tdep *tdep, 471 const struct ppc_reg_offsets *offsets, 472 int regnum) 473 { 474 if (regnum >= tdep->ppc_fp0_regnum 475 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) 476 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; 477 478 if (regnum == tdep->ppc_fpscr_regnum) 479 return offsets->fpscr_offset; 480 481 return -1; 482 } 483 484 static int 485 ppc_vrreg_offset (struct gdbarch_tdep *tdep, 486 const struct ppc_reg_offsets *offsets, 487 int regnum) 488 { 489 if (regnum >= tdep->ppc_vr0_regnum 490 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs) 491 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16; 492 493 if (regnum == tdep->ppc_vrsave_regnum - 1) 494 return offsets->vscr_offset; 495 496 if (regnum == tdep->ppc_vrsave_regnum) 497 return offsets->vrsave_offset; 498 499 return -1; 500 } 501 502 /* Supply register REGNUM in the general-purpose register set REGSET 503 from the buffer specified by GREGS and LEN to register cache 504 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 505 506 void 507 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, 508 int regnum, const void *gregs, size_t len) 509 { 510 struct gdbarch *gdbarch = get_regcache_arch (regcache); 511 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 512 const struct ppc_reg_offsets *offsets 513 = (const struct ppc_reg_offsets *) regset->regmap; 514 size_t offset; 515 int regsize; 516 517 if (regnum == -1) 518 { 519 int i; 520 int gpr_size = offsets->gpr_size; 521 522 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 523 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 524 i++, offset += gpr_size) 525 ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset, 526 gpr_size); 527 528 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), 529 (const gdb_byte *) gregs, offsets->pc_offset, gpr_size); 530 ppc_supply_reg (regcache, tdep->ppc_ps_regnum, 531 (const gdb_byte *) gregs, offsets->ps_offset, gpr_size); 532 ppc_supply_reg (regcache, tdep->ppc_lr_regnum, 533 (const gdb_byte *) gregs, offsets->lr_offset, gpr_size); 534 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, 535 (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size); 536 ppc_supply_reg (regcache, tdep->ppc_cr_regnum, 537 (const gdb_byte *) gregs, offsets->cr_offset, 538 offsets->xr_size); 539 ppc_supply_reg (regcache, tdep->ppc_xer_regnum, 540 (const gdb_byte *) gregs, offsets->xer_offset, 541 offsets->xr_size); 542 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, 543 (const gdb_byte *) gregs, offsets->mq_offset, 544 offsets->xr_size); 545 return; 546 } 547 548 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 549 ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize); 550 } 551 552 /* Supply register REGNUM in the floating-point register set REGSET 553 from the buffer specified by FPREGS and LEN to register cache 554 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 555 556 void 557 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, 558 int regnum, const void *fpregs, size_t len) 559 { 560 struct gdbarch *gdbarch = get_regcache_arch (regcache); 561 struct gdbarch_tdep *tdep; 562 const struct ppc_reg_offsets *offsets; 563 size_t offset; 564 565 if (!ppc_floating_point_unit_p (gdbarch)) 566 return; 567 568 tdep = gdbarch_tdep (gdbarch); 569 offsets = (const struct ppc_reg_offsets *) regset->regmap; 570 if (regnum == -1) 571 { 572 int i; 573 574 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 575 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 576 i++, offset += 8) 577 ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8); 578 579 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, 580 (const gdb_byte *) fpregs, offsets->fpscr_offset, 581 offsets->fpscr_size); 582 return; 583 } 584 585 offset = ppc_fpreg_offset (tdep, offsets, regnum); 586 ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset, 587 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 588 } 589 590 /* Supply register REGNUM in the VSX register set REGSET 591 from the buffer specified by VSXREGS and LEN to register cache 592 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 593 594 void 595 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache, 596 int regnum, const void *vsxregs, size_t len) 597 { 598 struct gdbarch *gdbarch = get_regcache_arch (regcache); 599 struct gdbarch_tdep *tdep; 600 601 if (!ppc_vsx_support_p (gdbarch)) 602 return; 603 604 tdep = gdbarch_tdep (gdbarch); 605 606 if (regnum == -1) 607 { 608 int i; 609 610 for (i = tdep->ppc_vsr0_upper_regnum; 611 i < tdep->ppc_vsr0_upper_regnum + 32; 612 i++) 613 ppc_supply_reg (regcache, i, (const gdb_byte *) vsxregs, 0, 8); 614 615 return; 616 } 617 else 618 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vsxregs, 0, 8); 619 } 620 621 /* Supply register REGNUM in the Altivec register set REGSET 622 from the buffer specified by VRREGS and LEN to register cache 623 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 624 625 void 626 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache, 627 int regnum, const void *vrregs, size_t len) 628 { 629 struct gdbarch *gdbarch = get_regcache_arch (regcache); 630 struct gdbarch_tdep *tdep; 631 const struct ppc_reg_offsets *offsets; 632 size_t offset; 633 634 if (!ppc_altivec_support_p (gdbarch)) 635 return; 636 637 tdep = gdbarch_tdep (gdbarch); 638 offsets = (const struct ppc_reg_offsets *) regset->regmap; 639 if (regnum == -1) 640 { 641 int i; 642 643 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; 644 i < tdep->ppc_vr0_regnum + ppc_num_vrs; 645 i++, offset += 16) 646 ppc_supply_reg (regcache, i, (const gdb_byte *) vrregs, offset, 16); 647 648 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1), 649 (const gdb_byte *) vrregs, offsets->vscr_offset, 4); 650 651 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum, 652 (const gdb_byte *) vrregs, offsets->vrsave_offset, 4); 653 return; 654 } 655 656 offset = ppc_vrreg_offset (tdep, offsets, regnum); 657 if (regnum != tdep->ppc_vrsave_regnum 658 && regnum != tdep->ppc_vrsave_regnum - 1) 659 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vrregs, offset, 16); 660 else 661 ppc_supply_reg (regcache, regnum, 662 (const gdb_byte *) vrregs, offset, 4); 663 } 664 665 /* Collect register REGNUM in the general-purpose register set 666 REGSET from register cache REGCACHE into the buffer specified by 667 GREGS and LEN. If REGNUM is -1, do this for all registers in 668 REGSET. */ 669 670 void 671 ppc_collect_gregset (const struct regset *regset, 672 const struct regcache *regcache, 673 int regnum, void *gregs, size_t len) 674 { 675 struct gdbarch *gdbarch = get_regcache_arch (regcache); 676 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 677 const struct ppc_reg_offsets *offsets 678 = (const struct ppc_reg_offsets *) regset->regmap; 679 size_t offset; 680 int regsize; 681 682 if (regnum == -1) 683 { 684 int i; 685 int gpr_size = offsets->gpr_size; 686 687 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 688 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 689 i++, offset += gpr_size) 690 ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size); 691 692 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), 693 (gdb_byte *) gregs, offsets->pc_offset, gpr_size); 694 ppc_collect_reg (regcache, tdep->ppc_ps_regnum, 695 (gdb_byte *) gregs, offsets->ps_offset, gpr_size); 696 ppc_collect_reg (regcache, tdep->ppc_lr_regnum, 697 (gdb_byte *) gregs, offsets->lr_offset, gpr_size); 698 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, 699 (gdb_byte *) gregs, offsets->ctr_offset, gpr_size); 700 ppc_collect_reg (regcache, tdep->ppc_cr_regnum, 701 (gdb_byte *) gregs, offsets->cr_offset, 702 offsets->xr_size); 703 ppc_collect_reg (regcache, tdep->ppc_xer_regnum, 704 (gdb_byte *) gregs, offsets->xer_offset, 705 offsets->xr_size); 706 ppc_collect_reg (regcache, tdep->ppc_mq_regnum, 707 (gdb_byte *) gregs, offsets->mq_offset, 708 offsets->xr_size); 709 return; 710 } 711 712 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 713 ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize); 714 } 715 716 /* Collect register REGNUM in the floating-point register set 717 REGSET from register cache REGCACHE into the buffer specified by 718 FPREGS and LEN. If REGNUM is -1, do this for all registers in 719 REGSET. */ 720 721 void 722 ppc_collect_fpregset (const struct regset *regset, 723 const struct regcache *regcache, 724 int regnum, void *fpregs, size_t len) 725 { 726 struct gdbarch *gdbarch = get_regcache_arch (regcache); 727 struct gdbarch_tdep *tdep; 728 const struct ppc_reg_offsets *offsets; 729 size_t offset; 730 731 if (!ppc_floating_point_unit_p (gdbarch)) 732 return; 733 734 tdep = gdbarch_tdep (gdbarch); 735 offsets = (const struct ppc_reg_offsets *) regset->regmap; 736 if (regnum == -1) 737 { 738 int i; 739 740 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 741 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 742 i++, offset += 8) 743 ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8); 744 745 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, 746 (gdb_byte *) fpregs, offsets->fpscr_offset, 747 offsets->fpscr_size); 748 return; 749 } 750 751 offset = ppc_fpreg_offset (tdep, offsets, regnum); 752 ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset, 753 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 754 } 755 756 /* Collect register REGNUM in the VSX register set 757 REGSET from register cache REGCACHE into the buffer specified by 758 VSXREGS and LEN. If REGNUM is -1, do this for all registers in 759 REGSET. */ 760 761 void 762 ppc_collect_vsxregset (const struct regset *regset, 763 const struct regcache *regcache, 764 int regnum, void *vsxregs, size_t len) 765 { 766 struct gdbarch *gdbarch = get_regcache_arch (regcache); 767 struct gdbarch_tdep *tdep; 768 769 if (!ppc_vsx_support_p (gdbarch)) 770 return; 771 772 tdep = gdbarch_tdep (gdbarch); 773 774 if (regnum == -1) 775 { 776 int i; 777 778 for (i = tdep->ppc_vsr0_upper_regnum; 779 i < tdep->ppc_vsr0_upper_regnum + 32; 780 i++) 781 ppc_collect_reg (regcache, i, (gdb_byte *) vsxregs, 0, 8); 782 783 return; 784 } 785 else 786 ppc_collect_reg (regcache, regnum, (gdb_byte *) vsxregs, 0, 8); 787 } 788 789 790 /* Collect register REGNUM in the Altivec register set 791 REGSET from register cache REGCACHE into the buffer specified by 792 VRREGS and LEN. If REGNUM is -1, do this for all registers in 793 REGSET. */ 794 795 void 796 ppc_collect_vrregset (const struct regset *regset, 797 const struct regcache *regcache, 798 int regnum, void *vrregs, size_t len) 799 { 800 struct gdbarch *gdbarch = get_regcache_arch (regcache); 801 struct gdbarch_tdep *tdep; 802 const struct ppc_reg_offsets *offsets; 803 size_t offset; 804 805 if (!ppc_altivec_support_p (gdbarch)) 806 return; 807 808 tdep = gdbarch_tdep (gdbarch); 809 offsets = (const struct ppc_reg_offsets *) regset->regmap; 810 if (regnum == -1) 811 { 812 int i; 813 814 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset; 815 i < tdep->ppc_vr0_regnum + ppc_num_vrs; 816 i++, offset += 16) 817 ppc_collect_reg (regcache, i, (gdb_byte *) vrregs, offset, 16); 818 819 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1), 820 (gdb_byte *) vrregs, offsets->vscr_offset, 4); 821 822 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum, 823 (gdb_byte *) vrregs, offsets->vrsave_offset, 4); 824 return; 825 } 826 827 offset = ppc_vrreg_offset (tdep, offsets, regnum); 828 if (regnum != tdep->ppc_vrsave_regnum 829 && regnum != tdep->ppc_vrsave_regnum - 1) 830 ppc_collect_reg (regcache, regnum, (gdb_byte *) vrregs, offset, 16); 831 else 832 ppc_collect_reg (regcache, regnum, 833 (gdb_byte *) vrregs, offset, 4); 834 } 835 836 837 static int 838 insn_changes_sp_or_jumps (unsigned long insn) 839 { 840 int opcode = (insn >> 26) & 0x03f; 841 int sd = (insn >> 21) & 0x01f; 842 int a = (insn >> 16) & 0x01f; 843 int subcode = (insn >> 1) & 0x3ff; 844 845 /* Changes the stack pointer. */ 846 847 /* NOTE: There are many ways to change the value of a given register. 848 The ways below are those used when the register is R1, the SP, 849 in a funtion's epilogue. */ 850 851 if (opcode == 31 && subcode == 444 && a == 1) 852 return 1; /* mr R1,Rn */ 853 if (opcode == 14 && sd == 1) 854 return 1; /* addi R1,Rn,simm */ 855 if (opcode == 58 && sd == 1) 856 return 1; /* ld R1,ds(Rn) */ 857 858 /* Transfers control. */ 859 860 if (opcode == 18) 861 return 1; /* b */ 862 if (opcode == 16) 863 return 1; /* bc */ 864 if (opcode == 19 && subcode == 16) 865 return 1; /* bclr */ 866 if (opcode == 19 && subcode == 528) 867 return 1; /* bcctr */ 868 869 return 0; 870 } 871 872 /* Return true if we are in the function's epilogue, i.e. after the 873 instruction that destroyed the function's stack frame. 874 875 1) scan forward from the point of execution: 876 a) If you find an instruction that modifies the stack pointer 877 or transfers control (except a return), execution is not in 878 an epilogue, return. 879 b) Stop scanning if you find a return instruction or reach the 880 end of the function or reach the hard limit for the size of 881 an epilogue. 882 2) scan backward from the point of execution: 883 a) If you find an instruction that modifies the stack pointer, 884 execution *is* in an epilogue, return. 885 b) Stop scanning if you reach an instruction that transfers 886 control or the beginning of the function or reach the hard 887 limit for the size of an epilogue. */ 888 889 static int 890 rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm, 891 struct gdbarch *gdbarch, CORE_ADDR pc) 892 { 893 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 894 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 895 bfd_byte insn_buf[PPC_INSN_SIZE]; 896 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; 897 unsigned long insn; 898 899 /* Find the search limits based on function boundaries and hard limit. */ 900 901 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) 902 return 0; 903 904 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 905 if (epilogue_start < func_start) epilogue_start = func_start; 906 907 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 908 if (epilogue_end > func_end) epilogue_end = func_end; 909 910 /* Scan forward until next 'blr'. */ 911 912 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) 913 { 914 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) 915 return 0; 916 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); 917 if (insn == 0x4e800020) 918 break; 919 /* Assume a bctr is a tail call unless it points strictly within 920 this function. */ 921 if (insn == 0x4e800420) 922 { 923 CORE_ADDR ctr = get_frame_register_unsigned (curfrm, 924 tdep->ppc_ctr_regnum); 925 if (ctr > func_start && ctr < func_end) 926 return 0; 927 else 928 break; 929 } 930 if (insn_changes_sp_or_jumps (insn)) 931 return 0; 932 } 933 934 /* Scan backward until adjustment to stack pointer (R1). */ 935 936 for (scan_pc = pc - PPC_INSN_SIZE; 937 scan_pc >= epilogue_start; 938 scan_pc -= PPC_INSN_SIZE) 939 { 940 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) 941 return 0; 942 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); 943 if (insn_changes_sp_or_jumps (insn)) 944 return 1; 945 } 946 947 return 0; 948 } 949 950 /* Implement the stack_frame_destroyed_p gdbarch method. */ 951 952 static int 953 rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 954 { 955 return rs6000_in_function_epilogue_frame_p (get_current_frame (), 956 gdbarch, pc); 957 } 958 959 /* Get the ith function argument for the current function. */ 960 static CORE_ADDR 961 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 962 struct type *type) 963 { 964 return get_frame_register_unsigned (frame, 3 + argi); 965 } 966 967 /* Sequence of bytes for breakpoint instruction. */ 968 969 static const unsigned char * 970 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr, 971 int *bp_size) 972 { 973 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; 974 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; 975 *bp_size = 4; 976 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 977 return big_breakpoint; 978 else 979 return little_breakpoint; 980 } 981 982 /* Instruction masks for displaced stepping. */ 983 #define BRANCH_MASK 0xfc000000 984 #define BP_MASK 0xFC0007FE 985 #define B_INSN 0x48000000 986 #define BC_INSN 0x40000000 987 #define BXL_INSN 0x4c000000 988 #define BP_INSN 0x7C000008 989 990 /* Instruction masks used during single-stepping of atomic 991 sequences. */ 992 #define LWARX_MASK 0xfc0007fe 993 #define LWARX_INSTRUCTION 0x7c000028 994 #define LDARX_INSTRUCTION 0x7c0000A8 995 #define STWCX_MASK 0xfc0007ff 996 #define STWCX_INSTRUCTION 0x7c00012d 997 #define STDCX_INSTRUCTION 0x7c0001ad 998 999 /* We can't displaced step atomic sequences. Otherwise this is just 1000 like simple_displaced_step_copy_insn. */ 1001 1002 static struct displaced_step_closure * 1003 ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, 1004 CORE_ADDR from, CORE_ADDR to, 1005 struct regcache *regs) 1006 { 1007 size_t len = gdbarch_max_insn_length (gdbarch); 1008 gdb_byte *buf = (gdb_byte *) xmalloc (len); 1009 struct cleanup *old_chain = make_cleanup (xfree, buf); 1010 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1011 int insn; 1012 1013 read_memory (from, buf, len); 1014 1015 insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order); 1016 1017 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ 1018 if ((insn & LWARX_MASK) == LWARX_INSTRUCTION 1019 || (insn & LWARX_MASK) == LDARX_INSTRUCTION) 1020 { 1021 if (debug_displaced) 1022 { 1023 fprintf_unfiltered (gdb_stdlog, 1024 "displaced: can't displaced step " 1025 "atomic sequence at %s\n", 1026 paddress (gdbarch, from)); 1027 } 1028 do_cleanups (old_chain); 1029 return NULL; 1030 } 1031 1032 write_memory (to, buf, len); 1033 1034 if (debug_displaced) 1035 { 1036 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ", 1037 paddress (gdbarch, from), paddress (gdbarch, to)); 1038 displaced_step_dump_bytes (gdb_stdlog, buf, len); 1039 } 1040 1041 discard_cleanups (old_chain); 1042 return (struct displaced_step_closure *) buf; 1043 } 1044 1045 /* Fix up the state of registers and memory after having single-stepped 1046 a displaced instruction. */ 1047 static void 1048 ppc_displaced_step_fixup (struct gdbarch *gdbarch, 1049 struct displaced_step_closure *closure, 1050 CORE_ADDR from, CORE_ADDR to, 1051 struct regcache *regs) 1052 { 1053 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1054 /* Our closure is a copy of the instruction. */ 1055 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure, 1056 PPC_INSN_SIZE, byte_order); 1057 ULONGEST opcode = 0; 1058 /* Offset for non PC-relative instructions. */ 1059 LONGEST offset = PPC_INSN_SIZE; 1060 1061 opcode = insn & BRANCH_MASK; 1062 1063 if (debug_displaced) 1064 fprintf_unfiltered (gdb_stdlog, 1065 "displaced: (ppc) fixup (%s, %s)\n", 1066 paddress (gdbarch, from), paddress (gdbarch, to)); 1067 1068 1069 /* Handle PC-relative branch instructions. */ 1070 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) 1071 { 1072 ULONGEST current_pc; 1073 1074 /* Read the current PC value after the instruction has been executed 1075 in a displaced location. Calculate the offset to be applied to the 1076 original PC value before the displaced stepping. */ 1077 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1078 ¤t_pc); 1079 offset = current_pc - to; 1080 1081 if (opcode != BXL_INSN) 1082 { 1083 /* Check for AA bit indicating whether this is an absolute 1084 addressing or PC-relative (1: absolute, 0: relative). */ 1085 if (!(insn & 0x2)) 1086 { 1087 /* PC-relative addressing is being used in the branch. */ 1088 if (debug_displaced) 1089 fprintf_unfiltered 1090 (gdb_stdlog, 1091 "displaced: (ppc) branch instruction: %s\n" 1092 "displaced: (ppc) adjusted PC from %s to %s\n", 1093 paddress (gdbarch, insn), paddress (gdbarch, current_pc), 1094 paddress (gdbarch, from + offset)); 1095 1096 regcache_cooked_write_unsigned (regs, 1097 gdbarch_pc_regnum (gdbarch), 1098 from + offset); 1099 } 1100 } 1101 else 1102 { 1103 /* If we're here, it means we have a branch to LR or CTR. If the 1104 branch was taken, the offset is probably greater than 4 (the next 1105 instruction), so it's safe to assume that an offset of 4 means we 1106 did not take the branch. */ 1107 if (offset == PPC_INSN_SIZE) 1108 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1109 from + PPC_INSN_SIZE); 1110 } 1111 1112 /* Check for LK bit indicating whether we should set the link 1113 register to point to the next instruction 1114 (1: Set, 0: Don't set). */ 1115 if (insn & 0x1) 1116 { 1117 /* Link register needs to be set to the next instruction's PC. */ 1118 regcache_cooked_write_unsigned (regs, 1119 gdbarch_tdep (gdbarch)->ppc_lr_regnum, 1120 from + PPC_INSN_SIZE); 1121 if (debug_displaced) 1122 fprintf_unfiltered (gdb_stdlog, 1123 "displaced: (ppc) adjusted LR to %s\n", 1124 paddress (gdbarch, from + PPC_INSN_SIZE)); 1125 1126 } 1127 } 1128 /* Check for breakpoints in the inferior. If we've found one, place the PC 1129 right at the breakpoint instruction. */ 1130 else if ((insn & BP_MASK) == BP_INSN) 1131 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); 1132 else 1133 /* Handle any other instructions that do not fit in the categories above. */ 1134 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1135 from + offset); 1136 } 1137 1138 /* Always use hardware single-stepping to execute the 1139 displaced instruction. */ 1140 static int 1141 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch, 1142 struct displaced_step_closure *closure) 1143 { 1144 return 1; 1145 } 1146 1147 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX 1148 instruction and ending with a STWCX/STDCX instruction. If such a sequence 1149 is found, attempt to step through it. A breakpoint is placed at the end of 1150 the sequence. */ 1151 1152 int 1153 ppc_deal_with_atomic_sequence (struct frame_info *frame) 1154 { 1155 struct gdbarch *gdbarch = get_frame_arch (frame); 1156 struct address_space *aspace = get_frame_address_space (frame); 1157 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1158 CORE_ADDR pc = get_frame_pc (frame); 1159 CORE_ADDR breaks[2] = {-1, -1}; 1160 CORE_ADDR loc = pc; 1161 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ 1162 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); 1163 int insn_count; 1164 int index; 1165 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 1166 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 1167 int bc_insn_count = 0; /* Conditional branch instruction count. */ 1168 1169 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ 1170 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION 1171 && (insn & LWARX_MASK) != LDARX_INSTRUCTION) 1172 return 0; 1173 1174 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 1175 instructions. */ 1176 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 1177 { 1178 loc += PPC_INSN_SIZE; 1179 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); 1180 1181 /* Assume that there is at most one conditional branch in the atomic 1182 sequence. If a conditional branch is found, put a breakpoint in 1183 its destination address. */ 1184 if ((insn & BRANCH_MASK) == BC_INSN) 1185 { 1186 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1187 int absolute = insn & 2; 1188 1189 if (bc_insn_count >= 1) 1190 return 0; /* More than one conditional branch found, fallback 1191 to the standard single-step code. */ 1192 1193 if (absolute) 1194 breaks[1] = immediate; 1195 else 1196 breaks[1] = loc + immediate; 1197 1198 bc_insn_count++; 1199 last_breakpoint++; 1200 } 1201 1202 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION 1203 || (insn & STWCX_MASK) == STDCX_INSTRUCTION) 1204 break; 1205 } 1206 1207 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ 1208 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION 1209 && (insn & STWCX_MASK) != STDCX_INSTRUCTION) 1210 return 0; 1211 1212 closing_insn = loc; 1213 loc += PPC_INSN_SIZE; 1214 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); 1215 1216 /* Insert a breakpoint right after the end of the atomic sequence. */ 1217 breaks[0] = loc; 1218 1219 /* Check for duplicated breakpoints. Check also for a breakpoint 1220 placed (branch instruction's destination) anywhere in sequence. */ 1221 if (last_breakpoint 1222 && (breaks[1] == breaks[0] 1223 || (breaks[1] >= pc && breaks[1] <= closing_insn))) 1224 last_breakpoint = 0; 1225 1226 /* Effectively inserts the breakpoints. */ 1227 for (index = 0; index <= last_breakpoint; index++) 1228 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); 1229 1230 return 1; 1231 } 1232 1233 1234 #define SIGNED_SHORT(x) \ 1235 ((sizeof (short) == 2) \ 1236 ? ((int)(short)(x)) \ 1237 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 1238 1239 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 1240 1241 /* Limit the number of skipped non-prologue instructions, as the examining 1242 of the prologue is expensive. */ 1243 static int max_skip_non_prologue_insns = 10; 1244 1245 /* Return nonzero if the given instruction OP can be part of the prologue 1246 of a function and saves a parameter on the stack. FRAMEP should be 1247 set if one of the previous instructions in the function has set the 1248 Frame Pointer. */ 1249 1250 static int 1251 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) 1252 { 1253 /* Move parameters from argument registers to temporary register. */ 1254 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ 1255 { 1256 /* Rx must be scratch register r0. */ 1257 const int rx_regno = (op >> 16) & 31; 1258 /* Ry: Only r3 - r10 are used for parameter passing. */ 1259 const int ry_regno = GET_SRC_REG (op); 1260 1261 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) 1262 { 1263 *r0_contains_arg = 1; 1264 return 1; 1265 } 1266 else 1267 return 0; 1268 } 1269 1270 /* Save a General Purpose Register on stack. */ 1271 1272 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ 1273 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ 1274 { 1275 /* Rx: Only r3 - r10 are used for parameter passing. */ 1276 const int rx_regno = GET_SRC_REG (op); 1277 1278 return (rx_regno >= 3 && rx_regno <= 10); 1279 } 1280 1281 /* Save a General Purpose Register on stack via the Frame Pointer. */ 1282 1283 if (framep && 1284 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ 1285 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ 1286 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ 1287 { 1288 /* Rx: Usually, only r3 - r10 are used for parameter passing. 1289 However, the compiler sometimes uses r0 to hold an argument. */ 1290 const int rx_regno = GET_SRC_REG (op); 1291 1292 return ((rx_regno >= 3 && rx_regno <= 10) 1293 || (rx_regno == 0 && *r0_contains_arg)); 1294 } 1295 1296 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 1297 { 1298 /* Only f2 - f8 are used for parameter passing. */ 1299 const int src_regno = GET_SRC_REG (op); 1300 1301 return (src_regno >= 2 && src_regno <= 8); 1302 } 1303 1304 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ 1305 { 1306 /* Only f2 - f8 are used for parameter passing. */ 1307 const int src_regno = GET_SRC_REG (op); 1308 1309 return (src_regno >= 2 && src_regno <= 8); 1310 } 1311 1312 /* Not an insn that saves a parameter on stack. */ 1313 return 0; 1314 } 1315 1316 /* Assuming that INSN is a "bl" instruction located at PC, return 1317 nonzero if the destination of the branch is a "blrl" instruction. 1318 1319 This sequence is sometimes found in certain function prologues. 1320 It allows the function to load the LR register with a value that 1321 they can use to access PIC data using PC-relative offsets. */ 1322 1323 static int 1324 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) 1325 { 1326 CORE_ADDR dest; 1327 int immediate; 1328 int absolute; 1329 int dest_insn; 1330 1331 absolute = (int) ((insn >> 1) & 1); 1332 immediate = ((insn & ~3) << 6) >> 6; 1333 if (absolute) 1334 dest = immediate; 1335 else 1336 dest = pc + immediate; 1337 1338 dest_insn = read_memory_integer (dest, 4, byte_order); 1339 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ 1340 return 1; 1341 1342 return 0; 1343 } 1344 1345 /* Masks for decoding a branch-and-link (bl) instruction. 1346 1347 BL_MASK and BL_INSTRUCTION are used in combination with each other. 1348 The former is anded with the opcode in question; if the result of 1349 this masking operation is equal to BL_INSTRUCTION, then the opcode in 1350 question is a ``bl'' instruction. 1351 1352 BL_DISPLACMENT_MASK is anded with the opcode in order to extract 1353 the branch displacement. */ 1354 1355 #define BL_MASK 0xfc000001 1356 #define BL_INSTRUCTION 0x48000001 1357 #define BL_DISPLACEMENT_MASK 0x03fffffc 1358 1359 static unsigned long 1360 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) 1361 { 1362 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1363 gdb_byte buf[4]; 1364 unsigned long op; 1365 1366 /* Fetch the instruction and convert it to an integer. */ 1367 if (target_read_memory (pc, buf, 4)) 1368 return 0; 1369 op = extract_unsigned_integer (buf, 4, byte_order); 1370 1371 return op; 1372 } 1373 1374 /* GCC generates several well-known sequences of instructions at the begining 1375 of each function prologue when compiling with -fstack-check. If one of 1376 such sequences starts at START_PC, then return the address of the 1377 instruction immediately past this sequence. Otherwise, return START_PC. */ 1378 1379 static CORE_ADDR 1380 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) 1381 { 1382 CORE_ADDR pc = start_pc; 1383 unsigned long op = rs6000_fetch_instruction (gdbarch, pc); 1384 1385 /* First possible sequence: A small number of probes. 1386 stw 0, -<some immediate>(1) 1387 [repeat this instruction any (small) number of times]. */ 1388 1389 if ((op & 0xffff0000) == 0x90010000) 1390 { 1391 while ((op & 0xffff0000) == 0x90010000) 1392 { 1393 pc = pc + 4; 1394 op = rs6000_fetch_instruction (gdbarch, pc); 1395 } 1396 return pc; 1397 } 1398 1399 /* Second sequence: A probing loop. 1400 addi 12,1,-<some immediate> 1401 lis 0,-<some immediate> 1402 [possibly ori 0,0,<some immediate>] 1403 add 0,12,0 1404 cmpw 0,12,0 1405 beq 0,<disp> 1406 addi 12,12,-<some immediate> 1407 stw 0,0(12) 1408 b <disp> 1409 [possibly one last probe: stw 0,<some immediate>(12)]. */ 1410 1411 while (1) 1412 { 1413 /* addi 12,1,-<some immediate> */ 1414 if ((op & 0xffff0000) != 0x39810000) 1415 break; 1416 1417 /* lis 0,-<some immediate> */ 1418 pc = pc + 4; 1419 op = rs6000_fetch_instruction (gdbarch, pc); 1420 if ((op & 0xffff0000) != 0x3c000000) 1421 break; 1422 1423 pc = pc + 4; 1424 op = rs6000_fetch_instruction (gdbarch, pc); 1425 /* [possibly ori 0,0,<some immediate>] */ 1426 if ((op & 0xffff0000) == 0x60000000) 1427 { 1428 pc = pc + 4; 1429 op = rs6000_fetch_instruction (gdbarch, pc); 1430 } 1431 /* add 0,12,0 */ 1432 if (op != 0x7c0c0214) 1433 break; 1434 1435 /* cmpw 0,12,0 */ 1436 pc = pc + 4; 1437 op = rs6000_fetch_instruction (gdbarch, pc); 1438 if (op != 0x7c0c0000) 1439 break; 1440 1441 /* beq 0,<disp> */ 1442 pc = pc + 4; 1443 op = rs6000_fetch_instruction (gdbarch, pc); 1444 if ((op & 0xff9f0001) != 0x41820000) 1445 break; 1446 1447 /* addi 12,12,-<some immediate> */ 1448 pc = pc + 4; 1449 op = rs6000_fetch_instruction (gdbarch, pc); 1450 if ((op & 0xffff0000) != 0x398c0000) 1451 break; 1452 1453 /* stw 0,0(12) */ 1454 pc = pc + 4; 1455 op = rs6000_fetch_instruction (gdbarch, pc); 1456 if (op != 0x900c0000) 1457 break; 1458 1459 /* b <disp> */ 1460 pc = pc + 4; 1461 op = rs6000_fetch_instruction (gdbarch, pc); 1462 if ((op & 0xfc000001) != 0x48000000) 1463 break; 1464 1465 /* [possibly one last probe: stw 0,<some immediate>(12)]. */ 1466 pc = pc + 4; 1467 op = rs6000_fetch_instruction (gdbarch, pc); 1468 if ((op & 0xffff0000) == 0x900c0000) 1469 { 1470 pc = pc + 4; 1471 op = rs6000_fetch_instruction (gdbarch, pc); 1472 } 1473 1474 /* We found a valid stack-check sequence, return the new PC. */ 1475 return pc; 1476 } 1477 1478 /* Third sequence: No probe; instead, a comparizon between the stack size 1479 limit (saved in a run-time global variable) and the current stack 1480 pointer: 1481 1482 addi 0,1,-<some immediate> 1483 lis 12,__gnat_stack_limit@ha 1484 lwz 12,__gnat_stack_limit@l(12) 1485 twllt 0,12 1486 1487 or, with a small variant in the case of a bigger stack frame: 1488 addis 0,1,<some immediate> 1489 addic 0,0,-<some immediate> 1490 lis 12,__gnat_stack_limit@ha 1491 lwz 12,__gnat_stack_limit@l(12) 1492 twllt 0,12 1493 */ 1494 while (1) 1495 { 1496 /* addi 0,1,-<some immediate> */ 1497 if ((op & 0xffff0000) != 0x38010000) 1498 { 1499 /* small stack frame variant not recognized; try the 1500 big stack frame variant: */ 1501 1502 /* addis 0,1,<some immediate> */ 1503 if ((op & 0xffff0000) != 0x3c010000) 1504 break; 1505 1506 /* addic 0,0,-<some immediate> */ 1507 pc = pc + 4; 1508 op = rs6000_fetch_instruction (gdbarch, pc); 1509 if ((op & 0xffff0000) != 0x30000000) 1510 break; 1511 } 1512 1513 /* lis 12,<some immediate> */ 1514 pc = pc + 4; 1515 op = rs6000_fetch_instruction (gdbarch, pc); 1516 if ((op & 0xffff0000) != 0x3d800000) 1517 break; 1518 1519 /* lwz 12,<some immediate>(12) */ 1520 pc = pc + 4; 1521 op = rs6000_fetch_instruction (gdbarch, pc); 1522 if ((op & 0xffff0000) != 0x818c0000) 1523 break; 1524 1525 /* twllt 0,12 */ 1526 pc = pc + 4; 1527 op = rs6000_fetch_instruction (gdbarch, pc); 1528 if ((op & 0xfffffffe) != 0x7c406008) 1529 break; 1530 1531 /* We found a valid stack-check sequence, return the new PC. */ 1532 return pc; 1533 } 1534 1535 /* No stack check code in our prologue, return the start_pc. */ 1536 return start_pc; 1537 } 1538 1539 /* return pc value after skipping a function prologue and also return 1540 information about a function frame. 1541 1542 in struct rs6000_framedata fdata: 1543 - frameless is TRUE, if function does not have a frame. 1544 - nosavedpc is TRUE, if function does not save %pc value in its frame. 1545 - offset is the initial size of this stack frame --- the amount by 1546 which we decrement the sp to allocate the frame. 1547 - saved_gpr is the number of the first saved gpr. 1548 - saved_fpr is the number of the first saved fpr. 1549 - saved_vr is the number of the first saved vr. 1550 - saved_ev is the number of the first saved ev. 1551 - alloca_reg is the number of the register used for alloca() handling. 1552 Otherwise -1. 1553 - gpr_offset is the offset of the first saved gpr from the previous frame. 1554 - fpr_offset is the offset of the first saved fpr from the previous frame. 1555 - vr_offset is the offset of the first saved vr from the previous frame. 1556 - ev_offset is the offset of the first saved ev from the previous frame. 1557 - lr_offset is the offset of the saved lr 1558 - cr_offset is the offset of the saved cr 1559 - vrsave_offset is the offset of the saved vrsave register. */ 1560 1561 static CORE_ADDR 1562 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, 1563 struct rs6000_framedata *fdata) 1564 { 1565 CORE_ADDR orig_pc = pc; 1566 CORE_ADDR last_prologue_pc = pc; 1567 CORE_ADDR li_found_pc = 0; 1568 gdb_byte buf[4]; 1569 unsigned long op; 1570 long offset = 0; 1571 long vr_saved_offset = 0; 1572 int lr_reg = -1; 1573 int cr_reg = -1; 1574 int vr_reg = -1; 1575 int ev_reg = -1; 1576 long ev_offset = 0; 1577 int vrsave_reg = -1; 1578 int reg; 1579 int framep = 0; 1580 int minimal_toc_loaded = 0; 1581 int prev_insn_was_prologue_insn = 1; 1582 int num_skip_non_prologue_insns = 0; 1583 int r0_contains_arg = 0; 1584 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); 1585 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1586 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1587 1588 memset (fdata, 0, sizeof (struct rs6000_framedata)); 1589 fdata->saved_gpr = -1; 1590 fdata->saved_fpr = -1; 1591 fdata->saved_vr = -1; 1592 fdata->saved_ev = -1; 1593 fdata->alloca_reg = -1; 1594 fdata->frameless = 1; 1595 fdata->nosavedpc = 1; 1596 fdata->lr_register = -1; 1597 1598 pc = rs6000_skip_stack_check (gdbarch, pc); 1599 if (pc >= lim_pc) 1600 pc = lim_pc; 1601 1602 for (;; pc += 4) 1603 { 1604 /* Sometimes it isn't clear if an instruction is a prologue 1605 instruction or not. When we encounter one of these ambiguous 1606 cases, we'll set prev_insn_was_prologue_insn to 0 (false). 1607 Otherwise, we'll assume that it really is a prologue instruction. */ 1608 if (prev_insn_was_prologue_insn) 1609 last_prologue_pc = pc; 1610 1611 /* Stop scanning if we've hit the limit. */ 1612 if (pc >= lim_pc) 1613 break; 1614 1615 prev_insn_was_prologue_insn = 1; 1616 1617 /* Fetch the instruction and convert it to an integer. */ 1618 if (target_read_memory (pc, buf, 4)) 1619 break; 1620 op = extract_unsigned_integer (buf, 4, byte_order); 1621 1622 if ((op & 0xfc1fffff) == 0x7c0802a6) 1623 { /* mflr Rx */ 1624 /* Since shared library / PIC code, which needs to get its 1625 address at runtime, can appear to save more than one link 1626 register vis: 1627 1628 *INDENT-OFF* 1629 stwu r1,-304(r1) 1630 mflr r3 1631 bl 0xff570d0 (blrl) 1632 stw r30,296(r1) 1633 mflr r30 1634 stw r31,300(r1) 1635 stw r3,308(r1); 1636 ... 1637 *INDENT-ON* 1638 1639 remember just the first one, but skip over additional 1640 ones. */ 1641 if (lr_reg == -1) 1642 lr_reg = (op & 0x03e00000) >> 21; 1643 if (lr_reg == 0) 1644 r0_contains_arg = 0; 1645 continue; 1646 } 1647 else if ((op & 0xfc1fffff) == 0x7c000026) 1648 { /* mfcr Rx */ 1649 cr_reg = (op & 0x03e00000); 1650 if (cr_reg == 0) 1651 r0_contains_arg = 0; 1652 continue; 1653 1654 } 1655 else if ((op & 0xfc1f0000) == 0xd8010000) 1656 { /* stfd Rx,NUM(r1) */ 1657 reg = GET_SRC_REG (op); 1658 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 1659 { 1660 fdata->saved_fpr = reg; 1661 fdata->fpr_offset = SIGNED_SHORT (op) + offset; 1662 } 1663 continue; 1664 1665 } 1666 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 1667 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 1668 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 1669 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 1670 { 1671 1672 reg = GET_SRC_REG (op); 1673 if ((op & 0xfc1f0000) == 0xbc010000) 1674 fdata->gpr_mask |= ~((1U << reg) - 1); 1675 else 1676 fdata->gpr_mask |= 1U << reg; 1677 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 1678 { 1679 fdata->saved_gpr = reg; 1680 if ((op & 0xfc1f0003) == 0xf8010000) 1681 op &= ~3UL; 1682 fdata->gpr_offset = SIGNED_SHORT (op) + offset; 1683 } 1684 continue; 1685 1686 } 1687 else if ((op & 0xffff0000) == 0x3c4c0000 1688 || (op & 0xffff0000) == 0x3c400000 1689 || (op & 0xffff0000) == 0x38420000) 1690 { 1691 /* . 0: addis 2,12,.TOC.-0b@ha 1692 . addi 2,2,.TOC.-0b@l 1693 or 1694 . lis 2,.TOC.@ha 1695 . addi 2,2,.TOC.@l 1696 used by ELFv2 global entry points to set up r2. */ 1697 continue; 1698 } 1699 else if (op == 0x60000000) 1700 { 1701 /* nop */ 1702 /* Allow nops in the prologue, but do not consider them to 1703 be part of the prologue unless followed by other prologue 1704 instructions. */ 1705 prev_insn_was_prologue_insn = 0; 1706 continue; 1707 1708 } 1709 else if ((op & 0xffff0000) == 0x3c000000) 1710 { /* addis 0,0,NUM, used for >= 32k frames */ 1711 fdata->offset = (op & 0x0000ffff) << 16; 1712 fdata->frameless = 0; 1713 r0_contains_arg = 0; 1714 continue; 1715 1716 } 1717 else if ((op & 0xffff0000) == 0x60000000) 1718 { /* ori 0,0,NUM, 2nd half of >= 32k frames */ 1719 fdata->offset |= (op & 0x0000ffff); 1720 fdata->frameless = 0; 1721 r0_contains_arg = 0; 1722 continue; 1723 1724 } 1725 else if (lr_reg >= 0 && 1726 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 1727 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || 1728 /* stw Rx, NUM(r1) */ 1729 ((op & 0xffff0000) == (lr_reg | 0x90010000)) || 1730 /* stwu Rx, NUM(r1) */ 1731 ((op & 0xffff0000) == (lr_reg | 0x94010000)))) 1732 { /* where Rx == lr */ 1733 fdata->lr_offset = offset; 1734 fdata->nosavedpc = 0; 1735 /* Invalidate lr_reg, but don't set it to -1. 1736 That would mean that it had never been set. */ 1737 lr_reg = -2; 1738 if ((op & 0xfc000003) == 0xf8000000 || /* std */ 1739 (op & 0xfc000000) == 0x90000000) /* stw */ 1740 { 1741 /* Does not update r1, so add displacement to lr_offset. */ 1742 fdata->lr_offset += SIGNED_SHORT (op); 1743 } 1744 continue; 1745 1746 } 1747 else if (cr_reg >= 0 && 1748 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 1749 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || 1750 /* stw Rx, NUM(r1) */ 1751 ((op & 0xffff0000) == (cr_reg | 0x90010000)) || 1752 /* stwu Rx, NUM(r1) */ 1753 ((op & 0xffff0000) == (cr_reg | 0x94010000)))) 1754 { /* where Rx == cr */ 1755 fdata->cr_offset = offset; 1756 /* Invalidate cr_reg, but don't set it to -1. 1757 That would mean that it had never been set. */ 1758 cr_reg = -2; 1759 if ((op & 0xfc000003) == 0xf8000000 || 1760 (op & 0xfc000000) == 0x90000000) 1761 { 1762 /* Does not update r1, so add displacement to cr_offset. */ 1763 fdata->cr_offset += SIGNED_SHORT (op); 1764 } 1765 continue; 1766 1767 } 1768 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) 1769 { 1770 /* bcl 20,xx,.+4 is used to get the current PC, with or without 1771 prediction bits. If the LR has already been saved, we can 1772 skip it. */ 1773 continue; 1774 } 1775 else if (op == 0x48000005) 1776 { /* bl .+4 used in 1777 -mrelocatable */ 1778 fdata->used_bl = 1; 1779 continue; 1780 1781 } 1782 else if (op == 0x48000004) 1783 { /* b .+4 (xlc) */ 1784 break; 1785 1786 } 1787 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 1788 in V.4 -mminimal-toc */ 1789 (op & 0xffff0000) == 0x3bde0000) 1790 { /* addi 30,30,foo@l */ 1791 continue; 1792 1793 } 1794 else if ((op & 0xfc000001) == 0x48000001) 1795 { /* bl foo, 1796 to save fprs??? */ 1797 1798 fdata->frameless = 0; 1799 1800 /* If the return address has already been saved, we can skip 1801 calls to blrl (for PIC). */ 1802 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) 1803 { 1804 fdata->used_bl = 1; 1805 continue; 1806 } 1807 1808 /* Don't skip over the subroutine call if it is not within 1809 the first three instructions of the prologue and either 1810 we have no line table information or the line info tells 1811 us that the subroutine call is not part of the line 1812 associated with the prologue. */ 1813 if ((pc - orig_pc) > 8) 1814 { 1815 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); 1816 struct symtab_and_line this_sal = find_pc_line (pc, 0); 1817 1818 if ((prologue_sal.line == 0) 1819 || (prologue_sal.line != this_sal.line)) 1820 break; 1821 } 1822 1823 op = read_memory_integer (pc + 4, 4, byte_order); 1824 1825 /* At this point, make sure this is not a trampoline 1826 function (a function that simply calls another functions, 1827 and nothing else). If the next is not a nop, this branch 1828 was part of the function prologue. */ 1829 1830 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 1831 break; /* Don't skip over 1832 this branch. */ 1833 1834 fdata->used_bl = 1; 1835 continue; 1836 } 1837 /* update stack pointer */ 1838 else if ((op & 0xfc1f0000) == 0x94010000) 1839 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 1840 fdata->frameless = 0; 1841 fdata->offset = SIGNED_SHORT (op); 1842 offset = fdata->offset; 1843 continue; 1844 } 1845 else if ((op & 0xfc1f016a) == 0x7c01016e) 1846 { /* stwux rX,r1,rY */ 1847 /* No way to figure out what r1 is going to be. */ 1848 fdata->frameless = 0; 1849 offset = fdata->offset; 1850 continue; 1851 } 1852 else if ((op & 0xfc1f0003) == 0xf8010001) 1853 { /* stdu rX,NUM(r1) */ 1854 fdata->frameless = 0; 1855 fdata->offset = SIGNED_SHORT (op & ~3UL); 1856 offset = fdata->offset; 1857 continue; 1858 } 1859 else if ((op & 0xfc1f016a) == 0x7c01016a) 1860 { /* stdux rX,r1,rY */ 1861 /* No way to figure out what r1 is going to be. */ 1862 fdata->frameless = 0; 1863 offset = fdata->offset; 1864 continue; 1865 } 1866 else if ((op & 0xffff0000) == 0x38210000) 1867 { /* addi r1,r1,SIMM */ 1868 fdata->frameless = 0; 1869 fdata->offset += SIGNED_SHORT (op); 1870 offset = fdata->offset; 1871 continue; 1872 } 1873 /* Load up minimal toc pointer. Do not treat an epilogue restore 1874 of r31 as a minimal TOC load. */ 1875 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 1876 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 1877 && !framep 1878 && !minimal_toc_loaded) 1879 { 1880 minimal_toc_loaded = 1; 1881 continue; 1882 1883 /* move parameters from argument registers to local variable 1884 registers */ 1885 } 1886 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 1887 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 1888 (((op >> 21) & 31) <= 10) && 1889 ((long) ((op >> 16) & 31) 1890 >= fdata->saved_gpr)) /* Rx: local var reg */ 1891 { 1892 continue; 1893 1894 /* store parameters in stack */ 1895 } 1896 /* Move parameters from argument registers to temporary register. */ 1897 else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) 1898 { 1899 continue; 1900 1901 /* Set up frame pointer */ 1902 } 1903 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ 1904 { 1905 fdata->frameless = 0; 1906 framep = 1; 1907 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); 1908 continue; 1909 1910 /* Another way to set up the frame pointer. */ 1911 } 1912 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 1913 || op == 0x7c3f0b78) 1914 { /* mr r31, r1 */ 1915 fdata->frameless = 0; 1916 framep = 1; 1917 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 1918 continue; 1919 1920 /* Another way to set up the frame pointer. */ 1921 } 1922 else if ((op & 0xfc1fffff) == 0x38010000) 1923 { /* addi rX, r1, 0x0 */ 1924 fdata->frameless = 0; 1925 framep = 1; 1926 fdata->alloca_reg = (tdep->ppc_gp0_regnum 1927 + ((op & ~0x38010000) >> 21)); 1928 continue; 1929 } 1930 /* AltiVec related instructions. */ 1931 /* Store the vrsave register (spr 256) in another register for 1932 later manipulation, or load a register into the vrsave 1933 register. 2 instructions are used: mfvrsave and 1934 mtvrsave. They are shorthand notation for mfspr Rn, SPR256 1935 and mtspr SPR256, Rn. */ 1936 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 1937 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 1938 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 1939 { 1940 vrsave_reg = GET_SRC_REG (op); 1941 continue; 1942 } 1943 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 1944 { 1945 continue; 1946 } 1947 /* Store the register where vrsave was saved to onto the stack: 1948 rS is the register where vrsave was stored in a previous 1949 instruction. */ 1950 /* 100100 sssss 00001 dddddddd dddddddd */ 1951 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 1952 { 1953 if (vrsave_reg == GET_SRC_REG (op)) 1954 { 1955 fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 1956 vrsave_reg = -1; 1957 } 1958 continue; 1959 } 1960 /* Compute the new value of vrsave, by modifying the register 1961 where vrsave was saved to. */ 1962 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 1963 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 1964 { 1965 continue; 1966 } 1967 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 1968 in a pair of insns to save the vector registers on the 1969 stack. */ 1970 /* 001110 00000 00000 iiii iiii iiii iiii */ 1971 /* 001110 01110 00000 iiii iiii iiii iiii */ 1972 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 1973 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 1974 { 1975 if ((op & 0xffff0000) == 0x38000000) 1976 r0_contains_arg = 0; 1977 li_found_pc = pc; 1978 vr_saved_offset = SIGNED_SHORT (op); 1979 1980 /* This insn by itself is not part of the prologue, unless 1981 if part of the pair of insns mentioned above. So do not 1982 record this insn as part of the prologue yet. */ 1983 prev_insn_was_prologue_insn = 0; 1984 } 1985 /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 1986 /* 011111 sssss 11111 00000 00111001110 */ 1987 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 1988 { 1989 if (pc == (li_found_pc + 4)) 1990 { 1991 vr_reg = GET_SRC_REG (op); 1992 /* If this is the first vector reg to be saved, or if 1993 it has a lower number than others previously seen, 1994 reupdate the frame info. */ 1995 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 1996 { 1997 fdata->saved_vr = vr_reg; 1998 fdata->vr_offset = vr_saved_offset + offset; 1999 } 2000 vr_saved_offset = -1; 2001 vr_reg = -1; 2002 li_found_pc = 0; 2003 } 2004 } 2005 /* End AltiVec related instructions. */ 2006 2007 /* Start BookE related instructions. */ 2008 /* Store gen register S at (r31+uimm). 2009 Any register less than r13 is volatile, so we don't care. */ 2010 /* 000100 sssss 11111 iiiii 01100100001 */ 2011 else if (arch_info->mach == bfd_mach_ppc_e500 2012 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 2013 { 2014 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 2015 { 2016 unsigned int imm; 2017 ev_reg = GET_SRC_REG (op); 2018 imm = (op >> 11) & 0x1f; 2019 ev_offset = imm * 8; 2020 /* If this is the first vector reg to be saved, or if 2021 it has a lower number than others previously seen, 2022 reupdate the frame info. */ 2023 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2024 { 2025 fdata->saved_ev = ev_reg; 2026 fdata->ev_offset = ev_offset + offset; 2027 } 2028 } 2029 continue; 2030 } 2031 /* Store gen register rS at (r1+rB). */ 2032 /* 000100 sssss 00001 bbbbb 01100100000 */ 2033 else if (arch_info->mach == bfd_mach_ppc_e500 2034 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 2035 { 2036 if (pc == (li_found_pc + 4)) 2037 { 2038 ev_reg = GET_SRC_REG (op); 2039 /* If this is the first vector reg to be saved, or if 2040 it has a lower number than others previously seen, 2041 reupdate the frame info. */ 2042 /* We know the contents of rB from the previous instruction. */ 2043 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2044 { 2045 fdata->saved_ev = ev_reg; 2046 fdata->ev_offset = vr_saved_offset + offset; 2047 } 2048 vr_saved_offset = -1; 2049 ev_reg = -1; 2050 li_found_pc = 0; 2051 } 2052 continue; 2053 } 2054 /* Store gen register r31 at (rA+uimm). */ 2055 /* 000100 11111 aaaaa iiiii 01100100001 */ 2056 else if (arch_info->mach == bfd_mach_ppc_e500 2057 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 2058 { 2059 /* Wwe know that the source register is 31 already, but 2060 it can't hurt to compute it. */ 2061 ev_reg = GET_SRC_REG (op); 2062 ev_offset = ((op >> 11) & 0x1f) * 8; 2063 /* If this is the first vector reg to be saved, or if 2064 it has a lower number than others previously seen, 2065 reupdate the frame info. */ 2066 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2067 { 2068 fdata->saved_ev = ev_reg; 2069 fdata->ev_offset = ev_offset + offset; 2070 } 2071 2072 continue; 2073 } 2074 /* Store gen register S at (r31+r0). 2075 Store param on stack when offset from SP bigger than 4 bytes. */ 2076 /* 000100 sssss 11111 00000 01100100000 */ 2077 else if (arch_info->mach == bfd_mach_ppc_e500 2078 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 2079 { 2080 if (pc == (li_found_pc + 4)) 2081 { 2082 if ((op & 0x03e00000) >= 0x01a00000) 2083 { 2084 ev_reg = GET_SRC_REG (op); 2085 /* If this is the first vector reg to be saved, or if 2086 it has a lower number than others previously seen, 2087 reupdate the frame info. */ 2088 /* We know the contents of r0 from the previous 2089 instruction. */ 2090 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2091 { 2092 fdata->saved_ev = ev_reg; 2093 fdata->ev_offset = vr_saved_offset + offset; 2094 } 2095 ev_reg = -1; 2096 } 2097 vr_saved_offset = -1; 2098 li_found_pc = 0; 2099 continue; 2100 } 2101 } 2102 /* End BookE related instructions. */ 2103 2104 else 2105 { 2106 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); 2107 2108 /* Not a recognized prologue instruction. 2109 Handle optimizer code motions into the prologue by continuing 2110 the search if we have no valid frame yet or if the return 2111 address is not yet saved in the frame. Also skip instructions 2112 if some of the GPRs expected to be saved are not yet saved. */ 2113 if (fdata->frameless == 0 && fdata->nosavedpc == 0 2114 && (fdata->gpr_mask & all_mask) == all_mask) 2115 break; 2116 2117 if (op == 0x4e800020 /* blr */ 2118 || op == 0x4e800420) /* bctr */ 2119 /* Do not scan past epilogue in frameless functions or 2120 trampolines. */ 2121 break; 2122 if ((op & 0xf4000000) == 0x40000000) /* bxx */ 2123 /* Never skip branches. */ 2124 break; 2125 2126 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 2127 /* Do not scan too many insns, scanning insns is expensive with 2128 remote targets. */ 2129 break; 2130 2131 /* Continue scanning. */ 2132 prev_insn_was_prologue_insn = 0; 2133 continue; 2134 } 2135 } 2136 2137 #if 0 2138 /* I have problems with skipping over __main() that I need to address 2139 * sometime. Previously, I used to use misc_function_vector which 2140 * didn't work as well as I wanted to be. -MGO */ 2141 2142 /* If the first thing after skipping a prolog is a branch to a function, 2143 this might be a call to an initializer in main(), introduced by gcc2. 2144 We'd like to skip over it as well. Fortunately, xlc does some extra 2145 work before calling a function right after a prologue, thus we can 2146 single out such gcc2 behaviour. */ 2147 2148 2149 if ((op & 0xfc000001) == 0x48000001) 2150 { /* bl foo, an initializer function? */ 2151 op = read_memory_integer (pc + 4, 4, byte_order); 2152 2153 if (op == 0x4def7b82) 2154 { /* cror 0xf, 0xf, 0xf (nop) */ 2155 2156 /* Check and see if we are in main. If so, skip over this 2157 initializer function as well. */ 2158 2159 tmp = find_pc_misc_function (pc); 2160 if (tmp >= 0 2161 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 2162 return pc + 8; 2163 } 2164 } 2165 #endif /* 0 */ 2166 2167 if (pc == lim_pc && lr_reg >= 0) 2168 fdata->lr_register = lr_reg; 2169 2170 fdata->offset = -fdata->offset; 2171 return last_prologue_pc; 2172 } 2173 2174 static CORE_ADDR 2175 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 2176 { 2177 struct rs6000_framedata frame; 2178 CORE_ADDR limit_pc, func_addr, func_end_addr = 0; 2179 2180 /* See if we can determine the end of the prologue via the symbol table. 2181 If so, then return either PC, or the PC after the prologue, whichever 2182 is greater. */ 2183 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) 2184 { 2185 CORE_ADDR post_prologue_pc 2186 = skip_prologue_using_sal (gdbarch, func_addr); 2187 if (post_prologue_pc != 0) 2188 return max (pc, post_prologue_pc); 2189 } 2190 2191 /* Can't determine prologue from the symbol table, need to examine 2192 instructions. */ 2193 2194 /* Find an upper limit on the function prologue using the debug 2195 information. If the debug information could not be used to provide 2196 that bound, then use an arbitrary large number as the upper bound. */ 2197 limit_pc = skip_prologue_using_sal (gdbarch, pc); 2198 if (limit_pc == 0) 2199 limit_pc = pc + 100; /* Magic. */ 2200 2201 /* Do not allow limit_pc to be past the function end, if we know 2202 where that end is... */ 2203 if (func_end_addr && limit_pc > func_end_addr) 2204 limit_pc = func_end_addr; 2205 2206 pc = skip_prologue (gdbarch, pc, limit_pc, &frame); 2207 return pc; 2208 } 2209 2210 /* When compiling for EABI, some versions of GCC emit a call to __eabi 2211 in the prologue of main(). 2212 2213 The function below examines the code pointed at by PC and checks to 2214 see if it corresponds to a call to __eabi. If so, it returns the 2215 address of the instruction following that call. Otherwise, it simply 2216 returns PC. */ 2217 2218 static CORE_ADDR 2219 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 2220 { 2221 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2222 gdb_byte buf[4]; 2223 unsigned long op; 2224 2225 if (target_read_memory (pc, buf, 4)) 2226 return pc; 2227 op = extract_unsigned_integer (buf, 4, byte_order); 2228 2229 if ((op & BL_MASK) == BL_INSTRUCTION) 2230 { 2231 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; 2232 CORE_ADDR call_dest = pc + 4 + displ; 2233 struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); 2234 2235 /* We check for ___eabi (three leading underscores) in addition 2236 to __eabi in case the GCC option "-fleading-underscore" was 2237 used to compile the program. */ 2238 if (s.minsym != NULL 2239 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL 2240 && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0 2241 || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0)) 2242 pc += 4; 2243 } 2244 return pc; 2245 } 2246 2247 /* All the ABI's require 16 byte alignment. */ 2248 static CORE_ADDR 2249 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 2250 { 2251 return (addr & -16); 2252 } 2253 2254 /* Return whether handle_inferior_event() should proceed through code 2255 starting at PC in function NAME when stepping. 2256 2257 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 2258 handle memory references that are too distant to fit in instructions 2259 generated by the compiler. For example, if 'foo' in the following 2260 instruction: 2261 2262 lwz r9,foo(r2) 2263 2264 is greater than 32767, the linker might replace the lwz with a branch to 2265 somewhere in @FIX1 that does the load in 2 instructions and then branches 2266 back to where execution should continue. 2267 2268 GDB should silently step over @FIX code, just like AIX dbx does. 2269 Unfortunately, the linker uses the "b" instruction for the 2270 branches, meaning that the link register doesn't get set. 2271 Therefore, GDB's usual step_over_function () mechanism won't work. 2272 2273 Instead, use the gdbarch_skip_trampoline_code and 2274 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past 2275 @FIX code. */ 2276 2277 static int 2278 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, 2279 CORE_ADDR pc, const char *name) 2280 { 2281 return name && startswith (name, "@FIX"); 2282 } 2283 2284 /* Skip code that the user doesn't want to see when stepping: 2285 2286 1. Indirect function calls use a piece of trampoline code to do context 2287 switching, i.e. to set the new TOC table. Skip such code if we are on 2288 its first instruction (as when we have single-stepped to here). 2289 2290 2. Skip shared library trampoline code (which is different from 2291 indirect function call trampolines). 2292 2293 3. Skip bigtoc fixup code. 2294 2295 Result is desired PC to step until, or NULL if we are not in 2296 code that should be skipped. */ 2297 2298 static CORE_ADDR 2299 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 2300 { 2301 struct gdbarch *gdbarch = get_frame_arch (frame); 2302 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2303 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2304 unsigned int ii, op; 2305 int rel; 2306 CORE_ADDR solib_target_pc; 2307 struct bound_minimal_symbol msymbol; 2308 2309 static unsigned trampoline_code[] = 2310 { 2311 0x800b0000, /* l r0,0x0(r11) */ 2312 0x90410014, /* st r2,0x14(r1) */ 2313 0x7c0903a6, /* mtctr r0 */ 2314 0x804b0004, /* l r2,0x4(r11) */ 2315 0x816b0008, /* l r11,0x8(r11) */ 2316 0x4e800420, /* bctr */ 2317 0x4e800020, /* br */ 2318 0 2319 }; 2320 2321 /* Check for bigtoc fixup code. */ 2322 msymbol = lookup_minimal_symbol_by_pc (pc); 2323 if (msymbol.minsym 2324 && rs6000_in_solib_return_trampoline (gdbarch, pc, 2325 MSYMBOL_LINKAGE_NAME (msymbol.minsym))) 2326 { 2327 /* Double-check that the third instruction from PC is relative "b". */ 2328 op = read_memory_integer (pc + 8, 4, byte_order); 2329 if ((op & 0xfc000003) == 0x48000000) 2330 { 2331 /* Extract bits 6-29 as a signed 24-bit relative word address and 2332 add it to the containing PC. */ 2333 rel = ((int)(op << 6) >> 6); 2334 return pc + 8 + rel; 2335 } 2336 } 2337 2338 /* If pc is in a shared library trampoline, return its target. */ 2339 solib_target_pc = find_solib_trampoline_target (frame, pc); 2340 if (solib_target_pc) 2341 return solib_target_pc; 2342 2343 for (ii = 0; trampoline_code[ii]; ++ii) 2344 { 2345 op = read_memory_integer (pc + (ii * 4), 4, byte_order); 2346 if (op != trampoline_code[ii]) 2347 return 0; 2348 } 2349 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination 2350 addr. */ 2351 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); 2352 return pc; 2353 } 2354 2355 /* ISA-specific vector types. */ 2356 2357 static struct type * 2358 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) 2359 { 2360 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2361 2362 if (!tdep->ppc_builtin_type_vec64) 2363 { 2364 const struct builtin_type *bt = builtin_type (gdbarch); 2365 2366 /* The type we're building is this: */ 2367 #if 0 2368 union __gdb_builtin_type_vec64 2369 { 2370 int64_t uint64; 2371 float v2_float[2]; 2372 int32_t v2_int32[2]; 2373 int16_t v4_int16[4]; 2374 int8_t v8_int8[8]; 2375 }; 2376 #endif 2377 2378 struct type *t; 2379 2380 t = arch_composite_type (gdbarch, 2381 "__ppc_builtin_type_vec64", TYPE_CODE_UNION); 2382 append_composite_type_field (t, "uint64", bt->builtin_int64); 2383 append_composite_type_field (t, "v2_float", 2384 init_vector_type (bt->builtin_float, 2)); 2385 append_composite_type_field (t, "v2_int32", 2386 init_vector_type (bt->builtin_int32, 2)); 2387 append_composite_type_field (t, "v4_int16", 2388 init_vector_type (bt->builtin_int16, 4)); 2389 append_composite_type_field (t, "v8_int8", 2390 init_vector_type (bt->builtin_int8, 8)); 2391 2392 TYPE_VECTOR (t) = 1; 2393 TYPE_NAME (t) = "ppc_builtin_type_vec64"; 2394 tdep->ppc_builtin_type_vec64 = t; 2395 } 2396 2397 return tdep->ppc_builtin_type_vec64; 2398 } 2399 2400 /* Vector 128 type. */ 2401 2402 static struct type * 2403 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) 2404 { 2405 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2406 2407 if (!tdep->ppc_builtin_type_vec128) 2408 { 2409 const struct builtin_type *bt = builtin_type (gdbarch); 2410 2411 /* The type we're building is this 2412 2413 type = union __ppc_builtin_type_vec128 { 2414 uint128_t uint128; 2415 double v2_double[2]; 2416 float v4_float[4]; 2417 int32_t v4_int32[4]; 2418 int16_t v8_int16[8]; 2419 int8_t v16_int8[16]; 2420 } 2421 */ 2422 2423 struct type *t; 2424 2425 t = arch_composite_type (gdbarch, 2426 "__ppc_builtin_type_vec128", TYPE_CODE_UNION); 2427 append_composite_type_field (t, "uint128", bt->builtin_uint128); 2428 append_composite_type_field (t, "v2_double", 2429 init_vector_type (bt->builtin_double, 2)); 2430 append_composite_type_field (t, "v4_float", 2431 init_vector_type (bt->builtin_float, 4)); 2432 append_composite_type_field (t, "v4_int32", 2433 init_vector_type (bt->builtin_int32, 4)); 2434 append_composite_type_field (t, "v8_int16", 2435 init_vector_type (bt->builtin_int16, 8)); 2436 append_composite_type_field (t, "v16_int8", 2437 init_vector_type (bt->builtin_int8, 16)); 2438 2439 TYPE_VECTOR (t) = 1; 2440 TYPE_NAME (t) = "ppc_builtin_type_vec128"; 2441 tdep->ppc_builtin_type_vec128 = t; 2442 } 2443 2444 return tdep->ppc_builtin_type_vec128; 2445 } 2446 2447 /* Return the name of register number REGNO, or the empty string if it 2448 is an anonymous register. */ 2449 2450 static const char * 2451 rs6000_register_name (struct gdbarch *gdbarch, int regno) 2452 { 2453 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2454 2455 /* The upper half "registers" have names in the XML description, 2456 but we present only the low GPRs and the full 64-bit registers 2457 to the user. */ 2458 if (tdep->ppc_ev0_upper_regnum >= 0 2459 && tdep->ppc_ev0_upper_regnum <= regno 2460 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 2461 return ""; 2462 2463 /* Hide the upper halves of the vs0~vs31 registers. */ 2464 if (tdep->ppc_vsr0_regnum >= 0 2465 && tdep->ppc_vsr0_upper_regnum <= regno 2466 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) 2467 return ""; 2468 2469 /* Check if the SPE pseudo registers are available. */ 2470 if (IS_SPE_PSEUDOREG (tdep, regno)) 2471 { 2472 static const char *const spe_regnames[] = { 2473 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", 2474 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", 2475 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", 2476 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", 2477 }; 2478 return spe_regnames[regno - tdep->ppc_ev0_regnum]; 2479 } 2480 2481 /* Check if the decimal128 pseudo-registers are available. */ 2482 if (IS_DFP_PSEUDOREG (tdep, regno)) 2483 { 2484 static const char *const dfp128_regnames[] = { 2485 "dl0", "dl1", "dl2", "dl3", 2486 "dl4", "dl5", "dl6", "dl7", 2487 "dl8", "dl9", "dl10", "dl11", 2488 "dl12", "dl13", "dl14", "dl15" 2489 }; 2490 return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; 2491 } 2492 2493 /* Check if this is a VSX pseudo-register. */ 2494 if (IS_VSX_PSEUDOREG (tdep, regno)) 2495 { 2496 static const char *const vsx_regnames[] = { 2497 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", 2498 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", 2499 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", 2500 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", 2501 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", 2502 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", 2503 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", 2504 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", 2505 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" 2506 }; 2507 return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; 2508 } 2509 2510 /* Check if the this is a Extended FP pseudo-register. */ 2511 if (IS_EFP_PSEUDOREG (tdep, regno)) 2512 { 2513 static const char *const efpr_regnames[] = { 2514 "f32", "f33", "f34", "f35", "f36", "f37", "f38", 2515 "f39", "f40", "f41", "f42", "f43", "f44", "f45", 2516 "f46", "f47", "f48", "f49", "f50", "f51", 2517 "f52", "f53", "f54", "f55", "f56", "f57", 2518 "f58", "f59", "f60", "f61", "f62", "f63" 2519 }; 2520 return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; 2521 } 2522 2523 return tdesc_register_name (gdbarch, regno); 2524 } 2525 2526 /* Return the GDB type object for the "standard" data type of data in 2527 register N. */ 2528 2529 static struct type * 2530 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 2531 { 2532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2533 2534 /* These are the only pseudo-registers we support. */ 2535 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) 2536 || IS_DFP_PSEUDOREG (tdep, regnum) 2537 || IS_VSX_PSEUDOREG (tdep, regnum) 2538 || IS_EFP_PSEUDOREG (tdep, regnum)); 2539 2540 /* These are the e500 pseudo-registers. */ 2541 if (IS_SPE_PSEUDOREG (tdep, regnum)) 2542 return rs6000_builtin_type_vec64 (gdbarch); 2543 else if (IS_DFP_PSEUDOREG (tdep, regnum)) 2544 /* PPC decimal128 pseudo-registers. */ 2545 return builtin_type (gdbarch)->builtin_declong; 2546 else if (IS_VSX_PSEUDOREG (tdep, regnum)) 2547 /* POWER7 VSX pseudo-registers. */ 2548 return rs6000_builtin_type_vec128 (gdbarch); 2549 else 2550 /* POWER7 Extended FP pseudo-registers. */ 2551 return builtin_type (gdbarch)->builtin_double; 2552 } 2553 2554 /* Is REGNUM a member of REGGROUP? */ 2555 static int 2556 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 2557 struct reggroup *group) 2558 { 2559 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2560 2561 /* These are the only pseudo-registers we support. */ 2562 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum) 2563 || IS_DFP_PSEUDOREG (tdep, regnum) 2564 || IS_VSX_PSEUDOREG (tdep, regnum) 2565 || IS_EFP_PSEUDOREG (tdep, regnum)); 2566 2567 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */ 2568 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum)) 2569 return group == all_reggroup || group == vector_reggroup; 2570 else 2571 /* PPC decimal128 or Extended FP pseudo-registers. */ 2572 return group == all_reggroup || group == float_reggroup; 2573 } 2574 2575 /* The register format for RS/6000 floating point registers is always 2576 double, we need a conversion if the memory format is float. */ 2577 2578 static int 2579 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, 2580 struct type *type) 2581 { 2582 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2583 2584 return (tdep->ppc_fp0_regnum >= 0 2585 && regnum >= tdep->ppc_fp0_regnum 2586 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs 2587 && TYPE_CODE (type) == TYPE_CODE_FLT 2588 && TYPE_LENGTH (type) 2589 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double)); 2590 } 2591 2592 static int 2593 rs6000_register_to_value (struct frame_info *frame, 2594 int regnum, 2595 struct type *type, 2596 gdb_byte *to, 2597 int *optimizedp, int *unavailablep) 2598 { 2599 struct gdbarch *gdbarch = get_frame_arch (frame); 2600 gdb_byte from[MAX_REGISTER_SIZE]; 2601 2602 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 2603 2604 if (!get_frame_register_bytes (frame, regnum, 0, 2605 register_size (gdbarch, regnum), 2606 from, optimizedp, unavailablep)) 2607 return 0; 2608 2609 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double, 2610 to, type); 2611 *optimizedp = *unavailablep = 0; 2612 return 1; 2613 } 2614 2615 static void 2616 rs6000_value_to_register (struct frame_info *frame, 2617 int regnum, 2618 struct type *type, 2619 const gdb_byte *from) 2620 { 2621 struct gdbarch *gdbarch = get_frame_arch (frame); 2622 gdb_byte to[MAX_REGISTER_SIZE]; 2623 2624 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 2625 2626 convert_typed_floating (from, type, 2627 to, builtin_type (gdbarch)->builtin_double); 2628 put_frame_register (frame, regnum, to); 2629 } 2630 2631 /* The type of a function that moves the value of REG between CACHE 2632 or BUF --- in either direction. */ 2633 typedef enum register_status (*move_ev_register_func) (struct regcache *, 2634 int, void *); 2635 2636 /* Move SPE vector register values between a 64-bit buffer and the two 2637 32-bit raw register halves in a regcache. This function handles 2638 both splitting a 64-bit value into two 32-bit halves, and joining 2639 two halves into a whole 64-bit value, depending on the function 2640 passed as the MOVE argument. 2641 2642 EV_REG must be the number of an SPE evN vector register --- a 2643 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a 2644 64-bit buffer. 2645 2646 Call MOVE once for each 32-bit half of that register, passing 2647 REGCACHE, the number of the raw register corresponding to that 2648 half, and the address of the appropriate half of BUFFER. 2649 2650 For example, passing 'regcache_raw_read' as the MOVE function will 2651 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing 2652 'regcache_raw_supply' will supply the contents of BUFFER to the 2653 appropriate pair of raw registers in REGCACHE. 2654 2655 You may need to cast away some 'const' qualifiers when passing 2656 MOVE, since this function can't tell at compile-time which of 2657 REGCACHE or BUFFER is acting as the source of the data. If C had 2658 co-variant type qualifiers, ... */ 2659 2660 static enum register_status 2661 e500_move_ev_register (move_ev_register_func move, 2662 struct regcache *regcache, int ev_reg, void *buffer) 2663 { 2664 struct gdbarch *arch = get_regcache_arch (regcache); 2665 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 2666 int reg_index; 2667 gdb_byte *byte_buffer = (gdb_byte *) buffer; 2668 enum register_status status; 2669 2670 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); 2671 2672 reg_index = ev_reg - tdep->ppc_ev0_regnum; 2673 2674 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) 2675 { 2676 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, 2677 byte_buffer); 2678 if (status == REG_VALID) 2679 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, 2680 byte_buffer + 4); 2681 } 2682 else 2683 { 2684 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); 2685 if (status == REG_VALID) 2686 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, 2687 byte_buffer + 4); 2688 } 2689 2690 return status; 2691 } 2692 2693 static enum register_status 2694 do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer) 2695 { 2696 return regcache_raw_read (regcache, regnum, (gdb_byte *) buffer); 2697 } 2698 2699 static enum register_status 2700 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) 2701 { 2702 regcache_raw_write (regcache, regnum, (const gdb_byte *) buffer); 2703 2704 return REG_VALID; 2705 } 2706 2707 static enum register_status 2708 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2709 int reg_nr, gdb_byte *buffer) 2710 { 2711 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer); 2712 } 2713 2714 static void 2715 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2716 int reg_nr, const gdb_byte *buffer) 2717 { 2718 e500_move_ev_register (do_regcache_raw_write, regcache, 2719 reg_nr, (void *) buffer); 2720 } 2721 2722 /* Read method for DFP pseudo-registers. */ 2723 static enum register_status 2724 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2725 int reg_nr, gdb_byte *buffer) 2726 { 2727 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2728 int reg_index = reg_nr - tdep->ppc_dl0_regnum; 2729 enum register_status status; 2730 2731 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2732 { 2733 /* Read two FP registers to form a whole dl register. */ 2734 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2735 2 * reg_index, buffer); 2736 if (status == REG_VALID) 2737 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2738 2 * reg_index + 1, buffer + 8); 2739 } 2740 else 2741 { 2742 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2743 2 * reg_index + 1, buffer); 2744 if (status == REG_VALID) 2745 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2746 2 * reg_index, buffer + 8); 2747 } 2748 2749 return status; 2750 } 2751 2752 /* Write method for DFP pseudo-registers. */ 2753 static void 2754 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2755 int reg_nr, const gdb_byte *buffer) 2756 { 2757 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2758 int reg_index = reg_nr - tdep->ppc_dl0_regnum; 2759 2760 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2761 { 2762 /* Write each half of the dl register into a separate 2763 FP register. */ 2764 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2765 2 * reg_index, buffer); 2766 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2767 2 * reg_index + 1, buffer + 8); 2768 } 2769 else 2770 { 2771 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2772 2 * reg_index + 1, buffer); 2773 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2774 2 * reg_index, buffer + 8); 2775 } 2776 } 2777 2778 /* Read method for POWER7 VSX pseudo-registers. */ 2779 static enum register_status 2780 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2781 int reg_nr, gdb_byte *buffer) 2782 { 2783 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2784 int reg_index = reg_nr - tdep->ppc_vsr0_regnum; 2785 enum register_status status; 2786 2787 /* Read the portion that overlaps the VMX registers. */ 2788 if (reg_index > 31) 2789 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum + 2790 reg_index - 32, buffer); 2791 else 2792 /* Read the portion that overlaps the FPR registers. */ 2793 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2794 { 2795 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2796 reg_index, buffer); 2797 if (status == REG_VALID) 2798 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + 2799 reg_index, buffer + 8); 2800 } 2801 else 2802 { 2803 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum + 2804 reg_index, buffer + 8); 2805 if (status == REG_VALID) 2806 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum + 2807 reg_index, buffer); 2808 } 2809 2810 return status; 2811 } 2812 2813 /* Write method for POWER7 VSX pseudo-registers. */ 2814 static void 2815 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2816 int reg_nr, const gdb_byte *buffer) 2817 { 2818 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2819 int reg_index = reg_nr - tdep->ppc_vsr0_regnum; 2820 2821 /* Write the portion that overlaps the VMX registers. */ 2822 if (reg_index > 31) 2823 regcache_raw_write (regcache, tdep->ppc_vr0_regnum + 2824 reg_index - 32, buffer); 2825 else 2826 /* Write the portion that overlaps the FPR registers. */ 2827 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2828 { 2829 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2830 reg_index, buffer); 2831 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + 2832 reg_index, buffer + 8); 2833 } 2834 else 2835 { 2836 regcache_raw_write (regcache, tdep->ppc_fp0_regnum + 2837 reg_index, buffer + 8); 2838 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum + 2839 reg_index, buffer); 2840 } 2841 } 2842 2843 /* Read method for POWER7 Extended FP pseudo-registers. */ 2844 static enum register_status 2845 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2846 int reg_nr, gdb_byte *buffer) 2847 { 2848 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2849 int reg_index = reg_nr - tdep->ppc_efpr0_regnum; 2850 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; 2851 2852 /* Read the portion that overlaps the VMX register. */ 2853 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 2854 offset, register_size (gdbarch, reg_nr), 2855 buffer); 2856 } 2857 2858 /* Write method for POWER7 Extended FP pseudo-registers. */ 2859 static void 2860 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2861 int reg_nr, const gdb_byte *buffer) 2862 { 2863 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2864 int reg_index = reg_nr - tdep->ppc_efpr0_regnum; 2865 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; 2866 2867 /* Write the portion that overlaps the VMX register. */ 2868 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 2869 offset, register_size (gdbarch, reg_nr), 2870 buffer); 2871 } 2872 2873 static enum register_status 2874 rs6000_pseudo_register_read (struct gdbarch *gdbarch, 2875 struct regcache *regcache, 2876 int reg_nr, gdb_byte *buffer) 2877 { 2878 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 2879 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2880 2881 gdb_assert (regcache_arch == gdbarch); 2882 2883 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 2884 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 2885 else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 2886 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 2887 else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 2888 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 2889 else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 2890 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 2891 else 2892 internal_error (__FILE__, __LINE__, 2893 _("rs6000_pseudo_register_read: " 2894 "called on unexpected register '%s' (%d)"), 2895 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 2896 } 2897 2898 static void 2899 rs6000_pseudo_register_write (struct gdbarch *gdbarch, 2900 struct regcache *regcache, 2901 int reg_nr, const gdb_byte *buffer) 2902 { 2903 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 2904 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2905 2906 gdb_assert (regcache_arch == gdbarch); 2907 2908 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 2909 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 2910 else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 2911 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 2912 else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 2913 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 2914 else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 2915 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 2916 else 2917 internal_error (__FILE__, __LINE__, 2918 _("rs6000_pseudo_register_write: " 2919 "called on unexpected register '%s' (%d)"), 2920 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 2921 } 2922 2923 static int 2924 rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch, 2925 struct agent_expr *ax, int reg_nr) 2926 { 2927 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2928 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 2929 { 2930 int reg_index = reg_nr - tdep->ppc_ev0_regnum; 2931 ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index); 2932 ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index); 2933 } 2934 else if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 2935 { 2936 int reg_index = reg_nr - tdep->ppc_dl0_regnum; 2937 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index); 2938 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1); 2939 } 2940 else if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 2941 { 2942 int reg_index = reg_nr - tdep->ppc_vsr0_regnum; 2943 if (reg_index > 31) 2944 { 2945 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32); 2946 } 2947 else 2948 { 2949 ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index); 2950 ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index); 2951 } 2952 } 2953 else if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 2954 { 2955 int reg_index = reg_nr - tdep->ppc_efpr0_regnum; 2956 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index); 2957 } 2958 else 2959 internal_error (__FILE__, __LINE__, 2960 _("rs6000_pseudo_register_collect: " 2961 "called on unexpected register '%s' (%d)"), 2962 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 2963 return 0; 2964 } 2965 2966 2967 static void 2968 rs6000_gen_return_address (struct gdbarch *gdbarch, 2969 struct agent_expr *ax, struct axs_value *value, 2970 CORE_ADDR scope) 2971 { 2972 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2973 value->type = register_type (gdbarch, tdep->ppc_lr_regnum); 2974 value->kind = axs_lvalue_register; 2975 value->u.reg = tdep->ppc_lr_regnum; 2976 } 2977 2978 2979 /* Convert a DBX STABS register number to a GDB register number. */ 2980 static int 2981 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) 2982 { 2983 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2984 2985 if (0 <= num && num <= 31) 2986 return tdep->ppc_gp0_regnum + num; 2987 else if (32 <= num && num <= 63) 2988 /* FIXME: jimb/2004-05-05: What should we do when the debug info 2989 specifies registers the architecture doesn't have? Our 2990 callers don't check the value we return. */ 2991 return tdep->ppc_fp0_regnum + (num - 32); 2992 else if (77 <= num && num <= 108) 2993 return tdep->ppc_vr0_regnum + (num - 77); 2994 else if (1200 <= num && num < 1200 + 32) 2995 return tdep->ppc_ev0_upper_regnum + (num - 1200); 2996 else 2997 switch (num) 2998 { 2999 case 64: 3000 return tdep->ppc_mq_regnum; 3001 case 65: 3002 return tdep->ppc_lr_regnum; 3003 case 66: 3004 return tdep->ppc_ctr_regnum; 3005 case 76: 3006 return tdep->ppc_xer_regnum; 3007 case 109: 3008 return tdep->ppc_vrsave_regnum; 3009 case 110: 3010 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 3011 case 111: 3012 return tdep->ppc_acc_regnum; 3013 case 112: 3014 return tdep->ppc_spefscr_regnum; 3015 default: 3016 return num; 3017 } 3018 } 3019 3020 3021 /* Convert a Dwarf 2 register number to a GDB register number. */ 3022 static int 3023 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) 3024 { 3025 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3026 3027 if (0 <= num && num <= 31) 3028 return tdep->ppc_gp0_regnum + num; 3029 else if (32 <= num && num <= 63) 3030 /* FIXME: jimb/2004-05-05: What should we do when the debug info 3031 specifies registers the architecture doesn't have? Our 3032 callers don't check the value we return. */ 3033 return tdep->ppc_fp0_regnum + (num - 32); 3034 else if (1124 <= num && num < 1124 + 32) 3035 return tdep->ppc_vr0_regnum + (num - 1124); 3036 else if (1200 <= num && num < 1200 + 32) 3037 return tdep->ppc_ev0_upper_regnum + (num - 1200); 3038 else 3039 switch (num) 3040 { 3041 case 64: 3042 return tdep->ppc_cr_regnum; 3043 case 67: 3044 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 3045 case 99: 3046 return tdep->ppc_acc_regnum; 3047 case 100: 3048 return tdep->ppc_mq_regnum; 3049 case 101: 3050 return tdep->ppc_xer_regnum; 3051 case 108: 3052 return tdep->ppc_lr_regnum; 3053 case 109: 3054 return tdep->ppc_ctr_regnum; 3055 case 356: 3056 return tdep->ppc_vrsave_regnum; 3057 case 612: 3058 return tdep->ppc_spefscr_regnum; 3059 default: 3060 return num; 3061 } 3062 } 3063 3064 /* Translate a .eh_frame register to DWARF register, or adjust a 3065 .debug_frame register. */ 3066 3067 static int 3068 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) 3069 { 3070 /* GCC releases before 3.4 use GCC internal register numbering in 3071 .debug_frame (and .debug_info, et cetera). The numbering is 3072 different from the standard SysV numbering for everything except 3073 for GPRs and FPRs. We can not detect this problem in most cases 3074 - to get accurate debug info for variables living in lr, ctr, v0, 3075 et cetera, use a newer version of GCC. But we must detect 3076 one important case - lr is in column 65 in .debug_frame output, 3077 instead of 108. 3078 3079 GCC 3.4, and the "hammer" branch, have a related problem. They 3080 record lr register saves in .debug_frame as 108, but still record 3081 the return column as 65. We fix that up too. 3082 3083 We can do this because 65 is assigned to fpsr, and GCC never 3084 generates debug info referring to it. To add support for 3085 handwritten debug info that restores fpsr, we would need to add a 3086 producer version check to this. */ 3087 if (!eh_frame_p) 3088 { 3089 if (num == 65) 3090 return 108; 3091 else 3092 return num; 3093 } 3094 3095 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC 3096 internal register numbering; translate that to the standard DWARF2 3097 register numbering. */ 3098 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ 3099 return num; 3100 else if (68 <= num && num <= 75) /* cr0-cr8 */ 3101 return num - 68 + 86; 3102 else if (77 <= num && num <= 108) /* vr0-vr31 */ 3103 return num - 77 + 1124; 3104 else 3105 switch (num) 3106 { 3107 case 64: /* mq */ 3108 return 100; 3109 case 65: /* lr */ 3110 return 108; 3111 case 66: /* ctr */ 3112 return 109; 3113 case 76: /* xer */ 3114 return 101; 3115 case 109: /* vrsave */ 3116 return 356; 3117 case 110: /* vscr */ 3118 return 67; 3119 case 111: /* spe_acc */ 3120 return 99; 3121 case 112: /* spefscr */ 3122 return 612; 3123 default: 3124 return num; 3125 } 3126 } 3127 3128 3129 /* Handling the various POWER/PowerPC variants. */ 3130 3131 /* Information about a particular processor variant. */ 3132 3133 struct variant 3134 { 3135 /* Name of this variant. */ 3136 char *name; 3137 3138 /* English description of the variant. */ 3139 char *description; 3140 3141 /* bfd_arch_info.arch corresponding to variant. */ 3142 enum bfd_architecture arch; 3143 3144 /* bfd_arch_info.mach corresponding to variant. */ 3145 unsigned long mach; 3146 3147 /* Target description for this variant. */ 3148 struct target_desc **tdesc; 3149 }; 3150 3151 static struct variant variants[] = 3152 { 3153 {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 3154 bfd_mach_ppc, &tdesc_powerpc_altivec32}, 3155 {"power", "POWER user-level", bfd_arch_rs6000, 3156 bfd_mach_rs6k, &tdesc_rs6000}, 3157 {"403", "IBM PowerPC 403", bfd_arch_powerpc, 3158 bfd_mach_ppc_403, &tdesc_powerpc_403}, 3159 {"405", "IBM PowerPC 405", bfd_arch_powerpc, 3160 bfd_mach_ppc_405, &tdesc_powerpc_405}, 3161 {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 3162 bfd_mach_ppc_601, &tdesc_powerpc_601}, 3163 {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 3164 bfd_mach_ppc_602, &tdesc_powerpc_602}, 3165 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 3166 bfd_mach_ppc_603, &tdesc_powerpc_603}, 3167 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 3168 604, &tdesc_powerpc_604}, 3169 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 3170 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, 3171 {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 3172 bfd_mach_ppc_505, &tdesc_powerpc_505}, 3173 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 3174 bfd_mach_ppc_860, &tdesc_powerpc_860}, 3175 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 3176 bfd_mach_ppc_750, &tdesc_powerpc_750}, 3177 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 3178 bfd_mach_ppc_7400, &tdesc_powerpc_7400}, 3179 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 3180 bfd_mach_ppc_e500, &tdesc_powerpc_e500}, 3181 3182 /* 64-bit */ 3183 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 3184 bfd_mach_ppc64, &tdesc_powerpc_altivec64}, 3185 {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 3186 bfd_mach_ppc_620, &tdesc_powerpc_64}, 3187 {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 3188 bfd_mach_ppc_630, &tdesc_powerpc_64}, 3189 {"a35", "PowerPC A35", bfd_arch_powerpc, 3190 bfd_mach_ppc_a35, &tdesc_powerpc_64}, 3191 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 3192 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, 3193 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 3194 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, 3195 3196 /* FIXME: I haven't checked the register sets of the following. */ 3197 {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 3198 bfd_mach_rs6k_rs1, &tdesc_rs6000}, 3199 {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 3200 bfd_mach_rs6k_rsc, &tdesc_rs6000}, 3201 {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 3202 bfd_mach_rs6k_rs2, &tdesc_rs6000}, 3203 3204 {0, 0, (enum bfd_architecture) 0, 0, 0} 3205 }; 3206 3207 /* Return the variant corresponding to architecture ARCH and machine number 3208 MACH. If no such variant exists, return null. */ 3209 3210 static const struct variant * 3211 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 3212 { 3213 const struct variant *v; 3214 3215 for (v = variants; v->name; v++) 3216 if (arch == v->arch && mach == v->mach) 3217 return v; 3218 3219 return NULL; 3220 } 3221 3222 static int 3223 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) 3224 { 3225 if (info->endian == BFD_ENDIAN_BIG) 3226 return print_insn_big_powerpc (memaddr, info); 3227 else 3228 return print_insn_little_powerpc (memaddr, info); 3229 } 3230 3231 static CORE_ADDR 3232 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 3233 { 3234 return frame_unwind_register_unsigned (next_frame, 3235 gdbarch_pc_regnum (gdbarch)); 3236 } 3237 3238 static struct frame_id 3239 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 3240 { 3241 return frame_id_build (get_frame_register_unsigned 3242 (this_frame, gdbarch_sp_regnum (gdbarch)), 3243 get_frame_pc (this_frame)); 3244 } 3245 3246 struct rs6000_frame_cache 3247 { 3248 CORE_ADDR base; 3249 CORE_ADDR initial_sp; 3250 struct trad_frame_saved_reg *saved_regs; 3251 3252 /* Set BASE_P to true if this frame cache is properly initialized. 3253 Otherwise set to false because some registers or memory cannot 3254 collected. */ 3255 int base_p; 3256 /* Cache PC for building unavailable frame. */ 3257 CORE_ADDR pc; 3258 }; 3259 3260 static struct rs6000_frame_cache * 3261 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache) 3262 { 3263 struct rs6000_frame_cache *cache; 3264 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3265 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3266 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3267 struct rs6000_framedata fdata; 3268 int wordsize = tdep->wordsize; 3269 CORE_ADDR func = 0, pc = 0; 3270 3271 if ((*this_cache) != NULL) 3272 return (struct rs6000_frame_cache *) (*this_cache); 3273 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 3274 (*this_cache) = cache; 3275 cache->pc = 0; 3276 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3277 3278 TRY 3279 { 3280 func = get_frame_func (this_frame); 3281 cache->pc = func; 3282 pc = get_frame_pc (this_frame); 3283 skip_prologue (gdbarch, func, pc, &fdata); 3284 3285 /* Figure out the parent's stack pointer. */ 3286 3287 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 3288 address of the current frame. Things might be easier if the 3289 ->frame pointed to the outer-most address of the frame. In 3290 the mean time, the address of the prev frame is used as the 3291 base address of this frame. */ 3292 cache->base = get_frame_register_unsigned 3293 (this_frame, gdbarch_sp_regnum (gdbarch)); 3294 } 3295 CATCH (ex, RETURN_MASK_ERROR) 3296 { 3297 if (ex.error != NOT_AVAILABLE_ERROR) 3298 throw_exception (ex); 3299 return (struct rs6000_frame_cache *) (*this_cache); 3300 } 3301 END_CATCH 3302 3303 /* If the function appears to be frameless, check a couple of likely 3304 indicators that we have simply failed to find the frame setup. 3305 Two common cases of this are missing symbols (i.e. 3306 get_frame_func returns the wrong address or 0), and assembly 3307 stubs which have a fast exit path but set up a frame on the slow 3308 path. 3309 3310 If the LR appears to return to this function, then presume that 3311 we have an ABI compliant frame that we failed to find. */ 3312 if (fdata.frameless && fdata.lr_offset == 0) 3313 { 3314 CORE_ADDR saved_lr; 3315 int make_frame = 0; 3316 3317 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); 3318 if (func == 0 && saved_lr == pc) 3319 make_frame = 1; 3320 else if (func != 0) 3321 { 3322 CORE_ADDR saved_func = get_pc_function_start (saved_lr); 3323 if (func == saved_func) 3324 make_frame = 1; 3325 } 3326 3327 if (make_frame) 3328 { 3329 fdata.frameless = 0; 3330 fdata.lr_offset = tdep->lr_frame_offset; 3331 } 3332 } 3333 3334 if (!fdata.frameless) 3335 { 3336 /* Frameless really means stackless. */ 3337 ULONGEST backchain; 3338 3339 if (safe_read_memory_unsigned_integer (cache->base, wordsize, 3340 byte_order, &backchain)) 3341 cache->base = (CORE_ADDR) backchain; 3342 } 3343 3344 trad_frame_set_value (cache->saved_regs, 3345 gdbarch_sp_regnum (gdbarch), cache->base); 3346 3347 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. 3348 All fpr's from saved_fpr to fp31 are saved. */ 3349 3350 if (fdata.saved_fpr >= 0) 3351 { 3352 int i; 3353 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; 3354 3355 /* If skip_prologue says floating-point registers were saved, 3356 but the current architecture has no floating-point registers, 3357 then that's strange. But we have no indices to even record 3358 the addresses under, so we just ignore it. */ 3359 if (ppc_floating_point_unit_p (gdbarch)) 3360 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) 3361 { 3362 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; 3363 fpr_addr += 8; 3364 } 3365 } 3366 3367 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. 3368 All gpr's from saved_gpr to gpr31 are saved (except during the 3369 prologue). */ 3370 3371 if (fdata.saved_gpr >= 0) 3372 { 3373 int i; 3374 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; 3375 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) 3376 { 3377 if (fdata.gpr_mask & (1U << i)) 3378 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; 3379 gpr_addr += wordsize; 3380 } 3381 } 3382 3383 /* if != -1, fdata.saved_vr is the smallest number of saved_vr. 3384 All vr's from saved_vr to vr31 are saved. */ 3385 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 3386 { 3387 if (fdata.saved_vr >= 0) 3388 { 3389 int i; 3390 CORE_ADDR vr_addr = cache->base + fdata.vr_offset; 3391 for (i = fdata.saved_vr; i < 32; i++) 3392 { 3393 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; 3394 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); 3395 } 3396 } 3397 } 3398 3399 /* if != -1, fdata.saved_ev is the smallest number of saved_ev. 3400 All vr's from saved_ev to ev31 are saved. ????? */ 3401 if (tdep->ppc_ev0_regnum != -1) 3402 { 3403 if (fdata.saved_ev >= 0) 3404 { 3405 int i; 3406 CORE_ADDR ev_addr = cache->base + fdata.ev_offset; 3407 CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); 3408 3409 for (i = fdata.saved_ev; i < ppc_num_gprs; i++) 3410 { 3411 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; 3412 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off; 3413 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); 3414 } 3415 } 3416 } 3417 3418 /* If != 0, fdata.cr_offset is the offset from the frame that 3419 holds the CR. */ 3420 if (fdata.cr_offset != 0) 3421 cache->saved_regs[tdep->ppc_cr_regnum].addr 3422 = cache->base + fdata.cr_offset; 3423 3424 /* If != 0, fdata.lr_offset is the offset from the frame that 3425 holds the LR. */ 3426 if (fdata.lr_offset != 0) 3427 cache->saved_regs[tdep->ppc_lr_regnum].addr 3428 = cache->base + fdata.lr_offset; 3429 else if (fdata.lr_register != -1) 3430 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register; 3431 /* The PC is found in the link register. */ 3432 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = 3433 cache->saved_regs[tdep->ppc_lr_regnum]; 3434 3435 /* If != 0, fdata.vrsave_offset is the offset from the frame that 3436 holds the VRSAVE. */ 3437 if (fdata.vrsave_offset != 0) 3438 cache->saved_regs[tdep->ppc_vrsave_regnum].addr 3439 = cache->base + fdata.vrsave_offset; 3440 3441 if (fdata.alloca_reg < 0) 3442 /* If no alloca register used, then fi->frame is the value of the 3443 %sp for this frame, and it is good enough. */ 3444 cache->initial_sp 3445 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 3446 else 3447 cache->initial_sp 3448 = get_frame_register_unsigned (this_frame, fdata.alloca_reg); 3449 3450 cache->base_p = 1; 3451 return cache; 3452 } 3453 3454 static void 3455 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache, 3456 struct frame_id *this_id) 3457 { 3458 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3459 this_cache); 3460 3461 if (!info->base_p) 3462 { 3463 (*this_id) = frame_id_build_unavailable_stack (info->pc); 3464 return; 3465 } 3466 3467 /* This marks the outermost frame. */ 3468 if (info->base == 0) 3469 return; 3470 3471 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3472 } 3473 3474 static struct value * 3475 rs6000_frame_prev_register (struct frame_info *this_frame, 3476 void **this_cache, int regnum) 3477 { 3478 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3479 this_cache); 3480 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3481 } 3482 3483 static const struct frame_unwind rs6000_frame_unwind = 3484 { 3485 NORMAL_FRAME, 3486 default_frame_unwind_stop_reason, 3487 rs6000_frame_this_id, 3488 rs6000_frame_prev_register, 3489 NULL, 3490 default_frame_sniffer 3491 }; 3492 3493 /* Allocate and initialize a frame cache for an epilogue frame. 3494 SP is restored and prev-PC is stored in LR. */ 3495 3496 static struct rs6000_frame_cache * 3497 rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache) 3498 { 3499 struct rs6000_frame_cache *cache; 3500 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3502 3503 if (*this_cache) 3504 return (struct rs6000_frame_cache *) *this_cache; 3505 3506 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 3507 (*this_cache) = cache; 3508 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3509 3510 TRY 3511 { 3512 /* At this point the stack looks as if we just entered the 3513 function, and the return address is stored in LR. */ 3514 CORE_ADDR sp, lr; 3515 3516 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 3517 lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); 3518 3519 cache->base = sp; 3520 cache->initial_sp = sp; 3521 3522 trad_frame_set_value (cache->saved_regs, 3523 gdbarch_pc_regnum (gdbarch), lr); 3524 } 3525 CATCH (ex, RETURN_MASK_ERROR) 3526 { 3527 if (ex.error != NOT_AVAILABLE_ERROR) 3528 throw_exception (ex); 3529 } 3530 END_CATCH 3531 3532 return cache; 3533 } 3534 3535 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h. 3536 Return the frame ID of an epilogue frame. */ 3537 3538 static void 3539 rs6000_epilogue_frame_this_id (struct frame_info *this_frame, 3540 void **this_cache, struct frame_id *this_id) 3541 { 3542 CORE_ADDR pc; 3543 struct rs6000_frame_cache *info = 3544 rs6000_epilogue_frame_cache (this_frame, this_cache); 3545 3546 pc = get_frame_func (this_frame); 3547 if (info->base == 0) 3548 (*this_id) = frame_id_build_unavailable_stack (pc); 3549 else 3550 (*this_id) = frame_id_build (info->base, pc); 3551 } 3552 3553 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h. 3554 Return the register value of REGNUM in previous frame. */ 3555 3556 static struct value * 3557 rs6000_epilogue_frame_prev_register (struct frame_info *this_frame, 3558 void **this_cache, int regnum) 3559 { 3560 struct rs6000_frame_cache *info = 3561 rs6000_epilogue_frame_cache (this_frame, this_cache); 3562 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3563 } 3564 3565 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h. 3566 Check whether this an epilogue frame. */ 3567 3568 static int 3569 rs6000_epilogue_frame_sniffer (const struct frame_unwind *self, 3570 struct frame_info *this_frame, 3571 void **this_prologue_cache) 3572 { 3573 if (frame_relative_level (this_frame) == 0) 3574 return rs6000_in_function_epilogue_frame_p (this_frame, 3575 get_frame_arch (this_frame), 3576 get_frame_pc (this_frame)); 3577 else 3578 return 0; 3579 } 3580 3581 /* Frame unwinder for epilogue frame. This is required for reverse step-over 3582 a function without debug information. */ 3583 3584 static const struct frame_unwind rs6000_epilogue_frame_unwind = 3585 { 3586 NORMAL_FRAME, 3587 default_frame_unwind_stop_reason, 3588 rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register, 3589 NULL, 3590 rs6000_epilogue_frame_sniffer 3591 }; 3592 3593 3594 static CORE_ADDR 3595 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache) 3596 { 3597 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3598 this_cache); 3599 return info->initial_sp; 3600 } 3601 3602 static const struct frame_base rs6000_frame_base = { 3603 &rs6000_frame_unwind, 3604 rs6000_frame_base_address, 3605 rs6000_frame_base_address, 3606 rs6000_frame_base_address 3607 }; 3608 3609 static const struct frame_base * 3610 rs6000_frame_base_sniffer (struct frame_info *this_frame) 3611 { 3612 return &rs6000_frame_base; 3613 } 3614 3615 /* DWARF-2 frame support. Used to handle the detection of 3616 clobbered registers during function calls. */ 3617 3618 static void 3619 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 3620 struct dwarf2_frame_state_reg *reg, 3621 struct frame_info *this_frame) 3622 { 3623 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3624 3625 /* PPC32 and PPC64 ABI's are the same regarding volatile and 3626 non-volatile registers. We will use the same code for both. */ 3627 3628 /* Call-saved GP registers. */ 3629 if ((regnum >= tdep->ppc_gp0_regnum + 14 3630 && regnum <= tdep->ppc_gp0_regnum + 31) 3631 || (regnum == tdep->ppc_gp0_regnum + 1)) 3632 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3633 3634 /* Call-clobbered GP registers. */ 3635 if ((regnum >= tdep->ppc_gp0_regnum + 3 3636 && regnum <= tdep->ppc_gp0_regnum + 12) 3637 || (regnum == tdep->ppc_gp0_regnum)) 3638 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3639 3640 /* Deal with FP registers, if supported. */ 3641 if (tdep->ppc_fp0_regnum >= 0) 3642 { 3643 /* Call-saved FP registers. */ 3644 if ((regnum >= tdep->ppc_fp0_regnum + 14 3645 && regnum <= tdep->ppc_fp0_regnum + 31)) 3646 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3647 3648 /* Call-clobbered FP registers. */ 3649 if ((regnum >= tdep->ppc_fp0_regnum 3650 && regnum <= tdep->ppc_fp0_regnum + 13)) 3651 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3652 } 3653 3654 /* Deal with ALTIVEC registers, if supported. */ 3655 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) 3656 { 3657 /* Call-saved Altivec registers. */ 3658 if ((regnum >= tdep->ppc_vr0_regnum + 20 3659 && regnum <= tdep->ppc_vr0_regnum + 31) 3660 || regnum == tdep->ppc_vrsave_regnum) 3661 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3662 3663 /* Call-clobbered Altivec registers. */ 3664 if ((regnum >= tdep->ppc_vr0_regnum 3665 && regnum <= tdep->ppc_vr0_regnum + 19)) 3666 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3667 } 3668 3669 /* Handle PC register and Stack Pointer correctly. */ 3670 if (regnum == gdbarch_pc_regnum (gdbarch)) 3671 reg->how = DWARF2_FRAME_REG_RA; 3672 else if (regnum == gdbarch_sp_regnum (gdbarch)) 3673 reg->how = DWARF2_FRAME_REG_CFA; 3674 } 3675 3676 3677 /* Return true if a .gnu_attributes section exists in BFD and it 3678 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo 3679 section exists in BFD and it indicates that SPE extensions are in 3680 use. Check the .gnu.attributes section first, as the binary might be 3681 compiled for SPE, but not actually using SPE instructions. */ 3682 3683 static int 3684 bfd_uses_spe_extensions (bfd *abfd) 3685 { 3686 asection *sect; 3687 gdb_byte *contents = NULL; 3688 bfd_size_type size; 3689 gdb_byte *ptr; 3690 int success = 0; 3691 int vector_abi; 3692 3693 if (!abfd) 3694 return 0; 3695 3696 #ifdef HAVE_ELF 3697 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user 3698 could be using the SPE vector abi without actually using any spe 3699 bits whatsoever. But it's close enough for now. */ 3700 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, 3701 Tag_GNU_Power_ABI_Vector); 3702 if (vector_abi == 3) 3703 return 1; 3704 #endif 3705 3706 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); 3707 if (!sect) 3708 return 0; 3709 3710 size = bfd_get_section_size (sect); 3711 contents = (gdb_byte *) xmalloc (size); 3712 if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) 3713 { 3714 xfree (contents); 3715 return 0; 3716 } 3717 3718 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: 3719 3720 struct { 3721 uint32 name_len; 3722 uint32 data_len; 3723 uint32 type; 3724 char name[name_len rounded up to 4-byte alignment]; 3725 char data[data_len]; 3726 }; 3727 3728 Technically, there's only supposed to be one such structure in a 3729 given apuinfo section, but the linker is not always vigilant about 3730 merging apuinfo sections from input files. Just go ahead and parse 3731 them all, exiting early when we discover the binary uses SPE 3732 insns. 3733 3734 It's not specified in what endianness the information in this 3735 section is stored. Assume that it's the endianness of the BFD. */ 3736 ptr = contents; 3737 while (1) 3738 { 3739 unsigned int name_len; 3740 unsigned int data_len; 3741 unsigned int type; 3742 3743 /* If we can't read the first three fields, we're done. */ 3744 if (size < 12) 3745 break; 3746 3747 name_len = bfd_get_32 (abfd, ptr); 3748 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ 3749 data_len = bfd_get_32 (abfd, ptr + 4); 3750 type = bfd_get_32 (abfd, ptr + 8); 3751 ptr += 12; 3752 3753 /* The name must be "APUinfo\0". */ 3754 if (name_len != 8 3755 && strcmp ((const char *) ptr, "APUinfo") != 0) 3756 break; 3757 ptr += name_len; 3758 3759 /* The type must be 2. */ 3760 if (type != 2) 3761 break; 3762 3763 /* The data is stored as a series of uint32. The upper half of 3764 each uint32 indicates the particular APU used and the lower 3765 half indicates the revision of that APU. We just care about 3766 the upper half. */ 3767 3768 /* Not 4-byte quantities. */ 3769 if (data_len & 3U) 3770 break; 3771 3772 while (data_len) 3773 { 3774 unsigned int apuinfo = bfd_get_32 (abfd, ptr); 3775 unsigned int apu = apuinfo >> 16; 3776 ptr += 4; 3777 data_len -= 4; 3778 3779 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept 3780 either. */ 3781 if (apu == 0x100 || apu == 0x101) 3782 { 3783 success = 1; 3784 data_len = 0; 3785 } 3786 } 3787 3788 if (success) 3789 break; 3790 } 3791 3792 xfree (contents); 3793 return success; 3794 } 3795 3796 /* These are macros for parsing instruction fields (I.1.6.28) */ 3797 3798 #define PPC_FIELD(value, from, len) \ 3799 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) 3800 #define PPC_SEXT(v, bs) \ 3801 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ 3802 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ 3803 - ((CORE_ADDR) 1 << ((bs) - 1))) 3804 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) 3805 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10) 3806 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5) 3807 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5) 3808 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5) 3809 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5) 3810 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5) 3811 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5) 3812 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5) 3813 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \ 3814 | (PPC_FIELD (insn, 16, 5) << 5)) 3815 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) 3816 #define PPC_T(insn) PPC_FIELD (insn, 6, 5) 3817 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16) 3818 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) 3819 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0) 3820 #define PPC_OE(insn) PPC_BIT (insn, 21) 3821 #define PPC_RC(insn) PPC_BIT (insn, 31) 3822 #define PPC_Rc(insn) PPC_BIT (insn, 21) 3823 #define PPC_LK(insn) PPC_BIT (insn, 31) 3824 #define PPC_TX(insn) PPC_BIT (insn, 31) 3825 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7) 3826 3827 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn)) 3828 #define PPC_XER_NB(xer) (xer & 0x7f) 3829 3830 /* Record Vector-Scalar Registers. 3831 For VSR less than 32, it's represented by an FPR and an VSR-upper register. 3832 Otherwise, it's just a VR register. Record them accordingly. */ 3833 3834 static int 3835 ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr) 3836 { 3837 if (vsr < 0 || vsr >= 64) 3838 return -1; 3839 3840 if (vsr >= 32) 3841 { 3842 if (tdep->ppc_vr0_regnum >= 0) 3843 record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32); 3844 } 3845 else 3846 { 3847 if (tdep->ppc_fp0_regnum >= 0) 3848 record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr); 3849 if (tdep->ppc_vsr0_upper_regnum >= 0) 3850 record_full_arch_list_add_reg (regcache, 3851 tdep->ppc_vsr0_upper_regnum + vsr); 3852 } 3853 3854 return 0; 3855 } 3856 3857 /* Parse and record instructions primary opcode-4 at ADDR. 3858 Return 0 if successful. */ 3859 3860 static int 3861 ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache, 3862 CORE_ADDR addr, uint32_t insn) 3863 { 3864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3865 int ext = PPC_FIELD (insn, 21, 11); 3866 3867 switch (ext & 0x3f) 3868 { 3869 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */ 3870 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ 3871 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */ 3872 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */ 3873 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 3874 /* FALL-THROUGH */ 3875 case 42: /* Vector Select */ 3876 case 43: /* Vector Permute */ 3877 case 44: /* Vector Shift Left Double by Octet Immediate */ 3878 case 45: /* Vector Permute and Exclusive-OR */ 3879 case 60: /* Vector Add Extended Unsigned Quadword Modulo */ 3880 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */ 3881 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */ 3882 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */ 3883 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */ 3884 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */ 3885 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */ 3886 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */ 3887 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */ 3888 case 46: /* Vector Multiply-Add Single-Precision */ 3889 case 47: /* Vector Negative Multiply-Subtract Single-Precision */ 3890 record_full_arch_list_add_reg (regcache, 3891 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 3892 return 0; 3893 } 3894 3895 switch ((ext & 0x1ff)) 3896 { 3897 /* 5.16 Decimal Integer Arithmetic Instructions */ 3898 case 1: /* Decimal Add Modulo */ 3899 case 65: /* Decimal Subtract Modulo */ 3900 3901 /* Bit-21 should be set. */ 3902 if (!PPC_BIT (insn, 21)) 3903 break; 3904 3905 record_full_arch_list_add_reg (regcache, 3906 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 3907 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 3908 return 0; 3909 } 3910 3911 /* Bit-21 is used for RC */ 3912 switch (ext & 0x3ff) 3913 { 3914 case 6: /* Vector Compare Equal To Unsigned Byte */ 3915 case 70: /* Vector Compare Equal To Unsigned Halfword */ 3916 case 134: /* Vector Compare Equal To Unsigned Word */ 3917 case 199: /* Vector Compare Equal To Unsigned Doubleword */ 3918 case 774: /* Vector Compare Greater Than Signed Byte */ 3919 case 838: /* Vector Compare Greater Than Signed Halfword */ 3920 case 902: /* Vector Compare Greater Than Signed Word */ 3921 case 967: /* Vector Compare Greater Than Signed Doubleword */ 3922 case 518: /* Vector Compare Greater Than Unsigned Byte */ 3923 case 646: /* Vector Compare Greater Than Unsigned Word */ 3924 case 582: /* Vector Compare Greater Than Unsigned Halfword */ 3925 case 711: /* Vector Compare Greater Than Unsigned Doubleword */ 3926 case 966: /* Vector Compare Bounds Single-Precision */ 3927 case 198: /* Vector Compare Equal To Single-Precision */ 3928 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */ 3929 case 710: /* Vector Compare Greater Than Single-Precision */ 3930 if (PPC_Rc (insn)) 3931 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 3932 record_full_arch_list_add_reg (regcache, 3933 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 3934 return 0; 3935 } 3936 3937 switch (ext) 3938 { 3939 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */ 3940 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */ 3941 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */ 3942 case 334: /* Vector Pack Signed Word Unsigned Saturate */ 3943 case 398: /* Vector Pack Signed Halfword Signed Saturate */ 3944 case 462: /* Vector Pack Signed Word Signed Saturate */ 3945 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */ 3946 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */ 3947 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */ 3948 case 512: /* Vector Add Unsigned Byte Saturate */ 3949 case 576: /* Vector Add Unsigned Halfword Saturate */ 3950 case 640: /* Vector Add Unsigned Word Saturate */ 3951 case 768: /* Vector Add Signed Byte Saturate */ 3952 case 832: /* Vector Add Signed Halfword Saturate */ 3953 case 896: /* Vector Add Signed Word Saturate */ 3954 case 1536: /* Vector Subtract Unsigned Byte Saturate */ 3955 case 1600: /* Vector Subtract Unsigned Halfword Saturate */ 3956 case 1664: /* Vector Subtract Unsigned Word Saturate */ 3957 case 1792: /* Vector Subtract Signed Byte Saturate */ 3958 case 1856: /* Vector Subtract Signed Halfword Saturate */ 3959 case 1920: /* Vector Subtract Signed Word Saturate */ 3960 3961 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */ 3962 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */ 3963 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */ 3964 case 1672: /* Vector Sum across Half Signed Word Saturate */ 3965 case 1928: /* Vector Sum across Signed Word Saturate */ 3966 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */ 3967 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */ 3968 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 3969 /* FALL-THROUGH */ 3970 case 12: /* Vector Merge High Byte */ 3971 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */ 3972 case 76: /* Vector Merge High Halfword */ 3973 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */ 3974 case 140: /* Vector Merge High Word */ 3975 case 268: /* Vector Merge Low Byte */ 3976 case 332: /* Vector Merge Low Halfword */ 3977 case 396: /* Vector Merge Low Word */ 3978 case 526: /* Vector Unpack High Signed Byte */ 3979 case 590: /* Vector Unpack High Signed Halfword */ 3980 case 654: /* Vector Unpack Low Signed Byte */ 3981 case 718: /* Vector Unpack Low Signed Halfword */ 3982 case 782: /* Vector Pack Pixel */ 3983 case 846: /* Vector Unpack High Pixel */ 3984 case 974: /* Vector Unpack Low Pixel */ 3985 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */ 3986 case 1614: /* Vector Unpack High Signed Word */ 3987 case 1676: /* Vector Merge Odd Word */ 3988 case 1742: /* Vector Unpack Low Signed Word */ 3989 case 1932: /* Vector Merge Even Word */ 3990 case 524: /* Vector Splat Byte */ 3991 case 588: /* Vector Splat Halfword */ 3992 case 652: /* Vector Splat Word */ 3993 case 780: /* Vector Splat Immediate Signed Byte */ 3994 case 844: /* Vector Splat Immediate Signed Halfword */ 3995 case 908: /* Vector Splat Immediate Signed Word */ 3996 case 452: /* Vector Shift Left */ 3997 case 708: /* Vector Shift Right */ 3998 case 1036: /* Vector Shift Left by Octet */ 3999 case 1100: /* Vector Shift Right by Octet */ 4000 case 0: /* Vector Add Unsigned Byte Modulo */ 4001 case 64: /* Vector Add Unsigned Halfword Modulo */ 4002 case 128: /* Vector Add Unsigned Word Modulo */ 4003 case 192: /* Vector Add Unsigned Doubleword Modulo */ 4004 case 256: /* Vector Add Unsigned Quadword Modulo */ 4005 case 320: /* Vector Add & write Carry Unsigned Quadword */ 4006 case 384: /* Vector Add and Write Carry-Out Unsigned Word */ 4007 case 8: /* Vector Multiply Odd Unsigned Byte */ 4008 case 72: /* Vector Multiply Odd Unsigned Halfword */ 4009 case 136: /* Vector Multiply Odd Unsigned Word */ 4010 case 264: /* Vector Multiply Odd Signed Byte */ 4011 case 328: /* Vector Multiply Odd Signed Halfword */ 4012 case 392: /* Vector Multiply Odd Signed Word */ 4013 case 520: /* Vector Multiply Even Unsigned Byte */ 4014 case 584: /* Vector Multiply Even Unsigned Halfword */ 4015 case 648: /* Vector Multiply Even Unsigned Word */ 4016 case 776: /* Vector Multiply Even Signed Byte */ 4017 case 840: /* Vector Multiply Even Signed Halfword */ 4018 case 904: /* Vector Multiply Even Signed Word */ 4019 case 137: /* Vector Multiply Unsigned Word Modulo */ 4020 case 1024: /* Vector Subtract Unsigned Byte Modulo */ 4021 case 1088: /* Vector Subtract Unsigned Halfword Modulo */ 4022 case 1152: /* Vector Subtract Unsigned Word Modulo */ 4023 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */ 4024 case 1280: /* Vector Subtract Unsigned Quadword Modulo */ 4025 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */ 4026 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */ 4027 case 1282: /* Vector Average Signed Byte */ 4028 case 1346: /* Vector Average Signed Halfword */ 4029 case 1410: /* Vector Average Signed Word */ 4030 case 1026: /* Vector Average Unsigned Byte */ 4031 case 1090: /* Vector Average Unsigned Halfword */ 4032 case 1154: /* Vector Average Unsigned Word */ 4033 case 258: /* Vector Maximum Signed Byte */ 4034 case 322: /* Vector Maximum Signed Halfword */ 4035 case 386: /* Vector Maximum Signed Word */ 4036 case 450: /* Vector Maximum Signed Doubleword */ 4037 case 2: /* Vector Maximum Unsigned Byte */ 4038 case 66: /* Vector Maximum Unsigned Halfword */ 4039 case 130: /* Vector Maximum Unsigned Word */ 4040 case 194: /* Vector Maximum Unsigned Doubleword */ 4041 case 770: /* Vector Minimum Signed Byte */ 4042 case 834: /* Vector Minimum Signed Halfword */ 4043 case 898: /* Vector Minimum Signed Word */ 4044 case 962: /* Vector Minimum Signed Doubleword */ 4045 case 514: /* Vector Minimum Unsigned Byte */ 4046 case 578: /* Vector Minimum Unsigned Halfword */ 4047 case 642: /* Vector Minimum Unsigned Word */ 4048 case 706: /* Vector Minimum Unsigned Doubleword */ 4049 case 1028: /* Vector Logical AND */ 4050 case 1668: /* Vector Logical Equivalent */ 4051 case 1092: /* Vector Logical AND with Complement */ 4052 case 1412: /* Vector Logical NAND */ 4053 case 1348: /* Vector Logical OR with Complement */ 4054 case 1156: /* Vector Logical OR */ 4055 case 1284: /* Vector Logical NOR */ 4056 case 1220: /* Vector Logical XOR */ 4057 case 4: /* Vector Rotate Left Byte */ 4058 case 132: /* Vector Rotate Left Word VX-form */ 4059 case 68: /* Vector Rotate Left Halfword */ 4060 case 196: /* Vector Rotate Left Doubleword */ 4061 case 260: /* Vector Shift Left Byte */ 4062 case 388: /* Vector Shift Left Word */ 4063 case 324: /* Vector Shift Left Halfword */ 4064 case 1476: /* Vector Shift Left Doubleword */ 4065 case 516: /* Vector Shift Right Byte */ 4066 case 644: /* Vector Shift Right Word */ 4067 case 580: /* Vector Shift Right Halfword */ 4068 case 1732: /* Vector Shift Right Doubleword */ 4069 case 772: /* Vector Shift Right Algebraic Byte */ 4070 case 900: /* Vector Shift Right Algebraic Word */ 4071 case 836: /* Vector Shift Right Algebraic Halfword */ 4072 case 964: /* Vector Shift Right Algebraic Doubleword */ 4073 case 10: /* Vector Add Single-Precision */ 4074 case 74: /* Vector Subtract Single-Precision */ 4075 case 1034: /* Vector Maximum Single-Precision */ 4076 case 1098: /* Vector Minimum Single-Precision */ 4077 case 842: /* Vector Convert From Signed Fixed-Point Word */ 4078 case 778: /* Vector Convert From Unsigned Fixed-Point Word */ 4079 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */ 4080 case 522: /* Vector Round to Single-Precision Integer Nearest */ 4081 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */ 4082 case 586: /* Vector Round to Single-Precision Integer toward Zero */ 4083 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */ 4084 case 458: /* Vector Log Base 2 Estimate Floating-Point */ 4085 case 266: /* Vector Reciprocal Estimate Single-Precision */ 4086 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */ 4087 case 1288: /* Vector AES Cipher */ 4088 case 1289: /* Vector AES Cipher Last */ 4089 case 1352: /* Vector AES Inverse Cipher */ 4090 case 1353: /* Vector AES Inverse Cipher Last */ 4091 case 1480: /* Vector AES SubBytes */ 4092 case 1730: /* Vector SHA-512 Sigma Doubleword */ 4093 case 1666: /* Vector SHA-256 Sigma Word */ 4094 case 1032: /* Vector Polynomial Multiply-Sum Byte */ 4095 case 1160: /* Vector Polynomial Multiply-Sum Word */ 4096 case 1096: /* Vector Polynomial Multiply-Sum Halfword */ 4097 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */ 4098 case 1292: /* Vector Gather Bits by Bytes by Doubleword */ 4099 case 1794: /* Vector Count Leading Zeros Byte */ 4100 case 1858: /* Vector Count Leading Zeros Halfword */ 4101 case 1922: /* Vector Count Leading Zeros Word */ 4102 case 1986: /* Vector Count Leading Zeros Doubleword */ 4103 case 1795: /* Vector Population Count Byte */ 4104 case 1859: /* Vector Population Count Halfword */ 4105 case 1923: /* Vector Population Count Word */ 4106 case 1987: /* Vector Population Count Doubleword */ 4107 case 1356: /* Vector Bit Permute Quadword */ 4108 record_full_arch_list_add_reg (regcache, 4109 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4110 return 0; 4111 4112 case 1604: /* Move To Vector Status and Control Register */ 4113 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 4114 return 0; 4115 case 1540: /* Move From Vector Status and Control Register */ 4116 record_full_arch_list_add_reg (regcache, 4117 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4118 return 0; 4119 } 4120 4121 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 4122 "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext); 4123 return -1; 4124 } 4125 4126 /* Parse and record instructions of primary opcode-19 at ADDR. 4127 Return 0 if successful. */ 4128 4129 static int 4130 ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache, 4131 CORE_ADDR addr, uint32_t insn) 4132 { 4133 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4134 int ext = PPC_EXTOP (insn); 4135 4136 switch (ext) 4137 { 4138 case 0: /* Move Condition Register Field */ 4139 case 33: /* Condition Register NOR */ 4140 case 129: /* Condition Register AND with Complement */ 4141 case 193: /* Condition Register XOR */ 4142 case 225: /* Condition Register NAND */ 4143 case 257: /* Condition Register AND */ 4144 case 289: /* Condition Register Equivalent */ 4145 case 417: /* Condition Register OR with Complement */ 4146 case 449: /* Condition Register OR */ 4147 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4148 return 0; 4149 4150 case 16: /* Branch Conditional */ 4151 case 560: /* Branch Conditional to Branch Target Address Register */ 4152 if ((PPC_BO (insn) & 0x4) == 0) 4153 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 4154 /* FALL-THROUGH */ 4155 case 528: /* Branch Conditional to Count Register */ 4156 if (PPC_LK (insn)) 4157 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 4158 return 0; 4159 4160 case 150: /* Instruction Synchronize */ 4161 /* Do nothing. */ 4162 return 0; 4163 } 4164 4165 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 4166 "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext); 4167 return -1; 4168 } 4169 4170 /* Parse and record instructions of primary opcode-31 at ADDR. 4171 Return 0 if successful. */ 4172 4173 static int 4174 ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache, 4175 CORE_ADDR addr, uint32_t insn) 4176 { 4177 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4178 int ext = PPC_EXTOP (insn); 4179 int tmp, nr, nb, i; 4180 CORE_ADDR at_dcsz, ea = 0; 4181 ULONGEST rb, ra, xer; 4182 int size = 0; 4183 4184 /* These instructions have OE bit. */ 4185 switch (ext & 0x1ff) 4186 { 4187 /* These write RT and XER. Update CR if RC is set. */ 4188 case 8: /* Subtract from carrying */ 4189 case 10: /* Add carrying */ 4190 case 136: /* Subtract from extended */ 4191 case 138: /* Add extended */ 4192 case 200: /* Subtract from zero extended */ 4193 case 202: /* Add to zero extended */ 4194 case 232: /* Subtract from minus one extended */ 4195 case 234: /* Add to minus one extended */ 4196 /* CA is always altered, but SO/OV are only altered when OE=1. 4197 In any case, XER is always altered. */ 4198 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4199 if (PPC_RC (insn)) 4200 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4201 record_full_arch_list_add_reg (regcache, 4202 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4203 return 0; 4204 4205 /* These write RT. Update CR if RC is set and update XER if OE is set. */ 4206 case 40: /* Subtract from */ 4207 case 104: /* Negate */ 4208 case 233: /* Multiply low doubleword */ 4209 case 235: /* Multiply low word */ 4210 case 266: /* Add */ 4211 case 393: /* Divide Doubleword Extended Unsigned */ 4212 case 395: /* Divide Word Extended Unsigned */ 4213 case 425: /* Divide Doubleword Extended */ 4214 case 427: /* Divide Word Extended */ 4215 case 457: /* Divide Doubleword Unsigned */ 4216 case 459: /* Divide Word Unsigned */ 4217 case 489: /* Divide Doubleword */ 4218 case 491: /* Divide Word */ 4219 if (PPC_OE (insn)) 4220 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4221 /* FALL-THROUGH */ 4222 case 9: /* Multiply High Doubleword Unsigned */ 4223 case 11: /* Multiply High Word Unsigned */ 4224 case 73: /* Multiply High Doubleword */ 4225 case 75: /* Multiply High Word */ 4226 if (PPC_RC (insn)) 4227 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4228 record_full_arch_list_add_reg (regcache, 4229 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4230 return 0; 4231 } 4232 4233 if ((ext & 0x1f) == 15) 4234 { 4235 /* Integer Select. bit[16:20] is used for BC. */ 4236 record_full_arch_list_add_reg (regcache, 4237 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4238 return 0; 4239 } 4240 4241 switch (ext) 4242 { 4243 case 78: /* Determine Leftmost Zero Byte */ 4244 if (PPC_RC (insn)) 4245 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4246 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4247 record_full_arch_list_add_reg (regcache, 4248 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4249 return 0; 4250 4251 /* These only write RT. */ 4252 case 19: /* Move from condition register */ 4253 /* Move From One Condition Register Field */ 4254 case 74: /* Add and Generate Sixes */ 4255 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */ 4256 case 302: /* Move From Branch History Rolling Buffer */ 4257 case 339: /* Move From Special Purpose Register */ 4258 case 371: /* Move From Time Base [Phased-Out] */ 4259 record_full_arch_list_add_reg (regcache, 4260 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4261 return 0; 4262 4263 /* These only write to RA. */ 4264 case 51: /* Move From VSR Doubleword */ 4265 case 115: /* Move From VSR Word and Zero */ 4266 case 122: /* Population count bytes */ 4267 case 378: /* Population count words */ 4268 case 506: /* Population count doublewords */ 4269 case 154: /* Parity Word */ 4270 case 186: /* Parity Doubleword */ 4271 case 252: /* Bit Permute Doubleword */ 4272 case 282: /* Convert Declets To Binary Coded Decimal */ 4273 case 314: /* Convert Binary Coded Decimal To Declets */ 4274 case 508: /* Compare bytes */ 4275 record_full_arch_list_add_reg (regcache, 4276 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4277 return 0; 4278 4279 /* These write CR and optional RA. */ 4280 case 792: /* Shift Right Algebraic Word */ 4281 case 794: /* Shift Right Algebraic Doubleword */ 4282 case 824: /* Shift Right Algebraic Word Immediate */ 4283 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */ 4284 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */ 4285 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4286 record_full_arch_list_add_reg (regcache, 4287 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4288 /* FALL-THROUGH */ 4289 case 0: /* Compare */ 4290 case 32: /* Compare logical */ 4291 case 144: /* Move To Condition Register Fields */ 4292 /* Move To One Condition Register Field */ 4293 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4294 return 0; 4295 4296 /* These write to RT. Update RA if 'update indexed.' */ 4297 case 53: /* Load Doubleword with Update Indexed */ 4298 case 119: /* Load Byte and Zero with Update Indexed */ 4299 case 311: /* Load Halfword and Zero with Update Indexed */ 4300 case 55: /* Load Word and Zero with Update Indexed */ 4301 case 375: /* Load Halfword Algebraic with Update Indexed */ 4302 case 373: /* Load Word Algebraic with Update Indexed */ 4303 record_full_arch_list_add_reg (regcache, 4304 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4305 /* FALL-THROUGH */ 4306 case 21: /* Load Doubleword Indexed */ 4307 case 52: /* Load Byte And Reserve Indexed */ 4308 case 116: /* Load Halfword And Reserve Indexed */ 4309 case 20: /* Load Word And Reserve Indexed */ 4310 case 84: /* Load Doubleword And Reserve Indexed */ 4311 case 87: /* Load Byte and Zero Indexed */ 4312 case 279: /* Load Halfword and Zero Indexed */ 4313 case 23: /* Load Word and Zero Indexed */ 4314 case 343: /* Load Halfword Algebraic Indexed */ 4315 case 341: /* Load Word Algebraic Indexed */ 4316 case 790: /* Load Halfword Byte-Reverse Indexed */ 4317 case 534: /* Load Word Byte-Reverse Indexed */ 4318 case 532: /* Load Doubleword Byte-Reverse Indexed */ 4319 record_full_arch_list_add_reg (regcache, 4320 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4321 return 0; 4322 4323 case 597: /* Load String Word Immediate */ 4324 case 533: /* Load String Word Indexed */ 4325 if (ext == 597) 4326 { 4327 nr = PPC_NB (insn); 4328 if (nr == 0) 4329 nr = 32; 4330 } 4331 else 4332 { 4333 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); 4334 nr = PPC_XER_NB (xer); 4335 } 4336 4337 nr = (nr + 3) >> 2; 4338 4339 /* If n=0, the contents of register RT are undefined. */ 4340 if (nr == 0) 4341 nr = 1; 4342 4343 for (i = 0; i < nr; i++) 4344 record_full_arch_list_add_reg (regcache, 4345 tdep->ppc_gp0_regnum 4346 + ((PPC_RT (insn) + i) & 0x1f)); 4347 return 0; 4348 4349 case 276: /* Load Quadword And Reserve Indexed */ 4350 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); 4351 record_full_arch_list_add_reg (regcache, tmp); 4352 record_full_arch_list_add_reg (regcache, tmp + 1); 4353 return 0; 4354 4355 /* These write VRT. */ 4356 case 6: /* Load Vector for Shift Left Indexed */ 4357 case 38: /* Load Vector for Shift Right Indexed */ 4358 case 7: /* Load Vector Element Byte Indexed */ 4359 case 39: /* Load Vector Element Halfword Indexed */ 4360 case 71: /* Load Vector Element Word Indexed */ 4361 case 103: /* Load Vector Indexed */ 4362 case 359: /* Load Vector Indexed LRU */ 4363 record_full_arch_list_add_reg (regcache, 4364 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4365 return 0; 4366 4367 /* These write FRT. Update RA if 'update indexed.' */ 4368 case 567: /* Load Floating-Point Single with Update Indexed */ 4369 case 631: /* Load Floating-Point Double with Update Indexed */ 4370 record_full_arch_list_add_reg (regcache, 4371 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4372 /* FALL-THROUGH */ 4373 case 535: /* Load Floating-Point Single Indexed */ 4374 case 599: /* Load Floating-Point Double Indexed */ 4375 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */ 4376 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */ 4377 record_full_arch_list_add_reg (regcache, 4378 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 4379 return 0; 4380 4381 case 791: /* Load Floating-Point Double Pair Indexed */ 4382 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 4383 record_full_arch_list_add_reg (regcache, tmp); 4384 record_full_arch_list_add_reg (regcache, tmp + 1); 4385 return 0; 4386 4387 case 179: /* Move To VSR Doubleword */ 4388 case 211: /* Move To VSR Word Algebraic */ 4389 case 243: /* Move To VSR Word and Zero */ 4390 case 588: /* Load VSX Scalar Doubleword Indexed */ 4391 case 524: /* Load VSX Scalar Single-Precision Indexed */ 4392 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */ 4393 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */ 4394 case 844: /* Load VSX Vector Doubleword*2 Indexed */ 4395 case 332: /* Load VSX Vector Doubleword & Splat Indexed */ 4396 case 780: /* Load VSX Vector Word*4 Indexed */ 4397 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 4398 return 0; 4399 4400 /* These write RA. Update CR if RC is set. */ 4401 case 24: /* Shift Left Word */ 4402 case 26: /* Count Leading Zeros Word */ 4403 case 27: /* Shift Left Doubleword */ 4404 case 28: /* AND */ 4405 case 58: /* Count Leading Zeros Doubleword */ 4406 case 60: /* AND with Complement */ 4407 case 124: /* NOR */ 4408 case 284: /* Equivalent */ 4409 case 316: /* XOR */ 4410 case 476: /* NAND */ 4411 case 412: /* OR with Complement */ 4412 case 444: /* OR */ 4413 case 536: /* Shift Right Word */ 4414 case 539: /* Shift Right Doubleword */ 4415 case 922: /* Extend Sign Halfword */ 4416 case 954: /* Extend Sign Byte */ 4417 case 986: /* Extend Sign Word */ 4418 if (PPC_RC (insn)) 4419 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4420 record_full_arch_list_add_reg (regcache, 4421 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4422 return 0; 4423 4424 /* Store memory. */ 4425 case 181: /* Store Doubleword with Update Indexed */ 4426 case 183: /* Store Word with Update Indexed */ 4427 case 247: /* Store Byte with Update Indexed */ 4428 case 439: /* Store Half Word with Update Indexed */ 4429 case 695: /* Store Floating-Point Single with Update Indexed */ 4430 case 759: /* Store Floating-Point Double with Update Indexed */ 4431 record_full_arch_list_add_reg (regcache, 4432 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4433 /* FALL-THROUGH */ 4434 case 135: /* Store Vector Element Byte Indexed */ 4435 case 167: /* Store Vector Element Halfword Indexed */ 4436 case 199: /* Store Vector Element Word Indexed */ 4437 case 231: /* Store Vector Indexed */ 4438 case 487: /* Store Vector Indexed LRU */ 4439 case 716: /* Store VSX Scalar Doubleword Indexed */ 4440 case 140: /* Store VSX Scalar as Integer Word Indexed */ 4441 case 652: /* Store VSX Scalar Single-Precision Indexed */ 4442 case 972: /* Store VSX Vector Doubleword*2 Indexed */ 4443 case 908: /* Store VSX Vector Word*4 Indexed */ 4444 case 149: /* Store Doubleword Indexed */ 4445 case 151: /* Store Word Indexed */ 4446 case 215: /* Store Byte Indexed */ 4447 case 407: /* Store Half Word Indexed */ 4448 case 694: /* Store Byte Conditional Indexed */ 4449 case 726: /* Store Halfword Conditional Indexed */ 4450 case 150: /* Store Word Conditional Indexed */ 4451 case 214: /* Store Doubleword Conditional Indexed */ 4452 case 182: /* Store Quadword Conditional Indexed */ 4453 case 662: /* Store Word Byte-Reverse Indexed */ 4454 case 918: /* Store Halfword Byte-Reverse Indexed */ 4455 case 660: /* Store Doubleword Byte-Reverse Indexed */ 4456 case 663: /* Store Floating-Point Single Indexed */ 4457 case 727: /* Store Floating-Point Double Indexed */ 4458 case 919: /* Store Floating-Point Double Pair Indexed */ 4459 case 983: /* Store Floating-Point as Integer Word Indexed */ 4460 if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182) 4461 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4462 4463 ra = 0; 4464 if (PPC_RA (insn) != 0) 4465 regcache_raw_read_unsigned (regcache, 4466 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 4467 regcache_raw_read_unsigned (regcache, 4468 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 4469 ea = ra + rb; 4470 4471 switch (ext) 4472 { 4473 case 183: /* Store Word with Update Indexed */ 4474 case 199: /* Store Vector Element Word Indexed */ 4475 case 140: /* Store VSX Scalar as Integer Word Indexed */ 4476 case 652: /* Store VSX Scalar Single-Precision Indexed */ 4477 case 151: /* Store Word Indexed */ 4478 case 150: /* Store Word Conditional Indexed */ 4479 case 662: /* Store Word Byte-Reverse Indexed */ 4480 case 663: /* Store Floating-Point Single Indexed */ 4481 case 695: /* Store Floating-Point Single with Update Indexed */ 4482 case 983: /* Store Floating-Point as Integer Word Indexed */ 4483 size = 4; 4484 break; 4485 case 247: /* Store Byte with Update Indexed */ 4486 case 135: /* Store Vector Element Byte Indexed */ 4487 case 215: /* Store Byte Indexed */ 4488 case 694: /* Store Byte Conditional Indexed */ 4489 size = 1; 4490 break; 4491 case 439: /* Store Halfword with Update Indexed */ 4492 case 167: /* Store Vector Element Halfword Indexed */ 4493 case 407: /* Store Halfword Indexed */ 4494 case 726: /* Store Halfword Conditional Indexed */ 4495 case 918: /* Store Halfword Byte-Reverse Indexed */ 4496 size = 2; 4497 break; 4498 case 181: /* Store Doubleword with Update Indexed */ 4499 case 716: /* Store VSX Scalar Doubleword Indexed */ 4500 case 149: /* Store Doubleword Indexed */ 4501 case 214: /* Store Doubleword Conditional Indexed */ 4502 case 660: /* Store Doubleword Byte-Reverse Indexed */ 4503 case 727: /* Store Floating-Point Double Indexed */ 4504 case 759: /* Store Floating-Point Double with Update Indexed */ 4505 size = 8; 4506 break; 4507 case 972: /* Store VSX Vector Doubleword*2 Indexed */ 4508 case 908: /* Store VSX Vector Word*4 Indexed */ 4509 case 182: /* Store Quadword Conditional Indexed */ 4510 case 231: /* Store Vector Indexed */ 4511 case 487: /* Store Vector Indexed LRU */ 4512 case 919: /* Store Floating-Point Double Pair Indexed */ 4513 size = 16; 4514 break; 4515 default: 4516 gdb_assert (0); 4517 } 4518 4519 /* Align address for Store Vector instructions. */ 4520 switch (ext) 4521 { 4522 case 167: /* Store Vector Element Halfword Indexed */ 4523 addr = addr & ~0x1ULL; 4524 break; 4525 4526 case 199: /* Store Vector Element Word Indexed */ 4527 addr = addr & ~0x3ULL; 4528 break; 4529 4530 case 231: /* Store Vector Indexed */ 4531 case 487: /* Store Vector Indexed LRU */ 4532 addr = addr & ~0xfULL; 4533 break; 4534 } 4535 4536 record_full_arch_list_add_mem (addr, size); 4537 return 0; 4538 4539 case 725: /* Store String Word Immediate */ 4540 ra = 0; 4541 if (PPC_RA (insn) != 0) 4542 regcache_raw_read_unsigned (regcache, 4543 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 4544 ea += ra; 4545 4546 nb = PPC_NB (insn); 4547 if (nb == 0) 4548 nb = 32; 4549 4550 record_full_arch_list_add_mem (ea, nb); 4551 4552 return 0; 4553 4554 case 661: /* Store String Word Indexed */ 4555 ra = 0; 4556 if (PPC_RA (insn) != 0) 4557 regcache_raw_read_unsigned (regcache, 4558 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 4559 ea += ra; 4560 4561 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); 4562 nb = PPC_XER_NB (xer); 4563 4564 if (nb != 0) 4565 { 4566 regcache_raw_read_unsigned (regcache, 4567 tdep->ppc_gp0_regnum + PPC_RB (insn), 4568 &rb); 4569 ea += rb; 4570 record_full_arch_list_add_mem (ea, nb); 4571 } 4572 4573 return 0; 4574 4575 case 467: /* Move To Special Purpose Register */ 4576 switch (PPC_SPR (insn)) 4577 { 4578 case 1: /* XER */ 4579 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4580 return 0; 4581 case 8: /* LR */ 4582 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 4583 return 0; 4584 case 9: /* CTR */ 4585 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 4586 return 0; 4587 case 256: /* VRSAVE */ 4588 record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum); 4589 return 0; 4590 } 4591 4592 goto UNKNOWN_OP; 4593 4594 case 147: /* Move To Split Little Endian */ 4595 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); 4596 return 0; 4597 4598 case 512: /* Move to Condition Register from XER */ 4599 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4600 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4601 return 0; 4602 4603 case 4: /* Trap Word */ 4604 case 68: /* Trap Doubleword */ 4605 case 430: /* Clear BHRB */ 4606 case 598: /* Synchronize */ 4607 case 62: /* Wait for Interrupt */ 4608 case 22: /* Instruction Cache Block Touch */ 4609 case 854: /* Enforce In-order Execution of I/O */ 4610 case 246: /* Data Cache Block Touch for Store */ 4611 case 54: /* Data Cache Block Store */ 4612 case 86: /* Data Cache Block Flush */ 4613 case 278: /* Data Cache Block Touch */ 4614 case 758: /* Data Cache Block Allocate */ 4615 case 982: /* Instruction Cache Block Invalidate */ 4616 return 0; 4617 4618 case 654: /* Transaction Begin */ 4619 case 686: /* Transaction End */ 4620 case 750: /* Transaction Suspend or Resume */ 4621 case 782: /* Transaction Abort Word Conditional */ 4622 case 814: /* Transaction Abort Doubleword Conditional */ 4623 case 846: /* Transaction Abort Word Conditional Immediate */ 4624 case 878: /* Transaction Abort Doubleword Conditional Immediate */ 4625 case 910: /* Transaction Abort */ 4626 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); 4627 /* FALL-THROUGH */ 4628 case 718: /* Transaction Check */ 4629 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4630 return 0; 4631 4632 case 1014: /* Data Cache Block set to Zero */ 4633 if (target_auxv_search (¤t_target, AT_DCACHEBSIZE, &at_dcsz) <= 0 4634 || at_dcsz == 0) 4635 at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */ 4636 4637 ra = 0; 4638 if (PPC_RA (insn) != 0) 4639 regcache_raw_read_unsigned (regcache, 4640 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 4641 regcache_raw_read_unsigned (regcache, 4642 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 4643 ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1)); 4644 record_full_arch_list_add_mem (ea, at_dcsz); 4645 return 0; 4646 } 4647 4648 UNKNOWN_OP: 4649 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 4650 "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext); 4651 return -1; 4652 } 4653 4654 /* Parse and record instructions of primary opcode-59 at ADDR. 4655 Return 0 if successful. */ 4656 4657 static int 4658 ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache, 4659 CORE_ADDR addr, uint32_t insn) 4660 { 4661 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4662 int ext = PPC_EXTOP (insn); 4663 4664 switch (ext & 0x1f) 4665 { 4666 case 18: /* Floating Divide */ 4667 case 20: /* Floating Subtract */ 4668 case 21: /* Floating Add */ 4669 case 22: /* Floating Square Root */ 4670 case 24: /* Floating Reciprocal Estimate */ 4671 case 25: /* Floating Multiply */ 4672 case 26: /* Floating Reciprocal Square Root Estimate */ 4673 case 28: /* Floating Multiply-Subtract */ 4674 case 29: /* Floating Multiply-Add */ 4675 case 30: /* Floating Negative Multiply-Subtract */ 4676 case 31: /* Floating Negative Multiply-Add */ 4677 record_full_arch_list_add_reg (regcache, 4678 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 4679 if (PPC_RC (insn)) 4680 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4681 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4682 4683 return 0; 4684 } 4685 4686 switch (ext) 4687 { 4688 case 2: /* DFP Add */ 4689 case 3: /* DFP Quantize */ 4690 case 34: /* DFP Multiply */ 4691 case 35: /* DFP Reround */ 4692 case 67: /* DFP Quantize Immediate */ 4693 case 99: /* DFP Round To FP Integer With Inexact */ 4694 case 227: /* DFP Round To FP Integer Without Inexact */ 4695 case 258: /* DFP Convert To DFP Long! */ 4696 case 290: /* DFP Convert To Fixed */ 4697 case 514: /* DFP Subtract */ 4698 case 546: /* DFP Divide */ 4699 case 770: /* DFP Round To DFP Short! */ 4700 case 802: /* DFP Convert From Fixed */ 4701 case 834: /* DFP Encode BCD To DPD */ 4702 if (PPC_RC (insn)) 4703 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4704 record_full_arch_list_add_reg (regcache, 4705 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 4706 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4707 return 0; 4708 4709 case 130: /* DFP Compare Ordered */ 4710 case 162: /* DFP Test Exponent */ 4711 case 194: /* DFP Test Data Class */ 4712 case 226: /* DFP Test Data Group */ 4713 case 642: /* DFP Compare Unordered */ 4714 case 674: /* DFP Test Significance */ 4715 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4716 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4717 return 0; 4718 4719 case 66: /* DFP Shift Significand Left Immediate */ 4720 case 98: /* DFP Shift Significand Right Immediate */ 4721 case 322: /* DFP Decode DPD To BCD */ 4722 case 354: /* DFP Extract Biased Exponent */ 4723 case 866: /* DFP Insert Biased Exponent */ 4724 record_full_arch_list_add_reg (regcache, 4725 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 4726 if (PPC_RC (insn)) 4727 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4728 return 0; 4729 4730 case 846: /* Floating Convert From Integer Doubleword Single */ 4731 case 974: /* Floating Convert From Integer Doubleword Unsigned 4732 Single */ 4733 record_full_arch_list_add_reg (regcache, 4734 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 4735 if (PPC_RC (insn)) 4736 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4737 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4738 4739 return 0; 4740 } 4741 4742 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 4743 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); 4744 return -1; 4745 } 4746 4747 /* Parse and record instructions of primary opcode-60 at ADDR. 4748 Return 0 if successful. */ 4749 4750 static int 4751 ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, 4752 CORE_ADDR addr, uint32_t insn) 4753 { 4754 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4755 int ext = PPC_EXTOP (insn); 4756 4757 switch (ext >> 2) 4758 { 4759 case 0: /* VSX Scalar Add Single-Precision */ 4760 case 32: /* VSX Scalar Add Double-Precision */ 4761 case 24: /* VSX Scalar Divide Single-Precision */ 4762 case 56: /* VSX Scalar Divide Double-Precision */ 4763 case 176: /* VSX Scalar Copy Sign Double-Precision */ 4764 case 33: /* VSX Scalar Multiply-Add Double-Precision */ 4765 case 41: /* ditto */ 4766 case 1: /* VSX Scalar Multiply-Add Single-Precision */ 4767 case 9: /* ditto */ 4768 case 160: /* VSX Scalar Maximum Double-Precision */ 4769 case 168: /* VSX Scalar Minimum Double-Precision */ 4770 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */ 4771 case 57: /* ditto */ 4772 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */ 4773 case 25: /* ditto */ 4774 case 48: /* VSX Scalar Multiply Double-Precision */ 4775 case 16: /* VSX Scalar Multiply Single-Precision */ 4776 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */ 4777 case 169: /* ditto */ 4778 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */ 4779 case 137: /* ditto */ 4780 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */ 4781 case 185: /* ditto */ 4782 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */ 4783 case 153: /* ditto */ 4784 case 40: /* VSX Scalar Subtract Double-Precision */ 4785 case 8: /* VSX Scalar Subtract Single-Precision */ 4786 case 96: /* VSX Vector Add Double-Precision */ 4787 case 64: /* VSX Vector Add Single-Precision */ 4788 case 120: /* VSX Vector Divide Double-Precision */ 4789 case 88: /* VSX Vector Divide Single-Precision */ 4790 case 97: /* VSX Vector Multiply-Add Double-Precision */ 4791 case 105: /* ditto */ 4792 case 65: /* VSX Vector Multiply-Add Single-Precision */ 4793 case 73: /* ditto */ 4794 case 224: /* VSX Vector Maximum Double-Precision */ 4795 case 192: /* VSX Vector Maximum Single-Precision */ 4796 case 232: /* VSX Vector Minimum Double-Precision */ 4797 case 200: /* VSX Vector Minimum Single-Precision */ 4798 case 113: /* VSX Vector Multiply-Subtract Double-Precision */ 4799 case 121: /* ditto */ 4800 case 81: /* VSX Vector Multiply-Subtract Single-Precision */ 4801 case 89: /* ditto */ 4802 case 112: /* VSX Vector Multiply Double-Precision */ 4803 case 80: /* VSX Vector Multiply Single-Precision */ 4804 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */ 4805 case 233: /* ditto */ 4806 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */ 4807 case 201: /* ditto */ 4808 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */ 4809 case 249: /* ditto */ 4810 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */ 4811 case 217: /* ditto */ 4812 case 104: /* VSX Vector Subtract Double-Precision */ 4813 case 72: /* VSX Vector Subtract Single-Precision */ 4814 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4815 case 240: /* VSX Vector Copy Sign Double-Precision */ 4816 case 208: /* VSX Vector Copy Sign Single-Precision */ 4817 case 130: /* VSX Logical AND */ 4818 case 138: /* VSX Logical AND with Complement */ 4819 case 186: /* VSX Logical Equivalence */ 4820 case 178: /* VSX Logical NAND */ 4821 case 170: /* VSX Logical OR with Complement */ 4822 case 162: /* VSX Logical NOR */ 4823 case 146: /* VSX Logical OR */ 4824 case 154: /* VSX Logical XOR */ 4825 case 18: /* VSX Merge High Word */ 4826 case 50: /* VSX Merge Low Word */ 4827 case 10: /* VSX Permute Doubleword Immediate (DM=0) */ 4828 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */ 4829 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */ 4830 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */ 4831 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */ 4832 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */ 4833 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */ 4834 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */ 4835 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 4836 return 0; 4837 4838 case 61: /* VSX Scalar Test for software Divide Double-Precision */ 4839 case 125: /* VSX Vector Test for software Divide Double-Precision */ 4840 case 93: /* VSX Vector Test for software Divide Single-Precision */ 4841 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4842 return 0; 4843 4844 case 35: /* VSX Scalar Compare Unordered Double-Precision */ 4845 case 43: /* VSX Scalar Compare Ordered Double-Precision */ 4846 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4847 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4848 return 0; 4849 } 4850 4851 switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */ 4852 { 4853 case 99: /* VSX Vector Compare Equal To Double-Precision */ 4854 case 67: /* VSX Vector Compare Equal To Single-Precision */ 4855 case 115: /* VSX Vector Compare Greater Than or 4856 Equal To Double-Precision */ 4857 case 83: /* VSX Vector Compare Greater Than or 4858 Equal To Single-Precision */ 4859 case 107: /* VSX Vector Compare Greater Than Double-Precision */ 4860 case 75: /* VSX Vector Compare Greater Than Single-Precision */ 4861 if (PPC_Rc (insn)) 4862 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4863 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4864 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 4865 return 0; 4866 } 4867 4868 switch (ext >> 1) 4869 { 4870 case 265: /* VSX Scalar round Double-Precision to 4871 Single-Precision and Convert to 4872 Single-Precision format */ 4873 case 344: /* VSX Scalar truncate Double-Precision to 4874 Integer and Convert to Signed Integer 4875 Doubleword format with Saturate */ 4876 case 88: /* VSX Scalar truncate Double-Precision to 4877 Integer and Convert to Signed Integer Word 4878 Format with Saturate */ 4879 case 328: /* VSX Scalar truncate Double-Precision integer 4880 and Convert to Unsigned Integer Doubleword 4881 Format with Saturate */ 4882 case 72: /* VSX Scalar truncate Double-Precision to 4883 Integer and Convert to Unsigned Integer Word 4884 Format with Saturate */ 4885 case 329: /* VSX Scalar Convert Single-Precision to 4886 Double-Precision format */ 4887 case 376: /* VSX Scalar Convert Signed Integer 4888 Doubleword to floating-point format and 4889 Round to Double-Precision format */ 4890 case 312: /* VSX Scalar Convert Signed Integer 4891 Doubleword to floating-point format and 4892 round to Single-Precision */ 4893 case 360: /* VSX Scalar Convert Unsigned Integer 4894 Doubleword to floating-point format and 4895 Round to Double-Precision format */ 4896 case 296: /* VSX Scalar Convert Unsigned Integer 4897 Doubleword to floating-point format and 4898 Round to Single-Precision */ 4899 case 73: /* VSX Scalar Round to Double-Precision Integer 4900 Using Round to Nearest Away */ 4901 case 107: /* VSX Scalar Round to Double-Precision Integer 4902 Exact using Current rounding mode */ 4903 case 121: /* VSX Scalar Round to Double-Precision Integer 4904 Using Round toward -Infinity */ 4905 case 105: /* VSX Scalar Round to Double-Precision Integer 4906 Using Round toward +Infinity */ 4907 case 89: /* VSX Scalar Round to Double-Precision Integer 4908 Using Round toward Zero */ 4909 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */ 4910 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */ 4911 case 281: /* VSX Scalar Round to Single-Precision */ 4912 case 74: /* VSX Scalar Reciprocal Square Root Estimate 4913 Double-Precision */ 4914 case 10: /* VSX Scalar Reciprocal Square Root Estimate 4915 Single-Precision */ 4916 case 75: /* VSX Scalar Square Root Double-Precision */ 4917 case 11: /* VSX Scalar Square Root Single-Precision */ 4918 case 393: /* VSX Vector round Double-Precision to 4919 Single-Precision and Convert to 4920 Single-Precision format */ 4921 case 472: /* VSX Vector truncate Double-Precision to 4922 Integer and Convert to Signed Integer 4923 Doubleword format with Saturate */ 4924 case 216: /* VSX Vector truncate Double-Precision to 4925 Integer and Convert to Signed Integer Word 4926 Format with Saturate */ 4927 case 456: /* VSX Vector truncate Double-Precision to 4928 Integer and Convert to Unsigned Integer 4929 Doubleword format with Saturate */ 4930 case 200: /* VSX Vector truncate Double-Precision to 4931 Integer and Convert to Unsigned Integer Word 4932 Format with Saturate */ 4933 case 457: /* VSX Vector Convert Single-Precision to 4934 Double-Precision format */ 4935 case 408: /* VSX Vector truncate Single-Precision to 4936 Integer and Convert to Signed Integer 4937 Doubleword format with Saturate */ 4938 case 152: /* VSX Vector truncate Single-Precision to 4939 Integer and Convert to Signed Integer Word 4940 Format with Saturate */ 4941 case 392: /* VSX Vector truncate Single-Precision to 4942 Integer and Convert to Unsigned Integer 4943 Doubleword format with Saturate */ 4944 case 136: /* VSX Vector truncate Single-Precision to 4945 Integer and Convert to Unsigned Integer Word 4946 Format with Saturate */ 4947 case 504: /* VSX Vector Convert and round Signed Integer 4948 Doubleword to Double-Precision format */ 4949 case 440: /* VSX Vector Convert and round Signed Integer 4950 Doubleword to Single-Precision format */ 4951 case 248: /* VSX Vector Convert Signed Integer Word to 4952 Double-Precision format */ 4953 case 184: /* VSX Vector Convert and round Signed Integer 4954 Word to Single-Precision format */ 4955 case 488: /* VSX Vector Convert and round Unsigned 4956 Integer Doubleword to Double-Precision format */ 4957 case 424: /* VSX Vector Convert and round Unsigned 4958 Integer Doubleword to Single-Precision format */ 4959 case 232: /* VSX Vector Convert and round Unsigned 4960 Integer Word to Double-Precision format */ 4961 case 168: /* VSX Vector Convert and round Unsigned 4962 Integer Word to Single-Precision format */ 4963 case 201: /* VSX Vector Round to Double-Precision 4964 Integer using round to Nearest Away */ 4965 case 235: /* VSX Vector Round to Double-Precision 4966 Integer Exact using Current rounding mode */ 4967 case 249: /* VSX Vector Round to Double-Precision 4968 Integer using round toward -Infinity */ 4969 case 233: /* VSX Vector Round to Double-Precision 4970 Integer using round toward +Infinity */ 4971 case 217: /* VSX Vector Round to Double-Precision 4972 Integer using round toward Zero */ 4973 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */ 4974 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */ 4975 case 137: /* VSX Vector Round to Single-Precision Integer 4976 Using Round to Nearest Away */ 4977 case 171: /* VSX Vector Round to Single-Precision Integer 4978 Exact Using Current rounding mode */ 4979 case 185: /* VSX Vector Round to Single-Precision Integer 4980 Using Round toward -Infinity */ 4981 case 169: /* VSX Vector Round to Single-Precision Integer 4982 Using Round toward +Infinity */ 4983 case 153: /* VSX Vector Round to Single-Precision Integer 4984 Using round toward Zero */ 4985 case 202: /* VSX Vector Reciprocal Square Root Estimate 4986 Double-Precision */ 4987 case 138: /* VSX Vector Reciprocal Square Root Estimate 4988 Single-Precision */ 4989 case 203: /* VSX Vector Square Root Double-Precision */ 4990 case 139: /* VSX Vector Square Root Single-Precision */ 4991 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4992 case 345: /* VSX Scalar Absolute Value Double-Precision */ 4993 case 267: /* VSX Scalar Convert Scalar Single-Precision to 4994 Vector Single-Precision format Non-signalling */ 4995 case 331: /* VSX Scalar Convert Single-Precision to 4996 Double-Precision format Non-signalling */ 4997 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */ 4998 case 377: /* VSX Scalar Negate Double-Precision */ 4999 case 473: /* VSX Vector Absolute Value Double-Precision */ 5000 case 409: /* VSX Vector Absolute Value Single-Precision */ 5001 case 489: /* VSX Vector Negative Absolute Value Double-Precision */ 5002 case 425: /* VSX Vector Negative Absolute Value Single-Precision */ 5003 case 505: /* VSX Vector Negate Double-Precision */ 5004 case 441: /* VSX Vector Negate Single-Precision */ 5005 case 164: /* VSX Splat Word */ 5006 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5007 return 0; 5008 5009 case 106: /* VSX Scalar Test for software Square Root 5010 Double-Precision */ 5011 case 234: /* VSX Vector Test for software Square Root 5012 Double-Precision */ 5013 case 170: /* VSX Vector Test for software Square Root 5014 Single-Precision */ 5015 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5016 return 0; 5017 } 5018 5019 if (((ext >> 3) & 0x3) == 3) /* VSX Select */ 5020 { 5021 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5022 return 0; 5023 } 5024 5025 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 5026 "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext); 5027 return -1; 5028 } 5029 5030 /* Parse and record instructions of primary opcode-63 at ADDR. 5031 Return 0 if successful. */ 5032 5033 static int 5034 ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, 5035 CORE_ADDR addr, uint32_t insn) 5036 { 5037 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5038 int ext = PPC_EXTOP (insn); 5039 int tmp; 5040 5041 switch (ext & 0x1f) 5042 { 5043 case 18: /* Floating Divide */ 5044 case 20: /* Floating Subtract */ 5045 case 21: /* Floating Add */ 5046 case 22: /* Floating Square Root */ 5047 case 24: /* Floating Reciprocal Estimate */ 5048 case 25: /* Floating Multiply */ 5049 case 26: /* Floating Reciprocal Square Root Estimate */ 5050 case 28: /* Floating Multiply-Subtract */ 5051 case 29: /* Floating Multiply-Add */ 5052 case 30: /* Floating Negative Multiply-Subtract */ 5053 case 31: /* Floating Negative Multiply-Add */ 5054 record_full_arch_list_add_reg (regcache, 5055 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5056 if (PPC_RC (insn)) 5057 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5058 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5059 return 0; 5060 5061 case 23: /* Floating Select */ 5062 record_full_arch_list_add_reg (regcache, 5063 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5064 if (PPC_RC (insn)) 5065 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5066 } 5067 5068 switch (ext) 5069 { 5070 case 2: /* DFP Add Quad */ 5071 case 3: /* DFP Quantize Quad */ 5072 case 34: /* DFP Multiply Quad */ 5073 case 35: /* DFP Reround Quad */ 5074 case 67: /* DFP Quantize Immediate Quad */ 5075 case 99: /* DFP Round To FP Integer With Inexact Quad */ 5076 case 227: /* DFP Round To FP Integer Without Inexact Quad */ 5077 case 258: /* DFP Convert To DFP Extended Quad */ 5078 case 514: /* DFP Subtract Quad */ 5079 case 546: /* DFP Divide Quad */ 5080 case 770: /* DFP Round To DFP Long Quad */ 5081 case 802: /* DFP Convert From Fixed Quad */ 5082 case 834: /* DFP Encode BCD To DPD Quad */ 5083 if (PPC_RC (insn)) 5084 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5085 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 5086 record_full_arch_list_add_reg (regcache, tmp); 5087 record_full_arch_list_add_reg (regcache, tmp + 1); 5088 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5089 return 0; 5090 5091 case 130: /* DFP Compare Ordered Quad */ 5092 case 162: /* DFP Test Exponent Quad */ 5093 case 194: /* DFP Test Data Class Quad */ 5094 case 226: /* DFP Test Data Group Quad */ 5095 case 642: /* DFP Compare Unordered Quad */ 5096 case 674: /* DFP Test Significance Quad */ 5097 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5098 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5099 return 0; 5100 5101 case 66: /* DFP Shift Significand Left Immediate Quad */ 5102 case 98: /* DFP Shift Significand Right Immediate Quad */ 5103 case 322: /* DFP Decode DPD To BCD Quad */ 5104 case 866: /* DFP Insert Biased Exponent Quad */ 5105 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 5106 record_full_arch_list_add_reg (regcache, tmp); 5107 record_full_arch_list_add_reg (regcache, tmp + 1); 5108 if (PPC_RC (insn)) 5109 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5110 return 0; 5111 5112 case 290: /* DFP Convert To Fixed Quad */ 5113 record_full_arch_list_add_reg (regcache, 5114 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5115 if (PPC_RC (insn)) 5116 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5117 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5118 break; 5119 5120 case 354: /* DFP Extract Biased Exponent Quad */ 5121 record_full_arch_list_add_reg (regcache, 5122 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5123 if (PPC_RC (insn)) 5124 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5125 return 0; 5126 5127 case 12: /* Floating Round to Single-Precision */ 5128 case 14: /* Floating Convert To Integer Word */ 5129 case 15: /* Floating Convert To Integer Word 5130 with round toward Zero */ 5131 case 142: /* Floating Convert To Integer Word Unsigned */ 5132 case 143: /* Floating Convert To Integer Word Unsigned 5133 with round toward Zero */ 5134 case 392: /* Floating Round to Integer Nearest */ 5135 case 424: /* Floating Round to Integer Toward Zero */ 5136 case 456: /* Floating Round to Integer Plus */ 5137 case 488: /* Floating Round to Integer Minus */ 5138 case 814: /* Floating Convert To Integer Doubleword */ 5139 case 815: /* Floating Convert To Integer Doubleword 5140 with round toward Zero */ 5141 case 846: /* Floating Convert From Integer Doubleword */ 5142 case 942: /* Floating Convert To Integer Doubleword Unsigned */ 5143 case 943: /* Floating Convert To Integer Doubleword Unsigned 5144 with round toward Zero */ 5145 case 974: /* Floating Convert From Integer Doubleword Unsigned */ 5146 record_full_arch_list_add_reg (regcache, 5147 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5148 if (PPC_RC (insn)) 5149 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5150 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5151 return 0; 5152 5153 case 583: /* Move From FPSCR */ 5154 case 8: /* Floating Copy Sign */ 5155 case 40: /* Floating Negate */ 5156 case 72: /* Floating Move Register */ 5157 case 136: /* Floating Negative Absolute Value */ 5158 case 264: /* Floating Absolute Value */ 5159 record_full_arch_list_add_reg (regcache, 5160 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5161 if (PPC_RC (insn)) 5162 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5163 return 0; 5164 5165 case 838: /* Floating Merge Odd Word */ 5166 case 966: /* Floating Merge Even Word */ 5167 record_full_arch_list_add_reg (regcache, 5168 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5169 return 0; 5170 5171 case 38: /* Move To FPSCR Bit 1 */ 5172 case 70: /* Move To FPSCR Bit 0 */ 5173 case 134: /* Move To FPSCR Field Immediate */ 5174 case 711: /* Move To FPSCR Fields */ 5175 if (PPC_RC (insn)) 5176 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5177 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5178 break; 5179 5180 case 0: /* Floating Compare Unordered */ 5181 case 32: /* Floating Compare Ordered */ 5182 case 64: /* Move to Condition Register from FPSCR */ 5183 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5184 /* FALL-THROUGH */ 5185 case 128: /* Floating Test for software Divide */ 5186 case 160: /* Floating Test for software Square Root */ 5187 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5188 return 0; 5189 5190 } 5191 5192 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 5193 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); 5194 return -1; 5195 } 5196 5197 /* Parse the current instruction and record the values of the registers and 5198 memory that will be changed in current instruction to "record_arch_list". 5199 Return -1 if something wrong. */ 5200 5201 int 5202 ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 5203 CORE_ADDR addr) 5204 { 5205 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5206 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5207 uint32_t insn; 5208 int op6, tmp, i; 5209 5210 insn = read_memory_unsigned_integer (addr, 4, byte_order); 5211 op6 = PPC_OP6 (insn); 5212 5213 switch (op6) 5214 { 5215 case 2: /* Trap Doubleword Immediate */ 5216 case 3: /* Trap Word Immediate */ 5217 /* Do nothing. */ 5218 break; 5219 5220 case 4: 5221 if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0) 5222 return -1; 5223 break; 5224 5225 case 17: /* System call */ 5226 if (PPC_LEV (insn) != 0) 5227 goto UNKNOWN_OP; 5228 5229 if (tdep->ppc_syscall_record != NULL) 5230 { 5231 if (tdep->ppc_syscall_record (regcache) != 0) 5232 return -1; 5233 } 5234 else 5235 { 5236 printf_unfiltered (_("no syscall record support\n")); 5237 return -1; 5238 } 5239 break; 5240 5241 case 7: /* Multiply Low Immediate */ 5242 record_full_arch_list_add_reg (regcache, 5243 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5244 break; 5245 5246 case 8: /* Subtract From Immediate Carrying */ 5247 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 5248 record_full_arch_list_add_reg (regcache, 5249 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5250 break; 5251 5252 case 10: /* Compare Logical Immediate */ 5253 case 11: /* Compare Immediate */ 5254 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5255 break; 5256 5257 case 13: /* Add Immediate Carrying and Record */ 5258 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5259 /* FALL-THROUGH */ 5260 case 12: /* Add Immediate Carrying */ 5261 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 5262 /* FALL-THROUGH */ 5263 case 14: /* Add Immediate */ 5264 case 15: /* Add Immediate Shifted */ 5265 record_full_arch_list_add_reg (regcache, 5266 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5267 break; 5268 5269 case 16: /* Branch Conditional */ 5270 if ((PPC_BO (insn) & 0x4) == 0) 5271 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 5272 /* FALL-THROUGH */ 5273 case 18: /* Branch */ 5274 if (PPC_LK (insn)) 5275 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 5276 break; 5277 5278 case 19: 5279 if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0) 5280 return -1; 5281 break; 5282 5283 case 20: /* Rotate Left Word Immediate then Mask Insert */ 5284 case 21: /* Rotate Left Word Immediate then AND with Mask */ 5285 case 23: /* Rotate Left Word then AND with Mask */ 5286 case 30: /* Rotate Left Doubleword Immediate then Clear Left */ 5287 /* Rotate Left Doubleword Immediate then Clear Right */ 5288 /* Rotate Left Doubleword Immediate then Clear */ 5289 /* Rotate Left Doubleword then Clear Left */ 5290 /* Rotate Left Doubleword then Clear Right */ 5291 /* Rotate Left Doubleword Immediate then Mask Insert */ 5292 if (PPC_RC (insn)) 5293 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5294 record_full_arch_list_add_reg (regcache, 5295 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5296 break; 5297 5298 case 28: /* AND Immediate */ 5299 case 29: /* AND Immediate Shifted */ 5300 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5301 /* FALL-THROUGH */ 5302 case 24: /* OR Immediate */ 5303 case 25: /* OR Immediate Shifted */ 5304 case 26: /* XOR Immediate */ 5305 case 27: /* XOR Immediate Shifted */ 5306 record_full_arch_list_add_reg (regcache, 5307 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5308 break; 5309 5310 case 31: 5311 if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0) 5312 return -1; 5313 break; 5314 5315 case 33: /* Load Word and Zero with Update */ 5316 case 35: /* Load Byte and Zero with Update */ 5317 case 41: /* Load Halfword and Zero with Update */ 5318 case 43: /* Load Halfword Algebraic with Update */ 5319 record_full_arch_list_add_reg (regcache, 5320 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5321 /* FALL-THROUGH */ 5322 case 32: /* Load Word and Zero */ 5323 case 34: /* Load Byte and Zero */ 5324 case 40: /* Load Halfword and Zero */ 5325 case 42: /* Load Halfword Algebraic */ 5326 record_full_arch_list_add_reg (regcache, 5327 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5328 break; 5329 5330 case 46: /* Load Multiple Word */ 5331 for (i = PPC_RT (insn); i < 32; i++) 5332 record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i); 5333 break; 5334 5335 case 56: /* Load Quadword */ 5336 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); 5337 record_full_arch_list_add_reg (regcache, tmp); 5338 record_full_arch_list_add_reg (regcache, tmp + 1); 5339 break; 5340 5341 case 49: /* Load Floating-Point Single with Update */ 5342 case 51: /* Load Floating-Point Double with Update */ 5343 record_full_arch_list_add_reg (regcache, 5344 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5345 /* FALL-THROUGH */ 5346 case 48: /* Load Floating-Point Single */ 5347 case 50: /* Load Floating-Point Double */ 5348 record_full_arch_list_add_reg (regcache, 5349 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5350 break; 5351 5352 case 47: /* Store Multiple Word */ 5353 { 5354 ULONGEST addr = 0; 5355 5356 if (PPC_RA (insn) != 0) 5357 regcache_raw_read_unsigned (regcache, 5358 tdep->ppc_gp0_regnum + PPC_RA (insn), 5359 &addr); 5360 5361 addr += PPC_D (insn); 5362 record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn))); 5363 } 5364 break; 5365 5366 case 37: /* Store Word with Update */ 5367 case 39: /* Store Byte with Update */ 5368 case 45: /* Store Halfword with Update */ 5369 case 53: /* Store Floating-Point Single with Update */ 5370 case 55: /* Store Floating-Point Double with Update */ 5371 record_full_arch_list_add_reg (regcache, 5372 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5373 /* FALL-THROUGH */ 5374 case 36: /* Store Word */ 5375 case 38: /* Store Byte */ 5376 case 44: /* Store Halfword */ 5377 case 52: /* Store Floating-Point Single */ 5378 case 54: /* Store Floating-Point Double */ 5379 { 5380 ULONGEST addr = 0; 5381 int size = -1; 5382 5383 if (PPC_RA (insn) != 0) 5384 regcache_raw_read_unsigned (regcache, 5385 tdep->ppc_gp0_regnum + PPC_RA (insn), 5386 &addr); 5387 addr += PPC_D (insn); 5388 5389 if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53) 5390 size = 4; 5391 else if (op6 == 54 || op6 == 55) 5392 size = 8; 5393 else if (op6 == 44 || op6 == 45) 5394 size = 2; 5395 else if (op6 == 38 || op6 == 39) 5396 size = 1; 5397 else 5398 gdb_assert (0); 5399 5400 record_full_arch_list_add_mem (addr, size); 5401 } 5402 break; 5403 5404 case 57: /* Load Floating-Point Double Pair */ 5405 if (PPC_FIELD (insn, 30, 2) != 0) 5406 goto UNKNOWN_OP; 5407 tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); 5408 record_full_arch_list_add_reg (regcache, tmp); 5409 record_full_arch_list_add_reg (regcache, tmp + 1); 5410 break; 5411 5412 case 58: /* Load Doubleword */ 5413 /* Load Doubleword with Update */ 5414 /* Load Word Algebraic */ 5415 if (PPC_FIELD (insn, 30, 2) > 2) 5416 goto UNKNOWN_OP; 5417 5418 record_full_arch_list_add_reg (regcache, 5419 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5420 if (PPC_BIT (insn, 31)) 5421 record_full_arch_list_add_reg (regcache, 5422 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5423 break; 5424 5425 case 59: 5426 if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0) 5427 return -1; 5428 break; 5429 5430 case 60: 5431 if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0) 5432 return -1; 5433 break; 5434 5435 case 61: /* Store Floating-Point Double Pair */ 5436 case 62: /* Store Doubleword */ 5437 /* Store Doubleword with Update */ 5438 /* Store Quadword with Update */ 5439 { 5440 ULONGEST addr = 0; 5441 int size; 5442 int sub2 = PPC_FIELD (insn, 30, 2); 5443 5444 if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2)) 5445 goto UNKNOWN_OP; 5446 5447 if (PPC_RA (insn) != 0) 5448 regcache_raw_read_unsigned (regcache, 5449 tdep->ppc_gp0_regnum + PPC_RA (insn), 5450 &addr); 5451 5452 size = ((op6 == 61) || sub2 == 2) ? 16 : 8; 5453 5454 addr += PPC_DS (insn) << 2; 5455 record_full_arch_list_add_mem (addr, size); 5456 5457 if (op6 == 62 && sub2 == 1) 5458 record_full_arch_list_add_reg (regcache, 5459 tdep->ppc_gp0_regnum + 5460 PPC_RA (insn)); 5461 5462 break; 5463 } 5464 5465 case 63: 5466 if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0) 5467 return -1; 5468 break; 5469 5470 default: 5471 UNKNOWN_OP: 5472 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x " 5473 "at %s, %d.\n", insn, paddress (gdbarch, addr), op6); 5474 return -1; 5475 } 5476 5477 if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) 5478 return -1; 5479 if (record_full_arch_list_add_end ()) 5480 return -1; 5481 return 0; 5482 } 5483 5484 /* Initialize the current architecture based on INFO. If possible, re-use an 5485 architecture from ARCHES, which is a list of architectures already created 5486 during this debugging session. 5487 5488 Called e.g. at program startup, when reading a core file, and when reading 5489 a binary file. */ 5490 5491 static struct gdbarch * 5492 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 5493 { 5494 struct gdbarch *gdbarch; 5495 struct gdbarch_tdep *tdep; 5496 int wordsize, from_xcoff_exec, from_elf_exec; 5497 enum bfd_architecture arch; 5498 unsigned long mach; 5499 bfd abfd; 5500 enum auto_boolean soft_float_flag = powerpc_soft_float_global; 5501 int soft_float; 5502 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; 5503 enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; 5504 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0, 5505 have_vsx = 0; 5506 int tdesc_wordsize = -1; 5507 const struct target_desc *tdesc = info.target_desc; 5508 struct tdesc_arch_data *tdesc_data = NULL; 5509 int num_pseudoregs = 0; 5510 int cur_reg; 5511 5512 /* INFO may refer to a binary that is not of the PowerPC architecture, 5513 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system. 5514 In this case, we must not attempt to infer properties of the (PowerPC 5515 side) of the target system from properties of that executable. Trust 5516 the target description instead. */ 5517 if (info.abfd 5518 && bfd_get_arch (info.abfd) != bfd_arch_powerpc 5519 && bfd_get_arch (info.abfd) != bfd_arch_rs6000) 5520 info.abfd = NULL; 5521 5522 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 5523 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 5524 5525 from_elf_exec = info.abfd && info.abfd->format == bfd_object && 5526 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 5527 5528 /* Check word size. If INFO is from a binary file, infer it from 5529 that, else choose a likely default. */ 5530 if (from_xcoff_exec) 5531 { 5532 if (bfd_xcoff_is_xcoff64 (info.abfd)) 5533 wordsize = 8; 5534 else 5535 wordsize = 4; 5536 } 5537 else if (from_elf_exec) 5538 { 5539 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 5540 wordsize = 8; 5541 else 5542 wordsize = 4; 5543 } 5544 else if (tdesc_has_registers (tdesc)) 5545 wordsize = -1; 5546 else 5547 { 5548 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 5549 wordsize = (info.bfd_arch_info->bits_per_word 5550 / info.bfd_arch_info->bits_per_byte); 5551 else 5552 wordsize = 4; 5553 } 5554 5555 /* Get the architecture and machine from the BFD. */ 5556 arch = info.bfd_arch_info->arch; 5557 mach = info.bfd_arch_info->mach; 5558 5559 /* For e500 executables, the apuinfo section is of help here. Such 5560 section contains the identifier and revision number of each 5561 Application-specific Processing Unit that is present on the 5562 chip. The content of the section is determined by the assembler 5563 which looks at each instruction and determines which unit (and 5564 which version of it) can execute it. Grovel through the section 5565 looking for relevant e500 APUs. */ 5566 5567 if (bfd_uses_spe_extensions (info.abfd)) 5568 { 5569 arch = info.bfd_arch_info->arch; 5570 mach = bfd_mach_ppc_e500; 5571 bfd_default_set_arch_mach (&abfd, arch, mach); 5572 info.bfd_arch_info = bfd_get_arch_info (&abfd); 5573 } 5574 5575 /* Find a default target description which describes our register 5576 layout, if we do not already have one. */ 5577 if (! tdesc_has_registers (tdesc)) 5578 { 5579 const struct variant *v; 5580 5581 /* Choose variant. */ 5582 v = find_variant_by_arch (arch, mach); 5583 if (!v) 5584 return NULL; 5585 5586 tdesc = *v->tdesc; 5587 } 5588 5589 gdb_assert (tdesc_has_registers (tdesc)); 5590 5591 /* Check any target description for validity. */ 5592 if (tdesc_has_registers (tdesc)) 5593 { 5594 static const char *const gprs[] = { 5595 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5596 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5597 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5598 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5599 }; 5600 const struct tdesc_feature *feature; 5601 int i, valid_p; 5602 static const char *const msr_names[] = { "msr", "ps" }; 5603 static const char *const cr_names[] = { "cr", "cnd" }; 5604 static const char *const ctr_names[] = { "ctr", "cnt" }; 5605 5606 feature = tdesc_find_feature (tdesc, 5607 "org.gnu.gdb.power.core"); 5608 if (feature == NULL) 5609 return NULL; 5610 5611 tdesc_data = tdesc_data_alloc (); 5612 5613 valid_p = 1; 5614 for (i = 0; i < ppc_num_gprs; i++) 5615 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]); 5616 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM, 5617 "pc"); 5618 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM, 5619 "lr"); 5620 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM, 5621 "xer"); 5622 5623 /* Allow alternate names for these registers, to accomodate GDB's 5624 historic naming. */ 5625 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, 5626 PPC_MSR_REGNUM, msr_names); 5627 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, 5628 PPC_CR_REGNUM, cr_names); 5629 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data, 5630 PPC_CTR_REGNUM, ctr_names); 5631 5632 if (!valid_p) 5633 { 5634 tdesc_data_cleanup (tdesc_data); 5635 return NULL; 5636 } 5637 5638 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM, 5639 "mq"); 5640 5641 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8; 5642 if (wordsize == -1) 5643 wordsize = tdesc_wordsize; 5644 5645 feature = tdesc_find_feature (tdesc, 5646 "org.gnu.gdb.power.fpu"); 5647 if (feature != NULL) 5648 { 5649 static const char *const fprs[] = { 5650 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 5651 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 5652 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 5653 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 5654 }; 5655 valid_p = 1; 5656 for (i = 0; i < ppc_num_fprs; i++) 5657 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5658 PPC_F0_REGNUM + i, fprs[i]); 5659 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5660 PPC_FPSCR_REGNUM, "fpscr"); 5661 5662 if (!valid_p) 5663 { 5664 tdesc_data_cleanup (tdesc_data); 5665 return NULL; 5666 } 5667 have_fpu = 1; 5668 } 5669 else 5670 have_fpu = 0; 5671 5672 /* The DFP pseudo-registers will be available when there are floating 5673 point registers. */ 5674 have_dfp = have_fpu; 5675 5676 feature = tdesc_find_feature (tdesc, 5677 "org.gnu.gdb.power.altivec"); 5678 if (feature != NULL) 5679 { 5680 static const char *const vector_regs[] = { 5681 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", 5682 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", 5683 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", 5684 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" 5685 }; 5686 5687 valid_p = 1; 5688 for (i = 0; i < ppc_num_gprs; i++) 5689 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5690 PPC_VR0_REGNUM + i, 5691 vector_regs[i]); 5692 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5693 PPC_VSCR_REGNUM, "vscr"); 5694 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5695 PPC_VRSAVE_REGNUM, "vrsave"); 5696 5697 if (have_spe || !valid_p) 5698 { 5699 tdesc_data_cleanup (tdesc_data); 5700 return NULL; 5701 } 5702 have_altivec = 1; 5703 } 5704 else 5705 have_altivec = 0; 5706 5707 /* Check for POWER7 VSX registers support. */ 5708 feature = tdesc_find_feature (tdesc, 5709 "org.gnu.gdb.power.vsx"); 5710 5711 if (feature != NULL) 5712 { 5713 static const char *const vsx_regs[] = { 5714 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", 5715 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", 5716 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", 5717 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", 5718 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", 5719 "vs30h", "vs31h" 5720 }; 5721 5722 valid_p = 1; 5723 5724 for (i = 0; i < ppc_num_vshrs; i++) 5725 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5726 PPC_VSR0_UPPER_REGNUM + i, 5727 vsx_regs[i]); 5728 if (!valid_p) 5729 { 5730 tdesc_data_cleanup (tdesc_data); 5731 return NULL; 5732 } 5733 5734 have_vsx = 1; 5735 } 5736 else 5737 have_vsx = 0; 5738 5739 /* On machines supporting the SPE APU, the general-purpose registers 5740 are 64 bits long. There are SIMD vector instructions to treat them 5741 as pairs of floats, but the rest of the instruction set treats them 5742 as 32-bit registers, and only operates on their lower halves. 5743 5744 In the GDB regcache, we treat their high and low halves as separate 5745 registers. The low halves we present as the general-purpose 5746 registers, and then we have pseudo-registers that stitch together 5747 the upper and lower halves and present them as pseudo-registers. 5748 5749 Thus, the target description is expected to supply the upper 5750 halves separately. */ 5751 5752 feature = tdesc_find_feature (tdesc, 5753 "org.gnu.gdb.power.spe"); 5754 if (feature != NULL) 5755 { 5756 static const char *const upper_spe[] = { 5757 "ev0h", "ev1h", "ev2h", "ev3h", 5758 "ev4h", "ev5h", "ev6h", "ev7h", 5759 "ev8h", "ev9h", "ev10h", "ev11h", 5760 "ev12h", "ev13h", "ev14h", "ev15h", 5761 "ev16h", "ev17h", "ev18h", "ev19h", 5762 "ev20h", "ev21h", "ev22h", "ev23h", 5763 "ev24h", "ev25h", "ev26h", "ev27h", 5764 "ev28h", "ev29h", "ev30h", "ev31h" 5765 }; 5766 5767 valid_p = 1; 5768 for (i = 0; i < ppc_num_gprs; i++) 5769 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5770 PPC_SPE_UPPER_GP0_REGNUM + i, 5771 upper_spe[i]); 5772 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5773 PPC_SPE_ACC_REGNUM, "acc"); 5774 valid_p &= tdesc_numbered_register (feature, tdesc_data, 5775 PPC_SPE_FSCR_REGNUM, "spefscr"); 5776 5777 if (have_mq || have_fpu || !valid_p) 5778 { 5779 tdesc_data_cleanup (tdesc_data); 5780 return NULL; 5781 } 5782 have_spe = 1; 5783 } 5784 else 5785 have_spe = 0; 5786 } 5787 5788 /* If we have a 64-bit binary on a 32-bit target, complain. Also 5789 complain for a 32-bit binary on a 64-bit target; we do not yet 5790 support that. For instance, the 32-bit ABI routines expect 5791 32-bit GPRs. 5792 5793 As long as there isn't an explicit target description, we'll 5794 choose one based on the BFD architecture and get a word size 5795 matching the binary (probably powerpc:common or 5796 powerpc:common64). So there is only trouble if a 64-bit target 5797 supplies a 64-bit description while debugging a 32-bit 5798 binary. */ 5799 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) 5800 { 5801 tdesc_data_cleanup (tdesc_data); 5802 return NULL; 5803 } 5804 5805 #ifdef HAVE_ELF 5806 if (from_elf_exec) 5807 { 5808 switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) 5809 { 5810 case 1: 5811 elf_abi = POWERPC_ELF_V1; 5812 break; 5813 case 2: 5814 elf_abi = POWERPC_ELF_V2; 5815 break; 5816 default: 5817 break; 5818 } 5819 } 5820 5821 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) 5822 { 5823 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 5824 Tag_GNU_Power_ABI_FP)) 5825 { 5826 case 1: 5827 soft_float_flag = AUTO_BOOLEAN_FALSE; 5828 break; 5829 case 2: 5830 soft_float_flag = AUTO_BOOLEAN_TRUE; 5831 break; 5832 default: 5833 break; 5834 } 5835 } 5836 5837 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) 5838 { 5839 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 5840 Tag_GNU_Power_ABI_Vector)) 5841 { 5842 case 1: 5843 vector_abi = POWERPC_VEC_GENERIC; 5844 break; 5845 case 2: 5846 vector_abi = POWERPC_VEC_ALTIVEC; 5847 break; 5848 case 3: 5849 vector_abi = POWERPC_VEC_SPE; 5850 break; 5851 default: 5852 break; 5853 } 5854 } 5855 #endif 5856 5857 /* At this point, the only supported ELF-based 64-bit little-endian 5858 operating system is GNU/Linux, and this uses the ELFv2 ABI by 5859 default. All other supported ELF-based operating systems use the 5860 ELFv1 ABI by default. Therefore, if the ABI marker is missing, 5861 e.g. because we run a legacy binary, or have attached to a process 5862 and have not found any associated binary file, set the default 5863 according to this heuristic. */ 5864 if (elf_abi == POWERPC_ELF_AUTO) 5865 { 5866 if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) 5867 elf_abi = POWERPC_ELF_V2; 5868 else 5869 elf_abi = POWERPC_ELF_V1; 5870 } 5871 5872 if (soft_float_flag == AUTO_BOOLEAN_TRUE) 5873 soft_float = 1; 5874 else if (soft_float_flag == AUTO_BOOLEAN_FALSE) 5875 soft_float = 0; 5876 else 5877 soft_float = !have_fpu; 5878 5879 /* If we have a hard float binary or setting but no floating point 5880 registers, downgrade to soft float anyway. We're still somewhat 5881 useful in this scenario. */ 5882 if (!soft_float && !have_fpu) 5883 soft_float = 1; 5884 5885 /* Similarly for vector registers. */ 5886 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) 5887 vector_abi = POWERPC_VEC_GENERIC; 5888 5889 if (vector_abi == POWERPC_VEC_SPE && !have_spe) 5890 vector_abi = POWERPC_VEC_GENERIC; 5891 5892 if (vector_abi == POWERPC_VEC_AUTO) 5893 { 5894 if (have_altivec) 5895 vector_abi = POWERPC_VEC_ALTIVEC; 5896 else if (have_spe) 5897 vector_abi = POWERPC_VEC_SPE; 5898 else 5899 vector_abi = POWERPC_VEC_GENERIC; 5900 } 5901 5902 /* Do not limit the vector ABI based on available hardware, since we 5903 do not yet know what hardware we'll decide we have. Yuck! FIXME! */ 5904 5905 /* Find a candidate among extant architectures. */ 5906 for (arches = gdbarch_list_lookup_by_info (arches, &info); 5907 arches != NULL; 5908 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 5909 { 5910 /* Word size in the various PowerPC bfd_arch_info structs isn't 5911 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 5912 separate word size check. */ 5913 tdep = gdbarch_tdep (arches->gdbarch); 5914 if (tdep && tdep->elf_abi != elf_abi) 5915 continue; 5916 if (tdep && tdep->soft_float != soft_float) 5917 continue; 5918 if (tdep && tdep->vector_abi != vector_abi) 5919 continue; 5920 if (tdep && tdep->wordsize == wordsize) 5921 { 5922 if (tdesc_data != NULL) 5923 tdesc_data_cleanup (tdesc_data); 5924 return arches->gdbarch; 5925 } 5926 } 5927 5928 /* None found, create a new architecture from INFO, whose bfd_arch_info 5929 validity depends on the source: 5930 - executable useless 5931 - rs6000_host_arch() good 5932 - core file good 5933 - "set arch" trust blindly 5934 - GDB startup useless but harmless */ 5935 5936 tdep = XCNEW (struct gdbarch_tdep); 5937 tdep->wordsize = wordsize; 5938 tdep->elf_abi = elf_abi; 5939 tdep->soft_float = soft_float; 5940 tdep->vector_abi = vector_abi; 5941 5942 gdbarch = gdbarch_alloc (&info, tdep); 5943 5944 tdep->ppc_gp0_regnum = PPC_R0_REGNUM; 5945 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; 5946 tdep->ppc_ps_regnum = PPC_MSR_REGNUM; 5947 tdep->ppc_cr_regnum = PPC_CR_REGNUM; 5948 tdep->ppc_lr_regnum = PPC_LR_REGNUM; 5949 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; 5950 tdep->ppc_xer_regnum = PPC_XER_REGNUM; 5951 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; 5952 5953 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; 5954 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; 5955 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; 5956 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; 5957 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; 5958 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; 5959 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; 5960 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; 5961 5962 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); 5963 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); 5964 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1); 5965 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); 5966 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); 5967 5968 /* The XML specification for PowerPC sensibly calls the MSR "msr". 5969 GDB traditionally called it "ps", though, so let GDB add an 5970 alias. */ 5971 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); 5972 5973 if (wordsize == 8) 5974 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 5975 else 5976 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 5977 5978 /* Set lr_frame_offset. */ 5979 if (wordsize == 8) 5980 tdep->lr_frame_offset = 16; 5981 else 5982 tdep->lr_frame_offset = 4; 5983 5984 if (have_spe || have_dfp || have_vsx) 5985 { 5986 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); 5987 set_gdbarch_pseudo_register_write (gdbarch, 5988 rs6000_pseudo_register_write); 5989 set_gdbarch_ax_pseudo_register_collect (gdbarch, 5990 rs6000_ax_pseudo_register_collect); 5991 } 5992 5993 set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address); 5994 5995 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 5996 5997 /* Select instruction printer. */ 5998 if (arch == bfd_arch_rs6000) 5999 set_gdbarch_print_insn (gdbarch, print_insn_rs6000); 6000 else 6001 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); 6002 6003 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); 6004 6005 if (have_spe) 6006 num_pseudoregs += 32; 6007 if (have_dfp) 6008 num_pseudoregs += 16; 6009 if (have_vsx) 6010 /* Include both VSX and Extended FP registers. */ 6011 num_pseudoregs += 96; 6012 6013 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); 6014 6015 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 6016 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 6017 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 6018 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 6019 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 6020 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 6021 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 6022 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 6023 set_gdbarch_char_signed (gdbarch, 0); 6024 6025 set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 6026 if (wordsize == 8) 6027 /* PPC64 SYSV. */ 6028 set_gdbarch_frame_red_zone_size (gdbarch, 288); 6029 6030 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); 6031 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); 6032 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); 6033 6034 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 6035 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); 6036 6037 if (wordsize == 4) 6038 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 6039 else if (wordsize == 8) 6040 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 6041 6042 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 6043 set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p); 6044 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); 6045 6046 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 6047 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); 6048 6049 /* The value of symbols of type N_SO and N_FUN maybe null when 6050 it shouldn't be. */ 6051 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); 6052 6053 /* Handles single stepping of atomic sequences. */ 6054 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); 6055 6056 /* Not sure on this. FIXMEmgo */ 6057 set_gdbarch_frame_args_skip (gdbarch, 8); 6058 6059 /* Helpers for function argument information. */ 6060 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 6061 6062 /* Trampoline. */ 6063 set_gdbarch_in_solib_return_trampoline 6064 (gdbarch, rs6000_in_solib_return_trampoline); 6065 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); 6066 6067 /* Hook in the DWARF CFI frame unwinder. */ 6068 dwarf2_append_unwinders (gdbarch); 6069 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); 6070 6071 /* Frame handling. */ 6072 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); 6073 6074 /* Setup displaced stepping. */ 6075 set_gdbarch_displaced_step_copy_insn (gdbarch, 6076 ppc_displaced_step_copy_insn); 6077 set_gdbarch_displaced_step_hw_singlestep (gdbarch, 6078 ppc_displaced_step_hw_singlestep); 6079 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); 6080 set_gdbarch_displaced_step_free_closure (gdbarch, 6081 simple_displaced_step_free_closure); 6082 set_gdbarch_displaced_step_location (gdbarch, 6083 displaced_step_at_entry_point); 6084 6085 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE); 6086 6087 /* Hook in ABI-specific overrides, if they have been registered. */ 6088 info.target_desc = tdesc; 6089 info.tdep_info = tdesc_data; 6090 gdbarch_init_osabi (info, gdbarch); 6091 6092 switch (info.osabi) 6093 { 6094 case GDB_OSABI_LINUX: 6095 case GDB_OSABI_NETBSD_AOUT: 6096 case GDB_OSABI_NETBSD_ELF: 6097 case GDB_OSABI_UNKNOWN: 6098 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 6099 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); 6100 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); 6101 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); 6102 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 6103 break; 6104 default: 6105 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 6106 6107 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 6108 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); 6109 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); 6110 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id); 6111 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 6112 } 6113 6114 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); 6115 set_tdesc_pseudo_register_reggroup_p (gdbarch, 6116 rs6000_pseudo_register_reggroup_p); 6117 tdesc_use_registers (gdbarch, tdesc, tdesc_data); 6118 6119 /* Override the normal target description method to make the SPE upper 6120 halves anonymous. */ 6121 set_gdbarch_register_name (gdbarch, rs6000_register_name); 6122 6123 /* Choose register numbers for all supported pseudo-registers. */ 6124 tdep->ppc_ev0_regnum = -1; 6125 tdep->ppc_dl0_regnum = -1; 6126 tdep->ppc_vsr0_regnum = -1; 6127 tdep->ppc_efpr0_regnum = -1; 6128 6129 cur_reg = gdbarch_num_regs (gdbarch); 6130 6131 if (have_spe) 6132 { 6133 tdep->ppc_ev0_regnum = cur_reg; 6134 cur_reg += 32; 6135 } 6136 if (have_dfp) 6137 { 6138 tdep->ppc_dl0_regnum = cur_reg; 6139 cur_reg += 16; 6140 } 6141 if (have_vsx) 6142 { 6143 tdep->ppc_vsr0_regnum = cur_reg; 6144 cur_reg += 64; 6145 tdep->ppc_efpr0_regnum = cur_reg; 6146 cur_reg += 32; 6147 } 6148 6149 gdb_assert (gdbarch_num_regs (gdbarch) 6150 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg); 6151 6152 /* Register the ravenscar_arch_ops. */ 6153 if (mach == bfd_mach_ppc_e500) 6154 register_e500_ravenscar_ops (gdbarch); 6155 else 6156 register_ppc_ravenscar_ops (gdbarch); 6157 6158 return gdbarch; 6159 } 6160 6161 static void 6162 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 6163 { 6164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 6165 6166 if (tdep == NULL) 6167 return; 6168 6169 /* FIXME: Dump gdbarch_tdep. */ 6170 } 6171 6172 /* PowerPC-specific commands. */ 6173 6174 static void 6175 set_powerpc_command (char *args, int from_tty) 6176 { 6177 printf_unfiltered (_("\ 6178 \"set powerpc\" must be followed by an appropriate subcommand.\n")); 6179 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout); 6180 } 6181 6182 static void 6183 show_powerpc_command (char *args, int from_tty) 6184 { 6185 cmd_show_list (showpowerpccmdlist, from_tty, ""); 6186 } 6187 6188 static void 6189 powerpc_set_soft_float (char *args, int from_tty, 6190 struct cmd_list_element *c) 6191 { 6192 struct gdbarch_info info; 6193 6194 /* Update the architecture. */ 6195 gdbarch_info_init (&info); 6196 if (!gdbarch_update_p (info)) 6197 internal_error (__FILE__, __LINE__, _("could not update architecture")); 6198 } 6199 6200 static void 6201 powerpc_set_vector_abi (char *args, int from_tty, 6202 struct cmd_list_element *c) 6203 { 6204 struct gdbarch_info info; 6205 int vector_abi; 6206 6207 for (vector_abi = POWERPC_VEC_AUTO; 6208 vector_abi != POWERPC_VEC_LAST; 6209 vector_abi++) 6210 if (strcmp (powerpc_vector_abi_string, 6211 powerpc_vector_strings[vector_abi]) == 0) 6212 { 6213 powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi; 6214 break; 6215 } 6216 6217 if (vector_abi == POWERPC_VEC_LAST) 6218 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."), 6219 powerpc_vector_abi_string); 6220 6221 /* Update the architecture. */ 6222 gdbarch_info_init (&info); 6223 if (!gdbarch_update_p (info)) 6224 internal_error (__FILE__, __LINE__, _("could not update architecture")); 6225 } 6226 6227 /* Show the current setting of the exact watchpoints flag. */ 6228 6229 static void 6230 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, 6231 struct cmd_list_element *c, 6232 const char *value) 6233 { 6234 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value); 6235 } 6236 6237 /* Read a PPC instruction from memory. */ 6238 6239 static unsigned int 6240 read_insn (struct frame_info *frame, CORE_ADDR pc) 6241 { 6242 struct gdbarch *gdbarch = get_frame_arch (frame); 6243 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 6244 6245 return read_memory_unsigned_integer (pc, 4, byte_order); 6246 } 6247 6248 /* Return non-zero if the instructions at PC match the series 6249 described in PATTERN, or zero otherwise. PATTERN is an array of 6250 'struct ppc_insn_pattern' objects, terminated by an entry whose 6251 mask is zero. 6252 6253 When the match is successful, fill INSN[i] with what PATTERN[i] 6254 matched. If PATTERN[i] is optional, and the instruction wasn't 6255 present, set INSN[i] to 0 (which is not a valid PPC instruction). 6256 INSN should have as many elements as PATTERN. Note that, if 6257 PATTERN contains optional instructions which aren't present in 6258 memory, then INSN will have holes, so INSN[i] isn't necessarily the 6259 i'th instruction in memory. */ 6260 6261 int 6262 ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc, 6263 struct ppc_insn_pattern *pattern, 6264 unsigned int *insns) 6265 { 6266 int i; 6267 unsigned int insn; 6268 6269 for (i = 0, insn = 0; pattern[i].mask; i++) 6270 { 6271 if (insn == 0) 6272 insn = read_insn (frame, pc); 6273 insns[i] = 0; 6274 if ((insn & pattern[i].mask) == pattern[i].data) 6275 { 6276 insns[i] = insn; 6277 pc += 4; 6278 insn = 0; 6279 } 6280 else if (!pattern[i].optional) 6281 return 0; 6282 } 6283 6284 return 1; 6285 } 6286 6287 /* Return the 'd' field of the d-form instruction INSN, properly 6288 sign-extended. */ 6289 6290 CORE_ADDR 6291 ppc_insn_d_field (unsigned int insn) 6292 { 6293 return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); 6294 } 6295 6296 /* Return the 'ds' field of the ds-form instruction INSN, with the two 6297 zero bits concatenated at the right, and properly 6298 sign-extended. */ 6299 6300 CORE_ADDR 6301 ppc_insn_ds_field (unsigned int insn) 6302 { 6303 return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); 6304 } 6305 6306 /* Initialization code. */ 6307 6308 /* -Wmissing-prototypes */ 6309 extern initialize_file_ftype _initialize_rs6000_tdep; 6310 6311 void 6312 _initialize_rs6000_tdep (void) 6313 { 6314 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 6315 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 6316 6317 /* Initialize the standard target descriptions. */ 6318 initialize_tdesc_powerpc_32 (); 6319 initialize_tdesc_powerpc_altivec32 (); 6320 initialize_tdesc_powerpc_vsx32 (); 6321 initialize_tdesc_powerpc_403 (); 6322 initialize_tdesc_powerpc_403gc (); 6323 initialize_tdesc_powerpc_405 (); 6324 initialize_tdesc_powerpc_505 (); 6325 initialize_tdesc_powerpc_601 (); 6326 initialize_tdesc_powerpc_602 (); 6327 initialize_tdesc_powerpc_603 (); 6328 initialize_tdesc_powerpc_604 (); 6329 initialize_tdesc_powerpc_64 (); 6330 initialize_tdesc_powerpc_altivec64 (); 6331 initialize_tdesc_powerpc_vsx64 (); 6332 initialize_tdesc_powerpc_7400 (); 6333 initialize_tdesc_powerpc_750 (); 6334 initialize_tdesc_powerpc_860 (); 6335 initialize_tdesc_powerpc_e500 (); 6336 initialize_tdesc_rs6000 (); 6337 6338 /* Add root prefix command for all "set powerpc"/"show powerpc" 6339 commands. */ 6340 add_prefix_cmd ("powerpc", no_class, set_powerpc_command, 6341 _("Various PowerPC-specific commands."), 6342 &setpowerpccmdlist, "set powerpc ", 0, &setlist); 6343 6344 add_prefix_cmd ("powerpc", no_class, show_powerpc_command, 6345 _("Various PowerPC-specific commands."), 6346 &showpowerpccmdlist, "show powerpc ", 0, &showlist); 6347 6348 /* Add a command to allow the user to force the ABI. */ 6349 add_setshow_auto_boolean_cmd ("soft-float", class_support, 6350 &powerpc_soft_float_global, 6351 _("Set whether to use a soft-float ABI."), 6352 _("Show whether to use a soft-float ABI."), 6353 NULL, 6354 powerpc_set_soft_float, NULL, 6355 &setpowerpccmdlist, &showpowerpccmdlist); 6356 6357 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, 6358 &powerpc_vector_abi_string, 6359 _("Set the vector ABI."), 6360 _("Show the vector ABI."), 6361 NULL, powerpc_set_vector_abi, NULL, 6362 &setpowerpccmdlist, &showpowerpccmdlist); 6363 6364 add_setshow_boolean_cmd ("exact-watchpoints", class_support, 6365 &target_exact_watchpoints, 6366 _("\ 6367 Set whether to use just one debug register for watchpoints on scalars."), 6368 _("\ 6369 Show whether to use just one debug register for watchpoints on scalars."), 6370 _("\ 6371 If true, GDB will use only one debug register when watching a variable of\n\ 6372 scalar type, thus assuming that the variable is accessed through the address\n\ 6373 of its first byte."), 6374 NULL, show_powerpc_exact_watchpoints, 6375 &setpowerpccmdlist, &showpowerpccmdlist); 6376 } 6377