1 /* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 1986-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "frame.h" 22 #include "inferior.h" 23 #include "infrun.h" 24 #include "symtab.h" 25 #include "target.h" 26 #include "gdbcore.h" 27 #include "gdbcmd.h" 28 #include "objfiles.h" 29 #include "arch-utils.h" 30 #include "regcache.h" 31 #include "regset.h" 32 #include "target-float.h" 33 #include "value.h" 34 #include "parser-defs.h" 35 #include "osabi.h" 36 #include "infcall.h" 37 #include "sim-regno.h" 38 #include "gdb/sim-ppc.h" 39 #include "reggroups.h" 40 #include "dwarf2/frame.h" 41 #include "target-descriptions.h" 42 #include "user-regs.h" 43 #include "record-full.h" 44 #include "auxv.h" 45 46 #include "coff/internal.h" /* for libcoff.h */ 47 #include "libcoff.h" /* for xcoff_data */ 48 #include "coff/xcoff.h" 49 #include "libxcoff.h" 50 51 #include "elf-bfd.h" 52 #include "elf/ppc.h" 53 #include "elf/ppc64.h" 54 55 #include "solib-svr4.h" 56 #include "ppc-tdep.h" 57 #include "ppc-ravenscar-thread.h" 58 59 #include "dis-asm.h" 60 61 #include "trad-frame.h" 62 #include "frame-unwind.h" 63 #include "frame-base.h" 64 65 #include "ax.h" 66 #include "ax-gdb.h" 67 #include <algorithm> 68 69 #include "features/rs6000/powerpc-32.c" 70 #include "features/rs6000/powerpc-altivec32.c" 71 #include "features/rs6000/powerpc-vsx32.c" 72 #include "features/rs6000/powerpc-403.c" 73 #include "features/rs6000/powerpc-403gc.c" 74 #include "features/rs6000/powerpc-405.c" 75 #include "features/rs6000/powerpc-505.c" 76 #include "features/rs6000/powerpc-601.c" 77 #include "features/rs6000/powerpc-602.c" 78 #include "features/rs6000/powerpc-603.c" 79 #include "features/rs6000/powerpc-604.c" 80 #include "features/rs6000/powerpc-64.c" 81 #include "features/rs6000/powerpc-altivec64.c" 82 #include "features/rs6000/powerpc-vsx64.c" 83 #include "features/rs6000/powerpc-7400.c" 84 #include "features/rs6000/powerpc-750.c" 85 #include "features/rs6000/powerpc-860.c" 86 #include "features/rs6000/powerpc-e500.c" 87 #include "features/rs6000/rs6000.c" 88 89 /* Determine if regnum is an SPE pseudo-register. */ 90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \ 91 && (regnum) >= (tdep)->ppc_ev0_regnum \ 92 && (regnum) < (tdep)->ppc_ev0_regnum + 32) 93 94 /* Determine if regnum is a decimal float pseudo-register. */ 95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \ 96 && (regnum) >= (tdep)->ppc_dl0_regnum \ 97 && (regnum) < (tdep)->ppc_dl0_regnum + 16) 98 99 /* Determine if regnum is a "vX" alias for the raw "vrX" vector 100 registers. */ 101 #define IS_V_ALIAS_PSEUDOREG(tdep, regnum) (\ 102 (tdep)->ppc_v0_alias_regnum >= 0 \ 103 && (regnum) >= (tdep)->ppc_v0_alias_regnum \ 104 && (regnum) < (tdep)->ppc_v0_alias_regnum + ppc_num_vrs) 105 106 /* Determine if regnum is a POWER7 VSX register. */ 107 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \ 108 && (regnum) >= (tdep)->ppc_vsr0_regnum \ 109 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs) 110 111 /* Determine if regnum is a POWER7 Extended FP register. */ 112 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \ 113 && (regnum) >= (tdep)->ppc_efpr0_regnum \ 114 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs) 115 116 /* Determine if regnum is a checkpointed decimal float 117 pseudo-register. */ 118 #define IS_CDFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cdl0_regnum >= 0 \ 119 && (regnum) >= (tdep)->ppc_cdl0_regnum \ 120 && (regnum) < (tdep)->ppc_cdl0_regnum + 16) 121 122 /* Determine if regnum is a Checkpointed POWER7 VSX register. */ 123 #define IS_CVSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cvsr0_regnum >= 0 \ 124 && (regnum) >= (tdep)->ppc_cvsr0_regnum \ 125 && (regnum) < (tdep)->ppc_cvsr0_regnum + ppc_num_vsrs) 126 127 /* Determine if regnum is a Checkpointed POWER7 Extended FP register. */ 128 #define IS_CEFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_cefpr0_regnum >= 0 \ 129 && (regnum) >= (tdep)->ppc_cefpr0_regnum \ 130 && (regnum) < (tdep)->ppc_cefpr0_regnum + ppc_num_efprs) 131 132 /* Holds the current set of options to be passed to the disassembler. */ 133 static char *powerpc_disassembler_options; 134 135 /* The list of available "set powerpc ..." and "show powerpc ..." 136 commands. */ 137 static struct cmd_list_element *setpowerpccmdlist = NULL; 138 static struct cmd_list_element *showpowerpccmdlist = NULL; 139 140 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO; 141 142 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */ 143 static const char *const powerpc_vector_strings[] = 144 { 145 "auto", 146 "generic", 147 "altivec", 148 "spe", 149 NULL 150 }; 151 152 /* A variable that can be configured by the user. */ 153 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO; 154 static const char *powerpc_vector_abi_string = "auto"; 155 156 /* PowerPC-related per-inferior data. */ 157 158 static const registry<inferior>::key<ppc_inferior_data> ppc_inferior_data_key; 159 160 /* Get the per-inferior PowerPC data for INF. */ 161 162 ppc_inferior_data * 163 get_ppc_per_inferior (inferior *inf) 164 { 165 ppc_inferior_data *per_inf = ppc_inferior_data_key.get (inf); 166 167 if (per_inf == nullptr) 168 per_inf = ppc_inferior_data_key.emplace (inf); 169 170 return per_inf; 171 } 172 173 /* To be used by skip_prologue. */ 174 175 struct rs6000_framedata 176 { 177 int offset; /* total size of frame --- the distance 178 by which we decrement sp to allocate 179 the frame */ 180 int saved_gpr; /* smallest # of saved gpr */ 181 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */ 182 int saved_fpr; /* smallest # of saved fpr */ 183 int saved_vr; /* smallest # of saved vr */ 184 int saved_ev; /* smallest # of saved ev */ 185 int alloca_reg; /* alloca register number (frame ptr) */ 186 char frameless; /* true if frameless functions. */ 187 char nosavedpc; /* true if pc not saved. */ 188 char used_bl; /* true if link register clobbered */ 189 int gpr_offset; /* offset of saved gprs from prev sp */ 190 int fpr_offset; /* offset of saved fprs from prev sp */ 191 int vr_offset; /* offset of saved vrs from prev sp */ 192 int ev_offset; /* offset of saved evs from prev sp */ 193 int lr_offset; /* offset of saved lr */ 194 int lr_register; /* register of saved lr, if trustworthy */ 195 int cr_offset; /* offset of saved cr */ 196 int vrsave_offset; /* offset of saved vrsave register */ 197 }; 198 199 200 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */ 201 int 202 vsx_register_p (struct gdbarch *gdbarch, int regno) 203 { 204 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 205 if (tdep->ppc_vsr0_regnum < 0) 206 return 0; 207 else 208 return (regno >= tdep->ppc_vsr0_upper_regnum && regno 209 <= tdep->ppc_vsr0_upper_regnum + 31); 210 } 211 212 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 213 int 214 altivec_register_p (struct gdbarch *gdbarch, int regno) 215 { 216 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 217 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 218 return 0; 219 else 220 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 221 } 222 223 224 /* Return true if REGNO is an SPE register, false otherwise. */ 225 int 226 spe_register_p (struct gdbarch *gdbarch, int regno) 227 { 228 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 229 230 /* Is it a reference to EV0 -- EV31, and do we have those? */ 231 if (IS_SPE_PSEUDOREG (tdep, regno)) 232 return 1; 233 234 /* Is it a reference to one of the raw upper GPR halves? */ 235 if (tdep->ppc_ev0_upper_regnum >= 0 236 && tdep->ppc_ev0_upper_regnum <= regno 237 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 238 return 1; 239 240 /* Is it a reference to the 64-bit accumulator, and do we have that? */ 241 if (tdep->ppc_acc_regnum >= 0 242 && tdep->ppc_acc_regnum == regno) 243 return 1; 244 245 /* Is it a reference to the SPE floating-point status and control register, 246 and do we have that? */ 247 if (tdep->ppc_spefscr_regnum >= 0 248 && tdep->ppc_spefscr_regnum == regno) 249 return 1; 250 251 return 0; 252 } 253 254 255 /* Return non-zero if the architecture described by GDBARCH has 256 floating-point registers (f0 --- f31 and fpscr). */ 257 int 258 ppc_floating_point_unit_p (struct gdbarch *gdbarch) 259 { 260 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 261 262 return (tdep->ppc_fp0_regnum >= 0 263 && tdep->ppc_fpscr_regnum >= 0); 264 } 265 266 /* Return non-zero if the architecture described by GDBARCH has 267 Altivec registers (vr0 --- vr31, vrsave and vscr). */ 268 int 269 ppc_altivec_support_p (struct gdbarch *gdbarch) 270 { 271 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 272 273 return (tdep->ppc_vr0_regnum >= 0 274 && tdep->ppc_vrsave_regnum >= 0); 275 } 276 277 /* Check that TABLE[GDB_REGNO] is not already initialized, and then 278 set it to SIM_REGNO. 279 280 This is a helper function for init_sim_regno_table, constructing 281 the table mapping GDB register numbers to sim register numbers; we 282 initialize every element in that table to -1 before we start 283 filling it in. */ 284 static void 285 set_sim_regno (int *table, int gdb_regno, int sim_regno) 286 { 287 /* Make sure we don't try to assign any given GDB register a sim 288 register number more than once. */ 289 gdb_assert (table[gdb_regno] == -1); 290 table[gdb_regno] = sim_regno; 291 } 292 293 294 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register 295 numbers to simulator register numbers, based on the values placed 296 in the ARCH->tdep->ppc_foo_regnum members. */ 297 static void 298 init_sim_regno_table (struct gdbarch *arch) 299 { 300 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (arch); 301 int total_regs = gdbarch_num_regs (arch); 302 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); 303 int i; 304 static const char *const segment_regs[] = { 305 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7", 306 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15" 307 }; 308 309 /* Presume that all registers not explicitly mentioned below are 310 unavailable from the sim. */ 311 for (i = 0; i < total_regs; i++) 312 sim_regno[i] = -1; 313 314 /* General-purpose registers. */ 315 for (i = 0; i < ppc_num_gprs; i++) 316 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); 317 318 /* Floating-point registers. */ 319 if (tdep->ppc_fp0_regnum >= 0) 320 for (i = 0; i < ppc_num_fprs; i++) 321 set_sim_regno (sim_regno, 322 tdep->ppc_fp0_regnum + i, 323 sim_ppc_f0_regnum + i); 324 if (tdep->ppc_fpscr_regnum >= 0) 325 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); 326 327 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); 328 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); 329 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); 330 331 /* Segment registers. */ 332 for (i = 0; i < ppc_num_srs; i++) 333 { 334 int gdb_regno; 335 336 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1); 337 if (gdb_regno >= 0) 338 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i); 339 } 340 341 /* Altivec registers. */ 342 if (tdep->ppc_vr0_regnum >= 0) 343 { 344 for (i = 0; i < ppc_num_vrs; i++) 345 set_sim_regno (sim_regno, 346 tdep->ppc_vr0_regnum + i, 347 sim_ppc_vr0_regnum + i); 348 349 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, 350 we can treat this more like the other cases. */ 351 set_sim_regno (sim_regno, 352 tdep->ppc_vr0_regnum + ppc_num_vrs, 353 sim_ppc_vscr_regnum); 354 } 355 /* vsave is a special-purpose register, so the code below handles it. */ 356 357 /* SPE APU (E500) registers. */ 358 if (tdep->ppc_ev0_upper_regnum >= 0) 359 for (i = 0; i < ppc_num_gprs; i++) 360 set_sim_regno (sim_regno, 361 tdep->ppc_ev0_upper_regnum + i, 362 sim_ppc_rh0_regnum + i); 363 if (tdep->ppc_acc_regnum >= 0) 364 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); 365 /* spefscr is a special-purpose register, so the code below handles it. */ 366 367 #ifdef WITH_PPC_SIM 368 /* Now handle all special-purpose registers. Verify that they 369 haven't mistakenly been assigned numbers by any of the above 370 code. */ 371 for (i = 0; i < sim_ppc_num_sprs; i++) 372 { 373 const char *spr_name = sim_spr_register_name (i); 374 int gdb_regno = -1; 375 376 if (spr_name != NULL) 377 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1); 378 379 if (gdb_regno != -1) 380 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i); 381 } 382 #endif 383 384 /* Drop the initialized array into place. */ 385 tdep->sim_regno = sim_regno; 386 } 387 388 389 /* Given a GDB register number REG, return the corresponding SIM 390 register number. */ 391 static int 392 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg) 393 { 394 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 395 int sim_regno; 396 397 if (tdep->sim_regno == NULL) 398 init_sim_regno_table (gdbarch); 399 400 gdb_assert (0 <= reg && reg <= gdbarch_num_cooked_regs (gdbarch)); 401 sim_regno = tdep->sim_regno[reg]; 402 403 if (sim_regno >= 0) 404 return sim_regno; 405 else 406 return LEGACY_SIM_REGNO_IGNORE; 407 } 408 409 410 411 /* Register set support functions. */ 412 413 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. 414 Write the register to REGCACHE. */ 415 416 void 417 ppc_supply_reg (struct regcache *regcache, int regnum, 418 const gdb_byte *regs, size_t offset, int regsize) 419 { 420 if (regnum != -1 && offset != -1) 421 { 422 if (regsize > 4) 423 { 424 struct gdbarch *gdbarch = regcache->arch (); 425 int gdb_regsize = register_size (gdbarch, regnum); 426 if (gdb_regsize < regsize 427 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 428 offset += regsize - gdb_regsize; 429 } 430 regcache->raw_supply (regnum, regs + offset); 431 } 432 } 433 434 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET 435 in a field REGSIZE wide. Zero pad as necessary. */ 436 437 void 438 ppc_collect_reg (const struct regcache *regcache, int regnum, 439 gdb_byte *regs, size_t offset, int regsize) 440 { 441 if (regnum != -1 && offset != -1) 442 { 443 if (regsize > 4) 444 { 445 struct gdbarch *gdbarch = regcache->arch (); 446 int gdb_regsize = register_size (gdbarch, regnum); 447 if (gdb_regsize < regsize) 448 { 449 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 450 { 451 memset (regs + offset, 0, regsize - gdb_regsize); 452 offset += regsize - gdb_regsize; 453 } 454 else 455 memset (regs + offset + regsize - gdb_regsize, 0, 456 regsize - gdb_regsize); 457 } 458 } 459 regcache->raw_collect (regnum, regs + offset); 460 } 461 } 462 463 static int 464 ppc_greg_offset (struct gdbarch *gdbarch, 465 ppc_gdbarch_tdep *tdep, 466 const struct ppc_reg_offsets *offsets, 467 int regnum, 468 int *regsize) 469 { 470 *regsize = offsets->gpr_size; 471 if (regnum >= tdep->ppc_gp0_regnum 472 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) 473 return (offsets->r0_offset 474 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); 475 476 if (regnum == gdbarch_pc_regnum (gdbarch)) 477 return offsets->pc_offset; 478 479 if (regnum == tdep->ppc_ps_regnum) 480 return offsets->ps_offset; 481 482 if (regnum == tdep->ppc_lr_regnum) 483 return offsets->lr_offset; 484 485 if (regnum == tdep->ppc_ctr_regnum) 486 return offsets->ctr_offset; 487 488 *regsize = offsets->xr_size; 489 if (regnum == tdep->ppc_cr_regnum) 490 return offsets->cr_offset; 491 492 if (regnum == tdep->ppc_xer_regnum) 493 return offsets->xer_offset; 494 495 if (regnum == tdep->ppc_mq_regnum) 496 return offsets->mq_offset; 497 498 return -1; 499 } 500 501 static int 502 ppc_fpreg_offset (ppc_gdbarch_tdep *tdep, 503 const struct ppc_reg_offsets *offsets, 504 int regnum) 505 { 506 if (regnum >= tdep->ppc_fp0_regnum 507 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) 508 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; 509 510 if (regnum == tdep->ppc_fpscr_regnum) 511 return offsets->fpscr_offset; 512 513 return -1; 514 } 515 516 /* Supply register REGNUM in the general-purpose register set REGSET 517 from the buffer specified by GREGS and LEN to register cache 518 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 519 520 void 521 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, 522 int regnum, const void *gregs, size_t len) 523 { 524 struct gdbarch *gdbarch = regcache->arch (); 525 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 526 const struct ppc_reg_offsets *offsets 527 = (const struct ppc_reg_offsets *) regset->regmap; 528 size_t offset; 529 int regsize; 530 531 if (regnum == -1) 532 { 533 int i; 534 int gpr_size = offsets->gpr_size; 535 536 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 537 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 538 i++, offset += gpr_size) 539 ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset, 540 gpr_size); 541 542 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), 543 (const gdb_byte *) gregs, offsets->pc_offset, gpr_size); 544 ppc_supply_reg (regcache, tdep->ppc_ps_regnum, 545 (const gdb_byte *) gregs, offsets->ps_offset, gpr_size); 546 ppc_supply_reg (regcache, tdep->ppc_lr_regnum, 547 (const gdb_byte *) gregs, offsets->lr_offset, gpr_size); 548 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, 549 (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size); 550 ppc_supply_reg (regcache, tdep->ppc_cr_regnum, 551 (const gdb_byte *) gregs, offsets->cr_offset, 552 offsets->xr_size); 553 ppc_supply_reg (regcache, tdep->ppc_xer_regnum, 554 (const gdb_byte *) gregs, offsets->xer_offset, 555 offsets->xr_size); 556 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, 557 (const gdb_byte *) gregs, offsets->mq_offset, 558 offsets->xr_size); 559 return; 560 } 561 562 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 563 ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize); 564 } 565 566 /* Supply register REGNUM in the floating-point register set REGSET 567 from the buffer specified by FPREGS and LEN to register cache 568 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 569 570 void 571 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, 572 int regnum, const void *fpregs, size_t len) 573 { 574 struct gdbarch *gdbarch = regcache->arch (); 575 const struct ppc_reg_offsets *offsets; 576 size_t offset; 577 578 if (!ppc_floating_point_unit_p (gdbarch)) 579 return; 580 581 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 582 offsets = (const struct ppc_reg_offsets *) regset->regmap; 583 if (regnum == -1) 584 { 585 int i; 586 587 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 588 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 589 i++, offset += 8) 590 ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8); 591 592 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, 593 (const gdb_byte *) fpregs, offsets->fpscr_offset, 594 offsets->fpscr_size); 595 return; 596 } 597 598 offset = ppc_fpreg_offset (tdep, offsets, regnum); 599 ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset, 600 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 601 } 602 603 /* Collect register REGNUM in the general-purpose register set 604 REGSET from register cache REGCACHE into the buffer specified by 605 GREGS and LEN. If REGNUM is -1, do this for all registers in 606 REGSET. */ 607 608 void 609 ppc_collect_gregset (const struct regset *regset, 610 const struct regcache *regcache, 611 int regnum, void *gregs, size_t len) 612 { 613 struct gdbarch *gdbarch = regcache->arch (); 614 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 615 const struct ppc_reg_offsets *offsets 616 = (const struct ppc_reg_offsets *) regset->regmap; 617 size_t offset; 618 int regsize; 619 620 if (regnum == -1) 621 { 622 int i; 623 int gpr_size = offsets->gpr_size; 624 625 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 626 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 627 i++, offset += gpr_size) 628 ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size); 629 630 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), 631 (gdb_byte *) gregs, offsets->pc_offset, gpr_size); 632 ppc_collect_reg (regcache, tdep->ppc_ps_regnum, 633 (gdb_byte *) gregs, offsets->ps_offset, gpr_size); 634 ppc_collect_reg (regcache, tdep->ppc_lr_regnum, 635 (gdb_byte *) gregs, offsets->lr_offset, gpr_size); 636 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, 637 (gdb_byte *) gregs, offsets->ctr_offset, gpr_size); 638 ppc_collect_reg (regcache, tdep->ppc_cr_regnum, 639 (gdb_byte *) gregs, offsets->cr_offset, 640 offsets->xr_size); 641 ppc_collect_reg (regcache, tdep->ppc_xer_regnum, 642 (gdb_byte *) gregs, offsets->xer_offset, 643 offsets->xr_size); 644 ppc_collect_reg (regcache, tdep->ppc_mq_regnum, 645 (gdb_byte *) gregs, offsets->mq_offset, 646 offsets->xr_size); 647 return; 648 } 649 650 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 651 ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize); 652 } 653 654 /* Collect register REGNUM in the floating-point register set 655 REGSET from register cache REGCACHE into the buffer specified by 656 FPREGS and LEN. If REGNUM is -1, do this for all registers in 657 REGSET. */ 658 659 void 660 ppc_collect_fpregset (const struct regset *regset, 661 const struct regcache *regcache, 662 int regnum, void *fpregs, size_t len) 663 { 664 struct gdbarch *gdbarch = regcache->arch (); 665 const struct ppc_reg_offsets *offsets; 666 size_t offset; 667 668 if (!ppc_floating_point_unit_p (gdbarch)) 669 return; 670 671 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 672 offsets = (const struct ppc_reg_offsets *) regset->regmap; 673 if (regnum == -1) 674 { 675 int i; 676 677 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 678 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 679 i++, offset += 8) 680 ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8); 681 682 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, 683 (gdb_byte *) fpregs, offsets->fpscr_offset, 684 offsets->fpscr_size); 685 return; 686 } 687 688 offset = ppc_fpreg_offset (tdep, offsets, regnum); 689 ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset, 690 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 691 } 692 693 static int 694 insn_changes_sp_or_jumps (unsigned long insn) 695 { 696 int opcode = (insn >> 26) & 0x03f; 697 int sd = (insn >> 21) & 0x01f; 698 int a = (insn >> 16) & 0x01f; 699 int subcode = (insn >> 1) & 0x3ff; 700 701 /* Changes the stack pointer. */ 702 703 /* NOTE: There are many ways to change the value of a given register. 704 The ways below are those used when the register is R1, the SP, 705 in a funtion's epilogue. */ 706 707 if (opcode == 31 && subcode == 444 && a == 1) 708 return 1; /* mr R1,Rn */ 709 if (opcode == 14 && sd == 1) 710 return 1; /* addi R1,Rn,simm */ 711 if (opcode == 58 && sd == 1) 712 return 1; /* ld R1,ds(Rn) */ 713 714 /* Transfers control. */ 715 716 if (opcode == 18) 717 return 1; /* b */ 718 if (opcode == 16) 719 return 1; /* bc */ 720 if (opcode == 19 && subcode == 16) 721 return 1; /* bclr */ 722 if (opcode == 19 && subcode == 528) 723 return 1; /* bcctr */ 724 725 return 0; 726 } 727 728 /* Return true if we are in the function's epilogue, i.e. after the 729 instruction that destroyed the function's stack frame. 730 731 1) scan forward from the point of execution: 732 a) If you find an instruction that modifies the stack pointer 733 or transfers control (except a return), execution is not in 734 an epilogue, return. 735 b) Stop scanning if you find a return instruction or reach the 736 end of the function or reach the hard limit for the size of 737 an epilogue. 738 2) scan backward from the point of execution: 739 a) If you find an instruction that modifies the stack pointer, 740 execution *is* in an epilogue, return. 741 b) Stop scanning if you reach an instruction that transfers 742 control or the beginning of the function or reach the hard 743 limit for the size of an epilogue. */ 744 745 static int 746 rs6000_in_function_epilogue_frame_p (frame_info_ptr curfrm, 747 struct gdbarch *gdbarch, CORE_ADDR pc) 748 { 749 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 750 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 751 bfd_byte insn_buf[PPC_INSN_SIZE]; 752 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; 753 unsigned long insn; 754 755 /* Find the search limits based on function boundaries and hard limit. */ 756 757 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) 758 return 0; 759 760 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 761 if (epilogue_start < func_start) epilogue_start = func_start; 762 763 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 764 if (epilogue_end > func_end) epilogue_end = func_end; 765 766 /* Scan forward until next 'blr'. */ 767 768 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) 769 { 770 if (!safe_frame_unwind_memory (curfrm, scan_pc, 771 {insn_buf, PPC_INSN_SIZE})) 772 return 0; 773 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); 774 if (insn == 0x4e800020) 775 break; 776 /* Assume a bctr is a tail call unless it points strictly within 777 this function. */ 778 if (insn == 0x4e800420) 779 { 780 CORE_ADDR ctr = get_frame_register_unsigned (curfrm, 781 tdep->ppc_ctr_regnum); 782 if (ctr > func_start && ctr < func_end) 783 return 0; 784 else 785 break; 786 } 787 if (insn_changes_sp_or_jumps (insn)) 788 return 0; 789 } 790 791 /* Scan backward until adjustment to stack pointer (R1). */ 792 793 for (scan_pc = pc - PPC_INSN_SIZE; 794 scan_pc >= epilogue_start; 795 scan_pc -= PPC_INSN_SIZE) 796 { 797 if (!safe_frame_unwind_memory (curfrm, scan_pc, 798 {insn_buf, PPC_INSN_SIZE})) 799 return 0; 800 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order); 801 if (insn_changes_sp_or_jumps (insn)) 802 return 1; 803 } 804 805 return 0; 806 } 807 808 /* Implement the stack_frame_destroyed_p gdbarch method. */ 809 810 static int 811 rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 812 { 813 return rs6000_in_function_epilogue_frame_p (get_current_frame (), 814 gdbarch, pc); 815 } 816 817 /* Get the ith function argument for the current function. */ 818 static CORE_ADDR 819 rs6000_fetch_pointer_argument (frame_info_ptr frame, int argi, 820 struct type *type) 821 { 822 return get_frame_register_unsigned (frame, 3 + argi); 823 } 824 825 /* Sequence of bytes for breakpoint instruction. */ 826 827 constexpr gdb_byte big_breakpoint[] = { 0x7f, 0xe0, 0x00, 0x08 }; 828 constexpr gdb_byte little_breakpoint[] = { 0x08, 0x00, 0xe0, 0x7f }; 829 830 typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint) 831 rs6000_breakpoint; 832 833 /* Instruction masks for displaced stepping. */ 834 #define OP_MASK 0xfc000000 835 #define BP_MASK 0xFC0007FE 836 #define B_INSN 0x48000000 837 #define BC_INSN 0x40000000 838 #define BXL_INSN 0x4c000000 839 #define BP_INSN 0x7C000008 840 841 /* Instruction masks used during single-stepping of atomic 842 sequences. */ 843 #define LOAD_AND_RESERVE_MASK 0xfc0007fe 844 #define LWARX_INSTRUCTION 0x7c000028 845 #define LDARX_INSTRUCTION 0x7c0000A8 846 #define LBARX_INSTRUCTION 0x7c000068 847 #define LHARX_INSTRUCTION 0x7c0000e8 848 #define LQARX_INSTRUCTION 0x7c000228 849 #define STORE_CONDITIONAL_MASK 0xfc0007ff 850 #define STWCX_INSTRUCTION 0x7c00012d 851 #define STDCX_INSTRUCTION 0x7c0001ad 852 #define STBCX_INSTRUCTION 0x7c00056d 853 #define STHCX_INSTRUCTION 0x7c0005ad 854 #define STQCX_INSTRUCTION 0x7c00016d 855 856 /* Instruction masks for single-stepping of addpcis/lnia. */ 857 #define ADDPCIS_INSN 0x4c000004 858 #define ADDPCIS_INSN_MASK 0xfc00003e 859 #define ADDPCIS_TARGET_REGISTER 0x03F00000 860 #define ADDPCIS_INSN_REGSHIFT 21 861 862 #define PNOP_MASK 0xfff3ffff 863 #define PNOP_INSN 0x07000000 864 #define R_MASK 0x00100000 865 #define R_ZERO 0x00000000 866 867 /* Check if insn is one of the Load And Reserve instructions used for atomic 868 sequences. */ 869 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \ 870 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \ 871 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \ 872 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \ 873 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION) 874 /* Check if insn is one of the Store Conditional instructions used for atomic 875 sequences. */ 876 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \ 877 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \ 878 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \ 879 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \ 880 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION) 881 882 typedef buf_displaced_step_copy_insn_closure 883 ppc_displaced_step_copy_insn_closure; 884 885 /* We can't displaced step atomic sequences. */ 886 887 static displaced_step_copy_insn_closure_up 888 ppc_displaced_step_copy_insn (struct gdbarch *gdbarch, 889 CORE_ADDR from, CORE_ADDR to, 890 struct regcache *regs) 891 { 892 size_t len = gdbarch_max_insn_length (gdbarch); 893 std::unique_ptr<ppc_displaced_step_copy_insn_closure> closure 894 (new ppc_displaced_step_copy_insn_closure (len)); 895 gdb_byte *buf = closure->buf.data (); 896 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 897 int insn; 898 899 len = target_read (current_inferior()->top_target(), TARGET_OBJECT_MEMORY, NULL, 900 buf, from, len); 901 if ((ssize_t) len < PPC_INSN_SIZE) 902 memory_error (TARGET_XFER_E_IO, from); 903 904 insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order); 905 906 /* Check for PNOP and for prefixed instructions with R=0. Those 907 instructions are safe to displace. Prefixed instructions with R=1 908 will read/write data to/from locations relative to the current PC. 909 We would not be able to fixup after an instruction has written data 910 into a displaced location, so decline to displace those instructions. */ 911 if ((insn & OP_MASK) == 1 << 26) 912 { 913 if (((insn & PNOP_MASK) != PNOP_INSN) 914 && ((insn & R_MASK) != R_ZERO)) 915 { 916 displaced_debug_printf ("Not displacing prefixed instruction %08x at %s", 917 insn, paddress (gdbarch, from)); 918 return NULL; 919 } 920 } 921 else 922 /* Non-prefixed instructions.. */ 923 { 924 /* Set the instruction length to 4 to match the actual instruction 925 length. */ 926 len = 4; 927 } 928 929 /* Assume all atomic sequences start with a Load and Reserve instruction. */ 930 if (IS_LOAD_AND_RESERVE_INSN (insn)) 931 { 932 displaced_debug_printf ("can't displaced step atomic sequence at %s", 933 paddress (gdbarch, from)); 934 935 return NULL; 936 } 937 938 write_memory (to, buf, len); 939 940 displaced_debug_printf ("copy %s->%s: %s", 941 paddress (gdbarch, from), paddress (gdbarch, to), 942 displaced_step_dump_bytes (buf, len).c_str ()); 943 944 /* This is a work around for a problem with g++ 4.8. */ 945 return displaced_step_copy_insn_closure_up (closure.release ()); 946 } 947 948 /* Fix up the state of registers and memory after having single-stepped 949 a displaced instruction. */ 950 static void 951 ppc_displaced_step_fixup (struct gdbarch *gdbarch, 952 struct displaced_step_copy_insn_closure *closure_, 953 CORE_ADDR from, CORE_ADDR to, 954 struct regcache *regs) 955 { 956 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 957 /* Our closure is a copy of the instruction. */ 958 ppc_displaced_step_copy_insn_closure *closure 959 = (ppc_displaced_step_copy_insn_closure *) closure_; 960 ULONGEST insn = extract_unsigned_integer (closure->buf.data (), 961 PPC_INSN_SIZE, byte_order); 962 ULONGEST opcode; 963 /* Offset for non PC-relative instructions. */ 964 LONGEST offset; 965 966 opcode = insn & OP_MASK; 967 968 /* Set offset to 8 if this is an 8-byte (prefixed) instruction. */ 969 if ((opcode) == 1 << 26) 970 offset = 2 * PPC_INSN_SIZE; 971 else 972 offset = PPC_INSN_SIZE; 973 974 displaced_debug_printf ("(ppc) fixup (%s, %s)", 975 paddress (gdbarch, from), paddress (gdbarch, to)); 976 977 /* Handle the addpcis/lnia instruction. */ 978 if ((insn & ADDPCIS_INSN_MASK) == ADDPCIS_INSN) 979 { 980 LONGEST displaced_offset; 981 ULONGEST current_val; 982 /* Measure the displacement. */ 983 displaced_offset = from - to; 984 /* Identify the target register that was updated by the instruction. */ 985 int regnum = (insn & ADDPCIS_TARGET_REGISTER) >> ADDPCIS_INSN_REGSHIFT; 986 /* Read and update the target value. */ 987 regcache_cooked_read_unsigned (regs, regnum , ¤t_val); 988 displaced_debug_printf ("addpcis target regnum %d was %s now %s", 989 regnum, paddress (gdbarch, current_val), 990 paddress (gdbarch, current_val 991 + displaced_offset)); 992 regcache_cooked_write_unsigned (regs, regnum, 993 current_val + displaced_offset); 994 /* point the PC back at the non-displaced instruction. */ 995 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), 996 from + offset); 997 } 998 /* Handle PC-relative branch instructions. */ 999 else if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN) 1000 { 1001 ULONGEST current_pc; 1002 1003 /* Read the current PC value after the instruction has been executed 1004 in a displaced location. Calculate the offset to be applied to the 1005 original PC value before the displaced stepping. */ 1006 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1007 ¤t_pc); 1008 offset = current_pc - to; 1009 1010 if (opcode != BXL_INSN) 1011 { 1012 /* Check for AA bit indicating whether this is an absolute 1013 addressing or PC-relative (1: absolute, 0: relative). */ 1014 if (!(insn & 0x2)) 1015 { 1016 /* PC-relative addressing is being used in the branch. */ 1017 displaced_debug_printf ("(ppc) branch instruction: %s", 1018 paddress (gdbarch, insn)); 1019 displaced_debug_printf ("(ppc) adjusted PC from %s to %s", 1020 paddress (gdbarch, current_pc), 1021 paddress (gdbarch, from + offset)); 1022 1023 regcache_cooked_write_unsigned (regs, 1024 gdbarch_pc_regnum (gdbarch), 1025 from + offset); 1026 } 1027 } 1028 else 1029 { 1030 /* If we're here, it means we have a branch to LR or CTR. If the 1031 branch was taken, the offset is probably greater than 4 (the next 1032 instruction), so it's safe to assume that an offset of 4 means we 1033 did not take the branch. */ 1034 if (offset == PPC_INSN_SIZE) 1035 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1036 from + PPC_INSN_SIZE); 1037 } 1038 1039 /* Check for LK bit indicating whether we should set the link 1040 register to point to the next instruction 1041 (1: Set, 0: Don't set). */ 1042 if (insn & 0x1) 1043 { 1044 /* Link register needs to be set to the next instruction's PC. */ 1045 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 1046 regcache_cooked_write_unsigned (regs, 1047 tdep->ppc_lr_regnum, 1048 from + PPC_INSN_SIZE); 1049 displaced_debug_printf ("(ppc) adjusted LR to %s", 1050 paddress (gdbarch, from + PPC_INSN_SIZE)); 1051 1052 } 1053 } 1054 /* Check for breakpoints in the inferior. If we've found one, place the PC 1055 right at the breakpoint instruction. */ 1056 else if ((insn & BP_MASK) == BP_INSN) 1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from); 1058 else 1059 { 1060 /* Handle any other instructions that do not fit in the categories 1061 above. */ 1062 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), 1063 from + offset); 1064 } 1065 } 1066 1067 /* Implementation of gdbarch_displaced_step_prepare. */ 1068 1069 static displaced_step_prepare_status 1070 ppc_displaced_step_prepare (gdbarch *arch, thread_info *thread, 1071 CORE_ADDR &displaced_pc) 1072 { 1073 ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf); 1074 1075 if (!per_inferior->disp_step_buf.has_value ()) 1076 { 1077 /* Figure out where the displaced step buffer is. */ 1078 CORE_ADDR disp_step_buf_addr 1079 = displaced_step_at_entry_point (thread->inf->gdbarch); 1080 1081 per_inferior->disp_step_buf.emplace (disp_step_buf_addr); 1082 } 1083 1084 return per_inferior->disp_step_buf->prepare (thread, displaced_pc); 1085 } 1086 1087 /* Implementation of gdbarch_displaced_step_finish. */ 1088 1089 static displaced_step_finish_status 1090 ppc_displaced_step_finish (gdbarch *arch, thread_info *thread, 1091 gdb_signal sig) 1092 { 1093 ppc_inferior_data *per_inferior = get_ppc_per_inferior (thread->inf); 1094 1095 gdb_assert (per_inferior->disp_step_buf.has_value ()); 1096 1097 return per_inferior->disp_step_buf->finish (arch, thread, sig); 1098 } 1099 1100 /* Implementation of gdbarch_displaced_step_restore_all_in_ptid. */ 1101 1102 static void 1103 ppc_displaced_step_restore_all_in_ptid (inferior *parent_inf, ptid_t ptid) 1104 { 1105 ppc_inferior_data *per_inferior = ppc_inferior_data_key.get (parent_inf); 1106 1107 if (per_inferior == nullptr 1108 || !per_inferior->disp_step_buf.has_value ()) 1109 return; 1110 1111 per_inferior->disp_step_buf->restore_in_ptid (ptid); 1112 } 1113 1114 /* Always use hardware single-stepping to execute the 1115 displaced instruction. */ 1116 static bool 1117 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch) 1118 { 1119 return true; 1120 } 1121 1122 /* Checks for an atomic sequence of instructions beginning with a 1123 Load And Reserve instruction and ending with a Store Conditional 1124 instruction. If such a sequence is found, attempt to step through it. 1125 A breakpoint is placed at the end of the sequence. */ 1126 std::vector<CORE_ADDR> 1127 ppc_deal_with_atomic_sequence (struct regcache *regcache) 1128 { 1129 struct gdbarch *gdbarch = regcache->arch (); 1130 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1131 CORE_ADDR pc = regcache_read_pc (regcache); 1132 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; 1133 CORE_ADDR loc = pc; 1134 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ 1135 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); 1136 int insn_count; 1137 int index; 1138 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 1139 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 1140 int bc_insn_count = 0; /* Conditional branch instruction count. */ 1141 1142 /* Assume all atomic sequences start with a Load And Reserve instruction. */ 1143 if (!IS_LOAD_AND_RESERVE_INSN (insn)) 1144 return {}; 1145 1146 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 1147 instructions. */ 1148 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 1149 { 1150 if ((insn & OP_MASK) == 1 << 26) 1151 loc += 2 * PPC_INSN_SIZE; 1152 else 1153 loc += PPC_INSN_SIZE; 1154 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order); 1155 1156 /* Assume that there is at most one conditional branch in the atomic 1157 sequence. If a conditional branch is found, put a breakpoint in 1158 its destination address. */ 1159 if ((insn & OP_MASK) == BC_INSN) 1160 { 1161 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000; 1162 int absolute = insn & 2; 1163 1164 if (bc_insn_count >= 1) 1165 return {}; /* More than one conditional branch found, fallback 1166 to the standard single-step code. */ 1167 1168 if (absolute) 1169 breaks[1] = immediate; 1170 else 1171 breaks[1] = loc + immediate; 1172 1173 bc_insn_count++; 1174 last_breakpoint++; 1175 } 1176 1177 if (IS_STORE_CONDITIONAL_INSN (insn)) 1178 break; 1179 } 1180 1181 /* Assume that the atomic sequence ends with a Store Conditional 1182 instruction. */ 1183 if (!IS_STORE_CONDITIONAL_INSN (insn)) 1184 return {}; 1185 1186 closing_insn = loc; 1187 loc += PPC_INSN_SIZE; 1188 1189 /* Insert a breakpoint right after the end of the atomic sequence. */ 1190 breaks[0] = loc; 1191 1192 /* Check for duplicated breakpoints. Check also for a breakpoint 1193 placed (branch instruction's destination) anywhere in sequence. */ 1194 if (last_breakpoint 1195 && (breaks[1] == breaks[0] 1196 || (breaks[1] >= pc && breaks[1] <= closing_insn))) 1197 last_breakpoint = 0; 1198 1199 std::vector<CORE_ADDR> next_pcs; 1200 1201 for (index = 0; index <= last_breakpoint; index++) 1202 next_pcs.push_back (breaks[index]); 1203 1204 return next_pcs; 1205 } 1206 1207 1208 #define SIGNED_SHORT(x) \ 1209 ((sizeof (short) == 2) \ 1210 ? ((int)(short)(x)) \ 1211 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 1212 1213 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 1214 1215 /* Limit the number of skipped non-prologue instructions, as the examining 1216 of the prologue is expensive. */ 1217 static int max_skip_non_prologue_insns = 10; 1218 1219 /* Return nonzero if the given instruction OP can be part of the prologue 1220 of a function and saves a parameter on the stack. FRAMEP should be 1221 set if one of the previous instructions in the function has set the 1222 Frame Pointer. */ 1223 1224 static int 1225 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) 1226 { 1227 /* Move parameters from argument registers to temporary register. */ 1228 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ 1229 { 1230 /* Rx must be scratch register r0. */ 1231 const int rx_regno = (op >> 16) & 31; 1232 /* Ry: Only r3 - r10 are used for parameter passing. */ 1233 const int ry_regno = GET_SRC_REG (op); 1234 1235 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) 1236 { 1237 *r0_contains_arg = 1; 1238 return 1; 1239 } 1240 else 1241 return 0; 1242 } 1243 1244 /* Save a General Purpose Register on stack. */ 1245 1246 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ 1247 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ 1248 { 1249 /* Rx: Only r3 - r10 are used for parameter passing. */ 1250 const int rx_regno = GET_SRC_REG (op); 1251 1252 return (rx_regno >= 3 && rx_regno <= 10); 1253 } 1254 1255 /* Save a General Purpose Register on stack via the Frame Pointer. */ 1256 1257 if (framep && 1258 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ 1259 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ 1260 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ 1261 { 1262 /* Rx: Usually, only r3 - r10 are used for parameter passing. 1263 However, the compiler sometimes uses r0 to hold an argument. */ 1264 const int rx_regno = GET_SRC_REG (op); 1265 1266 return ((rx_regno >= 3 && rx_regno <= 10) 1267 || (rx_regno == 0 && *r0_contains_arg)); 1268 } 1269 1270 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 1271 { 1272 /* Only f2 - f8 are used for parameter passing. */ 1273 const int src_regno = GET_SRC_REG (op); 1274 1275 return (src_regno >= 2 && src_regno <= 8); 1276 } 1277 1278 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ 1279 { 1280 /* Only f2 - f8 are used for parameter passing. */ 1281 const int src_regno = GET_SRC_REG (op); 1282 1283 return (src_regno >= 2 && src_regno <= 8); 1284 } 1285 1286 /* Not an insn that saves a parameter on stack. */ 1287 return 0; 1288 } 1289 1290 /* Assuming that INSN is a "bl" instruction located at PC, return 1291 nonzero if the destination of the branch is a "blrl" instruction. 1292 1293 This sequence is sometimes found in certain function prologues. 1294 It allows the function to load the LR register with a value that 1295 they can use to access PIC data using PC-relative offsets. */ 1296 1297 static int 1298 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order) 1299 { 1300 CORE_ADDR dest; 1301 int immediate; 1302 int absolute; 1303 int dest_insn; 1304 1305 absolute = (int) ((insn >> 1) & 1); 1306 immediate = ((insn & ~3) << 6) >> 6; 1307 if (absolute) 1308 dest = immediate; 1309 else 1310 dest = pc + immediate; 1311 1312 dest_insn = read_memory_integer (dest, 4, byte_order); 1313 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ 1314 return 1; 1315 1316 return 0; 1317 } 1318 1319 /* Return true if OP is a stw or std instruction with 1320 register operands RS and RA and any immediate offset. 1321 1322 If WITH_UPDATE is true, also return true if OP is 1323 a stwu or stdu instruction with the same operands. 1324 1325 Return false otherwise. 1326 */ 1327 static bool 1328 store_insn_p (unsigned long op, unsigned long rs, 1329 unsigned long ra, bool with_update) 1330 { 1331 rs = rs << 21; 1332 ra = ra << 16; 1333 1334 if (/* std RS, SIMM(RA) */ 1335 ((op & 0xffff0003) == (rs | ra | 0xf8000000)) || 1336 /* stw RS, SIMM(RA) */ 1337 ((op & 0xffff0000) == (rs | ra | 0x90000000))) 1338 return true; 1339 1340 if (with_update) 1341 { 1342 if (/* stdu RS, SIMM(RA) */ 1343 ((op & 0xffff0003) == (rs | ra | 0xf8000001)) || 1344 /* stwu RS, SIMM(RA) */ 1345 ((op & 0xffff0000) == (rs | ra | 0x94000000))) 1346 return true; 1347 } 1348 1349 return false; 1350 } 1351 1352 /* Masks for decoding a branch-and-link (bl) instruction. 1353 1354 BL_MASK and BL_INSTRUCTION are used in combination with each other. 1355 The former is anded with the opcode in question; if the result of 1356 this masking operation is equal to BL_INSTRUCTION, then the opcode in 1357 question is a ``bl'' instruction. 1358 1359 BL_DISPLACEMENT_MASK is anded with the opcode in order to extract 1360 the branch displacement. */ 1361 1362 #define BL_MASK 0xfc000001 1363 #define BL_INSTRUCTION 0x48000001 1364 #define BL_DISPLACEMENT_MASK 0x03fffffc 1365 1366 static unsigned long 1367 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc) 1368 { 1369 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1370 gdb_byte buf[4]; 1371 unsigned long op; 1372 1373 /* Fetch the instruction and convert it to an integer. */ 1374 if (target_read_memory (pc, buf, 4)) 1375 return 0; 1376 op = extract_unsigned_integer (buf, 4, byte_order); 1377 1378 return op; 1379 } 1380 1381 /* GCC generates several well-known sequences of instructions at the begining 1382 of each function prologue when compiling with -fstack-check. If one of 1383 such sequences starts at START_PC, then return the address of the 1384 instruction immediately past this sequence. Otherwise, return START_PC. */ 1385 1386 static CORE_ADDR 1387 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc) 1388 { 1389 CORE_ADDR pc = start_pc; 1390 unsigned long op = rs6000_fetch_instruction (gdbarch, pc); 1391 1392 /* First possible sequence: A small number of probes. 1393 stw 0, -<some immediate>(1) 1394 [repeat this instruction any (small) number of times]. */ 1395 1396 if ((op & 0xffff0000) == 0x90010000) 1397 { 1398 while ((op & 0xffff0000) == 0x90010000) 1399 { 1400 pc = pc + 4; 1401 op = rs6000_fetch_instruction (gdbarch, pc); 1402 } 1403 return pc; 1404 } 1405 1406 /* Second sequence: A probing loop. 1407 addi 12,1,-<some immediate> 1408 lis 0,-<some immediate> 1409 [possibly ori 0,0,<some immediate>] 1410 add 0,12,0 1411 cmpw 0,12,0 1412 beq 0,<disp> 1413 addi 12,12,-<some immediate> 1414 stw 0,0(12) 1415 b <disp> 1416 [possibly one last probe: stw 0,<some immediate>(12)]. */ 1417 1418 while (1) 1419 { 1420 /* addi 12,1,-<some immediate> */ 1421 if ((op & 0xffff0000) != 0x39810000) 1422 break; 1423 1424 /* lis 0,-<some immediate> */ 1425 pc = pc + 4; 1426 op = rs6000_fetch_instruction (gdbarch, pc); 1427 if ((op & 0xffff0000) != 0x3c000000) 1428 break; 1429 1430 pc = pc + 4; 1431 op = rs6000_fetch_instruction (gdbarch, pc); 1432 /* [possibly ori 0,0,<some immediate>] */ 1433 if ((op & 0xffff0000) == 0x60000000) 1434 { 1435 pc = pc + 4; 1436 op = rs6000_fetch_instruction (gdbarch, pc); 1437 } 1438 /* add 0,12,0 */ 1439 if (op != 0x7c0c0214) 1440 break; 1441 1442 /* cmpw 0,12,0 */ 1443 pc = pc + 4; 1444 op = rs6000_fetch_instruction (gdbarch, pc); 1445 if (op != 0x7c0c0000) 1446 break; 1447 1448 /* beq 0,<disp> */ 1449 pc = pc + 4; 1450 op = rs6000_fetch_instruction (gdbarch, pc); 1451 if ((op & 0xff9f0001) != 0x41820000) 1452 break; 1453 1454 /* addi 12,12,-<some immediate> */ 1455 pc = pc + 4; 1456 op = rs6000_fetch_instruction (gdbarch, pc); 1457 if ((op & 0xffff0000) != 0x398c0000) 1458 break; 1459 1460 /* stw 0,0(12) */ 1461 pc = pc + 4; 1462 op = rs6000_fetch_instruction (gdbarch, pc); 1463 if (op != 0x900c0000) 1464 break; 1465 1466 /* b <disp> */ 1467 pc = pc + 4; 1468 op = rs6000_fetch_instruction (gdbarch, pc); 1469 if ((op & 0xfc000001) != 0x48000000) 1470 break; 1471 1472 /* [possibly one last probe: stw 0,<some immediate>(12)]. */ 1473 pc = pc + 4; 1474 op = rs6000_fetch_instruction (gdbarch, pc); 1475 if ((op & 0xffff0000) == 0x900c0000) 1476 { 1477 pc = pc + 4; 1478 op = rs6000_fetch_instruction (gdbarch, pc); 1479 } 1480 1481 /* We found a valid stack-check sequence, return the new PC. */ 1482 return pc; 1483 } 1484 1485 /* Third sequence: No probe; instead, a comparison between the stack size 1486 limit (saved in a run-time global variable) and the current stack 1487 pointer: 1488 1489 addi 0,1,-<some immediate> 1490 lis 12,__gnat_stack_limit@ha 1491 lwz 12,__gnat_stack_limit@l(12) 1492 twllt 0,12 1493 1494 or, with a small variant in the case of a bigger stack frame: 1495 addis 0,1,<some immediate> 1496 addic 0,0,-<some immediate> 1497 lis 12,__gnat_stack_limit@ha 1498 lwz 12,__gnat_stack_limit@l(12) 1499 twllt 0,12 1500 */ 1501 while (1) 1502 { 1503 /* addi 0,1,-<some immediate> */ 1504 if ((op & 0xffff0000) != 0x38010000) 1505 { 1506 /* small stack frame variant not recognized; try the 1507 big stack frame variant: */ 1508 1509 /* addis 0,1,<some immediate> */ 1510 if ((op & 0xffff0000) != 0x3c010000) 1511 break; 1512 1513 /* addic 0,0,-<some immediate> */ 1514 pc = pc + 4; 1515 op = rs6000_fetch_instruction (gdbarch, pc); 1516 if ((op & 0xffff0000) != 0x30000000) 1517 break; 1518 } 1519 1520 /* lis 12,<some immediate> */ 1521 pc = pc + 4; 1522 op = rs6000_fetch_instruction (gdbarch, pc); 1523 if ((op & 0xffff0000) != 0x3d800000) 1524 break; 1525 1526 /* lwz 12,<some immediate>(12) */ 1527 pc = pc + 4; 1528 op = rs6000_fetch_instruction (gdbarch, pc); 1529 if ((op & 0xffff0000) != 0x818c0000) 1530 break; 1531 1532 /* twllt 0,12 */ 1533 pc = pc + 4; 1534 op = rs6000_fetch_instruction (gdbarch, pc); 1535 if ((op & 0xfffffffe) != 0x7c406008) 1536 break; 1537 1538 /* We found a valid stack-check sequence, return the new PC. */ 1539 return pc; 1540 } 1541 1542 /* No stack check code in our prologue, return the start_pc. */ 1543 return start_pc; 1544 } 1545 1546 /* return pc value after skipping a function prologue and also return 1547 information about a function frame. 1548 1549 in struct rs6000_framedata fdata: 1550 - frameless is TRUE, if function does not have a frame. 1551 - nosavedpc is TRUE, if function does not save %pc value in its frame. 1552 - offset is the initial size of this stack frame --- the amount by 1553 which we decrement the sp to allocate the frame. 1554 - saved_gpr is the number of the first saved gpr. 1555 - saved_fpr is the number of the first saved fpr. 1556 - saved_vr is the number of the first saved vr. 1557 - saved_ev is the number of the first saved ev. 1558 - alloca_reg is the number of the register used for alloca() handling. 1559 Otherwise -1. 1560 - gpr_offset is the offset of the first saved gpr from the previous frame. 1561 - fpr_offset is the offset of the first saved fpr from the previous frame. 1562 - vr_offset is the offset of the first saved vr from the previous frame. 1563 - ev_offset is the offset of the first saved ev from the previous frame. 1564 - lr_offset is the offset of the saved lr 1565 - cr_offset is the offset of the saved cr 1566 - vrsave_offset is the offset of the saved vrsave register. */ 1567 1568 static CORE_ADDR 1569 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc, 1570 struct rs6000_framedata *fdata) 1571 { 1572 CORE_ADDR orig_pc = pc; 1573 CORE_ADDR last_prologue_pc = pc; 1574 CORE_ADDR li_found_pc = 0; 1575 gdb_byte buf[4]; 1576 unsigned long op; 1577 long offset = 0; 1578 long alloca_reg_offset = 0; 1579 long vr_saved_offset = 0; 1580 int lr_reg = -1; 1581 int cr_reg = -1; 1582 int vr_reg = -1; 1583 int ev_reg = -1; 1584 long ev_offset = 0; 1585 int vrsave_reg = -1; 1586 int reg; 1587 int framep = 0; 1588 int minimal_toc_loaded = 0; 1589 int prev_insn_was_prologue_insn = 1; 1590 int num_skip_non_prologue_insns = 0; 1591 int r0_contains_arg = 0; 1592 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch); 1593 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 1594 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1595 1596 memset (fdata, 0, sizeof (struct rs6000_framedata)); 1597 fdata->saved_gpr = -1; 1598 fdata->saved_fpr = -1; 1599 fdata->saved_vr = -1; 1600 fdata->saved_ev = -1; 1601 fdata->alloca_reg = -1; 1602 fdata->frameless = 1; 1603 fdata->nosavedpc = 1; 1604 fdata->lr_register = -1; 1605 1606 pc = rs6000_skip_stack_check (gdbarch, pc); 1607 if (pc >= lim_pc) 1608 pc = lim_pc; 1609 1610 for (;; pc += 4) 1611 { 1612 /* Sometimes it isn't clear if an instruction is a prologue 1613 instruction or not. When we encounter one of these ambiguous 1614 cases, we'll set prev_insn_was_prologue_insn to 0 (false). 1615 Otherwise, we'll assume that it really is a prologue instruction. */ 1616 if (prev_insn_was_prologue_insn) 1617 last_prologue_pc = pc; 1618 1619 /* Stop scanning if we've hit the limit. */ 1620 if (pc >= lim_pc) 1621 break; 1622 1623 prev_insn_was_prologue_insn = 1; 1624 1625 /* Fetch the instruction and convert it to an integer. */ 1626 if (target_read_memory (pc, buf, 4)) 1627 break; 1628 op = extract_unsigned_integer (buf, 4, byte_order); 1629 1630 if ((op & 0xfc1fffff) == 0x7c0802a6) 1631 { /* mflr Rx */ 1632 /* Since shared library / PIC code, which needs to get its 1633 address at runtime, can appear to save more than one link 1634 register vis: 1635 1636 *INDENT-OFF* 1637 stwu r1,-304(r1) 1638 mflr r3 1639 bl 0xff570d0 (blrl) 1640 stw r30,296(r1) 1641 mflr r30 1642 stw r31,300(r1) 1643 stw r3,308(r1); 1644 ... 1645 *INDENT-ON* 1646 1647 remember just the first one, but skip over additional 1648 ones. */ 1649 if (lr_reg == -1) 1650 lr_reg = (op & 0x03e00000) >> 21; 1651 if (lr_reg == 0) 1652 r0_contains_arg = 0; 1653 continue; 1654 } 1655 else if ((op & 0xfc1fffff) == 0x7c000026) 1656 { /* mfcr Rx */ 1657 cr_reg = (op & 0x03e00000) >> 21; 1658 if (cr_reg == 0) 1659 r0_contains_arg = 0; 1660 continue; 1661 1662 } 1663 else if ((op & 0xfc1f0000) == 0xd8010000) 1664 { /* stfd Rx,NUM(r1) */ 1665 reg = GET_SRC_REG (op); 1666 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 1667 { 1668 fdata->saved_fpr = reg; 1669 fdata->fpr_offset = SIGNED_SHORT (op) + offset; 1670 } 1671 continue; 1672 1673 } 1674 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 1675 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 1676 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 1677 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 1678 { 1679 1680 reg = GET_SRC_REG (op); 1681 if ((op & 0xfc1f0000) == 0xbc010000) 1682 fdata->gpr_mask |= ~((1U << reg) - 1); 1683 else 1684 fdata->gpr_mask |= 1U << reg; 1685 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 1686 { 1687 fdata->saved_gpr = reg; 1688 if ((op & 0xfc1f0003) == 0xf8010000) 1689 op &= ~3UL; 1690 fdata->gpr_offset = SIGNED_SHORT (op) + offset; 1691 } 1692 continue; 1693 1694 } 1695 else if ((op & 0xffff0000) == 0x3c4c0000 1696 || (op & 0xffff0000) == 0x3c400000 1697 || (op & 0xffff0000) == 0x38420000) 1698 { 1699 /* . 0: addis 2,12,.TOC.-0b@ha 1700 . addi 2,2,.TOC.-0b@l 1701 or 1702 . lis 2,.TOC.@ha 1703 . addi 2,2,.TOC.@l 1704 used by ELFv2 global entry points to set up r2. */ 1705 continue; 1706 } 1707 else if (op == 0x60000000) 1708 { 1709 /* nop */ 1710 /* Allow nops in the prologue, but do not consider them to 1711 be part of the prologue unless followed by other prologue 1712 instructions. */ 1713 prev_insn_was_prologue_insn = 0; 1714 continue; 1715 1716 } 1717 else if ((op & 0xffff0000) == 0x3c000000) 1718 { /* addis 0,0,NUM, used for >= 32k frames */ 1719 fdata->offset = (op & 0x0000ffff) << 16; 1720 fdata->frameless = 0; 1721 r0_contains_arg = 0; 1722 continue; 1723 1724 } 1725 else if ((op & 0xffff0000) == 0x60000000) 1726 { /* ori 0,0,NUM, 2nd half of >= 32k frames */ 1727 fdata->offset |= (op & 0x0000ffff); 1728 fdata->frameless = 0; 1729 r0_contains_arg = 0; 1730 continue; 1731 1732 } 1733 else if (lr_reg >= 0 && 1734 ((store_insn_p (op, lr_reg, 1, true)) || 1735 (framep && 1736 (store_insn_p (op, lr_reg, 1737 fdata->alloca_reg - tdep->ppc_gp0_regnum, 1738 false))))) 1739 { 1740 if (store_insn_p (op, lr_reg, 1, true)) 1741 fdata->lr_offset = offset; 1742 else /* LR save through frame pointer. */ 1743 fdata->lr_offset = alloca_reg_offset; 1744 1745 fdata->nosavedpc = 0; 1746 /* Invalidate lr_reg, but don't set it to -1. 1747 That would mean that it had never been set. */ 1748 lr_reg = -2; 1749 if ((op & 0xfc000003) == 0xf8000000 || /* std */ 1750 (op & 0xfc000000) == 0x90000000) /* stw */ 1751 { 1752 /* Does not update r1, so add displacement to lr_offset. */ 1753 fdata->lr_offset += SIGNED_SHORT (op); 1754 } 1755 continue; 1756 1757 } 1758 else if (cr_reg >= 0 && 1759 (store_insn_p (op, cr_reg, 1, true))) 1760 { 1761 fdata->cr_offset = offset; 1762 /* Invalidate cr_reg, but don't set it to -1. 1763 That would mean that it had never been set. */ 1764 cr_reg = -2; 1765 if ((op & 0xfc000003) == 0xf8000000 || 1766 (op & 0xfc000000) == 0x90000000) 1767 { 1768 /* Does not update r1, so add displacement to cr_offset. */ 1769 fdata->cr_offset += SIGNED_SHORT (op); 1770 } 1771 continue; 1772 1773 } 1774 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) 1775 { 1776 /* bcl 20,xx,.+4 is used to get the current PC, with or without 1777 prediction bits. If the LR has already been saved, we can 1778 skip it. */ 1779 continue; 1780 } 1781 else if (op == 0x48000005) 1782 { /* bl .+4 used in 1783 -mrelocatable */ 1784 fdata->used_bl = 1; 1785 continue; 1786 1787 } 1788 else if (op == 0x48000004) 1789 { /* b .+4 (xlc) */ 1790 break; 1791 1792 } 1793 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 1794 in V.4 -mminimal-toc */ 1795 (op & 0xffff0000) == 0x3bde0000) 1796 { /* addi 30,30,foo@l */ 1797 continue; 1798 1799 } 1800 else if ((op & 0xfc000001) == 0x48000001) 1801 { /* bl foo, 1802 to save fprs??? */ 1803 1804 fdata->frameless = 0; 1805 1806 /* If the return address has already been saved, we can skip 1807 calls to blrl (for PIC). */ 1808 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order)) 1809 { 1810 fdata->used_bl = 1; 1811 continue; 1812 } 1813 1814 /* Don't skip over the subroutine call if it is not within 1815 the first three instructions of the prologue and either 1816 we have no line table information or the line info tells 1817 us that the subroutine call is not part of the line 1818 associated with the prologue. */ 1819 if ((pc - orig_pc) > 8) 1820 { 1821 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); 1822 struct symtab_and_line this_sal = find_pc_line (pc, 0); 1823 1824 if ((prologue_sal.line == 0) 1825 || (prologue_sal.line != this_sal.line)) 1826 break; 1827 } 1828 1829 op = read_memory_integer (pc + 4, 4, byte_order); 1830 1831 /* At this point, make sure this is not a trampoline 1832 function (a function that simply calls another functions, 1833 and nothing else). If the next is not a nop, this branch 1834 was part of the function prologue. */ 1835 1836 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 1837 break; /* Don't skip over 1838 this branch. */ 1839 1840 fdata->used_bl = 1; 1841 continue; 1842 } 1843 /* update stack pointer */ 1844 else if ((op & 0xfc1f0000) == 0x94010000) 1845 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 1846 fdata->frameless = 0; 1847 fdata->offset = SIGNED_SHORT (op); 1848 offset = fdata->offset; 1849 continue; 1850 } 1851 else if ((op & 0xfc1f07fa) == 0x7c01016a) 1852 { /* stwux rX,r1,rY || stdux rX,r1,rY */ 1853 /* No way to figure out what r1 is going to be. */ 1854 fdata->frameless = 0; 1855 offset = fdata->offset; 1856 continue; 1857 } 1858 else if ((op & 0xfc1f0003) == 0xf8010001) 1859 { /* stdu rX,NUM(r1) */ 1860 fdata->frameless = 0; 1861 fdata->offset = SIGNED_SHORT (op & ~3UL); 1862 offset = fdata->offset; 1863 continue; 1864 } 1865 else if ((op & 0xffff0000) == 0x38210000) 1866 { /* addi r1,r1,SIMM */ 1867 fdata->frameless = 0; 1868 fdata->offset += SIGNED_SHORT (op); 1869 offset = fdata->offset; 1870 continue; 1871 } 1872 /* Load up minimal toc pointer. Do not treat an epilogue restore 1873 of r31 as a minimal TOC load. */ 1874 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 1875 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 1876 && !framep 1877 && !minimal_toc_loaded) 1878 { 1879 minimal_toc_loaded = 1; 1880 continue; 1881 1882 /* move parameters from argument registers to local variable 1883 registers */ 1884 } 1885 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 1886 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 1887 (((op >> 21) & 31) <= 10) && 1888 ((long) ((op >> 16) & 31) 1889 >= fdata->saved_gpr)) /* Rx: local var reg */ 1890 { 1891 continue; 1892 1893 /* store parameters in stack */ 1894 } 1895 /* Move parameters from argument registers to temporary register. */ 1896 else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) 1897 { 1898 continue; 1899 1900 /* Set up frame pointer */ 1901 } 1902 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */ 1903 { 1904 fdata->frameless = 0; 1905 framep = 1; 1906 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29); 1907 alloca_reg_offset = offset; 1908 continue; 1909 1910 /* Another way to set up the frame pointer. */ 1911 } 1912 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 1913 || op == 0x7c3f0b78) 1914 { /* mr r31, r1 */ 1915 fdata->frameless = 0; 1916 framep = 1; 1917 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 1918 alloca_reg_offset = offset; 1919 continue; 1920 1921 /* Another way to set up the frame pointer. */ 1922 } 1923 else if ((op & 0xfc1fffff) == 0x38010000) 1924 { /* addi rX, r1, 0x0 */ 1925 fdata->frameless = 0; 1926 framep = 1; 1927 fdata->alloca_reg = (tdep->ppc_gp0_regnum 1928 + ((op & ~0x38010000) >> 21)); 1929 alloca_reg_offset = offset; 1930 continue; 1931 } 1932 /* AltiVec related instructions. */ 1933 /* Store the vrsave register (spr 256) in another register for 1934 later manipulation, or load a register into the vrsave 1935 register. 2 instructions are used: mfvrsave and 1936 mtvrsave. They are shorthand notation for mfspr Rn, SPR256 1937 and mtspr SPR256, Rn. */ 1938 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 1939 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 1940 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 1941 { 1942 vrsave_reg = GET_SRC_REG (op); 1943 continue; 1944 } 1945 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 1946 { 1947 continue; 1948 } 1949 /* Store the register where vrsave was saved to onto the stack: 1950 rS is the register where vrsave was stored in a previous 1951 instruction. */ 1952 /* 100100 sssss 00001 dddddddd dddddddd */ 1953 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 1954 { 1955 if (vrsave_reg == GET_SRC_REG (op)) 1956 { 1957 fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 1958 vrsave_reg = -1; 1959 } 1960 continue; 1961 } 1962 /* Compute the new value of vrsave, by modifying the register 1963 where vrsave was saved to. */ 1964 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 1965 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 1966 { 1967 continue; 1968 } 1969 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 1970 in a pair of insns to save the vector registers on the 1971 stack. */ 1972 /* 001110 00000 00000 iiii iiii iiii iiii */ 1973 /* 001110 01110 00000 iiii iiii iiii iiii */ 1974 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 1975 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 1976 { 1977 if ((op & 0xffff0000) == 0x38000000) 1978 r0_contains_arg = 0; 1979 li_found_pc = pc; 1980 vr_saved_offset = SIGNED_SHORT (op); 1981 1982 /* This insn by itself is not part of the prologue, unless 1983 if part of the pair of insns mentioned above. So do not 1984 record this insn as part of the prologue yet. */ 1985 prev_insn_was_prologue_insn = 0; 1986 } 1987 /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 1988 /* 011111 sssss 11111 00000 00111001110 */ 1989 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 1990 { 1991 if (pc == (li_found_pc + 4)) 1992 { 1993 vr_reg = GET_SRC_REG (op); 1994 /* If this is the first vector reg to be saved, or if 1995 it has a lower number than others previously seen, 1996 reupdate the frame info. */ 1997 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 1998 { 1999 fdata->saved_vr = vr_reg; 2000 fdata->vr_offset = vr_saved_offset + offset; 2001 } 2002 vr_saved_offset = -1; 2003 vr_reg = -1; 2004 li_found_pc = 0; 2005 } 2006 } 2007 /* End AltiVec related instructions. */ 2008 2009 /* Start BookE related instructions. */ 2010 /* Store gen register S at (r31+uimm). 2011 Any register less than r13 is volatile, so we don't care. */ 2012 /* 000100 sssss 11111 iiiii 01100100001 */ 2013 else if (arch_info->mach == bfd_mach_ppc_e500 2014 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 2015 { 2016 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 2017 { 2018 unsigned int imm; 2019 ev_reg = GET_SRC_REG (op); 2020 imm = (op >> 11) & 0x1f; 2021 ev_offset = imm * 8; 2022 /* If this is the first vector reg to be saved, or if 2023 it has a lower number than others previously seen, 2024 reupdate the frame info. */ 2025 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2026 { 2027 fdata->saved_ev = ev_reg; 2028 fdata->ev_offset = ev_offset + offset; 2029 } 2030 } 2031 continue; 2032 } 2033 /* Store gen register rS at (r1+rB). */ 2034 /* 000100 sssss 00001 bbbbb 01100100000 */ 2035 else if (arch_info->mach == bfd_mach_ppc_e500 2036 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 2037 { 2038 if (pc == (li_found_pc + 4)) 2039 { 2040 ev_reg = GET_SRC_REG (op); 2041 /* If this is the first vector reg to be saved, or if 2042 it has a lower number than others previously seen, 2043 reupdate the frame info. */ 2044 /* We know the contents of rB from the previous instruction. */ 2045 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2046 { 2047 fdata->saved_ev = ev_reg; 2048 fdata->ev_offset = vr_saved_offset + offset; 2049 } 2050 vr_saved_offset = -1; 2051 ev_reg = -1; 2052 li_found_pc = 0; 2053 } 2054 continue; 2055 } 2056 /* Store gen register r31 at (rA+uimm). */ 2057 /* 000100 11111 aaaaa iiiii 01100100001 */ 2058 else if (arch_info->mach == bfd_mach_ppc_e500 2059 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 2060 { 2061 /* Wwe know that the source register is 31 already, but 2062 it can't hurt to compute it. */ 2063 ev_reg = GET_SRC_REG (op); 2064 ev_offset = ((op >> 11) & 0x1f) * 8; 2065 /* If this is the first vector reg to be saved, or if 2066 it has a lower number than others previously seen, 2067 reupdate the frame info. */ 2068 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2069 { 2070 fdata->saved_ev = ev_reg; 2071 fdata->ev_offset = ev_offset + offset; 2072 } 2073 2074 continue; 2075 } 2076 /* Store gen register S at (r31+r0). 2077 Store param on stack when offset from SP bigger than 4 bytes. */ 2078 /* 000100 sssss 11111 00000 01100100000 */ 2079 else if (arch_info->mach == bfd_mach_ppc_e500 2080 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 2081 { 2082 if (pc == (li_found_pc + 4)) 2083 { 2084 if ((op & 0x03e00000) >= 0x01a00000) 2085 { 2086 ev_reg = GET_SRC_REG (op); 2087 /* If this is the first vector reg to be saved, or if 2088 it has a lower number than others previously seen, 2089 reupdate the frame info. */ 2090 /* We know the contents of r0 from the previous 2091 instruction. */ 2092 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 2093 { 2094 fdata->saved_ev = ev_reg; 2095 fdata->ev_offset = vr_saved_offset + offset; 2096 } 2097 ev_reg = -1; 2098 } 2099 vr_saved_offset = -1; 2100 li_found_pc = 0; 2101 continue; 2102 } 2103 } 2104 /* End BookE related instructions. */ 2105 2106 else 2107 { 2108 /* Not a recognized prologue instruction. 2109 Handle optimizer code motions into the prologue by continuing 2110 the search if we have no valid frame yet or if the return 2111 address is not yet saved in the frame. Also skip instructions 2112 if some of the GPRs expected to be saved are not yet saved. */ 2113 if (fdata->frameless == 0 && fdata->nosavedpc == 0 2114 && fdata->saved_gpr != -1) 2115 { 2116 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1); 2117 2118 if ((fdata->gpr_mask & all_mask) == all_mask) 2119 break; 2120 } 2121 2122 if (op == 0x4e800020 /* blr */ 2123 || op == 0x4e800420) /* bctr */ 2124 /* Do not scan past epilogue in frameless functions or 2125 trampolines. */ 2126 break; 2127 if ((op & 0xf4000000) == 0x40000000) /* bxx */ 2128 /* Never skip branches. */ 2129 break; 2130 2131 /* Test based on opcode and mask values of 2132 powerpc_opcodes[svc..svcla] in opcodes/ppc-opc.c. */ 2133 if ((op & 0xffff0000) == 0x44000000) 2134 /* Never skip system calls. */ 2135 break; 2136 2137 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 2138 /* Do not scan too many insns, scanning insns is expensive with 2139 remote targets. */ 2140 break; 2141 2142 /* Continue scanning. */ 2143 prev_insn_was_prologue_insn = 0; 2144 continue; 2145 } 2146 } 2147 2148 #if 0 2149 /* I have problems with skipping over __main() that I need to address 2150 * sometime. Previously, I used to use misc_function_vector which 2151 * didn't work as well as I wanted to be. -MGO */ 2152 2153 /* If the first thing after skipping a prolog is a branch to a function, 2154 this might be a call to an initializer in main(), introduced by gcc2. 2155 We'd like to skip over it as well. Fortunately, xlc does some extra 2156 work before calling a function right after a prologue, thus we can 2157 single out such gcc2 behaviour. */ 2158 2159 2160 if ((op & 0xfc000001) == 0x48000001) 2161 { /* bl foo, an initializer function? */ 2162 op = read_memory_integer (pc + 4, 4, byte_order); 2163 2164 if (op == 0x4def7b82) 2165 { /* cror 0xf, 0xf, 0xf (nop) */ 2166 2167 /* Check and see if we are in main. If so, skip over this 2168 initializer function as well. */ 2169 2170 tmp = find_pc_misc_function (pc); 2171 if (tmp >= 0 2172 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 2173 return pc + 8; 2174 } 2175 } 2176 #endif /* 0 */ 2177 2178 if (pc == lim_pc && lr_reg >= 0) 2179 fdata->lr_register = lr_reg; 2180 2181 fdata->offset = -fdata->offset; 2182 return last_prologue_pc; 2183 } 2184 2185 static CORE_ADDR 2186 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 2187 { 2188 struct rs6000_framedata frame; 2189 CORE_ADDR limit_pc, func_addr, func_end_addr = 0; 2190 2191 /* See if we can determine the end of the prologue via the symbol table. 2192 If so, then return either PC, or the PC after the prologue, whichever 2193 is greater. */ 2194 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr)) 2195 { 2196 CORE_ADDR post_prologue_pc 2197 = skip_prologue_using_sal (gdbarch, func_addr); 2198 if (post_prologue_pc != 0) 2199 return std::max (pc, post_prologue_pc); 2200 } 2201 2202 /* Can't determine prologue from the symbol table, need to examine 2203 instructions. */ 2204 2205 /* Find an upper limit on the function prologue using the debug 2206 information. If the debug information could not be used to provide 2207 that bound, then use an arbitrary large number as the upper bound. */ 2208 limit_pc = skip_prologue_using_sal (gdbarch, pc); 2209 if (limit_pc == 0) 2210 limit_pc = pc + 100; /* Magic. */ 2211 2212 /* Do not allow limit_pc to be past the function end, if we know 2213 where that end is... */ 2214 if (func_end_addr && limit_pc > func_end_addr) 2215 limit_pc = func_end_addr; 2216 2217 pc = skip_prologue (gdbarch, pc, limit_pc, &frame); 2218 return pc; 2219 } 2220 2221 /* When compiling for EABI, some versions of GCC emit a call to __eabi 2222 in the prologue of main(). 2223 2224 The function below examines the code pointed at by PC and checks to 2225 see if it corresponds to a call to __eabi. If so, it returns the 2226 address of the instruction following that call. Otherwise, it simply 2227 returns PC. */ 2228 2229 static CORE_ADDR 2230 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 2231 { 2232 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2233 gdb_byte buf[4]; 2234 unsigned long op; 2235 2236 if (target_read_memory (pc, buf, 4)) 2237 return pc; 2238 op = extract_unsigned_integer (buf, 4, byte_order); 2239 2240 if ((op & BL_MASK) == BL_INSTRUCTION) 2241 { 2242 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK; 2243 CORE_ADDR call_dest = pc + 4 + displ; 2244 struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest); 2245 2246 /* We check for ___eabi (three leading underscores) in addition 2247 to __eabi in case the GCC option "-fleading-underscore" was 2248 used to compile the program. */ 2249 if (s.minsym != NULL 2250 && s.minsym->linkage_name () != NULL 2251 && (strcmp (s.minsym->linkage_name (), "__eabi") == 0 2252 || strcmp (s.minsym->linkage_name (), "___eabi") == 0)) 2253 pc += 4; 2254 } 2255 return pc; 2256 } 2257 2258 /* All the ABI's require 16 byte alignment. */ 2259 static CORE_ADDR 2260 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 2261 { 2262 return (addr & -16); 2263 } 2264 2265 /* Return whether handle_inferior_event() should proceed through code 2266 starting at PC in function NAME when stepping. 2267 2268 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 2269 handle memory references that are too distant to fit in instructions 2270 generated by the compiler. For example, if 'foo' in the following 2271 instruction: 2272 2273 lwz r9,foo(r2) 2274 2275 is greater than 32767, the linker might replace the lwz with a branch to 2276 somewhere in @FIX1 that does the load in 2 instructions and then branches 2277 back to where execution should continue. 2278 2279 GDB should silently step over @FIX code, just like AIX dbx does. 2280 Unfortunately, the linker uses the "b" instruction for the 2281 branches, meaning that the link register doesn't get set. 2282 Therefore, GDB's usual step_over_function () mechanism won't work. 2283 2284 Instead, use the gdbarch_skip_trampoline_code and 2285 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past 2286 @FIX code. */ 2287 2288 static int 2289 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch, 2290 CORE_ADDR pc, const char *name) 2291 { 2292 return name && startswith (name, "@FIX"); 2293 } 2294 2295 /* Skip code that the user doesn't want to see when stepping: 2296 2297 1. Indirect function calls use a piece of trampoline code to do context 2298 switching, i.e. to set the new TOC table. Skip such code if we are on 2299 its first instruction (as when we have single-stepped to here). 2300 2301 2. Skip shared library trampoline code (which is different from 2302 indirect function call trampolines). 2303 2304 3. Skip bigtoc fixup code. 2305 2306 Result is desired PC to step until, or NULL if we are not in 2307 code that should be skipped. */ 2308 2309 static CORE_ADDR 2310 rs6000_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) 2311 { 2312 struct gdbarch *gdbarch = get_frame_arch (frame); 2313 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2314 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2315 unsigned int ii, op; 2316 int rel; 2317 CORE_ADDR solib_target_pc; 2318 struct bound_minimal_symbol msymbol; 2319 2320 static unsigned trampoline_code[] = 2321 { 2322 0x800b0000, /* l r0,0x0(r11) */ 2323 0x90410014, /* st r2,0x14(r1) */ 2324 0x7c0903a6, /* mtctr r0 */ 2325 0x804b0004, /* l r2,0x4(r11) */ 2326 0x816b0008, /* l r11,0x8(r11) */ 2327 0x4e800420, /* bctr */ 2328 0x4e800020, /* br */ 2329 0 2330 }; 2331 2332 /* Check for bigtoc fixup code. */ 2333 msymbol = lookup_minimal_symbol_by_pc (pc); 2334 if (msymbol.minsym 2335 && rs6000_in_solib_return_trampoline (gdbarch, pc, 2336 msymbol.minsym->linkage_name ())) 2337 { 2338 /* Double-check that the third instruction from PC is relative "b". */ 2339 op = read_memory_integer (pc + 8, 4, byte_order); 2340 if ((op & 0xfc000003) == 0x48000000) 2341 { 2342 /* Extract bits 6-29 as a signed 24-bit relative word address and 2343 add it to the containing PC. */ 2344 rel = ((int)(op << 6) >> 6); 2345 return pc + 8 + rel; 2346 } 2347 } 2348 2349 /* If pc is in a shared library trampoline, return its target. */ 2350 solib_target_pc = find_solib_trampoline_target (frame, pc); 2351 if (solib_target_pc) 2352 return solib_target_pc; 2353 2354 for (ii = 0; trampoline_code[ii]; ++ii) 2355 { 2356 op = read_memory_integer (pc + (ii * 4), 4, byte_order); 2357 if (op != trampoline_code[ii]) 2358 return 0; 2359 } 2360 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination 2361 addr. */ 2362 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order); 2363 return pc; 2364 } 2365 2366 /* ISA-specific vector types. */ 2367 2368 static struct type * 2369 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) 2370 { 2371 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2372 2373 if (!tdep->ppc_builtin_type_vec64) 2374 { 2375 const struct builtin_type *bt = builtin_type (gdbarch); 2376 2377 /* The type we're building is this: */ 2378 #if 0 2379 union __gdb_builtin_type_vec64 2380 { 2381 int64_t uint64; 2382 float v2_float[2]; 2383 int32_t v2_int32[2]; 2384 int16_t v4_int16[4]; 2385 int8_t v8_int8[8]; 2386 }; 2387 #endif 2388 2389 struct type *t; 2390 2391 t = arch_composite_type (gdbarch, 2392 "__ppc_builtin_type_vec64", TYPE_CODE_UNION); 2393 append_composite_type_field (t, "uint64", bt->builtin_int64); 2394 append_composite_type_field (t, "v2_float", 2395 init_vector_type (bt->builtin_float, 2)); 2396 append_composite_type_field (t, "v2_int32", 2397 init_vector_type (bt->builtin_int32, 2)); 2398 append_composite_type_field (t, "v4_int16", 2399 init_vector_type (bt->builtin_int16, 4)); 2400 append_composite_type_field (t, "v8_int8", 2401 init_vector_type (bt->builtin_int8, 8)); 2402 2403 t->set_is_vector (true); 2404 t->set_name ("ppc_builtin_type_vec64"); 2405 tdep->ppc_builtin_type_vec64 = t; 2406 } 2407 2408 return tdep->ppc_builtin_type_vec64; 2409 } 2410 2411 /* Vector 128 type. */ 2412 2413 static struct type * 2414 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) 2415 { 2416 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2417 2418 if (!tdep->ppc_builtin_type_vec128) 2419 { 2420 const struct builtin_type *bt = builtin_type (gdbarch); 2421 2422 /* The type we're building is this 2423 2424 type = union __ppc_builtin_type_vec128 { 2425 float128_t float128; 2426 uint128_t uint128; 2427 double v2_double[2]; 2428 float v4_float[4]; 2429 int32_t v4_int32[4]; 2430 int16_t v8_int16[8]; 2431 int8_t v16_int8[16]; 2432 } 2433 */ 2434 2435 /* PPC specific type for IEEE 128-bit float field */ 2436 struct type *t_float128 2437 = arch_float_type (gdbarch, 128, "float128_t", floatformats_ieee_quad); 2438 2439 struct type *t; 2440 2441 t = arch_composite_type (gdbarch, 2442 "__ppc_builtin_type_vec128", TYPE_CODE_UNION); 2443 append_composite_type_field (t, "float128", t_float128); 2444 append_composite_type_field (t, "uint128", bt->builtin_uint128); 2445 append_composite_type_field (t, "v2_double", 2446 init_vector_type (bt->builtin_double, 2)); 2447 append_composite_type_field (t, "v4_float", 2448 init_vector_type (bt->builtin_float, 4)); 2449 append_composite_type_field (t, "v4_int32", 2450 init_vector_type (bt->builtin_int32, 4)); 2451 append_composite_type_field (t, "v8_int16", 2452 init_vector_type (bt->builtin_int16, 8)); 2453 append_composite_type_field (t, "v16_int8", 2454 init_vector_type (bt->builtin_int8, 16)); 2455 2456 t->set_is_vector (true); 2457 t->set_name ("ppc_builtin_type_vec128"); 2458 tdep->ppc_builtin_type_vec128 = t; 2459 } 2460 2461 return tdep->ppc_builtin_type_vec128; 2462 } 2463 2464 /* Return the name of register number REGNO, or the empty string if it 2465 is an anonymous register. */ 2466 2467 static const char * 2468 rs6000_register_name (struct gdbarch *gdbarch, int regno) 2469 { 2470 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2471 2472 /* The upper half "registers" have names in the XML description, 2473 but we present only the low GPRs and the full 64-bit registers 2474 to the user. */ 2475 if (tdep->ppc_ev0_upper_regnum >= 0 2476 && tdep->ppc_ev0_upper_regnum <= regno 2477 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 2478 return ""; 2479 2480 /* Hide the upper halves of the vs0~vs31 registers. */ 2481 if (tdep->ppc_vsr0_regnum >= 0 2482 && tdep->ppc_vsr0_upper_regnum <= regno 2483 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs) 2484 return ""; 2485 2486 /* Hide the upper halves of the cvs0~cvs31 registers. */ 2487 if (PPC_CVSR0_UPPER_REGNUM <= regno 2488 && regno < PPC_CVSR0_UPPER_REGNUM + ppc_num_gprs) 2489 return ""; 2490 2491 /* Check if the SPE pseudo registers are available. */ 2492 if (IS_SPE_PSEUDOREG (tdep, regno)) 2493 { 2494 static const char *const spe_regnames[] = { 2495 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7", 2496 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15", 2497 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23", 2498 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31", 2499 }; 2500 return spe_regnames[regno - tdep->ppc_ev0_regnum]; 2501 } 2502 2503 /* Check if the decimal128 pseudo-registers are available. */ 2504 if (IS_DFP_PSEUDOREG (tdep, regno)) 2505 { 2506 static const char *const dfp128_regnames[] = { 2507 "dl0", "dl1", "dl2", "dl3", 2508 "dl4", "dl5", "dl6", "dl7", 2509 "dl8", "dl9", "dl10", "dl11", 2510 "dl12", "dl13", "dl14", "dl15" 2511 }; 2512 return dfp128_regnames[regno - tdep->ppc_dl0_regnum]; 2513 } 2514 2515 /* Check if this is a vX alias for a raw vrX vector register. */ 2516 if (IS_V_ALIAS_PSEUDOREG (tdep, regno)) 2517 { 2518 static const char *const vector_alias_regnames[] = { 2519 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2520 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2521 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2522 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 2523 }; 2524 return vector_alias_regnames[regno - tdep->ppc_v0_alias_regnum]; 2525 } 2526 2527 /* Check if this is a VSX pseudo-register. */ 2528 if (IS_VSX_PSEUDOREG (tdep, regno)) 2529 { 2530 static const char *const vsx_regnames[] = { 2531 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7", 2532 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14", 2533 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21", 2534 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28", 2535 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35", 2536 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42", 2537 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49", 2538 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56", 2539 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63" 2540 }; 2541 return vsx_regnames[regno - tdep->ppc_vsr0_regnum]; 2542 } 2543 2544 /* Check if the this is a Extended FP pseudo-register. */ 2545 if (IS_EFP_PSEUDOREG (tdep, regno)) 2546 { 2547 static const char *const efpr_regnames[] = { 2548 "f32", "f33", "f34", "f35", "f36", "f37", "f38", 2549 "f39", "f40", "f41", "f42", "f43", "f44", "f45", 2550 "f46", "f47", "f48", "f49", "f50", "f51", 2551 "f52", "f53", "f54", "f55", "f56", "f57", 2552 "f58", "f59", "f60", "f61", "f62", "f63" 2553 }; 2554 return efpr_regnames[regno - tdep->ppc_efpr0_regnum]; 2555 } 2556 2557 /* Check if this is a Checkpointed DFP pseudo-register. */ 2558 if (IS_CDFP_PSEUDOREG (tdep, regno)) 2559 { 2560 static const char *const cdfp128_regnames[] = { 2561 "cdl0", "cdl1", "cdl2", "cdl3", 2562 "cdl4", "cdl5", "cdl6", "cdl7", 2563 "cdl8", "cdl9", "cdl10", "cdl11", 2564 "cdl12", "cdl13", "cdl14", "cdl15" 2565 }; 2566 return cdfp128_regnames[regno - tdep->ppc_cdl0_regnum]; 2567 } 2568 2569 /* Check if this is a Checkpointed VSX pseudo-register. */ 2570 if (IS_CVSX_PSEUDOREG (tdep, regno)) 2571 { 2572 static const char *const cvsx_regnames[] = { 2573 "cvs0", "cvs1", "cvs2", "cvs3", "cvs4", "cvs5", "cvs6", "cvs7", 2574 "cvs8", "cvs9", "cvs10", "cvs11", "cvs12", "cvs13", "cvs14", 2575 "cvs15", "cvs16", "cvs17", "cvs18", "cvs19", "cvs20", "cvs21", 2576 "cvs22", "cvs23", "cvs24", "cvs25", "cvs26", "cvs27", "cvs28", 2577 "cvs29", "cvs30", "cvs31", "cvs32", "cvs33", "cvs34", "cvs35", 2578 "cvs36", "cvs37", "cvs38", "cvs39", "cvs40", "cvs41", "cvs42", 2579 "cvs43", "cvs44", "cvs45", "cvs46", "cvs47", "cvs48", "cvs49", 2580 "cvs50", "cvs51", "cvs52", "cvs53", "cvs54", "cvs55", "cvs56", 2581 "cvs57", "cvs58", "cvs59", "cvs60", "cvs61", "cvs62", "cvs63" 2582 }; 2583 return cvsx_regnames[regno - tdep->ppc_cvsr0_regnum]; 2584 } 2585 2586 /* Check if the this is a Checkpointed Extended FP pseudo-register. */ 2587 if (IS_CEFP_PSEUDOREG (tdep, regno)) 2588 { 2589 static const char *const cefpr_regnames[] = { 2590 "cf32", "cf33", "cf34", "cf35", "cf36", "cf37", "cf38", 2591 "cf39", "cf40", "cf41", "cf42", "cf43", "cf44", "cf45", 2592 "cf46", "cf47", "cf48", "cf49", "cf50", "cf51", 2593 "cf52", "cf53", "cf54", "cf55", "cf56", "cf57", 2594 "cf58", "cf59", "cf60", "cf61", "cf62", "cf63" 2595 }; 2596 return cefpr_regnames[regno - tdep->ppc_cefpr0_regnum]; 2597 } 2598 2599 return tdesc_register_name (gdbarch, regno); 2600 } 2601 2602 /* Return the GDB type object for the "standard" data type of data in 2603 register N. */ 2604 2605 static struct type * 2606 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 2607 { 2608 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2609 2610 /* These are the e500 pseudo-registers. */ 2611 if (IS_SPE_PSEUDOREG (tdep, regnum)) 2612 return rs6000_builtin_type_vec64 (gdbarch); 2613 else if (IS_DFP_PSEUDOREG (tdep, regnum) 2614 || IS_CDFP_PSEUDOREG (tdep, regnum)) 2615 /* PPC decimal128 pseudo-registers. */ 2616 return builtin_type (gdbarch)->builtin_declong; 2617 else if (IS_V_ALIAS_PSEUDOREG (tdep, regnum)) 2618 return gdbarch_register_type (gdbarch, 2619 tdep->ppc_vr0_regnum 2620 + (regnum 2621 - tdep->ppc_v0_alias_regnum)); 2622 else if (IS_VSX_PSEUDOREG (tdep, regnum) 2623 || IS_CVSX_PSEUDOREG (tdep, regnum)) 2624 /* POWER7 VSX pseudo-registers. */ 2625 return rs6000_builtin_type_vec128 (gdbarch); 2626 else if (IS_EFP_PSEUDOREG (tdep, regnum) 2627 || IS_CEFP_PSEUDOREG (tdep, regnum)) 2628 /* POWER7 Extended FP pseudo-registers. */ 2629 return builtin_type (gdbarch)->builtin_double; 2630 else 2631 internal_error (_("rs6000_pseudo_register_type: " 2632 "called on unexpected register '%s' (%d)"), 2633 gdbarch_register_name (gdbarch, regnum), regnum); 2634 } 2635 2636 /* Check if REGNUM is a member of REGGROUP. We only need to handle 2637 the vX aliases for the vector registers by always returning false 2638 to avoid duplicated information in "info register vector/all", 2639 since the raw vrX registers will already show in these cases. For 2640 other pseudo-registers we use the default membership function. */ 2641 2642 static int 2643 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 2644 const struct reggroup *group) 2645 { 2646 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2647 2648 if (IS_V_ALIAS_PSEUDOREG (tdep, regnum)) 2649 return 0; 2650 else 2651 return default_register_reggroup_p (gdbarch, regnum, group); 2652 } 2653 2654 /* The register format for RS/6000 floating point registers is always 2655 double, we need a conversion if the memory format is float. */ 2656 2657 static int 2658 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum, 2659 struct type *type) 2660 { 2661 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2662 2663 return (tdep->ppc_fp0_regnum >= 0 2664 && regnum >= tdep->ppc_fp0_regnum 2665 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs 2666 && type->code () == TYPE_CODE_FLT 2667 && (type->length () 2668 != builtin_type (gdbarch)->builtin_double->length ())); 2669 } 2670 2671 static int 2672 rs6000_register_to_value (frame_info_ptr frame, 2673 int regnum, 2674 struct type *type, 2675 gdb_byte *to, 2676 int *optimizedp, int *unavailablep) 2677 { 2678 struct gdbarch *gdbarch = get_frame_arch (frame); 2679 gdb_byte from[PPC_MAX_REGISTER_SIZE]; 2680 2681 gdb_assert (type->code () == TYPE_CODE_FLT); 2682 2683 if (!get_frame_register_bytes (frame, regnum, 0, 2684 gdb::make_array_view (from, 2685 register_size (gdbarch, 2686 regnum)), 2687 optimizedp, unavailablep)) 2688 return 0; 2689 2690 target_float_convert (from, builtin_type (gdbarch)->builtin_double, 2691 to, type); 2692 *optimizedp = *unavailablep = 0; 2693 return 1; 2694 } 2695 2696 static void 2697 rs6000_value_to_register (frame_info_ptr frame, 2698 int regnum, 2699 struct type *type, 2700 const gdb_byte *from) 2701 { 2702 struct gdbarch *gdbarch = get_frame_arch (frame); 2703 gdb_byte to[PPC_MAX_REGISTER_SIZE]; 2704 2705 gdb_assert (type->code () == TYPE_CODE_FLT); 2706 2707 target_float_convert (from, type, 2708 to, builtin_type (gdbarch)->builtin_double); 2709 put_frame_register (frame, regnum, to); 2710 } 2711 2712 /* The type of a function that moves the value of REG between CACHE 2713 or BUF --- in either direction. */ 2714 typedef enum register_status (*move_ev_register_func) (struct regcache *, 2715 int, void *); 2716 2717 /* Move SPE vector register values between a 64-bit buffer and the two 2718 32-bit raw register halves in a regcache. This function handles 2719 both splitting a 64-bit value into two 32-bit halves, and joining 2720 two halves into a whole 64-bit value, depending on the function 2721 passed as the MOVE argument. 2722 2723 EV_REG must be the number of an SPE evN vector register --- a 2724 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a 2725 64-bit buffer. 2726 2727 Call MOVE once for each 32-bit half of that register, passing 2728 REGCACHE, the number of the raw register corresponding to that 2729 half, and the address of the appropriate half of BUFFER. 2730 2731 For example, passing 'regcache_raw_read' as the MOVE function will 2732 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing 2733 'regcache_raw_supply' will supply the contents of BUFFER to the 2734 appropriate pair of raw registers in REGCACHE. 2735 2736 You may need to cast away some 'const' qualifiers when passing 2737 MOVE, since this function can't tell at compile-time which of 2738 REGCACHE or BUFFER is acting as the source of the data. If C had 2739 co-variant type qualifiers, ... */ 2740 2741 static enum register_status 2742 e500_move_ev_register (move_ev_register_func move, 2743 struct regcache *regcache, int ev_reg, void *buffer) 2744 { 2745 struct gdbarch *arch = regcache->arch (); 2746 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (arch); 2747 int reg_index; 2748 gdb_byte *byte_buffer = (gdb_byte *) buffer; 2749 enum register_status status; 2750 2751 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); 2752 2753 reg_index = ev_reg - tdep->ppc_ev0_regnum; 2754 2755 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) 2756 { 2757 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, 2758 byte_buffer); 2759 if (status == REG_VALID) 2760 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, 2761 byte_buffer + 4); 2762 } 2763 else 2764 { 2765 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); 2766 if (status == REG_VALID) 2767 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, 2768 byte_buffer + 4); 2769 } 2770 2771 return status; 2772 } 2773 2774 static enum register_status 2775 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer) 2776 { 2777 regcache->raw_write (regnum, (const gdb_byte *) buffer); 2778 2779 return REG_VALID; 2780 } 2781 2782 static enum register_status 2783 e500_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 2784 int ev_reg, gdb_byte *buffer) 2785 { 2786 struct gdbarch *arch = regcache->arch (); 2787 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2788 int reg_index; 2789 enum register_status status; 2790 2791 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg)); 2792 2793 reg_index = ev_reg - tdep->ppc_ev0_regnum; 2794 2795 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG) 2796 { 2797 status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, 2798 buffer); 2799 if (status == REG_VALID) 2800 status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, 2801 buffer + 4); 2802 } 2803 else 2804 { 2805 status = regcache->raw_read (tdep->ppc_gp0_regnum + reg_index, buffer); 2806 if (status == REG_VALID) 2807 status = regcache->raw_read (tdep->ppc_ev0_upper_regnum + reg_index, 2808 buffer + 4); 2809 } 2810 2811 return status; 2812 2813 } 2814 2815 static void 2816 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2817 int reg_nr, const gdb_byte *buffer) 2818 { 2819 e500_move_ev_register (do_regcache_raw_write, regcache, 2820 reg_nr, (void *) buffer); 2821 } 2822 2823 /* Read method for DFP pseudo-registers. */ 2824 static enum register_status 2825 dfp_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 2826 int reg_nr, gdb_byte *buffer) 2827 { 2828 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2829 int reg_index, fp0; 2830 enum register_status status; 2831 2832 if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 2833 { 2834 reg_index = reg_nr - tdep->ppc_dl0_regnum; 2835 fp0 = PPC_F0_REGNUM; 2836 } 2837 else 2838 { 2839 gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); 2840 2841 reg_index = reg_nr - tdep->ppc_cdl0_regnum; 2842 fp0 = PPC_CF0_REGNUM; 2843 } 2844 2845 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2846 { 2847 /* Read two FP registers to form a whole dl register. */ 2848 status = regcache->raw_read (fp0 + 2 * reg_index, buffer); 2849 if (status == REG_VALID) 2850 status = regcache->raw_read (fp0 + 2 * reg_index + 1, 2851 buffer + 8); 2852 } 2853 else 2854 { 2855 status = regcache->raw_read (fp0 + 2 * reg_index + 1, buffer); 2856 if (status == REG_VALID) 2857 status = regcache->raw_read (fp0 + 2 * reg_index, buffer + 8); 2858 } 2859 2860 return status; 2861 } 2862 2863 /* Write method for DFP pseudo-registers. */ 2864 static void 2865 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2866 int reg_nr, const gdb_byte *buffer) 2867 { 2868 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2869 int reg_index, fp0; 2870 2871 if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 2872 { 2873 reg_index = reg_nr - tdep->ppc_dl0_regnum; 2874 fp0 = PPC_F0_REGNUM; 2875 } 2876 else 2877 { 2878 gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); 2879 2880 reg_index = reg_nr - tdep->ppc_cdl0_regnum; 2881 fp0 = PPC_CF0_REGNUM; 2882 } 2883 2884 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2885 { 2886 /* Write each half of the dl register into a separate 2887 FP register. */ 2888 regcache->raw_write (fp0 + 2 * reg_index, buffer); 2889 regcache->raw_write (fp0 + 2 * reg_index + 1, buffer + 8); 2890 } 2891 else 2892 { 2893 regcache->raw_write (fp0 + 2 * reg_index + 1, buffer); 2894 regcache->raw_write (fp0 + 2 * reg_index, buffer + 8); 2895 } 2896 } 2897 2898 /* Read method for the vX aliases for the raw vrX registers. */ 2899 2900 static enum register_status 2901 v_alias_pseudo_register_read (struct gdbarch *gdbarch, 2902 readable_regcache *regcache, int reg_nr, 2903 gdb_byte *buffer) 2904 { 2905 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2906 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); 2907 2908 return regcache->raw_read (tdep->ppc_vr0_regnum 2909 + (reg_nr - tdep->ppc_v0_alias_regnum), 2910 buffer); 2911 } 2912 2913 /* Write method for the vX aliases for the raw vrX registers. */ 2914 2915 static void 2916 v_alias_pseudo_register_write (struct gdbarch *gdbarch, 2917 struct regcache *regcache, 2918 int reg_nr, const gdb_byte *buffer) 2919 { 2920 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2921 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); 2922 2923 regcache->raw_write (tdep->ppc_vr0_regnum 2924 + (reg_nr - tdep->ppc_v0_alias_regnum), buffer); 2925 } 2926 2927 /* Read method for POWER7 VSX pseudo-registers. */ 2928 static enum register_status 2929 vsx_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 2930 int reg_nr, gdb_byte *buffer) 2931 { 2932 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2933 int reg_index, vr0, fp0, vsr0_upper; 2934 enum register_status status; 2935 2936 if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 2937 { 2938 reg_index = reg_nr - tdep->ppc_vsr0_regnum; 2939 vr0 = PPC_VR0_REGNUM; 2940 fp0 = PPC_F0_REGNUM; 2941 vsr0_upper = PPC_VSR0_UPPER_REGNUM; 2942 } 2943 else 2944 { 2945 gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); 2946 2947 reg_index = reg_nr - tdep->ppc_cvsr0_regnum; 2948 vr0 = PPC_CVR0_REGNUM; 2949 fp0 = PPC_CF0_REGNUM; 2950 vsr0_upper = PPC_CVSR0_UPPER_REGNUM; 2951 } 2952 2953 /* Read the portion that overlaps the VMX registers. */ 2954 if (reg_index > 31) 2955 status = regcache->raw_read (vr0 + reg_index - 32, buffer); 2956 else 2957 /* Read the portion that overlaps the FPR registers. */ 2958 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 2959 { 2960 status = regcache->raw_read (fp0 + reg_index, buffer); 2961 if (status == REG_VALID) 2962 status = regcache->raw_read (vsr0_upper + reg_index, 2963 buffer + 8); 2964 } 2965 else 2966 { 2967 status = regcache->raw_read (fp0 + reg_index, buffer + 8); 2968 if (status == REG_VALID) 2969 status = regcache->raw_read (vsr0_upper + reg_index, buffer); 2970 } 2971 2972 return status; 2973 } 2974 2975 /* Write method for POWER7 VSX pseudo-registers. */ 2976 static void 2977 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2978 int reg_nr, const gdb_byte *buffer) 2979 { 2980 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 2981 int reg_index, vr0, fp0, vsr0_upper; 2982 2983 if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 2984 { 2985 reg_index = reg_nr - tdep->ppc_vsr0_regnum; 2986 vr0 = PPC_VR0_REGNUM; 2987 fp0 = PPC_F0_REGNUM; 2988 vsr0_upper = PPC_VSR0_UPPER_REGNUM; 2989 } 2990 else 2991 { 2992 gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); 2993 2994 reg_index = reg_nr - tdep->ppc_cvsr0_regnum; 2995 vr0 = PPC_CVR0_REGNUM; 2996 fp0 = PPC_CF0_REGNUM; 2997 vsr0_upper = PPC_CVSR0_UPPER_REGNUM; 2998 } 2999 3000 /* Write the portion that overlaps the VMX registers. */ 3001 if (reg_index > 31) 3002 regcache->raw_write (vr0 + reg_index - 32, buffer); 3003 else 3004 /* Write the portion that overlaps the FPR registers. */ 3005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 3006 { 3007 regcache->raw_write (fp0 + reg_index, buffer); 3008 regcache->raw_write (vsr0_upper + reg_index, buffer + 8); 3009 } 3010 else 3011 { 3012 regcache->raw_write (fp0 + reg_index, buffer + 8); 3013 regcache->raw_write (vsr0_upper + reg_index, buffer); 3014 } 3015 } 3016 3017 /* Read method for POWER7 Extended FP pseudo-registers. */ 3018 static enum register_status 3019 efp_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 3020 int reg_nr, gdb_byte *buffer) 3021 { 3022 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3023 int reg_index, vr0; 3024 3025 if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 3026 { 3027 reg_index = reg_nr - tdep->ppc_efpr0_regnum; 3028 vr0 = PPC_VR0_REGNUM; 3029 } 3030 else 3031 { 3032 gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); 3033 3034 reg_index = reg_nr - tdep->ppc_cefpr0_regnum; 3035 vr0 = PPC_CVR0_REGNUM; 3036 } 3037 3038 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; 3039 3040 /* Read the portion that overlaps the VMX register. */ 3041 return regcache->raw_read_part (vr0 + reg_index, offset, 3042 register_size (gdbarch, reg_nr), 3043 buffer); 3044 } 3045 3046 /* Write method for POWER7 Extended FP pseudo-registers. */ 3047 static void 3048 efp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 3049 int reg_nr, const gdb_byte *buffer) 3050 { 3051 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3052 int reg_index, vr0; 3053 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8; 3054 3055 if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 3056 { 3057 reg_index = reg_nr - tdep->ppc_efpr0_regnum; 3058 vr0 = PPC_VR0_REGNUM; 3059 } 3060 else 3061 { 3062 gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); 3063 3064 reg_index = reg_nr - tdep->ppc_cefpr0_regnum; 3065 vr0 = PPC_CVR0_REGNUM; 3066 3067 /* The call to raw_write_part fails silently if the initial read 3068 of the read-update-write sequence returns an invalid status, 3069 so we check this manually and throw an error if needed. */ 3070 regcache->raw_update (vr0 + reg_index); 3071 if (regcache->get_register_status (vr0 + reg_index) != REG_VALID) 3072 error (_("Cannot write to the checkpointed EFP register, " 3073 "the corresponding vector register is unavailable.")); 3074 } 3075 3076 /* Write the portion that overlaps the VMX register. */ 3077 regcache->raw_write_part (vr0 + reg_index, offset, 3078 register_size (gdbarch, reg_nr), buffer); 3079 } 3080 3081 static enum register_status 3082 rs6000_pseudo_register_read (struct gdbarch *gdbarch, 3083 readable_regcache *regcache, 3084 int reg_nr, gdb_byte *buffer) 3085 { 3086 struct gdbarch *regcache_arch = regcache->arch (); 3087 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3088 3089 gdb_assert (regcache_arch == gdbarch); 3090 3091 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 3092 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 3093 else if (IS_DFP_PSEUDOREG (tdep, reg_nr) 3094 || IS_CDFP_PSEUDOREG (tdep, reg_nr)) 3095 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 3096 else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) 3097 return v_alias_pseudo_register_read (gdbarch, regcache, reg_nr, 3098 buffer); 3099 else if (IS_VSX_PSEUDOREG (tdep, reg_nr) 3100 || IS_CVSX_PSEUDOREG (tdep, reg_nr)) 3101 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 3102 else if (IS_EFP_PSEUDOREG (tdep, reg_nr) 3103 || IS_CEFP_PSEUDOREG (tdep, reg_nr)) 3104 return efp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer); 3105 else 3106 internal_error (_("rs6000_pseudo_register_read: " 3107 "called on unexpected register '%s' (%d)"), 3108 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 3109 } 3110 3111 static void 3112 rs6000_pseudo_register_write (struct gdbarch *gdbarch, 3113 struct regcache *regcache, 3114 int reg_nr, const gdb_byte *buffer) 3115 { 3116 struct gdbarch *regcache_arch = regcache->arch (); 3117 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3118 3119 gdb_assert (regcache_arch == gdbarch); 3120 3121 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 3122 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 3123 else if (IS_DFP_PSEUDOREG (tdep, reg_nr) 3124 || IS_CDFP_PSEUDOREG (tdep, reg_nr)) 3125 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 3126 else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) 3127 v_alias_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 3128 else if (IS_VSX_PSEUDOREG (tdep, reg_nr) 3129 || IS_CVSX_PSEUDOREG (tdep, reg_nr)) 3130 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 3131 else if (IS_EFP_PSEUDOREG (tdep, reg_nr) 3132 || IS_CEFP_PSEUDOREG (tdep, reg_nr)) 3133 efp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer); 3134 else 3135 internal_error (_("rs6000_pseudo_register_write: " 3136 "called on unexpected register '%s' (%d)"), 3137 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 3138 } 3139 3140 /* Set the register mask in AX with the registers that form the DFP or 3141 checkpointed DFP pseudo-register REG_NR. */ 3142 3143 static void 3144 dfp_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3145 struct agent_expr *ax, int reg_nr) 3146 { 3147 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3148 int reg_index, fp0; 3149 3150 if (IS_DFP_PSEUDOREG (tdep, reg_nr)) 3151 { 3152 reg_index = reg_nr - tdep->ppc_dl0_regnum; 3153 fp0 = PPC_F0_REGNUM; 3154 } 3155 else 3156 { 3157 gdb_assert (IS_CDFP_PSEUDOREG (tdep, reg_nr)); 3158 3159 reg_index = reg_nr - tdep->ppc_cdl0_regnum; 3160 fp0 = PPC_CF0_REGNUM; 3161 } 3162 3163 ax_reg_mask (ax, fp0 + 2 * reg_index); 3164 ax_reg_mask (ax, fp0 + 2 * reg_index + 1); 3165 } 3166 3167 /* Set the register mask in AX with the raw vector register that 3168 corresponds to its REG_NR alias. */ 3169 3170 static void 3171 v_alias_pseudo_register_collect (struct gdbarch *gdbarch, 3172 struct agent_expr *ax, int reg_nr) 3173 { 3174 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3175 gdb_assert (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)); 3176 3177 ax_reg_mask (ax, tdep->ppc_vr0_regnum 3178 + (reg_nr - tdep->ppc_v0_alias_regnum)); 3179 } 3180 3181 /* Set the register mask in AX with the registers that form the VSX or 3182 checkpointed VSX pseudo-register REG_NR. */ 3183 3184 static void 3185 vsx_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3186 struct agent_expr *ax, int reg_nr) 3187 { 3188 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3189 int reg_index, vr0, fp0, vsr0_upper; 3190 3191 if (IS_VSX_PSEUDOREG (tdep, reg_nr)) 3192 { 3193 reg_index = reg_nr - tdep->ppc_vsr0_regnum; 3194 vr0 = PPC_VR0_REGNUM; 3195 fp0 = PPC_F0_REGNUM; 3196 vsr0_upper = PPC_VSR0_UPPER_REGNUM; 3197 } 3198 else 3199 { 3200 gdb_assert (IS_CVSX_PSEUDOREG (tdep, reg_nr)); 3201 3202 reg_index = reg_nr - tdep->ppc_cvsr0_regnum; 3203 vr0 = PPC_CVR0_REGNUM; 3204 fp0 = PPC_CF0_REGNUM; 3205 vsr0_upper = PPC_CVSR0_UPPER_REGNUM; 3206 } 3207 3208 if (reg_index > 31) 3209 { 3210 ax_reg_mask (ax, vr0 + reg_index - 32); 3211 } 3212 else 3213 { 3214 ax_reg_mask (ax, fp0 + reg_index); 3215 ax_reg_mask (ax, vsr0_upper + reg_index); 3216 } 3217 } 3218 3219 /* Set the register mask in AX with the register that corresponds to 3220 the EFP or checkpointed EFP pseudo-register REG_NR. */ 3221 3222 static void 3223 efp_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3224 struct agent_expr *ax, int reg_nr) 3225 { 3226 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3227 int reg_index, vr0; 3228 3229 if (IS_EFP_PSEUDOREG (tdep, reg_nr)) 3230 { 3231 reg_index = reg_nr - tdep->ppc_efpr0_regnum; 3232 vr0 = PPC_VR0_REGNUM; 3233 } 3234 else 3235 { 3236 gdb_assert (IS_CEFP_PSEUDOREG (tdep, reg_nr)); 3237 3238 reg_index = reg_nr - tdep->ppc_cefpr0_regnum; 3239 vr0 = PPC_CVR0_REGNUM; 3240 } 3241 3242 ax_reg_mask (ax, vr0 + reg_index); 3243 } 3244 3245 static int 3246 rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch, 3247 struct agent_expr *ax, int reg_nr) 3248 { 3249 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3250 if (IS_SPE_PSEUDOREG (tdep, reg_nr)) 3251 { 3252 int reg_index = reg_nr - tdep->ppc_ev0_regnum; 3253 ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index); 3254 ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index); 3255 } 3256 else if (IS_DFP_PSEUDOREG (tdep, reg_nr) 3257 || IS_CDFP_PSEUDOREG (tdep, reg_nr)) 3258 { 3259 dfp_ax_pseudo_register_collect (gdbarch, ax, reg_nr); 3260 } 3261 else if (IS_V_ALIAS_PSEUDOREG (tdep, reg_nr)) 3262 { 3263 v_alias_pseudo_register_collect (gdbarch, ax, reg_nr); 3264 } 3265 else if (IS_VSX_PSEUDOREG (tdep, reg_nr) 3266 || IS_CVSX_PSEUDOREG (tdep, reg_nr)) 3267 { 3268 vsx_ax_pseudo_register_collect (gdbarch, ax, reg_nr); 3269 } 3270 else if (IS_EFP_PSEUDOREG (tdep, reg_nr) 3271 || IS_CEFP_PSEUDOREG (tdep, reg_nr)) 3272 { 3273 efp_ax_pseudo_register_collect (gdbarch, ax, reg_nr); 3274 } 3275 else 3276 internal_error (_("rs6000_pseudo_register_collect: " 3277 "called on unexpected register '%s' (%d)"), 3278 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 3279 return 0; 3280 } 3281 3282 3283 static void 3284 rs6000_gen_return_address (struct gdbarch *gdbarch, 3285 struct agent_expr *ax, struct axs_value *value, 3286 CORE_ADDR scope) 3287 { 3288 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3289 value->type = register_type (gdbarch, tdep->ppc_lr_regnum); 3290 value->kind = axs_lvalue_register; 3291 value->u.reg = tdep->ppc_lr_regnum; 3292 } 3293 3294 3295 /* Convert a DBX STABS register number to a GDB register number. */ 3296 static int 3297 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) 3298 { 3299 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3300 3301 if (0 <= num && num <= 31) 3302 return tdep->ppc_gp0_regnum + num; 3303 else if (32 <= num && num <= 63) 3304 /* FIXME: jimb/2004-05-05: What should we do when the debug info 3305 specifies registers the architecture doesn't have? Our 3306 callers don't check the value we return. */ 3307 return tdep->ppc_fp0_regnum + (num - 32); 3308 else if (77 <= num && num <= 108) 3309 return tdep->ppc_vr0_regnum + (num - 77); 3310 else if (1200 <= num && num < 1200 + 32) 3311 return tdep->ppc_ev0_upper_regnum + (num - 1200); 3312 else 3313 switch (num) 3314 { 3315 case 64: 3316 return tdep->ppc_mq_regnum; 3317 case 65: 3318 return tdep->ppc_lr_regnum; 3319 case 66: 3320 return tdep->ppc_ctr_regnum; 3321 case 76: 3322 return tdep->ppc_xer_regnum; 3323 case 109: 3324 return tdep->ppc_vrsave_regnum; 3325 case 110: 3326 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 3327 case 111: 3328 return tdep->ppc_acc_regnum; 3329 case 112: 3330 return tdep->ppc_spefscr_regnum; 3331 default: 3332 return num; 3333 } 3334 } 3335 3336 3337 /* Convert a Dwarf 2 register number to a GDB register number. */ 3338 static int 3339 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num) 3340 { 3341 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3342 3343 if (0 <= num && num <= 31) 3344 return tdep->ppc_gp0_regnum + num; 3345 else if (32 <= num && num <= 63) 3346 /* FIXME: jimb/2004-05-05: What should we do when the debug info 3347 specifies registers the architecture doesn't have? Our 3348 callers don't check the value we return. */ 3349 return tdep->ppc_fp0_regnum + (num - 32); 3350 else if (1124 <= num && num < 1124 + 32) 3351 return tdep->ppc_vr0_regnum + (num - 1124); 3352 else if (1200 <= num && num < 1200 + 32) 3353 return tdep->ppc_ev0_upper_regnum + (num - 1200); 3354 else 3355 switch (num) 3356 { 3357 case 64: 3358 return tdep->ppc_cr_regnum; 3359 case 67: 3360 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 3361 case 99: 3362 return tdep->ppc_acc_regnum; 3363 case 100: 3364 return tdep->ppc_mq_regnum; 3365 case 101: 3366 return tdep->ppc_xer_regnum; 3367 case 108: 3368 return tdep->ppc_lr_regnum; 3369 case 109: 3370 return tdep->ppc_ctr_regnum; 3371 case 356: 3372 return tdep->ppc_vrsave_regnum; 3373 case 612: 3374 return tdep->ppc_spefscr_regnum; 3375 } 3376 3377 /* Unknown DWARF register number. */ 3378 return -1; 3379 } 3380 3381 /* Translate a .eh_frame register to DWARF register, or adjust a 3382 .debug_frame register. */ 3383 3384 static int 3385 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) 3386 { 3387 /* GCC releases before 3.4 use GCC internal register numbering in 3388 .debug_frame (and .debug_info, et cetera). The numbering is 3389 different from the standard SysV numbering for everything except 3390 for GPRs and FPRs. We can not detect this problem in most cases 3391 - to get accurate debug info for variables living in lr, ctr, v0, 3392 et cetera, use a newer version of GCC. But we must detect 3393 one important case - lr is in column 65 in .debug_frame output, 3394 instead of 108. 3395 3396 GCC 3.4, and the "hammer" branch, have a related problem. They 3397 record lr register saves in .debug_frame as 108, but still record 3398 the return column as 65. We fix that up too. 3399 3400 We can do this because 65 is assigned to fpsr, and GCC never 3401 generates debug info referring to it. To add support for 3402 handwritten debug info that restores fpsr, we would need to add a 3403 producer version check to this. */ 3404 if (!eh_frame_p) 3405 { 3406 if (num == 65) 3407 return 108; 3408 else 3409 return num; 3410 } 3411 3412 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC 3413 internal register numbering; translate that to the standard DWARF2 3414 register numbering. */ 3415 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ 3416 return num; 3417 else if (68 <= num && num <= 75) /* cr0-cr8 */ 3418 return num - 68 + 86; 3419 else if (77 <= num && num <= 108) /* vr0-vr31 */ 3420 return num - 77 + 1124; 3421 else 3422 switch (num) 3423 { 3424 case 64: /* mq */ 3425 return 100; 3426 case 65: /* lr */ 3427 return 108; 3428 case 66: /* ctr */ 3429 return 109; 3430 case 76: /* xer */ 3431 return 101; 3432 case 109: /* vrsave */ 3433 return 356; 3434 case 110: /* vscr */ 3435 return 67; 3436 case 111: /* spe_acc */ 3437 return 99; 3438 case 112: /* spefscr */ 3439 return 612; 3440 default: 3441 return num; 3442 } 3443 } 3444 3445 3446 /* Handling the various POWER/PowerPC variants. */ 3447 3448 /* Information about a particular processor variant. */ 3449 3450 struct ppc_variant 3451 { 3452 /* Name of this variant. */ 3453 const char *name; 3454 3455 /* English description of the variant. */ 3456 const char *description; 3457 3458 /* bfd_arch_info.arch corresponding to variant. */ 3459 enum bfd_architecture arch; 3460 3461 /* bfd_arch_info.mach corresponding to variant. */ 3462 unsigned long mach; 3463 3464 /* Target description for this variant. */ 3465 const struct target_desc **tdesc; 3466 }; 3467 3468 static struct ppc_variant variants[] = 3469 { 3470 {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 3471 bfd_mach_ppc, &tdesc_powerpc_altivec32}, 3472 {"power", "POWER user-level", bfd_arch_rs6000, 3473 bfd_mach_rs6k, &tdesc_rs6000}, 3474 {"403", "IBM PowerPC 403", bfd_arch_powerpc, 3475 bfd_mach_ppc_403, &tdesc_powerpc_403}, 3476 {"405", "IBM PowerPC 405", bfd_arch_powerpc, 3477 bfd_mach_ppc_405, &tdesc_powerpc_405}, 3478 {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 3479 bfd_mach_ppc_601, &tdesc_powerpc_601}, 3480 {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 3481 bfd_mach_ppc_602, &tdesc_powerpc_602}, 3482 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 3483 bfd_mach_ppc_603, &tdesc_powerpc_603}, 3484 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 3485 604, &tdesc_powerpc_604}, 3486 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 3487 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc}, 3488 {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 3489 bfd_mach_ppc_505, &tdesc_powerpc_505}, 3490 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 3491 bfd_mach_ppc_860, &tdesc_powerpc_860}, 3492 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 3493 bfd_mach_ppc_750, &tdesc_powerpc_750}, 3494 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 3495 bfd_mach_ppc_7400, &tdesc_powerpc_7400}, 3496 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 3497 bfd_mach_ppc_e500, &tdesc_powerpc_e500}, 3498 3499 /* 64-bit */ 3500 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 3501 bfd_mach_ppc64, &tdesc_powerpc_altivec64}, 3502 {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 3503 bfd_mach_ppc_620, &tdesc_powerpc_64}, 3504 {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 3505 bfd_mach_ppc_630, &tdesc_powerpc_64}, 3506 {"a35", "PowerPC A35", bfd_arch_powerpc, 3507 bfd_mach_ppc_a35, &tdesc_powerpc_64}, 3508 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 3509 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64}, 3510 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 3511 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64}, 3512 3513 /* FIXME: I haven't checked the register sets of the following. */ 3514 {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 3515 bfd_mach_rs6k_rs1, &tdesc_rs6000}, 3516 {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 3517 bfd_mach_rs6k_rsc, &tdesc_rs6000}, 3518 {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 3519 bfd_mach_rs6k_rs2, &tdesc_rs6000}, 3520 3521 {0, 0, (enum bfd_architecture) 0, 0, 0} 3522 }; 3523 3524 /* Return the variant corresponding to architecture ARCH and machine number 3525 MACH. If no such variant exists, return null. */ 3526 3527 static const struct ppc_variant * 3528 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 3529 { 3530 const struct ppc_variant *v; 3531 3532 for (v = variants; v->name; v++) 3533 if (arch == v->arch && mach == v->mach) 3534 return v; 3535 3536 return NULL; 3537 } 3538 3539 3540 3541 struct rs6000_frame_cache 3542 { 3543 CORE_ADDR base; 3544 CORE_ADDR initial_sp; 3545 trad_frame_saved_reg *saved_regs; 3546 3547 /* Set BASE_P to true if this frame cache is properly initialized. 3548 Otherwise set to false because some registers or memory cannot 3549 collected. */ 3550 int base_p; 3551 /* Cache PC for building unavailable frame. */ 3552 CORE_ADDR pc; 3553 }; 3554 3555 static struct rs6000_frame_cache * 3556 rs6000_frame_cache (frame_info_ptr this_frame, void **this_cache) 3557 { 3558 struct rs6000_frame_cache *cache; 3559 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3560 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3561 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 3562 struct rs6000_framedata fdata; 3563 int wordsize = tdep->wordsize; 3564 CORE_ADDR func = 0, pc = 0; 3565 3566 if ((*this_cache) != NULL) 3567 return (struct rs6000_frame_cache *) (*this_cache); 3568 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 3569 (*this_cache) = cache; 3570 cache->pc = 0; 3571 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3572 3573 try 3574 { 3575 func = get_frame_func (this_frame); 3576 cache->pc = func; 3577 pc = get_frame_pc (this_frame); 3578 skip_prologue (gdbarch, func, pc, &fdata); 3579 3580 /* Figure out the parent's stack pointer. */ 3581 3582 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 3583 address of the current frame. Things might be easier if the 3584 ->frame pointed to the outer-most address of the frame. In 3585 the mean time, the address of the prev frame is used as the 3586 base address of this frame. */ 3587 cache->base = get_frame_register_unsigned 3588 (this_frame, gdbarch_sp_regnum (gdbarch)); 3589 } 3590 catch (const gdb_exception_error &ex) 3591 { 3592 if (ex.error != NOT_AVAILABLE_ERROR) 3593 throw; 3594 return (struct rs6000_frame_cache *) (*this_cache); 3595 } 3596 3597 /* If the function appears to be frameless, check a couple of likely 3598 indicators that we have simply failed to find the frame setup. 3599 Two common cases of this are missing symbols (i.e. 3600 get_frame_func returns the wrong address or 0), and assembly 3601 stubs which have a fast exit path but set up a frame on the slow 3602 path. 3603 3604 If the LR appears to return to this function, then presume that 3605 we have an ABI compliant frame that we failed to find. */ 3606 if (fdata.frameless && fdata.lr_offset == 0) 3607 { 3608 CORE_ADDR saved_lr; 3609 int make_frame = 0; 3610 3611 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); 3612 if (func == 0 && saved_lr == pc) 3613 make_frame = 1; 3614 else if (func != 0) 3615 { 3616 CORE_ADDR saved_func = get_pc_function_start (saved_lr); 3617 if (func == saved_func) 3618 make_frame = 1; 3619 } 3620 3621 if (make_frame) 3622 { 3623 fdata.frameless = 0; 3624 fdata.lr_offset = tdep->lr_frame_offset; 3625 } 3626 } 3627 3628 if (!fdata.frameless) 3629 { 3630 /* Frameless really means stackless. */ 3631 ULONGEST backchain; 3632 3633 if (safe_read_memory_unsigned_integer (cache->base, wordsize, 3634 byte_order, &backchain)) 3635 cache->base = (CORE_ADDR) backchain; 3636 } 3637 3638 cache->saved_regs[gdbarch_sp_regnum (gdbarch)].set_value (cache->base); 3639 3640 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. 3641 All fpr's from saved_fpr to fp31 are saved. */ 3642 3643 if (fdata.saved_fpr >= 0) 3644 { 3645 int i; 3646 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; 3647 3648 /* If skip_prologue says floating-point registers were saved, 3649 but the current architecture has no floating-point registers, 3650 then that's strange. But we have no indices to even record 3651 the addresses under, so we just ignore it. */ 3652 if (ppc_floating_point_unit_p (gdbarch)) 3653 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) 3654 { 3655 cache->saved_regs[tdep->ppc_fp0_regnum + i].set_addr (fpr_addr); 3656 fpr_addr += 8; 3657 } 3658 } 3659 3660 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. 3661 All gpr's from saved_gpr to gpr31 are saved (except during the 3662 prologue). */ 3663 3664 if (fdata.saved_gpr >= 0) 3665 { 3666 int i; 3667 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; 3668 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) 3669 { 3670 if (fdata.gpr_mask & (1U << i)) 3671 cache->saved_regs[tdep->ppc_gp0_regnum + i].set_addr (gpr_addr); 3672 gpr_addr += wordsize; 3673 } 3674 } 3675 3676 /* if != -1, fdata.saved_vr is the smallest number of saved_vr. 3677 All vr's from saved_vr to vr31 are saved. */ 3678 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 3679 { 3680 if (fdata.saved_vr >= 0) 3681 { 3682 int i; 3683 CORE_ADDR vr_addr = cache->base + fdata.vr_offset; 3684 for (i = fdata.saved_vr; i < 32; i++) 3685 { 3686 cache->saved_regs[tdep->ppc_vr0_regnum + i].set_addr (vr_addr); 3687 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); 3688 } 3689 } 3690 } 3691 3692 /* if != -1, fdata.saved_ev is the smallest number of saved_ev. 3693 All vr's from saved_ev to ev31 are saved. ????? */ 3694 if (tdep->ppc_ev0_regnum != -1) 3695 { 3696 if (fdata.saved_ev >= 0) 3697 { 3698 int i; 3699 CORE_ADDR ev_addr = cache->base + fdata.ev_offset; 3700 CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0); 3701 3702 for (i = fdata.saved_ev; i < ppc_num_gprs; i++) 3703 { 3704 cache->saved_regs[tdep->ppc_ev0_regnum + i].set_addr (ev_addr); 3705 cache->saved_regs[tdep->ppc_gp0_regnum + i].set_addr (ev_addr 3706 + off); 3707 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); 3708 } 3709 } 3710 } 3711 3712 /* If != 0, fdata.cr_offset is the offset from the frame that 3713 holds the CR. */ 3714 if (fdata.cr_offset != 0) 3715 cache->saved_regs[tdep->ppc_cr_regnum].set_addr (cache->base 3716 + fdata.cr_offset); 3717 3718 /* If != 0, fdata.lr_offset is the offset from the frame that 3719 holds the LR. */ 3720 if (fdata.lr_offset != 0) 3721 cache->saved_regs[tdep->ppc_lr_regnum].set_addr (cache->base 3722 + fdata.lr_offset); 3723 else if (fdata.lr_register != -1) 3724 cache->saved_regs[tdep->ppc_lr_regnum].set_realreg (fdata.lr_register); 3725 /* The PC is found in the link register. */ 3726 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] = 3727 cache->saved_regs[tdep->ppc_lr_regnum]; 3728 3729 /* If != 0, fdata.vrsave_offset is the offset from the frame that 3730 holds the VRSAVE. */ 3731 if (fdata.vrsave_offset != 0) 3732 cache->saved_regs[tdep->ppc_vrsave_regnum].set_addr (cache->base 3733 + fdata.vrsave_offset); 3734 3735 if (fdata.alloca_reg < 0) 3736 /* If no alloca register used, then fi->frame is the value of the 3737 %sp for this frame, and it is good enough. */ 3738 cache->initial_sp 3739 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 3740 else 3741 cache->initial_sp 3742 = get_frame_register_unsigned (this_frame, fdata.alloca_reg); 3743 3744 cache->base_p = 1; 3745 return cache; 3746 } 3747 3748 static void 3749 rs6000_frame_this_id (frame_info_ptr this_frame, void **this_cache, 3750 struct frame_id *this_id) 3751 { 3752 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3753 this_cache); 3754 3755 if (!info->base_p) 3756 { 3757 (*this_id) = frame_id_build_unavailable_stack (info->pc); 3758 return; 3759 } 3760 3761 /* This marks the outermost frame. */ 3762 if (info->base == 0) 3763 return; 3764 3765 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3766 } 3767 3768 static struct value * 3769 rs6000_frame_prev_register (frame_info_ptr this_frame, 3770 void **this_cache, int regnum) 3771 { 3772 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3773 this_cache); 3774 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3775 } 3776 3777 static const struct frame_unwind rs6000_frame_unwind = 3778 { 3779 "rs6000 prologue", 3780 NORMAL_FRAME, 3781 default_frame_unwind_stop_reason, 3782 rs6000_frame_this_id, 3783 rs6000_frame_prev_register, 3784 NULL, 3785 default_frame_sniffer 3786 }; 3787 3788 /* Allocate and initialize a frame cache for an epilogue frame. 3789 SP is restored and prev-PC is stored in LR. */ 3790 3791 static struct rs6000_frame_cache * 3792 rs6000_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache) 3793 { 3794 struct rs6000_frame_cache *cache; 3795 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3796 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3797 3798 if (*this_cache) 3799 return (struct rs6000_frame_cache *) *this_cache; 3800 3801 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 3802 (*this_cache) = cache; 3803 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3804 3805 try 3806 { 3807 /* At this point the stack looks as if we just entered the 3808 function, and the return address is stored in LR. */ 3809 CORE_ADDR sp, lr; 3810 3811 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch)); 3812 lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum); 3813 3814 cache->base = sp; 3815 cache->initial_sp = sp; 3816 3817 cache->saved_regs[gdbarch_pc_regnum (gdbarch)].set_value (lr); 3818 } 3819 catch (const gdb_exception_error &ex) 3820 { 3821 if (ex.error != NOT_AVAILABLE_ERROR) 3822 throw; 3823 } 3824 3825 return cache; 3826 } 3827 3828 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h. 3829 Return the frame ID of an epilogue frame. */ 3830 3831 static void 3832 rs6000_epilogue_frame_this_id (frame_info_ptr this_frame, 3833 void **this_cache, struct frame_id *this_id) 3834 { 3835 CORE_ADDR pc; 3836 struct rs6000_frame_cache *info = 3837 rs6000_epilogue_frame_cache (this_frame, this_cache); 3838 3839 pc = get_frame_func (this_frame); 3840 if (info->base == 0) 3841 (*this_id) = frame_id_build_unavailable_stack (pc); 3842 else 3843 (*this_id) = frame_id_build (info->base, pc); 3844 } 3845 3846 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h. 3847 Return the register value of REGNUM in previous frame. */ 3848 3849 static struct value * 3850 rs6000_epilogue_frame_prev_register (frame_info_ptr this_frame, 3851 void **this_cache, int regnum) 3852 { 3853 struct rs6000_frame_cache *info = 3854 rs6000_epilogue_frame_cache (this_frame, this_cache); 3855 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3856 } 3857 3858 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h. 3859 Check whether this an epilogue frame. */ 3860 3861 static int 3862 rs6000_epilogue_frame_sniffer (const struct frame_unwind *self, 3863 frame_info_ptr this_frame, 3864 void **this_prologue_cache) 3865 { 3866 if (frame_relative_level (this_frame) == 0) 3867 return rs6000_in_function_epilogue_frame_p (this_frame, 3868 get_frame_arch (this_frame), 3869 get_frame_pc (this_frame)); 3870 else 3871 return 0; 3872 } 3873 3874 /* Frame unwinder for epilogue frame. This is required for reverse step-over 3875 a function without debug information. */ 3876 3877 static const struct frame_unwind rs6000_epilogue_frame_unwind = 3878 { 3879 "rs6000 epilogue", 3880 NORMAL_FRAME, 3881 default_frame_unwind_stop_reason, 3882 rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register, 3883 NULL, 3884 rs6000_epilogue_frame_sniffer 3885 }; 3886 3887 3888 static CORE_ADDR 3889 rs6000_frame_base_address (frame_info_ptr this_frame, void **this_cache) 3890 { 3891 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame, 3892 this_cache); 3893 return info->initial_sp; 3894 } 3895 3896 static const struct frame_base rs6000_frame_base = { 3897 &rs6000_frame_unwind, 3898 rs6000_frame_base_address, 3899 rs6000_frame_base_address, 3900 rs6000_frame_base_address 3901 }; 3902 3903 static const struct frame_base * 3904 rs6000_frame_base_sniffer (frame_info_ptr this_frame) 3905 { 3906 return &rs6000_frame_base; 3907 } 3908 3909 /* DWARF-2 frame support. Used to handle the detection of 3910 clobbered registers during function calls. */ 3911 3912 static void 3913 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 3914 struct dwarf2_frame_state_reg *reg, 3915 frame_info_ptr this_frame) 3916 { 3917 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 3918 3919 /* PPC32 and PPC64 ABI's are the same regarding volatile and 3920 non-volatile registers. We will use the same code for both. */ 3921 3922 /* Call-saved GP registers. */ 3923 if ((regnum >= tdep->ppc_gp0_regnum + 14 3924 && regnum <= tdep->ppc_gp0_regnum + 31) 3925 || (regnum == tdep->ppc_gp0_regnum + 1)) 3926 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3927 3928 /* Call-clobbered GP registers. */ 3929 if ((regnum >= tdep->ppc_gp0_regnum + 3 3930 && regnum <= tdep->ppc_gp0_regnum + 12) 3931 || (regnum == tdep->ppc_gp0_regnum)) 3932 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3933 3934 /* Deal with FP registers, if supported. */ 3935 if (tdep->ppc_fp0_regnum >= 0) 3936 { 3937 /* Call-saved FP registers. */ 3938 if ((regnum >= tdep->ppc_fp0_regnum + 14 3939 && regnum <= tdep->ppc_fp0_regnum + 31)) 3940 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3941 3942 /* Call-clobbered FP registers. */ 3943 if ((regnum >= tdep->ppc_fp0_regnum 3944 && regnum <= tdep->ppc_fp0_regnum + 13)) 3945 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3946 } 3947 3948 /* Deal with ALTIVEC registers, if supported. */ 3949 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) 3950 { 3951 /* Call-saved Altivec registers. */ 3952 if ((regnum >= tdep->ppc_vr0_regnum + 20 3953 && regnum <= tdep->ppc_vr0_regnum + 31) 3954 || regnum == tdep->ppc_vrsave_regnum) 3955 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3956 3957 /* Call-clobbered Altivec registers. */ 3958 if ((regnum >= tdep->ppc_vr0_regnum 3959 && regnum <= tdep->ppc_vr0_regnum + 19)) 3960 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3961 } 3962 3963 /* Handle PC register and Stack Pointer correctly. */ 3964 if (regnum == gdbarch_pc_regnum (gdbarch)) 3965 reg->how = DWARF2_FRAME_REG_RA; 3966 else if (regnum == gdbarch_sp_regnum (gdbarch)) 3967 reg->how = DWARF2_FRAME_REG_CFA; 3968 } 3969 3970 3971 /* Return true if a .gnu_attributes section exists in BFD and it 3972 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo 3973 section exists in BFD and it indicates that SPE extensions are in 3974 use. Check the .gnu.attributes section first, as the binary might be 3975 compiled for SPE, but not actually using SPE instructions. */ 3976 3977 static int 3978 bfd_uses_spe_extensions (bfd *abfd) 3979 { 3980 asection *sect; 3981 gdb_byte *contents = NULL; 3982 bfd_size_type size; 3983 gdb_byte *ptr; 3984 int success = 0; 3985 3986 if (!abfd) 3987 return 0; 3988 3989 #ifdef HAVE_ELF 3990 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user 3991 could be using the SPE vector abi without actually using any spe 3992 bits whatsoever. But it's close enough for now. */ 3993 int vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU, 3994 Tag_GNU_Power_ABI_Vector); 3995 if (vector_abi == 3) 3996 return 1; 3997 #endif 3998 3999 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo"); 4000 if (!sect) 4001 return 0; 4002 4003 size = bfd_section_size (sect); 4004 contents = (gdb_byte *) xmalloc (size); 4005 if (!bfd_get_section_contents (abfd, sect, contents, 0, size)) 4006 { 4007 xfree (contents); 4008 return 0; 4009 } 4010 4011 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows: 4012 4013 struct { 4014 uint32 name_len; 4015 uint32 data_len; 4016 uint32 type; 4017 char name[name_len rounded up to 4-byte alignment]; 4018 char data[data_len]; 4019 }; 4020 4021 Technically, there's only supposed to be one such structure in a 4022 given apuinfo section, but the linker is not always vigilant about 4023 merging apuinfo sections from input files. Just go ahead and parse 4024 them all, exiting early when we discover the binary uses SPE 4025 insns. 4026 4027 It's not specified in what endianness the information in this 4028 section is stored. Assume that it's the endianness of the BFD. */ 4029 ptr = contents; 4030 while (1) 4031 { 4032 unsigned int name_len; 4033 unsigned int data_len; 4034 unsigned int type; 4035 4036 /* If we can't read the first three fields, we're done. */ 4037 if (size < 12) 4038 break; 4039 4040 name_len = bfd_get_32 (abfd, ptr); 4041 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */ 4042 data_len = bfd_get_32 (abfd, ptr + 4); 4043 type = bfd_get_32 (abfd, ptr + 8); 4044 ptr += 12; 4045 4046 /* The name must be "APUinfo\0". */ 4047 if (name_len != 8 4048 && strcmp ((const char *) ptr, "APUinfo") != 0) 4049 break; 4050 ptr += name_len; 4051 4052 /* The type must be 2. */ 4053 if (type != 2) 4054 break; 4055 4056 /* The data is stored as a series of uint32. The upper half of 4057 each uint32 indicates the particular APU used and the lower 4058 half indicates the revision of that APU. We just care about 4059 the upper half. */ 4060 4061 /* Not 4-byte quantities. */ 4062 if (data_len & 3U) 4063 break; 4064 4065 while (data_len) 4066 { 4067 unsigned int apuinfo = bfd_get_32 (abfd, ptr); 4068 unsigned int apu = apuinfo >> 16; 4069 ptr += 4; 4070 data_len -= 4; 4071 4072 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept 4073 either. */ 4074 if (apu == 0x100 || apu == 0x101) 4075 { 4076 success = 1; 4077 data_len = 0; 4078 } 4079 } 4080 4081 if (success) 4082 break; 4083 } 4084 4085 xfree (contents); 4086 return success; 4087 } 4088 4089 /* These are macros for parsing instruction fields (I.1.6.28) */ 4090 4091 #define PPC_FIELD(value, from, len) \ 4092 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1)) 4093 #define PPC_SEXT(v, bs) \ 4094 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \ 4095 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \ 4096 - ((CORE_ADDR) 1 << ((bs) - 1))) 4097 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6) 4098 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10) 4099 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5) 4100 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5) 4101 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5) 4102 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5) 4103 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5) 4104 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5) 4105 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5) 4106 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \ 4107 | (PPC_FIELD (insn, 16, 5) << 5)) 4108 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5) 4109 #define PPC_T(insn) PPC_FIELD (insn, 6, 5) 4110 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16) 4111 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14) 4112 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12) 4113 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0) 4114 #define PPC_OE(insn) PPC_BIT (insn, 21) 4115 #define PPC_RC(insn) PPC_BIT (insn, 31) 4116 #define PPC_Rc(insn) PPC_BIT (insn, 21) 4117 #define PPC_LK(insn) PPC_BIT (insn, 31) 4118 #define PPC_TX(insn) PPC_BIT (insn, 31) 4119 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7) 4120 4121 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn)) 4122 #define PPC_XTp(insn) ((PPC_BIT (insn, 10) << 5) \ 4123 | PPC_FIELD (insn, 6, 4) << 1) 4124 #define PPC_XSp(insn) ((PPC_BIT (insn, 10) << 5) \ 4125 | PPC_FIELD (insn, 6, 4) << 1) 4126 #define PPC_XER_NB(xer) (xer & 0x7f) 4127 4128 /* The following macros are for the prefixed instructions. */ 4129 #define P_PPC_D(insn_prefix, insn_suffix) \ 4130 PPC_SEXT (PPC_FIELD (insn_prefix, 14, 18) << 16 \ 4131 | PPC_FIELD (insn_suffix, 16, 16), 34) 4132 #define P_PPC_TX5(insn_sufix) PPC_BIT (insn_suffix, 5) 4133 #define P_PPC_TX15(insn_suffix) PPC_BIT (insn_suffix, 15) 4134 #define P_PPC_XT(insn_suffix) ((PPC_TX (insn_suffix) << 5) \ 4135 | PPC_T (insn_suffix)) 4136 #define P_PPC_XT5(insn_suffix) ((P_PPC_TX5 (insn_suffix) << 5) \ 4137 | PPC_T (insn_suffix)) 4138 #define P_PPC_XT15(insn_suffix) \ 4139 ((P_PPC_TX15 (insn_suffix) << 5) | PPC_T (insn_suffix)) 4140 4141 /* Record Vector-Scalar Registers. 4142 For VSR less than 32, it's represented by an FPR and an VSR-upper register. 4143 Otherwise, it's just a VR register. Record them accordingly. */ 4144 4145 static int 4146 ppc_record_vsr (struct regcache *regcache, ppc_gdbarch_tdep *tdep, int vsr) 4147 { 4148 if (vsr < 0 || vsr >= 64) 4149 return -1; 4150 4151 if (vsr >= 32) 4152 { 4153 if (tdep->ppc_vr0_regnum >= 0) 4154 record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32); 4155 } 4156 else 4157 { 4158 if (tdep->ppc_fp0_regnum >= 0) 4159 record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr); 4160 if (tdep->ppc_vsr0_upper_regnum >= 0) 4161 record_full_arch_list_add_reg (regcache, 4162 tdep->ppc_vsr0_upper_regnum + vsr); 4163 } 4164 4165 return 0; 4166 } 4167 4168 /* The ppc_record_ACC_fpscr() records the changes to the VSR registers 4169 modified by a floating point instruction. The ENTRY argument selects which 4170 of the eight AT entries needs to be recorded. The boolean SAVE_FPSCR 4171 argument is set to TRUE to indicate the FPSCR also needs to be recorded. 4172 The function returns 0 on success. */ 4173 4174 static int 4175 ppc_record_ACC_fpscr (struct regcache *regcache, ppc_gdbarch_tdep *tdep, 4176 int entry, bool save_fpscr) 4177 { 4178 int i; 4179 if (entry < 0 || entry >= 8) 4180 return -1; 4181 4182 /* The ACC register file consists of 8 register entries, each register 4183 entry consist of four 128-bit rows. 4184 4185 The ACC rows map to specific VSR registers. 4186 ACC[0][0] -> VSR[0] 4187 ACC[0][1] -> VSR[1] 4188 ACC[0][2] -> VSR[2] 4189 ACC[0][3] -> VSR[3] 4190 ... 4191 ACC[7][0] -> VSR[28] 4192 ACC[7][1] -> VSR[29] 4193 ACC[7][2] -> VSR[30] 4194 ACC[7][3] -> VSR[31] 4195 4196 NOTE: 4197 In ISA 3.1 the ACC is mapped on top of VSR[0] thru VSR[31]. 4198 4199 In the future, the ACC may be implemented as an independent register file 4200 rather than mapping on top of the VSRs. This will then require the ACC to 4201 be assigned its own register number and the ptrace interface to be able 4202 access the ACC. Note the ptrace interface for the ACC will also need to 4203 be implemented. */ 4204 4205 /* ACC maps over the same VSR space as the fp registers. */ 4206 for (i = 0; i < 4; i++) 4207 { 4208 record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum 4209 + entry * 4 + i); 4210 record_full_arch_list_add_reg (regcache, 4211 tdep->ppc_vsr0_upper_regnum 4212 + entry * 4 + i); 4213 } 4214 4215 if (save_fpscr) 4216 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 4217 4218 return 0; 4219 } 4220 4221 /* Parse and record instructions primary opcode-4 at ADDR. 4222 Return 0 if successful. */ 4223 4224 static int 4225 ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache, 4226 CORE_ADDR addr, uint32_t insn) 4227 { 4228 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 4229 int ext = PPC_FIELD (insn, 21, 11); 4230 int vra = PPC_FIELD (insn, 11, 5); 4231 4232 switch (ext & 0x3f) 4233 { 4234 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */ 4235 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */ 4236 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */ 4237 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */ 4238 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 4239 /* FALL-THROUGH */ 4240 case 20: /* Move To VSR Byte Mask Immediate opcode, b2 = 0, 4241 ignore bit 31 */ 4242 case 21: /* Move To VSR Byte Mask Immediate opcode, b2 = 1, 4243 ignore bit 31 */ 4244 case 23: /* Vector Multiply-Sum & write Carry-out Unsigned 4245 Doubleword */ 4246 case 24: /* Vector Extract Double Unsigned Byte to VSR 4247 using GPR-specified Left-Index */ 4248 case 25: /* Vector Extract Double Unsigned Byte to VSR 4249 using GPR-specified Right-Index */ 4250 case 26: /* Vector Extract Double Unsigned Halfword to VSR 4251 using GPR-specified Left-Index */ 4252 case 27: /* Vector Extract Double Unsigned Halfword to VSR 4253 using GPR-specified Right-Index */ 4254 case 28: /* Vector Extract Double Unsigned Word to VSR 4255 using GPR-specified Left-Index */ 4256 case 29: /* Vector Extract Double Unsigned Word to VSR 4257 using GPR-specified Right-Index */ 4258 case 30: /* Vector Extract Double Unsigned Doubleword to VSR 4259 using GPR-specified Left-Index */ 4260 case 31: /* Vector Extract Double Unsigned Doubleword to VSR 4261 using GPR-specified Right-Index */ 4262 case 42: /* Vector Select */ 4263 case 43: /* Vector Permute */ 4264 case 59: /* Vector Permute Right-indexed */ 4265 case 22: /* Vector Shift 4266 Left Double by Bit Immediate if insn[21] = 0 4267 Right Double by Bit Immediate if insn[21] = 1 */ 4268 case 44: /* Vector Shift Left Double by Octet Immediate */ 4269 case 45: /* Vector Permute and Exclusive-OR */ 4270 case 60: /* Vector Add Extended Unsigned Quadword Modulo */ 4271 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */ 4272 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */ 4273 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */ 4274 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */ 4275 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */ 4276 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */ 4277 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */ 4278 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */ 4279 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */ 4280 case 46: /* Vector Multiply-Add Single-Precision */ 4281 case 47: /* Vector Negative Multiply-Subtract Single-Precision */ 4282 record_full_arch_list_add_reg (regcache, 4283 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4284 return 0; 4285 4286 case 48: /* Multiply-Add High Doubleword */ 4287 case 49: /* Multiply-Add High Doubleword Unsigned */ 4288 case 51: /* Multiply-Add Low Doubleword */ 4289 record_full_arch_list_add_reg (regcache, 4290 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4291 return 0; 4292 } 4293 4294 switch ((ext & 0x1ff)) 4295 { 4296 case 385: 4297 if (vra != 0 /* Decimal Convert To Signed Quadword */ 4298 && vra != 2 /* Decimal Convert From Signed Quadword */ 4299 && vra != 4 /* Decimal Convert To Zoned */ 4300 && vra != 5 /* Decimal Convert To National */ 4301 && vra != 6 /* Decimal Convert From Zoned */ 4302 && vra != 7 /* Decimal Convert From National */ 4303 && vra != 31) /* Decimal Set Sign */ 4304 break; 4305 /* Fall through. */ 4306 /* 5.16 Decimal Integer Arithmetic Instructions */ 4307 case 1: /* Decimal Add Modulo */ 4308 case 65: /* Decimal Subtract Modulo */ 4309 4310 case 193: /* Decimal Shift */ 4311 case 129: /* Decimal Unsigned Shift */ 4312 case 449: /* Decimal Shift and Round */ 4313 4314 case 257: /* Decimal Truncate */ 4315 case 321: /* Decimal Unsigned Truncate */ 4316 4317 /* Bit-21 should be set. */ 4318 if (!PPC_BIT (insn, 21)) 4319 break; 4320 4321 record_full_arch_list_add_reg (regcache, 4322 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4323 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4324 return 0; 4325 } 4326 4327 /* Bit-21 is used for RC */ 4328 switch (ext & 0x3ff) 4329 { 4330 case 5: /* Vector Rotate Left Quadword */ 4331 case 69: /* Vector Rotate Left Quadword then Mask Insert */ 4332 case 325: /* Vector Rotate Left Quadword then AND with Mask */ 4333 case 6: /* Vector Compare Equal To Unsigned Byte */ 4334 case 70: /* Vector Compare Equal To Unsigned Halfword */ 4335 case 134: /* Vector Compare Equal To Unsigned Word */ 4336 case 199: /* Vector Compare Equal To Unsigned Doubleword */ 4337 case 774: /* Vector Compare Greater Than Signed Byte */ 4338 case 838: /* Vector Compare Greater Than Signed Halfword */ 4339 case 902: /* Vector Compare Greater Than Signed Word */ 4340 case 967: /* Vector Compare Greater Than Signed Doubleword */ 4341 case 903: /* Vector Compare Greater Than Signed Quadword */ 4342 case 518: /* Vector Compare Greater Than Unsigned Byte */ 4343 case 646: /* Vector Compare Greater Than Unsigned Word */ 4344 case 582: /* Vector Compare Greater Than Unsigned Halfword */ 4345 case 711: /* Vector Compare Greater Than Unsigned Doubleword */ 4346 case 647: /* Vector Compare Greater Than Unsigned Quadword */ 4347 case 966: /* Vector Compare Bounds Single-Precision */ 4348 case 198: /* Vector Compare Equal To Single-Precision */ 4349 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */ 4350 case 455: /* Vector Compare Equal Quadword */ 4351 case 710: /* Vector Compare Greater Than Single-Precision */ 4352 case 7: /* Vector Compare Not Equal Byte */ 4353 case 71: /* Vector Compare Not Equal Halfword */ 4354 case 135: /* Vector Compare Not Equal Word */ 4355 case 263: /* Vector Compare Not Equal or Zero Byte */ 4356 case 327: /* Vector Compare Not Equal or Zero Halfword */ 4357 case 391: /* Vector Compare Not Equal or Zero Word */ 4358 if (PPC_Rc (insn)) 4359 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4360 record_full_arch_list_add_reg (regcache, 4361 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4362 return 0; 4363 4364 case 13: 4365 switch (vra) /* Bit-21 is used for RC */ 4366 { 4367 case 0: /* Vector String Isolate Byte Left-justified */ 4368 case 1: /* Vector String Isolate Byte Right-justified */ 4369 case 2: /* Vector String Isolate Halfword Left-justified */ 4370 case 3: /* Vector String Isolate Halfword Right-justified */ 4371 if (PPC_Rc (insn)) 4372 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4373 record_full_arch_list_add_reg (regcache, 4374 tdep->ppc_vr0_regnum 4375 + PPC_VRT (insn)); 4376 return 0; 4377 } 4378 } 4379 4380 if (ext == 1538) 4381 { 4382 switch (vra) 4383 { 4384 case 0: /* Vector Count Leading Zero Least-Significant Bits 4385 Byte */ 4386 case 1: /* Vector Count Trailing Zero Least-Significant Bits 4387 Byte */ 4388 record_full_arch_list_add_reg (regcache, 4389 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4390 return 0; 4391 4392 case 6: /* Vector Negate Word */ 4393 case 7: /* Vector Negate Doubleword */ 4394 case 8: /* Vector Parity Byte Word */ 4395 case 9: /* Vector Parity Byte Doubleword */ 4396 case 10: /* Vector Parity Byte Quadword */ 4397 case 16: /* Vector Extend Sign Byte To Word */ 4398 case 17: /* Vector Extend Sign Halfword To Word */ 4399 case 24: /* Vector Extend Sign Byte To Doubleword */ 4400 case 25: /* Vector Extend Sign Halfword To Doubleword */ 4401 case 26: /* Vector Extend Sign Word To Doubleword */ 4402 case 27: /* Vector Extend Sign Doubleword To Quadword */ 4403 case 28: /* Vector Count Trailing Zeros Byte */ 4404 case 29: /* Vector Count Trailing Zeros Halfword */ 4405 case 30: /* Vector Count Trailing Zeros Word */ 4406 case 31: /* Vector Count Trailing Zeros Doubleword */ 4407 record_full_arch_list_add_reg (regcache, 4408 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4409 return 0; 4410 } 4411 } 4412 4413 if (ext == 1602) 4414 { 4415 switch (vra) 4416 { 4417 case 0: /* Vector Expand Byte Mask */ 4418 case 1: /* Vector Expand Halfword Mask */ 4419 case 2: /* Vector Expand Word Mask */ 4420 case 3: /* Vector Expand Doubleword Mask */ 4421 case 4: /* Vector Expand Quadword Mask */ 4422 case 16: /* Move to VSR Byte Mask */ 4423 case 17: /* Move to VSR Halfword Mask */ 4424 case 18: /* Move to VSR Word Mask */ 4425 case 19: /* Move to VSR Doubleword Mask */ 4426 case 20: /* Move to VSR Quadword Mask */ 4427 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 4428 return 0; 4429 4430 case 8: /* Vector Extract Byte Mask */ 4431 case 9: /* Vector Extract Halfword Mask */ 4432 case 10: /* Vector Extract Word Mask */ 4433 case 11: /* Vector Extract Doubleword Mask */ 4434 case 12: /* Vector Extract Quadword Mask */ 4435 4436 /* Ignore the MP bit in the LSB position of the vra value. */ 4437 case 24: /* Vector Count Mask Bits Byte, MP = 0 */ 4438 case 25: /* Vector Count Mask Bits Byte, MP = 1 */ 4439 case 26: /* Vector Count Mask Bits Halfword, MP = 0 */ 4440 case 27: /* Vector Count Mask Bits Halfword, MP = 1 */ 4441 case 28: /* Vector Count Mask Bits Word, MP = 0 */ 4442 case 29: /* Vector Count Mask Bits Word, MP = 1 */ 4443 case 30: /* Vector Count Mask Bits Doubleword, MP = 0 */ 4444 case 31: /* Vector Count Mask Bits Doubleword, MP = 1 */ 4445 record_full_arch_list_add_reg (regcache, 4446 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4447 record_full_arch_list_add_reg (regcache, 4448 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4449 return 0; 4450 } 4451 } 4452 4453 switch (ext) 4454 { 4455 4456 case 257: /* Vector Compare Unsigned Quadword */ 4457 case 321: /* Vector Compare Signed Quadword */ 4458 /* Comparison tests that always set CR field BF */ 4459 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4460 record_full_arch_list_add_reg (regcache, 4461 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4462 return 0; 4463 4464 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */ 4465 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */ 4466 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */ 4467 case 334: /* Vector Pack Signed Word Unsigned Saturate */ 4468 case 398: /* Vector Pack Signed Halfword Signed Saturate */ 4469 case 462: /* Vector Pack Signed Word Signed Saturate */ 4470 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */ 4471 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */ 4472 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */ 4473 case 512: /* Vector Add Unsigned Byte Saturate */ 4474 case 576: /* Vector Add Unsigned Halfword Saturate */ 4475 case 640: /* Vector Add Unsigned Word Saturate */ 4476 case 768: /* Vector Add Signed Byte Saturate */ 4477 case 832: /* Vector Add Signed Halfword Saturate */ 4478 case 896: /* Vector Add Signed Word Saturate */ 4479 case 1536: /* Vector Subtract Unsigned Byte Saturate */ 4480 case 1600: /* Vector Subtract Unsigned Halfword Saturate */ 4481 case 1664: /* Vector Subtract Unsigned Word Saturate */ 4482 case 1792: /* Vector Subtract Signed Byte Saturate */ 4483 case 1856: /* Vector Subtract Signed Halfword Saturate */ 4484 case 1920: /* Vector Subtract Signed Word Saturate */ 4485 4486 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */ 4487 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */ 4488 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */ 4489 case 1672: /* Vector Sum across Half Signed Word Saturate */ 4490 case 1928: /* Vector Sum across Signed Word Saturate */ 4491 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */ 4492 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */ 4493 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 4494 /* FALL-THROUGH */ 4495 case 12: /* Vector Merge High Byte */ 4496 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */ 4497 case 76: /* Vector Merge High Halfword */ 4498 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */ 4499 case 140: /* Vector Merge High Word */ 4500 case 268: /* Vector Merge Low Byte */ 4501 case 332: /* Vector Merge Low Halfword */ 4502 case 396: /* Vector Merge Low Word */ 4503 case 397: /* Vector Clear Leftmost Bytes */ 4504 case 461: /* Vector Clear Rightmost Bytes */ 4505 case 526: /* Vector Unpack High Signed Byte */ 4506 case 590: /* Vector Unpack High Signed Halfword */ 4507 case 654: /* Vector Unpack Low Signed Byte */ 4508 case 718: /* Vector Unpack Low Signed Halfword */ 4509 case 782: /* Vector Pack Pixel */ 4510 case 846: /* Vector Unpack High Pixel */ 4511 case 974: /* Vector Unpack Low Pixel */ 4512 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */ 4513 case 1614: /* Vector Unpack High Signed Word */ 4514 case 1676: /* Vector Merge Odd Word */ 4515 case 1742: /* Vector Unpack Low Signed Word */ 4516 case 1932: /* Vector Merge Even Word */ 4517 case 524: /* Vector Splat Byte */ 4518 case 588: /* Vector Splat Halfword */ 4519 case 652: /* Vector Splat Word */ 4520 case 780: /* Vector Splat Immediate Signed Byte */ 4521 case 844: /* Vector Splat Immediate Signed Halfword */ 4522 case 908: /* Vector Splat Immediate Signed Word */ 4523 case 261: /* Vector Shift Left Quadword */ 4524 case 452: /* Vector Shift Left */ 4525 case 517: /* Vector Shift Right Quadword */ 4526 case 708: /* Vector Shift Right */ 4527 case 773: /* Vector Shift Right Algebraic Quadword */ 4528 case 1036: /* Vector Shift Left by Octet */ 4529 case 1100: /* Vector Shift Right by Octet */ 4530 case 0: /* Vector Add Unsigned Byte Modulo */ 4531 case 64: /* Vector Add Unsigned Halfword Modulo */ 4532 case 128: /* Vector Add Unsigned Word Modulo */ 4533 case 192: /* Vector Add Unsigned Doubleword Modulo */ 4534 case 256: /* Vector Add Unsigned Quadword Modulo */ 4535 case 320: /* Vector Add & write Carry Unsigned Quadword */ 4536 case 384: /* Vector Add and Write Carry-Out Unsigned Word */ 4537 case 8: /* Vector Multiply Odd Unsigned Byte */ 4538 case 72: /* Vector Multiply Odd Unsigned Halfword */ 4539 case 136: /* Vector Multiply Odd Unsigned Word */ 4540 case 200: /* Vector Multiply Odd Unsigned Doubleword */ 4541 case 264: /* Vector Multiply Odd Signed Byte */ 4542 case 328: /* Vector Multiply Odd Signed Halfword */ 4543 case 392: /* Vector Multiply Odd Signed Word */ 4544 case 456: /* Vector Multiply Odd Signed Doubleword */ 4545 case 520: /* Vector Multiply Even Unsigned Byte */ 4546 case 584: /* Vector Multiply Even Unsigned Halfword */ 4547 case 648: /* Vector Multiply Even Unsigned Word */ 4548 case 712: /* Vector Multiply Even Unsigned Doubleword */ 4549 case 776: /* Vector Multiply Even Signed Byte */ 4550 case 840: /* Vector Multiply Even Signed Halfword */ 4551 case 904: /* Vector Multiply Even Signed Word */ 4552 case 968: /* Vector Multiply Even Signed Doubleword */ 4553 case 457: /* Vector Multiply Low Doubleword */ 4554 case 649: /* Vector Multiply High Unsigned Word */ 4555 case 713: /* Vector Multiply High Unsigned Doubleword */ 4556 case 905: /* Vector Multiply High Signed Word */ 4557 case 969: /* Vector Multiply High Signed Doubleword */ 4558 case 11: /* Vector Divide Unsigned Quadword */ 4559 case 203: /* Vector Divide Unsigned Doubleword */ 4560 case 139: /* Vector Divide Unsigned Word */ 4561 case 267: /* Vector Divide Signed Quadword */ 4562 case 459: /* Vector Divide Signed Doubleword */ 4563 case 395: /* Vector Divide Signed Word */ 4564 case 523: /* Vector Divide Extended Unsigned Quadword */ 4565 case 715: /* Vector Divide Extended Unsigned Doubleword */ 4566 case 651: /* Vector Divide Extended Unsigned Word */ 4567 case 779: /* Vector Divide Extended Signed Quadword */ 4568 case 971: /* Vector Divide Extended Signed Doubleword */ 4569 case 907: /* Vector Divide Extended Unsigned Word */ 4570 case 1547: /* Vector Modulo Unsigned Quadword */ 4571 case 1675: /* Vector Modulo Unsigned Word */ 4572 case 1739: /* Vector Modulo Unsigned Doubleword */ 4573 case 1803: /* Vector Modulo Signed Quadword */ 4574 case 1931: /* Vector Modulo Signed Word */ 4575 case 1995: /* Vector Modulo Signed Doubleword */ 4576 4577 case 137: /* Vector Multiply Unsigned Word Modulo */ 4578 case 1024: /* Vector Subtract Unsigned Byte Modulo */ 4579 case 1088: /* Vector Subtract Unsigned Halfword Modulo */ 4580 case 1152: /* Vector Subtract Unsigned Word Modulo */ 4581 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */ 4582 case 1280: /* Vector Subtract Unsigned Quadword Modulo */ 4583 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */ 4584 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */ 4585 case 1282: /* Vector Average Signed Byte */ 4586 case 1346: /* Vector Average Signed Halfword */ 4587 case 1410: /* Vector Average Signed Word */ 4588 case 1026: /* Vector Average Unsigned Byte */ 4589 case 1090: /* Vector Average Unsigned Halfword */ 4590 case 1154: /* Vector Average Unsigned Word */ 4591 case 258: /* Vector Maximum Signed Byte */ 4592 case 322: /* Vector Maximum Signed Halfword */ 4593 case 386: /* Vector Maximum Signed Word */ 4594 case 450: /* Vector Maximum Signed Doubleword */ 4595 case 2: /* Vector Maximum Unsigned Byte */ 4596 case 66: /* Vector Maximum Unsigned Halfword */ 4597 case 130: /* Vector Maximum Unsigned Word */ 4598 case 194: /* Vector Maximum Unsigned Doubleword */ 4599 case 770: /* Vector Minimum Signed Byte */ 4600 case 834: /* Vector Minimum Signed Halfword */ 4601 case 898: /* Vector Minimum Signed Word */ 4602 case 962: /* Vector Minimum Signed Doubleword */ 4603 case 514: /* Vector Minimum Unsigned Byte */ 4604 case 578: /* Vector Minimum Unsigned Halfword */ 4605 case 642: /* Vector Minimum Unsigned Word */ 4606 case 706: /* Vector Minimum Unsigned Doubleword */ 4607 case 1028: /* Vector Logical AND */ 4608 case 1668: /* Vector Logical Equivalent */ 4609 case 1092: /* Vector Logical AND with Complement */ 4610 case 1412: /* Vector Logical NAND */ 4611 case 1348: /* Vector Logical OR with Complement */ 4612 case 1156: /* Vector Logical OR */ 4613 case 1284: /* Vector Logical NOR */ 4614 case 1220: /* Vector Logical XOR */ 4615 case 4: /* Vector Rotate Left Byte */ 4616 case 132: /* Vector Rotate Left Word VX-form */ 4617 case 68: /* Vector Rotate Left Halfword */ 4618 case 196: /* Vector Rotate Left Doubleword */ 4619 case 260: /* Vector Shift Left Byte */ 4620 case 388: /* Vector Shift Left Word */ 4621 case 324: /* Vector Shift Left Halfword */ 4622 case 1476: /* Vector Shift Left Doubleword */ 4623 case 516: /* Vector Shift Right Byte */ 4624 case 644: /* Vector Shift Right Word */ 4625 case 580: /* Vector Shift Right Halfword */ 4626 case 1732: /* Vector Shift Right Doubleword */ 4627 case 772: /* Vector Shift Right Algebraic Byte */ 4628 case 900: /* Vector Shift Right Algebraic Word */ 4629 case 836: /* Vector Shift Right Algebraic Halfword */ 4630 case 964: /* Vector Shift Right Algebraic Doubleword */ 4631 case 10: /* Vector Add Single-Precision */ 4632 case 74: /* Vector Subtract Single-Precision */ 4633 case 1034: /* Vector Maximum Single-Precision */ 4634 case 1098: /* Vector Minimum Single-Precision */ 4635 case 842: /* Vector Convert From Signed Fixed-Point Word */ 4636 case 778: /* Vector Convert From Unsigned Fixed-Point Word */ 4637 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */ 4638 case 522: /* Vector Round to Single-Precision Integer Nearest */ 4639 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */ 4640 case 586: /* Vector Round to Single-Precision Integer toward Zero */ 4641 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */ 4642 case 458: /* Vector Log Base 2 Estimate Floating-Point */ 4643 case 266: /* Vector Reciprocal Estimate Single-Precision */ 4644 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */ 4645 case 1288: /* Vector AES Cipher */ 4646 case 1289: /* Vector AES Cipher Last */ 4647 case 1352: /* Vector AES Inverse Cipher */ 4648 case 1353: /* Vector AES Inverse Cipher Last */ 4649 case 1480: /* Vector AES SubBytes */ 4650 case 1730: /* Vector SHA-512 Sigma Doubleword */ 4651 case 1666: /* Vector SHA-256 Sigma Word */ 4652 case 1032: /* Vector Polynomial Multiply-Sum Byte */ 4653 case 1160: /* Vector Polynomial Multiply-Sum Word */ 4654 case 1096: /* Vector Polynomial Multiply-Sum Halfword */ 4655 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */ 4656 case 1292: /* Vector Gather Bits by Bytes by Doubleword */ 4657 case 1794: /* Vector Count Leading Zeros Byte */ 4658 case 1858: /* Vector Count Leading Zeros Halfword */ 4659 case 1922: /* Vector Count Leading Zeros Word */ 4660 case 1924: /* Vector Count Leading Zeros Doubleword under 4661 bit Mask*/ 4662 case 1986: /* Vector Count Leading Zeros Doubleword */ 4663 case 1988: /* Vector Count Trailing Zeros Doubleword under bit 4664 Mask */ 4665 case 1795: /* Vector Population Count Byte */ 4666 case 1859: /* Vector Population Count Halfword */ 4667 case 1923: /* Vector Population Count Word */ 4668 case 1987: /* Vector Population Count Doubleword */ 4669 case 1356: /* Vector Bit Permute Quadword */ 4670 case 1484: /* Vector Bit Permute Doubleword */ 4671 case 513: /* Vector Multiply-by-10 Unsigned Quadword */ 4672 case 1: /* Vector Multiply-by-10 & write Carry Unsigned 4673 Quadword */ 4674 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */ 4675 case 65: /* Vector Multiply-by-10 Extended & write Carry 4676 Unsigned Quadword */ 4677 case 1027: /* Vector Absolute Difference Unsigned Byte */ 4678 case 1091: /* Vector Absolute Difference Unsigned Halfword */ 4679 case 1155: /* Vector Absolute Difference Unsigned Word */ 4680 case 1796: /* Vector Shift Right Variable */ 4681 case 1860: /* Vector Shift Left Variable */ 4682 case 133: /* Vector Rotate Left Word then Mask Insert */ 4683 case 197: /* Vector Rotate Left Doubleword then Mask Insert */ 4684 case 389: /* Vector Rotate Left Word then AND with Mask */ 4685 case 453: /* Vector Rotate Left Doubleword then AND with Mask */ 4686 case 525: /* Vector Extract Unsigned Byte */ 4687 case 589: /* Vector Extract Unsigned Halfword */ 4688 case 653: /* Vector Extract Unsigned Word */ 4689 case 717: /* Vector Extract Doubleword */ 4690 case 15: /* Vector Insert Byte from VSR using GPR-specified 4691 Left-Index */ 4692 case 79: /* Vector Insert Halfword from VSR using GPR-specified 4693 Left-Index */ 4694 case 143: /* Vector Insert Word from VSR using GPR-specified 4695 Left-Index */ 4696 case 207: /* Vector Insert Word from GPR using 4697 immediate-specified index */ 4698 case 463: /* Vector Insert Doubleword from GPR using 4699 immediate-specified index */ 4700 case 271: /* Vector Insert Byte from VSR using GPR-specified 4701 Right-Index */ 4702 case 335: /* Vector Insert Halfword from VSR using GPR-specified 4703 Right-Index */ 4704 case 399: /* Vector Insert Word from VSR using GPR-specified 4705 Right-Index */ 4706 case 527: /* Vector Insert Byte from GPR using GPR-specified 4707 Left-Index */ 4708 case 591: /* Vector Insert Halfword from GPR using GPR-specified 4709 Left-Index */ 4710 case 655: /* Vector Insert Word from GPR using GPR-specified 4711 Left-Index */ 4712 case 719: /* Vector Insert Doubleword from GPR using 4713 GPR-specified Left-Index */ 4714 case 783: /* Vector Insert Byte from GPR using GPR-specified 4715 Right-Index */ 4716 case 847: /* Vector Insert Halfword from GPR using GPR-specified 4717 Left-Index */ 4718 case 911: /* Vector Insert Word from GPR using GPR-specified 4719 Left-Index */ 4720 case 975: /* Vector Insert Doubleword from GPR using 4721 GPR-specified Right-Index */ 4722 case 781: /* Vector Insert Byte */ 4723 case 845: /* Vector Insert Halfword */ 4724 case 909: /* Vector Insert Word */ 4725 case 973: /* Vector Insert Doubleword */ 4726 case 1357: /* Vector Centrifuge Doubleword */ 4727 case 1421: /* Vector Parallel Bits Extract Doubleword */ 4728 case 1485: /* Vector Parallel Bits Deposit Doubleword */ 4729 record_full_arch_list_add_reg (regcache, 4730 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4731 return 0; 4732 4733 case 1228: /* Vector Gather every Nth Bit */ 4734 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */ 4735 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */ 4736 case 1677: /* Vector Extract Unsigned Word Left-Indexed */ 4737 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */ 4738 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */ 4739 case 1933: /* Vector Extract Unsigned Word Right-Indexed */ 4740 record_full_arch_list_add_reg (regcache, 4741 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4742 return 0; 4743 4744 case 1604: /* Move To Vector Status and Control Register */ 4745 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM); 4746 return 0; 4747 case 1540: /* Move From Vector Status and Control Register */ 4748 record_full_arch_list_add_reg (regcache, 4749 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4750 return 0; 4751 case 833: /* Decimal Copy Sign */ 4752 record_full_arch_list_add_reg (regcache, 4753 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 4754 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4755 return 0; 4756 } 4757 4758 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 4759 "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext); 4760 return -1; 4761 } 4762 4763 /* Parse and record instructions of primary opcode 6 at ADDR. 4764 Return 0 if successful. */ 4765 4766 static int 4767 ppc_process_record_op6 (struct gdbarch *gdbarch, struct regcache *regcache, 4768 CORE_ADDR addr, uint32_t insn) 4769 { 4770 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 4771 int subtype = PPC_FIELD (insn, 28, 4); 4772 CORE_ADDR ea = 0; 4773 4774 switch (subtype) 4775 { 4776 case 0: /* Load VSX Vector Paired */ 4777 ppc_record_vsr (regcache, tdep, PPC_XTp (insn)); 4778 ppc_record_vsr (regcache, tdep, PPC_XTp (insn) + 1); 4779 return 0; 4780 case 1: /* Store VSX Vector Paired */ 4781 if (PPC_RA (insn) != 0) 4782 regcache_raw_read_unsigned (regcache, 4783 tdep->ppc_gp0_regnum + PPC_RA (insn), &ea); 4784 ea += PPC_DQ (insn) << 4; 4785 record_full_arch_list_add_mem (ea, 32); 4786 return 0; 4787 } 4788 return -1; 4789 } 4790 4791 /* Parse and record instructions of primary opcode-19 at ADDR. 4792 Return 0 if successful. */ 4793 4794 static int 4795 ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache, 4796 CORE_ADDR addr, uint32_t insn) 4797 { 4798 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 4799 int ext = PPC_EXTOP (insn); 4800 4801 switch (ext & 0x01f) 4802 { 4803 case 2: /* Add PC Immediate Shifted */ 4804 record_full_arch_list_add_reg (regcache, 4805 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4806 return 0; 4807 } 4808 4809 switch (ext) 4810 { 4811 case 0: /* Move Condition Register Field */ 4812 case 33: /* Condition Register NOR */ 4813 case 129: /* Condition Register AND with Complement */ 4814 case 193: /* Condition Register XOR */ 4815 case 225: /* Condition Register NAND */ 4816 case 257: /* Condition Register AND */ 4817 case 289: /* Condition Register Equivalent */ 4818 case 417: /* Condition Register OR with Complement */ 4819 case 449: /* Condition Register OR */ 4820 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4821 return 0; 4822 4823 case 16: /* Branch Conditional */ 4824 case 560: /* Branch Conditional to Branch Target Address Register */ 4825 if ((PPC_BO (insn) & 0x4) == 0) 4826 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 4827 /* FALL-THROUGH */ 4828 case 528: /* Branch Conditional to Count Register */ 4829 if (PPC_LK (insn)) 4830 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 4831 return 0; 4832 4833 case 150: /* Instruction Synchronize */ 4834 /* Do nothing. */ 4835 return 0; 4836 } 4837 4838 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 4839 "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext); 4840 return -1; 4841 } 4842 4843 /* Parse and record instructions of primary opcode-31 with the extended opcode 4844 177. The argument is the word instruction (insn). Return 0 if successful. 4845 */ 4846 4847 static int 4848 ppc_process_record_op31_177 (struct gdbarch *gdbarch, 4849 struct regcache *regcache, 4850 uint32_t insn) 4851 { 4852 int RA_opcode = PPC_RA(insn); 4853 int as = PPC_FIELD (insn, 6, 3); 4854 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 4855 4856 switch (RA_opcode) 4857 { 4858 case 0: /* VSX Move From Accumulator, xxmfacc */ 4859 case 1: /* VSX Move To Accumulator, xxmtacc */ 4860 case 3: /* VSX Set Accumulator to Zero, xxsetaccz */ 4861 ppc_record_ACC_fpscr (regcache, tdep, as, false); 4862 return 0; 4863 } 4864 return -1; 4865 } 4866 4867 /* Parse and record instructions of primary opcode-31 at ADDR. 4868 Return 0 if successful. */ 4869 4870 static int 4871 ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache, 4872 CORE_ADDR addr, uint32_t insn) 4873 { 4874 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 4875 int ext = PPC_EXTOP (insn); 4876 int tmp, nr, nb = 0, i; 4877 CORE_ADDR at_dcsz, ea = 0; 4878 ULONGEST rb, ra, xer; 4879 int size = 0; 4880 4881 /* These instructions have OE bit. */ 4882 switch (ext & 0x1ff) 4883 { 4884 /* These write RT and XER. Update CR if RC is set. */ 4885 case 8: /* Subtract from carrying */ 4886 case 10: /* Add carrying */ 4887 case 136: /* Subtract from extended */ 4888 case 138: /* Add extended */ 4889 case 200: /* Subtract from zero extended */ 4890 case 202: /* Add to zero extended */ 4891 case 232: /* Subtract from minus one extended */ 4892 case 234: /* Add to minus one extended */ 4893 /* CA is always altered, but SO/OV are only altered when OE=1. 4894 In any case, XER is always altered. */ 4895 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4896 if (PPC_RC (insn)) 4897 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4898 record_full_arch_list_add_reg (regcache, 4899 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4900 return 0; 4901 4902 /* These write RT. Update CR if RC is set and update XER if OE is set. */ 4903 case 40: /* Subtract from */ 4904 case 104: /* Negate */ 4905 case 233: /* Multiply low doubleword */ 4906 case 235: /* Multiply low word */ 4907 case 266: /* Add */ 4908 case 393: /* Divide Doubleword Extended Unsigned */ 4909 case 395: /* Divide Word Extended Unsigned */ 4910 case 425: /* Divide Doubleword Extended */ 4911 case 427: /* Divide Word Extended */ 4912 case 457: /* Divide Doubleword Unsigned */ 4913 case 459: /* Divide Word Unsigned */ 4914 case 489: /* Divide Doubleword */ 4915 case 491: /* Divide Word */ 4916 if (PPC_OE (insn)) 4917 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4918 /* FALL-THROUGH */ 4919 case 9: /* Multiply High Doubleword Unsigned */ 4920 case 11: /* Multiply High Word Unsigned */ 4921 case 73: /* Multiply High Doubleword */ 4922 case 75: /* Multiply High Word */ 4923 if (PPC_RC (insn)) 4924 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4925 record_full_arch_list_add_reg (regcache, 4926 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4927 return 0; 4928 } 4929 4930 if ((ext & 0x1f) == 15) 4931 { 4932 /* Integer Select. bit[16:20] is used for BC. */ 4933 record_full_arch_list_add_reg (regcache, 4934 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4935 return 0; 4936 } 4937 4938 if ((ext & 0xff) == 170) 4939 { 4940 /* Add Extended using alternate carry bits */ 4941 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4942 record_full_arch_list_add_reg (regcache, 4943 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4944 return 0; 4945 } 4946 4947 switch (ext) 4948 { 4949 case 78: /* Determine Leftmost Zero Byte */ 4950 if (PPC_RC (insn)) 4951 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 4952 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 4953 record_full_arch_list_add_reg (regcache, 4954 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4955 return 0; 4956 4957 /* These only write RT. */ 4958 case 19: /* Move from condition register */ 4959 /* Move From One Condition Register Field */ 4960 case 74: /* Add and Generate Sixes */ 4961 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */ 4962 case 302: /* Move From Branch History Rolling Buffer */ 4963 case 339: /* Move From Special Purpose Register */ 4964 case 371: /* Move From Time Base [Phased-Out] */ 4965 case 309: /* Load Doubleword Monitored Indexed */ 4966 case 128: /* Set Boolean */ 4967 case 384: /* Set Boolean Condition */ 4968 case 416: /* Set Boolean Condition Reverse */ 4969 case 448: /* Set Negative Boolean Condition */ 4970 case 480: /* Set Negative Boolean Condition Reverse */ 4971 case 755: /* Deliver A Random Number */ 4972 record_full_arch_list_add_reg (regcache, 4973 tdep->ppc_gp0_regnum + PPC_RT (insn)); 4974 return 0; 4975 4976 /* These only write to RA. */ 4977 case 51: /* Move From VSR Doubleword */ 4978 case 59: /* Count Leading Zeros Doubleword under bit Mask */ 4979 case 115: /* Move From VSR Word and Zero */ 4980 case 122: /* Population count bytes */ 4981 case 155: /* Byte-Reverse Word */ 4982 case 156: /* Parallel Bits Deposit Doubleword */ 4983 case 187: /* Byte-Reverse Doubleword */ 4984 case 188: /* Parallel Bits Extract Doubleword */ 4985 case 219: /* Byte-Reverse Halfword */ 4986 case 220: /* Centrifuge Doubleword */ 4987 case 378: /* Population count words */ 4988 case 506: /* Population count doublewords */ 4989 case 154: /* Parity Word */ 4990 case 186: /* Parity Doubleword */ 4991 case 252: /* Bit Permute Doubleword */ 4992 case 282: /* Convert Declets To Binary Coded Decimal */ 4993 case 314: /* Convert Binary Coded Decimal To Declets */ 4994 case 508: /* Compare bytes */ 4995 case 307: /* Move From VSR Lower Doubleword */ 4996 case 571: /* Count Trailing Zeros Doubleword under bit Mask */ 4997 record_full_arch_list_add_reg (regcache, 4998 tdep->ppc_gp0_regnum + PPC_RA (insn)); 4999 return 0; 5000 5001 /* These write CR and optional RA. */ 5002 case 792: /* Shift Right Algebraic Word */ 5003 case 794: /* Shift Right Algebraic Doubleword */ 5004 case 824: /* Shift Right Algebraic Word Immediate */ 5005 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */ 5006 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */ 5007 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 5008 record_full_arch_list_add_reg (regcache, 5009 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5010 /* FALL-THROUGH */ 5011 case 0: /* Compare */ 5012 case 32: /* Compare logical */ 5013 case 144: /* Move To Condition Register Fields */ 5014 /* Move To One Condition Register Field */ 5015 case 192: /* Compare Ranged Byte */ 5016 case 224: /* Compare Equal Byte */ 5017 case 576: /* Move XER to CR Extended */ 5018 case 902: /* Paste (should always fail due to single-stepping and 5019 the memory location might not be accessible, so 5020 record only CR) */ 5021 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5022 return 0; 5023 5024 /* These write to RT. Update RA if 'update indexed.' */ 5025 case 53: /* Load Doubleword with Update Indexed */ 5026 case 119: /* Load Byte and Zero with Update Indexed */ 5027 case 311: /* Load Halfword and Zero with Update Indexed */ 5028 case 55: /* Load Word and Zero with Update Indexed */ 5029 case 375: /* Load Halfword Algebraic with Update Indexed */ 5030 case 373: /* Load Word Algebraic with Update Indexed */ 5031 record_full_arch_list_add_reg (regcache, 5032 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5033 /* FALL-THROUGH */ 5034 case 21: /* Load Doubleword Indexed */ 5035 case 52: /* Load Byte And Reserve Indexed */ 5036 case 116: /* Load Halfword And Reserve Indexed */ 5037 case 20: /* Load Word And Reserve Indexed */ 5038 case 84: /* Load Doubleword And Reserve Indexed */ 5039 case 87: /* Load Byte and Zero Indexed */ 5040 case 279: /* Load Halfword and Zero Indexed */ 5041 case 23: /* Load Word and Zero Indexed */ 5042 case 343: /* Load Halfword Algebraic Indexed */ 5043 case 341: /* Load Word Algebraic Indexed */ 5044 case 790: /* Load Halfword Byte-Reverse Indexed */ 5045 case 534: /* Load Word Byte-Reverse Indexed */ 5046 case 532: /* Load Doubleword Byte-Reverse Indexed */ 5047 case 582: /* Load Word Atomic */ 5048 case 614: /* Load Doubleword Atomic */ 5049 case 265: /* Modulo Unsigned Doubleword */ 5050 case 777: /* Modulo Signed Doubleword */ 5051 case 267: /* Modulo Unsigned Word */ 5052 case 779: /* Modulo Signed Word */ 5053 record_full_arch_list_add_reg (regcache, 5054 tdep->ppc_gp0_regnum + PPC_RT (insn)); 5055 return 0; 5056 5057 case 597: /* Load String Word Immediate */ 5058 case 533: /* Load String Word Indexed */ 5059 if (ext == 597) 5060 { 5061 nr = PPC_NB (insn); 5062 if (nr == 0) 5063 nr = 32; 5064 } 5065 else 5066 { 5067 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); 5068 nr = PPC_XER_NB (xer); 5069 } 5070 5071 nr = (nr + 3) >> 2; 5072 5073 /* If n=0, the contents of register RT are undefined. */ 5074 if (nr == 0) 5075 nr = 1; 5076 5077 for (i = 0; i < nr; i++) 5078 record_full_arch_list_add_reg (regcache, 5079 tdep->ppc_gp0_regnum 5080 + ((PPC_RT (insn) + i) & 0x1f)); 5081 return 0; 5082 5083 case 276: /* Load Quadword And Reserve Indexed */ 5084 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); 5085 record_full_arch_list_add_reg (regcache, tmp); 5086 record_full_arch_list_add_reg (regcache, tmp + 1); 5087 return 0; 5088 5089 /* These write VRT. */ 5090 case 6: /* Load Vector for Shift Left Indexed */ 5091 case 38: /* Load Vector for Shift Right Indexed */ 5092 case 7: /* Load Vector Element Byte Indexed */ 5093 case 39: /* Load Vector Element Halfword Indexed */ 5094 case 71: /* Load Vector Element Word Indexed */ 5095 case 103: /* Load Vector Indexed */ 5096 case 359: /* Load Vector Indexed LRU */ 5097 record_full_arch_list_add_reg (regcache, 5098 tdep->ppc_vr0_regnum + PPC_VRT (insn)); 5099 return 0; 5100 5101 /* These write FRT. Update RA if 'update indexed.' */ 5102 case 567: /* Load Floating-Point Single with Update Indexed */ 5103 case 631: /* Load Floating-Point Double with Update Indexed */ 5104 record_full_arch_list_add_reg (regcache, 5105 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5106 /* FALL-THROUGH */ 5107 case 535: /* Load Floating-Point Single Indexed */ 5108 case 599: /* Load Floating-Point Double Indexed */ 5109 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */ 5110 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */ 5111 record_full_arch_list_add_reg (regcache, 5112 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5113 return 0; 5114 5115 case 791: /* Load Floating-Point Double Pair Indexed */ 5116 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 5117 record_full_arch_list_add_reg (regcache, tmp); 5118 record_full_arch_list_add_reg (regcache, tmp + 1); 5119 return 0; 5120 5121 /* These write to destination register PPC_XT. */ 5122 case 179: /* Move To VSR Doubleword */ 5123 case 211: /* Move To VSR Word Algebraic */ 5124 case 243: /* Move To VSR Word and Zero */ 5125 case 588: /* Load VSX Scalar Doubleword Indexed */ 5126 case 524: /* Load VSX Scalar Single-Precision Indexed */ 5127 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */ 5128 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */ 5129 case 13: /* Load VSX Vector Rightmost Byte Indexed */ 5130 case 45: /* Load VSX Vector Rightmost Halfword Indexed */ 5131 case 77: /* Load VSX Vector Rightmost Word Indexed */ 5132 case 109: /* Load VSX Vector Rightmost Doubleword Indexed */ 5133 case 844: /* Load VSX Vector Doubleword*2 Indexed */ 5134 case 332: /* Load VSX Vector Doubleword & Splat Indexed */ 5135 case 780: /* Load VSX Vector Word*4 Indexed */ 5136 case 268: /* Load VSX Vector Indexed */ 5137 case 364: /* Load VSX Vector Word & Splat Indexed */ 5138 case 812: /* Load VSX Vector Halfword*8 Indexed */ 5139 case 876: /* Load VSX Vector Byte*16 Indexed */ 5140 case 269: /* Load VSX Vector with Length */ 5141 case 301: /* Load VSX Vector Left-justified with Length */ 5142 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */ 5143 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */ 5144 case 403: /* Move To VSR Word & Splat */ 5145 case 435: /* Move To VSR Double Doubleword */ 5146 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5147 return 0; 5148 5149 case 333: /* Load VSX Vector Paired Indexed */ 5150 ppc_record_vsr (regcache, tdep, PPC_XTp (insn)); 5151 ppc_record_vsr (regcache, tdep, PPC_XTp (insn) + 1); 5152 return 0; 5153 5154 /* These write RA. Update CR if RC is set. */ 5155 case 24: /* Shift Left Word */ 5156 case 26: /* Count Leading Zeros Word */ 5157 case 27: /* Shift Left Doubleword */ 5158 case 28: /* AND */ 5159 case 58: /* Count Leading Zeros Doubleword */ 5160 case 60: /* AND with Complement */ 5161 case 124: /* NOR */ 5162 case 284: /* Equivalent */ 5163 case 316: /* XOR */ 5164 case 476: /* NAND */ 5165 case 412: /* OR with Complement */ 5166 case 444: /* OR */ 5167 case 536: /* Shift Right Word */ 5168 case 539: /* Shift Right Doubleword */ 5169 case 922: /* Extend Sign Halfword */ 5170 case 954: /* Extend Sign Byte */ 5171 case 986: /* Extend Sign Word */ 5172 case 538: /* Count Trailing Zeros Word */ 5173 case 570: /* Count Trailing Zeros Doubleword */ 5174 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */ 5175 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */ 5176 5177 if (ext == 444 && tdep->ppc_ppr_regnum >= 0 5178 && (PPC_RS (insn) == PPC_RA (insn)) 5179 && (PPC_RA (insn) == PPC_RB (insn)) 5180 && !PPC_RC (insn)) 5181 { 5182 /* or Rx,Rx,Rx alters PRI in PPR. */ 5183 record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum); 5184 return 0; 5185 } 5186 5187 if (PPC_RC (insn)) 5188 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5189 record_full_arch_list_add_reg (regcache, 5190 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5191 return 0; 5192 5193 /* Store memory. */ 5194 case 181: /* Store Doubleword with Update Indexed */ 5195 case 183: /* Store Word with Update Indexed */ 5196 case 247: /* Store Byte with Update Indexed */ 5197 case 439: /* Store Half Word with Update Indexed */ 5198 case 695: /* Store Floating-Point Single with Update Indexed */ 5199 case 759: /* Store Floating-Point Double with Update Indexed */ 5200 record_full_arch_list_add_reg (regcache, 5201 tdep->ppc_gp0_regnum + PPC_RA (insn)); 5202 /* FALL-THROUGH */ 5203 case 135: /* Store Vector Element Byte Indexed */ 5204 case 167: /* Store Vector Element Halfword Indexed */ 5205 case 199: /* Store Vector Element Word Indexed */ 5206 case 231: /* Store Vector Indexed */ 5207 case 487: /* Store Vector Indexed LRU */ 5208 case 716: /* Store VSX Scalar Doubleword Indexed */ 5209 case 140: /* Store VSX Scalar as Integer Word Indexed */ 5210 case 652: /* Store VSX Scalar Single-Precision Indexed */ 5211 case 972: /* Store VSX Vector Doubleword*2 Indexed */ 5212 case 908: /* Store VSX Vector Word*4 Indexed */ 5213 case 149: /* Store Doubleword Indexed */ 5214 case 151: /* Store Word Indexed */ 5215 case 215: /* Store Byte Indexed */ 5216 case 407: /* Store Half Word Indexed */ 5217 case 694: /* Store Byte Conditional Indexed */ 5218 case 726: /* Store Halfword Conditional Indexed */ 5219 case 150: /* Store Word Conditional Indexed */ 5220 case 214: /* Store Doubleword Conditional Indexed */ 5221 case 182: /* Store Quadword Conditional Indexed */ 5222 case 662: /* Store Word Byte-Reverse Indexed */ 5223 case 918: /* Store Halfword Byte-Reverse Indexed */ 5224 case 660: /* Store Doubleword Byte-Reverse Indexed */ 5225 case 663: /* Store Floating-Point Single Indexed */ 5226 case 727: /* Store Floating-Point Double Indexed */ 5227 case 919: /* Store Floating-Point Double Pair Indexed */ 5228 case 983: /* Store Floating-Point as Integer Word Indexed */ 5229 case 396: /* Store VSX Vector Indexed */ 5230 case 940: /* Store VSX Vector Halfword*8 Indexed */ 5231 case 1004: /* Store VSX Vector Byte*16 Indexed */ 5232 case 909: /* Store VSX Scalar as Integer Byte Indexed */ 5233 case 941: /* Store VSX Scalar as Integer Halfword Indexed */ 5234 if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182) 5235 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5236 5237 ra = 0; 5238 if (PPC_RA (insn) != 0) 5239 regcache_raw_read_unsigned (regcache, 5240 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5241 regcache_raw_read_unsigned (regcache, 5242 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 5243 ea = ra + rb; 5244 5245 switch (ext) 5246 { 5247 case 183: /* Store Word with Update Indexed */ 5248 case 199: /* Store Vector Element Word Indexed */ 5249 case 140: /* Store VSX Scalar as Integer Word Indexed */ 5250 case 652: /* Store VSX Scalar Single-Precision Indexed */ 5251 case 151: /* Store Word Indexed */ 5252 case 150: /* Store Word Conditional Indexed */ 5253 case 662: /* Store Word Byte-Reverse Indexed */ 5254 case 663: /* Store Floating-Point Single Indexed */ 5255 case 695: /* Store Floating-Point Single with Update Indexed */ 5256 case 983: /* Store Floating-Point as Integer Word Indexed */ 5257 size = 4; 5258 break; 5259 case 247: /* Store Byte with Update Indexed */ 5260 case 135: /* Store Vector Element Byte Indexed */ 5261 case 215: /* Store Byte Indexed */ 5262 case 694: /* Store Byte Conditional Indexed */ 5263 case 909: /* Store VSX Scalar as Integer Byte Indexed */ 5264 size = 1; 5265 break; 5266 case 439: /* Store Halfword with Update Indexed */ 5267 case 167: /* Store Vector Element Halfword Indexed */ 5268 case 407: /* Store Halfword Indexed */ 5269 case 726: /* Store Halfword Conditional Indexed */ 5270 case 918: /* Store Halfword Byte-Reverse Indexed */ 5271 case 941: /* Store VSX Scalar as Integer Halfword Indexed */ 5272 size = 2; 5273 break; 5274 case 181: /* Store Doubleword with Update Indexed */ 5275 case 716: /* Store VSX Scalar Doubleword Indexed */ 5276 case 149: /* Store Doubleword Indexed */ 5277 case 214: /* Store Doubleword Conditional Indexed */ 5278 case 660: /* Store Doubleword Byte-Reverse Indexed */ 5279 case 727: /* Store Floating-Point Double Indexed */ 5280 case 759: /* Store Floating-Point Double with Update Indexed */ 5281 size = 8; 5282 break; 5283 case 972: /* Store VSX Vector Doubleword*2 Indexed */ 5284 case 908: /* Store VSX Vector Word*4 Indexed */ 5285 case 182: /* Store Quadword Conditional Indexed */ 5286 case 231: /* Store Vector Indexed */ 5287 case 487: /* Store Vector Indexed LRU */ 5288 case 919: /* Store Floating-Point Double Pair Indexed */ 5289 case 396: /* Store VSX Vector Indexed */ 5290 case 940: /* Store VSX Vector Halfword*8 Indexed */ 5291 case 1004: /* Store VSX Vector Byte*16 Indexed */ 5292 size = 16; 5293 break; 5294 default: 5295 gdb_assert (0); 5296 } 5297 5298 /* Align address for Store Vector instructions. */ 5299 switch (ext) 5300 { 5301 case 167: /* Store Vector Element Halfword Indexed */ 5302 ea = ea & ~0x1ULL; 5303 break; 5304 5305 case 199: /* Store Vector Element Word Indexed */ 5306 ea = ea & ~0x3ULL; 5307 break; 5308 5309 case 231: /* Store Vector Indexed */ 5310 case 487: /* Store Vector Indexed LRU */ 5311 ea = ea & ~0xfULL; 5312 break; 5313 } 5314 5315 record_full_arch_list_add_mem (ea, size); 5316 return 0; 5317 5318 case 141: /* Store VSX Vector Rightmost Byte Indexed */ 5319 case 173: /* Store VSX Vector Rightmost Halfword Indexed */ 5320 case 205: /* Store VSX Vector Rightmost Word Indexed */ 5321 case 237: /* Store VSX Vector Rightmost Doubleword Indexed */ 5322 switch(ext) 5323 { 5324 case 141: nb = 1; 5325 break; 5326 case 173: nb = 2; 5327 break; 5328 case 205: nb = 4; 5329 break; 5330 case 237: nb = 8; 5331 break; 5332 } 5333 ra = 0; 5334 if (PPC_RA (insn) != 0) 5335 regcache_raw_read_unsigned (regcache, 5336 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5337 regcache_raw_read_unsigned (regcache, 5338 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 5339 ea = ra + rb; 5340 record_full_arch_list_add_mem (ea, nb); 5341 return 0; 5342 5343 case 397: /* Store VSX Vector with Length */ 5344 case 429: /* Store VSX Vector Left-justified with Length */ 5345 ra = 0; 5346 if (PPC_RA (insn) != 0) 5347 regcache_raw_read_unsigned (regcache, 5348 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5349 ea = ra; 5350 regcache_raw_read_unsigned (regcache, 5351 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 5352 /* Store up to 16 bytes. */ 5353 nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff); 5354 if (nb > 0) 5355 record_full_arch_list_add_mem (ea, nb); 5356 return 0; 5357 5358 case 461: /* Store VSX Vector Paired Indexed */ 5359 { 5360 if (PPC_RA (insn) != 0) 5361 regcache_raw_read_unsigned (regcache, 5362 tdep->ppc_gp0_regnum 5363 + PPC_RA (insn), &ea); 5364 regcache_raw_read_unsigned (regcache, 5365 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 5366 ea += rb; 5367 record_full_arch_list_add_mem (ea, 32); 5368 return 0; 5369 } 5370 5371 case 710: /* Store Word Atomic */ 5372 case 742: /* Store Doubleword Atomic */ 5373 ra = 0; 5374 if (PPC_RA (insn) != 0) 5375 regcache_raw_read_unsigned (regcache, 5376 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5377 ea = ra; 5378 switch (ext) 5379 { 5380 case 710: /* Store Word Atomic */ 5381 size = 8; 5382 break; 5383 case 742: /* Store Doubleword Atomic */ 5384 size = 16; 5385 break; 5386 default: 5387 gdb_assert (0); 5388 } 5389 record_full_arch_list_add_mem (ea, size); 5390 return 0; 5391 5392 case 725: /* Store String Word Immediate */ 5393 ra = 0; 5394 if (PPC_RA (insn) != 0) 5395 regcache_raw_read_unsigned (regcache, 5396 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5397 ea += ra; 5398 5399 nb = PPC_NB (insn); 5400 if (nb == 0) 5401 nb = 32; 5402 5403 record_full_arch_list_add_mem (ea, nb); 5404 5405 return 0; 5406 5407 case 661: /* Store String Word Indexed */ 5408 ra = 0; 5409 if (PPC_RA (insn) != 0) 5410 regcache_raw_read_unsigned (regcache, 5411 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5412 ea += ra; 5413 5414 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer); 5415 nb = PPC_XER_NB (xer); 5416 5417 if (nb != 0) 5418 { 5419 regcache_raw_read_unsigned (regcache, 5420 tdep->ppc_gp0_regnum + PPC_RB (insn), 5421 &rb); 5422 ea += rb; 5423 record_full_arch_list_add_mem (ea, nb); 5424 } 5425 5426 return 0; 5427 5428 case 467: /* Move To Special Purpose Register */ 5429 switch (PPC_SPR (insn)) 5430 { 5431 case 1: /* XER */ 5432 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 5433 return 0; 5434 case 3: /* DSCR */ 5435 if (tdep->ppc_dscr_regnum >= 0) 5436 record_full_arch_list_add_reg (regcache, tdep->ppc_dscr_regnum); 5437 return 0; 5438 case 8: /* LR */ 5439 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 5440 return 0; 5441 case 9: /* CTR */ 5442 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 5443 return 0; 5444 case 256: /* VRSAVE */ 5445 record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum); 5446 return 0; 5447 case 815: /* TAR */ 5448 if (tdep->ppc_tar_regnum >= 0) 5449 record_full_arch_list_add_reg (regcache, tdep->ppc_tar_regnum); 5450 return 0; 5451 case 896: 5452 case 898: /* PPR */ 5453 if (tdep->ppc_ppr_regnum >= 0) 5454 record_full_arch_list_add_reg (regcache, tdep->ppc_ppr_regnum); 5455 return 0; 5456 } 5457 5458 goto UNKNOWN_OP; 5459 5460 case 147: /* Move To Split Little Endian */ 5461 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); 5462 return 0; 5463 5464 case 512: /* Move to Condition Register from XER */ 5465 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5466 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 5467 return 0; 5468 5469 case 4: /* Trap Word */ 5470 case 68: /* Trap Doubleword */ 5471 case 430: /* Clear BHRB */ 5472 case 598: /* Synchronize */ 5473 case 62: /* Wait for Interrupt */ 5474 case 30: /* Wait */ 5475 case 22: /* Instruction Cache Block Touch */ 5476 case 854: /* Enforce In-order Execution of I/O */ 5477 case 246: /* Data Cache Block Touch for Store */ 5478 case 54: /* Data Cache Block Store */ 5479 case 86: /* Data Cache Block Flush */ 5480 case 278: /* Data Cache Block Touch */ 5481 case 758: /* Data Cache Block Allocate */ 5482 case 982: /* Instruction Cache Block Invalidate */ 5483 case 774: /* Copy */ 5484 case 838: /* CP_Abort */ 5485 return 0; 5486 5487 case 654: /* Transaction Begin */ 5488 case 686: /* Transaction End */ 5489 case 750: /* Transaction Suspend or Resume */ 5490 case 782: /* Transaction Abort Word Conditional */ 5491 case 814: /* Transaction Abort Doubleword Conditional */ 5492 case 846: /* Transaction Abort Word Conditional Immediate */ 5493 case 878: /* Transaction Abort Doubleword Conditional Immediate */ 5494 case 910: /* Transaction Abort */ 5495 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum); 5496 /* FALL-THROUGH */ 5497 case 718: /* Transaction Check */ 5498 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5499 return 0; 5500 5501 case 1014: /* Data Cache Block set to Zero */ 5502 if (target_auxv_search (AT_DCACHEBSIZE, &at_dcsz) <= 0 5503 || at_dcsz == 0) 5504 at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */ 5505 5506 ra = 0; 5507 if (PPC_RA (insn) != 0) 5508 regcache_raw_read_unsigned (regcache, 5509 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra); 5510 regcache_raw_read_unsigned (regcache, 5511 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb); 5512 ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1)); 5513 record_full_arch_list_add_mem (ea, at_dcsz); 5514 return 0; 5515 5516 case 177: 5517 if (ppc_process_record_op31_177 (gdbarch, regcache, insn) == 0) 5518 return 0; 5519 } 5520 5521 UNKNOWN_OP: 5522 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 5523 "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext); 5524 return -1; 5525 } 5526 5527 /* Parse and record instructions of primary opcode-59 at ADDR. 5528 Return 0 if successful. */ 5529 5530 static int 5531 ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache, 5532 CORE_ADDR addr, uint32_t insn) 5533 { 5534 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 5535 int ext = PPC_EXTOP (insn); 5536 int at = PPC_FIELD (insn, 6, 3); 5537 5538 /* Note the mnemonics for the pmxvf64ger* instructions were officially 5539 changed to pmdmxvf64ger*. The old mnemonics are still supported as 5540 extended mnemonics. */ 5541 5542 switch (ext & 0x1f) 5543 { 5544 case 18: /* Floating Divide */ 5545 case 20: /* Floating Subtract */ 5546 case 21: /* Floating Add */ 5547 case 22: /* Floating Square Root */ 5548 case 24: /* Floating Reciprocal Estimate */ 5549 case 25: /* Floating Multiply */ 5550 case 26: /* Floating Reciprocal Square Root Estimate */ 5551 case 28: /* Floating Multiply-Subtract */ 5552 case 29: /* Floating Multiply-Add */ 5553 case 30: /* Floating Negative Multiply-Subtract */ 5554 case 31: /* Floating Negative Multiply-Add */ 5555 record_full_arch_list_add_reg (regcache, 5556 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5557 if (PPC_RC (insn)) 5558 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5559 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5560 5561 return 0; 5562 } 5563 5564 /* MMA instructions, keep looking. */ 5565 switch (ext >> 2) /* Additional opcode field is upper 8-bits of ext */ 5566 { 5567 case 3: /* VSX Vector 8-bit Signed/Unsigned Integer GER, xvi8ger4 */ 5568 case 2: /* VSX Vector 8-bit Signed/Unsigned Integer GER Positive 5569 multiply, Positive accumulate, xvi8ger4pp */ 5570 5571 case 99: /* VSX Vector 8-bit Signed/Unsigned Integer GER with 5572 Saturate Positive multiply, Positive accumulate, 5573 xvi8ger4spp */ 5574 5575 case 35: /* VSX Vector 4-bit Signed Integer GER, xvi4ger8 */ 5576 case 34: /* VSX Vector 4-bit Signed Integer GER Positive multiply, 5577 Positive accumulate, xvi4ger8pp */ 5578 5579 case 75: /* VSX Vector 16-bit Signed Integer GER, xvi16ger2 */ 5580 case 107: /* VSX Vector 16-bit Signed Integer GER Positive multiply, 5581 Positive accumulate, xvi16ger2pp */ 5582 5583 case 43: /* VSX Vector 16-bit Signed Integer GER with Saturation, 5584 xvi16ger2s */ 5585 case 42: /* VSX Vector 16-bit Signed Integer GER with Saturation 5586 Positive multiply, Positive accumulate, xvi16ger2spp */ 5587 ppc_record_ACC_fpscr (regcache, tdep, at, false); 5588 return 0; 5589 5590 case 19: /* VSX Vector 16-bit Floating-Point GER, xvf16ger2 */ 5591 case 18: /* VSX Vector 16-bit Floating-Point GER Positive multiply, 5592 Positive accumulate, xvf16ger2pp */ 5593 case 146: /* VSX Vector 16-bit Floating-Point GER Positive multiply, 5594 Negative accumulate, xvf16ger2pn */ 5595 case 82: /* VSX Vector 16-bit Floating-Point GER Negative multiply, 5596 Positive accumulate, xvf16ger2np */ 5597 case 210: /* VSX Vector 16-bit Floating-Point GER Negative multiply, 5598 Negative accumulate, xvf16ger2nn */ 5599 5600 case 27: /* VSX Vector 32-bit Floating-Point GER, xvf32ger */ 5601 case 26: /* VSX Vector 32-bit Floating-Point GER Positive multiply, 5602 Positive accumulate, xvf32gerpp */ 5603 case 154: /* VSX Vector 32-bit Floating-Point GER Positive multiply, 5604 Negative accumulate, xvf32gerpn */ 5605 case 90: /* VSX Vector 32-bit Floating-Point GER Negative multiply, 5606 Positive accumulate, xvf32gernp */ 5607 case 218: /* VSX Vector 32-bit Floating-Point GER Negative multiply, 5608 Negative accumulate, xvf32gernn */ 5609 5610 case 59: /* VSX Vector 64-bit Floating-Point GER, pmdmxvf64ger 5611 (pmxvf64ger) */ 5612 case 58: /* VSX Vector 64-bit Floating-Point GER Positive multiply, 5613 Positive accumulate, xvf64gerpp */ 5614 case 186: /* VSX Vector 64-bit Floating-Point GER Positive multiply, 5615 Negative accumulate, xvf64gerpn */ 5616 case 122: /* VSX Vector 64-bit Floating-Point GER Negative multiply, 5617 Positive accumulate, xvf64gernp */ 5618 case 250: /* VSX Vector 64-bit Floating-Point GER Negative multiply, 5619 Negative accumulate, pmdmxvf64gernn (pmxvf64gernn) */ 5620 5621 case 51: /* VSX Vector bfloat16 GER, xvbf16ger2 */ 5622 case 50: /* VSX Vector bfloat16 GER Positive multiply, 5623 Positive accumulate, xvbf16ger2pp */ 5624 case 178: /* VSX Vector bfloat16 GER Positive multiply, 5625 Negative accumulate, xvbf16ger2pn */ 5626 case 114: /* VSX Vector bfloat16 GER Negative multiply, 5627 Positive accumulate, xvbf16ger2np */ 5628 case 242: /* VSX Vector bfloat16 GER Negative multiply, 5629 Negative accumulate, xvbf16ger2nn */ 5630 ppc_record_ACC_fpscr (regcache, tdep, at, true); 5631 return 0; 5632 } 5633 5634 switch (ext) 5635 { 5636 case 2: /* DFP Add */ 5637 case 3: /* DFP Quantize */ 5638 case 34: /* DFP Multiply */ 5639 case 35: /* DFP Reround */ 5640 case 67: /* DFP Quantize Immediate */ 5641 case 99: /* DFP Round To FP Integer With Inexact */ 5642 case 227: /* DFP Round To FP Integer Without Inexact */ 5643 case 258: /* DFP Convert To DFP Long! */ 5644 case 290: /* DFP Convert To Fixed */ 5645 case 514: /* DFP Subtract */ 5646 case 546: /* DFP Divide */ 5647 case 770: /* DFP Round To DFP Short! */ 5648 case 802: /* DFP Convert From Fixed */ 5649 case 834: /* DFP Encode BCD To DPD */ 5650 if (PPC_RC (insn)) 5651 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5652 record_full_arch_list_add_reg (regcache, 5653 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5654 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5655 return 0; 5656 5657 case 130: /* DFP Compare Ordered */ 5658 case 162: /* DFP Test Exponent */ 5659 case 194: /* DFP Test Data Class */ 5660 case 226: /* DFP Test Data Group */ 5661 case 642: /* DFP Compare Unordered */ 5662 case 674: /* DFP Test Significance */ 5663 case 675: /* DFP Test Significance Immediate */ 5664 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5665 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5666 return 0; 5667 5668 case 66: /* DFP Shift Significand Left Immediate */ 5669 case 98: /* DFP Shift Significand Right Immediate */ 5670 case 322: /* DFP Decode DPD To BCD */ 5671 case 354: /* DFP Extract Biased Exponent */ 5672 case 866: /* DFP Insert Biased Exponent */ 5673 record_full_arch_list_add_reg (regcache, 5674 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5675 if (PPC_RC (insn)) 5676 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5677 return 0; 5678 5679 case 846: /* Floating Convert From Integer Doubleword Single */ 5680 case 974: /* Floating Convert From Integer Doubleword Unsigned 5681 Single */ 5682 record_full_arch_list_add_reg (regcache, 5683 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 5684 if (PPC_RC (insn)) 5685 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5686 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5687 5688 return 0; 5689 } 5690 5691 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 5692 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext); 5693 return -1; 5694 } 5695 5696 /* Parse and record an XX2-Form instruction with opcode 60 at ADDR. The 5697 word instruction is an argument insn. Return 0 if successful. */ 5698 5699 static int 5700 ppc_process_record_op60_XX2 (struct gdbarch *gdbarch, 5701 struct regcache *regcache, 5702 CORE_ADDR addr, uint32_t insn) 5703 { 5704 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 5705 int RA_opcode = PPC_RA(insn); 5706 5707 switch (RA_opcode) 5708 { 5709 case 2: /* VSX Vector Test Least-Significant Bit by Byte */ 5710 case 25: /* VSX Vector round and Convert Single-Precision format 5711 to Half-Precision format. Only changes the CR 5712 field. */ 5713 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5714 return 0; 5715 case 17: /* VSX Vector Convert with round Single-Precision 5716 to bfloat16 format */ 5717 case 24: /* VSX Vector Convert Half-Precision format to 5718 Single-Precision format */ 5719 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5720 /* Fall-through */ 5721 case 0: /* VSX Vector Extract Exponent Double-Precision */ 5722 case 1: /* VSX Vector Extract Significand Double-Precision */ 5723 case 7: /* VSX Vector Byte-Reverse Halfword */ 5724 case 8: /* VSX Vector Extract Exponent Single-Precision */ 5725 case 9: /* VSX Vector Extract Significand Single-Precision */ 5726 case 15: /* VSX Vector Byte-Reverse Word */ 5727 case 16: /* VSX Vector Convert bfloat16 to Single-Precision 5728 format Non-signaling */ 5729 case 23: /* VSX Vector Byte-Reverse Doubleword */ 5730 case 31: /* VSX Vector Byte-Reverse Quadword */ 5731 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5732 return 0; 5733 } 5734 5735 return -1; 5736 } 5737 5738 /* Parse and record instructions of primary opcode-60 at ADDR. 5739 Return 0 if successful. */ 5740 5741 static int 5742 ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache, 5743 CORE_ADDR addr, uint32_t insn) 5744 { 5745 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 5746 int ext = PPC_EXTOP (insn); 5747 5748 switch (ext >> 2) 5749 { 5750 case 0: /* VSX Scalar Add Single-Precision */ 5751 case 32: /* VSX Scalar Add Double-Precision */ 5752 case 24: /* VSX Scalar Divide Single-Precision */ 5753 case 56: /* VSX Scalar Divide Double-Precision */ 5754 case 176: /* VSX Scalar Copy Sign Double-Precision */ 5755 case 33: /* VSX Scalar Multiply-Add Double-Precision */ 5756 case 41: /* ditto */ 5757 case 1: /* VSX Scalar Multiply-Add Single-Precision */ 5758 case 9: /* ditto */ 5759 case 160: /* VSX Scalar Maximum Double-Precision */ 5760 case 168: /* VSX Scalar Minimum Double-Precision */ 5761 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */ 5762 case 57: /* ditto */ 5763 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */ 5764 case 25: /* ditto */ 5765 case 48: /* VSX Scalar Multiply Double-Precision */ 5766 case 16: /* VSX Scalar Multiply Single-Precision */ 5767 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */ 5768 case 169: /* ditto */ 5769 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */ 5770 case 137: /* ditto */ 5771 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */ 5772 case 185: /* ditto */ 5773 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */ 5774 case 153: /* ditto */ 5775 case 40: /* VSX Scalar Subtract Double-Precision */ 5776 case 8: /* VSX Scalar Subtract Single-Precision */ 5777 case 96: /* VSX Vector Add Double-Precision */ 5778 case 64: /* VSX Vector Add Single-Precision */ 5779 case 120: /* VSX Vector Divide Double-Precision */ 5780 case 88: /* VSX Vector Divide Single-Precision */ 5781 case 97: /* VSX Vector Multiply-Add Double-Precision */ 5782 case 105: /* ditto */ 5783 case 65: /* VSX Vector Multiply-Add Single-Precision */ 5784 case 73: /* ditto */ 5785 case 224: /* VSX Vector Maximum Double-Precision */ 5786 case 192: /* VSX Vector Maximum Single-Precision */ 5787 case 232: /* VSX Vector Minimum Double-Precision */ 5788 case 200: /* VSX Vector Minimum Single-Precision */ 5789 case 113: /* VSX Vector Multiply-Subtract Double-Precision */ 5790 case 121: /* ditto */ 5791 case 81: /* VSX Vector Multiply-Subtract Single-Precision */ 5792 case 89: /* ditto */ 5793 case 112: /* VSX Vector Multiply Double-Precision */ 5794 case 80: /* VSX Vector Multiply Single-Precision */ 5795 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */ 5796 case 233: /* ditto */ 5797 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */ 5798 case 201: /* ditto */ 5799 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */ 5800 case 249: /* ditto */ 5801 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */ 5802 case 217: /* ditto */ 5803 case 104: /* VSX Vector Subtract Double-Precision */ 5804 case 72: /* VSX Vector Subtract Single-Precision */ 5805 case 128: /* VSX Scalar Maximum Type-C Double-Precision */ 5806 case 136: /* VSX Scalar Minimum Type-C Double-Precision */ 5807 case 144: /* VSX Scalar Maximum Type-J Double-Precision */ 5808 case 152: /* VSX Scalar Minimum Type-J Double-Precision */ 5809 case 3: /* VSX Scalar Compare Equal Double-Precision */ 5810 case 11: /* VSX Scalar Compare Greater Than Double-Precision */ 5811 case 19: /* VSX Scalar Compare Greater Than or Equal 5812 Double-Precision */ 5813 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5814 /* FALL-THROUGH */ 5815 case 240: /* VSX Vector Copy Sign Double-Precision */ 5816 case 208: /* VSX Vector Copy Sign Single-Precision */ 5817 case 130: /* VSX Logical AND */ 5818 case 138: /* VSX Logical AND with Complement */ 5819 case 186: /* VSX Logical Equivalence */ 5820 case 178: /* VSX Logical NAND */ 5821 case 170: /* VSX Logical OR with Complement */ 5822 case 162: /* VSX Logical NOR */ 5823 case 146: /* VSX Logical OR */ 5824 case 154: /* VSX Logical XOR */ 5825 case 18: /* VSX Merge High Word */ 5826 case 50: /* VSX Merge Low Word */ 5827 case 10: /* VSX Permute Doubleword Immediate (DM=0) */ 5828 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */ 5829 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */ 5830 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */ 5831 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */ 5832 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */ 5833 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */ 5834 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */ 5835 case 216: /* VSX Vector Insert Exponent Single-Precision */ 5836 case 248: /* VSX Vector Insert Exponent Double-Precision */ 5837 case 26: /* VSX Vector Permute */ 5838 case 58: /* VSX Vector Permute Right-indexed */ 5839 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */ 5840 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */ 5841 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */ 5842 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */ 5843 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5844 return 0; 5845 5846 case 61: /* VSX Scalar Test for software Divide Double-Precision */ 5847 case 125: /* VSX Vector Test for software Divide Double-Precision */ 5848 case 93: /* VSX Vector Test for software Divide Single-Precision */ 5849 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5850 return 0; 5851 5852 case 35: /* VSX Scalar Compare Unordered Double-Precision */ 5853 case 43: /* VSX Scalar Compare Ordered Double-Precision */ 5854 case 59: /* VSX Scalar Compare Exponents Double-Precision */ 5855 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5856 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5857 return 0; 5858 } 5859 5860 switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */ 5861 { 5862 case 99: /* VSX Vector Compare Equal To Double-Precision */ 5863 case 67: /* VSX Vector Compare Equal To Single-Precision */ 5864 case 115: /* VSX Vector Compare Greater Than or 5865 Equal To Double-Precision */ 5866 case 83: /* VSX Vector Compare Greater Than or 5867 Equal To Single-Precision */ 5868 case 107: /* VSX Vector Compare Greater Than Double-Precision */ 5869 case 75: /* VSX Vector Compare Greater Than Single-Precision */ 5870 if (PPC_Rc (insn)) 5871 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 5872 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 5873 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 5874 return 0; 5875 } 5876 5877 switch (ext >> 1) 5878 { 5879 case 265: /* VSX Scalar round Double-Precision to 5880 Single-Precision and Convert to 5881 Single-Precision format */ 5882 case 344: /* VSX Scalar truncate Double-Precision to 5883 Integer and Convert to Signed Integer 5884 Doubleword format with Saturate */ 5885 case 88: /* VSX Scalar truncate Double-Precision to 5886 Integer and Convert to Signed Integer Word 5887 Format with Saturate */ 5888 case 328: /* VSX Scalar truncate Double-Precision integer 5889 and Convert to Unsigned Integer Doubleword 5890 Format with Saturate */ 5891 case 72: /* VSX Scalar truncate Double-Precision to 5892 Integer and Convert to Unsigned Integer Word 5893 Format with Saturate */ 5894 case 329: /* VSX Scalar Convert Single-Precision to 5895 Double-Precision format */ 5896 case 376: /* VSX Scalar Convert Signed Integer 5897 Doubleword to floating-point format and 5898 Round to Double-Precision format */ 5899 case 312: /* VSX Scalar Convert Signed Integer 5900 Doubleword to floating-point format and 5901 round to Single-Precision */ 5902 case 360: /* VSX Scalar Convert Unsigned Integer 5903 Doubleword to floating-point format and 5904 Round to Double-Precision format */ 5905 case 296: /* VSX Scalar Convert Unsigned Integer 5906 Doubleword to floating-point format and 5907 Round to Single-Precision */ 5908 case 73: /* VSX Scalar Round to Double-Precision Integer 5909 Using Round to Nearest Away */ 5910 case 107: /* VSX Scalar Round to Double-Precision Integer 5911 Exact using Current rounding mode */ 5912 case 121: /* VSX Scalar Round to Double-Precision Integer 5913 Using Round toward -Infinity */ 5914 case 105: /* VSX Scalar Round to Double-Precision Integer 5915 Using Round toward +Infinity */ 5916 case 89: /* VSX Scalar Round to Double-Precision Integer 5917 Using Round toward Zero */ 5918 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */ 5919 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */ 5920 case 281: /* VSX Scalar Round to Single-Precision */ 5921 case 74: /* VSX Scalar Reciprocal Square Root Estimate 5922 Double-Precision */ 5923 case 10: /* VSX Scalar Reciprocal Square Root Estimate 5924 Single-Precision */ 5925 case 75: /* VSX Scalar Square Root Double-Precision */ 5926 case 11: /* VSX Scalar Square Root Single-Precision */ 5927 case 393: /* VSX Vector round Double-Precision to 5928 Single-Precision and Convert to 5929 Single-Precision format */ 5930 case 472: /* VSX Vector truncate Double-Precision to 5931 Integer and Convert to Signed Integer 5932 Doubleword format with Saturate */ 5933 case 216: /* VSX Vector truncate Double-Precision to 5934 Integer and Convert to Signed Integer Word 5935 Format with Saturate */ 5936 case 456: /* VSX Vector truncate Double-Precision to 5937 Integer and Convert to Unsigned Integer 5938 Doubleword format with Saturate */ 5939 case 200: /* VSX Vector truncate Double-Precision to 5940 Integer and Convert to Unsigned Integer Word 5941 Format with Saturate */ 5942 case 457: /* VSX Vector Convert Single-Precision to 5943 Double-Precision format */ 5944 case 408: /* VSX Vector truncate Single-Precision to 5945 Integer and Convert to Signed Integer 5946 Doubleword format with Saturate */ 5947 case 152: /* VSX Vector truncate Single-Precision to 5948 Integer and Convert to Signed Integer Word 5949 Format with Saturate */ 5950 case 392: /* VSX Vector truncate Single-Precision to 5951 Integer and Convert to Unsigned Integer 5952 Doubleword format with Saturate */ 5953 case 136: /* VSX Vector truncate Single-Precision to 5954 Integer and Convert to Unsigned Integer Word 5955 Format with Saturate */ 5956 case 504: /* VSX Vector Convert and round Signed Integer 5957 Doubleword to Double-Precision format */ 5958 case 440: /* VSX Vector Convert and round Signed Integer 5959 Doubleword to Single-Precision format */ 5960 case 248: /* VSX Vector Convert Signed Integer Word to 5961 Double-Precision format */ 5962 case 184: /* VSX Vector Convert and round Signed Integer 5963 Word to Single-Precision format */ 5964 case 488: /* VSX Vector Convert and round Unsigned 5965 Integer Doubleword to Double-Precision format */ 5966 case 424: /* VSX Vector Convert and round Unsigned 5967 Integer Doubleword to Single-Precision format */ 5968 case 232: /* VSX Vector Convert and round Unsigned 5969 Integer Word to Double-Precision format */ 5970 case 168: /* VSX Vector Convert and round Unsigned 5971 Integer Word to Single-Precision format */ 5972 case 201: /* VSX Vector Round to Double-Precision 5973 Integer using round to Nearest Away */ 5974 case 235: /* VSX Vector Round to Double-Precision 5975 Integer Exact using Current rounding mode */ 5976 case 249: /* VSX Vector Round to Double-Precision 5977 Integer using round toward -Infinity */ 5978 case 233: /* VSX Vector Round to Double-Precision 5979 Integer using round toward +Infinity */ 5980 case 217: /* VSX Vector Round to Double-Precision 5981 Integer using round toward Zero */ 5982 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */ 5983 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */ 5984 case 137: /* VSX Vector Round to Single-Precision Integer 5985 Using Round to Nearest Away */ 5986 case 171: /* VSX Vector Round to Single-Precision Integer 5987 Exact Using Current rounding mode */ 5988 case 185: /* VSX Vector Round to Single-Precision Integer 5989 Using Round toward -Infinity */ 5990 case 169: /* VSX Vector Round to Single-Precision Integer 5991 Using Round toward +Infinity */ 5992 case 153: /* VSX Vector Round to Single-Precision Integer 5993 Using round toward Zero */ 5994 case 202: /* VSX Vector Reciprocal Square Root Estimate 5995 Double-Precision */ 5996 case 138: /* VSX Vector Reciprocal Square Root Estimate 5997 Single-Precision */ 5998 case 203: /* VSX Vector Square Root Double-Precision */ 5999 case 139: /* VSX Vector Square Root Single-Precision */ 6000 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6001 /* FALL-THROUGH */ 6002 case 345: /* VSX Scalar Absolute Value Double-Precision */ 6003 case 267: /* VSX Scalar Convert Scalar Single-Precision to 6004 Vector Single-Precision format Non-signalling */ 6005 case 331: /* VSX Scalar Convert Single-Precision to 6006 Double-Precision format Non-signalling */ 6007 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */ 6008 case 377: /* VSX Scalar Negate Double-Precision */ 6009 case 473: /* VSX Vector Absolute Value Double-Precision */ 6010 case 409: /* VSX Vector Absolute Value Single-Precision */ 6011 case 489: /* VSX Vector Negative Absolute Value Double-Precision */ 6012 case 425: /* VSX Vector Negative Absolute Value Single-Precision */ 6013 case 505: /* VSX Vector Negate Double-Precision */ 6014 case 441: /* VSX Vector Negate Single-Precision */ 6015 case 164: /* VSX Splat Word */ 6016 case 165: /* VSX Vector Extract Unsigned Word */ 6017 case 181: /* VSX Vector Insert Word */ 6018 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6019 return 0; 6020 6021 case 298: /* VSX Scalar Test Data Class Single-Precision */ 6022 case 362: /* VSX Scalar Test Data Class Double-Precision */ 6023 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6024 /* FALL-THROUGH */ 6025 case 106: /* VSX Scalar Test for software Square Root 6026 Double-Precision */ 6027 case 234: /* VSX Vector Test for software Square Root 6028 Double-Precision */ 6029 case 170: /* VSX Vector Test for software Square Root 6030 Single-Precision */ 6031 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6032 return 0; 6033 6034 case 347: 6035 switch (PPC_FIELD (insn, 11, 5)) 6036 { 6037 case 0: /* VSX Scalar Extract Exponent Double-Precision */ 6038 case 1: /* VSX Scalar Extract Significand Double-Precision */ 6039 record_full_arch_list_add_reg (regcache, 6040 tdep->ppc_gp0_regnum + PPC_RT (insn)); 6041 return 0; 6042 case 16: /* VSX Scalar Convert Half-Precision format to 6043 Double-Precision format */ 6044 case 17: /* VSX Scalar round & Convert Double-Precision format 6045 to Half-Precision format */ 6046 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6047 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6048 return 0; 6049 } 6050 break; 6051 6052 case 475: 6053 if (ppc_process_record_op60_XX2 (gdbarch, regcache, addr, insn) != 0) 6054 return -1; 6055 return 0; 6056 } 6057 6058 switch (ext) 6059 { 6060 case 360: 6061 if (PPC_FIELD (insn, 11, 2) == 0) /* VSX Vector Splat Immediate Byte */ 6062 { 6063 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6064 return 0; 6065 } 6066 if (PPC_FIELD (insn, 11, 5) == 31) /* Load VSX Vector Special Value 6067 Quadword */ 6068 { 6069 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6070 return 0; 6071 } 6072 break; 6073 case 916: /* VSX Vector Generate PCV from Byte Mask */ 6074 case 917: /* VSX Vector Generate PCV from Halfword Mask */ 6075 case 948: /* VSX Vector Generate PCV from Word Mask */ 6076 case 949: /* VSX Vector Generate PCV from Doubleword Mask */ 6077 case 918: /* VSX Scalar Insert Exponent Double-Precision */ 6078 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6079 return 0; 6080 } 6081 6082 if (((ext >> 3) & 0x3) == 3) /* VSX Select */ 6083 { 6084 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6085 return 0; 6086 } 6087 6088 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 6089 "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext); 6090 return -1; 6091 } 6092 6093 /* Parse and record instructions of primary opcode-61 at ADDR. 6094 Return 0 if successful. */ 6095 6096 static int 6097 ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache, 6098 CORE_ADDR addr, uint32_t insn) 6099 { 6100 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6101 ULONGEST ea = 0; 6102 int size; 6103 6104 switch (insn & 0x3) 6105 { 6106 case 0: /* Store Floating-Point Double Pair */ 6107 case 2: /* Store VSX Scalar Doubleword */ 6108 case 3: /* Store VSX Scalar Single */ 6109 if (PPC_RA (insn) != 0) 6110 regcache_raw_read_unsigned (regcache, 6111 tdep->ppc_gp0_regnum + PPC_RA (insn), 6112 &ea); 6113 ea += PPC_DS (insn) << 2; 6114 switch (insn & 0x3) 6115 { 6116 case 0: /* Store Floating-Point Double Pair */ 6117 size = 16; 6118 break; 6119 case 2: /* Store VSX Scalar Doubleword */ 6120 size = 8; 6121 break; 6122 case 3: /* Store VSX Scalar Single */ 6123 size = 4; 6124 break; 6125 default: 6126 gdb_assert (0); 6127 } 6128 record_full_arch_list_add_mem (ea, size); 6129 return 0; 6130 } 6131 6132 switch (insn & 0x7) 6133 { 6134 case 1: /* Load VSX Vector */ 6135 ppc_record_vsr (regcache, tdep, PPC_XT (insn)); 6136 return 0; 6137 case 5: /* Store VSX Vector */ 6138 if (PPC_RA (insn) != 0) 6139 regcache_raw_read_unsigned (regcache, 6140 tdep->ppc_gp0_regnum + PPC_RA (insn), 6141 &ea); 6142 ea += PPC_DQ (insn) << 4; 6143 record_full_arch_list_add_mem (ea, 16); 6144 return 0; 6145 } 6146 6147 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 6148 "at %s.\n", insn, paddress (gdbarch, addr)); 6149 return -1; 6150 } 6151 6152 /* Parse and record instructions of primary opcode-63 at ADDR. 6153 Return 0 if successful. */ 6154 6155 static int 6156 ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache, 6157 CORE_ADDR addr, uint32_t insn) 6158 { 6159 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6160 int ext = PPC_EXTOP (insn); 6161 int tmp; 6162 6163 switch (ext & 0x1f) 6164 { 6165 case 18: /* Floating Divide */ 6166 case 20: /* Floating Subtract */ 6167 case 21: /* Floating Add */ 6168 case 22: /* Floating Square Root */ 6169 case 24: /* Floating Reciprocal Estimate */ 6170 case 25: /* Floating Multiply */ 6171 case 26: /* Floating Reciprocal Square Root Estimate */ 6172 case 28: /* Floating Multiply-Subtract */ 6173 case 29: /* Floating Multiply-Add */ 6174 case 30: /* Floating Negative Multiply-Subtract */ 6175 case 31: /* Floating Negative Multiply-Add */ 6176 record_full_arch_list_add_reg (regcache, 6177 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6178 if (PPC_RC (insn)) 6179 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6180 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6181 return 0; 6182 6183 case 23: /* Floating Select */ 6184 record_full_arch_list_add_reg (regcache, 6185 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6186 if (PPC_RC (insn)) 6187 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6188 return 0; 6189 } 6190 6191 switch (ext & 0xff) 6192 { 6193 case 5: /* VSX Scalar Round to Quad-Precision Integer */ 6194 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended 6195 Precision */ 6196 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6197 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 6198 return 0; 6199 } 6200 6201 switch (ext) 6202 { 6203 case 2: /* DFP Add Quad */ 6204 case 3: /* DFP Quantize Quad */ 6205 case 34: /* DFP Multiply Quad */ 6206 case 35: /* DFP Reround Quad */ 6207 case 67: /* DFP Quantize Immediate Quad */ 6208 case 99: /* DFP Round To FP Integer With Inexact Quad */ 6209 case 227: /* DFP Round To FP Integer Without Inexact Quad */ 6210 case 258: /* DFP Convert To DFP Extended Quad */ 6211 case 514: /* DFP Subtract Quad */ 6212 case 546: /* DFP Divide Quad */ 6213 case 770: /* DFP Round To DFP Long Quad */ 6214 case 802: /* DFP Convert From Fixed Quad */ 6215 case 834: /* DFP Encode BCD To DPD Quad */ 6216 if (PPC_RC (insn)) 6217 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6218 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 6219 record_full_arch_list_add_reg (regcache, tmp); 6220 record_full_arch_list_add_reg (regcache, tmp + 1); 6221 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6222 return 0; 6223 6224 case 130: /* DFP Compare Ordered Quad */ 6225 case 162: /* DFP Test Exponent Quad */ 6226 case 194: /* DFP Test Data Class Quad */ 6227 case 226: /* DFP Test Data Group Quad */ 6228 case 642: /* DFP Compare Unordered Quad */ 6229 case 674: /* DFP Test Significance Quad */ 6230 case 675: /* DFP Test Significance Immediate Quad */ 6231 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6232 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6233 return 0; 6234 6235 case 66: /* DFP Shift Significand Left Immediate Quad */ 6236 case 98: /* DFP Shift Significand Right Immediate Quad */ 6237 case 322: /* DFP Decode DPD To BCD Quad */ 6238 case 866: /* DFP Insert Biased Exponent Quad */ 6239 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1); 6240 record_full_arch_list_add_reg (regcache, tmp); 6241 record_full_arch_list_add_reg (regcache, tmp + 1); 6242 if (PPC_RC (insn)) 6243 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6244 return 0; 6245 6246 case 290: /* DFP Convert To Fixed Quad */ 6247 record_full_arch_list_add_reg (regcache, 6248 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6249 if (PPC_RC (insn)) 6250 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6251 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6252 return 0; 6253 6254 case 354: /* DFP Extract Biased Exponent Quad */ 6255 record_full_arch_list_add_reg (regcache, 6256 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6257 if (PPC_RC (insn)) 6258 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6259 return 0; 6260 6261 case 12: /* Floating Round to Single-Precision */ 6262 case 14: /* Floating Convert To Integer Word */ 6263 case 15: /* Floating Convert To Integer Word 6264 with round toward Zero */ 6265 case 142: /* Floating Convert To Integer Word Unsigned */ 6266 case 143: /* Floating Convert To Integer Word Unsigned 6267 with round toward Zero */ 6268 case 392: /* Floating Round to Integer Nearest */ 6269 case 424: /* Floating Round to Integer Toward Zero */ 6270 case 456: /* Floating Round to Integer Plus */ 6271 case 488: /* Floating Round to Integer Minus */ 6272 case 814: /* Floating Convert To Integer Doubleword */ 6273 case 815: /* Floating Convert To Integer Doubleword 6274 with round toward Zero */ 6275 case 846: /* Floating Convert From Integer Doubleword */ 6276 case 942: /* Floating Convert To Integer Doubleword Unsigned */ 6277 case 943: /* Floating Convert To Integer Doubleword Unsigned 6278 with round toward Zero */ 6279 case 974: /* Floating Convert From Integer Doubleword Unsigned */ 6280 record_full_arch_list_add_reg (regcache, 6281 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6282 if (PPC_RC (insn)) 6283 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6284 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6285 return 0; 6286 6287 case 583: 6288 switch (PPC_FIELD (insn, 11, 5)) 6289 { 6290 case 1: /* Move From FPSCR & Clear Enables */ 6291 case 20: /* Move From FPSCR Control & set DRN */ 6292 case 21: /* Move From FPSCR Control & set DRN Immediate */ 6293 case 22: /* Move From FPSCR Control & set RN */ 6294 case 23: /* Move From FPSCR Control & set RN Immediate */ 6295 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6296 /* Fall through. */ 6297 case 0: /* Move From FPSCR */ 6298 case 24: /* Move From FPSCR Lightweight */ 6299 if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn)) 6300 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6301 record_full_arch_list_add_reg (regcache, 6302 tdep->ppc_fp0_regnum 6303 + PPC_FRT (insn)); 6304 return 0; 6305 } 6306 break; 6307 6308 case 8: /* Floating Copy Sign */ 6309 case 40: /* Floating Negate */ 6310 case 72: /* Floating Move Register */ 6311 case 136: /* Floating Negative Absolute Value */ 6312 case 264: /* Floating Absolute Value */ 6313 record_full_arch_list_add_reg (regcache, 6314 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6315 if (PPC_RC (insn)) 6316 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6317 return 0; 6318 6319 case 838: /* Floating Merge Odd Word */ 6320 case 966: /* Floating Merge Even Word */ 6321 record_full_arch_list_add_reg (regcache, 6322 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 6323 return 0; 6324 6325 case 38: /* Move To FPSCR Bit 1 */ 6326 case 70: /* Move To FPSCR Bit 0 */ 6327 case 134: /* Move To FPSCR Field Immediate */ 6328 case 711: /* Move To FPSCR Fields */ 6329 if (PPC_RC (insn)) 6330 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6331 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6332 return 0; 6333 6334 case 0: /* Floating Compare Unordered */ 6335 case 32: /* Floating Compare Ordered */ 6336 case 64: /* Move to Condition Register from FPSCR */ 6337 case 132: /* VSX Scalar Compare Ordered Quad-Precision */ 6338 case 164: /* VSX Scalar Compare Exponents Quad-Precision */ 6339 case 644: /* VSX Scalar Compare Unordered Quad-Precision */ 6340 case 708: /* VSX Scalar Test Data Class Quad-Precision */ 6341 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6342 /* FALL-THROUGH */ 6343 case 128: /* Floating Test for software Divide */ 6344 case 160: /* Floating Test for software Square Root */ 6345 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 6346 return 0; 6347 6348 case 4: /* VSX Scalar Add Quad-Precision */ 6349 case 36: /* VSX Scalar Multiply Quad-Precision */ 6350 case 388: /* VSX Scalar Multiply-Add Quad-Precision */ 6351 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */ 6352 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */ 6353 case 484: /* VSX Scalar Negative Multiply-Subtract 6354 Quad-Precision */ 6355 case 516: /* VSX Scalar Subtract Quad-Precision */ 6356 case 548: /* VSX Scalar Divide Quad-Precision */ 6357 case 994: 6358 { 6359 switch (PPC_FIELD (insn, 11, 5)) 6360 { 6361 case 0: /* DFP Convert From Fixed Quadword Quad */ 6362 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6363 6364 record_full_arch_list_add_reg (regcache, 6365 tdep->ppc_fp0_regnum 6366 + PPC_FRT (insn)); 6367 record_full_arch_list_add_reg (regcache, 6368 tdep->ppc_fp0_regnum 6369 + PPC_FRT (insn) + 1); 6370 return 0; 6371 case 1: /* DFP Convert To Fixed Quadword Quad */ 6372 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6373 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 6374 return 0; 6375 } 6376 } 6377 6378 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6379 /* FALL-THROUGH */ 6380 case 68: /* VSX Scalar Compare Equal Quad-Precision */ 6381 case 196: /* VSX Scalar Compare Greater Than or Equal 6382 Quad-Precision */ 6383 case 228: /* VSX Scalar Compare Greater Than Quad-Precision */ 6384 case 676: /* VSX Scalar Maximum Type-C Quad-Precision */ 6385 case 740: /* VSX Scalar Minimum Type-C Quad-Precision */ 6386 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6387 /* FALL-THROUGH */ 6388 case 100: /* VSX Scalar Copy Sign Quad-Precision */ 6389 case 868: /* VSX Scalar Insert Exponent Quad-Precision */ 6390 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 6391 return 0; 6392 6393 case 804: 6394 switch (PPC_FIELD (insn, 11, 5)) 6395 { 6396 case 27: /* VSX Scalar Square Root Quad-Precision */ 6397 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6398 /* FALL-THROUGH */ 6399 case 0: /* VSX Scalar Absolute Quad-Precision */ 6400 case 2: /* VSX Scalar Extract Exponent Quad-Precision */ 6401 case 8: /* VSX Scalar Negative Absolute Quad-Precision */ 6402 case 16: /* VSX Scalar Negate Quad-Precision */ 6403 case 18: /* VSX Scalar Extract Significand Quad-Precision */ 6404 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 6405 return 0; 6406 } 6407 break; 6408 6409 case 836: 6410 switch (PPC_FIELD (insn, 11, 5)) 6411 { 6412 case 0: /* VSX Scalar Convert with round to zero 6413 Quad-Precision to Unsigned Quadword */ 6414 case 1: /* VSX Scalar truncate & Convert Quad-Precision format 6415 to Unsigned Word format */ 6416 case 2: /* VSX Scalar Convert Unsigned Doubleword format to 6417 Quad-Precision format */ 6418 case 3: /* VSX Scalar Convert with round 6419 Unsigned Quadword to Quad-Precision */ 6420 case 8: /* VSX Scalar Convert with round to zero 6421 Quad-Precision to Signed Quadword */ 6422 case 9: /* VSX Scalar truncate & Convert Quad-Precision format 6423 to Signed Word format */ 6424 case 10: /* VSX Scalar Convert Signed Doubleword format to 6425 Quad-Precision format */ 6426 case 11: /* VSX Scalar Convert with round 6427 Signed Quadword to Quad-Precision */ 6428 case 17: /* VSX Scalar truncate & Convert Quad-Precision format 6429 to Unsigned Doubleword format */ 6430 case 20: /* VSX Scalar round & Convert Quad-Precision format to 6431 Double-Precision format */ 6432 case 22: /* VSX Scalar Convert Double-Precision format to 6433 Quad-Precision format */ 6434 case 25: /* VSX Scalar truncate & Convert Quad-Precision format 6435 to Signed Doubleword format */ 6436 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum); 6437 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 6438 return 0; 6439 } 6440 } 6441 6442 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 6443 "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext); 6444 return -1; 6445 } 6446 6447 /* Record the prefixed instructions with primary opcode 32. The arguments are 6448 the first 32-bits of the instruction (insn_prefix), and the second 32-bits 6449 of the instruction (insn_suffix). Return 0 on success. */ 6450 6451 static int 6452 ppc_process_record_prefix_op42 (struct gdbarch *gdbarch, 6453 struct regcache *regcache, 6454 uint32_t insn_prefix, uint32_t insn_suffix) 6455 { 6456 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6457 int type = PPC_FIELD (insn_prefix, 6, 2); 6458 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6459 6460 if (ST1 != 0) 6461 return -1; 6462 6463 switch (type) 6464 { 6465 case 0: /* Prefixed Load VSX Scalar Doubleword, plxsd */ 6466 ppc_record_vsr (regcache, tdep, PPC_VRT (insn_suffix) + 32); 6467 break; 6468 case 2: /* Prefixed Load Halfword Algebraic, plha */ 6469 record_full_arch_list_add_reg (regcache, 6470 tdep->ppc_gp0_regnum 6471 + PPC_RT (insn_suffix)); 6472 break; 6473 default: 6474 return -1; 6475 } 6476 return 0; 6477 } 6478 6479 /* Record the prefixed XX3-Form instructions with primary opcode 59. The 6480 arguments are the first 32-bits of the instruction (insn_prefix), and the 6481 second 32-bits of the instruction (insn_suffix). Return 0 on success. */ 6482 6483 static int 6484 ppc_process_record_prefix_op59_XX3 (struct gdbarch *gdbarch, 6485 struct regcache *regcache, 6486 uint32_t insn_prefix, uint32_t insn_suffix) 6487 { 6488 int opcode = PPC_FIELD (insn_suffix, 21, 8); 6489 int type = PPC_FIELD (insn_prefix, 6, 2); 6490 int ST4 = PPC_FIELD (insn_prefix, 8, 4); 6491 int at = PPC_FIELD (insn_suffix, 6, 3); 6492 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6493 6494 /* Note, the mnemonics for the pmxvf16ger*, pmxvf32ger*,pmxvf64ger*, 6495 pmxvi4ger8*, pmxvi8ger4* pmxvi16ger2* instructions were officially 6496 changed to pmdmxbf16ger*, pmdmxvf32ger*, pmdmxvf64ger*, pmdmxvi4ger8*, 6497 pmdmxvi8ger4*, pmdmxvi16ger* respectively. The old mnemonics are still 6498 supported by the assembler as extended mnemonics. The disassembler 6499 generates the new mnemonics. */ 6500 if (type == 3) 6501 { 6502 if (ST4 == 9) 6503 switch (opcode) 6504 { 6505 case 35: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER 6506 MMIRR, pmdmxvi4ger8 (pmxvi4ger8) */ 6507 case 34: /* Prefixed Masked VSX Vector 4-bit Signed Integer GER 6508 MMIRR, pmdmxvi4ger8pp (pmxvi4ger8pp) */ 6509 6510 case 99: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned 6511 Integer GER with Saturate Positive multiply, 6512 Positive accumulate, xvi8ger4spp */ 6513 6514 case 3: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned 6515 Integer GER MMIRR, pmdmxvi8ger4 (pmxvi8ger4) */ 6516 case 2: /* Prefixed Masked VSX Vector 8-bit Signed/Unsigned 6517 Integer GER Positive multiply, Positive accumulate 6518 MMIRR, pmdmxvi8ger4pp (pmxvi8ger4pp) */ 6519 6520 case 75: /* Prefixed Masked VSX Vector 16-bit Signed Integer 6521 GER MMIRR, pmdmxvi16ger2 (pmxvi16ger2) */ 6522 case 107: /* Prefixed Masked VSX Vector 16-bit Signed Integer 6523 GER Positive multiply, Positive accumulate, 6524 pmdmxvi16ger2pp (pmxvi16ger2pp) */ 6525 6526 case 43: /* Prefixed Masked VSX Vector 16-bit Signed Integer 6527 GER with Saturation MMIRR, pmdmxvi16ger2s 6528 (pmxvi16ger2s) */ 6529 case 42: /* Prefixed Masked VSX Vector 16-bit Signed Integer 6530 GER with Saturation Positive multiply, Positive 6531 accumulate MMIRR, pmdmxvi16ger2spp (pmxvi16ger2spp) 6532 */ 6533 ppc_record_ACC_fpscr (regcache, tdep, at, false); 6534 return 0; 6535 6536 case 19: /* Prefixed Masked VSX Vector 16-bit Floating-Point 6537 GER MMIRR, pmdmxvf16ger2 (pmxvf16ger2) */ 6538 case 18: /* Prefixed Masked VSX Vector 16-bit Floating-Point 6539 GER Positive multiply, Positive accumulate MMIRR, 6540 pmdmxvf16ger2pp (pmxvf16ger2pp) */ 6541 case 146: /* Prefixed Masked VSX Vector 16-bit Floating-Point 6542 GER Positive multiply, Negative accumulate MMIRR, 6543 pmdmxvf16ger2pn (pmxvf16ger2pn) */ 6544 case 82: /* Prefixed Masked VSX Vector 16-bit Floating-Point 6545 GER Negative multiply, Positive accumulate MMIRR, 6546 pmdmxvf16ger2np (pmxvf16ger2np) */ 6547 case 210: /* Prefixed Masked VSX Vector 16-bit Floating-Point 6548 GER Negative multiply, Negative accumulate MMIRR, 6549 pmdmxvf16ger2nn (pmxvf16ger2nn) */ 6550 6551 case 27: /* Prefixed Masked VSX Vector 32-bit Floating-Point 6552 GER MMIRR, pmdmxvf32ger (pmxvf32ger) */ 6553 case 26: /* Prefixed Masked VSX Vector 32-bit Floating-Point 6554 GER Positive multiply, Positive accumulate MMIRR, 6555 pmdmxvf32gerpp (pmxvf32gerpp) */ 6556 case 154: /* Prefixed Masked VSX Vector 32-bit Floating-Point 6557 GER Positive multiply, Negative accumulate MMIRR, 6558 pmdmxvf32gerpn (pmxvf32gerpn) */ 6559 case 90: /* Prefixed Masked VSX Vector 32-bit Floating-Point 6560 GER Negative multiply, Positive accumulate MMIRR, 6561 pmdmxvf32gernp (pmxvf32gernp )*/ 6562 case 218: /* Prefixed Masked VSX Vector 32-bit Floating-Point 6563 GER Negative multiply, Negative accumulate MMIRR, 6564 pmdmxvf32gernn (pmxvf32gernn) */ 6565 6566 case 59: /* Prefixed Masked VSX Vector 64-bit Floating-Point 6567 GER MMIRR, pmdmxvf64ger (pmxvf64ger) */ 6568 case 58: /* Floating-Point GER Positive multiply, Positive 6569 accumulate MMIRR, pmdmxvf64gerpp (pmxvf64gerpp) */ 6570 case 186: /* Prefixed Masked VSX Vector 64-bit Floating-Point 6571 GER Positive multiply, Negative accumulate MMIRR, 6572 pmdmxvf64gerpn (pmxvf64gerpn) */ 6573 case 122: /* Prefixed Masked VSX Vector 64-bit Floating-Point 6574 GER Negative multiply, Positive accumulate MMIRR, 6575 pmdmxvf64gernp (pmxvf64gernp) */ 6576 case 250: /* Prefixed Masked VSX Vector 64-bit Floating-Point 6577 GER Negative multiply, Negative accumulate MMIRR, 6578 pmdmxvf64gernn (pmxvf64gernn) */ 6579 6580 case 51: /* Prefixed Masked VSX Vector bfloat16 GER MMIRR, 6581 pmdmxvbf16ger2 (pmxvbf16ger2) */ 6582 case 50: /* Prefixed Masked VSX Vector bfloat16 GER Positive 6583 multiply, Positive accumulate MMIRR, 6584 pmdmxvbf16ger2pp (pmxvbf16ger2pp) */ 6585 case 178: /* Prefixed Masked VSX Vector bfloat16 GER Positive 6586 multiply, Negative accumulate MMIRR, 6587 pmdmxvbf16ger2pn (pmxvbf16ger2pn) */ 6588 case 114: /* Prefixed Masked VSX Vector bfloat16 GER Negative 6589 multiply, Positive accumulate MMIRR, 6590 pmdmxvbf16ger2np (pmxvbf16ger2np) */ 6591 case 242: /* Prefixed Masked VSX Vector bfloat16 GER Negative 6592 multiply, Negative accumulate MMIRR, 6593 pmdmxvbf16ger2nn (pmxvbf16ger2nn) */ 6594 ppc_record_ACC_fpscr (regcache, tdep, at, true); 6595 return 0; 6596 } 6597 } 6598 else 6599 return -1; 6600 6601 return 0; 6602 } 6603 6604 /* Record the prefixed store instructions. The arguments are the instruction 6605 address, the first 32-bits of the instruction(insn_prefix) and the following 6606 32-bits of the instruction (insn_suffix). Return 0 on success. */ 6607 6608 static int 6609 ppc_process_record_prefix_store (struct gdbarch *gdbarch, 6610 struct regcache *regcache, 6611 CORE_ADDR addr, uint32_t insn_prefix, 6612 uint32_t insn_suffix) 6613 { 6614 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6615 ULONGEST iaddr = 0; 6616 int size; 6617 int R = PPC_BIT (insn_prefix, 11); 6618 int op6 = PPC_OP6 (insn_suffix); 6619 6620 if (R == 0) 6621 { 6622 if (PPC_RA (insn_suffix) != 0) 6623 regcache_raw_read_unsigned (regcache, tdep->ppc_gp0_regnum 6624 + PPC_RA (insn_suffix), &iaddr); 6625 } 6626 else 6627 { 6628 iaddr = addr; /* PC relative */ 6629 } 6630 6631 switch (op6) 6632 { 6633 case 38: 6634 size = 1; /* store byte, pstb */ 6635 break; 6636 case 44: 6637 size = 2; /* store halfword, psth */ 6638 break; 6639 case 36: 6640 case 52: 6641 size = 4; /* store word, pstw, pstfs */ 6642 break; 6643 case 54: 6644 case 61: 6645 size = 8; /* store double word, pstd, pstfd */ 6646 break; 6647 case 60: 6648 size = 16; /* store quadword, pstq */ 6649 break; 6650 default: return -1; 6651 } 6652 6653 iaddr += P_PPC_D (insn_prefix, insn_suffix); 6654 record_full_arch_list_add_mem (iaddr, size); 6655 return 0; 6656 } 6657 6658 /* Record the prefixed instructions with primary op code 32. The arguments 6659 are the first 32-bits of the instruction (insn_prefix) and the following 6660 32-bits of the instruction (insn_suffix). Return 0 on success. */ 6661 6662 static int 6663 ppc_process_record_prefix_op32 (struct gdbarch *gdbarch, 6664 struct regcache *regcache, 6665 uint32_t insn_prefix, uint32_t insn_suffix) 6666 { 6667 int type = PPC_FIELD (insn_prefix, 6, 2); 6668 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6669 int ST4 = PPC_FIELD (insn_prefix, 8, 4); 6670 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6671 6672 if (type == 1) 6673 { 6674 if (ST4 == 0) 6675 { 6676 switch (PPC_FIELD (insn_suffix, 11, 3)) 6677 { 6678 case 0: /* VSX Vector Splat Immediate Word 8RR, xxsplti32dx */ 6679 ppc_record_vsr (regcache, tdep, P_PPC_XT15 (insn_suffix)); 6680 return 0; 6681 } 6682 6683 switch (PPC_FIELD (insn_suffix, 11, 4)) 6684 { 6685 case 2: /* VSX Vector Splat Immediate Double-Precision 6686 8RR, xxspltidp */ 6687 case 3: /* VSX Vector Splat Immediate Word 8RR, xxspltiw */ 6688 ppc_record_vsr (regcache, tdep, P_PPC_XT15 (insn_suffix)); 6689 return 0; 6690 default: 6691 return -1; 6692 } 6693 } 6694 else 6695 return -1; 6696 6697 } 6698 else if (type == 2) 6699 { 6700 if (ST1 == 0) /* Prefixed Load Word and Zero, plwz */ 6701 record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum 6702 + PPC_RT (insn_suffix)); 6703 else 6704 return -1; 6705 6706 } 6707 else 6708 return -1; 6709 6710 return 0; 6711 } 6712 6713 /* Record the prefixed instructions with primary op code 33. The arguments 6714 are the first 32-bits of the instruction(insn_prefix) and the following 6715 32-bits of the instruction (insn_suffix). Return 0 on success. */ 6716 6717 static int 6718 ppc_process_record_prefix_op33 (struct gdbarch *gdbarch, 6719 struct regcache *regcache, 6720 uint32_t insn_prefix, uint32_t insn_suffix) 6721 { 6722 int type = PPC_FIELD (insn_prefix, 6, 2); 6723 int ST4 = PPC_FIELD (insn_prefix, 8, 4); 6724 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6725 6726 if (type == 1) 6727 { 6728 if (ST4 == 0) 6729 switch (PPC_FIELD (insn_suffix, 26, 2)) 6730 { 6731 case 0: /* VSX Vector Blend Variable Byte 8RR, xxblendvb */ 6732 case 1: /* VSX Vector Blend Variable Halfword, xxblendvh */ 6733 case 2: /* VSX Vector Blend Variable Word, xxblendvw */ 6734 case 3: /* VSX Vector Blend Variable Doubleword, xxblendvd */ 6735 ppc_record_vsr (regcache, tdep, PPC_XT (insn_suffix)); 6736 break; 6737 default: 6738 return -1; 6739 } 6740 else 6741 return -1; 6742 6743 } 6744 else 6745 return -1; 6746 6747 return 0; 6748 } 6749 6750 /* Record the prefixed instructions with primary op code 34. The arguments 6751 are the first 32-bits of the instruction(insn_prefix) and the following 6752 32-bits of the instruction (insn_suffix). Return 0 on success. */ 6753 6754 static int 6755 ppc_process_record_prefix_op34 (struct gdbarch *gdbarch, 6756 struct regcache *regcache, 6757 uint32_t insn_prefix, uint32_t insn_suffix) 6758 { 6759 int type = PPC_FIELD (insn_prefix, 6, 2); 6760 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6761 int ST4 = PPC_FIELD (insn_prefix, 8, 4); 6762 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6763 6764 if (type == 1) 6765 { 6766 if (ST4 == 0) 6767 switch (PPC_FIELD (insn_suffix, 26, 2)) 6768 { 6769 case 0: /* VSX Vector Permute Extended 8RR, xxpermx */ 6770 case 1: /* VSX Vector Evaluate 8RR, xxeval */ 6771 ppc_record_vsr (regcache, tdep, P_PPC_XT (insn_suffix)); 6772 break; 6773 default: 6774 return -1; 6775 } 6776 else 6777 return -1; 6778 6779 } 6780 else if (type == 2) 6781 { 6782 if (ST1 == 0) /* Prefixed Load Word and Zero, plbz */ 6783 record_full_arch_list_add_reg (regcache, 6784 tdep->ppc_gp0_regnum 6785 + PPC_RT (insn_suffix)); 6786 else 6787 return -1; 6788 6789 } 6790 else 6791 return -1; 6792 6793 return 0; 6794 } 6795 6796 /* Record the prefixed VSX store, form DS, instructions. The arguments are the 6797 instruction address (addr), the first 32-bits of the instruction 6798 (insn_prefix) followed by the 32-bit instruction suffix (insn_suffix). 6799 Return 0 on success. */ 6800 6801 static int 6802 ppc_process_record_prefix_store_vsx_ds_form (struct gdbarch *gdbarch, 6803 struct regcache *regcache, 6804 CORE_ADDR addr, 6805 uint32_t insn_prefix, 6806 uint32_t insn_suffix) 6807 { 6808 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6809 ULONGEST ea = 0; 6810 int size; 6811 int R = PPC_BIT (insn_prefix, 11); 6812 int type = PPC_FIELD (insn_prefix, 6, 2); 6813 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6814 6815 if ((type == 0) && (ST1 == 0)) 6816 { 6817 if (R == 0) 6818 { 6819 if (PPC_RA (insn_suffix) != 0) 6820 regcache_raw_read_unsigned (regcache, 6821 tdep->ppc_gp0_regnum 6822 + PPC_RA (insn_suffix), 6823 &ea); 6824 } 6825 else 6826 { 6827 ea = addr; /* PC relative */ 6828 } 6829 6830 ea += P_PPC_D (insn_prefix, insn_suffix); 6831 switch (PPC_FIELD (insn_suffix, 0, 6)) 6832 { 6833 case 46: /* Prefixed Store VSX Scalar Doubleword, pstxsd */ 6834 size = 8; 6835 break; 6836 case 47: /* Prefixed,Store VSX Scalar Single-Precision, pstxssp */ 6837 size = 4; 6838 break; 6839 default: 6840 return -1; 6841 } 6842 record_full_arch_list_add_mem (ea, size); 6843 return 0; 6844 } 6845 else 6846 return -1; 6847 } 6848 6849 /* Record the prefixed VSX, form D, instructions. The arguments are the 6850 instruction address for PC-relative addresss (addr), the first 32-bits of 6851 the instruction (insn_prefix) and the following 32-bits of the instruction 6852 (insn_suffix). Return 0 on success. */ 6853 6854 static int 6855 ppc_process_record_prefix_vsx_d_form (struct gdbarch *gdbarch, 6856 struct regcache *regcache, 6857 CORE_ADDR addr, 6858 uint32_t insn_prefix, 6859 uint32_t insn_suffix) 6860 { 6861 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6862 ULONGEST ea = 0; 6863 int size; 6864 int R = PPC_BIT (insn_prefix, 11); 6865 int type = PPC_FIELD (insn_prefix, 6, 2); 6866 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6867 6868 if ((type == 0) && (ST1 == 0)) 6869 { 6870 switch (PPC_FIELD (insn_suffix, 0, 5)) 6871 { 6872 case 25: /* Prefixed Load VSX Vector, plxv */ 6873 ppc_record_vsr (regcache, tdep, P_PPC_XT5 (insn_prefix)); 6874 return 0; 6875 case 27: /* Prefixed Store VSX Vector 8LS, pstxv */ 6876 { 6877 size = 16; 6878 if (R == 0) 6879 { 6880 if (PPC_RA (insn_suffix) != 0) 6881 regcache_raw_read_unsigned (regcache, 6882 tdep->ppc_gp0_regnum 6883 + PPC_RA (insn_suffix), 6884 &ea); 6885 } 6886 else 6887 { 6888 ea = addr; /* PC relative */ 6889 } 6890 6891 ea += P_PPC_D (insn_prefix, insn_suffix); 6892 record_full_arch_list_add_mem (ea, size); 6893 return 0; 6894 } 6895 } 6896 return -1; 6897 } 6898 else 6899 return -1; 6900 } 6901 6902 /* Parse the current instruction and record the values of the registers and 6903 memory that will be changed in current instruction to "record_arch_list". 6904 Return -1 if something wrong. */ 6905 6906 /* This handles the recording of the various prefix instructions. It takes 6907 the instruction address, the first 32-bits of the instruction (insn_prefix) 6908 and the following 32-bits of the instruction (insn_suffix). Return 0 on 6909 success. */ 6910 6911 static int 6912 ppc_process_prefix_instruction (int insn_prefix, int insn_suffix, 6913 CORE_ADDR addr, struct gdbarch *gdbarch, 6914 struct regcache *regcache) 6915 { 6916 int type = PPC_FIELD (insn_prefix, 6, 2); 6917 int ST1 = PPC_FIELD (insn_prefix, 8, 1); 6918 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 6919 int op6; 6920 6921 /* D-form has uses a 5-bit opcode in the instruction suffix */ 6922 if (ppc_process_record_prefix_vsx_d_form ( gdbarch, regcache, addr, 6923 insn_prefix, insn_suffix) == 0) 6924 goto SUCCESS; 6925 6926 op6 = PPC_OP6 (insn_suffix); /* 6-bit opcode in the instruction suffix */ 6927 6928 switch (op6) 6929 { 6930 case 14: /* Prefixed Add Immediate, paddi */ 6931 if ((type == 2) && (ST1 == 0)) 6932 record_full_arch_list_add_reg (regcache, 6933 tdep->ppc_gp0_regnum 6934 + PPC_RT (insn_suffix)); 6935 else 6936 goto UNKNOWN_PREFIX_OP; 6937 break; 6938 6939 case 32: 6940 if (ppc_process_record_prefix_op32 (gdbarch, regcache, 6941 insn_prefix, insn_suffix) != 0) 6942 goto UNKNOWN_PREFIX_OP; 6943 break; 6944 6945 case 33: 6946 if (ppc_process_record_prefix_op33 (gdbarch, regcache, 6947 insn_prefix, insn_suffix) != 0) 6948 goto UNKNOWN_PREFIX_OP; 6949 break; 6950 6951 case 34: /* Prefixed Load Byte and Zero, plbz */ 6952 if (ppc_process_record_prefix_op34 (gdbarch, regcache, 6953 insn_prefix, insn_suffix) != 0) 6954 goto UNKNOWN_PREFIX_OP; 6955 break; 6956 case 40: /* Prefixed Load Halfword and Zero, plhz */ 6957 if ((type == 2) && (ST1 == 0)) 6958 record_full_arch_list_add_reg (regcache, 6959 tdep->ppc_gp0_regnum 6960 + PPC_RT (insn_suffix)); 6961 else 6962 goto UNKNOWN_PREFIX_OP; 6963 break; 6964 6965 break; 6966 6967 case 36: /* Prefixed Store Word, pstw */ 6968 case 38: /* Prefixed Store Byte, pstb */ 6969 case 44: /* Prefixed Store Halfword, psth */ 6970 case 52: /* Prefixed Store Floating-Point Single, pstfs */ 6971 case 54: /* Prefixed Store Floating-Point Double, pstfd */ 6972 case 60: /* Prefixed Store Quadword, pstq */ 6973 case 61: /* Prefixed Store Doubleword, pstd */ 6974 if (ppc_process_record_prefix_store (gdbarch, regcache, addr, 6975 insn_prefix, insn_suffix) != 0) 6976 goto UNKNOWN_PREFIX_OP; 6977 break; 6978 6979 case 42: 6980 if (ppc_process_record_prefix_op42 (gdbarch, regcache, 6981 insn_prefix, insn_suffix) != 0) 6982 goto UNKNOWN_PREFIX_OP; 6983 break; 6984 6985 case 43: /* Prefixed Load VSX Scalar Single-Precision, plxssp */ 6986 if ((type == 0) && (ST1 == 0)) 6987 ppc_record_vsr (regcache, tdep, PPC_VRT (insn_suffix) + 32); 6988 else 6989 goto UNKNOWN_PREFIX_OP; 6990 break; 6991 6992 case 46: 6993 case 47: 6994 if (ppc_process_record_prefix_store_vsx_ds_form (gdbarch, regcache, addr, 6995 insn_prefix, insn_suffix) != 0) 6996 goto UNKNOWN_PREFIX_OP; 6997 break; 6998 6999 case 56: /* Prefixed Load Quadword, plq */ 7000 { 7001 if ((type == 0) && (ST1 == 0)) 7002 { 7003 int tmp; 7004 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn_suffix) & ~1); 7005 record_full_arch_list_add_reg (regcache, tmp); 7006 record_full_arch_list_add_reg (regcache, tmp + 1); 7007 } 7008 else 7009 goto UNKNOWN_PREFIX_OP; 7010 break; 7011 } 7012 7013 case 41: /* Prefixed Load Word Algebraic, plwa */ 7014 case 57: /* Prefixed Load Doubleword, pld */ 7015 if ((type == 0) && (ST1 == 0)) 7016 record_full_arch_list_add_reg (regcache, 7017 tdep->ppc_gp0_regnum 7018 + PPC_RT (insn_suffix)); 7019 else 7020 goto UNKNOWN_PREFIX_OP; 7021 break; 7022 7023 case 48: /* Prefixed Load Floating-Point Single, plfs */ 7024 case 50: /* Prefixed Load Floating-Point Double, plfd */ 7025 if ((type == 2) && (ST1 == 0)) 7026 record_full_arch_list_add_reg (regcache, 7027 tdep->ppc_fp0_regnum 7028 + PPC_FRT (insn_suffix)); 7029 else 7030 goto UNKNOWN_PREFIX_OP; 7031 break; 7032 7033 case 58: /* Prefixed Load VSX Vector Paired, plxvp */ 7034 if ((type == 0) && (ST1 == 0)) 7035 { 7036 ppc_record_vsr (regcache, tdep, PPC_XTp (insn_suffix)); 7037 ppc_record_vsr (regcache, tdep, PPC_XTp (insn_suffix) + 1); 7038 } 7039 else 7040 goto UNKNOWN_PREFIX_OP; 7041 break; 7042 7043 case 59: 7044 if (ppc_process_record_prefix_op59_XX3 (gdbarch, regcache, insn_prefix, 7045 insn_suffix) != 0) 7046 goto UNKNOWN_PREFIX_OP; 7047 break; 7048 7049 case 62: /* Prefixed Store VSX Vector Paired 8LS, pstxvp */ 7050 if ((type == 0) && (ST1 == 0)) 7051 { 7052 int R = PPC_BIT (insn_prefix, 11); 7053 CORE_ADDR ea = 0; 7054 7055 if (R == 0) 7056 { 7057 if (PPC_RA (insn_suffix) != 0) 7058 regcache_raw_read_unsigned (regcache, 7059 tdep->ppc_gp0_regnum 7060 + PPC_RA (insn_suffix), &ea); 7061 } 7062 else 7063 { 7064 ea = addr; /* PC relative */ 7065 } 7066 7067 ea += P_PPC_D (insn_prefix, insn_suffix) << 4; 7068 record_full_arch_list_add_mem (ea, 32); 7069 } 7070 else 7071 goto UNKNOWN_PREFIX_OP; 7072 break; 7073 7074 default: 7075 UNKNOWN_PREFIX_OP: 7076 gdb_printf (gdb_stdlog, 7077 "Warning: Don't know how to record prefix instruction " 7078 "%08x %08x at %s, %d.\n", 7079 insn_prefix, insn_suffix, paddress (gdbarch, addr), 7080 op6); 7081 return -1; 7082 } 7083 7084 SUCCESS: 7085 if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) 7086 return -1; 7087 7088 if (record_full_arch_list_add_end ()) 7089 return -1; 7090 return 0; 7091 } 7092 7093 int 7094 ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache, 7095 CORE_ADDR addr) 7096 { 7097 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 7098 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7099 uint32_t insn, insn_suffix; 7100 int op6, tmp, i; 7101 7102 insn = read_memory_unsigned_integer (addr, 4, byte_order); 7103 op6 = PPC_OP6 (insn); 7104 7105 switch (op6) 7106 { 7107 case 1: /* prefixed instruction */ 7108 { 7109 /* Get the lower 32-bits of the prefixed instruction. */ 7110 insn_suffix = read_memory_unsigned_integer (addr+4, 4, byte_order); 7111 return ppc_process_prefix_instruction (insn, insn_suffix, addr, 7112 gdbarch, regcache); 7113 } 7114 case 2: /* Trap Doubleword Immediate */ 7115 case 3: /* Trap Word Immediate */ 7116 /* Do nothing. */ 7117 break; 7118 7119 case 4: /* Vector Integer, Compare, Logical, Shift, etc. */ 7120 if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0) 7121 return -1; 7122 break; 7123 7124 case 6: /* Vector Load and Store */ 7125 if (ppc_process_record_op6 (gdbarch, regcache, addr, insn) != 0) 7126 return -1; 7127 break; 7128 7129 case 17: /* System call */ 7130 if (PPC_LEV (insn) != 0) 7131 goto UNKNOWN_OP; 7132 7133 if (tdep->ppc_syscall_record != NULL) 7134 { 7135 if (tdep->ppc_syscall_record (regcache) != 0) 7136 return -1; 7137 } 7138 else 7139 { 7140 gdb_printf (gdb_stderr, _("no syscall record support\n")); 7141 return -1; 7142 } 7143 break; 7144 7145 case 7: /* Multiply Low Immediate */ 7146 record_full_arch_list_add_reg (regcache, 7147 tdep->ppc_gp0_regnum + PPC_RT (insn)); 7148 break; 7149 7150 case 8: /* Subtract From Immediate Carrying */ 7151 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 7152 record_full_arch_list_add_reg (regcache, 7153 tdep->ppc_gp0_regnum + PPC_RT (insn)); 7154 break; 7155 7156 case 10: /* Compare Logical Immediate */ 7157 case 11: /* Compare Immediate */ 7158 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 7159 break; 7160 7161 case 13: /* Add Immediate Carrying and Record */ 7162 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 7163 /* FALL-THROUGH */ 7164 case 12: /* Add Immediate Carrying */ 7165 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum); 7166 /* FALL-THROUGH */ 7167 case 14: /* Add Immediate */ 7168 case 15: /* Add Immediate Shifted */ 7169 record_full_arch_list_add_reg (regcache, 7170 tdep->ppc_gp0_regnum + PPC_RT (insn)); 7171 break; 7172 7173 case 16: /* Branch Conditional */ 7174 if ((PPC_BO (insn) & 0x4) == 0) 7175 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum); 7176 /* FALL-THROUGH */ 7177 case 18: /* Branch */ 7178 if (PPC_LK (insn)) 7179 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum); 7180 break; 7181 7182 case 19: 7183 if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0) 7184 return -1; 7185 break; 7186 7187 case 20: /* Rotate Left Word Immediate then Mask Insert */ 7188 case 21: /* Rotate Left Word Immediate then AND with Mask */ 7189 case 23: /* Rotate Left Word then AND with Mask */ 7190 case 30: /* Rotate Left Doubleword Immediate then Clear Left */ 7191 /* Rotate Left Doubleword Immediate then Clear Right */ 7192 /* Rotate Left Doubleword Immediate then Clear */ 7193 /* Rotate Left Doubleword then Clear Left */ 7194 /* Rotate Left Doubleword then Clear Right */ 7195 /* Rotate Left Doubleword Immediate then Mask Insert */ 7196 if (PPC_RC (insn)) 7197 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 7198 record_full_arch_list_add_reg (regcache, 7199 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7200 break; 7201 7202 case 28: /* AND Immediate */ 7203 case 29: /* AND Immediate Shifted */ 7204 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum); 7205 /* FALL-THROUGH */ 7206 case 24: /* OR Immediate */ 7207 case 25: /* OR Immediate Shifted */ 7208 case 26: /* XOR Immediate */ 7209 case 27: /* XOR Immediate Shifted */ 7210 record_full_arch_list_add_reg (regcache, 7211 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7212 break; 7213 7214 case 31: 7215 if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0) 7216 return -1; 7217 break; 7218 7219 case 33: /* Load Word and Zero with Update */ 7220 case 35: /* Load Byte and Zero with Update */ 7221 case 41: /* Load Halfword and Zero with Update */ 7222 case 43: /* Load Halfword Algebraic with Update */ 7223 record_full_arch_list_add_reg (regcache, 7224 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7225 /* FALL-THROUGH */ 7226 case 32: /* Load Word and Zero */ 7227 case 34: /* Load Byte and Zero */ 7228 case 40: /* Load Halfword and Zero */ 7229 case 42: /* Load Halfword Algebraic */ 7230 record_full_arch_list_add_reg (regcache, 7231 tdep->ppc_gp0_regnum + PPC_RT (insn)); 7232 break; 7233 7234 case 46: /* Load Multiple Word */ 7235 for (i = PPC_RT (insn); i < 32; i++) 7236 record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i); 7237 break; 7238 7239 case 56: /* Load Quadword */ 7240 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1); 7241 record_full_arch_list_add_reg (regcache, tmp); 7242 record_full_arch_list_add_reg (regcache, tmp + 1); 7243 break; 7244 7245 case 49: /* Load Floating-Point Single with Update */ 7246 case 51: /* Load Floating-Point Double with Update */ 7247 record_full_arch_list_add_reg (regcache, 7248 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7249 /* FALL-THROUGH */ 7250 case 48: /* Load Floating-Point Single */ 7251 case 50: /* Load Floating-Point Double */ 7252 record_full_arch_list_add_reg (regcache, 7253 tdep->ppc_fp0_regnum + PPC_FRT (insn)); 7254 break; 7255 7256 case 47: /* Store Multiple Word */ 7257 { 7258 ULONGEST iaddr = 0; 7259 7260 if (PPC_RA (insn) != 0) 7261 regcache_raw_read_unsigned (regcache, 7262 tdep->ppc_gp0_regnum + PPC_RA (insn), 7263 &iaddr); 7264 7265 iaddr += PPC_D (insn); 7266 record_full_arch_list_add_mem (iaddr, 4 * (32 - PPC_RS (insn))); 7267 } 7268 break; 7269 7270 case 37: /* Store Word with Update */ 7271 case 39: /* Store Byte with Update */ 7272 case 45: /* Store Halfword with Update */ 7273 case 53: /* Store Floating-Point Single with Update */ 7274 case 55: /* Store Floating-Point Double with Update */ 7275 record_full_arch_list_add_reg (regcache, 7276 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7277 /* FALL-THROUGH */ 7278 case 36: /* Store Word */ 7279 case 38: /* Store Byte */ 7280 case 44: /* Store Halfword */ 7281 case 52: /* Store Floating-Point Single */ 7282 case 54: /* Store Floating-Point Double */ 7283 { 7284 ULONGEST iaddr = 0; 7285 int size = -1; 7286 7287 if (PPC_RA (insn) != 0) 7288 regcache_raw_read_unsigned (regcache, 7289 tdep->ppc_gp0_regnum + PPC_RA (insn), 7290 &iaddr); 7291 iaddr += PPC_D (insn); 7292 7293 if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53) 7294 size = 4; 7295 else if (op6 == 54 || op6 == 55) 7296 size = 8; 7297 else if (op6 == 44 || op6 == 45) 7298 size = 2; 7299 else if (op6 == 38 || op6 == 39) 7300 size = 1; 7301 else 7302 gdb_assert (0); 7303 7304 record_full_arch_list_add_mem (iaddr, size); 7305 } 7306 break; 7307 7308 case 57: 7309 switch (insn & 0x3) 7310 { 7311 case 0: /* Load Floating-Point Double Pair */ 7312 tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1); 7313 record_full_arch_list_add_reg (regcache, tmp); 7314 record_full_arch_list_add_reg (regcache, tmp + 1); 7315 break; 7316 case 2: /* Load VSX Scalar Doubleword */ 7317 case 3: /* Load VSX Scalar Single */ 7318 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32); 7319 break; 7320 default: 7321 goto UNKNOWN_OP; 7322 } 7323 break; 7324 7325 case 58: /* Load Doubleword */ 7326 /* Load Doubleword with Update */ 7327 /* Load Word Algebraic */ 7328 if (PPC_FIELD (insn, 30, 2) > 2) 7329 goto UNKNOWN_OP; 7330 7331 record_full_arch_list_add_reg (regcache, 7332 tdep->ppc_gp0_regnum + PPC_RT (insn)); 7333 if (PPC_BIT (insn, 31)) 7334 record_full_arch_list_add_reg (regcache, 7335 tdep->ppc_gp0_regnum + PPC_RA (insn)); 7336 break; 7337 7338 case 59: 7339 if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0) 7340 return -1; 7341 break; 7342 7343 case 60: 7344 if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0) 7345 return -1; 7346 break; 7347 7348 case 61: 7349 if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0) 7350 return -1; 7351 break; 7352 7353 case 62: /* Store Doubleword */ 7354 /* Store Doubleword with Update */ 7355 /* Store Quadword with Update */ 7356 { 7357 ULONGEST iaddr = 0; 7358 int size; 7359 int sub2 = PPC_FIELD (insn, 30, 2); 7360 7361 if (sub2 > 2) 7362 goto UNKNOWN_OP; 7363 7364 if (PPC_RA (insn) != 0) 7365 regcache_raw_read_unsigned (regcache, 7366 tdep->ppc_gp0_regnum + PPC_RA (insn), 7367 &iaddr); 7368 7369 size = (sub2 == 2) ? 16 : 8; 7370 7371 iaddr += PPC_DS (insn) << 2; 7372 record_full_arch_list_add_mem (iaddr, size); 7373 7374 if (op6 == 62 && sub2 == 1) 7375 record_full_arch_list_add_reg (regcache, 7376 tdep->ppc_gp0_regnum + 7377 PPC_RA (insn)); 7378 7379 break; 7380 } 7381 7382 case 63: 7383 if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0) 7384 return -1; 7385 break; 7386 7387 default: 7388 UNKNOWN_OP: 7389 gdb_printf (gdb_stdlog, "Warning: Don't know how to record %08x " 7390 "at %s, %d.\n", insn, paddress (gdbarch, addr), op6); 7391 return -1; 7392 } 7393 7394 if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM)) 7395 return -1; 7396 if (record_full_arch_list_add_end ()) 7397 return -1; 7398 return 0; 7399 } 7400 7401 /* Used for matching tw, twi, td and tdi instructions for POWER. */ 7402 7403 static constexpr uint32_t TX_INSN_MASK = 0xFC0007FF; 7404 static constexpr uint32_t TW_INSN = 0x7C000008; 7405 static constexpr uint32_t TD_INSN = 0x7C000088; 7406 7407 static constexpr uint32_t TXI_INSN_MASK = 0xFC000000; 7408 static constexpr uint32_t TWI_INSN = 0x0C000000; 7409 static constexpr uint32_t TDI_INSN = 0x08000000; 7410 7411 static inline bool 7412 is_tw_insn (uint32_t insn) 7413 { 7414 return (insn & TX_INSN_MASK) == TW_INSN; 7415 } 7416 7417 static inline bool 7418 is_twi_insn (uint32_t insn) 7419 { 7420 return (insn & TXI_INSN_MASK) == TWI_INSN; 7421 } 7422 7423 static inline bool 7424 is_td_insn (uint32_t insn) 7425 { 7426 return (insn & TX_INSN_MASK) == TD_INSN; 7427 } 7428 7429 static inline bool 7430 is_tdi_insn (uint32_t insn) 7431 { 7432 return (insn & TXI_INSN_MASK) == TDI_INSN; 7433 } 7434 7435 /* Implementation of gdbarch_program_breakpoint_here_p for POWER. */ 7436 7437 static bool 7438 rs6000_program_breakpoint_here_p (gdbarch *gdbarch, CORE_ADDR address) 7439 { 7440 gdb_byte target_mem[PPC_INSN_SIZE]; 7441 7442 /* Enable the automatic memory restoration from breakpoints while 7443 we read the memory. Otherwise we may find temporary breakpoints, ones 7444 inserted by GDB, and flag them as permanent breakpoints. */ 7445 scoped_restore restore_memory 7446 = make_scoped_restore_show_memory_breakpoints (0); 7447 7448 if (target_read_memory (address, target_mem, PPC_INSN_SIZE) == 0) 7449 { 7450 uint32_t insn = (uint32_t) extract_unsigned_integer 7451 (target_mem, PPC_INSN_SIZE, gdbarch_byte_order_for_code (gdbarch)); 7452 7453 /* Check if INSN is a TW, TWI, TD or TDI instruction. There 7454 are multiple choices of such instructions with different registers 7455 and / or immediate values but they all cause a break. */ 7456 if (is_tw_insn (insn) || is_twi_insn (insn) || is_td_insn (insn) 7457 || is_tdi_insn (insn)) 7458 return true; 7459 } 7460 7461 return false; 7462 } 7463 7464 /* Initialize the current architecture based on INFO. If possible, re-use an 7465 architecture from ARCHES, which is a list of architectures already created 7466 during this debugging session. 7467 7468 Called e.g. at program startup, when reading a core file, and when reading 7469 a binary file. */ 7470 7471 static struct gdbarch * 7472 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 7473 { 7474 struct gdbarch *gdbarch; 7475 int wordsize, from_xcoff_exec, from_elf_exec; 7476 enum bfd_architecture arch; 7477 unsigned long mach; 7478 bfd abfd; 7479 enum auto_boolean soft_float_flag = powerpc_soft_float_global; 7480 int soft_float; 7481 enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO; 7482 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global; 7483 enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO; 7484 int have_fpu = 0, have_spe = 0, have_mq = 0, have_altivec = 0; 7485 int have_dfp = 0, have_vsx = 0, have_ppr = 0, have_dscr = 0; 7486 int have_tar = 0, have_ebb = 0, have_pmu = 0, have_htm_spr = 0; 7487 int have_htm_core = 0, have_htm_fpu = 0, have_htm_altivec = 0; 7488 int have_htm_vsx = 0, have_htm_ppr = 0, have_htm_dscr = 0; 7489 int have_htm_tar = 0; 7490 int tdesc_wordsize = -1; 7491 const struct target_desc *tdesc = info.target_desc; 7492 tdesc_arch_data_up tdesc_data; 7493 int num_pseudoregs = 0; 7494 int cur_reg; 7495 7496 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 7497 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 7498 7499 from_elf_exec = info.abfd && info.abfd->format == bfd_object && 7500 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 7501 7502 /* Check word size. If INFO is from a binary file, infer it from 7503 that, else choose a likely default. */ 7504 if (from_xcoff_exec) 7505 { 7506 if (bfd_xcoff_is_xcoff64 (info.abfd)) 7507 wordsize = 8; 7508 else 7509 wordsize = 4; 7510 } 7511 else if (from_elf_exec) 7512 { 7513 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 7514 wordsize = 8; 7515 else 7516 wordsize = 4; 7517 } 7518 else if (tdesc_has_registers (tdesc)) 7519 wordsize = -1; 7520 else 7521 { 7522 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 7523 wordsize = (info.bfd_arch_info->bits_per_word 7524 / info.bfd_arch_info->bits_per_byte); 7525 else 7526 wordsize = 4; 7527 } 7528 7529 /* Get the architecture and machine from the BFD. */ 7530 arch = info.bfd_arch_info->arch; 7531 mach = info.bfd_arch_info->mach; 7532 7533 /* For e500 executables, the apuinfo section is of help here. Such 7534 section contains the identifier and revision number of each 7535 Application-specific Processing Unit that is present on the 7536 chip. The content of the section is determined by the assembler 7537 which looks at each instruction and determines which unit (and 7538 which version of it) can execute it. Grovel through the section 7539 looking for relevant e500 APUs. */ 7540 7541 if (bfd_uses_spe_extensions (info.abfd)) 7542 { 7543 arch = info.bfd_arch_info->arch; 7544 mach = bfd_mach_ppc_e500; 7545 bfd_default_set_arch_mach (&abfd, arch, mach); 7546 info.bfd_arch_info = bfd_get_arch_info (&abfd); 7547 } 7548 7549 /* Find a default target description which describes our register 7550 layout, if we do not already have one. */ 7551 if (! tdesc_has_registers (tdesc)) 7552 { 7553 const struct ppc_variant *v; 7554 7555 /* Choose variant. */ 7556 v = find_variant_by_arch (arch, mach); 7557 if (!v) 7558 return NULL; 7559 7560 tdesc = *v->tdesc; 7561 } 7562 7563 gdb_assert (tdesc_has_registers (tdesc)); 7564 7565 /* Check any target description for validity. */ 7566 if (tdesc_has_registers (tdesc)) 7567 { 7568 static const char *const gprs[] = { 7569 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7570 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7571 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7572 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7573 }; 7574 const struct tdesc_feature *feature; 7575 int i, valid_p; 7576 static const char *const msr_names[] = { "msr", "ps" }; 7577 static const char *const cr_names[] = { "cr", "cnd" }; 7578 static const char *const ctr_names[] = { "ctr", "cnt" }; 7579 7580 feature = tdesc_find_feature (tdesc, 7581 "org.gnu.gdb.power.core"); 7582 if (feature == NULL) 7583 return NULL; 7584 7585 tdesc_data = tdesc_data_alloc (); 7586 7587 valid_p = 1; 7588 for (i = 0; i < ppc_num_gprs; i++) 7589 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7590 i, gprs[i]); 7591 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7592 PPC_PC_REGNUM, "pc"); 7593 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7594 PPC_LR_REGNUM, "lr"); 7595 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7596 PPC_XER_REGNUM, "xer"); 7597 7598 /* Allow alternate names for these registers, to accomodate GDB's 7599 historic naming. */ 7600 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), 7601 PPC_MSR_REGNUM, msr_names); 7602 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), 7603 PPC_CR_REGNUM, cr_names); 7604 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data.get (), 7605 PPC_CTR_REGNUM, ctr_names); 7606 7607 if (!valid_p) 7608 return NULL; 7609 7610 have_mq = tdesc_numbered_register (feature, tdesc_data.get (), 7611 PPC_MQ_REGNUM, "mq"); 7612 7613 tdesc_wordsize = tdesc_register_bitsize (feature, "pc") / 8; 7614 if (wordsize == -1) 7615 wordsize = tdesc_wordsize; 7616 7617 feature = tdesc_find_feature (tdesc, 7618 "org.gnu.gdb.power.fpu"); 7619 if (feature != NULL) 7620 { 7621 static const char *const fprs[] = { 7622 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 7623 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 7624 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 7625 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" 7626 }; 7627 valid_p = 1; 7628 for (i = 0; i < ppc_num_fprs; i++) 7629 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7630 PPC_F0_REGNUM + i, fprs[i]); 7631 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7632 PPC_FPSCR_REGNUM, "fpscr"); 7633 7634 if (!valid_p) 7635 return NULL; 7636 have_fpu = 1; 7637 7638 /* The fpscr register was expanded in isa 2.05 to 64 bits 7639 along with the addition of the decimal floating point 7640 facility. */ 7641 if (tdesc_register_bitsize (feature, "fpscr") > 32) 7642 have_dfp = 1; 7643 } 7644 else 7645 have_fpu = 0; 7646 7647 feature = tdesc_find_feature (tdesc, 7648 "org.gnu.gdb.power.altivec"); 7649 if (feature != NULL) 7650 { 7651 static const char *const vector_regs[] = { 7652 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7", 7653 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15", 7654 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23", 7655 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31" 7656 }; 7657 7658 valid_p = 1; 7659 for (i = 0; i < ppc_num_gprs; i++) 7660 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7661 PPC_VR0_REGNUM + i, 7662 vector_regs[i]); 7663 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7664 PPC_VSCR_REGNUM, "vscr"); 7665 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7666 PPC_VRSAVE_REGNUM, "vrsave"); 7667 7668 if (have_spe || !valid_p) 7669 return NULL; 7670 have_altivec = 1; 7671 } 7672 else 7673 have_altivec = 0; 7674 7675 /* Check for POWER7 VSX registers support. */ 7676 feature = tdesc_find_feature (tdesc, 7677 "org.gnu.gdb.power.vsx"); 7678 7679 if (feature != NULL) 7680 { 7681 static const char *const vsx_regs[] = { 7682 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h", 7683 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h", 7684 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h", 7685 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h", 7686 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h", 7687 "vs30h", "vs31h" 7688 }; 7689 7690 valid_p = 1; 7691 7692 for (i = 0; i < ppc_num_vshrs; i++) 7693 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7694 PPC_VSR0_UPPER_REGNUM + i, 7695 vsx_regs[i]); 7696 7697 if (!valid_p || !have_fpu || !have_altivec) 7698 return NULL; 7699 7700 have_vsx = 1; 7701 } 7702 else 7703 have_vsx = 0; 7704 7705 /* On machines supporting the SPE APU, the general-purpose registers 7706 are 64 bits long. There are SIMD vector instructions to treat them 7707 as pairs of floats, but the rest of the instruction set treats them 7708 as 32-bit registers, and only operates on their lower halves. 7709 7710 In the GDB regcache, we treat their high and low halves as separate 7711 registers. The low halves we present as the general-purpose 7712 registers, and then we have pseudo-registers that stitch together 7713 the upper and lower halves and present them as pseudo-registers. 7714 7715 Thus, the target description is expected to supply the upper 7716 halves separately. */ 7717 7718 feature = tdesc_find_feature (tdesc, 7719 "org.gnu.gdb.power.spe"); 7720 if (feature != NULL) 7721 { 7722 static const char *const upper_spe[] = { 7723 "ev0h", "ev1h", "ev2h", "ev3h", 7724 "ev4h", "ev5h", "ev6h", "ev7h", 7725 "ev8h", "ev9h", "ev10h", "ev11h", 7726 "ev12h", "ev13h", "ev14h", "ev15h", 7727 "ev16h", "ev17h", "ev18h", "ev19h", 7728 "ev20h", "ev21h", "ev22h", "ev23h", 7729 "ev24h", "ev25h", "ev26h", "ev27h", 7730 "ev28h", "ev29h", "ev30h", "ev31h" 7731 }; 7732 7733 valid_p = 1; 7734 for (i = 0; i < ppc_num_gprs; i++) 7735 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7736 PPC_SPE_UPPER_GP0_REGNUM + i, 7737 upper_spe[i]); 7738 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7739 PPC_SPE_ACC_REGNUM, "acc"); 7740 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7741 PPC_SPE_FSCR_REGNUM, "spefscr"); 7742 7743 if (have_mq || have_fpu || !valid_p) 7744 return NULL; 7745 have_spe = 1; 7746 } 7747 else 7748 have_spe = 0; 7749 7750 /* Program Priority Register. */ 7751 feature = tdesc_find_feature (tdesc, 7752 "org.gnu.gdb.power.ppr"); 7753 if (feature != NULL) 7754 { 7755 valid_p = 1; 7756 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7757 PPC_PPR_REGNUM, "ppr"); 7758 7759 if (!valid_p) 7760 return NULL; 7761 have_ppr = 1; 7762 } 7763 else 7764 have_ppr = 0; 7765 7766 /* Data Stream Control Register. */ 7767 feature = tdesc_find_feature (tdesc, 7768 "org.gnu.gdb.power.dscr"); 7769 if (feature != NULL) 7770 { 7771 valid_p = 1; 7772 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7773 PPC_DSCR_REGNUM, "dscr"); 7774 7775 if (!valid_p) 7776 return NULL; 7777 have_dscr = 1; 7778 } 7779 else 7780 have_dscr = 0; 7781 7782 /* Target Address Register. */ 7783 feature = tdesc_find_feature (tdesc, 7784 "org.gnu.gdb.power.tar"); 7785 if (feature != NULL) 7786 { 7787 valid_p = 1; 7788 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7789 PPC_TAR_REGNUM, "tar"); 7790 7791 if (!valid_p) 7792 return NULL; 7793 have_tar = 1; 7794 } 7795 else 7796 have_tar = 0; 7797 7798 /* Event-based Branching Registers. */ 7799 feature = tdesc_find_feature (tdesc, 7800 "org.gnu.gdb.power.ebb"); 7801 if (feature != NULL) 7802 { 7803 static const char *const ebb_regs[] = { 7804 "bescr", "ebbhr", "ebbrr" 7805 }; 7806 7807 valid_p = 1; 7808 for (i = 0; i < ARRAY_SIZE (ebb_regs); i++) 7809 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7810 PPC_BESCR_REGNUM + i, 7811 ebb_regs[i]); 7812 if (!valid_p) 7813 return NULL; 7814 have_ebb = 1; 7815 } 7816 else 7817 have_ebb = 0; 7818 7819 /* Subset of the ISA 2.07 Performance Monitor Registers provided 7820 by Linux. */ 7821 feature = tdesc_find_feature (tdesc, 7822 "org.gnu.gdb.power.linux.pmu"); 7823 if (feature != NULL) 7824 { 7825 valid_p = 1; 7826 7827 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7828 PPC_MMCR0_REGNUM, 7829 "mmcr0"); 7830 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7831 PPC_MMCR2_REGNUM, 7832 "mmcr2"); 7833 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7834 PPC_SIAR_REGNUM, 7835 "siar"); 7836 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7837 PPC_SDAR_REGNUM, 7838 "sdar"); 7839 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7840 PPC_SIER_REGNUM, 7841 "sier"); 7842 7843 if (!valid_p) 7844 return NULL; 7845 have_pmu = 1; 7846 } 7847 else 7848 have_pmu = 0; 7849 7850 /* Hardware Transactional Memory Registers. */ 7851 feature = tdesc_find_feature (tdesc, 7852 "org.gnu.gdb.power.htm.spr"); 7853 if (feature != NULL) 7854 { 7855 static const char *const tm_spr_regs[] = { 7856 "tfhar", "texasr", "tfiar" 7857 }; 7858 7859 valid_p = 1; 7860 for (i = 0; i < ARRAY_SIZE (tm_spr_regs); i++) 7861 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7862 PPC_TFHAR_REGNUM + i, 7863 tm_spr_regs[i]); 7864 if (!valid_p) 7865 return NULL; 7866 7867 have_htm_spr = 1; 7868 } 7869 else 7870 have_htm_spr = 0; 7871 7872 feature = tdesc_find_feature (tdesc, 7873 "org.gnu.gdb.power.htm.core"); 7874 if (feature != NULL) 7875 { 7876 static const char *const cgprs[] = { 7877 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 7878 "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", 7879 "cr15", "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", 7880 "cr22", "cr23", "cr24", "cr25", "cr26", "cr27", "cr28", 7881 "cr29", "cr30", "cr31", "ccr", "cxer", "clr", "cctr" 7882 }; 7883 7884 valid_p = 1; 7885 7886 for (i = 0; i < ARRAY_SIZE (cgprs); i++) 7887 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7888 PPC_CR0_REGNUM + i, 7889 cgprs[i]); 7890 if (!valid_p) 7891 return NULL; 7892 7893 have_htm_core = 1; 7894 } 7895 else 7896 have_htm_core = 0; 7897 7898 feature = tdesc_find_feature (tdesc, 7899 "org.gnu.gdb.power.htm.fpu"); 7900 if (feature != NULL) 7901 { 7902 valid_p = 1; 7903 7904 static const char *const cfprs[] = { 7905 "cf0", "cf1", "cf2", "cf3", "cf4", "cf5", "cf6", "cf7", 7906 "cf8", "cf9", "cf10", "cf11", "cf12", "cf13", "cf14", "cf15", 7907 "cf16", "cf17", "cf18", "cf19", "cf20", "cf21", "cf22", 7908 "cf23", "cf24", "cf25", "cf26", "cf27", "cf28", "cf29", 7909 "cf30", "cf31", "cfpscr" 7910 }; 7911 7912 for (i = 0; i < ARRAY_SIZE (cfprs); i++) 7913 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7914 PPC_CF0_REGNUM + i, 7915 cfprs[i]); 7916 7917 if (!valid_p) 7918 return NULL; 7919 have_htm_fpu = 1; 7920 } 7921 else 7922 have_htm_fpu = 0; 7923 7924 feature = tdesc_find_feature (tdesc, 7925 "org.gnu.gdb.power.htm.altivec"); 7926 if (feature != NULL) 7927 { 7928 valid_p = 1; 7929 7930 static const char *const cvmx[] = { 7931 "cvr0", "cvr1", "cvr2", "cvr3", "cvr4", "cvr5", "cvr6", 7932 "cvr7", "cvr8", "cvr9", "cvr10", "cvr11", "cvr12", "cvr13", 7933 "cvr14", "cvr15","cvr16", "cvr17", "cvr18", "cvr19", "cvr20", 7934 "cvr21", "cvr22", "cvr23", "cvr24", "cvr25", "cvr26", 7935 "cvr27", "cvr28", "cvr29", "cvr30", "cvr31", "cvscr", 7936 "cvrsave" 7937 }; 7938 7939 for (i = 0; i < ARRAY_SIZE (cvmx); i++) 7940 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7941 PPC_CVR0_REGNUM + i, 7942 cvmx[i]); 7943 7944 if (!valid_p) 7945 return NULL; 7946 have_htm_altivec = 1; 7947 } 7948 else 7949 have_htm_altivec = 0; 7950 7951 feature = tdesc_find_feature (tdesc, 7952 "org.gnu.gdb.power.htm.vsx"); 7953 if (feature != NULL) 7954 { 7955 valid_p = 1; 7956 7957 static const char *const cvsx[] = { 7958 "cvs0h", "cvs1h", "cvs2h", "cvs3h", "cvs4h", "cvs5h", 7959 "cvs6h", "cvs7h", "cvs8h", "cvs9h", "cvs10h", "cvs11h", 7960 "cvs12h", "cvs13h", "cvs14h", "cvs15h", "cvs16h", "cvs17h", 7961 "cvs18h", "cvs19h", "cvs20h", "cvs21h", "cvs22h", "cvs23h", 7962 "cvs24h", "cvs25h", "cvs26h", "cvs27h", "cvs28h", "cvs29h", 7963 "cvs30h", "cvs31h" 7964 }; 7965 7966 for (i = 0; i < ARRAY_SIZE (cvsx); i++) 7967 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 7968 (PPC_CVSR0_UPPER_REGNUM 7969 + i), 7970 cvsx[i]); 7971 7972 if (!valid_p || !have_htm_fpu || !have_htm_altivec) 7973 return NULL; 7974 have_htm_vsx = 1; 7975 } 7976 else 7977 have_htm_vsx = 0; 7978 7979 feature = tdesc_find_feature (tdesc, 7980 "org.gnu.gdb.power.htm.ppr"); 7981 if (feature != NULL) 7982 { 7983 valid_p = tdesc_numbered_register (feature, tdesc_data.get (), 7984 PPC_CPPR_REGNUM, "cppr"); 7985 7986 if (!valid_p) 7987 return NULL; 7988 have_htm_ppr = 1; 7989 } 7990 else 7991 have_htm_ppr = 0; 7992 7993 feature = tdesc_find_feature (tdesc, 7994 "org.gnu.gdb.power.htm.dscr"); 7995 if (feature != NULL) 7996 { 7997 valid_p = tdesc_numbered_register (feature, tdesc_data.get (), 7998 PPC_CDSCR_REGNUM, "cdscr"); 7999 8000 if (!valid_p) 8001 return NULL; 8002 have_htm_dscr = 1; 8003 } 8004 else 8005 have_htm_dscr = 0; 8006 8007 feature = tdesc_find_feature (tdesc, 8008 "org.gnu.gdb.power.htm.tar"); 8009 if (feature != NULL) 8010 { 8011 valid_p = tdesc_numbered_register (feature, tdesc_data.get (), 8012 PPC_CTAR_REGNUM, "ctar"); 8013 8014 if (!valid_p) 8015 return NULL; 8016 have_htm_tar = 1; 8017 } 8018 else 8019 have_htm_tar = 0; 8020 } 8021 8022 /* If we have a 64-bit binary on a 32-bit target, complain. Also 8023 complain for a 32-bit binary on a 64-bit target; we do not yet 8024 support that. For instance, the 32-bit ABI routines expect 8025 32-bit GPRs. 8026 8027 As long as there isn't an explicit target description, we'll 8028 choose one based on the BFD architecture and get a word size 8029 matching the binary (probably powerpc:common or 8030 powerpc:common64). So there is only trouble if a 64-bit target 8031 supplies a 64-bit description while debugging a 32-bit 8032 binary. */ 8033 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize) 8034 return NULL; 8035 8036 #ifdef HAVE_ELF 8037 if (from_elf_exec) 8038 { 8039 switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI) 8040 { 8041 case 1: 8042 elf_abi = POWERPC_ELF_V1; 8043 break; 8044 case 2: 8045 elf_abi = POWERPC_ELF_V2; 8046 break; 8047 default: 8048 break; 8049 } 8050 } 8051 8052 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec) 8053 { 8054 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8055 Tag_GNU_Power_ABI_FP) & 3) 8056 { 8057 case 1: 8058 soft_float_flag = AUTO_BOOLEAN_FALSE; 8059 break; 8060 case 2: 8061 soft_float_flag = AUTO_BOOLEAN_TRUE; 8062 break; 8063 default: 8064 break; 8065 } 8066 } 8067 8068 if (long_double_abi == POWERPC_LONG_DOUBLE_AUTO && from_elf_exec) 8069 { 8070 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8071 Tag_GNU_Power_ABI_FP) >> 2) 8072 { 8073 case 1: 8074 long_double_abi = POWERPC_LONG_DOUBLE_IBM128; 8075 break; 8076 case 3: 8077 long_double_abi = POWERPC_LONG_DOUBLE_IEEE128; 8078 break; 8079 default: 8080 break; 8081 } 8082 } 8083 8084 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec) 8085 { 8086 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8087 Tag_GNU_Power_ABI_Vector)) 8088 { 8089 case 1: 8090 vector_abi = POWERPC_VEC_GENERIC; 8091 break; 8092 case 2: 8093 vector_abi = POWERPC_VEC_ALTIVEC; 8094 break; 8095 case 3: 8096 vector_abi = POWERPC_VEC_SPE; 8097 break; 8098 default: 8099 break; 8100 } 8101 } 8102 #endif 8103 8104 /* At this point, the only supported ELF-based 64-bit little-endian 8105 operating system is GNU/Linux, and this uses the ELFv2 ABI by 8106 default. All other supported ELF-based operating systems use the 8107 ELFv1 ABI by default. Therefore, if the ABI marker is missing, 8108 e.g. because we run a legacy binary, or have attached to a process 8109 and have not found any associated binary file, set the default 8110 according to this heuristic. */ 8111 if (elf_abi == POWERPC_ELF_AUTO) 8112 { 8113 if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE) 8114 elf_abi = POWERPC_ELF_V2; 8115 else 8116 elf_abi = POWERPC_ELF_V1; 8117 } 8118 8119 if (soft_float_flag == AUTO_BOOLEAN_TRUE) 8120 soft_float = 1; 8121 else if (soft_float_flag == AUTO_BOOLEAN_FALSE) 8122 soft_float = 0; 8123 else 8124 soft_float = !have_fpu; 8125 8126 /* If we have a hard float binary or setting but no floating point 8127 registers, downgrade to soft float anyway. We're still somewhat 8128 useful in this scenario. */ 8129 if (!soft_float && !have_fpu) 8130 soft_float = 1; 8131 8132 /* Similarly for vector registers. */ 8133 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec) 8134 vector_abi = POWERPC_VEC_GENERIC; 8135 8136 if (vector_abi == POWERPC_VEC_SPE && !have_spe) 8137 vector_abi = POWERPC_VEC_GENERIC; 8138 8139 if (vector_abi == POWERPC_VEC_AUTO) 8140 { 8141 if (have_altivec) 8142 vector_abi = POWERPC_VEC_ALTIVEC; 8143 else if (have_spe) 8144 vector_abi = POWERPC_VEC_SPE; 8145 else 8146 vector_abi = POWERPC_VEC_GENERIC; 8147 } 8148 8149 /* Do not limit the vector ABI based on available hardware, since we 8150 do not yet know what hardware we'll decide we have. Yuck! FIXME! */ 8151 8152 /* Find a candidate among extant architectures. */ 8153 for (arches = gdbarch_list_lookup_by_info (arches, &info); 8154 arches != NULL; 8155 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 8156 { 8157 /* Word size in the various PowerPC bfd_arch_info structs isn't 8158 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 8159 separate word size check. */ 8160 ppc_gdbarch_tdep *tdep 8161 = gdbarch_tdep<ppc_gdbarch_tdep> (arches->gdbarch); 8162 if (tdep && tdep->elf_abi != elf_abi) 8163 continue; 8164 if (tdep && tdep->soft_float != soft_float) 8165 continue; 8166 if (tdep && tdep->long_double_abi != long_double_abi) 8167 continue; 8168 if (tdep && tdep->vector_abi != vector_abi) 8169 continue; 8170 if (tdep && tdep->wordsize == wordsize) 8171 return arches->gdbarch; 8172 } 8173 8174 /* None found, create a new architecture from INFO, whose bfd_arch_info 8175 validity depends on the source: 8176 - executable useless 8177 - rs6000_host_arch() good 8178 - core file good 8179 - "set arch" trust blindly 8180 - GDB startup useless but harmless */ 8181 8182 ppc_gdbarch_tdep *tdep = new ppc_gdbarch_tdep; 8183 tdep->wordsize = wordsize; 8184 tdep->elf_abi = elf_abi; 8185 tdep->soft_float = soft_float; 8186 tdep->long_double_abi = long_double_abi; 8187 tdep->vector_abi = vector_abi; 8188 8189 gdbarch = gdbarch_alloc (&info, tdep); 8190 8191 tdep->ppc_gp0_regnum = PPC_R0_REGNUM; 8192 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2; 8193 tdep->ppc_ps_regnum = PPC_MSR_REGNUM; 8194 tdep->ppc_cr_regnum = PPC_CR_REGNUM; 8195 tdep->ppc_lr_regnum = PPC_LR_REGNUM; 8196 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM; 8197 tdep->ppc_xer_regnum = PPC_XER_REGNUM; 8198 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1; 8199 8200 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1; 8201 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1; 8202 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1; 8203 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1; 8204 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1; 8205 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1; 8206 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1; 8207 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1; 8208 tdep->ppc_ppr_regnum = have_ppr ? PPC_PPR_REGNUM : -1; 8209 tdep->ppc_dscr_regnum = have_dscr ? PPC_DSCR_REGNUM : -1; 8210 tdep->ppc_tar_regnum = have_tar ? PPC_TAR_REGNUM : -1; 8211 tdep->have_ebb = have_ebb; 8212 8213 /* If additional pmu registers are added, care must be taken when 8214 setting new fields in the tdep below, to maintain compatibility 8215 with features that only provide some of the registers. Currently 8216 gdb access to the pmu registers is only supported in linux, and 8217 linux only provides a subset of the pmu registers defined in the 8218 architecture. */ 8219 8220 tdep->ppc_mmcr0_regnum = have_pmu ? PPC_MMCR0_REGNUM : -1; 8221 tdep->ppc_mmcr2_regnum = have_pmu ? PPC_MMCR2_REGNUM : -1; 8222 tdep->ppc_siar_regnum = have_pmu ? PPC_SIAR_REGNUM : -1; 8223 tdep->ppc_sdar_regnum = have_pmu ? PPC_SDAR_REGNUM : -1; 8224 tdep->ppc_sier_regnum = have_pmu ? PPC_SIER_REGNUM : -1; 8225 8226 tdep->have_htm_spr = have_htm_spr; 8227 tdep->have_htm_core = have_htm_core; 8228 tdep->have_htm_fpu = have_htm_fpu; 8229 tdep->have_htm_altivec = have_htm_altivec; 8230 tdep->have_htm_vsx = have_htm_vsx; 8231 tdep->ppc_cppr_regnum = have_htm_ppr ? PPC_CPPR_REGNUM : -1; 8232 tdep->ppc_cdscr_regnum = have_htm_dscr ? PPC_CDSCR_REGNUM : -1; 8233 tdep->ppc_ctar_regnum = have_htm_tar ? PPC_CTAR_REGNUM : -1; 8234 8235 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM); 8236 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1); 8237 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum); 8238 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); 8239 8240 /* The XML specification for PowerPC sensibly calls the MSR "msr". 8241 GDB traditionally called it "ps", though, so let GDB add an 8242 alias. */ 8243 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum); 8244 8245 if (wordsize == 8) 8246 { 8247 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 8248 set_gdbarch_get_return_buf_addr (gdbarch, 8249 ppc64_sysv_get_return_buf_addr); 8250 } 8251 else 8252 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 8253 8254 /* Set lr_frame_offset. */ 8255 if (wordsize == 8) 8256 tdep->lr_frame_offset = 16; 8257 else 8258 tdep->lr_frame_offset = 4; 8259 8260 if (have_spe || have_dfp || have_altivec 8261 || have_vsx || have_htm_fpu || have_htm_vsx) 8262 { 8263 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read); 8264 set_gdbarch_pseudo_register_write (gdbarch, 8265 rs6000_pseudo_register_write); 8266 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8267 rs6000_ax_pseudo_register_collect); 8268 } 8269 8270 set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address); 8271 8272 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 8273 8274 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS); 8275 8276 if (have_spe) 8277 num_pseudoregs += 32; 8278 if (have_dfp) 8279 num_pseudoregs += 16; 8280 if (have_altivec) 8281 num_pseudoregs += 32; 8282 if (have_vsx) 8283 /* Include both VSX and Extended FP registers. */ 8284 num_pseudoregs += 96; 8285 if (have_htm_fpu) 8286 num_pseudoregs += 16; 8287 /* Include both checkpointed VSX and EFP registers. */ 8288 if (have_htm_vsx) 8289 num_pseudoregs += 64 + 32; 8290 8291 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs); 8292 8293 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 8294 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 8295 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 8296 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 8297 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 8298 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 8299 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 8300 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 8301 set_gdbarch_char_signed (gdbarch, 0); 8302 8303 set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 8304 if (wordsize == 8) 8305 /* PPC64 SYSV. */ 8306 set_gdbarch_frame_red_zone_size (gdbarch, 288); 8307 8308 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); 8309 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); 8310 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); 8311 8312 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 8313 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); 8314 8315 if (wordsize == 4) 8316 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 8317 else if (wordsize == 8) 8318 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 8319 8320 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 8321 set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p); 8322 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue); 8323 8324 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8325 8326 set_gdbarch_breakpoint_kind_from_pc (gdbarch, 8327 rs6000_breakpoint::kind_from_pc); 8328 set_gdbarch_sw_breakpoint_from_kind (gdbarch, 8329 rs6000_breakpoint::bp_from_kind); 8330 set_gdbarch_program_breakpoint_here_p (gdbarch, 8331 rs6000_program_breakpoint_here_p); 8332 8333 /* The value of symbols of type N_SO and N_FUN maybe null when 8334 it shouldn't be. */ 8335 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1); 8336 8337 /* Handles single stepping of atomic sequences. */ 8338 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence); 8339 8340 /* Not sure on this. FIXMEmgo */ 8341 set_gdbarch_frame_args_skip (gdbarch, 8); 8342 8343 /* Helpers for function argument information. */ 8344 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 8345 8346 /* Trampoline. */ 8347 set_gdbarch_in_solib_return_trampoline 8348 (gdbarch, rs6000_in_solib_return_trampoline); 8349 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); 8350 8351 /* Hook in the DWARF CFI frame unwinder. */ 8352 dwarf2_append_unwinders (gdbarch); 8353 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); 8354 8355 /* Frame handling. */ 8356 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); 8357 8358 /* Setup displaced stepping. */ 8359 set_gdbarch_displaced_step_copy_insn (gdbarch, 8360 ppc_displaced_step_copy_insn); 8361 set_gdbarch_displaced_step_hw_singlestep (gdbarch, 8362 ppc_displaced_step_hw_singlestep); 8363 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup); 8364 set_gdbarch_displaced_step_prepare (gdbarch, ppc_displaced_step_prepare); 8365 set_gdbarch_displaced_step_finish (gdbarch, ppc_displaced_step_finish); 8366 set_gdbarch_displaced_step_restore_all_in_ptid 8367 (gdbarch, ppc_displaced_step_restore_all_in_ptid); 8368 8369 set_gdbarch_max_insn_length (gdbarch, 2 * PPC_INSN_SIZE); 8370 8371 /* Hook in ABI-specific overrides, if they have been registered. */ 8372 info.target_desc = tdesc; 8373 info.tdesc_data = tdesc_data.get (); 8374 gdbarch_init_osabi (info, gdbarch); 8375 8376 switch (info.osabi) 8377 { 8378 case GDB_OSABI_LINUX: 8379 case GDB_OSABI_NETBSD: 8380 case GDB_OSABI_UNKNOWN: 8381 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); 8382 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); 8383 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 8384 break; 8385 default: 8386 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 8387 8388 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind); 8389 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind); 8390 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 8391 } 8392 8393 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type); 8394 set_tdesc_pseudo_register_reggroup_p (gdbarch, 8395 rs6000_pseudo_register_reggroup_p); 8396 tdesc_use_registers (gdbarch, tdesc, std::move (tdesc_data)); 8397 8398 /* Override the normal target description method to make the SPE upper 8399 halves anonymous. */ 8400 set_gdbarch_register_name (gdbarch, rs6000_register_name); 8401 8402 /* Choose register numbers for all supported pseudo-registers. */ 8403 tdep->ppc_ev0_regnum = -1; 8404 tdep->ppc_dl0_regnum = -1; 8405 tdep->ppc_v0_alias_regnum = -1; 8406 tdep->ppc_vsr0_regnum = -1; 8407 tdep->ppc_efpr0_regnum = -1; 8408 tdep->ppc_cdl0_regnum = -1; 8409 tdep->ppc_cvsr0_regnum = -1; 8410 tdep->ppc_cefpr0_regnum = -1; 8411 8412 cur_reg = gdbarch_num_regs (gdbarch); 8413 8414 if (have_spe) 8415 { 8416 tdep->ppc_ev0_regnum = cur_reg; 8417 cur_reg += 32; 8418 } 8419 if (have_dfp) 8420 { 8421 tdep->ppc_dl0_regnum = cur_reg; 8422 cur_reg += 16; 8423 } 8424 if (have_altivec) 8425 { 8426 tdep->ppc_v0_alias_regnum = cur_reg; 8427 cur_reg += 32; 8428 } 8429 if (have_vsx) 8430 { 8431 tdep->ppc_vsr0_regnum = cur_reg; 8432 cur_reg += 64; 8433 tdep->ppc_efpr0_regnum = cur_reg; 8434 cur_reg += 32; 8435 } 8436 if (have_htm_fpu) 8437 { 8438 tdep->ppc_cdl0_regnum = cur_reg; 8439 cur_reg += 16; 8440 } 8441 if (have_htm_vsx) 8442 { 8443 tdep->ppc_cvsr0_regnum = cur_reg; 8444 cur_reg += 64; 8445 tdep->ppc_cefpr0_regnum = cur_reg; 8446 cur_reg += 32; 8447 } 8448 8449 gdb_assert (gdbarch_num_cooked_regs (gdbarch) == cur_reg); 8450 8451 /* Register the ravenscar_arch_ops. */ 8452 if (mach == bfd_mach_ppc_e500) 8453 register_e500_ravenscar_ops (gdbarch); 8454 else 8455 register_ppc_ravenscar_ops (gdbarch); 8456 8457 set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options); 8458 set_gdbarch_valid_disassembler_options (gdbarch, 8459 disassembler_options_powerpc ()); 8460 8461 return gdbarch; 8462 } 8463 8464 static void 8465 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 8466 { 8467 ppc_gdbarch_tdep *tdep = gdbarch_tdep<ppc_gdbarch_tdep> (gdbarch); 8468 8469 if (tdep == NULL) 8470 return; 8471 8472 /* FIXME: Dump gdbarch_tdep. */ 8473 } 8474 8475 static void 8476 powerpc_set_soft_float (const char *args, int from_tty, 8477 struct cmd_list_element *c) 8478 { 8479 struct gdbarch_info info; 8480 8481 /* Update the architecture. */ 8482 if (!gdbarch_update_p (info)) 8483 internal_error (_("could not update architecture")); 8484 } 8485 8486 static void 8487 powerpc_set_vector_abi (const char *args, int from_tty, 8488 struct cmd_list_element *c) 8489 { 8490 int vector_abi; 8491 8492 for (vector_abi = POWERPC_VEC_AUTO; 8493 vector_abi != POWERPC_VEC_LAST; 8494 vector_abi++) 8495 if (strcmp (powerpc_vector_abi_string, 8496 powerpc_vector_strings[vector_abi]) == 0) 8497 { 8498 powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi; 8499 break; 8500 } 8501 8502 if (vector_abi == POWERPC_VEC_LAST) 8503 internal_error (_("Invalid vector ABI accepted: %s."), 8504 powerpc_vector_abi_string); 8505 8506 /* Update the architecture. */ 8507 gdbarch_info info; 8508 if (!gdbarch_update_p (info)) 8509 internal_error (_("could not update architecture")); 8510 } 8511 8512 /* Show the current setting of the exact watchpoints flag. */ 8513 8514 static void 8515 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty, 8516 struct cmd_list_element *c, 8517 const char *value) 8518 { 8519 gdb_printf (file, _("Use of exact watchpoints is %s.\n"), value); 8520 } 8521 8522 /* Read a PPC instruction from memory. */ 8523 8524 static unsigned int 8525 read_insn (frame_info_ptr frame, CORE_ADDR pc) 8526 { 8527 struct gdbarch *gdbarch = get_frame_arch (frame); 8528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 8529 8530 return read_memory_unsigned_integer (pc, 4, byte_order); 8531 } 8532 8533 /* Return non-zero if the instructions at PC match the series 8534 described in PATTERN, or zero otherwise. PATTERN is an array of 8535 'struct ppc_insn_pattern' objects, terminated by an entry whose 8536 mask is zero. 8537 8538 When the match is successful, fill INSNS[i] with what PATTERN[i] 8539 matched. If PATTERN[i] is optional, and the instruction wasn't 8540 present, set INSNS[i] to 0 (which is not a valid PPC instruction). 8541 INSNS should have as many elements as PATTERN, minus the terminator. 8542 Note that, if PATTERN contains optional instructions which aren't 8543 present in memory, then INSNS will have holes, so INSNS[i] isn't 8544 necessarily the i'th instruction in memory. */ 8545 8546 int 8547 ppc_insns_match_pattern (frame_info_ptr frame, CORE_ADDR pc, 8548 const struct ppc_insn_pattern *pattern, 8549 unsigned int *insns) 8550 { 8551 int i; 8552 unsigned int insn; 8553 8554 for (i = 0, insn = 0; pattern[i].mask; i++) 8555 { 8556 if (insn == 0) 8557 insn = read_insn (frame, pc); 8558 insns[i] = 0; 8559 if ((insn & pattern[i].mask) == pattern[i].data) 8560 { 8561 insns[i] = insn; 8562 pc += 4; 8563 insn = 0; 8564 } 8565 else if (!pattern[i].optional) 8566 return 0; 8567 } 8568 8569 return 1; 8570 } 8571 8572 /* Return the 'd' field of the d-form instruction INSN, properly 8573 sign-extended. */ 8574 8575 CORE_ADDR 8576 ppc_insn_d_field (unsigned int insn) 8577 { 8578 return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000); 8579 } 8580 8581 /* Return the 'ds' field of the ds-form instruction INSN, with the two 8582 zero bits concatenated at the right, and properly 8583 sign-extended. */ 8584 8585 CORE_ADDR 8586 ppc_insn_ds_field (unsigned int insn) 8587 { 8588 return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000); 8589 } 8590 8591 CORE_ADDR 8592 ppc_insn_prefix_dform (unsigned int insn1, unsigned int insn2) 8593 { 8594 /* result is 34-bits */ 8595 return (CORE_ADDR) ((((insn1 & 0x3ffff) ^ 0x20000) - 0x20000) << 16) 8596 | (CORE_ADDR)(insn2 & 0xffff); 8597 } 8598 8599 /* Initialization code. */ 8600 8601 void _initialize_rs6000_tdep (); 8602 void 8603 _initialize_rs6000_tdep () 8604 { 8605 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 8606 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 8607 8608 /* Initialize the standard target descriptions. */ 8609 initialize_tdesc_powerpc_32 (); 8610 initialize_tdesc_powerpc_altivec32 (); 8611 initialize_tdesc_powerpc_vsx32 (); 8612 initialize_tdesc_powerpc_403 (); 8613 initialize_tdesc_powerpc_403gc (); 8614 initialize_tdesc_powerpc_405 (); 8615 initialize_tdesc_powerpc_505 (); 8616 initialize_tdesc_powerpc_601 (); 8617 initialize_tdesc_powerpc_602 (); 8618 initialize_tdesc_powerpc_603 (); 8619 initialize_tdesc_powerpc_604 (); 8620 initialize_tdesc_powerpc_64 (); 8621 initialize_tdesc_powerpc_altivec64 (); 8622 initialize_tdesc_powerpc_vsx64 (); 8623 initialize_tdesc_powerpc_7400 (); 8624 initialize_tdesc_powerpc_750 (); 8625 initialize_tdesc_powerpc_860 (); 8626 initialize_tdesc_powerpc_e500 (); 8627 initialize_tdesc_rs6000 (); 8628 8629 /* Add root prefix command for all "set powerpc"/"show powerpc" 8630 commands. */ 8631 add_setshow_prefix_cmd ("powerpc", no_class, 8632 _("Various PowerPC-specific commands."), 8633 _("Various PowerPC-specific commands."), 8634 &setpowerpccmdlist, &showpowerpccmdlist, 8635 &setlist, &showlist); 8636 8637 /* Add a command to allow the user to force the ABI. */ 8638 add_setshow_auto_boolean_cmd ("soft-float", class_support, 8639 &powerpc_soft_float_global, 8640 _("Set whether to use a soft-float ABI."), 8641 _("Show whether to use a soft-float ABI."), 8642 NULL, 8643 powerpc_set_soft_float, NULL, 8644 &setpowerpccmdlist, &showpowerpccmdlist); 8645 8646 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings, 8647 &powerpc_vector_abi_string, 8648 _("Set the vector ABI."), 8649 _("Show the vector ABI."), 8650 NULL, powerpc_set_vector_abi, NULL, 8651 &setpowerpccmdlist, &showpowerpccmdlist); 8652 8653 add_setshow_boolean_cmd ("exact-watchpoints", class_support, 8654 &target_exact_watchpoints, 8655 _("\ 8656 Set whether to use just one debug register for watchpoints on scalars."), 8657 _("\ 8658 Show whether to use just one debug register for watchpoints on scalars."), 8659 _("\ 8660 If true, GDB will use only one debug register when watching a variable of\n\ 8661 scalar type, thus assuming that the variable is accessed through the address\n\ 8662 of its first byte."), 8663 NULL, show_powerpc_exact_watchpoints, 8664 &setpowerpccmdlist, &showpowerpccmdlist); 8665 } 8666