1 /* Target-dependent code for the NDS32 architecture, for GDB. 2 3 Copyright (C) 2013-2023 Free Software Foundation, Inc. 4 Contributed by Andes Technology Corporation. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21 #ifndef NDS32_TDEP_H 22 #define NDS32_TDEP_H 23 24 #include "gdbarch.h" 25 26 enum nds32_regnum 27 { 28 /* General purpose registers. */ 29 NDS32_R0_REGNUM = 0, 30 NDS32_R5_REGNUM = 5, 31 NDS32_TA_REGNUM = 15, /* Temporary register. */ 32 NDS32_FP_REGNUM = 28, /* Frame pointer. */ 33 NDS32_GP_REGNUM = 29, /* Global pointer. */ 34 NDS32_LP_REGNUM = 30, /* Link pointer. */ 35 NDS32_SP_REGNUM = 31, /* Stack pointer. */ 36 37 NDS32_PC_REGNUM = 32, /* Program counter. */ 38 39 NDS32_NUM_REGS, 40 41 /* The first double precision floating-point register. */ 42 NDS32_FD0_REGNUM = NDS32_NUM_REGS, 43 }; 44 45 struct nds32_gdbarch_tdep : gdbarch_tdep_base 46 { 47 /* The guessed FPU configuration. */ 48 int fpu_freg = 0; 49 /* FSRs are defined as pseudo registers. */ 50 int use_pseudo_fsrs = 0; 51 /* Cached regnum of the first FSR (FS0). */ 52 int fs0_regnum = 0; 53 /* ELF ABI info. */ 54 int elf_abi = 0; 55 }; 56 #endif /* NDS32_TDEP_H */ 57