1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. 2 3 Copyright (C) 1988-2016 Free Software Foundation, Inc. 4 5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU 6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "inferior.h" 26 #include "symtab.h" 27 #include "value.h" 28 #include "gdbcmd.h" 29 #include "language.h" 30 #include "gdbcore.h" 31 #include "symfile.h" 32 #include "objfiles.h" 33 #include "gdbtypes.h" 34 #include "target.h" 35 #include "arch-utils.h" 36 #include "regcache.h" 37 #include "osabi.h" 38 #include "mips-tdep.h" 39 #include "block.h" 40 #include "reggroups.h" 41 #include "opcode/mips.h" 42 #include "elf/mips.h" 43 #include "elf-bfd.h" 44 #include "symcat.h" 45 #include "sim-regno.h" 46 #include "dis-asm.h" 47 #include "frame-unwind.h" 48 #include "frame-base.h" 49 #include "trad-frame.h" 50 #include "infcall.h" 51 #include "floatformat.h" 52 #include "remote.h" 53 #include "target-descriptions.h" 54 #include "dwarf2-frame.h" 55 #include "user-regs.h" 56 #include "valprint.h" 57 #include "ax.h" 58 59 static const struct objfile_data *mips_pdr_data; 60 61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); 62 63 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, 64 ULONGEST inst); 65 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); 66 static int mips16_instruction_has_delay_slot (unsigned short inst, 67 int mustbe32); 68 69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 70 CORE_ADDR addr); 71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 72 CORE_ADDR addr, int mustbe32); 73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 74 CORE_ADDR addr, int mustbe32); 75 76 static void mips_print_float_info (struct gdbarch *, struct ui_file *, 77 struct frame_info *, const char *); 78 79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ 80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ 81 #define ST0_FR (1 << 26) 82 83 /* The sizes of floating point registers. */ 84 85 enum 86 { 87 MIPS_FPU_SINGLE_REGSIZE = 4, 88 MIPS_FPU_DOUBLE_REGSIZE = 8 89 }; 90 91 enum 92 { 93 MIPS32_REGSIZE = 4, 94 MIPS64_REGSIZE = 8 95 }; 96 97 static const char *mips_abi_string; 98 99 static const char *const mips_abi_strings[] = { 100 "auto", 101 "n32", 102 "o32", 103 "n64", 104 "o64", 105 "eabi32", 106 "eabi64", 107 NULL 108 }; 109 110 /* For backwards compatibility we default to MIPS16. This flag is 111 overridden as soon as unambiguous ELF file flags tell us the 112 compressed ISA encoding used. */ 113 static const char mips_compression_mips16[] = "mips16"; 114 static const char mips_compression_micromips[] = "micromips"; 115 static const char *const mips_compression_strings[] = 116 { 117 mips_compression_mips16, 118 mips_compression_micromips, 119 NULL 120 }; 121 122 static const char *mips_compression_string = mips_compression_mips16; 123 124 /* The standard register names, and all the valid aliases for them. */ 125 struct register_alias 126 { 127 const char *name; 128 int regnum; 129 }; 130 131 /* Aliases for o32 and most other ABIs. */ 132 const struct register_alias mips_o32_aliases[] = { 133 { "ta0", 12 }, 134 { "ta1", 13 }, 135 { "ta2", 14 }, 136 { "ta3", 15 } 137 }; 138 139 /* Aliases for n32 and n64. */ 140 const struct register_alias mips_n32_n64_aliases[] = { 141 { "ta0", 8 }, 142 { "ta1", 9 }, 143 { "ta2", 10 }, 144 { "ta3", 11 } 145 }; 146 147 /* Aliases for ABI-independent registers. */ 148 const struct register_alias mips_register_aliases[] = { 149 /* The architecture manuals specify these ABI-independent names for 150 the GPRs. */ 151 #define R(n) { "r" #n, n } 152 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 153 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 154 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 155 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 156 #undef R 157 158 /* k0 and k1 are sometimes called these instead (for "kernel 159 temp"). */ 160 { "kt0", 26 }, 161 { "kt1", 27 }, 162 163 /* This is the traditional GDB name for the CP0 status register. */ 164 { "sr", MIPS_PS_REGNUM }, 165 166 /* This is the traditional GDB name for the CP0 BadVAddr register. */ 167 { "bad", MIPS_EMBED_BADVADDR_REGNUM }, 168 169 /* This is the traditional GDB name for the FCSR. */ 170 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } 171 }; 172 173 const struct register_alias mips_numeric_register_aliases[] = { 174 #define R(n) { #n, n } 175 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 176 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 177 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 178 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 179 #undef R 180 }; 181 182 #ifndef MIPS_DEFAULT_FPU_TYPE 183 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE 184 #endif 185 static int mips_fpu_type_auto = 1; 186 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; 187 188 static unsigned int mips_debug = 0; 189 190 /* Properties (for struct target_desc) describing the g/G packet 191 layout. */ 192 #define PROPERTY_GP32 "internal: transfers-32bit-registers" 193 #define PROPERTY_GP64 "internal: transfers-64bit-registers" 194 195 struct target_desc *mips_tdesc_gp32; 196 struct target_desc *mips_tdesc_gp64; 197 198 const struct mips_regnum * 199 mips_regnum (struct gdbarch *gdbarch) 200 { 201 return gdbarch_tdep (gdbarch)->regnum; 202 } 203 204 static int 205 mips_fpa0_regnum (struct gdbarch *gdbarch) 206 { 207 return mips_regnum (gdbarch)->fp0 + 12; 208 } 209 210 /* Return 1 if REGNUM refers to a floating-point general register, raw 211 or cooked. Otherwise return 0. */ 212 213 static int 214 mips_float_register_p (struct gdbarch *gdbarch, int regnum) 215 { 216 int rawnum = regnum % gdbarch_num_regs (gdbarch); 217 218 return (rawnum >= mips_regnum (gdbarch)->fp0 219 && rawnum < mips_regnum (gdbarch)->fp0 + 32); 220 } 221 222 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ 223 == MIPS_ABI_EABI32 \ 224 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) 225 226 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ 227 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) 228 229 #define MIPS_LAST_ARG_REGNUM(gdbarch) \ 230 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) 231 232 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) 233 234 /* Return the MIPS ABI associated with GDBARCH. */ 235 enum mips_abi 236 mips_abi (struct gdbarch *gdbarch) 237 { 238 return gdbarch_tdep (gdbarch)->mips_abi; 239 } 240 241 int 242 mips_isa_regsize (struct gdbarch *gdbarch) 243 { 244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 245 246 /* If we know how big the registers are, use that size. */ 247 if (tdep->register_size_valid_p) 248 return tdep->register_size; 249 250 /* Fall back to the previous behavior. */ 251 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word 252 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); 253 } 254 255 /* Return the currently configured (or set) saved register size. */ 256 257 unsigned int 258 mips_abi_regsize (struct gdbarch *gdbarch) 259 { 260 switch (mips_abi (gdbarch)) 261 { 262 case MIPS_ABI_EABI32: 263 case MIPS_ABI_O32: 264 return 4; 265 case MIPS_ABI_N32: 266 case MIPS_ABI_N64: 267 case MIPS_ABI_O64: 268 case MIPS_ABI_EABI64: 269 return 8; 270 case MIPS_ABI_UNKNOWN: 271 case MIPS_ABI_LAST: 272 default: 273 internal_error (__FILE__, __LINE__, _("bad switch")); 274 } 275 } 276 277 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here 278 are some functions to handle addresses associated with compressed 279 code including but not limited to testing, setting, or clearing 280 bit 0 of such addresses. */ 281 282 /* Return one iff compressed code is the MIPS16 instruction set. */ 283 284 static int 285 is_mips16_isa (struct gdbarch *gdbarch) 286 { 287 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; 288 } 289 290 /* Return one iff compressed code is the microMIPS instruction set. */ 291 292 static int 293 is_micromips_isa (struct gdbarch *gdbarch) 294 { 295 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; 296 } 297 298 /* Return one iff ADDR denotes compressed code. */ 299 300 static int 301 is_compact_addr (CORE_ADDR addr) 302 { 303 return ((addr) & 1); 304 } 305 306 /* Return one iff ADDR denotes standard ISA code. */ 307 308 static int 309 is_mips_addr (CORE_ADDR addr) 310 { 311 return !is_compact_addr (addr); 312 } 313 314 /* Return one iff ADDR denotes MIPS16 code. */ 315 316 static int 317 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 318 { 319 return is_compact_addr (addr) && is_mips16_isa (gdbarch); 320 } 321 322 /* Return one iff ADDR denotes microMIPS code. */ 323 324 static int 325 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 326 { 327 return is_compact_addr (addr) && is_micromips_isa (gdbarch); 328 } 329 330 /* Strip the ISA (compression) bit off from ADDR. */ 331 332 static CORE_ADDR 333 unmake_compact_addr (CORE_ADDR addr) 334 { 335 return ((addr) & ~(CORE_ADDR) 1); 336 } 337 338 /* Add the ISA (compression) bit to ADDR. */ 339 340 static CORE_ADDR 341 make_compact_addr (CORE_ADDR addr) 342 { 343 return ((addr) | (CORE_ADDR) 1); 344 } 345 346 /* Extern version of unmake_compact_addr; we use a separate function 347 so that unmake_compact_addr can be inlined throughout this file. */ 348 349 CORE_ADDR 350 mips_unmake_compact_addr (CORE_ADDR addr) 351 { 352 return unmake_compact_addr (addr); 353 } 354 355 /* Functions for setting and testing a bit in a minimal symbol that 356 marks it as MIPS16 or microMIPS function. The MSB of the minimal 357 symbol's "info" field is used for this purpose. 358 359 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is 360 "special", i.e. refers to a MIPS16 or microMIPS function, and sets 361 one of the "special" bits in a minimal symbol to mark it accordingly. 362 The test checks an ELF-private flag that is valid for true function 363 symbols only; for synthetic symbols such as for PLT stubs that have 364 no ELF-private part at all the MIPS BFD backend arranges for this 365 information to be carried in the asymbol's udata field instead. 366 367 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit 368 in a minimal symbol. */ 369 370 static void 371 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) 372 { 373 elf_symbol_type *elfsym = (elf_symbol_type *) sym; 374 unsigned char st_other; 375 376 if ((sym->flags & BSF_SYNTHETIC) == 0) 377 st_other = elfsym->internal_elf_sym.st_other; 378 else if ((sym->flags & BSF_FUNCTION) != 0) 379 st_other = sym->udata.i; 380 else 381 return; 382 383 if (ELF_ST_IS_MICROMIPS (st_other)) 384 { 385 MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; 386 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); 387 } 388 else if (ELF_ST_IS_MIPS16 (st_other)) 389 { 390 MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; 391 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); 392 } 393 } 394 395 /* Return one iff MSYM refers to standard ISA code. */ 396 397 static int 398 msymbol_is_mips (struct minimal_symbol *msym) 399 { 400 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) 401 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); 402 } 403 404 /* Return one iff MSYM refers to MIPS16 code. */ 405 406 static int 407 msymbol_is_mips16 (struct minimal_symbol *msym) 408 { 409 return MSYMBOL_TARGET_FLAG_MIPS16 (msym); 410 } 411 412 /* Return one iff MSYM refers to microMIPS code. */ 413 414 static int 415 msymbol_is_micromips (struct minimal_symbol *msym) 416 { 417 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); 418 } 419 420 /* Set the ISA bit in the main symbol too, complementing the corresponding 421 minimal symbol setting and reflecting the run-time value of the symbol. 422 The need for comes from the ISA bit having been cleared as code in 423 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's 424 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values 425 of symbols referring to compressed code different in GDB to the values 426 used by actual code. That in turn makes them evaluate incorrectly in 427 expressions, producing results different to what the same expressions 428 yield when compiled into the program being debugged. */ 429 430 static void 431 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) 432 { 433 if (SYMBOL_CLASS (sym) == LOC_BLOCK) 434 { 435 /* We are in symbol reading so it is OK to cast away constness. */ 436 struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); 437 CORE_ADDR compact_block_start; 438 struct bound_minimal_symbol msym; 439 440 compact_block_start = BLOCK_START (block) | 1; 441 msym = lookup_minimal_symbol_by_pc (compact_block_start); 442 if (msym.minsym && !msymbol_is_mips (msym.minsym)) 443 { 444 BLOCK_START (block) = compact_block_start; 445 } 446 } 447 } 448 449 /* XFER a value from the big/little/left end of the register. 450 Depending on the size of the value it might occupy the entire 451 register or just part of it. Make an allowance for this, aligning 452 things accordingly. */ 453 454 static void 455 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, 456 int reg_num, int length, 457 enum bfd_endian endian, gdb_byte *in, 458 const gdb_byte *out, int buf_offset) 459 { 460 int reg_offset = 0; 461 462 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); 463 /* Need to transfer the left or right part of the register, based on 464 the targets byte order. */ 465 switch (endian) 466 { 467 case BFD_ENDIAN_BIG: 468 reg_offset = register_size (gdbarch, reg_num) - length; 469 break; 470 case BFD_ENDIAN_LITTLE: 471 reg_offset = 0; 472 break; 473 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ 474 reg_offset = 0; 475 break; 476 default: 477 internal_error (__FILE__, __LINE__, _("bad switch")); 478 } 479 if (mips_debug) 480 fprintf_unfiltered (gdb_stderr, 481 "xfer $%d, reg offset %d, buf offset %d, length %d, ", 482 reg_num, reg_offset, buf_offset, length); 483 if (mips_debug && out != NULL) 484 { 485 int i; 486 fprintf_unfiltered (gdb_stdlog, "out "); 487 for (i = 0; i < length; i++) 488 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); 489 } 490 if (in != NULL) 491 regcache_cooked_read_part (regcache, reg_num, reg_offset, length, 492 in + buf_offset); 493 if (out != NULL) 494 regcache_cooked_write_part (regcache, reg_num, reg_offset, length, 495 out + buf_offset); 496 if (mips_debug && in != NULL) 497 { 498 int i; 499 fprintf_unfiltered (gdb_stdlog, "in "); 500 for (i = 0; i < length; i++) 501 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); 502 } 503 if (mips_debug) 504 fprintf_unfiltered (gdb_stdlog, "\n"); 505 } 506 507 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU 508 compatiblity mode. A return value of 1 means that we have 509 physical 64-bit registers, but should treat them as 32-bit registers. */ 510 511 static int 512 mips2_fp_compat (struct frame_info *frame) 513 { 514 struct gdbarch *gdbarch = get_frame_arch (frame); 515 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not 516 meaningful. */ 517 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) 518 return 0; 519 520 #if 0 521 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, 522 in all the places we deal with FP registers. PR gdb/413. */ 523 /* Otherwise check the FR bit in the status register - it controls 524 the FP compatiblity mode. If it is clear we are in compatibility 525 mode. */ 526 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) 527 return 1; 528 #endif 529 530 return 0; 531 } 532 533 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 534 535 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); 536 537 static void reinit_frame_cache_sfunc (char *, int, struct cmd_list_element *); 538 539 /* The list of available "set mips " and "show mips " commands. */ 540 541 static struct cmd_list_element *setmipscmdlist = NULL; 542 static struct cmd_list_element *showmipscmdlist = NULL; 543 544 /* Integer registers 0 thru 31 are handled explicitly by 545 mips_register_name(). Processor specific registers 32 and above 546 are listed in the following tables. */ 547 548 enum 549 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; 550 551 /* Generic MIPS. */ 552 553 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 554 "sr", "lo", "hi", "bad", "cause", "pc", 555 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 556 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 557 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 558 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 559 "fsr", "fir", 560 }; 561 562 /* Names of IDT R3041 registers. */ 563 564 static const char *mips_r3041_reg_names[] = { 565 "sr", "lo", "hi", "bad", "cause", "pc", 566 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 567 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 568 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 569 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 570 "fsr", "fir", "", /*"fp" */ "", 571 "", "", "bus", "ccfg", "", "", "", "", 572 "", "", "port", "cmp", "", "", "epc", "prid", 573 }; 574 575 /* Names of tx39 registers. */ 576 577 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 578 "sr", "lo", "hi", "bad", "cause", "pc", 579 "", "", "", "", "", "", "", "", 580 "", "", "", "", "", "", "", "", 581 "", "", "", "", "", "", "", "", 582 "", "", "", "", "", "", "", "", 583 "", "", "", "", 584 "", "", "", "", "", "", "", "", 585 "", "", "config", "cache", "debug", "depc", "epc", 586 }; 587 588 /* Names of IRIX registers. */ 589 static const char *mips_irix_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 590 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 591 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 592 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 593 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 594 "pc", "cause", "bad", "hi", "lo", "fsr", "fir" 595 }; 596 597 /* Names of registers with Linux kernels. */ 598 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 599 "sr", "lo", "hi", "bad", "cause", "pc", 600 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 601 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 602 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 603 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 604 "fsr", "fir" 605 }; 606 607 608 /* Return the name of the register corresponding to REGNO. */ 609 static const char * 610 mips_register_name (struct gdbarch *gdbarch, int regno) 611 { 612 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 613 /* GPR names for all ABIs other than n32/n64. */ 614 static char *mips_gpr_names[] = { 615 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 616 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 617 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 618 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 619 }; 620 621 /* GPR names for n32 and n64 ABIs. */ 622 static char *mips_n32_n64_gpr_names[] = { 623 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 624 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 625 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 626 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 627 }; 628 629 enum mips_abi abi = mips_abi (gdbarch); 630 631 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, 632 but then don't make the raw register names visible. This (upper) 633 range of user visible register numbers are the pseudo-registers. 634 635 This approach was adopted accommodate the following scenario: 636 It is possible to debug a 64-bit device using a 32-bit 637 programming model. In such instances, the raw registers are 638 configured to be 64-bits wide, while the pseudo registers are 639 configured to be 32-bits wide. The registers that the user 640 sees - the pseudo registers - match the users expectations 641 given the programming model being used. */ 642 int rawnum = regno % gdbarch_num_regs (gdbarch); 643 if (regno < gdbarch_num_regs (gdbarch)) 644 return ""; 645 646 /* The MIPS integer registers are always mapped from 0 to 31. The 647 names of the registers (which reflects the conventions regarding 648 register use) vary depending on the ABI. */ 649 if (0 <= rawnum && rawnum < 32) 650 { 651 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) 652 return mips_n32_n64_gpr_names[rawnum]; 653 else 654 return mips_gpr_names[rawnum]; 655 } 656 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 657 return tdesc_register_name (gdbarch, rawnum); 658 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) 659 { 660 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); 661 if (tdep->mips_processor_reg_names[rawnum - 32]) 662 return tdep->mips_processor_reg_names[rawnum - 32]; 663 return ""; 664 } 665 else 666 internal_error (__FILE__, __LINE__, 667 _("mips_register_name: bad register number %d"), rawnum); 668 } 669 670 /* Return the groups that a MIPS register can be categorised into. */ 671 672 static int 673 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 674 struct reggroup *reggroup) 675 { 676 int vector_p; 677 int float_p; 678 int raw_p; 679 int rawnum = regnum % gdbarch_num_regs (gdbarch); 680 int pseudo = regnum / gdbarch_num_regs (gdbarch); 681 if (reggroup == all_reggroup) 682 return pseudo; 683 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); 684 float_p = TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT; 685 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs 686 (gdbarch), as not all architectures are multi-arch. */ 687 raw_p = rawnum < gdbarch_num_regs (gdbarch); 688 if (gdbarch_register_name (gdbarch, regnum) == NULL 689 || gdbarch_register_name (gdbarch, regnum)[0] == '\0') 690 return 0; 691 if (reggroup == float_reggroup) 692 return float_p && pseudo; 693 if (reggroup == vector_reggroup) 694 return vector_p && pseudo; 695 if (reggroup == general_reggroup) 696 return (!vector_p && !float_p) && pseudo; 697 /* Save the pseudo registers. Need to make certain that any code 698 extracting register values from a saved register cache also uses 699 pseudo registers. */ 700 if (reggroup == save_reggroup) 701 return raw_p && pseudo; 702 /* Restore the same pseudo register. */ 703 if (reggroup == restore_reggroup) 704 return raw_p && pseudo; 705 return 0; 706 } 707 708 /* Return the groups that a MIPS register can be categorised into. 709 This version is only used if we have a target description which 710 describes real registers (and their groups). */ 711 712 static int 713 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 714 struct reggroup *reggroup) 715 { 716 int rawnum = regnum % gdbarch_num_regs (gdbarch); 717 int pseudo = regnum / gdbarch_num_regs (gdbarch); 718 int ret; 719 720 /* Only save, restore, and display the pseudo registers. Need to 721 make certain that any code extracting register values from a 722 saved register cache also uses pseudo registers. 723 724 Note: saving and restoring the pseudo registers is slightly 725 strange; if we have 64 bits, we should save and restore all 726 64 bits. But this is hard and has little benefit. */ 727 if (!pseudo) 728 return 0; 729 730 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); 731 if (ret != -1) 732 return ret; 733 734 return mips_register_reggroup_p (gdbarch, regnum, reggroup); 735 } 736 737 /* Map the symbol table registers which live in the range [1 * 738 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw 739 registers. Take care of alignment and size problems. */ 740 741 static enum register_status 742 mips_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 743 int cookednum, gdb_byte *buf) 744 { 745 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 746 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 747 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 748 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 749 return regcache_raw_read (regcache, rawnum, buf); 750 else if (register_size (gdbarch, rawnum) > 751 register_size (gdbarch, cookednum)) 752 { 753 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 754 return regcache_raw_read_part (regcache, rawnum, 0, 4, buf); 755 else 756 { 757 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 758 LONGEST regval; 759 enum register_status status; 760 761 status = regcache_raw_read_signed (regcache, rawnum, ®val); 762 if (status == REG_VALID) 763 store_signed_integer (buf, 4, byte_order, regval); 764 return status; 765 } 766 } 767 else 768 internal_error (__FILE__, __LINE__, _("bad register size")); 769 } 770 771 static void 772 mips_pseudo_register_write (struct gdbarch *gdbarch, 773 struct regcache *regcache, int cookednum, 774 const gdb_byte *buf) 775 { 776 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 777 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 778 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 779 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 780 regcache_raw_write (regcache, rawnum, buf); 781 else if (register_size (gdbarch, rawnum) > 782 register_size (gdbarch, cookednum)) 783 { 784 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 785 regcache_raw_write_part (regcache, rawnum, 0, 4, buf); 786 else 787 { 788 /* Sign extend the shortened version of the register prior 789 to placing it in the raw register. This is required for 790 some mips64 parts in order to avoid unpredictable behavior. */ 791 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 792 LONGEST regval = extract_signed_integer (buf, 4, byte_order); 793 regcache_raw_write_signed (regcache, rawnum, regval); 794 } 795 } 796 else 797 internal_error (__FILE__, __LINE__, _("bad register size")); 798 } 799 800 static int 801 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, 802 struct agent_expr *ax, int reg) 803 { 804 int rawnum = reg % gdbarch_num_regs (gdbarch); 805 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 806 && reg < 2 * gdbarch_num_regs (gdbarch)); 807 808 ax_reg_mask (ax, rawnum); 809 810 return 0; 811 } 812 813 static int 814 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, 815 struct agent_expr *ax, int reg) 816 { 817 int rawnum = reg % gdbarch_num_regs (gdbarch); 818 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 819 && reg < 2 * gdbarch_num_regs (gdbarch)); 820 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) 821 { 822 ax_reg (ax, rawnum); 823 824 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) 825 { 826 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p 827 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) 828 { 829 ax_const_l (ax, 32); 830 ax_simple (ax, aop_lsh); 831 } 832 ax_const_l (ax, 32); 833 ax_simple (ax, aop_rsh_signed); 834 } 835 } 836 else 837 internal_error (__FILE__, __LINE__, _("bad register size")); 838 839 return 0; 840 } 841 842 /* Table to translate 3-bit register field to actual register number. */ 843 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 844 845 /* Heuristic_proc_start may hunt through the text section for a long 846 time across a 2400 baud serial line. Allows the user to limit this 847 search. */ 848 849 static int heuristic_fence_post = 0; 850 851 /* Number of bytes of storage in the actual machine representation for 852 register N. NOTE: This defines the pseudo register type so need to 853 rebuild the architecture vector. */ 854 855 static int mips64_transfers_32bit_regs_p = 0; 856 857 static void 858 set_mips64_transfers_32bit_regs (char *args, int from_tty, 859 struct cmd_list_element *c) 860 { 861 struct gdbarch_info info; 862 gdbarch_info_init (&info); 863 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 864 instead of relying on globals. Doing that would let generic code 865 handle the search for this specific architecture. */ 866 if (!gdbarch_update_p (info)) 867 { 868 mips64_transfers_32bit_regs_p = 0; 869 error (_("32-bit compatibility mode not supported")); 870 } 871 } 872 873 /* Convert to/from a register and the corresponding memory value. */ 874 875 /* This predicate tests for the case of an 8 byte floating point 876 value that is being transferred to or from a pair of floating point 877 registers each of which are (or are considered to be) only 4 bytes 878 wide. */ 879 static int 880 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, 881 struct type *type) 882 { 883 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 884 && register_size (gdbarch, regnum) == 4 885 && mips_float_register_p (gdbarch, regnum) 886 && TYPE_CODE (type) == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); 887 } 888 889 /* This predicate tests for the case of a value of less than 8 890 bytes in width that is being transfered to or from an 8 byte 891 general purpose register. */ 892 static int 893 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, 894 struct type *type) 895 { 896 int num_regs = gdbarch_num_regs (gdbarch); 897 898 return (register_size (gdbarch, regnum) == 8 899 && regnum % num_regs > 0 && regnum % num_regs < 32 900 && TYPE_LENGTH (type) < 8); 901 } 902 903 static int 904 mips_convert_register_p (struct gdbarch *gdbarch, 905 int regnum, struct type *type) 906 { 907 return (mips_convert_register_float_case_p (gdbarch, regnum, type) 908 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); 909 } 910 911 static int 912 mips_register_to_value (struct frame_info *frame, int regnum, 913 struct type *type, gdb_byte *to, 914 int *optimizedp, int *unavailablep) 915 { 916 struct gdbarch *gdbarch = get_frame_arch (frame); 917 918 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 919 { 920 get_frame_register (frame, regnum + 0, to + 4); 921 get_frame_register (frame, regnum + 1, to + 0); 922 923 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, 924 optimizedp, unavailablep)) 925 return 0; 926 927 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, 928 optimizedp, unavailablep)) 929 return 0; 930 *optimizedp = *unavailablep = 0; 931 return 1; 932 } 933 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 934 { 935 int len = TYPE_LENGTH (type); 936 CORE_ADDR offset; 937 938 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; 939 if (!get_frame_register_bytes (frame, regnum, offset, len, to, 940 optimizedp, unavailablep)) 941 return 0; 942 943 *optimizedp = *unavailablep = 0; 944 return 1; 945 } 946 else 947 { 948 internal_error (__FILE__, __LINE__, 949 _("mips_register_to_value: unrecognized case")); 950 } 951 } 952 953 static void 954 mips_value_to_register (struct frame_info *frame, int regnum, 955 struct type *type, const gdb_byte *from) 956 { 957 struct gdbarch *gdbarch = get_frame_arch (frame); 958 959 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 960 { 961 put_frame_register (frame, regnum + 0, from + 4); 962 put_frame_register (frame, regnum + 1, from + 0); 963 } 964 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 965 { 966 gdb_byte fill[8]; 967 int len = TYPE_LENGTH (type); 968 969 /* Sign extend values, irrespective of type, that are stored to 970 a 64-bit general purpose register. (32-bit unsigned values 971 are stored as signed quantities within a 64-bit register. 972 When performing an operation, in compiled code, that combines 973 a 32-bit unsigned value with a signed 64-bit value, a type 974 conversion is first performed that zeroes out the high 32 bits.) */ 975 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 976 { 977 if (from[0] & 0x80) 978 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); 979 else 980 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); 981 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); 982 put_frame_register_bytes (frame, regnum, 8 - len, len, from); 983 } 984 else 985 { 986 if (from[len-1] & 0x80) 987 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); 988 else 989 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); 990 put_frame_register_bytes (frame, regnum, 0, len, from); 991 put_frame_register_bytes (frame, regnum, len, 8 - len, fill); 992 } 993 } 994 else 995 { 996 internal_error (__FILE__, __LINE__, 997 _("mips_value_to_register: unrecognized case")); 998 } 999 } 1000 1001 /* Return the GDB type object for the "standard" data type of data in 1002 register REG. */ 1003 1004 static struct type * 1005 mips_register_type (struct gdbarch *gdbarch, int regnum) 1006 { 1007 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); 1008 if (mips_float_register_p (gdbarch, regnum)) 1009 { 1010 /* The floating-point registers raw, or cooked, always match 1011 mips_isa_regsize(), and also map 1:1, byte for byte. */ 1012 if (mips_isa_regsize (gdbarch) == 4) 1013 return builtin_type (gdbarch)->builtin_float; 1014 else 1015 return builtin_type (gdbarch)->builtin_double; 1016 } 1017 else if (regnum < gdbarch_num_regs (gdbarch)) 1018 { 1019 /* The raw or ISA registers. These are all sized according to 1020 the ISA regsize. */ 1021 if (mips_isa_regsize (gdbarch) == 4) 1022 return builtin_type (gdbarch)->builtin_int32; 1023 else 1024 return builtin_type (gdbarch)->builtin_int64; 1025 } 1026 else 1027 { 1028 int rawnum = regnum - gdbarch_num_regs (gdbarch); 1029 1030 /* The cooked or ABI registers. These are sized according to 1031 the ABI (with a few complications). */ 1032 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1033 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1034 return builtin_type (gdbarch)->builtin_int32; 1035 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX 1036 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1037 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1038 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1039 /* The pseudo/cooked view of the embedded registers is always 1040 32-bit. The raw view is handled below. */ 1041 return builtin_type (gdbarch)->builtin_int32; 1042 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 1043 /* The target, while possibly using a 64-bit register buffer, 1044 is only transfering 32-bits of each integer register. 1045 Reflect this in the cooked/pseudo (ABI) register value. */ 1046 return builtin_type (gdbarch)->builtin_int32; 1047 else if (mips_abi_regsize (gdbarch) == 4) 1048 /* The ABI is restricted to 32-bit registers (the ISA could be 1049 32- or 64-bit). */ 1050 return builtin_type (gdbarch)->builtin_int32; 1051 else 1052 /* 64-bit ABI. */ 1053 return builtin_type (gdbarch)->builtin_int64; 1054 } 1055 } 1056 1057 /* Return the GDB type for the pseudo register REGNUM, which is the 1058 ABI-level view. This function is only called if there is a target 1059 description which includes registers, so we know precisely the 1060 types of hardware registers. */ 1061 1062 static struct type * 1063 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 1064 { 1065 const int num_regs = gdbarch_num_regs (gdbarch); 1066 int rawnum = regnum % num_regs; 1067 struct type *rawtype; 1068 1069 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); 1070 1071 /* Absent registers are still absent. */ 1072 rawtype = gdbarch_register_type (gdbarch, rawnum); 1073 if (TYPE_LENGTH (rawtype) == 0) 1074 return rawtype; 1075 1076 /* Present the floating point registers however the hardware did; 1077 do not try to convert between FPU layouts. */ 1078 if (mips_float_register_p (gdbarch, rawnum)) 1079 return rawtype; 1080 1081 /* Floating-point control registers are always 32-bit even though for 1082 backwards compatibility reasons 64-bit targets will transfer them 1083 as 64-bit quantities even if using XML descriptions. */ 1084 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1085 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1086 return builtin_type (gdbarch)->builtin_int32; 1087 1088 /* Use pointer types for registers if we can. For n32 we can not, 1089 since we do not have a 64-bit pointer type. */ 1090 if (mips_abi_regsize (gdbarch) 1091 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) 1092 { 1093 if (rawnum == MIPS_SP_REGNUM 1094 || rawnum == mips_regnum (gdbarch)->badvaddr) 1095 return builtin_type (gdbarch)->builtin_data_ptr; 1096 else if (rawnum == mips_regnum (gdbarch)->pc) 1097 return builtin_type (gdbarch)->builtin_func_ptr; 1098 } 1099 1100 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 1101 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) 1102 || rawnum == mips_regnum (gdbarch)->lo 1103 || rawnum == mips_regnum (gdbarch)->hi 1104 || rawnum == mips_regnum (gdbarch)->badvaddr 1105 || rawnum == mips_regnum (gdbarch)->cause 1106 || rawnum == mips_regnum (gdbarch)->pc 1107 || (mips_regnum (gdbarch)->dspacc != -1 1108 && rawnum >= mips_regnum (gdbarch)->dspacc 1109 && rawnum < mips_regnum (gdbarch)->dspacc + 6))) 1110 return builtin_type (gdbarch)->builtin_int32; 1111 1112 /* The pseudo/cooked view of embedded registers is always 1113 32-bit, even if the target transfers 64-bit values for them. 1114 New targets relying on XML descriptions should only transfer 1115 the necessary 32 bits, but older versions of GDB expected 64, 1116 so allow the target to provide 64 bits without interfering 1117 with the displayed type. */ 1118 if (gdbarch_osabi (gdbarch) != GDB_OSABI_IRIX 1119 && gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1120 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1121 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1122 return builtin_type (gdbarch)->builtin_int32; 1123 1124 /* For all other registers, pass through the hardware type. */ 1125 return rawtype; 1126 } 1127 1128 /* Should the upper word of 64-bit addresses be zeroed? */ 1129 enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; 1130 1131 static int 1132 mips_mask_address_p (struct gdbarch_tdep *tdep) 1133 { 1134 switch (mask_address_var) 1135 { 1136 case AUTO_BOOLEAN_TRUE: 1137 return 1; 1138 case AUTO_BOOLEAN_FALSE: 1139 return 0; 1140 break; 1141 case AUTO_BOOLEAN_AUTO: 1142 return tdep->default_mask_address_p; 1143 default: 1144 internal_error (__FILE__, __LINE__, 1145 _("mips_mask_address_p: bad switch")); 1146 return -1; 1147 } 1148 } 1149 1150 static void 1151 show_mask_address (struct ui_file *file, int from_tty, 1152 struct cmd_list_element *c, const char *value) 1153 { 1154 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); 1155 1156 deprecated_show_value_hack (file, from_tty, c, value); 1157 switch (mask_address_var) 1158 { 1159 case AUTO_BOOLEAN_TRUE: 1160 printf_filtered ("The 32 bit mips address mask is enabled\n"); 1161 break; 1162 case AUTO_BOOLEAN_FALSE: 1163 printf_filtered ("The 32 bit mips address mask is disabled\n"); 1164 break; 1165 case AUTO_BOOLEAN_AUTO: 1166 printf_filtered 1167 ("The 32 bit address mask is set automatically. Currently %s\n", 1168 mips_mask_address_p (tdep) ? "enabled" : "disabled"); 1169 break; 1170 default: 1171 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); 1172 break; 1173 } 1174 } 1175 1176 /* Tell if the program counter value in MEMADDR is in a standard ISA 1177 function. */ 1178 1179 int 1180 mips_pc_is_mips (CORE_ADDR memaddr) 1181 { 1182 struct bound_minimal_symbol sym; 1183 1184 /* Flags indicating that this is a MIPS16 or microMIPS function is 1185 stored by elfread.c in the high bit of the info field. Use this 1186 to decide if the function is standard MIPS. Otherwise if bit 0 1187 of the address is clear, then this is a standard MIPS function. */ 1188 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1189 if (sym.minsym) 1190 return msymbol_is_mips (sym.minsym); 1191 else 1192 return is_mips_addr (memaddr); 1193 } 1194 1195 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ 1196 1197 int 1198 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1199 { 1200 struct bound_minimal_symbol sym; 1201 1202 /* A flag indicating that this is a MIPS16 function is stored by 1203 elfread.c in the high bit of the info field. Use this to decide 1204 if the function is MIPS16. Otherwise if bit 0 of the address is 1205 set, then ELF file flags will tell if this is a MIPS16 function. */ 1206 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1207 if (sym.minsym) 1208 return msymbol_is_mips16 (sym.minsym); 1209 else 1210 return is_mips16_addr (gdbarch, memaddr); 1211 } 1212 1213 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ 1214 1215 int 1216 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1217 { 1218 struct bound_minimal_symbol sym; 1219 1220 /* A flag indicating that this is a microMIPS function is stored by 1221 elfread.c in the high bit of the info field. Use this to decide 1222 if the function is microMIPS. Otherwise if bit 0 of the address 1223 is set, then ELF file flags will tell if this is a microMIPS 1224 function. */ 1225 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1226 if (sym.minsym) 1227 return msymbol_is_micromips (sym.minsym); 1228 else 1229 return is_micromips_addr (gdbarch, memaddr); 1230 } 1231 1232 /* Tell the ISA type of the function the program counter value in MEMADDR 1233 is in. */ 1234 1235 static enum mips_isa 1236 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1237 { 1238 struct bound_minimal_symbol sym; 1239 1240 /* A flag indicating that this is a MIPS16 or a microMIPS function 1241 is stored by elfread.c in the high bit of the info field. Use 1242 this to decide if the function is MIPS16 or microMIPS or normal 1243 MIPS. Otherwise if bit 0 of the address is set, then ELF file 1244 flags will tell if this is a MIPS16 or a microMIPS function. */ 1245 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1246 if (sym.minsym) 1247 { 1248 if (msymbol_is_micromips (sym.minsym)) 1249 return ISA_MICROMIPS; 1250 else if (msymbol_is_mips16 (sym.minsym)) 1251 return ISA_MIPS16; 1252 else 1253 return ISA_MIPS; 1254 } 1255 else 1256 { 1257 if (is_mips_addr (memaddr)) 1258 return ISA_MIPS; 1259 else if (is_micromips_addr (gdbarch, memaddr)) 1260 return ISA_MICROMIPS; 1261 else 1262 return ISA_MIPS16; 1263 } 1264 } 1265 1266 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. 1267 The need for comes from the ISA bit having been cleared, making 1268 addresses in FDE, range records, etc. referring to compressed code 1269 different to those in line information, the symbol table and finally 1270 the PC register. That in turn confuses many operations. */ 1271 1272 static CORE_ADDR 1273 mips_adjust_dwarf2_addr (CORE_ADDR pc) 1274 { 1275 pc = unmake_compact_addr (pc); 1276 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); 1277 } 1278 1279 /* Recalculate the line record requested so that the resulting PC has 1280 the ISA bit set correctly, used by DWARF-2 machinery. The need for 1281 this adjustment comes from some records associated with compressed 1282 code having the ISA bit cleared, most notably at function prologue 1283 ends. The ISA bit is in this context retrieved from the minimal 1284 symbol covering the address requested, which in turn has been 1285 constructed from the binary's symbol table rather than DWARF-2 1286 information. The correct setting of the ISA bit is required for 1287 breakpoint addresses to correctly match against the stop PC. 1288 1289 As line entries can specify relative address adjustments we need to 1290 keep track of the absolute value of the last line address recorded 1291 in line information, so that we can calculate the actual address to 1292 apply the ISA bit adjustment to. We use PC for this tracking and 1293 keep the original address there. 1294 1295 As such relative address adjustments can be odd within compressed 1296 code we need to keep track of the last line address with the ISA 1297 bit adjustment applied too, as the original address may or may not 1298 have had the ISA bit set. We use ADJ_PC for this tracking and keep 1299 the adjusted address there. 1300 1301 For relative address adjustments we then use these variables to 1302 calculate the address intended by line information, which will be 1303 PC-relative, and return an updated adjustment carrying ISA bit 1304 information, which will be ADJ_PC-relative. For absolute address 1305 adjustments we just return the same address that we store in ADJ_PC 1306 too. 1307 1308 As the first line entry can be relative to an implied address value 1309 of 0 we need to have the initial address set up that we store in PC 1310 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' 1311 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ 1312 1313 static CORE_ADDR 1314 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) 1315 { 1316 static CORE_ADDR adj_pc; 1317 static CORE_ADDR pc; 1318 CORE_ADDR isa_pc; 1319 1320 pc = rel ? pc + addr : addr; 1321 isa_pc = mips_adjust_dwarf2_addr (pc); 1322 addr = rel ? isa_pc - adj_pc : isa_pc; 1323 adj_pc = isa_pc; 1324 return addr; 1325 } 1326 1327 /* Various MIPS16 thunk (aka stub or trampoline) names. */ 1328 1329 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; 1330 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; 1331 static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; 1332 static const char mips_str_call_stub[] = "__call_stub_"; 1333 static const char mips_str_fn_stub[] = "__fn_stub_"; 1334 1335 /* This is used as a PIC thunk prefix. */ 1336 1337 static const char mips_str_pic[] = ".pic."; 1338 1339 /* Return non-zero if the PC is inside a call thunk (aka stub or 1340 trampoline) that should be treated as a temporary frame. */ 1341 1342 static int 1343 mips_in_frame_stub (CORE_ADDR pc) 1344 { 1345 CORE_ADDR start_addr; 1346 const char *name; 1347 1348 /* Find the starting address of the function containing the PC. */ 1349 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 1350 return 0; 1351 1352 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ 1353 if (startswith (name, mips_str_mips16_call_stub)) 1354 return 1; 1355 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ 1356 if (startswith (name, mips_str_call_stub)) 1357 return 1; 1358 /* If the PC is in __fn_stub_*, this is a call stub. */ 1359 if (startswith (name, mips_str_fn_stub)) 1360 return 1; 1361 1362 return 0; /* Not a stub. */ 1363 } 1364 1365 /* MIPS believes that the PC has a sign extended value. Perhaps the 1366 all registers should be sign extended for simplicity? */ 1367 1368 static CORE_ADDR 1369 mips_read_pc (struct regcache *regcache) 1370 { 1371 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); 1372 LONGEST pc; 1373 1374 regcache_cooked_read_signed (regcache, regnum, &pc); 1375 return pc; 1376 } 1377 1378 static CORE_ADDR 1379 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1380 { 1381 CORE_ADDR pc; 1382 1383 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); 1384 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as 1385 intermediate frames. In this case we can get the caller's address 1386 from $ra, or if $ra contains an address within a thunk as well, then 1387 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} 1388 and thus the caller's address is in $s2. */ 1389 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) 1390 { 1391 pc = frame_unwind_register_signed 1392 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 1393 if (mips_in_frame_stub (pc)) 1394 pc = frame_unwind_register_signed 1395 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 1396 } 1397 return pc; 1398 } 1399 1400 static CORE_ADDR 1401 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1402 { 1403 return frame_unwind_register_signed 1404 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); 1405 } 1406 1407 /* Assuming THIS_FRAME is a dummy, return the frame ID of that 1408 dummy frame. The frame ID's base needs to match the TOS value 1409 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1410 breakpoint. */ 1411 1412 static struct frame_id 1413 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1414 { 1415 return frame_id_build 1416 (get_frame_register_signed (this_frame, 1417 gdbarch_num_regs (gdbarch) 1418 + MIPS_SP_REGNUM), 1419 get_frame_pc (this_frame)); 1420 } 1421 1422 /* Implement the "write_pc" gdbarch method. */ 1423 1424 void 1425 mips_write_pc (struct regcache *regcache, CORE_ADDR pc) 1426 { 1427 int regnum = gdbarch_pc_regnum (get_regcache_arch (regcache)); 1428 1429 regcache_cooked_write_unsigned (regcache, regnum, pc); 1430 } 1431 1432 /* Fetch and return instruction from the specified location. Handle 1433 MIPS16/microMIPS as appropriate. */ 1434 1435 static ULONGEST 1436 mips_fetch_instruction (struct gdbarch *gdbarch, 1437 enum mips_isa isa, CORE_ADDR addr, int *errp) 1438 { 1439 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1440 gdb_byte buf[MIPS_INSN32_SIZE]; 1441 int instlen; 1442 int err; 1443 1444 switch (isa) 1445 { 1446 case ISA_MICROMIPS: 1447 case ISA_MIPS16: 1448 instlen = MIPS_INSN16_SIZE; 1449 addr = unmake_compact_addr (addr); 1450 break; 1451 case ISA_MIPS: 1452 instlen = MIPS_INSN32_SIZE; 1453 break; 1454 default: 1455 internal_error (__FILE__, __LINE__, _("invalid ISA")); 1456 break; 1457 } 1458 err = target_read_memory (addr, buf, instlen); 1459 if (errp != NULL) 1460 *errp = err; 1461 if (err != 0) 1462 { 1463 if (errp == NULL) 1464 memory_error (TARGET_XFER_E_IO, addr); 1465 return 0; 1466 } 1467 return extract_unsigned_integer (buf, instlen, byte_order); 1468 } 1469 1470 /* These are the fields of 32 bit mips instructions. */ 1471 #define mips32_op(x) (x >> 26) 1472 #define itype_op(x) (x >> 26) 1473 #define itype_rs(x) ((x >> 21) & 0x1f) 1474 #define itype_rt(x) ((x >> 16) & 0x1f) 1475 #define itype_immediate(x) (x & 0xffff) 1476 1477 #define jtype_op(x) (x >> 26) 1478 #define jtype_target(x) (x & 0x03ffffff) 1479 1480 #define rtype_op(x) (x >> 26) 1481 #define rtype_rs(x) ((x >> 21) & 0x1f) 1482 #define rtype_rt(x) ((x >> 16) & 0x1f) 1483 #define rtype_rd(x) ((x >> 11) & 0x1f) 1484 #define rtype_shamt(x) ((x >> 6) & 0x1f) 1485 #define rtype_funct(x) (x & 0x3f) 1486 1487 /* MicroMIPS instruction fields. */ 1488 #define micromips_op(x) ((x) >> 10) 1489 1490 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest 1491 bit and the size respectively of the field extracted. */ 1492 #define b0s4_imm(x) ((x) & 0xf) 1493 #define b0s5_imm(x) ((x) & 0x1f) 1494 #define b0s5_reg(x) ((x) & 0x1f) 1495 #define b0s7_imm(x) ((x) & 0x7f) 1496 #define b0s10_imm(x) ((x) & 0x3ff) 1497 #define b1s4_imm(x) (((x) >> 1) & 0xf) 1498 #define b1s9_imm(x) (((x) >> 1) & 0x1ff) 1499 #define b2s3_cc(x) (((x) >> 2) & 0x7) 1500 #define b4s2_regl(x) (((x) >> 4) & 0x3) 1501 #define b5s5_op(x) (((x) >> 5) & 0x1f) 1502 #define b5s5_reg(x) (((x) >> 5) & 0x1f) 1503 #define b6s4_op(x) (((x) >> 6) & 0xf) 1504 #define b7s3_reg(x) (((x) >> 7) & 0x7) 1505 1506 /* 32-bit instruction formats, B and S refer to the lowest bit and the size 1507 respectively of the field extracted. */ 1508 #define b0s6_op(x) ((x) & 0x3f) 1509 #define b0s11_op(x) ((x) & 0x7ff) 1510 #define b0s12_imm(x) ((x) & 0xfff) 1511 #define b0s16_imm(x) ((x) & 0xffff) 1512 #define b0s26_imm(x) ((x) & 0x3ffffff) 1513 #define b6s10_ext(x) (((x) >> 6) & 0x3ff) 1514 #define b11s5_reg(x) (((x) >> 11) & 0x1f) 1515 #define b12s4_op(x) (((x) >> 12) & 0xf) 1516 1517 /* Return the size in bytes of the instruction INSN encoded in the ISA 1518 instruction set. */ 1519 1520 static int 1521 mips_insn_size (enum mips_isa isa, ULONGEST insn) 1522 { 1523 switch (isa) 1524 { 1525 case ISA_MICROMIPS: 1526 if ((micromips_op (insn) & 0x4) == 0x4 1527 || (micromips_op (insn) & 0x7) == 0x0) 1528 return 2 * MIPS_INSN16_SIZE; 1529 else 1530 return MIPS_INSN16_SIZE; 1531 case ISA_MIPS16: 1532 if ((insn & 0xf800) == 0xf000) 1533 return 2 * MIPS_INSN16_SIZE; 1534 else 1535 return MIPS_INSN16_SIZE; 1536 case ISA_MIPS: 1537 return MIPS_INSN32_SIZE; 1538 } 1539 internal_error (__FILE__, __LINE__, _("invalid ISA")); 1540 } 1541 1542 static LONGEST 1543 mips32_relative_offset (ULONGEST inst) 1544 { 1545 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; 1546 } 1547 1548 /* Determine the address of the next instruction executed after the INST 1549 floating condition branch instruction at PC. COUNT specifies the 1550 number of the floating condition bits tested by the branch. */ 1551 1552 static CORE_ADDR 1553 mips32_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, 1554 ULONGEST inst, CORE_ADDR pc, int count) 1555 { 1556 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1557 int cnum = (itype_rt (inst) >> 2) & (count - 1); 1558 int tf = itype_rt (inst) & 1; 1559 int mask = (1 << count) - 1; 1560 ULONGEST fcs; 1561 int cond; 1562 1563 if (fcsr == -1) 1564 /* No way to handle; it'll most likely trap anyway. */ 1565 return pc; 1566 1567 fcs = get_frame_register_unsigned (frame, fcsr); 1568 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1569 1570 if (((cond >> cnum) & mask) != mask * !tf) 1571 pc += mips32_relative_offset (inst); 1572 else 1573 pc += 4; 1574 1575 return pc; 1576 } 1577 1578 /* Return nonzero if the gdbarch is an Octeon series. */ 1579 1580 static int 1581 is_octeon (struct gdbarch *gdbarch) 1582 { 1583 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); 1584 1585 return (info->mach == bfd_mach_mips_octeon 1586 || info->mach == bfd_mach_mips_octeonp 1587 || info->mach == bfd_mach_mips_octeon2); 1588 } 1589 1590 /* Return true if the OP represents the Octeon's BBIT instruction. */ 1591 1592 static int 1593 is_octeon_bbit_op (int op, struct gdbarch *gdbarch) 1594 { 1595 if (!is_octeon (gdbarch)) 1596 return 0; 1597 /* BBIT0 is encoded as LWC2: 110 010. */ 1598 /* BBIT032 is encoded as LDC2: 110 110. */ 1599 /* BBIT1 is encoded as SWC2: 111 010. */ 1600 /* BBIT132 is encoded as SDC2: 111 110. */ 1601 if (op == 50 || op == 54 || op == 58 || op == 62) 1602 return 1; 1603 return 0; 1604 } 1605 1606 1607 /* Determine where to set a single step breakpoint while considering 1608 branch prediction. */ 1609 1610 static CORE_ADDR 1611 mips32_next_pc (struct frame_info *frame, CORE_ADDR pc) 1612 { 1613 struct gdbarch *gdbarch = get_frame_arch (frame); 1614 unsigned long inst; 1615 int op; 1616 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 1617 op = itype_op (inst); 1618 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch 1619 instruction. */ 1620 { 1621 if (op >> 2 == 5) 1622 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 1623 { 1624 switch (op & 0x03) 1625 { 1626 case 0: /* BEQL */ 1627 goto equal_branch; 1628 case 1: /* BNEL */ 1629 goto neq_branch; 1630 case 2: /* BLEZL */ 1631 goto less_branch; 1632 case 3: /* BGTZL */ 1633 goto greater_branch; 1634 default: 1635 pc += 4; 1636 } 1637 } 1638 else if (op == 17 && itype_rs (inst) == 8) 1639 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 1640 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 1); 1641 else if (op == 17 && itype_rs (inst) == 9 1642 && (itype_rt (inst) & 2) == 0) 1643 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ 1644 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 2); 1645 else if (op == 17 && itype_rs (inst) == 10 1646 && (itype_rt (inst) & 2) == 0) 1647 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ 1648 pc = mips32_bc1_pc (gdbarch, frame, inst, pc + 4, 4); 1649 else if (op == 29) 1650 /* JALX: 011101 */ 1651 /* The new PC will be alternate mode. */ 1652 { 1653 unsigned long reg; 1654 1655 reg = jtype_target (inst) << 2; 1656 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ 1657 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; 1658 } 1659 else if (is_octeon_bbit_op (op, gdbarch)) 1660 { 1661 int bit, branch_if; 1662 1663 branch_if = op == 58 || op == 62; 1664 bit = itype_rt (inst); 1665 1666 /* Take into account the *32 instructions. */ 1667 if (op == 54 || op == 62) 1668 bit += 32; 1669 1670 if (((get_frame_register_signed (frame, 1671 itype_rs (inst)) >> bit) & 1) 1672 == branch_if) 1673 pc += mips32_relative_offset (inst) + 4; 1674 else 1675 pc += 8; /* After the delay slot. */ 1676 } 1677 1678 else 1679 pc += 4; /* Not a branch, next instruction is easy. */ 1680 } 1681 else 1682 { /* This gets way messy. */ 1683 1684 /* Further subdivide into SPECIAL, REGIMM and other. */ 1685 switch (op & 0x07) /* Extract bits 28,27,26. */ 1686 { 1687 case 0: /* SPECIAL */ 1688 op = rtype_funct (inst); 1689 switch (op) 1690 { 1691 case 8: /* JR */ 1692 case 9: /* JALR */ 1693 /* Set PC to that address. */ 1694 pc = get_frame_register_signed (frame, rtype_rs (inst)); 1695 break; 1696 case 12: /* SYSCALL */ 1697 { 1698 struct gdbarch_tdep *tdep; 1699 1700 tdep = gdbarch_tdep (get_frame_arch (frame)); 1701 if (tdep->syscall_next_pc != NULL) 1702 pc = tdep->syscall_next_pc (frame); 1703 else 1704 pc += 4; 1705 } 1706 break; 1707 default: 1708 pc += 4; 1709 } 1710 1711 break; /* end SPECIAL */ 1712 case 1: /* REGIMM */ 1713 { 1714 op = itype_rt (inst); /* branch condition */ 1715 switch (op) 1716 { 1717 case 0: /* BLTZ */ 1718 case 2: /* BLTZL */ 1719 case 16: /* BLTZAL */ 1720 case 18: /* BLTZALL */ 1721 less_branch: 1722 if (get_frame_register_signed (frame, itype_rs (inst)) < 0) 1723 pc += mips32_relative_offset (inst) + 4; 1724 else 1725 pc += 8; /* after the delay slot */ 1726 break; 1727 case 1: /* BGEZ */ 1728 case 3: /* BGEZL */ 1729 case 17: /* BGEZAL */ 1730 case 19: /* BGEZALL */ 1731 if (get_frame_register_signed (frame, itype_rs (inst)) >= 0) 1732 pc += mips32_relative_offset (inst) + 4; 1733 else 1734 pc += 8; /* after the delay slot */ 1735 break; 1736 case 0x1c: /* BPOSGE32 */ 1737 case 0x1e: /* BPOSGE64 */ 1738 pc += 4; 1739 if (itype_rs (inst) == 0) 1740 { 1741 unsigned int pos = (op & 2) ? 64 : 32; 1742 int dspctl = mips_regnum (gdbarch)->dspctl; 1743 1744 if (dspctl == -1) 1745 /* No way to handle; it'll most likely trap anyway. */ 1746 break; 1747 1748 if ((get_frame_register_unsigned (frame, 1749 dspctl) & 0x7f) >= pos) 1750 pc += mips32_relative_offset (inst); 1751 else 1752 pc += 4; 1753 } 1754 break; 1755 /* All of the other instructions in the REGIMM category */ 1756 default: 1757 pc += 4; 1758 } 1759 } 1760 break; /* end REGIMM */ 1761 case 2: /* J */ 1762 case 3: /* JAL */ 1763 { 1764 unsigned long reg; 1765 reg = jtype_target (inst) << 2; 1766 /* Upper four bits get never changed... */ 1767 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 1768 } 1769 break; 1770 case 4: /* BEQ, BEQL */ 1771 equal_branch: 1772 if (get_frame_register_signed (frame, itype_rs (inst)) == 1773 get_frame_register_signed (frame, itype_rt (inst))) 1774 pc += mips32_relative_offset (inst) + 4; 1775 else 1776 pc += 8; 1777 break; 1778 case 5: /* BNE, BNEL */ 1779 neq_branch: 1780 if (get_frame_register_signed (frame, itype_rs (inst)) != 1781 get_frame_register_signed (frame, itype_rt (inst))) 1782 pc += mips32_relative_offset (inst) + 4; 1783 else 1784 pc += 8; 1785 break; 1786 case 6: /* BLEZ, BLEZL */ 1787 if (get_frame_register_signed (frame, itype_rs (inst)) <= 0) 1788 pc += mips32_relative_offset (inst) + 4; 1789 else 1790 pc += 8; 1791 break; 1792 case 7: 1793 default: 1794 greater_branch: /* BGTZ, BGTZL */ 1795 if (get_frame_register_signed (frame, itype_rs (inst)) > 0) 1796 pc += mips32_relative_offset (inst) + 4; 1797 else 1798 pc += 8; 1799 break; 1800 } /* switch */ 1801 } /* else */ 1802 return pc; 1803 } /* mips32_next_pc */ 1804 1805 /* Extract the 7-bit signed immediate offset from the microMIPS instruction 1806 INSN. */ 1807 1808 static LONGEST 1809 micromips_relative_offset7 (ULONGEST insn) 1810 { 1811 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; 1812 } 1813 1814 /* Extract the 10-bit signed immediate offset from the microMIPS instruction 1815 INSN. */ 1816 1817 static LONGEST 1818 micromips_relative_offset10 (ULONGEST insn) 1819 { 1820 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; 1821 } 1822 1823 /* Extract the 16-bit signed immediate offset from the microMIPS instruction 1824 INSN. */ 1825 1826 static LONGEST 1827 micromips_relative_offset16 (ULONGEST insn) 1828 { 1829 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; 1830 } 1831 1832 /* Return the size in bytes of the microMIPS instruction at the address PC. */ 1833 1834 static int 1835 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) 1836 { 1837 ULONGEST insn; 1838 1839 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1840 return mips_insn_size (ISA_MICROMIPS, insn); 1841 } 1842 1843 /* Calculate the address of the next microMIPS instruction to execute 1844 after the INSN coprocessor 1 conditional branch instruction at the 1845 address PC. COUNT denotes the number of coprocessor condition bits 1846 examined by the branch. */ 1847 1848 static CORE_ADDR 1849 micromips_bc1_pc (struct gdbarch *gdbarch, struct frame_info *frame, 1850 ULONGEST insn, CORE_ADDR pc, int count) 1851 { 1852 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1853 int cnum = b2s3_cc (insn >> 16) & (count - 1); 1854 int tf = b5s5_op (insn >> 16) & 1; 1855 int mask = (1 << count) - 1; 1856 ULONGEST fcs; 1857 int cond; 1858 1859 if (fcsr == -1) 1860 /* No way to handle; it'll most likely trap anyway. */ 1861 return pc; 1862 1863 fcs = get_frame_register_unsigned (frame, fcsr); 1864 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1865 1866 if (((cond >> cnum) & mask) != mask * !tf) 1867 pc += micromips_relative_offset16 (insn); 1868 else 1869 pc += micromips_pc_insn_size (gdbarch, pc); 1870 1871 return pc; 1872 } 1873 1874 /* Calculate the address of the next microMIPS instruction to execute 1875 after the instruction at the address PC. */ 1876 1877 static CORE_ADDR 1878 micromips_next_pc (struct frame_info *frame, CORE_ADDR pc) 1879 { 1880 struct gdbarch *gdbarch = get_frame_arch (frame); 1881 ULONGEST insn; 1882 1883 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1884 pc += MIPS_INSN16_SIZE; 1885 switch (mips_insn_size (ISA_MICROMIPS, insn)) 1886 { 1887 /* 32-bit instructions. */ 1888 case 2 * MIPS_INSN16_SIZE: 1889 insn <<= 16; 1890 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1891 pc += MIPS_INSN16_SIZE; 1892 switch (micromips_op (insn >> 16)) 1893 { 1894 case 0x00: /* POOL32A: bits 000000 */ 1895 if (b0s6_op (insn) == 0x3c 1896 /* POOL32Axf: bits 000000 ... 111100 */ 1897 && (b6s10_ext (insn) & 0x2bf) == 0x3c) 1898 /* JALR, JALR.HB: 000000 000x111100 111100 */ 1899 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 1900 pc = get_frame_register_signed (frame, b0s5_reg (insn >> 16)); 1901 break; 1902 1903 case 0x10: /* POOL32I: bits 010000 */ 1904 switch (b5s5_op (insn >> 16)) 1905 { 1906 case 0x00: /* BLTZ: bits 010000 00000 */ 1907 case 0x01: /* BLTZAL: bits 010000 00001 */ 1908 case 0x11: /* BLTZALS: bits 010000 10001 */ 1909 if (get_frame_register_signed (frame, 1910 b0s5_reg (insn >> 16)) < 0) 1911 pc += micromips_relative_offset16 (insn); 1912 else 1913 pc += micromips_pc_insn_size (gdbarch, pc); 1914 break; 1915 1916 case 0x02: /* BGEZ: bits 010000 00010 */ 1917 case 0x03: /* BGEZAL: bits 010000 00011 */ 1918 case 0x13: /* BGEZALS: bits 010000 10011 */ 1919 if (get_frame_register_signed (frame, 1920 b0s5_reg (insn >> 16)) >= 0) 1921 pc += micromips_relative_offset16 (insn); 1922 else 1923 pc += micromips_pc_insn_size (gdbarch, pc); 1924 break; 1925 1926 case 0x04: /* BLEZ: bits 010000 00100 */ 1927 if (get_frame_register_signed (frame, 1928 b0s5_reg (insn >> 16)) <= 0) 1929 pc += micromips_relative_offset16 (insn); 1930 else 1931 pc += micromips_pc_insn_size (gdbarch, pc); 1932 break; 1933 1934 case 0x05: /* BNEZC: bits 010000 00101 */ 1935 if (get_frame_register_signed (frame, 1936 b0s5_reg (insn >> 16)) != 0) 1937 pc += micromips_relative_offset16 (insn); 1938 break; 1939 1940 case 0x06: /* BGTZ: bits 010000 00110 */ 1941 if (get_frame_register_signed (frame, 1942 b0s5_reg (insn >> 16)) > 0) 1943 pc += micromips_relative_offset16 (insn); 1944 else 1945 pc += micromips_pc_insn_size (gdbarch, pc); 1946 break; 1947 1948 case 0x07: /* BEQZC: bits 010000 00111 */ 1949 if (get_frame_register_signed (frame, 1950 b0s5_reg (insn >> 16)) == 0) 1951 pc += micromips_relative_offset16 (insn); 1952 break; 1953 1954 case 0x14: /* BC2F: bits 010000 10100 xxx00 */ 1955 case 0x15: /* BC2T: bits 010000 10101 xxx00 */ 1956 if (((insn >> 16) & 0x3) == 0x0) 1957 /* BC2F, BC2T: don't know how to handle these. */ 1958 break; 1959 break; 1960 1961 case 0x1a: /* BPOSGE64: bits 010000 11010 */ 1962 case 0x1b: /* BPOSGE32: bits 010000 11011 */ 1963 { 1964 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; 1965 int dspctl = mips_regnum (gdbarch)->dspctl; 1966 1967 if (dspctl == -1) 1968 /* No way to handle; it'll most likely trap anyway. */ 1969 break; 1970 1971 if ((get_frame_register_unsigned (frame, 1972 dspctl) & 0x7f) >= pos) 1973 pc += micromips_relative_offset16 (insn); 1974 else 1975 pc += micromips_pc_insn_size (gdbarch, pc); 1976 } 1977 break; 1978 1979 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ 1980 /* BC1ANY2F: bits 010000 11100 xxx01 */ 1981 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ 1982 /* BC1ANY2T: bits 010000 11101 xxx01 */ 1983 if (((insn >> 16) & 0x2) == 0x0) 1984 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 1985 ((insn >> 16) & 0x1) + 1); 1986 break; 1987 1988 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ 1989 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ 1990 if (((insn >> 16) & 0x3) == 0x1) 1991 pc = micromips_bc1_pc (gdbarch, frame, insn, pc, 4); 1992 break; 1993 } 1994 break; 1995 1996 case 0x1d: /* JALS: bits 011101 */ 1997 case 0x35: /* J: bits 110101 */ 1998 case 0x3d: /* JAL: bits 111101 */ 1999 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); 2000 break; 2001 2002 case 0x25: /* BEQ: bits 100101 */ 2003 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) 2004 == get_frame_register_signed (frame, b5s5_reg (insn >> 16))) 2005 pc += micromips_relative_offset16 (insn); 2006 else 2007 pc += micromips_pc_insn_size (gdbarch, pc); 2008 break; 2009 2010 case 0x2d: /* BNE: bits 101101 */ 2011 if (get_frame_register_signed (frame, b0s5_reg (insn >> 16)) 2012 != get_frame_register_signed (frame, b5s5_reg (insn >> 16))) 2013 pc += micromips_relative_offset16 (insn); 2014 else 2015 pc += micromips_pc_insn_size (gdbarch, pc); 2016 break; 2017 2018 case 0x3c: /* JALX: bits 111100 */ 2019 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); 2020 break; 2021 } 2022 break; 2023 2024 /* 16-bit instructions. */ 2025 case MIPS_INSN16_SIZE: 2026 switch (micromips_op (insn)) 2027 { 2028 case 0x11: /* POOL16C: bits 010001 */ 2029 if ((b5s5_op (insn) & 0x1c) == 0xc) 2030 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 2031 pc = get_frame_register_signed (frame, b0s5_reg (insn)); 2032 else if (b5s5_op (insn) == 0x18) 2033 /* JRADDIUSP: bits 010001 11000 */ 2034 pc = get_frame_register_signed (frame, MIPS_RA_REGNUM); 2035 break; 2036 2037 case 0x23: /* BEQZ16: bits 100011 */ 2038 { 2039 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2040 2041 if (get_frame_register_signed (frame, rs) == 0) 2042 pc += micromips_relative_offset7 (insn); 2043 else 2044 pc += micromips_pc_insn_size (gdbarch, pc); 2045 } 2046 break; 2047 2048 case 0x2b: /* BNEZ16: bits 101011 */ 2049 { 2050 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2051 2052 if (get_frame_register_signed (frame, rs) != 0) 2053 pc += micromips_relative_offset7 (insn); 2054 else 2055 pc += micromips_pc_insn_size (gdbarch, pc); 2056 } 2057 break; 2058 2059 case 0x33: /* B16: bits 110011 */ 2060 pc += micromips_relative_offset10 (insn); 2061 break; 2062 } 2063 break; 2064 } 2065 2066 return pc; 2067 } 2068 2069 /* Decoding the next place to set a breakpoint is irregular for the 2070 mips 16 variant, but fortunately, there fewer instructions. We have 2071 to cope ith extensions for 16 bit instructions and a pair of actual 2072 32 bit instructions. We dont want to set a single step instruction 2073 on the extend instruction either. */ 2074 2075 /* Lots of mips16 instruction formats */ 2076 /* Predicting jumps requires itype,ritype,i8type 2077 and their extensions extItype,extritype,extI8type. */ 2078 enum mips16_inst_fmts 2079 { 2080 itype, /* 0 immediate 5,10 */ 2081 ritype, /* 1 5,3,8 */ 2082 rrtype, /* 2 5,3,3,5 */ 2083 rritype, /* 3 5,3,3,5 */ 2084 rrrtype, /* 4 5,3,3,3,2 */ 2085 rriatype, /* 5 5,3,3,1,4 */ 2086 shifttype, /* 6 5,3,3,3,2 */ 2087 i8type, /* 7 5,3,8 */ 2088 i8movtype, /* 8 5,3,3,5 */ 2089 i8mov32rtype, /* 9 5,3,5,3 */ 2090 i64type, /* 10 5,3,8 */ 2091 ri64type, /* 11 5,3,3,5 */ 2092 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ 2093 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ 2094 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ 2095 extRRItype, /* 15 5,5,5,5,3,3,5 */ 2096 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ 2097 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ 2098 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ 2099 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ 2100 extRi64type, /* 20 5,6,5,5,3,3,5 */ 2101 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ 2102 }; 2103 /* I am heaping all the fields of the formats into one structure and 2104 then, only the fields which are involved in instruction extension. */ 2105 struct upk_mips16 2106 { 2107 CORE_ADDR offset; 2108 unsigned int regx; /* Function in i8 type. */ 2109 unsigned int regy; 2110 }; 2111 2112 2113 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format 2114 for the bits which make up the immediate extension. */ 2115 2116 static CORE_ADDR 2117 extended_offset (unsigned int extension) 2118 { 2119 CORE_ADDR value; 2120 2121 value = (extension >> 16) & 0x1f; /* Extract 15:11. */ 2122 value = value << 6; 2123 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ 2124 value = value << 5; 2125 value |= extension & 0x1f; /* Extract 4:0. */ 2126 2127 return value; 2128 } 2129 2130 /* Only call this function if you know that this is an extendable 2131 instruction. It won't malfunction, but why make excess remote memory 2132 references? If the immediate operands get sign extended or something, 2133 do it after the extension is performed. */ 2134 /* FIXME: Every one of these cases needs to worry about sign extension 2135 when the offset is to be used in relative addressing. */ 2136 2137 static unsigned int 2138 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) 2139 { 2140 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2141 gdb_byte buf[8]; 2142 2143 pc = unmake_compact_addr (pc); /* Clear the low order bit. */ 2144 target_read_memory (pc, buf, 2); 2145 return extract_unsigned_integer (buf, 2, byte_order); 2146 } 2147 2148 static void 2149 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, 2150 unsigned int extension, 2151 unsigned int inst, 2152 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) 2153 { 2154 CORE_ADDR offset; 2155 int regx; 2156 int regy; 2157 switch (insn_format) 2158 { 2159 case itype: 2160 { 2161 CORE_ADDR value; 2162 if (extension) 2163 { 2164 value = extended_offset ((extension << 16) | inst); 2165 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2166 } 2167 else 2168 { 2169 value = inst & 0x7ff; 2170 value = (value ^ 0x400) - 0x400; /* Sign-extend. */ 2171 } 2172 offset = value; 2173 regx = -1; 2174 regy = -1; 2175 } 2176 break; 2177 case ritype: 2178 case i8type: 2179 { /* A register identifier and an offset. */ 2180 /* Most of the fields are the same as I type but the 2181 immediate value is of a different length. */ 2182 CORE_ADDR value; 2183 if (extension) 2184 { 2185 value = extended_offset ((extension << 16) | inst); 2186 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2187 } 2188 else 2189 { 2190 value = inst & 0xff; /* 8 bits */ 2191 value = (value ^ 0x80) - 0x80; /* Sign-extend. */ 2192 } 2193 offset = value; 2194 regx = (inst >> 8) & 0x07; /* i8 funct */ 2195 regy = -1; 2196 break; 2197 } 2198 case jalxtype: 2199 { 2200 unsigned long value; 2201 unsigned int nexthalf; 2202 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); 2203 value = value << 16; 2204 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); 2205 /* Low bit still set. */ 2206 value |= nexthalf; 2207 offset = value; 2208 regx = -1; 2209 regy = -1; 2210 break; 2211 } 2212 default: 2213 internal_error (__FILE__, __LINE__, _("bad switch")); 2214 } 2215 upk->offset = offset; 2216 upk->regx = regx; 2217 upk->regy = regy; 2218 } 2219 2220 2221 /* Calculate the destination of a branch whose 16-bit opcode word is at PC, 2222 and having a signed 16-bit OFFSET. */ 2223 2224 static CORE_ADDR 2225 add_offset_16 (CORE_ADDR pc, int offset) 2226 { 2227 return pc + (offset << 1) + 2; 2228 } 2229 2230 static CORE_ADDR 2231 extended_mips16_next_pc (struct frame_info *frame, CORE_ADDR pc, 2232 unsigned int extension, unsigned int insn) 2233 { 2234 struct gdbarch *gdbarch = get_frame_arch (frame); 2235 int op = (insn >> 11); 2236 switch (op) 2237 { 2238 case 2: /* Branch */ 2239 { 2240 struct upk_mips16 upk; 2241 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); 2242 pc = add_offset_16 (pc, upk.offset); 2243 break; 2244 } 2245 case 3: /* JAL , JALX - Watch out, these are 32 bit 2246 instructions. */ 2247 { 2248 struct upk_mips16 upk; 2249 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); 2250 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); 2251 if ((insn >> 10) & 0x01) /* Exchange mode */ 2252 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ 2253 else 2254 pc |= 0x01; 2255 break; 2256 } 2257 case 4: /* beqz */ 2258 { 2259 struct upk_mips16 upk; 2260 int reg; 2261 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2262 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); 2263 if (reg == 0) 2264 pc = add_offset_16 (pc, upk.offset); 2265 else 2266 pc += 2; 2267 break; 2268 } 2269 case 5: /* bnez */ 2270 { 2271 struct upk_mips16 upk; 2272 int reg; 2273 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2274 reg = get_frame_register_signed (frame, mips_reg3_to_reg[upk.regx]); 2275 if (reg != 0) 2276 pc = add_offset_16 (pc, upk.offset); 2277 else 2278 pc += 2; 2279 break; 2280 } 2281 case 12: /* I8 Formats btez btnez */ 2282 { 2283 struct upk_mips16 upk; 2284 int reg; 2285 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); 2286 /* upk.regx contains the opcode */ 2287 reg = get_frame_register_signed (frame, 24); /* Test register is 24 */ 2288 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ 2289 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ 2290 pc = add_offset_16 (pc, upk.offset); 2291 else 2292 pc += 2; 2293 break; 2294 } 2295 case 29: /* RR Formats JR, JALR, JALR-RA */ 2296 { 2297 struct upk_mips16 upk; 2298 /* upk.fmt = rrtype; */ 2299 op = insn & 0x1f; 2300 if (op == 0) 2301 { 2302 int reg; 2303 upk.regx = (insn >> 8) & 0x07; 2304 upk.regy = (insn >> 5) & 0x07; 2305 if ((upk.regy & 1) == 0) 2306 reg = mips_reg3_to_reg[upk.regx]; 2307 else 2308 reg = 31; /* Function return instruction. */ 2309 pc = get_frame_register_signed (frame, reg); 2310 } 2311 else 2312 pc += 2; 2313 break; 2314 } 2315 case 30: 2316 /* This is an instruction extension. Fetch the real instruction 2317 (which follows the extension) and decode things based on 2318 that. */ 2319 { 2320 pc += 2; 2321 pc = extended_mips16_next_pc (frame, pc, insn, 2322 fetch_mips_16 (gdbarch, pc)); 2323 break; 2324 } 2325 default: 2326 { 2327 pc += 2; 2328 break; 2329 } 2330 } 2331 return pc; 2332 } 2333 2334 static CORE_ADDR 2335 mips16_next_pc (struct frame_info *frame, CORE_ADDR pc) 2336 { 2337 struct gdbarch *gdbarch = get_frame_arch (frame); 2338 unsigned int insn = fetch_mips_16 (gdbarch, pc); 2339 return extended_mips16_next_pc (frame, pc, 0, insn); 2340 } 2341 2342 /* The mips_next_pc function supports single_step when the remote 2343 target monitor or stub is not developed enough to do a single_step. 2344 It works by decoding the current instruction and predicting where a 2345 branch will go. This isn't hard because all the data is available. 2346 The MIPS32, MIPS16 and microMIPS variants are quite different. */ 2347 static CORE_ADDR 2348 mips_next_pc (struct frame_info *frame, CORE_ADDR pc) 2349 { 2350 struct gdbarch *gdbarch = get_frame_arch (frame); 2351 2352 if (mips_pc_is_mips16 (gdbarch, pc)) 2353 return mips16_next_pc (frame, pc); 2354 else if (mips_pc_is_micromips (gdbarch, pc)) 2355 return micromips_next_pc (frame, pc); 2356 else 2357 return mips32_next_pc (frame, pc); 2358 } 2359 2360 /* Return non-zero if the MIPS16 instruction INSN is a compact branch 2361 or jump. */ 2362 2363 static int 2364 mips16_instruction_is_compact_branch (unsigned short insn) 2365 { 2366 switch (insn & 0xf800) 2367 { 2368 case 0xe800: 2369 return (insn & 0x009f) == 0x80; /* JALRC/JRC */ 2370 case 0x6000: 2371 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ 2372 case 0x2800: /* BNEZ */ 2373 case 0x2000: /* BEQZ */ 2374 case 0x1000: /* B */ 2375 return 1; 2376 default: 2377 return 0; 2378 } 2379 } 2380 2381 /* Return non-zero if the microMIPS instruction INSN is a compact branch 2382 or jump. */ 2383 2384 static int 2385 micromips_instruction_is_compact_branch (unsigned short insn) 2386 { 2387 switch (micromips_op (insn)) 2388 { 2389 case 0x11: /* POOL16C: bits 010001 */ 2390 return (b5s5_op (insn) == 0x18 2391 /* JRADDIUSP: bits 010001 11000 */ 2392 || b5s5_op (insn) == 0xd); 2393 /* JRC: bits 010011 01101 */ 2394 case 0x10: /* POOL32I: bits 010000 */ 2395 return (b5s5_op (insn) & 0x1d) == 0x5; 2396 /* BEQZC/BNEZC: bits 010000 001x1 */ 2397 default: 2398 return 0; 2399 } 2400 } 2401 2402 struct mips_frame_cache 2403 { 2404 CORE_ADDR base; 2405 struct trad_frame_saved_reg *saved_regs; 2406 }; 2407 2408 /* Set a register's saved stack address in temp_saved_regs. If an 2409 address has already been set for this register, do nothing; this 2410 way we will only recognize the first save of a given register in a 2411 function prologue. 2412 2413 For simplicity, save the address in both [0 .. gdbarch_num_regs) and 2414 [gdbarch_num_regs .. 2*gdbarch_num_regs). 2415 Strictly speaking, only the second range is used as it is only second 2416 range (the ABI instead of ISA registers) that comes into play when finding 2417 saved registers in a frame. */ 2418 2419 static void 2420 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, 2421 int regnum, CORE_ADDR offset) 2422 { 2423 if (this_cache != NULL 2424 && this_cache->saved_regs[regnum].addr == -1) 2425 { 2426 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr 2427 = offset; 2428 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr 2429 = offset; 2430 } 2431 } 2432 2433 2434 /* Fetch the immediate value from a MIPS16 instruction. 2435 If the previous instruction was an EXTEND, use it to extend 2436 the upper bits of the immediate value. This is a helper function 2437 for mips16_scan_prologue. */ 2438 2439 static int 2440 mips16_get_imm (unsigned short prev_inst, /* previous instruction */ 2441 unsigned short inst, /* current instruction */ 2442 int nbits, /* number of bits in imm field */ 2443 int scale, /* scale factor to be applied to imm */ 2444 int is_signed) /* is the imm field signed? */ 2445 { 2446 int offset; 2447 2448 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ 2449 { 2450 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); 2451 if (offset & 0x8000) /* check for negative extend */ 2452 offset = 0 - (0x10000 - (offset & 0xffff)); 2453 return offset | (inst & 0x1f); 2454 } 2455 else 2456 { 2457 int max_imm = 1 << nbits; 2458 int mask = max_imm - 1; 2459 int sign_bit = max_imm >> 1; 2460 2461 offset = inst & mask; 2462 if (is_signed && (offset & sign_bit)) 2463 offset = 0 - (max_imm - offset); 2464 return offset * scale; 2465 } 2466 } 2467 2468 2469 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 2470 the associated FRAME_CACHE if not null. 2471 Return the address of the first instruction past the prologue. */ 2472 2473 static CORE_ADDR 2474 mips16_scan_prologue (struct gdbarch *gdbarch, 2475 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2476 struct frame_info *this_frame, 2477 struct mips_frame_cache *this_cache) 2478 { 2479 int prev_non_prologue_insn = 0; 2480 int this_non_prologue_insn; 2481 int non_prologue_insns = 0; 2482 CORE_ADDR prev_pc; 2483 CORE_ADDR cur_pc; 2484 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ 2485 CORE_ADDR sp; 2486 long frame_offset = 0; /* Size of stack frame. */ 2487 long frame_adjust = 0; /* Offset of FP from SP. */ 2488 int frame_reg = MIPS_SP_REGNUM; 2489 unsigned short prev_inst = 0; /* saved copy of previous instruction. */ 2490 unsigned inst = 0; /* current instruction */ 2491 unsigned entry_inst = 0; /* the entry instruction */ 2492 unsigned save_inst = 0; /* the save instruction */ 2493 int prev_delay_slot = 0; 2494 int in_delay_slot; 2495 int reg, offset; 2496 2497 int extend_bytes = 0; 2498 int prev_extend_bytes = 0; 2499 CORE_ADDR end_prologue_addr; 2500 2501 /* Can be called when there's no process, and hence when there's no 2502 THIS_FRAME. */ 2503 if (this_frame != NULL) 2504 sp = get_frame_register_signed (this_frame, 2505 gdbarch_num_regs (gdbarch) 2506 + MIPS_SP_REGNUM); 2507 else 2508 sp = 0; 2509 2510 if (limit_pc > start_pc + 200) 2511 limit_pc = start_pc + 200; 2512 prev_pc = start_pc; 2513 2514 /* Permit at most one non-prologue non-control-transfer instruction 2515 in the middle which may have been reordered by the compiler for 2516 optimisation. */ 2517 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) 2518 { 2519 this_non_prologue_insn = 0; 2520 in_delay_slot = 0; 2521 2522 /* Save the previous instruction. If it's an EXTEND, we'll extract 2523 the immediate offset extension from it in mips16_get_imm. */ 2524 prev_inst = inst; 2525 2526 /* Fetch and decode the instruction. */ 2527 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, 2528 cur_pc, NULL); 2529 2530 /* Normally we ignore extend instructions. However, if it is 2531 not followed by a valid prologue instruction, then this 2532 instruction is not part of the prologue either. We must 2533 remember in this case to adjust the end_prologue_addr back 2534 over the extend. */ 2535 if ((inst & 0xf800) == 0xf000) /* extend */ 2536 { 2537 extend_bytes = MIPS_INSN16_SIZE; 2538 continue; 2539 } 2540 2541 prev_extend_bytes = extend_bytes; 2542 extend_bytes = 0; 2543 2544 if ((inst & 0xff00) == 0x6300 /* addiu sp */ 2545 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 2546 { 2547 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); 2548 if (offset < 0) /* Negative stack adjustment? */ 2549 frame_offset -= offset; 2550 else 2551 /* Exit loop if a positive stack adjustment is found, which 2552 usually means that the stack cleanup code in the function 2553 epilogue is reached. */ 2554 break; 2555 } 2556 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ 2557 { 2558 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2559 reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; 2560 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2561 } 2562 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ 2563 { 2564 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2565 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2566 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2567 } 2568 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ 2569 { 2570 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2571 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2572 } 2573 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ 2574 { 2575 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); 2576 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2577 } 2578 else if (inst == 0x673d) /* move $s1, $sp */ 2579 { 2580 frame_addr = sp; 2581 frame_reg = 17; 2582 } 2583 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ 2584 { 2585 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2586 frame_addr = sp + offset; 2587 frame_reg = 17; 2588 frame_adjust = offset; 2589 } 2590 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ 2591 { 2592 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); 2593 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2594 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2595 } 2596 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ 2597 { 2598 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2599 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2600 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2601 } 2602 else if ((inst & 0xf81f) == 0xe809 2603 && (inst & 0x700) != 0x700) /* entry */ 2604 entry_inst = inst; /* Save for later processing. */ 2605 else if ((inst & 0xff80) == 0x6480) /* save */ 2606 { 2607 save_inst = inst; /* Save for later processing. */ 2608 if (prev_extend_bytes) /* extend */ 2609 save_inst |= prev_inst << 16; 2610 } 2611 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ 2612 { 2613 /* This instruction is part of the prologue, but we don't 2614 need to do anything special to handle it. */ 2615 } 2616 else if (mips16_instruction_has_delay_slot (inst, 0)) 2617 /* JAL/JALR/JALX/JR */ 2618 { 2619 /* The instruction in the delay slot can be a part 2620 of the prologue, so move forward once more. */ 2621 in_delay_slot = 1; 2622 if (mips16_instruction_has_delay_slot (inst, 1)) 2623 /* JAL/JALX */ 2624 { 2625 prev_extend_bytes = MIPS_INSN16_SIZE; 2626 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ 2627 } 2628 } 2629 else 2630 { 2631 this_non_prologue_insn = 1; 2632 } 2633 2634 non_prologue_insns += this_non_prologue_insn; 2635 2636 /* A jump or branch, or enough non-prologue insns seen? If so, 2637 then we must have reached the end of the prologue by now. */ 2638 if (prev_delay_slot || non_prologue_insns > 1 2639 || mips16_instruction_is_compact_branch (inst)) 2640 break; 2641 2642 prev_non_prologue_insn = this_non_prologue_insn; 2643 prev_delay_slot = in_delay_slot; 2644 prev_pc = cur_pc - prev_extend_bytes; 2645 } 2646 2647 /* The entry instruction is typically the first instruction in a function, 2648 and it stores registers at offsets relative to the value of the old SP 2649 (before the prologue). But the value of the sp parameter to this 2650 function is the new SP (after the prologue has been executed). So we 2651 can't calculate those offsets until we've seen the entire prologue, 2652 and can calculate what the old SP must have been. */ 2653 if (entry_inst != 0) 2654 { 2655 int areg_count = (entry_inst >> 8) & 7; 2656 int sreg_count = (entry_inst >> 6) & 3; 2657 2658 /* The entry instruction always subtracts 32 from the SP. */ 2659 frame_offset += 32; 2660 2661 /* Now we can calculate what the SP must have been at the 2662 start of the function prologue. */ 2663 sp += frame_offset; 2664 2665 /* Check if a0-a3 were saved in the caller's argument save area. */ 2666 for (reg = 4, offset = 0; reg < areg_count + 4; reg++) 2667 { 2668 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2669 offset += mips_abi_regsize (gdbarch); 2670 } 2671 2672 /* Check if the ra register was pushed on the stack. */ 2673 offset = -4; 2674 if (entry_inst & 0x20) 2675 { 2676 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2677 offset -= mips_abi_regsize (gdbarch); 2678 } 2679 2680 /* Check if the s0 and s1 registers were pushed on the stack. */ 2681 for (reg = 16; reg < sreg_count + 16; reg++) 2682 { 2683 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2684 offset -= mips_abi_regsize (gdbarch); 2685 } 2686 } 2687 2688 /* The SAVE instruction is similar to ENTRY, except that defined by the 2689 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the 2690 size of the frame is specified as an immediate field of instruction 2691 and an extended variation exists which lets additional registers and 2692 frame space to be specified. The instruction always treats registers 2693 as 32-bit so its usefulness for 64-bit ABIs is questionable. */ 2694 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) 2695 { 2696 static int args_table[16] = { 2697 0, 0, 0, 0, 1, 1, 1, 1, 2698 2, 2, 2, 0, 3, 3, 4, -1, 2699 }; 2700 static int astatic_table[16] = { 2701 0, 1, 2, 3, 0, 1, 2, 3, 2702 0, 1, 2, 4, 0, 1, 0, -1, 2703 }; 2704 int aregs = (save_inst >> 16) & 0xf; 2705 int xsregs = (save_inst >> 24) & 0x7; 2706 int args = args_table[aregs]; 2707 int astatic = astatic_table[aregs]; 2708 long frame_size; 2709 2710 if (args < 0) 2711 { 2712 warning (_("Invalid number of argument registers encoded in SAVE.")); 2713 args = 0; 2714 } 2715 if (astatic < 0) 2716 { 2717 warning (_("Invalid number of static registers encoded in SAVE.")); 2718 astatic = 0; 2719 } 2720 2721 /* For standard SAVE the frame size of 0 means 128. */ 2722 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); 2723 if (frame_size == 0 && (save_inst >> 16) == 0) 2724 frame_size = 16; 2725 frame_size *= 8; 2726 frame_offset += frame_size; 2727 2728 /* Now we can calculate what the SP must have been at the 2729 start of the function prologue. */ 2730 sp += frame_offset; 2731 2732 /* Check if A0-A3 were saved in the caller's argument save area. */ 2733 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) 2734 { 2735 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2736 offset += mips_abi_regsize (gdbarch); 2737 } 2738 2739 offset = -4; 2740 2741 /* Check if the RA register was pushed on the stack. */ 2742 if (save_inst & 0x40) 2743 { 2744 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2745 offset -= mips_abi_regsize (gdbarch); 2746 } 2747 2748 /* Check if the S8 register was pushed on the stack. */ 2749 if (xsregs > 6) 2750 { 2751 set_reg_offset (gdbarch, this_cache, 30, sp + offset); 2752 offset -= mips_abi_regsize (gdbarch); 2753 xsregs--; 2754 } 2755 /* Check if S2-S7 were pushed on the stack. */ 2756 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) 2757 { 2758 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2759 offset -= mips_abi_regsize (gdbarch); 2760 } 2761 2762 /* Check if the S1 register was pushed on the stack. */ 2763 if (save_inst & 0x10) 2764 { 2765 set_reg_offset (gdbarch, this_cache, 17, sp + offset); 2766 offset -= mips_abi_regsize (gdbarch); 2767 } 2768 /* Check if the S0 register was pushed on the stack. */ 2769 if (save_inst & 0x20) 2770 { 2771 set_reg_offset (gdbarch, this_cache, 16, sp + offset); 2772 offset -= mips_abi_regsize (gdbarch); 2773 } 2774 2775 /* Check if A0-A3 were pushed on the stack. */ 2776 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) 2777 { 2778 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2779 offset -= mips_abi_regsize (gdbarch); 2780 } 2781 } 2782 2783 if (this_cache != NULL) 2784 { 2785 this_cache->base = 2786 (get_frame_register_signed (this_frame, 2787 gdbarch_num_regs (gdbarch) + frame_reg) 2788 + frame_offset - frame_adjust); 2789 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 2790 be able to get rid of the assignment below, evetually. But it's 2791 still needed for now. */ 2792 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 2793 + mips_regnum (gdbarch)->pc] 2794 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 2795 } 2796 2797 /* Set end_prologue_addr to the address of the instruction immediately 2798 after the last one we scanned. Unless the last one looked like a 2799 non-prologue instruction (and we looked ahead), in which case use 2800 its address instead. */ 2801 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot 2802 ? prev_pc : cur_pc - prev_extend_bytes); 2803 2804 return end_prologue_addr; 2805 } 2806 2807 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). 2808 Procedures that use the 32-bit instruction set are handled by the 2809 mips_insn32 unwinder. */ 2810 2811 static struct mips_frame_cache * 2812 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) 2813 { 2814 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2815 struct mips_frame_cache *cache; 2816 2817 if ((*this_cache) != NULL) 2818 return (struct mips_frame_cache *) (*this_cache); 2819 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 2820 (*this_cache) = cache; 2821 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 2822 2823 /* Analyze the function prologue. */ 2824 { 2825 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 2826 CORE_ADDR start_addr; 2827 2828 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2829 if (start_addr == 0) 2830 start_addr = heuristic_proc_start (gdbarch, pc); 2831 /* We can't analyze the prologue if we couldn't find the begining 2832 of the function. */ 2833 if (start_addr == 0) 2834 return cache; 2835 2836 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, 2837 (struct mips_frame_cache *) *this_cache); 2838 } 2839 2840 /* gdbarch_sp_regnum contains the value and not the address. */ 2841 trad_frame_set_value (cache->saved_regs, 2842 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 2843 cache->base); 2844 2845 return (struct mips_frame_cache *) (*this_cache); 2846 } 2847 2848 static void 2849 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, 2850 struct frame_id *this_id) 2851 { 2852 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2853 this_cache); 2854 /* This marks the outermost frame. */ 2855 if (info->base == 0) 2856 return; 2857 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 2858 } 2859 2860 static struct value * 2861 mips_insn16_frame_prev_register (struct frame_info *this_frame, 2862 void **this_cache, int regnum) 2863 { 2864 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2865 this_cache); 2866 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 2867 } 2868 2869 static int 2870 mips_insn16_frame_sniffer (const struct frame_unwind *self, 2871 struct frame_info *this_frame, void **this_cache) 2872 { 2873 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2874 CORE_ADDR pc = get_frame_pc (this_frame); 2875 if (mips_pc_is_mips16 (gdbarch, pc)) 2876 return 1; 2877 return 0; 2878 } 2879 2880 static const struct frame_unwind mips_insn16_frame_unwind = 2881 { 2882 NORMAL_FRAME, 2883 default_frame_unwind_stop_reason, 2884 mips_insn16_frame_this_id, 2885 mips_insn16_frame_prev_register, 2886 NULL, 2887 mips_insn16_frame_sniffer 2888 }; 2889 2890 static CORE_ADDR 2891 mips_insn16_frame_base_address (struct frame_info *this_frame, 2892 void **this_cache) 2893 { 2894 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2895 this_cache); 2896 return info->base; 2897 } 2898 2899 static const struct frame_base mips_insn16_frame_base = 2900 { 2901 &mips_insn16_frame_unwind, 2902 mips_insn16_frame_base_address, 2903 mips_insn16_frame_base_address, 2904 mips_insn16_frame_base_address 2905 }; 2906 2907 static const struct frame_base * 2908 mips_insn16_frame_base_sniffer (struct frame_info *this_frame) 2909 { 2910 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2911 CORE_ADDR pc = get_frame_pc (this_frame); 2912 if (mips_pc_is_mips16 (gdbarch, pc)) 2913 return &mips_insn16_frame_base; 2914 else 2915 return NULL; 2916 } 2917 2918 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped 2919 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are 2920 interpreted directly, and then multiplied by 4. */ 2921 2922 static int 2923 micromips_decode_imm9 (int imm) 2924 { 2925 imm = (imm ^ 0x100) - 0x100; 2926 if (imm > -3 && imm < 2) 2927 imm ^= 0x100; 2928 return imm << 2; 2929 } 2930 2931 /* Analyze the function prologue from START_PC to LIMIT_PC. Return 2932 the address of the first instruction past the prologue. */ 2933 2934 static CORE_ADDR 2935 micromips_scan_prologue (struct gdbarch *gdbarch, 2936 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2937 struct frame_info *this_frame, 2938 struct mips_frame_cache *this_cache) 2939 { 2940 CORE_ADDR end_prologue_addr; 2941 int prev_non_prologue_insn = 0; 2942 int frame_reg = MIPS_SP_REGNUM; 2943 int this_non_prologue_insn; 2944 int non_prologue_insns = 0; 2945 long frame_offset = 0; /* Size of stack frame. */ 2946 long frame_adjust = 0; /* Offset of FP from SP. */ 2947 int prev_delay_slot = 0; 2948 int in_delay_slot; 2949 CORE_ADDR prev_pc; 2950 CORE_ADDR cur_pc; 2951 ULONGEST insn; /* current instruction */ 2952 CORE_ADDR sp; 2953 long offset; 2954 long sp_adj; 2955 long v1_off = 0; /* The assumption is LUI will replace it. */ 2956 int reglist; 2957 int breg; 2958 int dreg; 2959 int sreg; 2960 int treg; 2961 int loc; 2962 int op; 2963 int s; 2964 int i; 2965 2966 /* Can be called when there's no process, and hence when there's no 2967 THIS_FRAME. */ 2968 if (this_frame != NULL) 2969 sp = get_frame_register_signed (this_frame, 2970 gdbarch_num_regs (gdbarch) 2971 + MIPS_SP_REGNUM); 2972 else 2973 sp = 0; 2974 2975 if (limit_pc > start_pc + 200) 2976 limit_pc = start_pc + 200; 2977 prev_pc = start_pc; 2978 2979 /* Permit at most one non-prologue non-control-transfer instruction 2980 in the middle which may have been reordered by the compiler for 2981 optimisation. */ 2982 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) 2983 { 2984 this_non_prologue_insn = 0; 2985 in_delay_slot = 0; 2986 sp_adj = 0; 2987 loc = 0; 2988 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); 2989 loc += MIPS_INSN16_SIZE; 2990 switch (mips_insn_size (ISA_MICROMIPS, insn)) 2991 { 2992 /* 32-bit instructions. */ 2993 case 2 * MIPS_INSN16_SIZE: 2994 insn <<= 16; 2995 insn |= mips_fetch_instruction (gdbarch, 2996 ISA_MICROMIPS, cur_pc + loc, NULL); 2997 loc += MIPS_INSN16_SIZE; 2998 switch (micromips_op (insn >> 16)) 2999 { 3000 /* Record $sp/$fp adjustment. */ 3001 /* Discard (D)ADDU $gp,$jp used for PIC code. */ 3002 case 0x0: /* POOL32A: bits 000000 */ 3003 case 0x16: /* POOL32S: bits 010110 */ 3004 op = b0s11_op (insn); 3005 sreg = b0s5_reg (insn >> 16); 3006 treg = b5s5_reg (insn >> 16); 3007 dreg = b11s5_reg (insn); 3008 if (op == 0x1d0 3009 /* SUBU: bits 000000 00111010000 */ 3010 /* DSUBU: bits 010110 00111010000 */ 3011 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM 3012 && treg == 3) 3013 /* (D)SUBU $sp, $v1 */ 3014 sp_adj = v1_off; 3015 else if (op != 0x150 3016 /* ADDU: bits 000000 00101010000 */ 3017 /* DADDU: bits 010110 00101010000 */ 3018 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) 3019 this_non_prologue_insn = 1; 3020 break; 3021 3022 case 0x8: /* POOL32B: bits 001000 */ 3023 op = b12s4_op (insn); 3024 breg = b0s5_reg (insn >> 16); 3025 reglist = sreg = b5s5_reg (insn >> 16); 3026 offset = (b0s12_imm (insn) ^ 0x800) - 0x800; 3027 if ((op == 0x9 || op == 0xc) 3028 /* SWP: bits 001000 1001 */ 3029 /* SDP: bits 001000 1100 */ 3030 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) 3031 /* S[DW]P reg,offset($sp) */ 3032 { 3033 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); 3034 set_reg_offset (gdbarch, this_cache, 3035 sreg, sp + offset); 3036 set_reg_offset (gdbarch, this_cache, 3037 sreg + 1, sp + offset + s); 3038 } 3039 else if ((op == 0xd || op == 0xf) 3040 /* SWM: bits 001000 1101 */ 3041 /* SDM: bits 001000 1111 */ 3042 && breg == MIPS_SP_REGNUM 3043 /* SWM reglist,offset($sp) */ 3044 && ((reglist >= 1 && reglist <= 9) 3045 || (reglist >= 16 && reglist <= 25))) 3046 { 3047 int sreglist = min(reglist & 0xf, 8); 3048 3049 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); 3050 for (i = 0; i < sreglist; i++) 3051 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); 3052 if ((reglist & 0xf) > 8) 3053 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); 3054 if ((reglist & 0x10) == 0x10) 3055 set_reg_offset (gdbarch, this_cache, 3056 MIPS_RA_REGNUM, sp + s * i++); 3057 } 3058 else 3059 this_non_prologue_insn = 1; 3060 break; 3061 3062 /* Record $sp/$fp adjustment. */ 3063 /* Discard (D)ADDIU $gp used for PIC code. */ 3064 case 0xc: /* ADDIU: bits 001100 */ 3065 case 0x17: /* DADDIU: bits 010111 */ 3066 sreg = b0s5_reg (insn >> 16); 3067 dreg = b5s5_reg (insn >> 16); 3068 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3069 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) 3070 /* (D)ADDIU $sp, imm */ 3071 sp_adj = offset; 3072 else if (sreg == MIPS_SP_REGNUM && dreg == 30) 3073 /* (D)ADDIU $fp, $sp, imm */ 3074 { 3075 frame_adjust = offset; 3076 frame_reg = 30; 3077 } 3078 else if (sreg != 28 || dreg != 28) 3079 /* (D)ADDIU $gp, imm */ 3080 this_non_prologue_insn = 1; 3081 break; 3082 3083 /* LUI $v1 is used for larger $sp adjustments. */ 3084 /* Discard LUI $gp used for PIC code. */ 3085 case 0x10: /* POOL32I: bits 010000 */ 3086 if (b5s5_op (insn >> 16) == 0xd 3087 /* LUI: bits 010000 001101 */ 3088 && b0s5_reg (insn >> 16) == 3) 3089 /* LUI $v1, imm */ 3090 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; 3091 else if (b5s5_op (insn >> 16) != 0xd 3092 /* LUI: bits 010000 001101 */ 3093 || b0s5_reg (insn >> 16) != 28) 3094 /* LUI $gp, imm */ 3095 this_non_prologue_insn = 1; 3096 break; 3097 3098 /* ORI $v1 is used for larger $sp adjustments. */ 3099 case 0x14: /* ORI: bits 010100 */ 3100 sreg = b0s5_reg (insn >> 16); 3101 dreg = b5s5_reg (insn >> 16); 3102 if (sreg == 3 && dreg == 3) 3103 /* ORI $v1, imm */ 3104 v1_off |= b0s16_imm (insn); 3105 else 3106 this_non_prologue_insn = 1; 3107 break; 3108 3109 case 0x26: /* SWC1: bits 100110 */ 3110 case 0x2e: /* SDC1: bits 101110 */ 3111 breg = b0s5_reg (insn >> 16); 3112 if (breg != MIPS_SP_REGNUM) 3113 /* S[DW]C1 reg,offset($sp) */ 3114 this_non_prologue_insn = 1; 3115 break; 3116 3117 case 0x36: /* SD: bits 110110 */ 3118 case 0x3e: /* SW: bits 111110 */ 3119 breg = b0s5_reg (insn >> 16); 3120 sreg = b5s5_reg (insn >> 16); 3121 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3122 if (breg == MIPS_SP_REGNUM) 3123 /* S[DW] reg,offset($sp) */ 3124 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3125 else 3126 this_non_prologue_insn = 1; 3127 break; 3128 3129 default: 3130 /* The instruction in the delay slot can be a part 3131 of the prologue, so move forward once more. */ 3132 if (micromips_instruction_has_delay_slot (insn, 0)) 3133 in_delay_slot = 1; 3134 else 3135 this_non_prologue_insn = 1; 3136 break; 3137 } 3138 insn >>= 16; 3139 break; 3140 3141 /* 16-bit instructions. */ 3142 case MIPS_INSN16_SIZE: 3143 switch (micromips_op (insn)) 3144 { 3145 case 0x3: /* MOVE: bits 000011 */ 3146 sreg = b0s5_reg (insn); 3147 dreg = b5s5_reg (insn); 3148 if (sreg == MIPS_SP_REGNUM && dreg == 30) 3149 /* MOVE $fp, $sp */ 3150 frame_reg = 30; 3151 else if ((sreg & 0x1c) != 0x4) 3152 /* MOVE reg, $a0-$a3 */ 3153 this_non_prologue_insn = 1; 3154 break; 3155 3156 case 0x11: /* POOL16C: bits 010001 */ 3157 if (b6s4_op (insn) == 0x5) 3158 /* SWM: bits 010001 0101 */ 3159 { 3160 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; 3161 reglist = b4s2_regl (insn); 3162 for (i = 0; i <= reglist; i++) 3163 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); 3164 set_reg_offset (gdbarch, this_cache, 3165 MIPS_RA_REGNUM, sp + 4 * i++); 3166 } 3167 else 3168 this_non_prologue_insn = 1; 3169 break; 3170 3171 case 0x13: /* POOL16D: bits 010011 */ 3172 if ((insn & 0x1) == 0x1) 3173 /* ADDIUSP: bits 010011 1 */ 3174 sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); 3175 else if (b5s5_reg (insn) == MIPS_SP_REGNUM) 3176 /* ADDIUS5: bits 010011 0 */ 3177 /* ADDIUS5 $sp, imm */ 3178 sp_adj = (b1s4_imm (insn) ^ 8) - 8; 3179 else 3180 this_non_prologue_insn = 1; 3181 break; 3182 3183 case 0x32: /* SWSP: bits 110010 */ 3184 offset = b0s5_imm (insn) << 2; 3185 sreg = b5s5_reg (insn); 3186 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3187 break; 3188 3189 default: 3190 /* The instruction in the delay slot can be a part 3191 of the prologue, so move forward once more. */ 3192 if (micromips_instruction_has_delay_slot (insn << 16, 0)) 3193 in_delay_slot = 1; 3194 else 3195 this_non_prologue_insn = 1; 3196 break; 3197 } 3198 break; 3199 } 3200 if (sp_adj < 0) 3201 frame_offset -= sp_adj; 3202 3203 non_prologue_insns += this_non_prologue_insn; 3204 3205 /* A jump or branch, enough non-prologue insns seen or positive 3206 stack adjustment? If so, then we must have reached the end 3207 of the prologue by now. */ 3208 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 3209 || micromips_instruction_is_compact_branch (insn)) 3210 break; 3211 3212 prev_non_prologue_insn = this_non_prologue_insn; 3213 prev_delay_slot = in_delay_slot; 3214 prev_pc = cur_pc; 3215 } 3216 3217 if (this_cache != NULL) 3218 { 3219 this_cache->base = 3220 (get_frame_register_signed (this_frame, 3221 gdbarch_num_regs (gdbarch) + frame_reg) 3222 + frame_offset - frame_adjust); 3223 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 3224 be able to get rid of the assignment below, evetually. But it's 3225 still needed for now. */ 3226 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3227 + mips_regnum (gdbarch)->pc] 3228 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 3229 } 3230 3231 /* Set end_prologue_addr to the address of the instruction immediately 3232 after the last one we scanned. Unless the last one looked like a 3233 non-prologue instruction (and we looked ahead), in which case use 3234 its address instead. */ 3235 end_prologue_addr 3236 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3237 3238 return end_prologue_addr; 3239 } 3240 3241 /* Heuristic unwinder for procedures using microMIPS instructions. 3242 Procedures that use the 32-bit instruction set are handled by the 3243 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ 3244 3245 static struct mips_frame_cache * 3246 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) 3247 { 3248 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3249 struct mips_frame_cache *cache; 3250 3251 if ((*this_cache) != NULL) 3252 return (struct mips_frame_cache *) (*this_cache); 3253 3254 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3255 (*this_cache) = cache; 3256 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3257 3258 /* Analyze the function prologue. */ 3259 { 3260 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3261 CORE_ADDR start_addr; 3262 3263 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3264 if (start_addr == 0) 3265 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); 3266 /* We can't analyze the prologue if we couldn't find the begining 3267 of the function. */ 3268 if (start_addr == 0) 3269 return cache; 3270 3271 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, 3272 (struct mips_frame_cache *) *this_cache); 3273 } 3274 3275 /* gdbarch_sp_regnum contains the value and not the address. */ 3276 trad_frame_set_value (cache->saved_regs, 3277 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 3278 cache->base); 3279 3280 return (struct mips_frame_cache *) (*this_cache); 3281 } 3282 3283 static void 3284 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, 3285 struct frame_id *this_id) 3286 { 3287 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3288 this_cache); 3289 /* This marks the outermost frame. */ 3290 if (info->base == 0) 3291 return; 3292 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3293 } 3294 3295 static struct value * 3296 mips_micro_frame_prev_register (struct frame_info *this_frame, 3297 void **this_cache, int regnum) 3298 { 3299 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3300 this_cache); 3301 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3302 } 3303 3304 static int 3305 mips_micro_frame_sniffer (const struct frame_unwind *self, 3306 struct frame_info *this_frame, void **this_cache) 3307 { 3308 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3309 CORE_ADDR pc = get_frame_pc (this_frame); 3310 3311 if (mips_pc_is_micromips (gdbarch, pc)) 3312 return 1; 3313 return 0; 3314 } 3315 3316 static const struct frame_unwind mips_micro_frame_unwind = 3317 { 3318 NORMAL_FRAME, 3319 default_frame_unwind_stop_reason, 3320 mips_micro_frame_this_id, 3321 mips_micro_frame_prev_register, 3322 NULL, 3323 mips_micro_frame_sniffer 3324 }; 3325 3326 static CORE_ADDR 3327 mips_micro_frame_base_address (struct frame_info *this_frame, 3328 void **this_cache) 3329 { 3330 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3331 this_cache); 3332 return info->base; 3333 } 3334 3335 static const struct frame_base mips_micro_frame_base = 3336 { 3337 &mips_micro_frame_unwind, 3338 mips_micro_frame_base_address, 3339 mips_micro_frame_base_address, 3340 mips_micro_frame_base_address 3341 }; 3342 3343 static const struct frame_base * 3344 mips_micro_frame_base_sniffer (struct frame_info *this_frame) 3345 { 3346 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3347 CORE_ADDR pc = get_frame_pc (this_frame); 3348 3349 if (mips_pc_is_micromips (gdbarch, pc)) 3350 return &mips_micro_frame_base; 3351 else 3352 return NULL; 3353 } 3354 3355 /* Mark all the registers as unset in the saved_regs array 3356 of THIS_CACHE. Do nothing if THIS_CACHE is null. */ 3357 3358 static void 3359 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) 3360 { 3361 if (this_cache == NULL || this_cache->saved_regs == NULL) 3362 return; 3363 3364 { 3365 const int num_regs = gdbarch_num_regs (gdbarch); 3366 int i; 3367 3368 for (i = 0; i < num_regs; i++) 3369 { 3370 this_cache->saved_regs[i].addr = -1; 3371 } 3372 } 3373 } 3374 3375 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 3376 the associated FRAME_CACHE if not null. 3377 Return the address of the first instruction past the prologue. */ 3378 3379 static CORE_ADDR 3380 mips32_scan_prologue (struct gdbarch *gdbarch, 3381 CORE_ADDR start_pc, CORE_ADDR limit_pc, 3382 struct frame_info *this_frame, 3383 struct mips_frame_cache *this_cache) 3384 { 3385 int prev_non_prologue_insn; 3386 int this_non_prologue_insn; 3387 int non_prologue_insns; 3388 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for 3389 frame-pointer. */ 3390 int prev_delay_slot; 3391 CORE_ADDR prev_pc; 3392 CORE_ADDR cur_pc; 3393 CORE_ADDR sp; 3394 long frame_offset; 3395 int frame_reg = MIPS_SP_REGNUM; 3396 3397 CORE_ADDR end_prologue_addr; 3398 int seen_sp_adjust = 0; 3399 int load_immediate_bytes = 0; 3400 int in_delay_slot; 3401 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); 3402 3403 /* Can be called when there's no process, and hence when there's no 3404 THIS_FRAME. */ 3405 if (this_frame != NULL) 3406 sp = get_frame_register_signed (this_frame, 3407 gdbarch_num_regs (gdbarch) 3408 + MIPS_SP_REGNUM); 3409 else 3410 sp = 0; 3411 3412 if (limit_pc > start_pc + 200) 3413 limit_pc = start_pc + 200; 3414 3415 restart: 3416 prev_non_prologue_insn = 0; 3417 non_prologue_insns = 0; 3418 prev_delay_slot = 0; 3419 prev_pc = start_pc; 3420 3421 /* Permit at most one non-prologue non-control-transfer instruction 3422 in the middle which may have been reordered by the compiler for 3423 optimisation. */ 3424 frame_offset = 0; 3425 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) 3426 { 3427 unsigned long inst, high_word; 3428 long offset; 3429 int reg; 3430 3431 this_non_prologue_insn = 0; 3432 in_delay_slot = 0; 3433 3434 /* Fetch the instruction. */ 3435 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, 3436 cur_pc, NULL); 3437 3438 /* Save some code by pre-extracting some useful fields. */ 3439 high_word = (inst >> 16) & 0xffff; 3440 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; 3441 reg = high_word & 0x1f; 3442 3443 if (high_word == 0x27bd /* addiu $sp,$sp,-i */ 3444 || high_word == 0x23bd /* addi $sp,$sp,-i */ 3445 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ 3446 { 3447 if (offset < 0) /* Negative stack adjustment? */ 3448 frame_offset -= offset; 3449 else 3450 /* Exit loop if a positive stack adjustment is found, which 3451 usually means that the stack cleanup code in the function 3452 epilogue is reached. */ 3453 break; 3454 seen_sp_adjust = 1; 3455 } 3456 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ 3457 && !regsize_is_64_bits) 3458 { 3459 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3460 } 3461 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ 3462 && regsize_is_64_bits) 3463 { 3464 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ 3465 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3466 } 3467 else if (high_word == 0x27be) /* addiu $30,$sp,size */ 3468 { 3469 /* Old gcc frame, r30 is virtual frame pointer. */ 3470 if (offset != frame_offset) 3471 frame_addr = sp + offset; 3472 else if (this_frame && frame_reg == MIPS_SP_REGNUM) 3473 { 3474 unsigned alloca_adjust; 3475 3476 frame_reg = 30; 3477 frame_addr = get_frame_register_signed 3478 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3479 frame_offset = 0; 3480 3481 alloca_adjust = (unsigned) (frame_addr - (sp + offset)); 3482 if (alloca_adjust > 0) 3483 { 3484 /* FP > SP + frame_size. This may be because of 3485 an alloca or somethings similar. Fix sp to 3486 "pre-alloca" value, and try again. */ 3487 sp += alloca_adjust; 3488 /* Need to reset the status of all registers. Otherwise, 3489 we will hit a guard that prevents the new address 3490 for each register to be recomputed during the second 3491 pass. */ 3492 reset_saved_regs (gdbarch, this_cache); 3493 goto restart; 3494 } 3495 } 3496 } 3497 /* move $30,$sp. With different versions of gas this will be either 3498 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. 3499 Accept any one of these. */ 3500 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) 3501 { 3502 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ 3503 if (this_frame && frame_reg == MIPS_SP_REGNUM) 3504 { 3505 unsigned alloca_adjust; 3506 3507 frame_reg = 30; 3508 frame_addr = get_frame_register_signed 3509 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3510 3511 alloca_adjust = (unsigned) (frame_addr - sp); 3512 if (alloca_adjust > 0) 3513 { 3514 /* FP > SP + frame_size. This may be because of 3515 an alloca or somethings similar. Fix sp to 3516 "pre-alloca" value, and try again. */ 3517 sp = frame_addr; 3518 /* Need to reset the status of all registers. Otherwise, 3519 we will hit a guard that prevents the new address 3520 for each register to be recomputed during the second 3521 pass. */ 3522 reset_saved_regs (gdbarch, this_cache); 3523 goto restart; 3524 } 3525 } 3526 } 3527 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ 3528 && !regsize_is_64_bits) 3529 { 3530 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 3531 } 3532 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ 3533 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ 3534 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ 3535 || high_word == 0x3c1c /* lui $gp,n */ 3536 || high_word == 0x279c /* addiu $gp,$gp,n */ 3537 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ 3538 || inst == 0x033ce021 /* addu $gp,$t9,$gp */ 3539 ) 3540 { 3541 /* These instructions are part of the prologue, but we don't 3542 need to do anything special to handle them. */ 3543 } 3544 /* The instructions below load $at or $t0 with an immediate 3545 value in preparation for a stack adjustment via 3546 subu $sp,$sp,[$at,$t0]. These instructions could also 3547 initialize a local variable, so we accept them only before 3548 a stack adjustment instruction was seen. */ 3549 else if (!seen_sp_adjust 3550 && !prev_delay_slot 3551 && (high_word == 0x3c01 /* lui $at,n */ 3552 || high_word == 0x3c08 /* lui $t0,n */ 3553 || high_word == 0x3421 /* ori $at,$at,n */ 3554 || high_word == 0x3508 /* ori $t0,$t0,n */ 3555 || high_word == 0x3401 /* ori $at,$zero,n */ 3556 || high_word == 0x3408 /* ori $t0,$zero,n */ 3557 )) 3558 { 3559 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ 3560 } 3561 /* Check for branches and jumps. The instruction in the delay 3562 slot can be a part of the prologue, so move forward once more. */ 3563 else if (mips32_instruction_has_delay_slot (gdbarch, inst)) 3564 { 3565 in_delay_slot = 1; 3566 } 3567 /* This instruction is not an instruction typically found 3568 in a prologue, so we must have reached the end of the 3569 prologue. */ 3570 else 3571 { 3572 this_non_prologue_insn = 1; 3573 } 3574 3575 non_prologue_insns += this_non_prologue_insn; 3576 3577 /* A jump or branch, or enough non-prologue insns seen? If so, 3578 then we must have reached the end of the prologue by now. */ 3579 if (prev_delay_slot || non_prologue_insns > 1) 3580 break; 3581 3582 prev_non_prologue_insn = this_non_prologue_insn; 3583 prev_delay_slot = in_delay_slot; 3584 prev_pc = cur_pc; 3585 } 3586 3587 if (this_cache != NULL) 3588 { 3589 this_cache->base = 3590 (get_frame_register_signed (this_frame, 3591 gdbarch_num_regs (gdbarch) + frame_reg) 3592 + frame_offset); 3593 /* FIXME: brobecker/2004-09-15: We should be able to get rid of 3594 this assignment below, eventually. But it's still needed 3595 for now. */ 3596 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3597 + mips_regnum (gdbarch)->pc] 3598 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3599 + MIPS_RA_REGNUM]; 3600 } 3601 3602 /* Set end_prologue_addr to the address of the instruction immediately 3603 after the last one we scanned. Unless the last one looked like a 3604 non-prologue instruction (and we looked ahead), in which case use 3605 its address instead. */ 3606 end_prologue_addr 3607 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3608 3609 /* In a frameless function, we might have incorrectly 3610 skipped some load immediate instructions. Undo the skipping 3611 if the load immediate was not followed by a stack adjustment. */ 3612 if (load_immediate_bytes && !seen_sp_adjust) 3613 end_prologue_addr -= load_immediate_bytes; 3614 3615 return end_prologue_addr; 3616 } 3617 3618 /* Heuristic unwinder for procedures using 32-bit instructions (covers 3619 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit 3620 instructions (a.k.a. MIPS16) are handled by the mips_insn16 3621 unwinder. Likewise microMIPS and the mips_micro unwinder. */ 3622 3623 static struct mips_frame_cache * 3624 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) 3625 { 3626 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3627 struct mips_frame_cache *cache; 3628 3629 if ((*this_cache) != NULL) 3630 return (struct mips_frame_cache *) (*this_cache); 3631 3632 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3633 (*this_cache) = cache; 3634 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3635 3636 /* Analyze the function prologue. */ 3637 { 3638 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3639 CORE_ADDR start_addr; 3640 3641 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3642 if (start_addr == 0) 3643 start_addr = heuristic_proc_start (gdbarch, pc); 3644 /* We can't analyze the prologue if we couldn't find the begining 3645 of the function. */ 3646 if (start_addr == 0) 3647 return cache; 3648 3649 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, 3650 (struct mips_frame_cache *) *this_cache); 3651 } 3652 3653 /* gdbarch_sp_regnum contains the value and not the address. */ 3654 trad_frame_set_value (cache->saved_regs, 3655 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 3656 cache->base); 3657 3658 return (struct mips_frame_cache *) (*this_cache); 3659 } 3660 3661 static void 3662 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, 3663 struct frame_id *this_id) 3664 { 3665 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3666 this_cache); 3667 /* This marks the outermost frame. */ 3668 if (info->base == 0) 3669 return; 3670 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3671 } 3672 3673 static struct value * 3674 mips_insn32_frame_prev_register (struct frame_info *this_frame, 3675 void **this_cache, int regnum) 3676 { 3677 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3678 this_cache); 3679 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3680 } 3681 3682 static int 3683 mips_insn32_frame_sniffer (const struct frame_unwind *self, 3684 struct frame_info *this_frame, void **this_cache) 3685 { 3686 CORE_ADDR pc = get_frame_pc (this_frame); 3687 if (mips_pc_is_mips (pc)) 3688 return 1; 3689 return 0; 3690 } 3691 3692 static const struct frame_unwind mips_insn32_frame_unwind = 3693 { 3694 NORMAL_FRAME, 3695 default_frame_unwind_stop_reason, 3696 mips_insn32_frame_this_id, 3697 mips_insn32_frame_prev_register, 3698 NULL, 3699 mips_insn32_frame_sniffer 3700 }; 3701 3702 static CORE_ADDR 3703 mips_insn32_frame_base_address (struct frame_info *this_frame, 3704 void **this_cache) 3705 { 3706 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3707 this_cache); 3708 return info->base; 3709 } 3710 3711 static const struct frame_base mips_insn32_frame_base = 3712 { 3713 &mips_insn32_frame_unwind, 3714 mips_insn32_frame_base_address, 3715 mips_insn32_frame_base_address, 3716 mips_insn32_frame_base_address 3717 }; 3718 3719 static const struct frame_base * 3720 mips_insn32_frame_base_sniffer (struct frame_info *this_frame) 3721 { 3722 CORE_ADDR pc = get_frame_pc (this_frame); 3723 if (mips_pc_is_mips (pc)) 3724 return &mips_insn32_frame_base; 3725 else 3726 return NULL; 3727 } 3728 3729 static struct trad_frame_cache * 3730 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) 3731 { 3732 CORE_ADDR pc; 3733 CORE_ADDR start_addr; 3734 CORE_ADDR stack_addr; 3735 struct trad_frame_cache *this_trad_cache; 3736 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3737 int num_regs = gdbarch_num_regs (gdbarch); 3738 3739 if ((*this_cache) != NULL) 3740 return (struct trad_frame_cache *) (*this_cache); 3741 this_trad_cache = trad_frame_cache_zalloc (this_frame); 3742 (*this_cache) = this_trad_cache; 3743 3744 /* The return address is in the link register. */ 3745 trad_frame_set_reg_realreg (this_trad_cache, 3746 gdbarch_pc_regnum (gdbarch), 3747 num_regs + MIPS_RA_REGNUM); 3748 3749 /* Frame ID, since it's a frameless / stackless function, no stack 3750 space is allocated and SP on entry is the current SP. */ 3751 pc = get_frame_pc (this_frame); 3752 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3753 stack_addr = get_frame_register_signed (this_frame, 3754 num_regs + MIPS_SP_REGNUM); 3755 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); 3756 3757 /* Assume that the frame's base is the same as the 3758 stack-pointer. */ 3759 trad_frame_set_this_base (this_trad_cache, stack_addr); 3760 3761 return this_trad_cache; 3762 } 3763 3764 static void 3765 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, 3766 struct frame_id *this_id) 3767 { 3768 struct trad_frame_cache *this_trad_cache 3769 = mips_stub_frame_cache (this_frame, this_cache); 3770 trad_frame_get_id (this_trad_cache, this_id); 3771 } 3772 3773 static struct value * 3774 mips_stub_frame_prev_register (struct frame_info *this_frame, 3775 void **this_cache, int regnum) 3776 { 3777 struct trad_frame_cache *this_trad_cache 3778 = mips_stub_frame_cache (this_frame, this_cache); 3779 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 3780 } 3781 3782 static int 3783 mips_stub_frame_sniffer (const struct frame_unwind *self, 3784 struct frame_info *this_frame, void **this_cache) 3785 { 3786 gdb_byte dummy[4]; 3787 struct obj_section *s; 3788 CORE_ADDR pc = get_frame_address_in_block (this_frame); 3789 struct bound_minimal_symbol msym; 3790 3791 /* Use the stub unwinder for unreadable code. */ 3792 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 3793 return 1; 3794 3795 if (in_plt_section (pc) || in_mips_stubs_section (pc)) 3796 return 1; 3797 3798 /* Calling a PIC function from a non-PIC function passes through a 3799 stub. The stub for foo is named ".pic.foo". */ 3800 msym = lookup_minimal_symbol_by_pc (pc); 3801 if (msym.minsym != NULL 3802 && MSYMBOL_LINKAGE_NAME (msym.minsym) != NULL 3803 && startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) 3804 return 1; 3805 3806 return 0; 3807 } 3808 3809 static const struct frame_unwind mips_stub_frame_unwind = 3810 { 3811 NORMAL_FRAME, 3812 default_frame_unwind_stop_reason, 3813 mips_stub_frame_this_id, 3814 mips_stub_frame_prev_register, 3815 NULL, 3816 mips_stub_frame_sniffer 3817 }; 3818 3819 static CORE_ADDR 3820 mips_stub_frame_base_address (struct frame_info *this_frame, 3821 void **this_cache) 3822 { 3823 struct trad_frame_cache *this_trad_cache 3824 = mips_stub_frame_cache (this_frame, this_cache); 3825 return trad_frame_get_this_base (this_trad_cache); 3826 } 3827 3828 static const struct frame_base mips_stub_frame_base = 3829 { 3830 &mips_stub_frame_unwind, 3831 mips_stub_frame_base_address, 3832 mips_stub_frame_base_address, 3833 mips_stub_frame_base_address 3834 }; 3835 3836 static const struct frame_base * 3837 mips_stub_frame_base_sniffer (struct frame_info *this_frame) 3838 { 3839 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) 3840 return &mips_stub_frame_base; 3841 else 3842 return NULL; 3843 } 3844 3845 /* mips_addr_bits_remove - remove useless address bits */ 3846 3847 static CORE_ADDR 3848 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) 3849 { 3850 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3851 3852 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) 3853 /* This hack is a work-around for existing boards using PMON, the 3854 simulator, and any other 64-bit targets that doesn't have true 3855 64-bit addressing. On these targets, the upper 32 bits of 3856 addresses are ignored by the hardware. Thus, the PC or SP are 3857 likely to have been sign extended to all 1s by instruction 3858 sequences that load 32-bit addresses. For example, a typical 3859 piece of code that loads an address is this: 3860 3861 lui $r2, <upper 16 bits> 3862 ori $r2, <lower 16 bits> 3863 3864 But the lui sign-extends the value such that the upper 32 bits 3865 may be all 1s. The workaround is simply to mask off these 3866 bits. In the future, gcc may be changed to support true 64-bit 3867 addressing, and this masking will have to be disabled. */ 3868 return addr &= 0xffffffffUL; 3869 else 3870 return addr; 3871 } 3872 3873 3874 /* Checks for an atomic sequence of instructions beginning with a LL/LLD 3875 instruction and ending with a SC/SCD instruction. If such a sequence 3876 is found, attempt to step through it. A breakpoint is placed at the end of 3877 the sequence. */ 3878 3879 /* Instructions used during single-stepping of atomic sequences, standard 3880 ISA version. */ 3881 #define LL_OPCODE 0x30 3882 #define LLD_OPCODE 0x34 3883 #define SC_OPCODE 0x38 3884 #define SCD_OPCODE 0x3c 3885 3886 static int 3887 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, 3888 struct address_space *aspace, CORE_ADDR pc) 3889 { 3890 CORE_ADDR breaks[2] = {-1, -1}; 3891 CORE_ADDR loc = pc; 3892 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ 3893 ULONGEST insn; 3894 int insn_count; 3895 int index; 3896 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 3897 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 3898 3899 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3900 /* Assume all atomic sequences start with a ll/lld instruction. */ 3901 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) 3902 return 0; 3903 3904 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 3905 instructions. */ 3906 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 3907 { 3908 int is_branch = 0; 3909 loc += MIPS_INSN32_SIZE; 3910 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3911 3912 /* Assume that there is at most one branch in the atomic 3913 sequence. If a branch is found, put a breakpoint in its 3914 destination address. */ 3915 switch (itype_op (insn)) 3916 { 3917 case 0: /* SPECIAL */ 3918 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ 3919 return 0; /* fallback to the standard single-step code. */ 3920 break; 3921 case 1: /* REGIMM */ 3922 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ 3923 || ((itype_rt (insn) & 0x1e) == 0 3924 && itype_rs (insn) == 0)); /* BPOSGE* */ 3925 break; 3926 case 2: /* J */ 3927 case 3: /* JAL */ 3928 return 0; /* fallback to the standard single-step code. */ 3929 case 4: /* BEQ */ 3930 case 5: /* BNE */ 3931 case 6: /* BLEZ */ 3932 case 7: /* BGTZ */ 3933 case 20: /* BEQL */ 3934 case 21: /* BNEL */ 3935 case 22: /* BLEZL */ 3936 case 23: /* BGTTL */ 3937 is_branch = 1; 3938 break; 3939 case 17: /* COP1 */ 3940 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) 3941 && (itype_rt (insn) & 0x2) == 0); 3942 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ 3943 break; 3944 /* Fall through. */ 3945 case 18: /* COP2 */ 3946 case 19: /* COP3 */ 3947 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ 3948 break; 3949 } 3950 if (is_branch) 3951 { 3952 branch_bp = loc + mips32_relative_offset (insn) + 4; 3953 if (last_breakpoint >= 1) 3954 return 0; /* More than one branch found, fallback to the 3955 standard single-step code. */ 3956 breaks[1] = branch_bp; 3957 last_breakpoint++; 3958 } 3959 3960 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) 3961 break; 3962 } 3963 3964 /* Assume that the atomic sequence ends with a sc/scd instruction. */ 3965 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) 3966 return 0; 3967 3968 loc += MIPS_INSN32_SIZE; 3969 3970 /* Insert a breakpoint right after the end of the atomic sequence. */ 3971 breaks[0] = loc; 3972 3973 /* Check for duplicated breakpoints. Check also for a breakpoint 3974 placed (branch instruction's destination) in the atomic sequence. */ 3975 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 3976 last_breakpoint = 0; 3977 3978 /* Effectively inserts the breakpoints. */ 3979 for (index = 0; index <= last_breakpoint; index++) 3980 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); 3981 3982 return 1; 3983 } 3984 3985 static int 3986 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, 3987 struct address_space *aspace, 3988 CORE_ADDR pc) 3989 { 3990 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 3991 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 3992 CORE_ADDR breaks[2] = {-1, -1}; 3993 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's 3994 destination. */ 3995 CORE_ADDR loc = pc; 3996 int sc_found = 0; 3997 ULONGEST insn; 3998 int insn_count; 3999 int index; 4000 4001 /* Assume all atomic sequences start with a ll/lld instruction. */ 4002 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4003 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ 4004 return 0; 4005 loc += MIPS_INSN16_SIZE; 4006 insn <<= 16; 4007 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4008 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ 4009 return 0; 4010 loc += MIPS_INSN16_SIZE; 4011 4012 /* Assume all atomic sequences end with an sc/scd instruction. Assume 4013 that no atomic sequence is longer than "atomic_sequence_length" 4014 instructions. */ 4015 for (insn_count = 0; 4016 !sc_found && insn_count < atomic_sequence_length; 4017 ++insn_count) 4018 { 4019 int is_branch = 0; 4020 4021 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4022 loc += MIPS_INSN16_SIZE; 4023 4024 /* Assume that there is at most one conditional branch in the 4025 atomic sequence. If a branch is found, put a breakpoint in 4026 its destination address. */ 4027 switch (mips_insn_size (ISA_MICROMIPS, insn)) 4028 { 4029 /* 32-bit instructions. */ 4030 case 2 * MIPS_INSN16_SIZE: 4031 switch (micromips_op (insn)) 4032 { 4033 case 0x10: /* POOL32I: bits 010000 */ 4034 if ((b5s5_op (insn) & 0x18) != 0x0 4035 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 4036 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ 4037 && (b5s5_op (insn) & 0x1d) != 0x11 4038 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 4039 && ((b5s5_op (insn) & 0x1e) != 0x14 4040 || (insn & 0x3) != 0x0) 4041 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 4042 && (b5s5_op (insn) & 0x1e) != 0x1a 4043 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 4044 && ((b5s5_op (insn) & 0x1e) != 0x1c 4045 || (insn & 0x3) != 0x0) 4046 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 4047 && ((b5s5_op (insn) & 0x1c) != 0x1c 4048 || (insn & 0x3) != 0x1)) 4049 /* BC1ANY*: bits 010000 111xx xxx01 */ 4050 break; 4051 /* Fall through. */ 4052 4053 case 0x25: /* BEQ: bits 100101 */ 4054 case 0x2d: /* BNE: bits 101101 */ 4055 insn <<= 16; 4056 insn |= mips_fetch_instruction (gdbarch, 4057 ISA_MICROMIPS, loc, NULL); 4058 branch_bp = (loc + MIPS_INSN16_SIZE 4059 + micromips_relative_offset16 (insn)); 4060 is_branch = 1; 4061 break; 4062 4063 case 0x00: /* POOL32A: bits 000000 */ 4064 insn <<= 16; 4065 insn |= mips_fetch_instruction (gdbarch, 4066 ISA_MICROMIPS, loc, NULL); 4067 if (b0s6_op (insn) != 0x3c 4068 /* POOL32Axf: bits 000000 ... 111100 */ 4069 || (b6s10_ext (insn) & 0x2bf) != 0x3c) 4070 /* JALR, JALR.HB: 000000 000x111100 111100 */ 4071 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 4072 break; 4073 /* Fall through. */ 4074 4075 case 0x1d: /* JALS: bits 011101 */ 4076 case 0x35: /* J: bits 110101 */ 4077 case 0x3d: /* JAL: bits 111101 */ 4078 case 0x3c: /* JALX: bits 111100 */ 4079 return 0; /* Fall back to the standard single-step code. */ 4080 4081 case 0x18: /* POOL32C: bits 011000 */ 4082 if ((b12s4_op (insn) & 0xb) == 0xb) 4083 /* SC, SCD: bits 011000 1x11 */ 4084 sc_found = 1; 4085 break; 4086 } 4087 loc += MIPS_INSN16_SIZE; 4088 break; 4089 4090 /* 16-bit instructions. */ 4091 case MIPS_INSN16_SIZE: 4092 switch (micromips_op (insn)) 4093 { 4094 case 0x23: /* BEQZ16: bits 100011 */ 4095 case 0x2b: /* BNEZ16: bits 101011 */ 4096 branch_bp = loc + micromips_relative_offset7 (insn); 4097 is_branch = 1; 4098 break; 4099 4100 case 0x11: /* POOL16C: bits 010001 */ 4101 if ((b5s5_op (insn) & 0x1c) != 0xc 4102 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 4103 && b5s5_op (insn) != 0x18) 4104 /* JRADDIUSP: bits 010001 11000 */ 4105 break; 4106 return 0; /* Fall back to the standard single-step code. */ 4107 4108 case 0x33: /* B16: bits 110011 */ 4109 return 0; /* Fall back to the standard single-step code. */ 4110 } 4111 break; 4112 } 4113 if (is_branch) 4114 { 4115 if (last_breakpoint >= 1) 4116 return 0; /* More than one branch found, fallback to the 4117 standard single-step code. */ 4118 breaks[1] = branch_bp; 4119 last_breakpoint++; 4120 } 4121 } 4122 if (!sc_found) 4123 return 0; 4124 4125 /* Insert a breakpoint right after the end of the atomic sequence. */ 4126 breaks[0] = loc; 4127 4128 /* Check for duplicated breakpoints. Check also for a breakpoint 4129 placed (branch instruction's destination) in the atomic sequence */ 4130 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 4131 last_breakpoint = 0; 4132 4133 /* Effectively inserts the breakpoints. */ 4134 for (index = 0; index <= last_breakpoint; index++) 4135 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]); 4136 4137 return 1; 4138 } 4139 4140 static int 4141 deal_with_atomic_sequence (struct gdbarch *gdbarch, 4142 struct address_space *aspace, CORE_ADDR pc) 4143 { 4144 if (mips_pc_is_mips (pc)) 4145 return mips_deal_with_atomic_sequence (gdbarch, aspace, pc); 4146 else if (mips_pc_is_micromips (gdbarch, pc)) 4147 return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc); 4148 else 4149 return 0; 4150 } 4151 4152 /* mips_software_single_step() is called just before we want to resume 4153 the inferior, if we want to single-step it but there is no hardware 4154 or kernel single-step support (MIPS on GNU/Linux for example). We find 4155 the target of the coming instruction and breakpoint it. */ 4156 4157 int 4158 mips_software_single_step (struct frame_info *frame) 4159 { 4160 struct gdbarch *gdbarch = get_frame_arch (frame); 4161 struct address_space *aspace = get_frame_address_space (frame); 4162 CORE_ADDR pc, next_pc; 4163 4164 pc = get_frame_pc (frame); 4165 if (deal_with_atomic_sequence (gdbarch, aspace, pc)) 4166 return 1; 4167 4168 next_pc = mips_next_pc (frame, pc); 4169 4170 insert_single_step_breakpoint (gdbarch, aspace, next_pc); 4171 return 1; 4172 } 4173 4174 /* Test whether the PC points to the return instruction at the 4175 end of a function. */ 4176 4177 static int 4178 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) 4179 { 4180 ULONGEST insn; 4181 ULONGEST hint; 4182 4183 /* This used to check for MIPS16, but this piece of code is never 4184 called for MIPS16 functions. And likewise microMIPS ones. */ 4185 gdb_assert (mips_pc_is_mips (pc)); 4186 4187 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 4188 hint = 0x7c0; 4189 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ 4190 } 4191 4192 4193 /* This fencepost looks highly suspicious to me. Removing it also 4194 seems suspicious as it could affect remote debugging across serial 4195 lines. */ 4196 4197 static CORE_ADDR 4198 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) 4199 { 4200 CORE_ADDR start_pc; 4201 CORE_ADDR fence; 4202 int instlen; 4203 int seen_adjsp = 0; 4204 struct inferior *inf; 4205 4206 pc = gdbarch_addr_bits_remove (gdbarch, pc); 4207 start_pc = pc; 4208 fence = start_pc - heuristic_fence_post; 4209 if (start_pc == 0) 4210 return 0; 4211 4212 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) 4213 fence = VM_MIN_ADDRESS; 4214 4215 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; 4216 4217 inf = current_inferior (); 4218 4219 /* Search back for previous return. */ 4220 for (start_pc -= instlen;; start_pc -= instlen) 4221 if (start_pc < fence) 4222 { 4223 /* It's not clear to me why we reach this point when 4224 stop_soon, but with this test, at least we 4225 don't print out warnings for every child forked (eg, on 4226 decstation). 22apr93 rich@cygnus.com. */ 4227 if (inf->control.stop_soon == NO_STOP_QUIETLY) 4228 { 4229 static int blurb_printed = 0; 4230 4231 warning (_("GDB can't find the start of the function at %s."), 4232 paddress (gdbarch, pc)); 4233 4234 if (!blurb_printed) 4235 { 4236 /* This actually happens frequently in embedded 4237 development, when you first connect to a board 4238 and your stack pointer and pc are nowhere in 4239 particular. This message needs to give people 4240 in that situation enough information to 4241 determine that it's no big deal. */ 4242 printf_filtered ("\n\ 4243 GDB is unable to find the start of the function at %s\n\ 4244 and thus can't determine the size of that function's stack frame.\n\ 4245 This means that GDB may be unable to access that stack frame, or\n\ 4246 the frames below it.\n\ 4247 This problem is most likely caused by an invalid program counter or\n\ 4248 stack pointer.\n\ 4249 However, if you think GDB should simply search farther back\n\ 4250 from %s for code which looks like the beginning of a\n\ 4251 function, you can increase the range of the search using the `set\n\ 4252 heuristic-fence-post' command.\n", 4253 paddress (gdbarch, pc), paddress (gdbarch, pc)); 4254 blurb_printed = 1; 4255 } 4256 } 4257 4258 return 0; 4259 } 4260 else if (mips_pc_is_mips16 (gdbarch, start_pc)) 4261 { 4262 unsigned short inst; 4263 4264 /* On MIPS16, any one of the following is likely to be the 4265 start of a function: 4266 extend save 4267 save 4268 entry 4269 addiu sp,-n 4270 daddiu sp,-n 4271 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ 4272 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); 4273 if ((inst & 0xff80) == 0x6480) /* save */ 4274 { 4275 if (start_pc - instlen >= fence) 4276 { 4277 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, 4278 start_pc - instlen, NULL); 4279 if ((inst & 0xf800) == 0xf000) /* extend */ 4280 start_pc -= instlen; 4281 } 4282 break; 4283 } 4284 else if (((inst & 0xf81f) == 0xe809 4285 && (inst & 0x700) != 0x700) /* entry */ 4286 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ 4287 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ 4288 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ 4289 break; 4290 else if ((inst & 0xff00) == 0x6300 /* addiu sp */ 4291 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 4292 seen_adjsp = 1; 4293 else 4294 seen_adjsp = 0; 4295 } 4296 else if (mips_pc_is_micromips (gdbarch, start_pc)) 4297 { 4298 ULONGEST insn; 4299 int stop = 0; 4300 long offset; 4301 int dreg; 4302 int sreg; 4303 4304 /* On microMIPS, any one of the following is likely to be the 4305 start of a function: 4306 ADDIUSP -imm 4307 (D)ADDIU $sp, -imm 4308 LUI $gp, imm */ 4309 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 4310 switch (micromips_op (insn)) 4311 { 4312 case 0xc: /* ADDIU: bits 001100 */ 4313 case 0x17: /* DADDIU: bits 010111 */ 4314 sreg = b0s5_reg (insn); 4315 dreg = b5s5_reg (insn); 4316 insn <<= 16; 4317 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, 4318 pc + MIPS_INSN16_SIZE, NULL); 4319 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 4320 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 4321 /* (D)ADDIU $sp, imm */ 4322 && offset < 0) 4323 stop = 1; 4324 break; 4325 4326 case 0x10: /* POOL32I: bits 010000 */ 4327 if (b5s5_op (insn) == 0xd 4328 /* LUI: bits 010000 001101 */ 4329 && b0s5_reg (insn >> 16) == 28) 4330 /* LUI $gp, imm */ 4331 stop = 1; 4332 break; 4333 4334 case 0x13: /* POOL16D: bits 010011 */ 4335 if ((insn & 0x1) == 0x1) 4336 /* ADDIUSP: bits 010011 1 */ 4337 { 4338 offset = micromips_decode_imm9 (b1s9_imm (insn)); 4339 if (offset < 0) 4340 /* ADDIUSP -imm */ 4341 stop = 1; 4342 } 4343 else 4344 /* ADDIUS5: bits 010011 0 */ 4345 { 4346 dreg = b5s5_reg (insn); 4347 offset = (b1s4_imm (insn) ^ 8) - 8; 4348 if (dreg == MIPS_SP_REGNUM && offset < 0) 4349 /* ADDIUS5 $sp, -imm */ 4350 stop = 1; 4351 } 4352 break; 4353 } 4354 if (stop) 4355 break; 4356 } 4357 else if (mips_about_to_return (gdbarch, start_pc)) 4358 { 4359 /* Skip return and its delay slot. */ 4360 start_pc += 2 * MIPS_INSN32_SIZE; 4361 break; 4362 } 4363 4364 return start_pc; 4365 } 4366 4367 struct mips_objfile_private 4368 { 4369 bfd_size_type size; 4370 char *contents; 4371 }; 4372 4373 /* According to the current ABI, should the type be passed in a 4374 floating-point register (assuming that there is space)? When there 4375 is no FPU, FP are not even considered as possible candidates for 4376 FP registers and, consequently this returns false - forces FP 4377 arguments into integer registers. */ 4378 4379 static int 4380 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, 4381 struct type *arg_type) 4382 { 4383 return ((typecode == TYPE_CODE_FLT 4384 || (MIPS_EABI (gdbarch) 4385 && (typecode == TYPE_CODE_STRUCT 4386 || typecode == TYPE_CODE_UNION) 4387 && TYPE_NFIELDS (arg_type) == 1 4388 && TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (arg_type, 0))) 4389 == TYPE_CODE_FLT)) 4390 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); 4391 } 4392 4393 /* On o32, argument passing in GPRs depends on the alignment of the type being 4394 passed. Return 1 if this type must be aligned to a doubleword boundary. */ 4395 4396 static int 4397 mips_type_needs_double_align (struct type *type) 4398 { 4399 enum type_code typecode = TYPE_CODE (type); 4400 4401 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) 4402 return 1; 4403 else if (typecode == TYPE_CODE_STRUCT) 4404 { 4405 if (TYPE_NFIELDS (type) < 1) 4406 return 0; 4407 return mips_type_needs_double_align (TYPE_FIELD_TYPE (type, 0)); 4408 } 4409 else if (typecode == TYPE_CODE_UNION) 4410 { 4411 int i, n; 4412 4413 n = TYPE_NFIELDS (type); 4414 for (i = 0; i < n; i++) 4415 if (mips_type_needs_double_align (TYPE_FIELD_TYPE (type, i))) 4416 return 1; 4417 return 0; 4418 } 4419 return 0; 4420 } 4421 4422 /* Adjust the address downward (direction of stack growth) so that it 4423 is correctly aligned for a new stack frame. */ 4424 static CORE_ADDR 4425 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 4426 { 4427 return align_down (addr, 16); 4428 } 4429 4430 /* Implement the "push_dummy_code" gdbarch method. */ 4431 4432 static CORE_ADDR 4433 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 4434 CORE_ADDR funaddr, struct value **args, 4435 int nargs, struct type *value_type, 4436 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 4437 struct regcache *regcache) 4438 { 4439 static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; 4440 CORE_ADDR nop_addr; 4441 CORE_ADDR bp_slot; 4442 4443 /* Reserve enough room on the stack for our breakpoint instruction. */ 4444 bp_slot = sp - sizeof (nop_insn); 4445 4446 /* Return to microMIPS mode if calling microMIPS code to avoid 4447 triggering an address error exception on processors that only 4448 support microMIPS execution. */ 4449 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) 4450 ? make_compact_addr (bp_slot) : bp_slot); 4451 4452 /* The breakpoint layer automatically adjusts the address of 4453 breakpoints inserted in a branch delay slot. With enough 4454 bad luck, the 4 bytes located just before our breakpoint 4455 instruction could look like a branch instruction, and thus 4456 trigger the adjustement, and break the function call entirely. 4457 So, we reserve those 4 bytes and write a nop instruction 4458 to prevent that from happening. */ 4459 nop_addr = bp_slot - sizeof (nop_insn); 4460 write_memory (nop_addr, nop_insn, sizeof (nop_insn)); 4461 sp = mips_frame_align (gdbarch, nop_addr); 4462 4463 /* Inferior resumes at the function entry point. */ 4464 *real_pc = funaddr; 4465 4466 return sp; 4467 } 4468 4469 static CORE_ADDR 4470 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4471 struct regcache *regcache, CORE_ADDR bp_addr, 4472 int nargs, struct value **args, CORE_ADDR sp, 4473 int struct_return, CORE_ADDR struct_addr) 4474 { 4475 int argreg; 4476 int float_argreg; 4477 int argnum; 4478 int len = 0; 4479 int stack_offset = 0; 4480 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4481 CORE_ADDR func_addr = find_function_addr (function, NULL); 4482 int regsize = mips_abi_regsize (gdbarch); 4483 4484 /* For shared libraries, "t9" needs to point at the function 4485 address. */ 4486 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4487 4488 /* Set the return address register to point to the entry point of 4489 the program, where a breakpoint lies in wait. */ 4490 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4491 4492 /* First ensure that the stack and structure return address (if any) 4493 are properly aligned. The stack has to be at least 64-bit 4494 aligned even on 32-bit machines, because doubles must be 64-bit 4495 aligned. For n32 and n64, stack frames need to be 128-bit 4496 aligned, so we round to this widest known alignment. */ 4497 4498 sp = align_down (sp, 16); 4499 struct_addr = align_down (struct_addr, 16); 4500 4501 /* Now make space on the stack for the args. We allocate more 4502 than necessary for EABI, because the first few arguments are 4503 passed in registers, but that's OK. */ 4504 for (argnum = 0; argnum < nargs; argnum++) 4505 len += align_up (TYPE_LENGTH (value_type (args[argnum])), regsize); 4506 sp -= align_up (len, 16); 4507 4508 if (mips_debug) 4509 fprintf_unfiltered (gdb_stdlog, 4510 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", 4511 paddress (gdbarch, sp), (long) align_up (len, 16)); 4512 4513 /* Initialize the integer and float register pointers. */ 4514 argreg = MIPS_A0_REGNUM; 4515 float_argreg = mips_fpa0_regnum (gdbarch); 4516 4517 /* The struct_return pointer occupies the first parameter-passing reg. */ 4518 if (struct_return) 4519 { 4520 if (mips_debug) 4521 fprintf_unfiltered (gdb_stdlog, 4522 "mips_eabi_push_dummy_call: " 4523 "struct_return reg=%d %s\n", 4524 argreg, paddress (gdbarch, struct_addr)); 4525 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4526 } 4527 4528 /* Now load as many as possible of the first arguments into 4529 registers, and push the rest onto the stack. Loop thru args 4530 from first to last. */ 4531 for (argnum = 0; argnum < nargs; argnum++) 4532 { 4533 const gdb_byte *val; 4534 gdb_byte valbuf[MAX_REGISTER_SIZE]; 4535 struct value *arg = args[argnum]; 4536 struct type *arg_type = check_typedef (value_type (arg)); 4537 int len = TYPE_LENGTH (arg_type); 4538 enum type_code typecode = TYPE_CODE (arg_type); 4539 4540 if (mips_debug) 4541 fprintf_unfiltered (gdb_stdlog, 4542 "mips_eabi_push_dummy_call: %d len=%d type=%d", 4543 argnum + 1, len, (int) typecode); 4544 4545 /* The EABI passes structures that do not fit in a register by 4546 reference. */ 4547 if (len > regsize 4548 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 4549 { 4550 store_unsigned_integer (valbuf, regsize, byte_order, 4551 value_address (arg)); 4552 typecode = TYPE_CODE_PTR; 4553 len = regsize; 4554 val = valbuf; 4555 if (mips_debug) 4556 fprintf_unfiltered (gdb_stdlog, " push"); 4557 } 4558 else 4559 val = value_contents (arg); 4560 4561 /* 32-bit ABIs always start floating point arguments in an 4562 even-numbered floating point register. Round the FP register 4563 up before the check to see if there are any FP registers 4564 left. Non MIPS_EABI targets also pass the FP in the integer 4565 registers so also round up normal registers. */ 4566 if (regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) 4567 { 4568 if ((float_argreg & 1)) 4569 float_argreg++; 4570 } 4571 4572 /* Floating point arguments passed in registers have to be 4573 treated specially. On 32-bit architectures, doubles 4574 are passed in register pairs; the even register gets 4575 the low word, and the odd register gets the high word. 4576 On non-EABI processors, the first two floating point arguments are 4577 also copied to general registers, because MIPS16 functions 4578 don't use float registers for arguments. This duplication of 4579 arguments in general registers can't hurt non-MIPS16 functions 4580 because those registers are normally skipped. */ 4581 /* MIPS_EABI squeezes a struct that contains a single floating 4582 point value into an FP register instead of pushing it onto the 4583 stack. */ 4584 if (fp_register_arg_p (gdbarch, typecode, arg_type) 4585 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 4586 { 4587 /* EABI32 will pass doubles in consecutive registers, even on 4588 64-bit cores. At one time, we used to check the size of 4589 `float_argreg' to determine whether or not to pass doubles 4590 in consecutive registers, but this is not sufficient for 4591 making the ABI determination. */ 4592 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) 4593 { 4594 int low_offset = gdbarch_byte_order (gdbarch) 4595 == BFD_ENDIAN_BIG ? 4 : 0; 4596 long regval; 4597 4598 /* Write the low word of the double to the even register(s). */ 4599 regval = extract_signed_integer (val + low_offset, 4600 4, byte_order); 4601 if (mips_debug) 4602 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4603 float_argreg, phex (regval, 4)); 4604 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4605 4606 /* Write the high word of the double to the odd register(s). */ 4607 regval = extract_signed_integer (val + 4 - low_offset, 4608 4, byte_order); 4609 if (mips_debug) 4610 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4611 float_argreg, phex (regval, 4)); 4612 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4613 } 4614 else 4615 { 4616 /* This is a floating point value that fits entirely 4617 in a single register. */ 4618 /* On 32 bit ABI's the float_argreg is further adjusted 4619 above to ensure that it is even register aligned. */ 4620 LONGEST regval = extract_signed_integer (val, len, byte_order); 4621 if (mips_debug) 4622 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4623 float_argreg, phex (regval, len)); 4624 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4625 } 4626 } 4627 else 4628 { 4629 /* Copy the argument to general registers or the stack in 4630 register-sized pieces. Large arguments are split between 4631 registers and stack. */ 4632 /* Note: structs whose size is not a multiple of regsize 4633 are treated specially: Irix cc passes 4634 them in registers where gcc sometimes puts them on the 4635 stack. For maximum compatibility, we will put them in 4636 both places. */ 4637 int odd_sized_struct = (len > regsize && len % regsize != 0); 4638 4639 /* Note: Floating-point values that didn't fit into an FP 4640 register are only written to memory. */ 4641 while (len > 0) 4642 { 4643 /* Remember if the argument was written to the stack. */ 4644 int stack_used_p = 0; 4645 int partial_len = (len < regsize ? len : regsize); 4646 4647 if (mips_debug) 4648 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 4649 partial_len); 4650 4651 /* Write this portion of the argument to the stack. */ 4652 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 4653 || odd_sized_struct 4654 || fp_register_arg_p (gdbarch, typecode, arg_type)) 4655 { 4656 /* Should shorter than int integer values be 4657 promoted to int before being stored? */ 4658 int longword_offset = 0; 4659 CORE_ADDR addr; 4660 stack_used_p = 1; 4661 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 4662 { 4663 if (regsize == 8 4664 && (typecode == TYPE_CODE_INT 4665 || typecode == TYPE_CODE_PTR 4666 || typecode == TYPE_CODE_FLT) && len <= 4) 4667 longword_offset = regsize - len; 4668 else if ((typecode == TYPE_CODE_STRUCT 4669 || typecode == TYPE_CODE_UNION) 4670 && TYPE_LENGTH (arg_type) < regsize) 4671 longword_offset = regsize - len; 4672 } 4673 4674 if (mips_debug) 4675 { 4676 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 4677 paddress (gdbarch, stack_offset)); 4678 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 4679 paddress (gdbarch, longword_offset)); 4680 } 4681 4682 addr = sp + stack_offset + longword_offset; 4683 4684 if (mips_debug) 4685 { 4686 int i; 4687 fprintf_unfiltered (gdb_stdlog, " @%s ", 4688 paddress (gdbarch, addr)); 4689 for (i = 0; i < partial_len; i++) 4690 { 4691 fprintf_unfiltered (gdb_stdlog, "%02x", 4692 val[i] & 0xff); 4693 } 4694 } 4695 write_memory (addr, val, partial_len); 4696 } 4697 4698 /* Note!!! This is NOT an else clause. Odd sized 4699 structs may go thru BOTH paths. Floating point 4700 arguments will not. */ 4701 /* Write this portion of the argument to a general 4702 purpose register. */ 4703 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) 4704 && !fp_register_arg_p (gdbarch, typecode, arg_type)) 4705 { 4706 LONGEST regval = 4707 extract_signed_integer (val, partial_len, byte_order); 4708 4709 if (mips_debug) 4710 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 4711 argreg, 4712 phex (regval, regsize)); 4713 regcache_cooked_write_signed (regcache, argreg, regval); 4714 argreg++; 4715 } 4716 4717 len -= partial_len; 4718 val += partial_len; 4719 4720 /* Compute the offset into the stack at which we will 4721 copy the next parameter. 4722 4723 In the new EABI (and the NABI32), the stack_offset 4724 only needs to be adjusted when it has been used. */ 4725 4726 if (stack_used_p) 4727 stack_offset += align_up (partial_len, regsize); 4728 } 4729 } 4730 if (mips_debug) 4731 fprintf_unfiltered (gdb_stdlog, "\n"); 4732 } 4733 4734 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 4735 4736 /* Return adjusted stack pointer. */ 4737 return sp; 4738 } 4739 4740 /* Determine the return value convention being used. */ 4741 4742 static enum return_value_convention 4743 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, 4744 struct type *type, struct regcache *regcache, 4745 gdb_byte *readbuf, const gdb_byte *writebuf) 4746 { 4747 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4748 int fp_return_type = 0; 4749 int offset, regnum, xfer; 4750 4751 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) 4752 return RETURN_VALUE_STRUCT_CONVENTION; 4753 4754 /* Floating point type? */ 4755 if (tdep->mips_fpu_type != MIPS_FPU_NONE) 4756 { 4757 if (TYPE_CODE (type) == TYPE_CODE_FLT) 4758 fp_return_type = 1; 4759 /* Structs with a single field of float type 4760 are returned in a floating point register. */ 4761 if ((TYPE_CODE (type) == TYPE_CODE_STRUCT 4762 || TYPE_CODE (type) == TYPE_CODE_UNION) 4763 && TYPE_NFIELDS (type) == 1) 4764 { 4765 struct type *fieldtype = TYPE_FIELD_TYPE (type, 0); 4766 4767 if (TYPE_CODE (check_typedef (fieldtype)) == TYPE_CODE_FLT) 4768 fp_return_type = 1; 4769 } 4770 } 4771 4772 if (fp_return_type) 4773 { 4774 /* A floating-point value belongs in the least significant part 4775 of FP0/FP1. */ 4776 if (mips_debug) 4777 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 4778 regnum = mips_regnum (gdbarch)->fp0; 4779 } 4780 else 4781 { 4782 /* An integer value goes in V0/V1. */ 4783 if (mips_debug) 4784 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); 4785 regnum = MIPS_V0_REGNUM; 4786 } 4787 for (offset = 0; 4788 offset < TYPE_LENGTH (type); 4789 offset += mips_abi_regsize (gdbarch), regnum++) 4790 { 4791 xfer = mips_abi_regsize (gdbarch); 4792 if (offset + xfer > TYPE_LENGTH (type)) 4793 xfer = TYPE_LENGTH (type) - offset; 4794 mips_xfer_register (gdbarch, regcache, 4795 gdbarch_num_regs (gdbarch) + regnum, xfer, 4796 gdbarch_byte_order (gdbarch), readbuf, writebuf, 4797 offset); 4798 } 4799 4800 return RETURN_VALUE_REGISTER_CONVENTION; 4801 } 4802 4803 4804 /* N32/N64 ABI stuff. */ 4805 4806 /* Search for a naturally aligned double at OFFSET inside a struct 4807 ARG_TYPE. The N32 / N64 ABIs pass these in floating point 4808 registers. */ 4809 4810 static int 4811 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, 4812 int offset) 4813 { 4814 int i; 4815 4816 if (TYPE_CODE (arg_type) != TYPE_CODE_STRUCT) 4817 return 0; 4818 4819 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) 4820 return 0; 4821 4822 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) 4823 return 0; 4824 4825 for (i = 0; i < TYPE_NFIELDS (arg_type); i++) 4826 { 4827 int pos; 4828 struct type *field_type; 4829 4830 /* We're only looking at normal fields. */ 4831 if (field_is_static (&TYPE_FIELD (arg_type, i)) 4832 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) 4833 continue; 4834 4835 /* If we have gone past the offset, there is no double to pass. */ 4836 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; 4837 if (pos > offset) 4838 return 0; 4839 4840 field_type = check_typedef (TYPE_FIELD_TYPE (arg_type, i)); 4841 4842 /* If this field is entirely before the requested offset, go 4843 on to the next one. */ 4844 if (pos + TYPE_LENGTH (field_type) <= offset) 4845 continue; 4846 4847 /* If this is our special aligned double, we can stop. */ 4848 if (TYPE_CODE (field_type) == TYPE_CODE_FLT 4849 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) 4850 return 1; 4851 4852 /* This field starts at or before the requested offset, and 4853 overlaps it. If it is a structure, recurse inwards. */ 4854 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); 4855 } 4856 4857 return 0; 4858 } 4859 4860 static CORE_ADDR 4861 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4862 struct regcache *regcache, CORE_ADDR bp_addr, 4863 int nargs, struct value **args, CORE_ADDR sp, 4864 int struct_return, CORE_ADDR struct_addr) 4865 { 4866 int argreg; 4867 int float_argreg; 4868 int argnum; 4869 int len = 0; 4870 int stack_offset = 0; 4871 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4872 CORE_ADDR func_addr = find_function_addr (function, NULL); 4873 4874 /* For shared libraries, "t9" needs to point at the function 4875 address. */ 4876 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4877 4878 /* Set the return address register to point to the entry point of 4879 the program, where a breakpoint lies in wait. */ 4880 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4881 4882 /* First ensure that the stack and structure return address (if any) 4883 are properly aligned. The stack has to be at least 64-bit 4884 aligned even on 32-bit machines, because doubles must be 64-bit 4885 aligned. For n32 and n64, stack frames need to be 128-bit 4886 aligned, so we round to this widest known alignment. */ 4887 4888 sp = align_down (sp, 16); 4889 struct_addr = align_down (struct_addr, 16); 4890 4891 /* Now make space on the stack for the args. */ 4892 for (argnum = 0; argnum < nargs; argnum++) 4893 len += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); 4894 sp -= align_up (len, 16); 4895 4896 if (mips_debug) 4897 fprintf_unfiltered (gdb_stdlog, 4898 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", 4899 paddress (gdbarch, sp), (long) align_up (len, 16)); 4900 4901 /* Initialize the integer and float register pointers. */ 4902 argreg = MIPS_A0_REGNUM; 4903 float_argreg = mips_fpa0_regnum (gdbarch); 4904 4905 /* The struct_return pointer occupies the first parameter-passing reg. */ 4906 if (struct_return) 4907 { 4908 if (mips_debug) 4909 fprintf_unfiltered (gdb_stdlog, 4910 "mips_n32n64_push_dummy_call: " 4911 "struct_return reg=%d %s\n", 4912 argreg, paddress (gdbarch, struct_addr)); 4913 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4914 } 4915 4916 /* Now load as many as possible of the first arguments into 4917 registers, and push the rest onto the stack. Loop thru args 4918 from first to last. */ 4919 for (argnum = 0; argnum < nargs; argnum++) 4920 { 4921 const gdb_byte *val; 4922 struct value *arg = args[argnum]; 4923 struct type *arg_type = check_typedef (value_type (arg)); 4924 int len = TYPE_LENGTH (arg_type); 4925 enum type_code typecode = TYPE_CODE (arg_type); 4926 4927 if (mips_debug) 4928 fprintf_unfiltered (gdb_stdlog, 4929 "mips_n32n64_push_dummy_call: %d len=%d type=%d", 4930 argnum + 1, len, (int) typecode); 4931 4932 val = value_contents (arg); 4933 4934 /* A 128-bit long double value requires an even-odd pair of 4935 floating-point registers. */ 4936 if (len == 16 4937 && fp_register_arg_p (gdbarch, typecode, arg_type) 4938 && (float_argreg & 1)) 4939 { 4940 float_argreg++; 4941 argreg++; 4942 } 4943 4944 if (fp_register_arg_p (gdbarch, typecode, arg_type) 4945 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 4946 { 4947 /* This is a floating point value that fits entirely 4948 in a single register or a pair of registers. */ 4949 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 4950 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); 4951 if (mips_debug) 4952 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4953 float_argreg, phex (regval, reglen)); 4954 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 4955 4956 if (mips_debug) 4957 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 4958 argreg, phex (regval, reglen)); 4959 regcache_cooked_write_unsigned (regcache, argreg, regval); 4960 float_argreg++; 4961 argreg++; 4962 if (len == 16) 4963 { 4964 regval = extract_unsigned_integer (val + reglen, 4965 reglen, byte_order); 4966 if (mips_debug) 4967 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4968 float_argreg, phex (regval, reglen)); 4969 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 4970 4971 if (mips_debug) 4972 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 4973 argreg, phex (regval, reglen)); 4974 regcache_cooked_write_unsigned (regcache, argreg, regval); 4975 float_argreg++; 4976 argreg++; 4977 } 4978 } 4979 else 4980 { 4981 /* Copy the argument to general registers or the stack in 4982 register-sized pieces. Large arguments are split between 4983 registers and stack. */ 4984 /* For N32/N64, structs, unions, or other composite types are 4985 treated as a sequence of doublewords, and are passed in integer 4986 or floating point registers as though they were simple scalar 4987 parameters to the extent that they fit, with any excess on the 4988 stack packed according to the normal memory layout of the 4989 object. 4990 The caller does not reserve space for the register arguments; 4991 the callee is responsible for reserving it if required. */ 4992 /* Note: Floating-point values that didn't fit into an FP 4993 register are only written to memory. */ 4994 while (len > 0) 4995 { 4996 /* Remember if the argument was written to the stack. */ 4997 int stack_used_p = 0; 4998 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 4999 5000 if (mips_debug) 5001 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5002 partial_len); 5003 5004 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5005 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); 5006 5007 /* Write this portion of the argument to the stack. */ 5008 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) 5009 { 5010 /* Should shorter than int integer values be 5011 promoted to int before being stored? */ 5012 int longword_offset = 0; 5013 CORE_ADDR addr; 5014 stack_used_p = 1; 5015 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 5016 { 5017 if ((typecode == TYPE_CODE_INT 5018 || typecode == TYPE_CODE_PTR) 5019 && len <= 4) 5020 longword_offset = MIPS64_REGSIZE - len; 5021 } 5022 5023 if (mips_debug) 5024 { 5025 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 5026 paddress (gdbarch, stack_offset)); 5027 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 5028 paddress (gdbarch, longword_offset)); 5029 } 5030 5031 addr = sp + stack_offset + longword_offset; 5032 5033 if (mips_debug) 5034 { 5035 int i; 5036 fprintf_unfiltered (gdb_stdlog, " @%s ", 5037 paddress (gdbarch, addr)); 5038 for (i = 0; i < partial_len; i++) 5039 { 5040 fprintf_unfiltered (gdb_stdlog, "%02x", 5041 val[i] & 0xff); 5042 } 5043 } 5044 write_memory (addr, val, partial_len); 5045 } 5046 5047 /* Note!!! This is NOT an else clause. Odd sized 5048 structs may go thru BOTH paths. */ 5049 /* Write this portion of the argument to a general 5050 purpose register. */ 5051 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 5052 { 5053 LONGEST regval; 5054 5055 /* Sign extend pointers, 32-bit integers and signed 5056 16-bit and 8-bit integers; everything else is taken 5057 as is. */ 5058 5059 if ((partial_len == 4 5060 && (typecode == TYPE_CODE_PTR 5061 || typecode == TYPE_CODE_INT)) 5062 || (partial_len < 4 5063 && typecode == TYPE_CODE_INT 5064 && !TYPE_UNSIGNED (arg_type))) 5065 regval = extract_signed_integer (val, partial_len, 5066 byte_order); 5067 else 5068 regval = extract_unsigned_integer (val, partial_len, 5069 byte_order); 5070 5071 /* A non-floating-point argument being passed in a 5072 general register. If a struct or union, and if 5073 the remaining length is smaller than the register 5074 size, we have to adjust the register value on 5075 big endian targets. 5076 5077 It does not seem to be necessary to do the 5078 same for integral types. */ 5079 5080 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5081 && partial_len < MIPS64_REGSIZE 5082 && (typecode == TYPE_CODE_STRUCT 5083 || typecode == TYPE_CODE_UNION)) 5084 regval <<= ((MIPS64_REGSIZE - partial_len) 5085 * TARGET_CHAR_BIT); 5086 5087 if (mips_debug) 5088 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 5089 argreg, 5090 phex (regval, MIPS64_REGSIZE)); 5091 regcache_cooked_write_unsigned (regcache, argreg, regval); 5092 5093 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, 5094 TYPE_LENGTH (arg_type) - len)) 5095 { 5096 if (mips_debug) 5097 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", 5098 float_argreg, 5099 phex (regval, MIPS64_REGSIZE)); 5100 regcache_cooked_write_unsigned (regcache, float_argreg, 5101 regval); 5102 } 5103 5104 float_argreg++; 5105 argreg++; 5106 } 5107 5108 len -= partial_len; 5109 val += partial_len; 5110 5111 /* Compute the offset into the stack at which we will 5112 copy the next parameter. 5113 5114 In N32 (N64?), the stack_offset only needs to be 5115 adjusted when it has been used. */ 5116 5117 if (stack_used_p) 5118 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 5119 } 5120 } 5121 if (mips_debug) 5122 fprintf_unfiltered (gdb_stdlog, "\n"); 5123 } 5124 5125 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5126 5127 /* Return adjusted stack pointer. */ 5128 return sp; 5129 } 5130 5131 static enum return_value_convention 5132 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, 5133 struct type *type, struct regcache *regcache, 5134 gdb_byte *readbuf, const gdb_byte *writebuf) 5135 { 5136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5137 5138 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 5139 5140 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 5141 if needed), as appropriate for the type. Composite results (struct, 5142 union, or array) are returned in $2/$f0 and $3/$f2 according to the 5143 following rules: 5144 5145 * A struct with only one or two floating point fields is returned in $f0 5146 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX 5147 case. 5148 5149 * Any other composite results of at most 128 bits are returned in 5150 $2 (first 64 bits) and $3 (remainder, if necessary). 5151 5152 * Larger composite results are handled by converting the function to a 5153 procedure with an implicit first parameter, which is a pointer to an area 5154 reserved by the caller to receive the result. [The o32-bit ABI requires 5155 that all composite results be handled by conversion to implicit first 5156 parameters. The MIPS/SGI Fortran implementation has always made a 5157 specific exception to return COMPLEX results in the floating point 5158 registers.] */ 5159 5160 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) 5161 return RETURN_VALUE_STRUCT_CONVENTION; 5162 else if (TYPE_CODE (type) == TYPE_CODE_FLT 5163 && TYPE_LENGTH (type) == 16 5164 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5165 { 5166 /* A 128-bit floating-point value fills both $f0 and $f2. The 5167 two registers are used in the same as memory order, so the 5168 eight bytes with the lower memory address are in $f0. */ 5169 if (mips_debug) 5170 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); 5171 mips_xfer_register (gdbarch, regcache, 5172 (gdbarch_num_regs (gdbarch) 5173 + mips_regnum (gdbarch)->fp0), 5174 8, gdbarch_byte_order (gdbarch), 5175 readbuf, writebuf, 0); 5176 mips_xfer_register (gdbarch, regcache, 5177 (gdbarch_num_regs (gdbarch) 5178 + mips_regnum (gdbarch)->fp0 + 2), 5179 8, gdbarch_byte_order (gdbarch), 5180 readbuf ? readbuf + 8 : readbuf, 5181 writebuf ? writebuf + 8 : writebuf, 0); 5182 return RETURN_VALUE_REGISTER_CONVENTION; 5183 } 5184 else if (TYPE_CODE (type) == TYPE_CODE_FLT 5185 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5186 { 5187 /* A single or double floating-point value that fits in FP0. */ 5188 if (mips_debug) 5189 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 5190 mips_xfer_register (gdbarch, regcache, 5191 (gdbarch_num_regs (gdbarch) 5192 + mips_regnum (gdbarch)->fp0), 5193 TYPE_LENGTH (type), 5194 gdbarch_byte_order (gdbarch), 5195 readbuf, writebuf, 0); 5196 return RETURN_VALUE_REGISTER_CONVENTION; 5197 } 5198 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 5199 && TYPE_NFIELDS (type) <= 2 5200 && TYPE_NFIELDS (type) >= 1 5201 && ((TYPE_NFIELDS (type) == 1 5202 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) 5203 == TYPE_CODE_FLT)) 5204 || (TYPE_NFIELDS (type) == 2 5205 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 0))) 5206 == TYPE_CODE_FLT) 5207 && (TYPE_CODE (check_typedef (TYPE_FIELD_TYPE (type, 1))) 5208 == TYPE_CODE_FLT)))) 5209 { 5210 /* A struct that contains one or two floats. Each value is part 5211 in the least significant part of their floating point 5212 register (or GPR, for soft float). */ 5213 int regnum; 5214 int field; 5215 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE 5216 ? mips_regnum (gdbarch)->fp0 5217 : MIPS_V0_REGNUM); 5218 field < TYPE_NFIELDS (type); field++, regnum += 2) 5219 { 5220 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) 5221 / TARGET_CHAR_BIT); 5222 if (mips_debug) 5223 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 5224 offset); 5225 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)) == 16) 5226 { 5227 /* A 16-byte long double field goes in two consecutive 5228 registers. */ 5229 mips_xfer_register (gdbarch, regcache, 5230 gdbarch_num_regs (gdbarch) + regnum, 5231 8, 5232 gdbarch_byte_order (gdbarch), 5233 readbuf, writebuf, offset); 5234 mips_xfer_register (gdbarch, regcache, 5235 gdbarch_num_regs (gdbarch) + regnum + 1, 5236 8, 5237 gdbarch_byte_order (gdbarch), 5238 readbuf, writebuf, offset + 8); 5239 } 5240 else 5241 mips_xfer_register (gdbarch, regcache, 5242 gdbarch_num_regs (gdbarch) + regnum, 5243 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), 5244 gdbarch_byte_order (gdbarch), 5245 readbuf, writebuf, offset); 5246 } 5247 return RETURN_VALUE_REGISTER_CONVENTION; 5248 } 5249 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 5250 || TYPE_CODE (type) == TYPE_CODE_UNION 5251 || TYPE_CODE (type) == TYPE_CODE_ARRAY) 5252 { 5253 /* A composite type. Extract the left justified value, 5254 regardless of the byte order. I.e. DO NOT USE 5255 mips_xfer_lower. */ 5256 int offset; 5257 int regnum; 5258 for (offset = 0, regnum = MIPS_V0_REGNUM; 5259 offset < TYPE_LENGTH (type); 5260 offset += register_size (gdbarch, regnum), regnum++) 5261 { 5262 int xfer = register_size (gdbarch, regnum); 5263 if (offset + xfer > TYPE_LENGTH (type)) 5264 xfer = TYPE_LENGTH (type) - offset; 5265 if (mips_debug) 5266 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 5267 offset, xfer, regnum); 5268 mips_xfer_register (gdbarch, regcache, 5269 gdbarch_num_regs (gdbarch) + regnum, 5270 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, 5271 offset); 5272 } 5273 return RETURN_VALUE_REGISTER_CONVENTION; 5274 } 5275 else 5276 { 5277 /* A scalar extract each part but least-significant-byte 5278 justified. */ 5279 int offset; 5280 int regnum; 5281 for (offset = 0, regnum = MIPS_V0_REGNUM; 5282 offset < TYPE_LENGTH (type); 5283 offset += register_size (gdbarch, regnum), regnum++) 5284 { 5285 int xfer = register_size (gdbarch, regnum); 5286 if (offset + xfer > TYPE_LENGTH (type)) 5287 xfer = TYPE_LENGTH (type) - offset; 5288 if (mips_debug) 5289 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5290 offset, xfer, regnum); 5291 mips_xfer_register (gdbarch, regcache, 5292 gdbarch_num_regs (gdbarch) + regnum, 5293 xfer, gdbarch_byte_order (gdbarch), 5294 readbuf, writebuf, offset); 5295 } 5296 return RETURN_VALUE_REGISTER_CONVENTION; 5297 } 5298 } 5299 5300 /* Which registers to use for passing floating-point values between 5301 function calls, one of floating-point, general and both kinds of 5302 registers. O32 and O64 use different register kinds for standard 5303 MIPS and MIPS16 code; to make the handling of cases where we may 5304 not know what kind of code is being used (e.g. no debug information) 5305 easier we sometimes use both kinds. */ 5306 5307 enum mips_fval_reg 5308 { 5309 mips_fval_fpr, 5310 mips_fval_gpr, 5311 mips_fval_both 5312 }; 5313 5314 /* O32 ABI stuff. */ 5315 5316 static CORE_ADDR 5317 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5318 struct regcache *regcache, CORE_ADDR bp_addr, 5319 int nargs, struct value **args, CORE_ADDR sp, 5320 int struct_return, CORE_ADDR struct_addr) 5321 { 5322 int argreg; 5323 int float_argreg; 5324 int argnum; 5325 int len = 0; 5326 int stack_offset = 0; 5327 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5328 CORE_ADDR func_addr = find_function_addr (function, NULL); 5329 5330 /* For shared libraries, "t9" needs to point at the function 5331 address. */ 5332 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5333 5334 /* Set the return address register to point to the entry point of 5335 the program, where a breakpoint lies in wait. */ 5336 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5337 5338 /* First ensure that the stack and structure return address (if any) 5339 are properly aligned. The stack has to be at least 64-bit 5340 aligned even on 32-bit machines, because doubles must be 64-bit 5341 aligned. For n32 and n64, stack frames need to be 128-bit 5342 aligned, so we round to this widest known alignment. */ 5343 5344 sp = align_down (sp, 16); 5345 struct_addr = align_down (struct_addr, 16); 5346 5347 /* Now make space on the stack for the args. */ 5348 for (argnum = 0; argnum < nargs; argnum++) 5349 { 5350 struct type *arg_type = check_typedef (value_type (args[argnum])); 5351 5352 /* Align to double-word if necessary. */ 5353 if (mips_type_needs_double_align (arg_type)) 5354 len = align_up (len, MIPS32_REGSIZE * 2); 5355 /* Allocate space on the stack. */ 5356 len += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); 5357 } 5358 sp -= align_up (len, 16); 5359 5360 if (mips_debug) 5361 fprintf_unfiltered (gdb_stdlog, 5362 "mips_o32_push_dummy_call: sp=%s allocated %ld\n", 5363 paddress (gdbarch, sp), (long) align_up (len, 16)); 5364 5365 /* Initialize the integer and float register pointers. */ 5366 argreg = MIPS_A0_REGNUM; 5367 float_argreg = mips_fpa0_regnum (gdbarch); 5368 5369 /* The struct_return pointer occupies the first parameter-passing reg. */ 5370 if (struct_return) 5371 { 5372 if (mips_debug) 5373 fprintf_unfiltered (gdb_stdlog, 5374 "mips_o32_push_dummy_call: " 5375 "struct_return reg=%d %s\n", 5376 argreg, paddress (gdbarch, struct_addr)); 5377 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5378 stack_offset += MIPS32_REGSIZE; 5379 } 5380 5381 /* Now load as many as possible of the first arguments into 5382 registers, and push the rest onto the stack. Loop thru args 5383 from first to last. */ 5384 for (argnum = 0; argnum < nargs; argnum++) 5385 { 5386 const gdb_byte *val; 5387 struct value *arg = args[argnum]; 5388 struct type *arg_type = check_typedef (value_type (arg)); 5389 int len = TYPE_LENGTH (arg_type); 5390 enum type_code typecode = TYPE_CODE (arg_type); 5391 5392 if (mips_debug) 5393 fprintf_unfiltered (gdb_stdlog, 5394 "mips_o32_push_dummy_call: %d len=%d type=%d", 5395 argnum + 1, len, (int) typecode); 5396 5397 val = value_contents (arg); 5398 5399 /* 32-bit ABIs always start floating point arguments in an 5400 even-numbered floating point register. Round the FP register 5401 up before the check to see if there are any FP registers 5402 left. O32 targets also pass the FP in the integer registers 5403 so also round up normal registers. */ 5404 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5405 { 5406 if ((float_argreg & 1)) 5407 float_argreg++; 5408 } 5409 5410 /* Floating point arguments passed in registers have to be 5411 treated specially. On 32-bit architectures, doubles are 5412 passed in register pairs; the even FP register gets the 5413 low word, and the odd FP register gets the high word. 5414 On O32, the first two floating point arguments are also 5415 copied to general registers, following their memory order, 5416 because MIPS16 functions don't use float registers for 5417 arguments. This duplication of arguments in general 5418 registers can't hurt non-MIPS16 functions, because those 5419 registers are normally skipped. */ 5420 5421 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5422 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 5423 { 5424 if (register_size (gdbarch, float_argreg) < 8 && len == 8) 5425 { 5426 int freg_offset = gdbarch_byte_order (gdbarch) 5427 == BFD_ENDIAN_BIG ? 1 : 0; 5428 unsigned long regval; 5429 5430 /* First word. */ 5431 regval = extract_unsigned_integer (val, 4, byte_order); 5432 if (mips_debug) 5433 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5434 float_argreg + freg_offset, 5435 phex (regval, 4)); 5436 regcache_cooked_write_unsigned (regcache, 5437 float_argreg++ + freg_offset, 5438 regval); 5439 if (mips_debug) 5440 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5441 argreg, phex (regval, 4)); 5442 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5443 5444 /* Second word. */ 5445 regval = extract_unsigned_integer (val + 4, 4, byte_order); 5446 if (mips_debug) 5447 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5448 float_argreg - freg_offset, 5449 phex (regval, 4)); 5450 regcache_cooked_write_unsigned (regcache, 5451 float_argreg++ - freg_offset, 5452 regval); 5453 if (mips_debug) 5454 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5455 argreg, phex (regval, 4)); 5456 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5457 } 5458 else 5459 { 5460 /* This is a floating point value that fits entirely 5461 in a single register. */ 5462 /* On 32 bit ABI's the float_argreg is further adjusted 5463 above to ensure that it is even register aligned. */ 5464 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 5465 if (mips_debug) 5466 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5467 float_argreg, phex (regval, len)); 5468 regcache_cooked_write_unsigned (regcache, 5469 float_argreg++, regval); 5470 /* Although two FP registers are reserved for each 5471 argument, only one corresponding integer register is 5472 reserved. */ 5473 if (mips_debug) 5474 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5475 argreg, phex (regval, len)); 5476 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5477 } 5478 /* Reserve space for the FP register. */ 5479 stack_offset += align_up (len, MIPS32_REGSIZE); 5480 } 5481 else 5482 { 5483 /* Copy the argument to general registers or the stack in 5484 register-sized pieces. Large arguments are split between 5485 registers and stack. */ 5486 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE 5487 are treated specially: Irix cc passes 5488 them in registers where gcc sometimes puts them on the 5489 stack. For maximum compatibility, we will put them in 5490 both places. */ 5491 int odd_sized_struct = (len > MIPS32_REGSIZE 5492 && len % MIPS32_REGSIZE != 0); 5493 /* Structures should be aligned to eight bytes (even arg registers) 5494 on MIPS_ABI_O32, if their first member has double precision. */ 5495 if (mips_type_needs_double_align (arg_type)) 5496 { 5497 if ((argreg & 1)) 5498 { 5499 argreg++; 5500 stack_offset += MIPS32_REGSIZE; 5501 } 5502 } 5503 while (len > 0) 5504 { 5505 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); 5506 5507 if (mips_debug) 5508 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5509 partial_len); 5510 5511 /* Write this portion of the argument to the stack. */ 5512 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 5513 || odd_sized_struct) 5514 { 5515 /* Should shorter than int integer values be 5516 promoted to int before being stored? */ 5517 int longword_offset = 0; 5518 CORE_ADDR addr; 5519 5520 if (mips_debug) 5521 { 5522 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 5523 paddress (gdbarch, stack_offset)); 5524 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 5525 paddress (gdbarch, longword_offset)); 5526 } 5527 5528 addr = sp + stack_offset + longword_offset; 5529 5530 if (mips_debug) 5531 { 5532 int i; 5533 fprintf_unfiltered (gdb_stdlog, " @%s ", 5534 paddress (gdbarch, addr)); 5535 for (i = 0; i < partial_len; i++) 5536 { 5537 fprintf_unfiltered (gdb_stdlog, "%02x", 5538 val[i] & 0xff); 5539 } 5540 } 5541 write_memory (addr, val, partial_len); 5542 } 5543 5544 /* Note!!! This is NOT an else clause. Odd sized 5545 structs may go thru BOTH paths. */ 5546 /* Write this portion of the argument to a general 5547 purpose register. */ 5548 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 5549 { 5550 LONGEST regval = extract_signed_integer (val, partial_len, 5551 byte_order); 5552 /* Value may need to be sign extended, because 5553 mips_isa_regsize() != mips_abi_regsize(). */ 5554 5555 /* A non-floating-point argument being passed in a 5556 general register. If a struct or union, and if 5557 the remaining length is smaller than the register 5558 size, we have to adjust the register value on 5559 big endian targets. 5560 5561 It does not seem to be necessary to do the 5562 same for integral types. 5563 5564 Also don't do this adjustment on O64 binaries. 5565 5566 cagney/2001-07-23: gdb/179: Also, GCC, when 5567 outputting LE O32 with sizeof (struct) < 5568 mips_abi_regsize(), generates a left shift 5569 as part of storing the argument in a register 5570 (the left shift isn't generated when 5571 sizeof (struct) >= mips_abi_regsize()). Since 5572 it is quite possible that this is GCC 5573 contradicting the LE/O32 ABI, GDB has not been 5574 adjusted to accommodate this. Either someone 5575 needs to demonstrate that the LE/O32 ABI 5576 specifies such a left shift OR this new ABI gets 5577 identified as such and GDB gets tweaked 5578 accordingly. */ 5579 5580 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5581 && partial_len < MIPS32_REGSIZE 5582 && (typecode == TYPE_CODE_STRUCT 5583 || typecode == TYPE_CODE_UNION)) 5584 regval <<= ((MIPS32_REGSIZE - partial_len) 5585 * TARGET_CHAR_BIT); 5586 5587 if (mips_debug) 5588 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 5589 argreg, 5590 phex (regval, MIPS32_REGSIZE)); 5591 regcache_cooked_write_unsigned (regcache, argreg, regval); 5592 argreg++; 5593 5594 /* Prevent subsequent floating point arguments from 5595 being passed in floating point registers. */ 5596 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; 5597 } 5598 5599 len -= partial_len; 5600 val += partial_len; 5601 5602 /* Compute the offset into the stack at which we will 5603 copy the next parameter. 5604 5605 In older ABIs, the caller reserved space for 5606 registers that contained arguments. This was loosely 5607 refered to as their "home". Consequently, space is 5608 always allocated. */ 5609 5610 stack_offset += align_up (partial_len, MIPS32_REGSIZE); 5611 } 5612 } 5613 if (mips_debug) 5614 fprintf_unfiltered (gdb_stdlog, "\n"); 5615 } 5616 5617 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5618 5619 /* Return adjusted stack pointer. */ 5620 return sp; 5621 } 5622 5623 static enum return_value_convention 5624 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, 5625 struct type *type, struct regcache *regcache, 5626 gdb_byte *readbuf, const gdb_byte *writebuf) 5627 { 5628 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 5629 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 5630 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5631 enum mips_fval_reg fval_reg; 5632 5633 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 5634 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 5635 || TYPE_CODE (type) == TYPE_CODE_UNION 5636 || TYPE_CODE (type) == TYPE_CODE_ARRAY) 5637 return RETURN_VALUE_STRUCT_CONVENTION; 5638 else if (TYPE_CODE (type) == TYPE_CODE_FLT 5639 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5640 { 5641 /* A single-precision floating-point value. If reading in or copying, 5642 then we get it from/put it to FP0 for standard MIPS code or GPR2 5643 for MIPS16 code. If writing out only, then we put it to both FP0 5644 and GPR2. We do not support reading in with no function known, if 5645 this safety check ever triggers, then we'll have to try harder. */ 5646 gdb_assert (function || !readbuf); 5647 if (mips_debug) 5648 switch (fval_reg) 5649 { 5650 case mips_fval_fpr: 5651 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 5652 break; 5653 case mips_fval_gpr: 5654 fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); 5655 break; 5656 case mips_fval_both: 5657 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); 5658 break; 5659 } 5660 if (fval_reg != mips_fval_gpr) 5661 mips_xfer_register (gdbarch, regcache, 5662 (gdbarch_num_regs (gdbarch) 5663 + mips_regnum (gdbarch)->fp0), 5664 TYPE_LENGTH (type), 5665 gdbarch_byte_order (gdbarch), 5666 readbuf, writebuf, 0); 5667 if (fval_reg != mips_fval_fpr) 5668 mips_xfer_register (gdbarch, regcache, 5669 gdbarch_num_regs (gdbarch) + 2, 5670 TYPE_LENGTH (type), 5671 gdbarch_byte_order (gdbarch), 5672 readbuf, writebuf, 0); 5673 return RETURN_VALUE_REGISTER_CONVENTION; 5674 } 5675 else if (TYPE_CODE (type) == TYPE_CODE_FLT 5676 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5677 { 5678 /* A double-precision floating-point value. If reading in or copying, 5679 then we get it from/put it to FP1 and FP0 for standard MIPS code or 5680 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it 5681 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with 5682 no function known, if this safety check ever triggers, then we'll 5683 have to try harder. */ 5684 gdb_assert (function || !readbuf); 5685 if (mips_debug) 5686 switch (fval_reg) 5687 { 5688 case mips_fval_fpr: 5689 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); 5690 break; 5691 case mips_fval_gpr: 5692 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); 5693 break; 5694 case mips_fval_both: 5695 fprintf_unfiltered (gdb_stderr, 5696 "Return float in $fp1/$fp0 and $2/$3\n"); 5697 break; 5698 } 5699 if (fval_reg != mips_fval_gpr) 5700 { 5701 /* The most significant part goes in FP1, and the least significant 5702 in FP0. */ 5703 switch (gdbarch_byte_order (gdbarch)) 5704 { 5705 case BFD_ENDIAN_LITTLE: 5706 mips_xfer_register (gdbarch, regcache, 5707 (gdbarch_num_regs (gdbarch) 5708 + mips_regnum (gdbarch)->fp0 + 0), 5709 4, gdbarch_byte_order (gdbarch), 5710 readbuf, writebuf, 0); 5711 mips_xfer_register (gdbarch, regcache, 5712 (gdbarch_num_regs (gdbarch) 5713 + mips_regnum (gdbarch)->fp0 + 1), 5714 4, gdbarch_byte_order (gdbarch), 5715 readbuf, writebuf, 4); 5716 break; 5717 case BFD_ENDIAN_BIG: 5718 mips_xfer_register (gdbarch, regcache, 5719 (gdbarch_num_regs (gdbarch) 5720 + mips_regnum (gdbarch)->fp0 + 1), 5721 4, gdbarch_byte_order (gdbarch), 5722 readbuf, writebuf, 0); 5723 mips_xfer_register (gdbarch, regcache, 5724 (gdbarch_num_regs (gdbarch) 5725 + mips_regnum (gdbarch)->fp0 + 0), 5726 4, gdbarch_byte_order (gdbarch), 5727 readbuf, writebuf, 4); 5728 break; 5729 default: 5730 internal_error (__FILE__, __LINE__, _("bad switch")); 5731 } 5732 } 5733 if (fval_reg != mips_fval_fpr) 5734 { 5735 /* The two 32-bit parts are always placed in GPR2 and GPR3 5736 following these registers' memory order. */ 5737 mips_xfer_register (gdbarch, regcache, 5738 gdbarch_num_regs (gdbarch) + 2, 5739 4, gdbarch_byte_order (gdbarch), 5740 readbuf, writebuf, 0); 5741 mips_xfer_register (gdbarch, regcache, 5742 gdbarch_num_regs (gdbarch) + 3, 5743 4, gdbarch_byte_order (gdbarch), 5744 readbuf, writebuf, 4); 5745 } 5746 return RETURN_VALUE_REGISTER_CONVENTION; 5747 } 5748 #if 0 5749 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 5750 && TYPE_NFIELDS (type) <= 2 5751 && TYPE_NFIELDS (type) >= 1 5752 && ((TYPE_NFIELDS (type) == 1 5753 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 5754 == TYPE_CODE_FLT)) 5755 || (TYPE_NFIELDS (type) == 2 5756 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) 5757 == TYPE_CODE_FLT) 5758 && (TYPE_CODE (TYPE_FIELD_TYPE (type, 1)) 5759 == TYPE_CODE_FLT))) 5760 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5761 { 5762 /* A struct that contains one or two floats. Each value is part 5763 in the least significant part of their floating point 5764 register.. */ 5765 gdb_byte reg[MAX_REGISTER_SIZE]; 5766 int regnum; 5767 int field; 5768 for (field = 0, regnum = mips_regnum (gdbarch)->fp0; 5769 field < TYPE_NFIELDS (type); field++, regnum += 2) 5770 { 5771 int offset = (FIELD_BITPOS (TYPE_FIELDS (type)[field]) 5772 / TARGET_CHAR_BIT); 5773 if (mips_debug) 5774 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 5775 offset); 5776 mips_xfer_register (gdbarch, regcache, 5777 gdbarch_num_regs (gdbarch) + regnum, 5778 TYPE_LENGTH (TYPE_FIELD_TYPE (type, field)), 5779 gdbarch_byte_order (gdbarch), 5780 readbuf, writebuf, offset); 5781 } 5782 return RETURN_VALUE_REGISTER_CONVENTION; 5783 } 5784 #endif 5785 #if 0 5786 else if (TYPE_CODE (type) == TYPE_CODE_STRUCT 5787 || TYPE_CODE (type) == TYPE_CODE_UNION) 5788 { 5789 /* A structure or union. Extract the left justified value, 5790 regardless of the byte order. I.e. DO NOT USE 5791 mips_xfer_lower. */ 5792 int offset; 5793 int regnum; 5794 for (offset = 0, regnum = MIPS_V0_REGNUM; 5795 offset < TYPE_LENGTH (type); 5796 offset += register_size (gdbarch, regnum), regnum++) 5797 { 5798 int xfer = register_size (gdbarch, regnum); 5799 if (offset + xfer > TYPE_LENGTH (type)) 5800 xfer = TYPE_LENGTH (type) - offset; 5801 if (mips_debug) 5802 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 5803 offset, xfer, regnum); 5804 mips_xfer_register (gdbarch, regcache, 5805 gdbarch_num_regs (gdbarch) + regnum, xfer, 5806 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); 5807 } 5808 return RETURN_VALUE_REGISTER_CONVENTION; 5809 } 5810 #endif 5811 else 5812 { 5813 /* A scalar extract each part but least-significant-byte 5814 justified. o32 thinks registers are 4 byte, regardless of 5815 the ISA. */ 5816 int offset; 5817 int regnum; 5818 for (offset = 0, regnum = MIPS_V0_REGNUM; 5819 offset < TYPE_LENGTH (type); 5820 offset += MIPS32_REGSIZE, regnum++) 5821 { 5822 int xfer = MIPS32_REGSIZE; 5823 if (offset + xfer > TYPE_LENGTH (type)) 5824 xfer = TYPE_LENGTH (type) - offset; 5825 if (mips_debug) 5826 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5827 offset, xfer, regnum); 5828 mips_xfer_register (gdbarch, regcache, 5829 gdbarch_num_regs (gdbarch) + regnum, xfer, 5830 gdbarch_byte_order (gdbarch), 5831 readbuf, writebuf, offset); 5832 } 5833 return RETURN_VALUE_REGISTER_CONVENTION; 5834 } 5835 } 5836 5837 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 5838 ABI. */ 5839 5840 static CORE_ADDR 5841 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5842 struct regcache *regcache, CORE_ADDR bp_addr, 5843 int nargs, 5844 struct value **args, CORE_ADDR sp, 5845 int struct_return, CORE_ADDR struct_addr) 5846 { 5847 int argreg; 5848 int float_argreg; 5849 int argnum; 5850 int len = 0; 5851 int stack_offset = 0; 5852 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5853 CORE_ADDR func_addr = find_function_addr (function, NULL); 5854 5855 /* For shared libraries, "t9" needs to point at the function 5856 address. */ 5857 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5858 5859 /* Set the return address register to point to the entry point of 5860 the program, where a breakpoint lies in wait. */ 5861 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5862 5863 /* First ensure that the stack and structure return address (if any) 5864 are properly aligned. The stack has to be at least 64-bit 5865 aligned even on 32-bit machines, because doubles must be 64-bit 5866 aligned. For n32 and n64, stack frames need to be 128-bit 5867 aligned, so we round to this widest known alignment. */ 5868 5869 sp = align_down (sp, 16); 5870 struct_addr = align_down (struct_addr, 16); 5871 5872 /* Now make space on the stack for the args. */ 5873 for (argnum = 0; argnum < nargs; argnum++) 5874 { 5875 struct type *arg_type = check_typedef (value_type (args[argnum])); 5876 5877 /* Allocate space on the stack. */ 5878 len += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); 5879 } 5880 sp -= align_up (len, 16); 5881 5882 if (mips_debug) 5883 fprintf_unfiltered (gdb_stdlog, 5884 "mips_o64_push_dummy_call: sp=%s allocated %ld\n", 5885 paddress (gdbarch, sp), (long) align_up (len, 16)); 5886 5887 /* Initialize the integer and float register pointers. */ 5888 argreg = MIPS_A0_REGNUM; 5889 float_argreg = mips_fpa0_regnum (gdbarch); 5890 5891 /* The struct_return pointer occupies the first parameter-passing reg. */ 5892 if (struct_return) 5893 { 5894 if (mips_debug) 5895 fprintf_unfiltered (gdb_stdlog, 5896 "mips_o64_push_dummy_call: " 5897 "struct_return reg=%d %s\n", 5898 argreg, paddress (gdbarch, struct_addr)); 5899 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5900 stack_offset += MIPS64_REGSIZE; 5901 } 5902 5903 /* Now load as many as possible of the first arguments into 5904 registers, and push the rest onto the stack. Loop thru args 5905 from first to last. */ 5906 for (argnum = 0; argnum < nargs; argnum++) 5907 { 5908 const gdb_byte *val; 5909 struct value *arg = args[argnum]; 5910 struct type *arg_type = check_typedef (value_type (arg)); 5911 int len = TYPE_LENGTH (arg_type); 5912 enum type_code typecode = TYPE_CODE (arg_type); 5913 5914 if (mips_debug) 5915 fprintf_unfiltered (gdb_stdlog, 5916 "mips_o64_push_dummy_call: %d len=%d type=%d", 5917 argnum + 1, len, (int) typecode); 5918 5919 val = value_contents (arg); 5920 5921 /* Floating point arguments passed in registers have to be 5922 treated specially. On 32-bit architectures, doubles are 5923 passed in register pairs; the even FP register gets the 5924 low word, and the odd FP register gets the high word. 5925 On O64, the first two floating point arguments are also 5926 copied to general registers, because MIPS16 functions 5927 don't use float registers for arguments. This duplication 5928 of arguments in general registers can't hurt non-MIPS16 5929 functions because those registers are normally skipped. */ 5930 5931 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5932 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 5933 { 5934 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 5935 if (mips_debug) 5936 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5937 float_argreg, phex (regval, len)); 5938 regcache_cooked_write_unsigned (regcache, float_argreg++, regval); 5939 if (mips_debug) 5940 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5941 argreg, phex (regval, len)); 5942 regcache_cooked_write_unsigned (regcache, argreg, regval); 5943 argreg++; 5944 /* Reserve space for the FP register. */ 5945 stack_offset += align_up (len, MIPS64_REGSIZE); 5946 } 5947 else 5948 { 5949 /* Copy the argument to general registers or the stack in 5950 register-sized pieces. Large arguments are split between 5951 registers and stack. */ 5952 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE 5953 are treated specially: Irix cc passes them in registers 5954 where gcc sometimes puts them on the stack. For maximum 5955 compatibility, we will put them in both places. */ 5956 int odd_sized_struct = (len > MIPS64_REGSIZE 5957 && len % MIPS64_REGSIZE != 0); 5958 while (len > 0) 5959 { 5960 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 5961 5962 if (mips_debug) 5963 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5964 partial_len); 5965 5966 /* Write this portion of the argument to the stack. */ 5967 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 5968 || odd_sized_struct) 5969 { 5970 /* Should shorter than int integer values be 5971 promoted to int before being stored? */ 5972 int longword_offset = 0; 5973 CORE_ADDR addr; 5974 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 5975 { 5976 if ((typecode == TYPE_CODE_INT 5977 || typecode == TYPE_CODE_PTR 5978 || typecode == TYPE_CODE_FLT) 5979 && len <= 4) 5980 longword_offset = MIPS64_REGSIZE - len; 5981 } 5982 5983 if (mips_debug) 5984 { 5985 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 5986 paddress (gdbarch, stack_offset)); 5987 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 5988 paddress (gdbarch, longword_offset)); 5989 } 5990 5991 addr = sp + stack_offset + longword_offset; 5992 5993 if (mips_debug) 5994 { 5995 int i; 5996 fprintf_unfiltered (gdb_stdlog, " @%s ", 5997 paddress (gdbarch, addr)); 5998 for (i = 0; i < partial_len; i++) 5999 { 6000 fprintf_unfiltered (gdb_stdlog, "%02x", 6001 val[i] & 0xff); 6002 } 6003 } 6004 write_memory (addr, val, partial_len); 6005 } 6006 6007 /* Note!!! This is NOT an else clause. Odd sized 6008 structs may go thru BOTH paths. */ 6009 /* Write this portion of the argument to a general 6010 purpose register. */ 6011 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 6012 { 6013 LONGEST regval = extract_signed_integer (val, partial_len, 6014 byte_order); 6015 /* Value may need to be sign extended, because 6016 mips_isa_regsize() != mips_abi_regsize(). */ 6017 6018 /* A non-floating-point argument being passed in a 6019 general register. If a struct or union, and if 6020 the remaining length is smaller than the register 6021 size, we have to adjust the register value on 6022 big endian targets. 6023 6024 It does not seem to be necessary to do the 6025 same for integral types. */ 6026 6027 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 6028 && partial_len < MIPS64_REGSIZE 6029 && (typecode == TYPE_CODE_STRUCT 6030 || typecode == TYPE_CODE_UNION)) 6031 regval <<= ((MIPS64_REGSIZE - partial_len) 6032 * TARGET_CHAR_BIT); 6033 6034 if (mips_debug) 6035 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 6036 argreg, 6037 phex (regval, MIPS64_REGSIZE)); 6038 regcache_cooked_write_unsigned (regcache, argreg, regval); 6039 argreg++; 6040 6041 /* Prevent subsequent floating point arguments from 6042 being passed in floating point registers. */ 6043 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; 6044 } 6045 6046 len -= partial_len; 6047 val += partial_len; 6048 6049 /* Compute the offset into the stack at which we will 6050 copy the next parameter. 6051 6052 In older ABIs, the caller reserved space for 6053 registers that contained arguments. This was loosely 6054 refered to as their "home". Consequently, space is 6055 always allocated. */ 6056 6057 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 6058 } 6059 } 6060 if (mips_debug) 6061 fprintf_unfiltered (gdb_stdlog, "\n"); 6062 } 6063 6064 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 6065 6066 /* Return adjusted stack pointer. */ 6067 return sp; 6068 } 6069 6070 static enum return_value_convention 6071 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, 6072 struct type *type, struct regcache *regcache, 6073 gdb_byte *readbuf, const gdb_byte *writebuf) 6074 { 6075 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 6076 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 6077 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 6078 enum mips_fval_reg fval_reg; 6079 6080 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 6081 if (TYPE_CODE (type) == TYPE_CODE_STRUCT 6082 || TYPE_CODE (type) == TYPE_CODE_UNION 6083 || TYPE_CODE (type) == TYPE_CODE_ARRAY) 6084 return RETURN_VALUE_STRUCT_CONVENTION; 6085 else if (fp_register_arg_p (gdbarch, TYPE_CODE (type), type)) 6086 { 6087 /* A floating-point value. If reading in or copying, then we get it 6088 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. 6089 If writing out only, then we put it to both FP0 and GPR2. We do 6090 not support reading in with no function known, if this safety 6091 check ever triggers, then we'll have to try harder. */ 6092 gdb_assert (function || !readbuf); 6093 if (mips_debug) 6094 switch (fval_reg) 6095 { 6096 case mips_fval_fpr: 6097 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 6098 break; 6099 case mips_fval_gpr: 6100 fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); 6101 break; 6102 case mips_fval_both: 6103 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); 6104 break; 6105 } 6106 if (fval_reg != mips_fval_gpr) 6107 mips_xfer_register (gdbarch, regcache, 6108 (gdbarch_num_regs (gdbarch) 6109 + mips_regnum (gdbarch)->fp0), 6110 TYPE_LENGTH (type), 6111 gdbarch_byte_order (gdbarch), 6112 readbuf, writebuf, 0); 6113 if (fval_reg != mips_fval_fpr) 6114 mips_xfer_register (gdbarch, regcache, 6115 gdbarch_num_regs (gdbarch) + 2, 6116 TYPE_LENGTH (type), 6117 gdbarch_byte_order (gdbarch), 6118 readbuf, writebuf, 0); 6119 return RETURN_VALUE_REGISTER_CONVENTION; 6120 } 6121 else 6122 { 6123 /* A scalar extract each part but least-significant-byte 6124 justified. */ 6125 int offset; 6126 int regnum; 6127 for (offset = 0, regnum = MIPS_V0_REGNUM; 6128 offset < TYPE_LENGTH (type); 6129 offset += MIPS64_REGSIZE, regnum++) 6130 { 6131 int xfer = MIPS64_REGSIZE; 6132 if (offset + xfer > TYPE_LENGTH (type)) 6133 xfer = TYPE_LENGTH (type) - offset; 6134 if (mips_debug) 6135 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 6136 offset, xfer, regnum); 6137 mips_xfer_register (gdbarch, regcache, 6138 gdbarch_num_regs (gdbarch) + regnum, 6139 xfer, gdbarch_byte_order (gdbarch), 6140 readbuf, writebuf, offset); 6141 } 6142 return RETURN_VALUE_REGISTER_CONVENTION; 6143 } 6144 } 6145 6146 /* Floating point register management. 6147 6148 Background: MIPS1 & 2 fp registers are 32 bits wide. To support 6149 64bit operations, these early MIPS cpus treat fp register pairs 6150 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp 6151 registers and offer a compatibility mode that emulates the MIPS2 fp 6152 model. When operating in MIPS2 fp compat mode, later cpu's split 6153 double precision floats into two 32-bit chunks and store them in 6154 consecutive fp regs. To display 64-bit floats stored in this 6155 fashion, we have to combine 32 bits from f0 and 32 bits from f1. 6156 Throw in user-configurable endianness and you have a real mess. 6157 6158 The way this works is: 6159 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit 6160 double-precision value will be split across two logical registers. 6161 The lower-numbered logical register will hold the low-order bits, 6162 regardless of the processor's endianness. 6163 - If we are on a 64-bit processor, and we are looking for a 6164 single-precision value, it will be in the low ordered bits 6165 of a 64-bit GPR (after mfc1, for example) or a 64-bit register 6166 save slot in memory. 6167 - If we are in 64-bit mode, everything is straightforward. 6168 6169 Note that this code only deals with "live" registers at the top of the 6170 stack. We will attempt to deal with saved registers later, when 6171 the raw/cooked register interface is in place. (We need a general 6172 interface that can deal with dynamic saved register sizes -- fp 6173 regs could be 32 bits wide in one frame and 64 on the frame above 6174 and below). */ 6175 6176 /* Copy a 32-bit single-precision value from the current frame 6177 into rare_buffer. */ 6178 6179 static void 6180 mips_read_fp_register_single (struct frame_info *frame, int regno, 6181 gdb_byte *rare_buffer) 6182 { 6183 struct gdbarch *gdbarch = get_frame_arch (frame); 6184 int raw_size = register_size (gdbarch, regno); 6185 gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); 6186 6187 if (!deprecated_frame_register_read (frame, regno, raw_buffer)) 6188 error (_("can't read register %d (%s)"), 6189 regno, gdbarch_register_name (gdbarch, regno)); 6190 if (raw_size == 8) 6191 { 6192 /* We have a 64-bit value for this register. Find the low-order 6193 32 bits. */ 6194 int offset; 6195 6196 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6197 offset = 4; 6198 else 6199 offset = 0; 6200 6201 memcpy (rare_buffer, raw_buffer + offset, 4); 6202 } 6203 else 6204 { 6205 memcpy (rare_buffer, raw_buffer, 4); 6206 } 6207 } 6208 6209 /* Copy a 64-bit double-precision value from the current frame into 6210 rare_buffer. This may include getting half of it from the next 6211 register. */ 6212 6213 static void 6214 mips_read_fp_register_double (struct frame_info *frame, int regno, 6215 gdb_byte *rare_buffer) 6216 { 6217 struct gdbarch *gdbarch = get_frame_arch (frame); 6218 int raw_size = register_size (gdbarch, regno); 6219 6220 if (raw_size == 8 && !mips2_fp_compat (frame)) 6221 { 6222 /* We have a 64-bit value for this register, and we should use 6223 all 64 bits. */ 6224 if (!deprecated_frame_register_read (frame, regno, rare_buffer)) 6225 error (_("can't read register %d (%s)"), 6226 regno, gdbarch_register_name (gdbarch, regno)); 6227 } 6228 else 6229 { 6230 int rawnum = regno % gdbarch_num_regs (gdbarch); 6231 6232 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) 6233 internal_error (__FILE__, __LINE__, 6234 _("mips_read_fp_register_double: bad access to " 6235 "odd-numbered FP register")); 6236 6237 /* mips_read_fp_register_single will find the correct 32 bits from 6238 each register. */ 6239 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6240 { 6241 mips_read_fp_register_single (frame, regno, rare_buffer + 4); 6242 mips_read_fp_register_single (frame, regno + 1, rare_buffer); 6243 } 6244 else 6245 { 6246 mips_read_fp_register_single (frame, regno, rare_buffer); 6247 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); 6248 } 6249 } 6250 } 6251 6252 static void 6253 mips_print_fp_register (struct ui_file *file, struct frame_info *frame, 6254 int regnum) 6255 { /* Do values for FP (float) regs. */ 6256 struct gdbarch *gdbarch = get_frame_arch (frame); 6257 gdb_byte *raw_buffer; 6258 double doub, flt1; /* Doubles extracted from raw hex data. */ 6259 int inv1, inv2; 6260 6261 raw_buffer 6262 = ((gdb_byte *) 6263 alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); 6264 6265 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); 6266 fprintf_filtered (file, "%*s", 6267 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), 6268 ""); 6269 6270 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) 6271 { 6272 struct value_print_options opts; 6273 6274 /* 4-byte registers: Print hex and floating. Also print even 6275 numbered registers as doubles. */ 6276 mips_read_fp_register_single (frame, regnum, raw_buffer); 6277 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, 6278 raw_buffer, &inv1); 6279 6280 get_formatted_print_options (&opts, 'x'); 6281 print_scalar_formatted (raw_buffer, 6282 builtin_type (gdbarch)->builtin_uint32, 6283 &opts, 'w', file); 6284 6285 fprintf_filtered (file, " flt: "); 6286 if (inv1) 6287 fprintf_filtered (file, " <invalid float> "); 6288 else 6289 fprintf_filtered (file, "%-17.9g", flt1); 6290 6291 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) 6292 { 6293 mips_read_fp_register_double (frame, regnum, raw_buffer); 6294 doub = unpack_double (builtin_type (gdbarch)->builtin_double, 6295 raw_buffer, &inv2); 6296 6297 fprintf_filtered (file, " dbl: "); 6298 if (inv2) 6299 fprintf_filtered (file, "<invalid double>"); 6300 else 6301 fprintf_filtered (file, "%-24.17g", doub); 6302 } 6303 } 6304 else 6305 { 6306 struct value_print_options opts; 6307 6308 /* Eight byte registers: print each one as hex, float and double. */ 6309 mips_read_fp_register_single (frame, regnum, raw_buffer); 6310 flt1 = unpack_double (builtin_type (gdbarch)->builtin_float, 6311 raw_buffer, &inv1); 6312 6313 mips_read_fp_register_double (frame, regnum, raw_buffer); 6314 doub = unpack_double (builtin_type (gdbarch)->builtin_double, 6315 raw_buffer, &inv2); 6316 6317 get_formatted_print_options (&opts, 'x'); 6318 print_scalar_formatted (raw_buffer, 6319 builtin_type (gdbarch)->builtin_uint64, 6320 &opts, 'g', file); 6321 6322 fprintf_filtered (file, " flt: "); 6323 if (inv1) 6324 fprintf_filtered (file, "<invalid float>"); 6325 else 6326 fprintf_filtered (file, "%-17.9g", flt1); 6327 6328 fprintf_filtered (file, " dbl: "); 6329 if (inv2) 6330 fprintf_filtered (file, "<invalid double>"); 6331 else 6332 fprintf_filtered (file, "%-24.17g", doub); 6333 } 6334 } 6335 6336 static void 6337 mips_print_register (struct ui_file *file, struct frame_info *frame, 6338 int regnum) 6339 { 6340 struct gdbarch *gdbarch = get_frame_arch (frame); 6341 struct value_print_options opts; 6342 struct value *val; 6343 6344 if (mips_float_register_p (gdbarch, regnum)) 6345 { 6346 mips_print_fp_register (file, frame, regnum); 6347 return; 6348 } 6349 6350 val = get_frame_register_value (frame, regnum); 6351 6352 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); 6353 6354 /* The problem with printing numeric register names (r26, etc.) is that 6355 the user can't use them on input. Probably the best solution is to 6356 fix it so that either the numeric or the funky (a2, etc.) names 6357 are accepted on input. */ 6358 if (regnum < MIPS_NUMREGS) 6359 fprintf_filtered (file, "(r%d): ", regnum); 6360 else 6361 fprintf_filtered (file, ": "); 6362 6363 get_formatted_print_options (&opts, 'x'); 6364 val_print_scalar_formatted (value_type (val), 6365 value_contents_for_printing (val), 6366 value_embedded_offset (val), 6367 val, 6368 &opts, 0, file); 6369 } 6370 6371 /* Print IEEE exception condition bits in FLAGS. */ 6372 6373 static void 6374 print_fpu_flags (struct ui_file *file, int flags) 6375 { 6376 if (flags & (1 << 0)) 6377 fputs_filtered (" inexact", file); 6378 if (flags & (1 << 1)) 6379 fputs_filtered (" uflow", file); 6380 if (flags & (1 << 2)) 6381 fputs_filtered (" oflow", file); 6382 if (flags & (1 << 3)) 6383 fputs_filtered (" div0", file); 6384 if (flags & (1 << 4)) 6385 fputs_filtered (" inval", file); 6386 if (flags & (1 << 5)) 6387 fputs_filtered (" unimp", file); 6388 fputc_filtered ('\n', file); 6389 } 6390 6391 /* Print interesting information about the floating point processor 6392 (if present) or emulator. */ 6393 6394 static void 6395 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, 6396 struct frame_info *frame, const char *args) 6397 { 6398 int fcsr = mips_regnum (gdbarch)->fp_control_status; 6399 enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); 6400 ULONGEST fcs = 0; 6401 int i; 6402 6403 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) 6404 type = MIPS_FPU_NONE; 6405 6406 fprintf_filtered (file, "fpu type: %s\n", 6407 type == MIPS_FPU_DOUBLE ? "double-precision" 6408 : type == MIPS_FPU_SINGLE ? "single-precision" 6409 : "none / unused"); 6410 6411 if (type == MIPS_FPU_NONE) 6412 return; 6413 6414 fprintf_filtered (file, "reg size: %d bits\n", 6415 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); 6416 6417 fputs_filtered ("cond :", file); 6418 if (fcs & (1 << 23)) 6419 fputs_filtered (" 0", file); 6420 for (i = 1; i <= 7; i++) 6421 if (fcs & (1 << (24 + i))) 6422 fprintf_filtered (file, " %d", i); 6423 fputc_filtered ('\n', file); 6424 6425 fputs_filtered ("cause :", file); 6426 print_fpu_flags (file, (fcs >> 12) & 0x3f); 6427 fputs ("mask :", stdout); 6428 print_fpu_flags (file, (fcs >> 7) & 0x1f); 6429 fputs ("flags :", stdout); 6430 print_fpu_flags (file, (fcs >> 2) & 0x1f); 6431 6432 fputs_filtered ("rounding: ", file); 6433 switch (fcs & 3) 6434 { 6435 case 0: fputs_filtered ("nearest\n", file); break; 6436 case 1: fputs_filtered ("zero\n", file); break; 6437 case 2: fputs_filtered ("+inf\n", file); break; 6438 case 3: fputs_filtered ("-inf\n", file); break; 6439 } 6440 6441 fputs_filtered ("flush :", file); 6442 if (fcs & (1 << 21)) 6443 fputs_filtered (" nearest", file); 6444 if (fcs & (1 << 22)) 6445 fputs_filtered (" override", file); 6446 if (fcs & (1 << 24)) 6447 fputs_filtered (" zero", file); 6448 if ((fcs & (0xb << 21)) == 0) 6449 fputs_filtered (" no", file); 6450 fputc_filtered ('\n', file); 6451 6452 fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); 6453 fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); 6454 fputc_filtered ('\n', file); 6455 6456 default_print_float_info (gdbarch, file, frame, args); 6457 } 6458 6459 /* Replacement for generic do_registers_info. 6460 Print regs in pretty columns. */ 6461 6462 static int 6463 print_fp_register_row (struct ui_file *file, struct frame_info *frame, 6464 int regnum) 6465 { 6466 fprintf_filtered (file, " "); 6467 mips_print_fp_register (file, frame, regnum); 6468 fprintf_filtered (file, "\n"); 6469 return regnum + 1; 6470 } 6471 6472 6473 /* Print a row's worth of GP (int) registers, with name labels above. */ 6474 6475 static int 6476 print_gp_register_row (struct ui_file *file, struct frame_info *frame, 6477 int start_regnum) 6478 { 6479 struct gdbarch *gdbarch = get_frame_arch (frame); 6480 /* Do values for GP (int) regs. */ 6481 gdb_byte raw_buffer[MAX_REGISTER_SIZE]; 6482 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols 6483 per row. */ 6484 int col, byte; 6485 int regnum; 6486 6487 /* For GP registers, we print a separate row of names above the vals. */ 6488 for (col = 0, regnum = start_regnum; 6489 col < ncols && regnum < gdbarch_num_regs (gdbarch) 6490 + gdbarch_num_pseudo_regs (gdbarch); 6491 regnum++) 6492 { 6493 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6494 continue; /* unused register */ 6495 if (mips_float_register_p (gdbarch, regnum)) 6496 break; /* End the row: reached FP register. */ 6497 /* Large registers are handled separately. */ 6498 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6499 { 6500 if (col > 0) 6501 break; /* End the row before this register. */ 6502 6503 /* Print this register on a row by itself. */ 6504 mips_print_register (file, frame, regnum); 6505 fprintf_filtered (file, "\n"); 6506 return regnum + 1; 6507 } 6508 if (col == 0) 6509 fprintf_filtered (file, " "); 6510 fprintf_filtered (file, 6511 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", 6512 gdbarch_register_name (gdbarch, regnum)); 6513 col++; 6514 } 6515 6516 if (col == 0) 6517 return regnum; 6518 6519 /* Print the R0 to R31 names. */ 6520 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) 6521 fprintf_filtered (file, "\n R%-4d", 6522 start_regnum % gdbarch_num_regs (gdbarch)); 6523 else 6524 fprintf_filtered (file, "\n "); 6525 6526 /* Now print the values in hex, 4 or 8 to the row. */ 6527 for (col = 0, regnum = start_regnum; 6528 col < ncols && regnum < gdbarch_num_regs (gdbarch) 6529 + gdbarch_num_pseudo_regs (gdbarch); 6530 regnum++) 6531 { 6532 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6533 continue; /* unused register */ 6534 if (mips_float_register_p (gdbarch, regnum)) 6535 break; /* End row: reached FP register. */ 6536 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6537 break; /* End row: large register. */ 6538 6539 /* OK: get the data in raw format. */ 6540 if (!deprecated_frame_register_read (frame, regnum, raw_buffer)) 6541 error (_("can't read register %d (%s)"), 6542 regnum, gdbarch_register_name (gdbarch, regnum)); 6543 /* pad small registers */ 6544 for (byte = 0; 6545 byte < (mips_abi_regsize (gdbarch) 6546 - register_size (gdbarch, regnum)); byte++) 6547 printf_filtered (" "); 6548 /* Now print the register value in hex, endian order. */ 6549 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6550 for (byte = 6551 register_size (gdbarch, regnum) - register_size (gdbarch, regnum); 6552 byte < register_size (gdbarch, regnum); byte++) 6553 fprintf_filtered (file, "%02x", raw_buffer[byte]); 6554 else 6555 for (byte = register_size (gdbarch, regnum) - 1; 6556 byte >= 0; byte--) 6557 fprintf_filtered (file, "%02x", raw_buffer[byte]); 6558 fprintf_filtered (file, " "); 6559 col++; 6560 } 6561 if (col > 0) /* ie. if we actually printed anything... */ 6562 fprintf_filtered (file, "\n"); 6563 6564 return regnum; 6565 } 6566 6567 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ 6568 6569 static void 6570 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 6571 struct frame_info *frame, int regnum, int all) 6572 { 6573 if (regnum != -1) /* Do one specified register. */ 6574 { 6575 gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); 6576 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') 6577 error (_("Not a valid register for the current processor type")); 6578 6579 mips_print_register (file, frame, regnum); 6580 fprintf_filtered (file, "\n"); 6581 } 6582 else 6583 /* Do all (or most) registers. */ 6584 { 6585 regnum = gdbarch_num_regs (gdbarch); 6586 while (regnum < gdbarch_num_regs (gdbarch) 6587 + gdbarch_num_pseudo_regs (gdbarch)) 6588 { 6589 if (mips_float_register_p (gdbarch, regnum)) 6590 { 6591 if (all) /* True for "INFO ALL-REGISTERS" command. */ 6592 regnum = print_fp_register_row (file, frame, regnum); 6593 else 6594 regnum += MIPS_NUMREGS; /* Skip floating point regs. */ 6595 } 6596 else 6597 regnum = print_gp_register_row (file, frame, regnum); 6598 } 6599 } 6600 } 6601 6602 static int 6603 mips_single_step_through_delay (struct gdbarch *gdbarch, 6604 struct frame_info *frame) 6605 { 6606 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 6607 CORE_ADDR pc = get_frame_pc (frame); 6608 struct address_space *aspace; 6609 enum mips_isa isa; 6610 ULONGEST insn; 6611 int status; 6612 int size; 6613 6614 if ((mips_pc_is_mips (pc) 6615 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) 6616 || (mips_pc_is_micromips (gdbarch, pc) 6617 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) 6618 || (mips_pc_is_mips16 (gdbarch, pc) 6619 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) 6620 return 0; 6621 6622 isa = mips_pc_isa (gdbarch, pc); 6623 /* _has_delay_slot above will have validated the read. */ 6624 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); 6625 size = mips_insn_size (isa, insn); 6626 aspace = get_frame_address_space (frame); 6627 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; 6628 } 6629 6630 /* To skip prologues, I use this predicate. Returns either PC itself 6631 if the code at PC does not look like a function prologue; otherwise 6632 returns an address that (if we're lucky) follows the prologue. If 6633 LENIENT, then we must skip everything which is involved in setting 6634 up the frame (it's OK to skip more, just so long as we don't skip 6635 anything which might clobber the registers which are being saved. 6636 We must skip more in the case where part of the prologue is in the 6637 delay slot of a non-prologue instruction). */ 6638 6639 static CORE_ADDR 6640 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 6641 { 6642 CORE_ADDR limit_pc; 6643 CORE_ADDR func_addr; 6644 6645 /* See if we can determine the end of the prologue via the symbol table. 6646 If so, then return either PC, or the PC after the prologue, whichever 6647 is greater. */ 6648 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 6649 { 6650 CORE_ADDR post_prologue_pc 6651 = skip_prologue_using_sal (gdbarch, func_addr); 6652 if (post_prologue_pc != 0) 6653 return max (pc, post_prologue_pc); 6654 } 6655 6656 /* Can't determine prologue from the symbol table, need to examine 6657 instructions. */ 6658 6659 /* Find an upper limit on the function prologue using the debug 6660 information. If the debug information could not be used to provide 6661 that bound, then use an arbitrary large number as the upper bound. */ 6662 limit_pc = skip_prologue_using_sal (gdbarch, pc); 6663 if (limit_pc == 0) 6664 limit_pc = pc + 100; /* Magic. */ 6665 6666 if (mips_pc_is_mips16 (gdbarch, pc)) 6667 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6668 else if (mips_pc_is_micromips (gdbarch, pc)) 6669 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6670 else 6671 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6672 } 6673 6674 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). 6675 This is a helper function for mips_stack_frame_destroyed_p. */ 6676 6677 static int 6678 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6679 { 6680 CORE_ADDR func_addr = 0, func_end = 0; 6681 6682 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6683 { 6684 /* The MIPS epilogue is max. 12 bytes long. */ 6685 CORE_ADDR addr = func_end - 12; 6686 6687 if (addr < func_addr + 4) 6688 addr = func_addr + 4; 6689 if (pc < addr) 6690 return 0; 6691 6692 for (; pc < func_end; pc += MIPS_INSN32_SIZE) 6693 { 6694 unsigned long high_word; 6695 unsigned long inst; 6696 6697 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 6698 high_word = (inst >> 16) & 0xffff; 6699 6700 if (high_word != 0x27bd /* addiu $sp,$sp,offset */ 6701 && high_word != 0x67bd /* daddiu $sp,$sp,offset */ 6702 && inst != 0x03e00008 /* jr $ra */ 6703 && inst != 0x00000000) /* nop */ 6704 return 0; 6705 } 6706 6707 return 1; 6708 } 6709 6710 return 0; 6711 } 6712 6713 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). 6714 This is a helper function for mips_stack_frame_destroyed_p. */ 6715 6716 static int 6717 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6718 { 6719 CORE_ADDR func_addr = 0; 6720 CORE_ADDR func_end = 0; 6721 CORE_ADDR addr; 6722 ULONGEST insn; 6723 long offset; 6724 int dreg; 6725 int sreg; 6726 int loc; 6727 6728 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6729 return 0; 6730 6731 /* The microMIPS epilogue is max. 12 bytes long. */ 6732 addr = func_end - 12; 6733 6734 if (addr < func_addr + 2) 6735 addr = func_addr + 2; 6736 if (pc < addr) 6737 return 0; 6738 6739 for (; pc < func_end; pc += loc) 6740 { 6741 loc = 0; 6742 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 6743 loc += MIPS_INSN16_SIZE; 6744 switch (mips_insn_size (ISA_MICROMIPS, insn)) 6745 { 6746 /* 32-bit instructions. */ 6747 case 2 * MIPS_INSN16_SIZE: 6748 insn <<= 16; 6749 insn |= mips_fetch_instruction (gdbarch, 6750 ISA_MICROMIPS, pc + loc, NULL); 6751 loc += MIPS_INSN16_SIZE; 6752 switch (micromips_op (insn >> 16)) 6753 { 6754 case 0xc: /* ADDIU: bits 001100 */ 6755 case 0x17: /* DADDIU: bits 010111 */ 6756 sreg = b0s5_reg (insn >> 16); 6757 dreg = b5s5_reg (insn >> 16); 6758 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 6759 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 6760 /* (D)ADDIU $sp, imm */ 6761 && offset >= 0) 6762 break; 6763 return 0; 6764 6765 default: 6766 return 0; 6767 } 6768 break; 6769 6770 /* 16-bit instructions. */ 6771 case MIPS_INSN16_SIZE: 6772 switch (micromips_op (insn)) 6773 { 6774 case 0x3: /* MOVE: bits 000011 */ 6775 sreg = b0s5_reg (insn); 6776 dreg = b5s5_reg (insn); 6777 if (sreg == 0 && dreg == 0) 6778 /* MOVE $zero, $zero aka NOP */ 6779 break; 6780 return 0; 6781 6782 case 0x11: /* POOL16C: bits 010001 */ 6783 if (b5s5_op (insn) == 0x18 6784 /* JRADDIUSP: bits 010011 11000 */ 6785 || (b5s5_op (insn) == 0xd 6786 /* JRC: bits 010011 01101 */ 6787 && b0s5_reg (insn) == MIPS_RA_REGNUM)) 6788 /* JRC $ra */ 6789 break; 6790 return 0; 6791 6792 case 0x13: /* POOL16D: bits 010011 */ 6793 offset = micromips_decode_imm9 (b1s9_imm (insn)); 6794 if ((insn & 0x1) == 0x1 6795 /* ADDIUSP: bits 010011 1 */ 6796 && offset > 0) 6797 break; 6798 return 0; 6799 6800 default: 6801 return 0; 6802 } 6803 } 6804 } 6805 6806 return 1; 6807 } 6808 6809 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). 6810 This is a helper function for mips_stack_frame_destroyed_p. */ 6811 6812 static int 6813 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6814 { 6815 CORE_ADDR func_addr = 0, func_end = 0; 6816 6817 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6818 { 6819 /* The MIPS epilogue is max. 12 bytes long. */ 6820 CORE_ADDR addr = func_end - 12; 6821 6822 if (addr < func_addr + 4) 6823 addr = func_addr + 4; 6824 if (pc < addr) 6825 return 0; 6826 6827 for (; pc < func_end; pc += MIPS_INSN16_SIZE) 6828 { 6829 unsigned short inst; 6830 6831 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); 6832 6833 if ((inst & 0xf800) == 0xf000) /* extend */ 6834 continue; 6835 6836 if (inst != 0x6300 /* addiu $sp,offset */ 6837 && inst != 0xfb00 /* daddiu $sp,$sp,offset */ 6838 && inst != 0xe820 /* jr $ra */ 6839 && inst != 0xe8a0 /* jrc $ra */ 6840 && inst != 0x6500) /* nop */ 6841 return 0; 6842 } 6843 6844 return 1; 6845 } 6846 6847 return 0; 6848 } 6849 6850 /* Implement the stack_frame_destroyed_p gdbarch method. 6851 6852 The epilogue is defined here as the area at the end of a function, 6853 after an instruction which destroys the function's stack frame. */ 6854 6855 static int 6856 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6857 { 6858 if (mips_pc_is_mips16 (gdbarch, pc)) 6859 return mips16_stack_frame_destroyed_p (gdbarch, pc); 6860 else if (mips_pc_is_micromips (gdbarch, pc)) 6861 return micromips_stack_frame_destroyed_p (gdbarch, pc); 6862 else 6863 return mips32_stack_frame_destroyed_p (gdbarch, pc); 6864 } 6865 6866 /* Root of all "set mips "/"show mips " commands. This will eventually be 6867 used for all MIPS-specific commands. */ 6868 6869 static void 6870 show_mips_command (char *args, int from_tty) 6871 { 6872 help_list (showmipscmdlist, "show mips ", all_commands, gdb_stdout); 6873 } 6874 6875 static void 6876 set_mips_command (char *args, int from_tty) 6877 { 6878 printf_unfiltered 6879 ("\"set mips\" must be followed by an appropriate subcommand.\n"); 6880 help_list (setmipscmdlist, "set mips ", all_commands, gdb_stdout); 6881 } 6882 6883 /* Commands to show/set the MIPS FPU type. */ 6884 6885 static void 6886 show_mipsfpu_command (char *args, int from_tty) 6887 { 6888 char *fpu; 6889 6890 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 6891 { 6892 printf_unfiltered 6893 ("The MIPS floating-point coprocessor is unknown " 6894 "because the current architecture is not MIPS.\n"); 6895 return; 6896 } 6897 6898 switch (MIPS_FPU_TYPE (target_gdbarch ())) 6899 { 6900 case MIPS_FPU_SINGLE: 6901 fpu = "single-precision"; 6902 break; 6903 case MIPS_FPU_DOUBLE: 6904 fpu = "double-precision"; 6905 break; 6906 case MIPS_FPU_NONE: 6907 fpu = "absent (none)"; 6908 break; 6909 default: 6910 internal_error (__FILE__, __LINE__, _("bad switch")); 6911 } 6912 if (mips_fpu_type_auto) 6913 printf_unfiltered ("The MIPS floating-point coprocessor " 6914 "is set automatically (currently %s)\n", 6915 fpu); 6916 else 6917 printf_unfiltered 6918 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); 6919 } 6920 6921 6922 static void 6923 set_mipsfpu_command (char *args, int from_tty) 6924 { 6925 printf_unfiltered ("\"set mipsfpu\" must be followed by \"double\", " 6926 "\"single\",\"none\" or \"auto\".\n"); 6927 show_mipsfpu_command (args, from_tty); 6928 } 6929 6930 static void 6931 set_mipsfpu_single_command (char *args, int from_tty) 6932 { 6933 struct gdbarch_info info; 6934 gdbarch_info_init (&info); 6935 mips_fpu_type = MIPS_FPU_SINGLE; 6936 mips_fpu_type_auto = 0; 6937 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6938 instead of relying on globals. Doing that would let generic code 6939 handle the search for this specific architecture. */ 6940 if (!gdbarch_update_p (info)) 6941 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6942 } 6943 6944 static void 6945 set_mipsfpu_double_command (char *args, int from_tty) 6946 { 6947 struct gdbarch_info info; 6948 gdbarch_info_init (&info); 6949 mips_fpu_type = MIPS_FPU_DOUBLE; 6950 mips_fpu_type_auto = 0; 6951 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6952 instead of relying on globals. Doing that would let generic code 6953 handle the search for this specific architecture. */ 6954 if (!gdbarch_update_p (info)) 6955 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6956 } 6957 6958 static void 6959 set_mipsfpu_none_command (char *args, int from_tty) 6960 { 6961 struct gdbarch_info info; 6962 gdbarch_info_init (&info); 6963 mips_fpu_type = MIPS_FPU_NONE; 6964 mips_fpu_type_auto = 0; 6965 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6966 instead of relying on globals. Doing that would let generic code 6967 handle the search for this specific architecture. */ 6968 if (!gdbarch_update_p (info)) 6969 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6970 } 6971 6972 static void 6973 set_mipsfpu_auto_command (char *args, int from_tty) 6974 { 6975 mips_fpu_type_auto = 1; 6976 } 6977 6978 /* Just like reinit_frame_cache, but with the right arguments to be 6979 callable as an sfunc. */ 6980 6981 static void 6982 reinit_frame_cache_sfunc (char *args, int from_tty, 6983 struct cmd_list_element *c) 6984 { 6985 reinit_frame_cache (); 6986 } 6987 6988 static int 6989 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) 6990 { 6991 struct gdbarch *gdbarch = (struct gdbarch *) info->application_data; 6992 6993 /* FIXME: cagney/2003-06-26: Is this even necessary? The 6994 disassembler needs to be able to locally determine the ISA, and 6995 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not 6996 work. */ 6997 if (mips_pc_is_mips16 (gdbarch, memaddr)) 6998 info->mach = bfd_mach_mips16; 6999 else if (mips_pc_is_micromips (gdbarch, memaddr)) 7000 info->mach = bfd_mach_mips_micromips; 7001 7002 /* Round down the instruction address to the appropriate boundary. */ 7003 memaddr &= (info->mach == bfd_mach_mips16 7004 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; 7005 7006 /* Set the disassembler options. */ 7007 if (!info->disassembler_options) 7008 /* This string is not recognized explicitly by the disassembler, 7009 but it tells the disassembler to not try to guess the ABI from 7010 the bfd elf headers, such that, if the user overrides the ABI 7011 of a program linked as NewABI, the disassembly will follow the 7012 register naming conventions specified by the user. */ 7013 info->disassembler_options = "gpr-names=32"; 7014 7015 /* Call the appropriate disassembler based on the target endian-ness. */ 7016 if (info->endian == BFD_ENDIAN_BIG) 7017 return print_insn_big_mips (memaddr, info); 7018 else 7019 return print_insn_little_mips (memaddr, info); 7020 } 7021 7022 static int 7023 gdb_print_insn_mips_n32 (bfd_vma memaddr, struct disassemble_info *info) 7024 { 7025 /* Set up the disassembler info, so that we get the right 7026 register names from libopcodes. */ 7027 info->disassembler_options = "gpr-names=n32"; 7028 info->flavour = bfd_target_elf_flavour; 7029 7030 return gdb_print_insn_mips (memaddr, info); 7031 } 7032 7033 static int 7034 gdb_print_insn_mips_n64 (bfd_vma memaddr, struct disassemble_info *info) 7035 { 7036 /* Set up the disassembler info, so that we get the right 7037 register names from libopcodes. */ 7038 info->disassembler_options = "gpr-names=64"; 7039 info->flavour = bfd_target_elf_flavour; 7040 7041 return gdb_print_insn_mips (memaddr, info); 7042 } 7043 7044 /* This function implements gdbarch_breakpoint_from_pc. It uses the 7045 program counter value to determine whether a 16- or 32-bit breakpoint 7046 should be used. It returns a pointer to a string of bytes that encode a 7047 breakpoint instruction, stores the length of the string to *lenptr, and 7048 adjusts pc (if necessary) to point to the actual memory location where 7049 the breakpoint should be inserted. */ 7050 7051 static const gdb_byte * 7052 mips_breakpoint_from_pc (struct gdbarch *gdbarch, 7053 CORE_ADDR *pcptr, int *lenptr) 7054 { 7055 CORE_ADDR pc = *pcptr; 7056 7057 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 7058 { 7059 if (mips_pc_is_mips16 (gdbarch, pc)) 7060 { 7061 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; 7062 *pcptr = unmake_compact_addr (pc); 7063 *lenptr = sizeof (mips16_big_breakpoint); 7064 return mips16_big_breakpoint; 7065 } 7066 else if (mips_pc_is_micromips (gdbarch, pc)) 7067 { 7068 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; 7069 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; 7070 ULONGEST insn; 7071 int err; 7072 int size; 7073 7074 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err); 7075 size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn); 7076 *pcptr = unmake_compact_addr (pc); 7077 *lenptr = size; 7078 return (size == 2) ? micromips16_big_breakpoint 7079 : micromips32_big_breakpoint; 7080 } 7081 else 7082 { 7083 /* The IDT board uses an unusual breakpoint value, and 7084 sometimes gets confused when it sees the usual MIPS 7085 breakpoint instruction. */ 7086 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; 7087 static gdb_byte pmon_big_breakpoint[] = { 0, 0, 0, 0xd }; 7088 static gdb_byte idt_big_breakpoint[] = { 0, 0, 0x0a, 0xd }; 7089 /* Likewise, IRIX appears to expect a different breakpoint, 7090 although this is not apparent until you try to use pthreads. */ 7091 static gdb_byte irix_big_breakpoint[] = { 0, 0, 0, 0xd }; 7092 7093 *lenptr = sizeof (big_breakpoint); 7094 7095 if (strcmp (target_shortname, "mips") == 0) 7096 return idt_big_breakpoint; 7097 else if (strcmp (target_shortname, "ddb") == 0 7098 || strcmp (target_shortname, "pmon") == 0 7099 || strcmp (target_shortname, "lsi") == 0) 7100 return pmon_big_breakpoint; 7101 else if (gdbarch_osabi (gdbarch) == GDB_OSABI_IRIX) 7102 return irix_big_breakpoint; 7103 else 7104 return big_breakpoint; 7105 } 7106 } 7107 else 7108 { 7109 if (mips_pc_is_mips16 (gdbarch, pc)) 7110 { 7111 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; 7112 *pcptr = unmake_compact_addr (pc); 7113 *lenptr = sizeof (mips16_little_breakpoint); 7114 return mips16_little_breakpoint; 7115 } 7116 else if (mips_pc_is_micromips (gdbarch, pc)) 7117 { 7118 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; 7119 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; 7120 ULONGEST insn; 7121 int err; 7122 int size; 7123 7124 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &err); 7125 size = err ? 2 : mips_insn_size (ISA_MICROMIPS, insn); 7126 *pcptr = unmake_compact_addr (pc); 7127 *lenptr = size; 7128 return (size == 2) ? micromips16_little_breakpoint 7129 : micromips32_little_breakpoint; 7130 } 7131 else 7132 { 7133 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; 7134 static gdb_byte pmon_little_breakpoint[] = { 0xd, 0, 0, 0 }; 7135 static gdb_byte idt_little_breakpoint[] = { 0xd, 0x0a, 0, 0 }; 7136 7137 *lenptr = sizeof (little_breakpoint); 7138 7139 if (strcmp (target_shortname, "mips") == 0) 7140 return idt_little_breakpoint; 7141 else if (strcmp (target_shortname, "ddb") == 0 7142 || strcmp (target_shortname, "pmon") == 0 7143 || strcmp (target_shortname, "lsi") == 0) 7144 return pmon_little_breakpoint; 7145 else 7146 return little_breakpoint; 7147 } 7148 } 7149 } 7150 7151 /* Determine the remote breakpoint kind suitable for the PC. The following 7152 kinds are used: 7153 7154 * 2 -- 16-bit MIPS16 mode breakpoint, 7155 7156 * 3 -- 16-bit microMIPS mode breakpoint, 7157 7158 * 4 -- 32-bit standard MIPS mode breakpoint, 7159 7160 * 5 -- 32-bit microMIPS mode breakpoint. */ 7161 7162 static void 7163 mips_remote_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, 7164 int *kindptr) 7165 { 7166 CORE_ADDR pc = *pcptr; 7167 7168 if (mips_pc_is_mips16 (gdbarch, pc)) 7169 { 7170 *pcptr = unmake_compact_addr (pc); 7171 *kindptr = 2; 7172 } 7173 else if (mips_pc_is_micromips (gdbarch, pc)) 7174 { 7175 ULONGEST insn; 7176 int status; 7177 int size; 7178 7179 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); 7180 size = status ? 2 : mips_insn_size (ISA_MICROMIPS, insn) == 2 ? 2 : 4; 7181 *pcptr = unmake_compact_addr (pc); 7182 *kindptr = size | 1; 7183 } 7184 else 7185 *kindptr = 4; 7186 } 7187 7188 /* Return non-zero if the standard MIPS instruction INST has a branch 7189 delay slot (i.e. it is a jump or branch instruction). This function 7190 is based on mips32_next_pc. */ 7191 7192 static int 7193 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) 7194 { 7195 int op; 7196 int rs; 7197 int rt; 7198 7199 op = itype_op (inst); 7200 if ((inst & 0xe0000000) != 0) 7201 { 7202 rs = itype_rs (inst); 7203 rt = itype_rt (inst); 7204 return (is_octeon_bbit_op (op, gdbarch) 7205 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 7206 || op == 29 /* JALX: bits 011101 */ 7207 || (op == 17 7208 && (rs == 8 7209 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 7210 || (rs == 9 && (rt & 0x2) == 0) 7211 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ 7212 || (rs == 10 && (rt & 0x2) == 0)))); 7213 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ 7214 } 7215 else 7216 switch (op & 0x07) /* extract bits 28,27,26 */ 7217 { 7218 case 0: /* SPECIAL */ 7219 op = rtype_funct (inst); 7220 return (op == 8 /* JR */ 7221 || op == 9); /* JALR */ 7222 break; /* end SPECIAL */ 7223 case 1: /* REGIMM */ 7224 rs = itype_rs (inst); 7225 rt = itype_rt (inst); /* branch condition */ 7226 return ((rt & 0xc) == 0 7227 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ 7228 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ 7229 || ((rt & 0x1e) == 0x1c && rs == 0)); 7230 /* BPOSGE32, BPOSGE64: bits 1110x */ 7231 break; /* end REGIMM */ 7232 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ 7233 return 1; 7234 break; 7235 } 7236 } 7237 7238 /* Return non-zero if a standard MIPS instruction at ADDR has a branch 7239 delay slot (i.e. it is a jump or branch instruction). */ 7240 7241 static int 7242 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) 7243 { 7244 ULONGEST insn; 7245 int status; 7246 7247 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); 7248 if (status) 7249 return 0; 7250 7251 return mips32_instruction_has_delay_slot (gdbarch, insn); 7252 } 7253 7254 /* Return non-zero if the microMIPS instruction INSN, comprising the 7255 16-bit major opcode word in the high 16 bits and any second word 7256 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact 7257 jump or branch instruction). The instruction must be 32-bit if 7258 MUSTBE32 is set or can be any instruction otherwise. */ 7259 7260 static int 7261 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) 7262 { 7263 ULONGEST major = insn >> 16; 7264 7265 switch (micromips_op (major)) 7266 { 7267 /* 16-bit instructions. */ 7268 case 0x33: /* B16: bits 110011 */ 7269 case 0x2b: /* BNEZ16: bits 101011 */ 7270 case 0x23: /* BEQZ16: bits 100011 */ 7271 return !mustbe32; 7272 case 0x11: /* POOL16C: bits 010001 */ 7273 return (!mustbe32 7274 && ((b5s5_op (major) == 0xc 7275 /* JR16: bits 010001 01100 */ 7276 || (b5s5_op (major) & 0x1e) == 0xe))); 7277 /* JALR16, JALRS16: bits 010001 0111x */ 7278 /* 32-bit instructions. */ 7279 case 0x3d: /* JAL: bits 111101 */ 7280 case 0x3c: /* JALX: bits 111100 */ 7281 case 0x35: /* J: bits 110101 */ 7282 case 0x2d: /* BNE: bits 101101 */ 7283 case 0x25: /* BEQ: bits 100101 */ 7284 case 0x1d: /* JALS: bits 011101 */ 7285 return 1; 7286 case 0x10: /* POOL32I: bits 010000 */ 7287 return ((b5s5_op (major) & 0x1c) == 0x0 7288 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 7289 || (b5s5_op (major) & 0x1d) == 0x4 7290 /* BLEZ, BGTZ: bits 010000 001x0 */ 7291 || (b5s5_op (major) & 0x1d) == 0x11 7292 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 7293 || ((b5s5_op (major) & 0x1e) == 0x14 7294 && (major & 0x3) == 0x0) 7295 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 7296 || (b5s5_op (major) & 0x1e) == 0x1a 7297 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 7298 || ((b5s5_op (major) & 0x1e) == 0x1c 7299 && (major & 0x3) == 0x0) 7300 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 7301 || ((b5s5_op (major) & 0x1c) == 0x1c 7302 && (major & 0x3) == 0x1)); 7303 /* BC1ANY*: bits 010000 111xx xxx01 */ 7304 case 0x0: /* POOL32A: bits 000000 */ 7305 return (b0s6_op (insn) == 0x3c 7306 /* POOL32Axf: bits 000000 ... 111100 */ 7307 && (b6s10_ext (insn) & 0x2bf) == 0x3c); 7308 /* JALR, JALR.HB: 000000 000x111100 111100 */ 7309 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 7310 default: 7311 return 0; 7312 } 7313 } 7314 7315 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay 7316 slot (i.e. it is a non-compact jump instruction). The instruction 7317 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7318 7319 static int 7320 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7321 CORE_ADDR addr, int mustbe32) 7322 { 7323 ULONGEST insn; 7324 int status; 7325 int size; 7326 7327 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7328 if (status) 7329 return 0; 7330 size = mips_insn_size (ISA_MICROMIPS, insn); 7331 insn <<= 16; 7332 if (size == 2 * MIPS_INSN16_SIZE) 7333 { 7334 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7335 if (status) 7336 return 0; 7337 } 7338 7339 return micromips_instruction_has_delay_slot (insn, mustbe32); 7340 } 7341 7342 /* Return non-zero if the MIPS16 instruction INST, which must be 7343 a 32-bit instruction if MUSTBE32 is set or can be any instruction 7344 otherwise, has a branch delay slot (i.e. it is a non-compact jump 7345 instruction). This function is based on mips16_next_pc. */ 7346 7347 static int 7348 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) 7349 { 7350 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ 7351 return !mustbe32; 7352 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ 7353 } 7354 7355 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay 7356 slot (i.e. it is a non-compact jump instruction). The instruction 7357 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7358 7359 static int 7360 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7361 CORE_ADDR addr, int mustbe32) 7362 { 7363 unsigned short insn; 7364 int status; 7365 7366 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); 7367 if (status) 7368 return 0; 7369 7370 return mips16_instruction_has_delay_slot (insn, mustbe32); 7371 } 7372 7373 /* Calculate the starting address of the MIPS memory segment BPADDR is in. 7374 This assumes KSSEG exists. */ 7375 7376 static CORE_ADDR 7377 mips_segment_boundary (CORE_ADDR bpaddr) 7378 { 7379 CORE_ADDR mask = CORE_ADDR_MAX; 7380 int segsize; 7381 7382 if (sizeof (CORE_ADDR) == 8) 7383 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid 7384 a compiler warning produced where CORE_ADDR is a 32-bit type even 7385 though in that case this is dead code). */ 7386 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) 7387 { 7388 case 3: 7389 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) 7390 segsize = 29; /* 32-bit compatibility segment */ 7391 else 7392 segsize = 62; /* xkseg */ 7393 break; 7394 case 2: /* xkphys */ 7395 segsize = 59; 7396 break; 7397 default: /* xksseg (1), xkuseg/kuseg (0) */ 7398 segsize = 62; 7399 break; 7400 } 7401 else if (bpaddr & 0x80000000) /* kernel segment */ 7402 segsize = 29; 7403 else 7404 segsize = 31; /* user segment */ 7405 mask <<= segsize; 7406 return bpaddr & mask; 7407 } 7408 7409 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting 7410 it backwards if necessary. Return the address of the new location. */ 7411 7412 static CORE_ADDR 7413 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) 7414 { 7415 CORE_ADDR prev_addr; 7416 CORE_ADDR boundary; 7417 CORE_ADDR func_addr; 7418 7419 /* If a breakpoint is set on the instruction in a branch delay slot, 7420 GDB gets confused. When the breakpoint is hit, the PC isn't on 7421 the instruction in the branch delay slot, the PC will point to 7422 the branch instruction. Since the PC doesn't match any known 7423 breakpoints, GDB reports a trap exception. 7424 7425 There are two possible fixes for this problem. 7426 7427 1) When the breakpoint gets hit, see if the BD bit is set in the 7428 Cause register (which indicates the last exception occurred in a 7429 branch delay slot). If the BD bit is set, fix the PC to point to 7430 the instruction in the branch delay slot. 7431 7432 2) When the user sets the breakpoint, don't allow him to set the 7433 breakpoint on the instruction in the branch delay slot. Instead 7434 move the breakpoint to the branch instruction (which will have 7435 the same result). 7436 7437 The problem with the first solution is that if the user then 7438 single-steps the processor, the branch instruction will get 7439 skipped (since GDB thinks the PC is on the instruction in the 7440 branch delay slot). 7441 7442 So, we'll use the second solution. To do this we need to know if 7443 the instruction we're trying to set the breakpoint on is in the 7444 branch delay slot. */ 7445 7446 boundary = mips_segment_boundary (bpaddr); 7447 7448 /* Make sure we don't scan back before the beginning of the current 7449 function, since we may fetch constant data or insns that look like 7450 a jump. Of course we might do that anyway if the compiler has 7451 moved constants inline. :-( */ 7452 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) 7453 && func_addr > boundary && func_addr <= bpaddr) 7454 boundary = func_addr; 7455 7456 if (mips_pc_is_mips (bpaddr)) 7457 { 7458 if (bpaddr == boundary) 7459 return bpaddr; 7460 7461 /* If the previous instruction has a branch delay slot, we have 7462 to move the breakpoint to the branch instruction. */ 7463 prev_addr = bpaddr - 4; 7464 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) 7465 bpaddr = prev_addr; 7466 } 7467 else 7468 { 7469 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); 7470 CORE_ADDR addr, jmpaddr; 7471 int i; 7472 7473 boundary = unmake_compact_addr (boundary); 7474 7475 /* The only MIPS16 instructions with delay slots are JAL, JALX, 7476 JALR and JR. An absolute JAL/JALX is always 4 bytes long, 7477 so try for that first, then try the 2 byte JALR/JR. 7478 The microMIPS ASE has a whole range of jumps and branches 7479 with delay slots, some of which take 4 bytes and some take 7480 2 bytes, so the idea is the same. 7481 FIXME: We have to assume that bpaddr is not the second half 7482 of an extended instruction. */ 7483 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) 7484 ? micromips_insn_at_pc_has_delay_slot 7485 : mips16_insn_at_pc_has_delay_slot); 7486 7487 jmpaddr = 0; 7488 addr = bpaddr; 7489 for (i = 1; i < 4; i++) 7490 { 7491 if (unmake_compact_addr (addr) == boundary) 7492 break; 7493 addr -= MIPS_INSN16_SIZE; 7494 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) 7495 /* Looks like a JR/JALR at [target-1], but it could be 7496 the second word of a previous JAL/JALX, so record it 7497 and check back one more. */ 7498 jmpaddr = addr; 7499 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) 7500 { 7501 if (i == 2) 7502 /* Looks like a JAL/JALX at [target-2], but it could also 7503 be the second word of a previous JAL/JALX, record it, 7504 and check back one more. */ 7505 jmpaddr = addr; 7506 else 7507 /* Looks like a JAL/JALX at [target-3], so any previously 7508 recorded JAL/JALX or JR/JALR must be wrong, because: 7509 7510 >-3: JAL 7511 -2: JAL-ext (can't be JAL/JALX) 7512 -1: bdslot (can't be JR/JALR) 7513 0: target insn 7514 7515 Of course it could be another JAL-ext which looks 7516 like a JAL, but in that case we'd have broken out 7517 of this loop at [target-2]: 7518 7519 -4: JAL 7520 >-3: JAL-ext 7521 -2: bdslot (can't be jmp) 7522 -1: JR/JALR 7523 0: target insn */ 7524 jmpaddr = 0; 7525 } 7526 else 7527 { 7528 /* Not a jump instruction: if we're at [target-1] this 7529 could be the second word of a JAL/JALX, so continue; 7530 otherwise we're done. */ 7531 if (i > 1) 7532 break; 7533 } 7534 } 7535 7536 if (jmpaddr) 7537 bpaddr = jmpaddr; 7538 } 7539 7540 return bpaddr; 7541 } 7542 7543 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 7544 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ 7545 7546 static int 7547 mips_is_stub_suffix (const char *suffix, int zero) 7548 { 7549 switch (suffix[0]) 7550 { 7551 case '0': 7552 return zero && suffix[1] == '\0'; 7553 case '1': 7554 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); 7555 case '2': 7556 case '5': 7557 case '6': 7558 case '9': 7559 return suffix[1] == '\0'; 7560 default: 7561 return 0; 7562 } 7563 } 7564 7565 /* Return non-zero if MODE is one of the mode infixes used for MIPS16 7566 call stubs, one of sf, df, sc, or dc. */ 7567 7568 static int 7569 mips_is_stub_mode (const char *mode) 7570 { 7571 return ((mode[0] == 's' || mode[0] == 'd') 7572 && (mode[1] == 'f' || mode[1] == 'c')); 7573 } 7574 7575 /* Code at PC is a compiler-generated stub. Such a stub for a function 7576 bar might have a name like __fn_stub_bar, and might look like this: 7577 7578 mfc1 $4, $f13 7579 mfc1 $5, $f12 7580 mfc1 $6, $f15 7581 mfc1 $7, $f14 7582 7583 followed by (or interspersed with): 7584 7585 j bar 7586 7587 or: 7588 7589 lui $25, %hi(bar) 7590 addiu $25, $25, %lo(bar) 7591 jr $25 7592 7593 ($1 may be used in old code; for robustness we accept any register) 7594 or, in PIC code: 7595 7596 lui $28, %hi(_gp_disp) 7597 addiu $28, $28, %lo(_gp_disp) 7598 addu $28, $28, $25 7599 lw $25, %got(bar) 7600 addiu $25, $25, %lo(bar) 7601 jr $25 7602 7603 In the case of a __call_stub_bar stub, the sequence to set up 7604 arguments might look like this: 7605 7606 mtc1 $4, $f13 7607 mtc1 $5, $f12 7608 mtc1 $6, $f15 7609 mtc1 $7, $f14 7610 7611 followed by (or interspersed with) one of the jump sequences above. 7612 7613 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead 7614 of J or JR, respectively, followed by: 7615 7616 mfc1 $2, $f0 7617 mfc1 $3, $f1 7618 jr $18 7619 7620 We are at the beginning of the stub here, and scan down and extract 7621 the target address from the jump immediate instruction or, if a jump 7622 register instruction is used, from the register referred. Return 7623 the value of PC calculated or 0 if inconclusive. 7624 7625 The limit on the search is arbitrarily set to 20 instructions. FIXME. */ 7626 7627 static CORE_ADDR 7628 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) 7629 { 7630 struct gdbarch *gdbarch = get_frame_arch (frame); 7631 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7632 int addrreg = MIPS_ZERO_REGNUM; 7633 CORE_ADDR start_pc = pc; 7634 CORE_ADDR target_pc = 0; 7635 CORE_ADDR addr = 0; 7636 CORE_ADDR gp = 0; 7637 int status = 0; 7638 int i; 7639 7640 for (i = 0; 7641 status == 0 && target_pc == 0 && i < 20; 7642 i++, pc += MIPS_INSN32_SIZE) 7643 { 7644 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 7645 CORE_ADDR imm; 7646 int rt; 7647 int rs; 7648 int rd; 7649 7650 switch (itype_op (inst)) 7651 { 7652 case 0: /* SPECIAL */ 7653 switch (rtype_funct (inst)) 7654 { 7655 case 8: /* JR */ 7656 case 9: /* JALR */ 7657 rs = rtype_rs (inst); 7658 if (rs == MIPS_GP_REGNUM) 7659 target_pc = gp; /* Hmm... */ 7660 else if (rs == addrreg) 7661 target_pc = addr; 7662 break; 7663 7664 case 0x21: /* ADDU */ 7665 rt = rtype_rt (inst); 7666 rs = rtype_rs (inst); 7667 rd = rtype_rd (inst); 7668 if (rd == MIPS_GP_REGNUM 7669 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) 7670 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) 7671 gp += start_pc; 7672 break; 7673 } 7674 break; 7675 7676 case 2: /* J */ 7677 case 3: /* JAL */ 7678 target_pc = jtype_target (inst) << 2; 7679 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 7680 break; 7681 7682 case 9: /* ADDIU */ 7683 rt = itype_rt (inst); 7684 rs = itype_rs (inst); 7685 if (rt == rs) 7686 { 7687 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7688 if (rt == MIPS_GP_REGNUM) 7689 gp += imm; 7690 else if (rt == addrreg) 7691 addr += imm; 7692 } 7693 break; 7694 7695 case 0xf: /* LUI */ 7696 rt = itype_rt (inst); 7697 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; 7698 if (rt == MIPS_GP_REGNUM) 7699 gp = imm; 7700 else if (rt != MIPS_ZERO_REGNUM) 7701 { 7702 addrreg = rt; 7703 addr = imm; 7704 } 7705 break; 7706 7707 case 0x23: /* LW */ 7708 rt = itype_rt (inst); 7709 rs = itype_rs (inst); 7710 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7711 if (gp != 0 && rs == MIPS_GP_REGNUM) 7712 { 7713 gdb_byte buf[4]; 7714 7715 memset (buf, 0, sizeof (buf)); 7716 status = target_read_memory (gp + imm, buf, sizeof (buf)); 7717 addrreg = rt; 7718 addr = extract_signed_integer (buf, sizeof (buf), byte_order); 7719 } 7720 break; 7721 } 7722 } 7723 7724 return target_pc; 7725 } 7726 7727 /* If PC is in a MIPS16 call or return stub, return the address of the 7728 target PC, which is either the callee or the caller. There are several 7729 cases which must be handled: 7730 7731 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7732 and the target PC is in $31 ($ra). 7733 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7734 and the target PC is in $2. 7735 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7736 i.e. before the JALR instruction, this is effectively a call stub 7737 and the target PC is in $2. Otherwise this is effectively 7738 a return stub and the target PC is in $18. 7739 * If the PC is at the start of __call_stub_fp_*, i.e. before the 7740 JAL or JALR instruction, this is effectively a call stub and the 7741 target PC is buried in the instruction stream. Otherwise this 7742 is effectively a return stub and the target PC is in $18. 7743 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call 7744 stub and the target PC is buried in the instruction stream. 7745 7746 See the source code for the stubs in gcc/config/mips/mips16.S, or the 7747 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the 7748 gory details. */ 7749 7750 static CORE_ADDR 7751 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7752 { 7753 struct gdbarch *gdbarch = get_frame_arch (frame); 7754 CORE_ADDR start_addr; 7755 const char *name; 7756 size_t prefixlen; 7757 7758 /* Find the starting address and name of the function containing the PC. */ 7759 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 7760 return 0; 7761 7762 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7763 and the target PC is in $31 ($ra). */ 7764 prefixlen = strlen (mips_str_mips16_ret_stub); 7765 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7766 && mips_is_stub_mode (name + prefixlen) 7767 && name[prefixlen + 2] == '\0') 7768 return get_frame_register_signed 7769 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 7770 7771 /* If the PC is in __mips16_call_stub_*, this is one of the call 7772 call/return stubs. */ 7773 prefixlen = strlen (mips_str_mips16_call_stub); 7774 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) 7775 { 7776 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7777 and the target PC is in $2. */ 7778 if (mips_is_stub_suffix (name + prefixlen, 0)) 7779 return get_frame_register_signed 7780 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7781 7782 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7783 i.e. before the JALR instruction, this is effectively a call stub 7784 and the target PC is in $2. Otherwise this is effectively 7785 a return stub and the target PC is in $18. */ 7786 else if (mips_is_stub_mode (name + prefixlen) 7787 && name[prefixlen + 2] == '_' 7788 && mips_is_stub_suffix (name + prefixlen + 3, 0)) 7789 { 7790 if (pc == start_addr) 7791 /* This is the 'call' part of a call stub. The return 7792 address is in $2. */ 7793 return get_frame_register_signed 7794 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7795 else 7796 /* This is the 'return' part of a call stub. The return 7797 address is in $18. */ 7798 return get_frame_register_signed 7799 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7800 } 7801 else 7802 return 0; /* Not a stub. */ 7803 } 7804 7805 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the 7806 compiler-generated call or call/return stubs. */ 7807 if (startswith (name, mips_str_fn_stub) 7808 || startswith (name, mips_str_call_stub)) 7809 { 7810 if (pc == start_addr) 7811 /* This is the 'call' part of a call stub. Call this helper 7812 to scan through this code for interesting instructions 7813 and determine the final PC. */ 7814 return mips_get_mips16_fn_stub_pc (frame, pc); 7815 else 7816 /* This is the 'return' part of a call stub. The return address 7817 is in $18. */ 7818 return get_frame_register_signed 7819 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7820 } 7821 7822 return 0; /* Not a stub. */ 7823 } 7824 7825 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). 7826 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ 7827 7828 static int 7829 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) 7830 { 7831 CORE_ADDR start_addr; 7832 size_t prefixlen; 7833 7834 /* Find the starting address of the function containing the PC. */ 7835 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) 7836 return 0; 7837 7838 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at 7839 the start, i.e. after the JALR instruction, this is effectively 7840 a return stub. */ 7841 prefixlen = strlen (mips_str_mips16_call_stub); 7842 if (pc != start_addr 7843 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 7844 && mips_is_stub_mode (name + prefixlen) 7845 && name[prefixlen + 2] == '_' 7846 && mips_is_stub_suffix (name + prefixlen + 3, 1)) 7847 return 1; 7848 7849 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after 7850 the JAL or JALR instruction, this is effectively a return stub. */ 7851 prefixlen = strlen (mips_str_call_fp_stub); 7852 if (pc != start_addr 7853 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) 7854 return 1; 7855 7856 /* Consume the .pic. prefix of any PIC stub, this function must return 7857 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub 7858 or the call stub path will trigger in handle_inferior_event causing 7859 it to go astray. */ 7860 prefixlen = strlen (mips_str_pic); 7861 if (strncmp (name, mips_str_pic, prefixlen) == 0) 7862 name += prefixlen; 7863 7864 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ 7865 prefixlen = strlen (mips_str_mips16_ret_stub); 7866 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7867 && mips_is_stub_mode (name + prefixlen) 7868 && name[prefixlen + 2] == '\0') 7869 return 1; 7870 7871 return 0; /* Not a stub. */ 7872 } 7873 7874 /* If the current PC is the start of a non-PIC-to-PIC stub, return the 7875 PC of the stub target. The stub just loads $t9 and jumps to it, 7876 so that $t9 has the correct value at function entry. */ 7877 7878 static CORE_ADDR 7879 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7880 { 7881 struct gdbarch *gdbarch = get_frame_arch (frame); 7882 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7883 struct bound_minimal_symbol msym; 7884 int i; 7885 gdb_byte stub_code[16]; 7886 int32_t stub_words[4]; 7887 7888 /* The stub for foo is named ".pic.foo", and is either two 7889 instructions inserted before foo or a three instruction sequence 7890 which jumps to foo. */ 7891 msym = lookup_minimal_symbol_by_pc (pc); 7892 if (msym.minsym == NULL 7893 || BMSYMBOL_VALUE_ADDRESS (msym) != pc 7894 || MSYMBOL_LINKAGE_NAME (msym.minsym) == NULL 7895 || !startswith (MSYMBOL_LINKAGE_NAME (msym.minsym), ".pic.")) 7896 return 0; 7897 7898 /* A two-instruction header. */ 7899 if (MSYMBOL_SIZE (msym.minsym) == 8) 7900 return pc + 8; 7901 7902 /* A three-instruction (plus delay slot) trampoline. */ 7903 if (MSYMBOL_SIZE (msym.minsym) == 16) 7904 { 7905 if (target_read_memory (pc, stub_code, 16) != 0) 7906 return 0; 7907 for (i = 0; i < 4; i++) 7908 stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 7909 4, byte_order); 7910 7911 /* A stub contains these instructions: 7912 lui t9, %hi(target) 7913 j target 7914 addiu t9, t9, %lo(target) 7915 nop 7916 7917 This works even for N64, since stubs are only generated with 7918 -msym32. */ 7919 if ((stub_words[0] & 0xffff0000U) == 0x3c190000 7920 && (stub_words[1] & 0xfc000000U) == 0x08000000 7921 && (stub_words[2] & 0xffff0000U) == 0x27390000 7922 && stub_words[3] == 0x00000000) 7923 return ((((stub_words[0] & 0x0000ffff) << 16) 7924 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; 7925 } 7926 7927 /* Not a recognized stub. */ 7928 return 0; 7929 } 7930 7931 static CORE_ADDR 7932 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7933 { 7934 CORE_ADDR requested_pc = pc; 7935 CORE_ADDR target_pc; 7936 CORE_ADDR new_pc; 7937 7938 do 7939 { 7940 target_pc = pc; 7941 7942 new_pc = mips_skip_mips16_trampoline_code (frame, pc); 7943 if (new_pc) 7944 pc = new_pc; 7945 7946 new_pc = find_solib_trampoline_target (frame, pc); 7947 if (new_pc) 7948 pc = new_pc; 7949 7950 new_pc = mips_skip_pic_trampoline_code (frame, pc); 7951 if (new_pc) 7952 pc = new_pc; 7953 } 7954 while (pc != target_pc); 7955 7956 return pc != requested_pc ? pc : 0; 7957 } 7958 7959 /* Convert a dbx stab register number (from `r' declaration) to a GDB 7960 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7961 7962 static int 7963 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) 7964 { 7965 int regnum; 7966 if (num >= 0 && num < 32) 7967 regnum = num; 7968 else if (num >= 38 && num < 70) 7969 regnum = num + mips_regnum (gdbarch)->fp0 - 38; 7970 else if (num == 70) 7971 regnum = mips_regnum (gdbarch)->hi; 7972 else if (num == 71) 7973 regnum = mips_regnum (gdbarch)->lo; 7974 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) 7975 regnum = num + mips_regnum (gdbarch)->dspacc - 72; 7976 else 7977 return -1; 7978 return gdbarch_num_regs (gdbarch) + regnum; 7979 } 7980 7981 7982 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * 7983 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7984 7985 static int 7986 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) 7987 { 7988 int regnum; 7989 if (num >= 0 && num < 32) 7990 regnum = num; 7991 else if (num >= 32 && num < 64) 7992 regnum = num + mips_regnum (gdbarch)->fp0 - 32; 7993 else if (num == 64) 7994 regnum = mips_regnum (gdbarch)->hi; 7995 else if (num == 65) 7996 regnum = mips_regnum (gdbarch)->lo; 7997 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) 7998 regnum = num + mips_regnum (gdbarch)->dspacc - 66; 7999 else 8000 return -1; 8001 return gdbarch_num_regs (gdbarch) + regnum; 8002 } 8003 8004 static int 8005 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) 8006 { 8007 /* Only makes sense to supply raw registers. */ 8008 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); 8009 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to 8010 decide if it is valid. Should instead define a standard sim/gdb 8011 register numbering scheme. */ 8012 if (gdbarch_register_name (gdbarch, 8013 gdbarch_num_regs (gdbarch) + regnum) != NULL 8014 && gdbarch_register_name (gdbarch, 8015 gdbarch_num_regs (gdbarch) 8016 + regnum)[0] != '\0') 8017 return regnum; 8018 else 8019 return LEGACY_SIM_REGNO_IGNORE; 8020 } 8021 8022 8023 /* Convert an integer into an address. Extracting the value signed 8024 guarantees a correctly sign extended address. */ 8025 8026 static CORE_ADDR 8027 mips_integer_to_address (struct gdbarch *gdbarch, 8028 struct type *type, const gdb_byte *buf) 8029 { 8030 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 8031 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); 8032 } 8033 8034 /* Dummy virtual frame pointer method. This is no more or less accurate 8035 than most other architectures; we just need to be explicit about it, 8036 because the pseudo-register gdbarch_sp_regnum will otherwise lead to 8037 an assertion failure. */ 8038 8039 static void 8040 mips_virtual_frame_pointer (struct gdbarch *gdbarch, 8041 CORE_ADDR pc, int *reg, LONGEST *offset) 8042 { 8043 *reg = MIPS_SP_REGNUM; 8044 *offset = 0; 8045 } 8046 8047 static void 8048 mips_find_abi_section (bfd *abfd, asection *sect, void *obj) 8049 { 8050 enum mips_abi *abip = (enum mips_abi *) obj; 8051 const char *name = bfd_get_section_name (abfd, sect); 8052 8053 if (*abip != MIPS_ABI_UNKNOWN) 8054 return; 8055 8056 if (!startswith (name, ".mdebug.")) 8057 return; 8058 8059 if (strcmp (name, ".mdebug.abi32") == 0) 8060 *abip = MIPS_ABI_O32; 8061 else if (strcmp (name, ".mdebug.abiN32") == 0) 8062 *abip = MIPS_ABI_N32; 8063 else if (strcmp (name, ".mdebug.abi64") == 0) 8064 *abip = MIPS_ABI_N64; 8065 else if (strcmp (name, ".mdebug.abiO64") == 0) 8066 *abip = MIPS_ABI_O64; 8067 else if (strcmp (name, ".mdebug.eabi32") == 0) 8068 *abip = MIPS_ABI_EABI32; 8069 else if (strcmp (name, ".mdebug.eabi64") == 0) 8070 *abip = MIPS_ABI_EABI64; 8071 else 8072 warning (_("unsupported ABI %s."), name + 8); 8073 } 8074 8075 static void 8076 mips_find_long_section (bfd *abfd, asection *sect, void *obj) 8077 { 8078 int *lbp = (int *) obj; 8079 const char *name = bfd_get_section_name (abfd, sect); 8080 8081 if (startswith (name, ".gcc_compiled_long32")) 8082 *lbp = 32; 8083 else if (startswith (name, ".gcc_compiled_long64")) 8084 *lbp = 64; 8085 else if (startswith (name, ".gcc_compiled_long")) 8086 warning (_("unrecognized .gcc_compiled_longXX")); 8087 } 8088 8089 static enum mips_abi 8090 global_mips_abi (void) 8091 { 8092 int i; 8093 8094 for (i = 0; mips_abi_strings[i] != NULL; i++) 8095 if (mips_abi_strings[i] == mips_abi_string) 8096 return (enum mips_abi) i; 8097 8098 internal_error (__FILE__, __LINE__, _("unknown ABI string")); 8099 } 8100 8101 /* Return the default compressed instruction set, either of MIPS16 8102 or microMIPS, selected when none could have been determined from 8103 the ELF header of the binary being executed (or no binary has been 8104 selected. */ 8105 8106 static enum mips_isa 8107 global_mips_compression (void) 8108 { 8109 int i; 8110 8111 for (i = 0; mips_compression_strings[i] != NULL; i++) 8112 if (mips_compression_strings[i] == mips_compression_string) 8113 return (enum mips_isa) i; 8114 8115 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); 8116 } 8117 8118 static void 8119 mips_register_g_packet_guesses (struct gdbarch *gdbarch) 8120 { 8121 /* If the size matches the set of 32-bit or 64-bit integer registers, 8122 assume that's what we've got. */ 8123 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); 8124 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); 8125 8126 /* If the size matches the full set of registers GDB traditionally 8127 knows about, including floating point, for either 32-bit or 8128 64-bit, assume that's what we've got. */ 8129 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); 8130 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); 8131 8132 /* Otherwise we don't have a useful guess. */ 8133 } 8134 8135 static struct value * 8136 value_of_mips_user_reg (struct frame_info *frame, const void *baton) 8137 { 8138 const int *reg_p = (const int *) baton; 8139 return value_of_register (*reg_p, frame); 8140 } 8141 8142 static struct gdbarch * 8143 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 8144 { 8145 struct gdbarch *gdbarch; 8146 struct gdbarch_tdep *tdep; 8147 int elf_flags; 8148 enum mips_abi mips_abi, found_abi, wanted_abi; 8149 int i, num_regs; 8150 enum mips_fpu_type fpu_type; 8151 struct tdesc_arch_data *tdesc_data = NULL; 8152 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; 8153 const char **reg_names; 8154 struct mips_regnum mips_regnum, *regnum; 8155 enum mips_isa mips_isa; 8156 int dspacc; 8157 int dspctl; 8158 8159 /* Fill in the OS dependent register numbers and names. */ 8160 if (info.osabi == GDB_OSABI_IRIX) 8161 { 8162 mips_regnum.fp0 = 32; 8163 mips_regnum.pc = 64; 8164 mips_regnum.cause = 65; 8165 mips_regnum.badvaddr = 66; 8166 mips_regnum.hi = 67; 8167 mips_regnum.lo = 68; 8168 mips_regnum.fp_control_status = 69; 8169 mips_regnum.fp_implementation_revision = 70; 8170 mips_regnum.dspacc = dspacc = -1; 8171 mips_regnum.dspctl = dspctl = -1; 8172 num_regs = 71; 8173 reg_names = mips_irix_reg_names; 8174 } 8175 else if (info.osabi == GDB_OSABI_LINUX) 8176 { 8177 mips_regnum.fp0 = 38; 8178 mips_regnum.pc = 37; 8179 mips_regnum.cause = 36; 8180 mips_regnum.badvaddr = 35; 8181 mips_regnum.hi = 34; 8182 mips_regnum.lo = 33; 8183 mips_regnum.fp_control_status = 70; 8184 mips_regnum.fp_implementation_revision = 71; 8185 mips_regnum.dspacc = -1; 8186 mips_regnum.dspctl = -1; 8187 dspacc = 72; 8188 dspctl = 78; 8189 num_regs = 90; 8190 reg_names = mips_linux_reg_names; 8191 } 8192 else 8193 { 8194 mips_regnum.lo = MIPS_EMBED_LO_REGNUM; 8195 mips_regnum.hi = MIPS_EMBED_HI_REGNUM; 8196 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; 8197 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; 8198 mips_regnum.pc = MIPS_EMBED_PC_REGNUM; 8199 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; 8200 mips_regnum.fp_control_status = 70; 8201 mips_regnum.fp_implementation_revision = 71; 8202 mips_regnum.dspacc = dspacc = -1; 8203 mips_regnum.dspctl = dspctl = -1; 8204 num_regs = MIPS_LAST_EMBED_REGNUM + 1; 8205 if (info.bfd_arch_info != NULL 8206 && info.bfd_arch_info->mach == bfd_mach_mips3900) 8207 reg_names = mips_tx39_reg_names; 8208 else 8209 reg_names = mips_generic_reg_names; 8210 } 8211 8212 /* Check any target description for validity. */ 8213 if (tdesc_has_registers (info.target_desc)) 8214 { 8215 static const char *const mips_gprs[] = { 8216 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8217 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8218 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8219 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 8220 }; 8221 static const char *const mips_fprs[] = { 8222 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 8223 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 8224 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 8225 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 8226 }; 8227 8228 const struct tdesc_feature *feature; 8229 int valid_p; 8230 8231 feature = tdesc_find_feature (info.target_desc, 8232 "org.gnu.gdb.mips.cpu"); 8233 if (feature == NULL) 8234 return NULL; 8235 8236 tdesc_data = tdesc_data_alloc (); 8237 8238 valid_p = 1; 8239 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) 8240 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 8241 mips_gprs[i]); 8242 8243 8244 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8245 mips_regnum.lo, "lo"); 8246 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8247 mips_regnum.hi, "hi"); 8248 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8249 mips_regnum.pc, "pc"); 8250 8251 if (!valid_p) 8252 { 8253 tdesc_data_cleanup (tdesc_data); 8254 return NULL; 8255 } 8256 8257 feature = tdesc_find_feature (info.target_desc, 8258 "org.gnu.gdb.mips.cp0"); 8259 if (feature == NULL) 8260 { 8261 tdesc_data_cleanup (tdesc_data); 8262 return NULL; 8263 } 8264 8265 valid_p = 1; 8266 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8267 mips_regnum.badvaddr, "badvaddr"); 8268 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8269 MIPS_PS_REGNUM, "status"); 8270 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8271 mips_regnum.cause, "cause"); 8272 8273 if (!valid_p) 8274 { 8275 tdesc_data_cleanup (tdesc_data); 8276 return NULL; 8277 } 8278 8279 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS 8280 backend is not prepared for that, though. */ 8281 feature = tdesc_find_feature (info.target_desc, 8282 "org.gnu.gdb.mips.fpu"); 8283 if (feature == NULL) 8284 { 8285 tdesc_data_cleanup (tdesc_data); 8286 return NULL; 8287 } 8288 8289 valid_p = 1; 8290 for (i = 0; i < 32; i++) 8291 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8292 i + mips_regnum.fp0, mips_fprs[i]); 8293 8294 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8295 mips_regnum.fp_control_status, 8296 "fcsr"); 8297 valid_p 8298 &= tdesc_numbered_register (feature, tdesc_data, 8299 mips_regnum.fp_implementation_revision, 8300 "fir"); 8301 8302 if (!valid_p) 8303 { 8304 tdesc_data_cleanup (tdesc_data); 8305 return NULL; 8306 } 8307 8308 num_regs = mips_regnum.fp_implementation_revision + 1; 8309 8310 if (dspacc >= 0) 8311 { 8312 feature = tdesc_find_feature (info.target_desc, 8313 "org.gnu.gdb.mips.dsp"); 8314 /* The DSP registers are optional; it's OK if they are absent. */ 8315 if (feature != NULL) 8316 { 8317 i = 0; 8318 valid_p = 1; 8319 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8320 dspacc + i++, "hi1"); 8321 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8322 dspacc + i++, "lo1"); 8323 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8324 dspacc + i++, "hi2"); 8325 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8326 dspacc + i++, "lo2"); 8327 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8328 dspacc + i++, "hi3"); 8329 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8330 dspacc + i++, "lo3"); 8331 8332 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8333 dspctl, "dspctl"); 8334 8335 if (!valid_p) 8336 { 8337 tdesc_data_cleanup (tdesc_data); 8338 return NULL; 8339 } 8340 8341 mips_regnum.dspacc = dspacc; 8342 mips_regnum.dspctl = dspctl; 8343 8344 num_regs = mips_regnum.dspctl + 1; 8345 } 8346 } 8347 8348 /* It would be nice to detect an attempt to use a 64-bit ABI 8349 when only 32-bit registers are provided. */ 8350 reg_names = NULL; 8351 } 8352 8353 /* First of all, extract the elf_flags, if available. */ 8354 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8355 elf_flags = elf_elfheader (info.abfd)->e_flags; 8356 else if (arches != NULL) 8357 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; 8358 else 8359 elf_flags = 0; 8360 if (gdbarch_debug) 8361 fprintf_unfiltered (gdb_stdlog, 8362 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); 8363 8364 /* Check ELF_FLAGS to see if it specifies the ABI being used. */ 8365 switch ((elf_flags & EF_MIPS_ABI)) 8366 { 8367 case E_MIPS_ABI_O32: 8368 found_abi = MIPS_ABI_O32; 8369 break; 8370 case E_MIPS_ABI_O64: 8371 found_abi = MIPS_ABI_O64; 8372 break; 8373 case E_MIPS_ABI_EABI32: 8374 found_abi = MIPS_ABI_EABI32; 8375 break; 8376 case E_MIPS_ABI_EABI64: 8377 found_abi = MIPS_ABI_EABI64; 8378 break; 8379 default: 8380 if ((elf_flags & EF_MIPS_ABI2)) 8381 found_abi = MIPS_ABI_N32; 8382 else 8383 found_abi = MIPS_ABI_UNKNOWN; 8384 break; 8385 } 8386 8387 /* GCC creates a pseudo-section whose name describes the ABI. */ 8388 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) 8389 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); 8390 8391 /* If we have no useful BFD information, use the ABI from the last 8392 MIPS architecture (if there is one). */ 8393 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) 8394 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; 8395 8396 /* Try the architecture for any hint of the correct ABI. */ 8397 if (found_abi == MIPS_ABI_UNKNOWN 8398 && info.bfd_arch_info != NULL 8399 && info.bfd_arch_info->arch == bfd_arch_mips) 8400 { 8401 switch (info.bfd_arch_info->mach) 8402 { 8403 case bfd_mach_mips3900: 8404 found_abi = MIPS_ABI_EABI32; 8405 break; 8406 case bfd_mach_mips4100: 8407 case bfd_mach_mips5000: 8408 found_abi = MIPS_ABI_EABI64; 8409 break; 8410 case bfd_mach_mips8000: 8411 case bfd_mach_mips10000: 8412 /* On Irix, ELF64 executables use the N64 ABI. The 8413 pseudo-sections which describe the ABI aren't present 8414 on IRIX. (Even for executables created by gcc.) */ 8415 if (info.abfd != NULL 8416 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8417 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8418 found_abi = MIPS_ABI_N64; 8419 else 8420 found_abi = MIPS_ABI_N32; 8421 break; 8422 } 8423 } 8424 8425 /* Default 64-bit objects to N64 instead of O32. */ 8426 if (found_abi == MIPS_ABI_UNKNOWN 8427 && info.abfd != NULL 8428 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8429 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8430 found_abi = MIPS_ABI_N64; 8431 8432 if (gdbarch_debug) 8433 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", 8434 found_abi); 8435 8436 /* What has the user specified from the command line? */ 8437 wanted_abi = global_mips_abi (); 8438 if (gdbarch_debug) 8439 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", 8440 wanted_abi); 8441 8442 /* Now that we have found what the ABI for this binary would be, 8443 check whether the user is overriding it. */ 8444 if (wanted_abi != MIPS_ABI_UNKNOWN) 8445 mips_abi = wanted_abi; 8446 else if (found_abi != MIPS_ABI_UNKNOWN) 8447 mips_abi = found_abi; 8448 else 8449 mips_abi = MIPS_ABI_O32; 8450 if (gdbarch_debug) 8451 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", 8452 mips_abi); 8453 8454 /* Determine the default compressed ISA. */ 8455 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 8456 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) 8457 mips_isa = ISA_MICROMIPS; 8458 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 8459 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) 8460 mips_isa = ISA_MIPS16; 8461 else 8462 mips_isa = global_mips_compression (); 8463 mips_compression_string = mips_compression_strings[mips_isa]; 8464 8465 /* Also used when doing an architecture lookup. */ 8466 if (gdbarch_debug) 8467 fprintf_unfiltered (gdb_stdlog, 8468 "mips_gdbarch_init: " 8469 "mips64_transfers_32bit_regs_p = %d\n", 8470 mips64_transfers_32bit_regs_p); 8471 8472 /* Determine the MIPS FPU type. */ 8473 #ifdef HAVE_ELF 8474 if (info.abfd 8475 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8476 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8477 Tag_GNU_MIPS_ABI_FP); 8478 #endif /* HAVE_ELF */ 8479 8480 if (!mips_fpu_type_auto) 8481 fpu_type = mips_fpu_type; 8482 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) 8483 { 8484 switch (elf_fpu_type) 8485 { 8486 case Val_GNU_MIPS_ABI_FP_DOUBLE: 8487 fpu_type = MIPS_FPU_DOUBLE; 8488 break; 8489 case Val_GNU_MIPS_ABI_FP_SINGLE: 8490 fpu_type = MIPS_FPU_SINGLE; 8491 break; 8492 case Val_GNU_MIPS_ABI_FP_SOFT: 8493 default: 8494 /* Soft float or unknown. */ 8495 fpu_type = MIPS_FPU_NONE; 8496 break; 8497 } 8498 } 8499 else if (info.bfd_arch_info != NULL 8500 && info.bfd_arch_info->arch == bfd_arch_mips) 8501 switch (info.bfd_arch_info->mach) 8502 { 8503 case bfd_mach_mips3900: 8504 case bfd_mach_mips4100: 8505 case bfd_mach_mips4111: 8506 case bfd_mach_mips4120: 8507 fpu_type = MIPS_FPU_NONE; 8508 break; 8509 case bfd_mach_mips4650: 8510 fpu_type = MIPS_FPU_SINGLE; 8511 break; 8512 default: 8513 fpu_type = MIPS_FPU_DOUBLE; 8514 break; 8515 } 8516 else if (arches != NULL) 8517 fpu_type = gdbarch_tdep (arches->gdbarch)->mips_fpu_type; 8518 else 8519 fpu_type = MIPS_FPU_DOUBLE; 8520 if (gdbarch_debug) 8521 fprintf_unfiltered (gdb_stdlog, 8522 "mips_gdbarch_init: fpu_type = %d\n", fpu_type); 8523 8524 /* Check for blatant incompatibilities. */ 8525 8526 /* If we have only 32-bit registers, then we can't debug a 64-bit 8527 ABI. */ 8528 if (info.target_desc 8529 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL 8530 && mips_abi != MIPS_ABI_EABI32 8531 && mips_abi != MIPS_ABI_O32) 8532 { 8533 if (tdesc_data != NULL) 8534 tdesc_data_cleanup (tdesc_data); 8535 return NULL; 8536 } 8537 8538 /* Try to find a pre-existing architecture. */ 8539 for (arches = gdbarch_list_lookup_by_info (arches, &info); 8540 arches != NULL; 8541 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 8542 { 8543 /* MIPS needs to be pedantic about which ABI and the compressed 8544 ISA variation the object is using. */ 8545 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) 8546 continue; 8547 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) 8548 continue; 8549 if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) 8550 continue; 8551 /* Need to be pedantic about which register virtual size is 8552 used. */ 8553 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p 8554 != mips64_transfers_32bit_regs_p) 8555 continue; 8556 /* Be pedantic about which FPU is selected. */ 8557 if (gdbarch_tdep (arches->gdbarch)->mips_fpu_type != fpu_type) 8558 continue; 8559 8560 if (tdesc_data != NULL) 8561 tdesc_data_cleanup (tdesc_data); 8562 return arches->gdbarch; 8563 } 8564 8565 /* Need a new architecture. Fill in a target specific vector. */ 8566 tdep = XNEW (struct gdbarch_tdep); 8567 gdbarch = gdbarch_alloc (&info, tdep); 8568 tdep->elf_flags = elf_flags; 8569 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; 8570 tdep->found_abi = found_abi; 8571 tdep->mips_abi = mips_abi; 8572 tdep->mips_isa = mips_isa; 8573 tdep->mips_fpu_type = fpu_type; 8574 tdep->register_size_valid_p = 0; 8575 tdep->register_size = 0; 8576 8577 if (info.target_desc) 8578 { 8579 /* Some useful properties can be inferred from the target. */ 8580 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) 8581 { 8582 tdep->register_size_valid_p = 1; 8583 tdep->register_size = 4; 8584 } 8585 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) 8586 { 8587 tdep->register_size_valid_p = 1; 8588 tdep->register_size = 8; 8589 } 8590 } 8591 8592 /* Initially set everything according to the default ABI/ISA. */ 8593 set_gdbarch_short_bit (gdbarch, 16); 8594 set_gdbarch_int_bit (gdbarch, 32); 8595 set_gdbarch_float_bit (gdbarch, 32); 8596 set_gdbarch_double_bit (gdbarch, 64); 8597 set_gdbarch_long_double_bit (gdbarch, 64); 8598 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); 8599 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); 8600 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); 8601 8602 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8603 mips_ax_pseudo_register_collect); 8604 set_gdbarch_ax_pseudo_register_push_stack 8605 (gdbarch, mips_ax_pseudo_register_push_stack); 8606 8607 set_gdbarch_elf_make_msymbol_special (gdbarch, 8608 mips_elf_make_msymbol_special); 8609 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); 8610 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); 8611 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); 8612 8613 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); 8614 *regnum = mips_regnum; 8615 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); 8616 set_gdbarch_num_regs (gdbarch, num_regs); 8617 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8618 set_gdbarch_register_name (gdbarch, mips_register_name); 8619 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); 8620 tdep->mips_processor_reg_names = reg_names; 8621 tdep->regnum = regnum; 8622 8623 switch (mips_abi) 8624 { 8625 case MIPS_ABI_O32: 8626 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); 8627 set_gdbarch_return_value (gdbarch, mips_o32_return_value); 8628 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8629 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8630 tdep->default_mask_address_p = 0; 8631 set_gdbarch_long_bit (gdbarch, 32); 8632 set_gdbarch_ptr_bit (gdbarch, 32); 8633 set_gdbarch_long_long_bit (gdbarch, 64); 8634 break; 8635 case MIPS_ABI_O64: 8636 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); 8637 set_gdbarch_return_value (gdbarch, mips_o64_return_value); 8638 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8639 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8640 tdep->default_mask_address_p = 0; 8641 set_gdbarch_long_bit (gdbarch, 32); 8642 set_gdbarch_ptr_bit (gdbarch, 32); 8643 set_gdbarch_long_long_bit (gdbarch, 64); 8644 break; 8645 case MIPS_ABI_EABI32: 8646 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8647 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8648 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8649 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8650 tdep->default_mask_address_p = 0; 8651 set_gdbarch_long_bit (gdbarch, 32); 8652 set_gdbarch_ptr_bit (gdbarch, 32); 8653 set_gdbarch_long_long_bit (gdbarch, 64); 8654 break; 8655 case MIPS_ABI_EABI64: 8656 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8657 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8658 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8659 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8660 tdep->default_mask_address_p = 0; 8661 set_gdbarch_long_bit (gdbarch, 64); 8662 set_gdbarch_ptr_bit (gdbarch, 64); 8663 set_gdbarch_long_long_bit (gdbarch, 64); 8664 break; 8665 case MIPS_ABI_N32: 8666 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8667 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8668 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8669 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8670 tdep->default_mask_address_p = 0; 8671 set_gdbarch_long_bit (gdbarch, 32); 8672 set_gdbarch_ptr_bit (gdbarch, 32); 8673 set_gdbarch_long_long_bit (gdbarch, 64); 8674 set_gdbarch_long_double_bit (gdbarch, 128); 8675 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8676 break; 8677 case MIPS_ABI_N64: 8678 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8679 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8680 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8681 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8682 tdep->default_mask_address_p = 0; 8683 set_gdbarch_long_bit (gdbarch, 64); 8684 set_gdbarch_ptr_bit (gdbarch, 64); 8685 set_gdbarch_long_long_bit (gdbarch, 64); 8686 set_gdbarch_long_double_bit (gdbarch, 128); 8687 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8688 break; 8689 default: 8690 internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); 8691 } 8692 8693 /* GCC creates a pseudo-section whose name specifies the size of 8694 longs, since -mlong32 or -mlong64 may be used independent of 8695 other options. How those options affect pointer sizes is ABI and 8696 architecture dependent, so use them to override the default sizes 8697 set by the ABI. This table shows the relationship between ABI, 8698 -mlongXX, and size of pointers: 8699 8700 ABI -mlongXX ptr bits 8701 --- -------- -------- 8702 o32 32 32 8703 o32 64 32 8704 n32 32 32 8705 n32 64 64 8706 o64 32 32 8707 o64 64 64 8708 n64 32 32 8709 n64 64 64 8710 eabi32 32 32 8711 eabi32 64 32 8712 eabi64 32 32 8713 eabi64 64 64 8714 8715 Note that for o32 and eabi32, pointers are always 32 bits 8716 regardless of any -mlongXX option. For all others, pointers and 8717 longs are the same, as set by -mlongXX or set by defaults. */ 8718 8719 if (info.abfd != NULL) 8720 { 8721 int long_bit = 0; 8722 8723 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); 8724 if (long_bit) 8725 { 8726 set_gdbarch_long_bit (gdbarch, long_bit); 8727 switch (mips_abi) 8728 { 8729 case MIPS_ABI_O32: 8730 case MIPS_ABI_EABI32: 8731 break; 8732 case MIPS_ABI_N32: 8733 case MIPS_ABI_O64: 8734 case MIPS_ABI_N64: 8735 case MIPS_ABI_EABI64: 8736 set_gdbarch_ptr_bit (gdbarch, long_bit); 8737 break; 8738 default: 8739 internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); 8740 } 8741 } 8742 } 8743 8744 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE 8745 that could indicate -gp32 BUT gas/config/tc-mips.c contains the 8746 comment: 8747 8748 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE 8749 flag in object files because to do so would make it impossible to 8750 link with libraries compiled without "-gp32". This is 8751 unnecessarily restrictive. 8752 8753 We could solve this problem by adding "-gp32" multilibs to gcc, 8754 but to set this flag before gcc is built with such multilibs will 8755 break too many systems.'' 8756 8757 But even more unhelpfully, the default linker output target for 8758 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even 8759 for 64-bit programs - you need to change the ABI to change this, 8760 and not all gcc targets support that currently. Therefore using 8761 this flag to detect 32-bit mode would do the wrong thing given 8762 the current gcc - it would make GDB treat these 64-bit programs 8763 as 32-bit programs by default. */ 8764 8765 set_gdbarch_read_pc (gdbarch, mips_read_pc); 8766 set_gdbarch_write_pc (gdbarch, mips_write_pc); 8767 8768 /* Add/remove bits from an address. The MIPS needs be careful to 8769 ensure that all 32 bit addresses are sign extended to 64 bits. */ 8770 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); 8771 8772 /* Unwind the frame. */ 8773 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); 8774 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); 8775 set_gdbarch_dummy_id (gdbarch, mips_dummy_id); 8776 8777 /* Map debug register numbers onto internal register numbers. */ 8778 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); 8779 set_gdbarch_ecoff_reg_to_regnum (gdbarch, 8780 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8781 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, 8782 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8783 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); 8784 8785 /* MIPS version of CALL_DUMMY. */ 8786 8787 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 8788 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); 8789 set_gdbarch_frame_align (gdbarch, mips_frame_align); 8790 8791 set_gdbarch_print_float_info (gdbarch, mips_print_float_info); 8792 8793 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); 8794 set_gdbarch_register_to_value (gdbarch, mips_register_to_value); 8795 set_gdbarch_value_to_register (gdbarch, mips_value_to_register); 8796 8797 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8798 set_gdbarch_breakpoint_from_pc (gdbarch, mips_breakpoint_from_pc); 8799 set_gdbarch_remote_breakpoint_from_pc (gdbarch, 8800 mips_remote_breakpoint_from_pc); 8801 set_gdbarch_adjust_breakpoint_address (gdbarch, 8802 mips_adjust_breakpoint_address); 8803 8804 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); 8805 8806 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); 8807 8808 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); 8809 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); 8810 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); 8811 8812 set_gdbarch_register_type (gdbarch, mips_register_type); 8813 8814 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); 8815 8816 if (mips_abi == MIPS_ABI_N32) 8817 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n32); 8818 else if (mips_abi == MIPS_ABI_N64) 8819 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips_n64); 8820 else 8821 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); 8822 8823 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, 8824 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint 8825 need to all be folded into the target vector. Since they are 8826 being used as guards for target_stopped_by_watchpoint, why not have 8827 target_stopped_by_watchpoint return the type of watchpoint that the code 8828 is sitting on? */ 8829 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 8830 8831 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); 8832 8833 /* NOTE drow/2012-04-25: We overload the core solib trampoline code 8834 to support MIPS16. This is a bad thing. Make sure not to do it 8835 if we have an OS ABI that actually supports shared libraries, since 8836 shared library support is more important. If we have an OS someday 8837 that supports both shared libraries and MIPS16, we'll have to find 8838 a better place for these. 8839 macro/2012-04-25: But that applies to return trampolines only and 8840 currently no MIPS OS ABI uses shared libraries that have them. */ 8841 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); 8842 8843 set_gdbarch_single_step_through_delay (gdbarch, 8844 mips_single_step_through_delay); 8845 8846 /* Virtual tables. */ 8847 set_gdbarch_vbit_in_delta (gdbarch, 1); 8848 8849 mips_register_g_packet_guesses (gdbarch); 8850 8851 /* Hook in OS ABI-specific overrides, if they have been registered. */ 8852 info.tdep_info = tdesc_data; 8853 gdbarch_init_osabi (info, gdbarch); 8854 8855 /* The hook may have adjusted num_regs, fetch the final value and 8856 set pc_regnum and sp_regnum now that it has been fixed. */ 8857 num_regs = gdbarch_num_regs (gdbarch); 8858 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); 8859 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8860 8861 /* Unwind the frame. */ 8862 dwarf2_append_unwinders (gdbarch); 8863 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); 8864 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); 8865 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); 8866 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); 8867 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); 8868 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); 8869 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); 8870 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); 8871 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); 8872 8873 if (tdesc_data) 8874 { 8875 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); 8876 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); 8877 8878 /* Override the normal target description methods to handle our 8879 dual real and pseudo registers. */ 8880 set_gdbarch_register_name (gdbarch, mips_register_name); 8881 set_gdbarch_register_reggroup_p (gdbarch, 8882 mips_tdesc_register_reggroup_p); 8883 8884 num_regs = gdbarch_num_regs (gdbarch); 8885 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8886 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); 8887 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8888 } 8889 8890 /* Add ABI-specific aliases for the registers. */ 8891 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) 8892 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) 8893 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, 8894 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); 8895 else 8896 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) 8897 user_reg_add (gdbarch, mips_o32_aliases[i].name, 8898 value_of_mips_user_reg, &mips_o32_aliases[i].regnum); 8899 8900 /* Add some other standard aliases. */ 8901 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) 8902 user_reg_add (gdbarch, mips_register_aliases[i].name, 8903 value_of_mips_user_reg, &mips_register_aliases[i].regnum); 8904 8905 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) 8906 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, 8907 value_of_mips_user_reg, 8908 &mips_numeric_register_aliases[i].regnum); 8909 8910 return gdbarch; 8911 } 8912 8913 static void 8914 mips_abi_update (char *ignore_args, int from_tty, struct cmd_list_element *c) 8915 { 8916 struct gdbarch_info info; 8917 8918 /* Force the architecture to update, and (if it's a MIPS architecture) 8919 mips_gdbarch_init will take care of the rest. */ 8920 gdbarch_info_init (&info); 8921 gdbarch_update_p (info); 8922 } 8923 8924 /* Print out which MIPS ABI is in use. */ 8925 8926 static void 8927 show_mips_abi (struct ui_file *file, 8928 int from_tty, 8929 struct cmd_list_element *ignored_cmd, 8930 const char *ignored_value) 8931 { 8932 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 8933 fprintf_filtered 8934 (file, 8935 "The MIPS ABI is unknown because the current architecture " 8936 "is not MIPS.\n"); 8937 else 8938 { 8939 enum mips_abi global_abi = global_mips_abi (); 8940 enum mips_abi actual_abi = mips_abi (target_gdbarch ()); 8941 const char *actual_abi_str = mips_abi_strings[actual_abi]; 8942 8943 if (global_abi == MIPS_ABI_UNKNOWN) 8944 fprintf_filtered 8945 (file, 8946 "The MIPS ABI is set automatically (currently \"%s\").\n", 8947 actual_abi_str); 8948 else if (global_abi == actual_abi) 8949 fprintf_filtered 8950 (file, 8951 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", 8952 actual_abi_str); 8953 else 8954 { 8955 /* Probably shouldn't happen... */ 8956 fprintf_filtered (file, 8957 "The (auto detected) MIPS ABI \"%s\" is in use " 8958 "even though the user setting was \"%s\".\n", 8959 actual_abi_str, mips_abi_strings[global_abi]); 8960 } 8961 } 8962 } 8963 8964 /* Print out which MIPS compressed ISA encoding is used. */ 8965 8966 static void 8967 show_mips_compression (struct ui_file *file, int from_tty, 8968 struct cmd_list_element *c, const char *value) 8969 { 8970 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), 8971 value); 8972 } 8973 8974 static void 8975 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 8976 { 8977 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 8978 if (tdep != NULL) 8979 { 8980 int ef_mips_arch; 8981 int ef_mips_32bitmode; 8982 /* Determine the ISA. */ 8983 switch (tdep->elf_flags & EF_MIPS_ARCH) 8984 { 8985 case E_MIPS_ARCH_1: 8986 ef_mips_arch = 1; 8987 break; 8988 case E_MIPS_ARCH_2: 8989 ef_mips_arch = 2; 8990 break; 8991 case E_MIPS_ARCH_3: 8992 ef_mips_arch = 3; 8993 break; 8994 case E_MIPS_ARCH_4: 8995 ef_mips_arch = 4; 8996 break; 8997 default: 8998 ef_mips_arch = 0; 8999 break; 9000 } 9001 /* Determine the size of a pointer. */ 9002 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); 9003 fprintf_unfiltered (file, 9004 "mips_dump_tdep: tdep->elf_flags = 0x%x\n", 9005 tdep->elf_flags); 9006 fprintf_unfiltered (file, 9007 "mips_dump_tdep: ef_mips_32bitmode = %d\n", 9008 ef_mips_32bitmode); 9009 fprintf_unfiltered (file, 9010 "mips_dump_tdep: ef_mips_arch = %d\n", 9011 ef_mips_arch); 9012 fprintf_unfiltered (file, 9013 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", 9014 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); 9015 fprintf_unfiltered (file, 9016 "mips_dump_tdep: " 9017 "mips_mask_address_p() %d (default %d)\n", 9018 mips_mask_address_p (tdep), 9019 tdep->default_mask_address_p); 9020 } 9021 fprintf_unfiltered (file, 9022 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", 9023 MIPS_DEFAULT_FPU_TYPE, 9024 (MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_NONE ? "none" 9025 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_SINGLE ? "single" 9026 : MIPS_DEFAULT_FPU_TYPE == MIPS_FPU_DOUBLE ? "double" 9027 : "???")); 9028 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", 9029 MIPS_EABI (gdbarch)); 9030 fprintf_unfiltered (file, 9031 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", 9032 MIPS_FPU_TYPE (gdbarch), 9033 (MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_NONE ? "none" 9034 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_SINGLE ? "single" 9035 : MIPS_FPU_TYPE (gdbarch) == MIPS_FPU_DOUBLE ? "double" 9036 : "???")); 9037 } 9038 9039 extern initialize_file_ftype _initialize_mips_tdep; /* -Wmissing-prototypes */ 9040 9041 void 9042 _initialize_mips_tdep (void) 9043 { 9044 static struct cmd_list_element *mipsfpulist = NULL; 9045 struct cmd_list_element *c; 9046 9047 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; 9048 if (MIPS_ABI_LAST + 1 9049 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) 9050 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); 9051 9052 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); 9053 9054 mips_pdr_data = register_objfile_data (); 9055 9056 /* Create feature sets with the appropriate properties. The values 9057 are not important. */ 9058 mips_tdesc_gp32 = allocate_target_description (); 9059 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); 9060 9061 mips_tdesc_gp64 = allocate_target_description (); 9062 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); 9063 9064 /* Add root prefix command for all "set mips"/"show mips" commands. */ 9065 add_prefix_cmd ("mips", no_class, set_mips_command, 9066 _("Various MIPS specific commands."), 9067 &setmipscmdlist, "set mips ", 0, &setlist); 9068 9069 add_prefix_cmd ("mips", no_class, show_mips_command, 9070 _("Various MIPS specific commands."), 9071 &showmipscmdlist, "show mips ", 0, &showlist); 9072 9073 /* Allow the user to override the ABI. */ 9074 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, 9075 &mips_abi_string, _("\ 9076 Set the MIPS ABI used by this program."), _("\ 9077 Show the MIPS ABI used by this program."), _("\ 9078 This option can be set to one of:\n\ 9079 auto - the default ABI associated with the current binary\n\ 9080 o32\n\ 9081 o64\n\ 9082 n32\n\ 9083 n64\n\ 9084 eabi32\n\ 9085 eabi64"), 9086 mips_abi_update, 9087 show_mips_abi, 9088 &setmipscmdlist, &showmipscmdlist); 9089 9090 /* Allow the user to set the ISA to assume for compressed code if ELF 9091 file flags don't tell or there is no program file selected. This 9092 setting is updated whenever unambiguous ELF file flags are interpreted, 9093 and carried over to subsequent sessions. */ 9094 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, 9095 &mips_compression_string, _("\ 9096 Set the compressed ISA encoding used by MIPS code."), _("\ 9097 Show the compressed ISA encoding used by MIPS code."), _("\ 9098 Select the compressed ISA encoding used in functions that have no symbol\n\ 9099 information available. The encoding can be set to either of:\n\ 9100 mips16\n\ 9101 micromips\n\ 9102 and is updated automatically from ELF file flags if available."), 9103 mips_abi_update, 9104 show_mips_compression, 9105 &setmipscmdlist, &showmipscmdlist); 9106 9107 /* Let the user turn off floating point and set the fence post for 9108 heuristic_proc_start. */ 9109 9110 add_prefix_cmd ("mipsfpu", class_support, set_mipsfpu_command, 9111 _("Set use of MIPS floating-point coprocessor."), 9112 &mipsfpulist, "set mipsfpu ", 0, &setlist); 9113 add_cmd ("single", class_support, set_mipsfpu_single_command, 9114 _("Select single-precision MIPS floating-point coprocessor."), 9115 &mipsfpulist); 9116 add_cmd ("double", class_support, set_mipsfpu_double_command, 9117 _("Select double-precision MIPS floating-point coprocessor."), 9118 &mipsfpulist); 9119 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); 9120 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); 9121 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); 9122 add_cmd ("none", class_support, set_mipsfpu_none_command, 9123 _("Select no MIPS floating-point coprocessor."), &mipsfpulist); 9124 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); 9125 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); 9126 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); 9127 add_cmd ("auto", class_support, set_mipsfpu_auto_command, 9128 _("Select MIPS floating-point coprocessor automatically."), 9129 &mipsfpulist); 9130 add_cmd ("mipsfpu", class_support, show_mipsfpu_command, 9131 _("Show current use of MIPS floating-point coprocessor target."), 9132 &showlist); 9133 9134 /* We really would like to have both "0" and "unlimited" work, but 9135 command.c doesn't deal with that. So make it a var_zinteger 9136 because the user can always use "999999" or some such for unlimited. */ 9137 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, 9138 &heuristic_fence_post, _("\ 9139 Set the distance searched for the start of a function."), _("\ 9140 Show the distance searched for the start of a function."), _("\ 9141 If you are debugging a stripped executable, GDB needs to search through the\n\ 9142 program for the start of a function. This command sets the distance of the\n\ 9143 search. The only need to set it is when debugging a stripped executable."), 9144 reinit_frame_cache_sfunc, 9145 NULL, /* FIXME: i18n: The distance searched for 9146 the start of a function is %s. */ 9147 &setlist, &showlist); 9148 9149 /* Allow the user to control whether the upper bits of 64-bit 9150 addresses should be zeroed. */ 9151 add_setshow_auto_boolean_cmd ("mask-address", no_class, 9152 &mask_address_var, _("\ 9153 Set zeroing of upper 32 bits of 64-bit addresses."), _("\ 9154 Show zeroing of upper 32 bits of 64-bit addresses."), _("\ 9155 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ 9156 allow GDB to determine the correct value."), 9157 NULL, show_mask_address, 9158 &setmipscmdlist, &showmipscmdlist); 9159 9160 /* Allow the user to control the size of 32 bit registers within the 9161 raw remote packet. */ 9162 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, 9163 &mips64_transfers_32bit_regs_p, _("\ 9164 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9165 _("\ 9166 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9167 _("\ 9168 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ 9169 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 9170 64 bits for others. Use \"off\" to disable compatibility mode"), 9171 set_mips64_transfers_32bit_regs, 9172 NULL, /* FIXME: i18n: Compatibility with 64-bit 9173 MIPS target that transfers 32-bit 9174 quantities is %s. */ 9175 &setlist, &showlist); 9176 9177 /* Debug this files internals. */ 9178 add_setshow_zuinteger_cmd ("mips", class_maintenance, 9179 &mips_debug, _("\ 9180 Set mips debugging."), _("\ 9181 Show mips debugging."), _("\ 9182 When non-zero, mips specific debugging is enabled."), 9183 NULL, 9184 NULL, /* FIXME: i18n: Mips debugging is 9185 currently %s. */ 9186 &setdebuglist, &showdebuglist); 9187 } 9188