1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. 2 3 Copyright (C) 1988-2023 Free Software Foundation, Inc. 4 5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU 6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "inferior.h" 26 #include "symtab.h" 27 #include "value.h" 28 #include "gdbcmd.h" 29 #include "language.h" 30 #include "gdbcore.h" 31 #include "symfile.h" 32 #include "objfiles.h" 33 #include "gdbtypes.h" 34 #include "target.h" 35 #include "arch-utils.h" 36 #include "regcache.h" 37 #include "osabi.h" 38 #include "mips-tdep.h" 39 #include "block.h" 40 #include "reggroups.h" 41 #include "opcode/mips.h" 42 #include "elf/mips.h" 43 #include "elf-bfd.h" 44 #include "symcat.h" 45 #include "sim-regno.h" 46 #include "dis-asm.h" 47 #include "disasm.h" 48 #include "frame-unwind.h" 49 #include "frame-base.h" 50 #include "trad-frame.h" 51 #include "infcall.h" 52 #include "remote.h" 53 #include "target-descriptions.h" 54 #include "dwarf2/frame.h" 55 #include "user-regs.h" 56 #include "valprint.h" 57 #include "ax.h" 58 #include "target-float.h" 59 #include <algorithm> 60 61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); 62 63 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, 64 ULONGEST inst); 65 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); 66 static int mips16_instruction_has_delay_slot (unsigned short inst, 67 int mustbe32); 68 69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 70 CORE_ADDR addr); 71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 72 CORE_ADDR addr, int mustbe32); 73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 74 CORE_ADDR addr, int mustbe32); 75 76 static void mips_print_float_info (struct gdbarch *, struct ui_file *, 77 frame_info_ptr, const char *); 78 79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ 80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ 81 #define ST0_FR (1 << 26) 82 83 /* The sizes of floating point registers. */ 84 85 enum 86 { 87 MIPS_FPU_SINGLE_REGSIZE = 4, 88 MIPS_FPU_DOUBLE_REGSIZE = 8 89 }; 90 91 enum 92 { 93 MIPS32_REGSIZE = 4, 94 MIPS64_REGSIZE = 8 95 }; 96 97 static const char *mips_abi_string; 98 99 static const char *const mips_abi_strings[] = { 100 "auto", 101 "n32", 102 "o32", 103 "n64", 104 "o64", 105 "eabi32", 106 "eabi64", 107 NULL 108 }; 109 110 /* Enum describing the different kinds of breakpoints. */ 111 112 enum mips_breakpoint_kind 113 { 114 /* 16-bit MIPS16 mode breakpoint. */ 115 MIPS_BP_KIND_MIPS16 = 2, 116 117 /* 16-bit microMIPS mode breakpoint. */ 118 MIPS_BP_KIND_MICROMIPS16 = 3, 119 120 /* 32-bit standard MIPS mode breakpoint. */ 121 MIPS_BP_KIND_MIPS32 = 4, 122 123 /* 32-bit microMIPS mode breakpoint. */ 124 MIPS_BP_KIND_MICROMIPS32 = 5, 125 }; 126 127 /* For backwards compatibility we default to MIPS16. This flag is 128 overridden as soon as unambiguous ELF file flags tell us the 129 compressed ISA encoding used. */ 130 static const char mips_compression_mips16[] = "mips16"; 131 static const char mips_compression_micromips[] = "micromips"; 132 static const char *const mips_compression_strings[] = 133 { 134 mips_compression_mips16, 135 mips_compression_micromips, 136 NULL 137 }; 138 139 static const char *mips_compression_string = mips_compression_mips16; 140 141 /* The standard register names, and all the valid aliases for them. */ 142 struct register_alias 143 { 144 const char *name; 145 int regnum; 146 }; 147 148 /* Aliases for o32 and most other ABIs. */ 149 const struct register_alias mips_o32_aliases[] = { 150 { "ta0", 12 }, 151 { "ta1", 13 }, 152 { "ta2", 14 }, 153 { "ta3", 15 } 154 }; 155 156 /* Aliases for n32 and n64. */ 157 const struct register_alias mips_n32_n64_aliases[] = { 158 { "ta0", 8 }, 159 { "ta1", 9 }, 160 { "ta2", 10 }, 161 { "ta3", 11 } 162 }; 163 164 /* Aliases for ABI-independent registers. */ 165 const struct register_alias mips_register_aliases[] = { 166 /* The architecture manuals specify these ABI-independent names for 167 the GPRs. */ 168 #define R(n) { "r" #n, n } 169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 173 #undef R 174 175 /* k0 and k1 are sometimes called these instead (for "kernel 176 temp"). */ 177 { "kt0", 26 }, 178 { "kt1", 27 }, 179 180 /* This is the traditional GDB name for the CP0 status register. */ 181 { "sr", MIPS_PS_REGNUM }, 182 183 /* This is the traditional GDB name for the CP0 BadVAddr register. */ 184 { "bad", MIPS_EMBED_BADVADDR_REGNUM }, 185 186 /* This is the traditional GDB name for the FCSR. */ 187 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } 188 }; 189 190 const struct register_alias mips_numeric_register_aliases[] = { 191 #define R(n) { #n, n } 192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 196 #undef R 197 }; 198 199 #ifndef MIPS_DEFAULT_FPU_TYPE 200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE 201 #endif 202 static int mips_fpu_type_auto = 1; 203 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; 204 205 static unsigned int mips_debug = 0; 206 207 /* Properties (for struct target_desc) describing the g/G packet 208 layout. */ 209 #define PROPERTY_GP32 "internal: transfers-32bit-registers" 210 #define PROPERTY_GP64 "internal: transfers-64bit-registers" 211 212 struct target_desc *mips_tdesc_gp32; 213 struct target_desc *mips_tdesc_gp64; 214 215 /* The current set of options to be passed to the disassembler. */ 216 static char *mips_disassembler_options; 217 218 /* Implicit disassembler options for individual ABIs. These tell 219 libopcodes to use general-purpose register names corresponding 220 to the ABI we have selected, perhaps via a `set mips abi ...' 221 override, rather than ones inferred from the ABI set in the ELF 222 headers of the binary file selected for debugging. */ 223 static const char mips_disassembler_options_o32[] = "gpr-names=32"; 224 static const char mips_disassembler_options_n32[] = "gpr-names=n32"; 225 static const char mips_disassembler_options_n64[] = "gpr-names=64"; 226 227 const struct mips_regnum * 228 mips_regnum (struct gdbarch *gdbarch) 229 { 230 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 231 return tdep->regnum; 232 } 233 234 static int 235 mips_fpa0_regnum (struct gdbarch *gdbarch) 236 { 237 return mips_regnum (gdbarch)->fp0 + 12; 238 } 239 240 /* Return 1 if REGNUM refers to a floating-point general register, raw 241 or cooked. Otherwise return 0. */ 242 243 static int 244 mips_float_register_p (struct gdbarch *gdbarch, int regnum) 245 { 246 int rawnum = regnum % gdbarch_num_regs (gdbarch); 247 248 return (rawnum >= mips_regnum (gdbarch)->fp0 249 && rawnum < mips_regnum (gdbarch)->fp0 + 32); 250 } 251 252 static bool 253 mips_eabi (gdbarch *arch) 254 { 255 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); 256 return (tdep->mips_abi == MIPS_ABI_EABI32 \ 257 || tdep->mips_abi == MIPS_ABI_EABI64); 258 } 259 260 static int 261 mips_last_fp_arg_regnum (gdbarch *arch) 262 { 263 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); 264 return tdep->mips_last_fp_arg_regnum; 265 } 266 267 static int 268 mips_last_arg_regnum (gdbarch *arch) 269 { 270 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); 271 return tdep->mips_last_arg_regnum; 272 } 273 274 static enum mips_fpu_type 275 mips_get_fpu_type (gdbarch *arch) 276 { 277 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); 278 return tdep->mips_fpu_type; 279 } 280 281 /* Return the MIPS ABI associated with GDBARCH. */ 282 enum mips_abi 283 mips_abi (struct gdbarch *gdbarch) 284 { 285 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 286 return tdep->mips_abi; 287 } 288 289 int 290 mips_isa_regsize (struct gdbarch *gdbarch) 291 { 292 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 293 294 /* If we know how big the registers are, use that size. */ 295 if (tdep->register_size_valid_p) 296 return tdep->register_size; 297 298 /* Fall back to the previous behavior. */ 299 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word 300 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); 301 } 302 303 /* Max saved register size. */ 304 #define MAX_MIPS_ABI_REGSIZE 8 305 306 /* Return the currently configured (or set) saved register size. */ 307 308 unsigned int 309 mips_abi_regsize (struct gdbarch *gdbarch) 310 { 311 switch (mips_abi (gdbarch)) 312 { 313 case MIPS_ABI_EABI32: 314 case MIPS_ABI_O32: 315 return 4; 316 case MIPS_ABI_N32: 317 case MIPS_ABI_N64: 318 case MIPS_ABI_O64: 319 case MIPS_ABI_EABI64: 320 return 8; 321 case MIPS_ABI_UNKNOWN: 322 case MIPS_ABI_LAST: 323 default: 324 internal_error (_("bad switch")); 325 } 326 } 327 328 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here 329 are some functions to handle addresses associated with compressed 330 code including but not limited to testing, setting, or clearing 331 bit 0 of such addresses. */ 332 333 /* Return one iff compressed code is the MIPS16 instruction set. */ 334 335 static int 336 is_mips16_isa (struct gdbarch *gdbarch) 337 { 338 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 339 return tdep->mips_isa == ISA_MIPS16; 340 } 341 342 /* Return one iff compressed code is the microMIPS instruction set. */ 343 344 static int 345 is_micromips_isa (struct gdbarch *gdbarch) 346 { 347 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 348 return tdep->mips_isa == ISA_MICROMIPS; 349 } 350 351 /* Return one iff ADDR denotes compressed code. */ 352 353 static int 354 is_compact_addr (CORE_ADDR addr) 355 { 356 return ((addr) & 1); 357 } 358 359 /* Return one iff ADDR denotes standard ISA code. */ 360 361 static int 362 is_mips_addr (CORE_ADDR addr) 363 { 364 return !is_compact_addr (addr); 365 } 366 367 /* Return one iff ADDR denotes MIPS16 code. */ 368 369 static int 370 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 371 { 372 return is_compact_addr (addr) && is_mips16_isa (gdbarch); 373 } 374 375 /* Return one iff ADDR denotes microMIPS code. */ 376 377 static int 378 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 379 { 380 return is_compact_addr (addr) && is_micromips_isa (gdbarch); 381 } 382 383 /* Strip the ISA (compression) bit off from ADDR. */ 384 385 static CORE_ADDR 386 unmake_compact_addr (CORE_ADDR addr) 387 { 388 return ((addr) & ~(CORE_ADDR) 1); 389 } 390 391 /* Add the ISA (compression) bit to ADDR. */ 392 393 static CORE_ADDR 394 make_compact_addr (CORE_ADDR addr) 395 { 396 return ((addr) | (CORE_ADDR) 1); 397 } 398 399 /* Extern version of unmake_compact_addr; we use a separate function 400 so that unmake_compact_addr can be inlined throughout this file. */ 401 402 CORE_ADDR 403 mips_unmake_compact_addr (CORE_ADDR addr) 404 { 405 return unmake_compact_addr (addr); 406 } 407 408 /* Functions for setting and testing a bit in a minimal symbol that 409 marks it as MIPS16 or microMIPS function. The MSB of the minimal 410 symbol's "info" field is used for this purpose. 411 412 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is 413 "special", i.e. refers to a MIPS16 or microMIPS function, and sets 414 one of the "special" bits in a minimal symbol to mark it accordingly. 415 The test checks an ELF-private flag that is valid for true function 416 symbols only; for synthetic symbols such as for PLT stubs that have 417 no ELF-private part at all the MIPS BFD backend arranges for this 418 information to be carried in the asymbol's udata field instead. 419 420 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit 421 in a minimal symbol. */ 422 423 static void 424 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) 425 { 426 elf_symbol_type *elfsym = (elf_symbol_type *) sym; 427 unsigned char st_other; 428 429 if ((sym->flags & BSF_SYNTHETIC) == 0) 430 st_other = elfsym->internal_elf_sym.st_other; 431 else if ((sym->flags & BSF_FUNCTION) != 0) 432 st_other = sym->udata.i; 433 else 434 return; 435 436 if (ELF_ST_IS_MICROMIPS (st_other)) 437 { 438 SET_MSYMBOL_TARGET_FLAG_MICROMIPS (msym); 439 msym->set_value_address (msym->value_raw_address () | 1); 440 } 441 else if (ELF_ST_IS_MIPS16 (st_other)) 442 { 443 SET_MSYMBOL_TARGET_FLAG_MIPS16 (msym); 444 msym->set_value_address (msym->value_raw_address () | 1); 445 } 446 } 447 448 /* Return one iff MSYM refers to standard ISA code. */ 449 450 static int 451 msymbol_is_mips (struct minimal_symbol *msym) 452 { 453 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) 454 || MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); 455 } 456 457 /* Return one iff MSYM refers to MIPS16 code. */ 458 459 static int 460 msymbol_is_mips16 (struct minimal_symbol *msym) 461 { 462 return MSYMBOL_TARGET_FLAG_MIPS16 (msym); 463 } 464 465 /* Return one iff MSYM refers to microMIPS code. */ 466 467 static int 468 msymbol_is_micromips (struct minimal_symbol *msym) 469 { 470 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); 471 } 472 473 /* Set the ISA bit in the main symbol too, complementing the corresponding 474 minimal symbol setting and reflecting the run-time value of the symbol. 475 The need for comes from the ISA bit having been cleared as code in 476 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's 477 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values 478 of symbols referring to compressed code different in GDB to the values 479 used by actual code. That in turn makes them evaluate incorrectly in 480 expressions, producing results different to what the same expressions 481 yield when compiled into the program being debugged. */ 482 483 static void 484 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) 485 { 486 if (sym->aclass () == LOC_BLOCK) 487 { 488 /* We are in symbol reading so it is OK to cast away constness. */ 489 struct block *block = (struct block *) sym->value_block (); 490 CORE_ADDR compact_block_start; 491 struct bound_minimal_symbol msym; 492 493 compact_block_start = block->start () | 1; 494 msym = lookup_minimal_symbol_by_pc (compact_block_start); 495 if (msym.minsym && !msymbol_is_mips (msym.minsym)) 496 { 497 block->set_start (compact_block_start); 498 } 499 } 500 } 501 502 /* XFER a value from the big/little/left end of the register. 503 Depending on the size of the value it might occupy the entire 504 register or just part of it. Make an allowance for this, aligning 505 things accordingly. */ 506 507 static void 508 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, 509 int reg_num, int length, 510 enum bfd_endian endian, gdb_byte *in, 511 const gdb_byte *out, int buf_offset) 512 { 513 int reg_offset = 0; 514 515 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); 516 /* Need to transfer the left or right part of the register, based on 517 the targets byte order. */ 518 switch (endian) 519 { 520 case BFD_ENDIAN_BIG: 521 reg_offset = register_size (gdbarch, reg_num) - length; 522 break; 523 case BFD_ENDIAN_LITTLE: 524 reg_offset = 0; 525 break; 526 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ 527 reg_offset = 0; 528 break; 529 default: 530 internal_error (_("bad switch")); 531 } 532 if (mips_debug) 533 gdb_printf (gdb_stderr, 534 "xfer $%d, reg offset %d, buf offset %d, length %d, ", 535 reg_num, reg_offset, buf_offset, length); 536 if (mips_debug && out != NULL) 537 { 538 int i; 539 gdb_printf (gdb_stdlog, "out "); 540 for (i = 0; i < length; i++) 541 gdb_printf (gdb_stdlog, "%02x", out[buf_offset + i]); 542 } 543 if (in != NULL) 544 regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); 545 if (out != NULL) 546 regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); 547 if (mips_debug && in != NULL) 548 { 549 int i; 550 gdb_printf (gdb_stdlog, "in "); 551 for (i = 0; i < length; i++) 552 gdb_printf (gdb_stdlog, "%02x", in[buf_offset + i]); 553 } 554 if (mips_debug) 555 gdb_printf (gdb_stdlog, "\n"); 556 } 557 558 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU 559 compatiblity mode. A return value of 1 means that we have 560 physical 64-bit registers, but should treat them as 32-bit registers. */ 561 562 static int 563 mips2_fp_compat (frame_info_ptr frame) 564 { 565 struct gdbarch *gdbarch = get_frame_arch (frame); 566 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not 567 meaningful. */ 568 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) 569 return 0; 570 571 #if 0 572 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, 573 in all the places we deal with FP registers. PR gdb/413. */ 574 /* Otherwise check the FR bit in the status register - it controls 575 the FP compatiblity mode. If it is clear we are in compatibility 576 mode. */ 577 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) 578 return 1; 579 #endif 580 581 return 0; 582 } 583 584 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 585 586 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); 587 588 /* The list of available "set mips " and "show mips " commands. */ 589 590 static struct cmd_list_element *setmipscmdlist = NULL; 591 static struct cmd_list_element *showmipscmdlist = NULL; 592 593 /* Integer registers 0 thru 31 are handled explicitly by 594 mips_register_name(). Processor specific registers 32 and above 595 are listed in the following tables. */ 596 597 enum 598 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; 599 600 /* Generic MIPS. */ 601 602 static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 603 "sr", "lo", "hi", "bad", "cause", "pc", 604 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 605 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 606 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 607 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 608 "fsr", "fir", 609 }; 610 611 /* Names of tx39 registers. */ 612 613 static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 614 "sr", "lo", "hi", "bad", "cause", "pc", 615 "", "", "", "", "", "", "", "", 616 "", "", "", "", "", "", "", "", 617 "", "", "", "", "", "", "", "", 618 "", "", "", "", "", "", "", "", 619 "", "", "", "", 620 "", "", "", "", "", "", "", "", 621 "", "", "config", "cache", "debug", "depc", "epc", 622 }; 623 624 /* Names of registers with Linux kernels. */ 625 static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 626 "sr", "lo", "hi", "bad", "cause", "pc", 627 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 628 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 629 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 630 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 631 "fsr", "fir" 632 }; 633 634 635 /* Return the name of the register corresponding to REGNO. */ 636 static const char * 637 mips_register_name (struct gdbarch *gdbarch, int regno) 638 { 639 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 640 /* GPR names for all ABIs other than n32/n64. */ 641 static const char *mips_gpr_names[] = { 642 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 643 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 644 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 645 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 646 }; 647 648 /* GPR names for n32 and n64 ABIs. */ 649 static const char *mips_n32_n64_gpr_names[] = { 650 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 651 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 652 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 653 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 654 }; 655 656 enum mips_abi abi = mips_abi (gdbarch); 657 658 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, 659 but then don't make the raw register names visible. This (upper) 660 range of user visible register numbers are the pseudo-registers. 661 662 This approach was adopted accommodate the following scenario: 663 It is possible to debug a 64-bit device using a 32-bit 664 programming model. In such instances, the raw registers are 665 configured to be 64-bits wide, while the pseudo registers are 666 configured to be 32-bits wide. The registers that the user 667 sees - the pseudo registers - match the users expectations 668 given the programming model being used. */ 669 int rawnum = regno % gdbarch_num_regs (gdbarch); 670 if (regno < gdbarch_num_regs (gdbarch)) 671 return ""; 672 673 /* The MIPS integer registers are always mapped from 0 to 31. The 674 names of the registers (which reflects the conventions regarding 675 register use) vary depending on the ABI. */ 676 if (0 <= rawnum && rawnum < 32) 677 { 678 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) 679 return mips_n32_n64_gpr_names[rawnum]; 680 else 681 return mips_gpr_names[rawnum]; 682 } 683 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 684 return tdesc_register_name (gdbarch, rawnum); 685 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) 686 { 687 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); 688 if (tdep->mips_processor_reg_names[rawnum - 32]) 689 return tdep->mips_processor_reg_names[rawnum - 32]; 690 return ""; 691 } 692 else 693 internal_error (_("mips_register_name: bad register number %d"), rawnum); 694 } 695 696 /* Return the groups that a MIPS register can be categorised into. */ 697 698 static int 699 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 700 const struct reggroup *reggroup) 701 { 702 int vector_p; 703 int float_p; 704 int raw_p; 705 int rawnum = regnum % gdbarch_num_regs (gdbarch); 706 int pseudo = regnum / gdbarch_num_regs (gdbarch); 707 if (reggroup == all_reggroup) 708 return pseudo; 709 vector_p = register_type (gdbarch, regnum)->is_vector (); 710 float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT; 711 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs 712 (gdbarch), as not all architectures are multi-arch. */ 713 raw_p = rawnum < gdbarch_num_regs (gdbarch); 714 if (gdbarch_register_name (gdbarch, regnum)[0] == '\0') 715 return 0; 716 if (reggroup == float_reggroup) 717 return float_p && pseudo; 718 if (reggroup == vector_reggroup) 719 return vector_p && pseudo; 720 if (reggroup == general_reggroup) 721 return (!vector_p && !float_p) && pseudo; 722 /* Save the pseudo registers. Need to make certain that any code 723 extracting register values from a saved register cache also uses 724 pseudo registers. */ 725 if (reggroup == save_reggroup) 726 return raw_p && pseudo; 727 /* Restore the same pseudo register. */ 728 if (reggroup == restore_reggroup) 729 return raw_p && pseudo; 730 return 0; 731 } 732 733 /* Return the groups that a MIPS register can be categorised into. 734 This version is only used if we have a target description which 735 describes real registers (and their groups). */ 736 737 static int 738 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 739 const struct reggroup *reggroup) 740 { 741 int rawnum = regnum % gdbarch_num_regs (gdbarch); 742 int pseudo = regnum / gdbarch_num_regs (gdbarch); 743 int ret; 744 745 /* Only save, restore, and display the pseudo registers. Need to 746 make certain that any code extracting register values from a 747 saved register cache also uses pseudo registers. 748 749 Note: saving and restoring the pseudo registers is slightly 750 strange; if we have 64 bits, we should save and restore all 751 64 bits. But this is hard and has little benefit. */ 752 if (!pseudo) 753 return 0; 754 755 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); 756 if (ret != -1) 757 return ret; 758 759 return mips_register_reggroup_p (gdbarch, regnum, reggroup); 760 } 761 762 /* Map the symbol table registers which live in the range [1 * 763 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw 764 registers. Take care of alignment and size problems. */ 765 766 static enum register_status 767 mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 768 int cookednum, gdb_byte *buf) 769 { 770 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 771 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 772 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 773 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 774 return regcache->raw_read (rawnum, buf); 775 else if (register_size (gdbarch, rawnum) > 776 register_size (gdbarch, cookednum)) 777 { 778 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 779 780 if (tdep->mips64_transfers_32bit_regs_p) 781 return regcache->raw_read_part (rawnum, 0, 4, buf); 782 else 783 { 784 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 785 LONGEST regval; 786 enum register_status status; 787 788 status = regcache->raw_read (rawnum, ®val); 789 if (status == REG_VALID) 790 store_signed_integer (buf, 4, byte_order, regval); 791 return status; 792 } 793 } 794 else 795 internal_error (_("bad register size")); 796 } 797 798 static void 799 mips_pseudo_register_write (struct gdbarch *gdbarch, 800 struct regcache *regcache, int cookednum, 801 const gdb_byte *buf) 802 { 803 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 804 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 805 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 806 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 807 regcache->raw_write (rawnum, buf); 808 else if (register_size (gdbarch, rawnum) > 809 register_size (gdbarch, cookednum)) 810 { 811 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 812 813 if (tdep->mips64_transfers_32bit_regs_p) 814 regcache->raw_write_part (rawnum, 0, 4, buf); 815 else 816 { 817 /* Sign extend the shortened version of the register prior 818 to placing it in the raw register. This is required for 819 some mips64 parts in order to avoid unpredictable behavior. */ 820 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 821 LONGEST regval = extract_signed_integer (buf, 4, byte_order); 822 regcache_raw_write_signed (regcache, rawnum, regval); 823 } 824 } 825 else 826 internal_error (_("bad register size")); 827 } 828 829 static int 830 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, 831 struct agent_expr *ax, int reg) 832 { 833 int rawnum = reg % gdbarch_num_regs (gdbarch); 834 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 835 && reg < 2 * gdbarch_num_regs (gdbarch)); 836 837 ax_reg_mask (ax, rawnum); 838 839 return 0; 840 } 841 842 static int 843 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, 844 struct agent_expr *ax, int reg) 845 { 846 int rawnum = reg % gdbarch_num_regs (gdbarch); 847 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 848 && reg < 2 * gdbarch_num_regs (gdbarch)); 849 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) 850 { 851 ax_reg (ax, rawnum); 852 853 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) 854 { 855 mips_gdbarch_tdep *tdep 856 = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 857 858 if (!tdep->mips64_transfers_32bit_regs_p 859 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) 860 { 861 ax_const_l (ax, 32); 862 ax_simple (ax, aop_lsh); 863 } 864 ax_const_l (ax, 32); 865 ax_simple (ax, aop_rsh_signed); 866 } 867 } 868 else 869 internal_error (_("bad register size")); 870 871 return 0; 872 } 873 874 /* Table to translate 3-bit register field to actual register number. */ 875 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 876 877 /* Heuristic_proc_start may hunt through the text section for a long 878 time across a 2400 baud serial line. Allows the user to limit this 879 search. */ 880 881 static int heuristic_fence_post = 0; 882 883 /* Number of bytes of storage in the actual machine representation for 884 register N. NOTE: This defines the pseudo register type so need to 885 rebuild the architecture vector. */ 886 887 static bool mips64_transfers_32bit_regs_p = false; 888 889 static void 890 set_mips64_transfers_32bit_regs (const char *args, int from_tty, 891 struct cmd_list_element *c) 892 { 893 struct gdbarch_info info; 894 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 895 instead of relying on globals. Doing that would let generic code 896 handle the search for this specific architecture. */ 897 if (!gdbarch_update_p (info)) 898 { 899 mips64_transfers_32bit_regs_p = 0; 900 error (_("32-bit compatibility mode not supported")); 901 } 902 } 903 904 /* Convert to/from a register and the corresponding memory value. */ 905 906 /* This predicate tests for the case of an 8 byte floating point 907 value that is being transferred to or from a pair of floating point 908 registers each of which are (or are considered to be) only 4 bytes 909 wide. */ 910 static int 911 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, 912 struct type *type) 913 { 914 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 915 && register_size (gdbarch, regnum) == 4 916 && mips_float_register_p (gdbarch, regnum) 917 && type->code () == TYPE_CODE_FLT && type->length () == 8); 918 } 919 920 /* This predicate tests for the case of a value of less than 8 921 bytes in width that is being transfered to or from an 8 byte 922 general purpose register. */ 923 static int 924 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, 925 struct type *type) 926 { 927 int num_regs = gdbarch_num_regs (gdbarch); 928 929 return (register_size (gdbarch, regnum) == 8 930 && regnum % num_regs > 0 && regnum % num_regs < 32 931 && type->length () < 8); 932 } 933 934 static int 935 mips_convert_register_p (struct gdbarch *gdbarch, 936 int regnum, struct type *type) 937 { 938 return (mips_convert_register_float_case_p (gdbarch, regnum, type) 939 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); 940 } 941 942 static int 943 mips_register_to_value (frame_info_ptr frame, int regnum, 944 struct type *type, gdb_byte *to, 945 int *optimizedp, int *unavailablep) 946 { 947 struct gdbarch *gdbarch = get_frame_arch (frame); 948 949 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 950 { 951 get_frame_register (frame, regnum + 0, to + 4); 952 get_frame_register (frame, regnum + 1, to + 0); 953 954 if (!get_frame_register_bytes (frame, regnum + 0, 0, {to + 4, 4}, 955 optimizedp, unavailablep)) 956 return 0; 957 958 if (!get_frame_register_bytes (frame, regnum + 1, 0, {to + 0, 4}, 959 optimizedp, unavailablep)) 960 return 0; 961 *optimizedp = *unavailablep = 0; 962 return 1; 963 } 964 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 965 { 966 size_t len = type->length (); 967 CORE_ADDR offset; 968 969 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; 970 if (!get_frame_register_bytes (frame, regnum, offset, {to, len}, 971 optimizedp, unavailablep)) 972 return 0; 973 974 *optimizedp = *unavailablep = 0; 975 return 1; 976 } 977 else 978 { 979 internal_error (_("mips_register_to_value: unrecognized case")); 980 } 981 } 982 983 static void 984 mips_value_to_register (frame_info_ptr frame, int regnum, 985 struct type *type, const gdb_byte *from) 986 { 987 struct gdbarch *gdbarch = get_frame_arch (frame); 988 989 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 990 { 991 put_frame_register (frame, regnum + 0, from + 4); 992 put_frame_register (frame, regnum + 1, from + 0); 993 } 994 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 995 { 996 gdb_byte fill[8]; 997 size_t len = type->length (); 998 999 /* Sign extend values, irrespective of type, that are stored to 1000 a 64-bit general purpose register. (32-bit unsigned values 1001 are stored as signed quantities within a 64-bit register. 1002 When performing an operation, in compiled code, that combines 1003 a 32-bit unsigned value with a signed 64-bit value, a type 1004 conversion is first performed that zeroes out the high 32 bits.) */ 1005 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 1006 { 1007 if (from[0] & 0x80) 1008 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); 1009 else 1010 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); 1011 put_frame_register_bytes (frame, regnum, 0, {fill, 8 - len}); 1012 put_frame_register_bytes (frame, regnum, 8 - len, {from, len}); 1013 } 1014 else 1015 { 1016 if (from[len-1] & 0x80) 1017 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); 1018 else 1019 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); 1020 put_frame_register_bytes (frame, regnum, 0, {from, len}); 1021 put_frame_register_bytes (frame, regnum, len, {fill, 8 - len}); 1022 } 1023 } 1024 else 1025 { 1026 internal_error (_("mips_value_to_register: unrecognized case")); 1027 } 1028 } 1029 1030 /* Return the GDB type object for the "standard" data type of data in 1031 register REG. */ 1032 1033 static struct type * 1034 mips_register_type (struct gdbarch *gdbarch, int regnum) 1035 { 1036 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); 1037 if (mips_float_register_p (gdbarch, regnum)) 1038 { 1039 /* The floating-point registers raw, or cooked, always match 1040 mips_isa_regsize(), and also map 1:1, byte for byte. */ 1041 if (mips_isa_regsize (gdbarch) == 4) 1042 return builtin_type (gdbarch)->builtin_float; 1043 else 1044 return builtin_type (gdbarch)->builtin_double; 1045 } 1046 else if (regnum < gdbarch_num_regs (gdbarch)) 1047 { 1048 /* The raw or ISA registers. These are all sized according to 1049 the ISA regsize. */ 1050 if (mips_isa_regsize (gdbarch) == 4) 1051 return builtin_type (gdbarch)->builtin_int32; 1052 else 1053 return builtin_type (gdbarch)->builtin_int64; 1054 } 1055 else 1056 { 1057 int rawnum = regnum - gdbarch_num_regs (gdbarch); 1058 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 1059 1060 /* The cooked or ABI registers. These are sized according to 1061 the ABI (with a few complications). */ 1062 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1063 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1064 return builtin_type (gdbarch)->builtin_int32; 1065 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1066 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1067 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1068 /* The pseudo/cooked view of the embedded registers is always 1069 32-bit. The raw view is handled below. */ 1070 return builtin_type (gdbarch)->builtin_int32; 1071 else if (tdep->mips64_transfers_32bit_regs_p) 1072 /* The target, while possibly using a 64-bit register buffer, 1073 is only transfering 32-bits of each integer register. 1074 Reflect this in the cooked/pseudo (ABI) register value. */ 1075 return builtin_type (gdbarch)->builtin_int32; 1076 else if (mips_abi_regsize (gdbarch) == 4) 1077 /* The ABI is restricted to 32-bit registers (the ISA could be 1078 32- or 64-bit). */ 1079 return builtin_type (gdbarch)->builtin_int32; 1080 else 1081 /* 64-bit ABI. */ 1082 return builtin_type (gdbarch)->builtin_int64; 1083 } 1084 } 1085 1086 /* Return the GDB type for the pseudo register REGNUM, which is the 1087 ABI-level view. This function is only called if there is a target 1088 description which includes registers, so we know precisely the 1089 types of hardware registers. */ 1090 1091 static struct type * 1092 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 1093 { 1094 const int num_regs = gdbarch_num_regs (gdbarch); 1095 int rawnum = regnum % num_regs; 1096 struct type *rawtype; 1097 1098 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); 1099 1100 /* Absent registers are still absent. */ 1101 rawtype = gdbarch_register_type (gdbarch, rawnum); 1102 if (rawtype->length () == 0) 1103 return rawtype; 1104 1105 /* Present the floating point registers however the hardware did; 1106 do not try to convert between FPU layouts. */ 1107 if (mips_float_register_p (gdbarch, rawnum)) 1108 return rawtype; 1109 1110 /* Floating-point control registers are always 32-bit even though for 1111 backwards compatibility reasons 64-bit targets will transfer them 1112 as 64-bit quantities even if using XML descriptions. */ 1113 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1114 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1115 return builtin_type (gdbarch)->builtin_int32; 1116 1117 /* Use pointer types for registers if we can. For n32 we can not, 1118 since we do not have a 64-bit pointer type. */ 1119 if (mips_abi_regsize (gdbarch) 1120 == builtin_type (gdbarch)->builtin_data_ptr->length()) 1121 { 1122 if (rawnum == MIPS_SP_REGNUM 1123 || rawnum == mips_regnum (gdbarch)->badvaddr) 1124 return builtin_type (gdbarch)->builtin_data_ptr; 1125 else if (rawnum == mips_regnum (gdbarch)->pc) 1126 return builtin_type (gdbarch)->builtin_func_ptr; 1127 } 1128 1129 if (mips_abi_regsize (gdbarch) == 4 && rawtype->length () == 8 1130 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) 1131 || rawnum == mips_regnum (gdbarch)->lo 1132 || rawnum == mips_regnum (gdbarch)->hi 1133 || rawnum == mips_regnum (gdbarch)->badvaddr 1134 || rawnum == mips_regnum (gdbarch)->cause 1135 || rawnum == mips_regnum (gdbarch)->pc 1136 || (mips_regnum (gdbarch)->dspacc != -1 1137 && rawnum >= mips_regnum (gdbarch)->dspacc 1138 && rawnum < mips_regnum (gdbarch)->dspacc + 6))) 1139 return builtin_type (gdbarch)->builtin_int32; 1140 1141 /* The pseudo/cooked view of embedded registers is always 1142 32-bit, even if the target transfers 64-bit values for them. 1143 New targets relying on XML descriptions should only transfer 1144 the necessary 32 bits, but older versions of GDB expected 64, 1145 so allow the target to provide 64 bits without interfering 1146 with the displayed type. */ 1147 if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1148 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1149 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1150 return builtin_type (gdbarch)->builtin_int32; 1151 1152 /* For all other registers, pass through the hardware type. */ 1153 return rawtype; 1154 } 1155 1156 /* Should the upper word of 64-bit addresses be zeroed? */ 1157 static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; 1158 1159 static int 1160 mips_mask_address_p (mips_gdbarch_tdep *tdep) 1161 { 1162 switch (mask_address_var) 1163 { 1164 case AUTO_BOOLEAN_TRUE: 1165 return 1; 1166 case AUTO_BOOLEAN_FALSE: 1167 return 0; 1168 break; 1169 case AUTO_BOOLEAN_AUTO: 1170 return tdep->default_mask_address_p; 1171 default: 1172 internal_error (_("mips_mask_address_p: bad switch")); 1173 return -1; 1174 } 1175 } 1176 1177 static void 1178 show_mask_address (struct ui_file *file, int from_tty, 1179 struct cmd_list_element *c, const char *value) 1180 { 1181 const char *additional_text = ""; 1182 if (mask_address_var == AUTO_BOOLEAN_AUTO) 1183 { 1184 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 1185 additional_text = _(" (current architecture is not MIPS)"); 1186 else 1187 { 1188 mips_gdbarch_tdep *tdep 1189 = gdbarch_tdep<mips_gdbarch_tdep> (target_gdbarch ()); 1190 1191 if (mips_mask_address_p (tdep)) 1192 additional_text = _(" (currently \"on\")"); 1193 else 1194 additional_text = _(" (currently \"off\")"); 1195 } 1196 } 1197 1198 gdb_printf (file, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"), 1199 value, additional_text); 1200 } 1201 1202 /* Tell if the program counter value in MEMADDR is in a standard ISA 1203 function. */ 1204 1205 int 1206 mips_pc_is_mips (CORE_ADDR memaddr) 1207 { 1208 struct bound_minimal_symbol sym; 1209 1210 /* Flags indicating that this is a MIPS16 or microMIPS function is 1211 stored by elfread.c in the high bit of the info field. Use this 1212 to decide if the function is standard MIPS. Otherwise if bit 0 1213 of the address is clear, then this is a standard MIPS function. */ 1214 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1215 if (sym.minsym) 1216 return msymbol_is_mips (sym.minsym); 1217 else 1218 return is_mips_addr (memaddr); 1219 } 1220 1221 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ 1222 1223 int 1224 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1225 { 1226 struct bound_minimal_symbol sym; 1227 1228 /* A flag indicating that this is a MIPS16 function is stored by 1229 elfread.c in the high bit of the info field. Use this to decide 1230 if the function is MIPS16. Otherwise if bit 0 of the address is 1231 set, then ELF file flags will tell if this is a MIPS16 function. */ 1232 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1233 if (sym.minsym) 1234 return msymbol_is_mips16 (sym.minsym); 1235 else 1236 return is_mips16_addr (gdbarch, memaddr); 1237 } 1238 1239 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ 1240 1241 int 1242 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1243 { 1244 struct bound_minimal_symbol sym; 1245 1246 /* A flag indicating that this is a microMIPS function is stored by 1247 elfread.c in the high bit of the info field. Use this to decide 1248 if the function is microMIPS. Otherwise if bit 0 of the address 1249 is set, then ELF file flags will tell if this is a microMIPS 1250 function. */ 1251 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1252 if (sym.minsym) 1253 return msymbol_is_micromips (sym.minsym); 1254 else 1255 return is_micromips_addr (gdbarch, memaddr); 1256 } 1257 1258 /* Tell the ISA type of the function the program counter value in MEMADDR 1259 is in. */ 1260 1261 static enum mips_isa 1262 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1263 { 1264 struct bound_minimal_symbol sym; 1265 1266 /* A flag indicating that this is a MIPS16 or a microMIPS function 1267 is stored by elfread.c in the high bit of the info field. Use 1268 this to decide if the function is MIPS16 or microMIPS or normal 1269 MIPS. Otherwise if bit 0 of the address is set, then ELF file 1270 flags will tell if this is a MIPS16 or a microMIPS function. */ 1271 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1272 if (sym.minsym) 1273 { 1274 if (msymbol_is_micromips (sym.minsym)) 1275 return ISA_MICROMIPS; 1276 else if (msymbol_is_mips16 (sym.minsym)) 1277 return ISA_MIPS16; 1278 else 1279 return ISA_MIPS; 1280 } 1281 else 1282 { 1283 if (is_mips_addr (memaddr)) 1284 return ISA_MIPS; 1285 else if (is_micromips_addr (gdbarch, memaddr)) 1286 return ISA_MICROMIPS; 1287 else 1288 return ISA_MIPS16; 1289 } 1290 } 1291 1292 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. 1293 The need for comes from the ISA bit having been cleared, making 1294 addresses in FDE, range records, etc. referring to compressed code 1295 different to those in line information, the symbol table and finally 1296 the PC register. That in turn confuses many operations. */ 1297 1298 static CORE_ADDR 1299 mips_adjust_dwarf2_addr (CORE_ADDR pc) 1300 { 1301 pc = unmake_compact_addr (pc); 1302 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); 1303 } 1304 1305 /* Recalculate the line record requested so that the resulting PC has 1306 the ISA bit set correctly, used by DWARF-2 machinery. The need for 1307 this adjustment comes from some records associated with compressed 1308 code having the ISA bit cleared, most notably at function prologue 1309 ends. The ISA bit is in this context retrieved from the minimal 1310 symbol covering the address requested, which in turn has been 1311 constructed from the binary's symbol table rather than DWARF-2 1312 information. The correct setting of the ISA bit is required for 1313 breakpoint addresses to correctly match against the stop PC. 1314 1315 As line entries can specify relative address adjustments we need to 1316 keep track of the absolute value of the last line address recorded 1317 in line information, so that we can calculate the actual address to 1318 apply the ISA bit adjustment to. We use PC for this tracking and 1319 keep the original address there. 1320 1321 As such relative address adjustments can be odd within compressed 1322 code we need to keep track of the last line address with the ISA 1323 bit adjustment applied too, as the original address may or may not 1324 have had the ISA bit set. We use ADJ_PC for this tracking and keep 1325 the adjusted address there. 1326 1327 For relative address adjustments we then use these variables to 1328 calculate the address intended by line information, which will be 1329 PC-relative, and return an updated adjustment carrying ISA bit 1330 information, which will be ADJ_PC-relative. For absolute address 1331 adjustments we just return the same address that we store in ADJ_PC 1332 too. 1333 1334 As the first line entry can be relative to an implied address value 1335 of 0 we need to have the initial address set up that we store in PC 1336 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' 1337 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ 1338 1339 static CORE_ADDR 1340 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) 1341 { 1342 static CORE_ADDR adj_pc; 1343 static CORE_ADDR pc; 1344 CORE_ADDR isa_pc; 1345 1346 pc = rel ? pc + addr : addr; 1347 isa_pc = mips_adjust_dwarf2_addr (pc); 1348 addr = rel ? isa_pc - adj_pc : isa_pc; 1349 adj_pc = isa_pc; 1350 return addr; 1351 } 1352 1353 /* Various MIPS16 thunk (aka stub or trampoline) names. */ 1354 1355 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; 1356 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; 1357 static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; 1358 static const char mips_str_call_stub[] = "__call_stub_"; 1359 static const char mips_str_fn_stub[] = "__fn_stub_"; 1360 1361 /* This is used as a PIC thunk prefix. */ 1362 1363 static const char mips_str_pic[] = ".pic."; 1364 1365 /* Return non-zero if the PC is inside a call thunk (aka stub or 1366 trampoline) that should be treated as a temporary frame. */ 1367 1368 static int 1369 mips_in_frame_stub (CORE_ADDR pc) 1370 { 1371 CORE_ADDR start_addr; 1372 const char *name; 1373 1374 /* Find the starting address of the function containing the PC. */ 1375 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 1376 return 0; 1377 1378 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ 1379 if (startswith (name, mips_str_mips16_call_stub)) 1380 return 1; 1381 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ 1382 if (startswith (name, mips_str_call_stub)) 1383 return 1; 1384 /* If the PC is in __fn_stub_*, this is a call stub. */ 1385 if (startswith (name, mips_str_fn_stub)) 1386 return 1; 1387 1388 return 0; /* Not a stub. */ 1389 } 1390 1391 /* MIPS believes that the PC has a sign extended value. Perhaps the 1392 all registers should be sign extended for simplicity? */ 1393 1394 static CORE_ADDR 1395 mips_read_pc (readable_regcache *regcache) 1396 { 1397 int regnum = gdbarch_pc_regnum (regcache->arch ()); 1398 LONGEST pc; 1399 1400 regcache->cooked_read (regnum, &pc); 1401 return pc; 1402 } 1403 1404 static CORE_ADDR 1405 mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) 1406 { 1407 CORE_ADDR pc; 1408 1409 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); 1410 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as 1411 intermediate frames. In this case we can get the caller's address 1412 from $ra, or if $ra contains an address within a thunk as well, then 1413 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} 1414 and thus the caller's address is in $s2. */ 1415 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) 1416 { 1417 pc = frame_unwind_register_signed 1418 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 1419 if (mips_in_frame_stub (pc)) 1420 pc = frame_unwind_register_signed 1421 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 1422 } 1423 return pc; 1424 } 1425 1426 static CORE_ADDR 1427 mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame) 1428 { 1429 return frame_unwind_register_signed 1430 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); 1431 } 1432 1433 /* Assuming THIS_FRAME is a dummy, return the frame ID of that 1434 dummy frame. The frame ID's base needs to match the TOS value 1435 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1436 breakpoint. */ 1437 1438 static struct frame_id 1439 mips_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) 1440 { 1441 return frame_id_build 1442 (get_frame_register_signed (this_frame, 1443 gdbarch_num_regs (gdbarch) 1444 + MIPS_SP_REGNUM), 1445 get_frame_pc (this_frame)); 1446 } 1447 1448 /* Implement the "write_pc" gdbarch method. */ 1449 1450 void 1451 mips_write_pc (struct regcache *regcache, CORE_ADDR pc) 1452 { 1453 int regnum = gdbarch_pc_regnum (regcache->arch ()); 1454 1455 regcache_cooked_write_unsigned (regcache, regnum, pc); 1456 } 1457 1458 /* Fetch and return instruction from the specified location. Handle 1459 MIPS16/microMIPS as appropriate. */ 1460 1461 static ULONGEST 1462 mips_fetch_instruction (struct gdbarch *gdbarch, 1463 enum mips_isa isa, CORE_ADDR addr, int *errp) 1464 { 1465 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1466 gdb_byte buf[MIPS_INSN32_SIZE]; 1467 int instlen; 1468 int err; 1469 1470 switch (isa) 1471 { 1472 case ISA_MICROMIPS: 1473 case ISA_MIPS16: 1474 instlen = MIPS_INSN16_SIZE; 1475 addr = unmake_compact_addr (addr); 1476 break; 1477 case ISA_MIPS: 1478 instlen = MIPS_INSN32_SIZE; 1479 break; 1480 default: 1481 internal_error (_("invalid ISA")); 1482 break; 1483 } 1484 err = target_read_memory (addr, buf, instlen); 1485 if (errp != NULL) 1486 *errp = err; 1487 if (err != 0) 1488 { 1489 if (errp == NULL) 1490 memory_error (TARGET_XFER_E_IO, addr); 1491 return 0; 1492 } 1493 return extract_unsigned_integer (buf, instlen, byte_order); 1494 } 1495 1496 /* These are the fields of 32 bit mips instructions. */ 1497 #define mips32_op(x) (x >> 26) 1498 #define itype_op(x) (x >> 26) 1499 #define itype_rs(x) ((x >> 21) & 0x1f) 1500 #define itype_rt(x) ((x >> 16) & 0x1f) 1501 #define itype_immediate(x) (x & 0xffff) 1502 1503 #define jtype_op(x) (x >> 26) 1504 #define jtype_target(x) (x & 0x03ffffff) 1505 1506 #define rtype_op(x) (x >> 26) 1507 #define rtype_rs(x) ((x >> 21) & 0x1f) 1508 #define rtype_rt(x) ((x >> 16) & 0x1f) 1509 #define rtype_rd(x) ((x >> 11) & 0x1f) 1510 #define rtype_shamt(x) ((x >> 6) & 0x1f) 1511 #define rtype_funct(x) (x & 0x3f) 1512 1513 /* MicroMIPS instruction fields. */ 1514 #define micromips_op(x) ((x) >> 10) 1515 1516 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest 1517 bit and the size respectively of the field extracted. */ 1518 #define b0s4_imm(x) ((x) & 0xf) 1519 #define b0s5_imm(x) ((x) & 0x1f) 1520 #define b0s5_reg(x) ((x) & 0x1f) 1521 #define b0s7_imm(x) ((x) & 0x7f) 1522 #define b0s10_imm(x) ((x) & 0x3ff) 1523 #define b1s4_imm(x) (((x) >> 1) & 0xf) 1524 #define b1s9_imm(x) (((x) >> 1) & 0x1ff) 1525 #define b2s3_cc(x) (((x) >> 2) & 0x7) 1526 #define b4s2_regl(x) (((x) >> 4) & 0x3) 1527 #define b5s5_op(x) (((x) >> 5) & 0x1f) 1528 #define b5s5_reg(x) (((x) >> 5) & 0x1f) 1529 #define b6s4_op(x) (((x) >> 6) & 0xf) 1530 #define b7s3_reg(x) (((x) >> 7) & 0x7) 1531 1532 /* 32-bit instruction formats, B and S refer to the lowest bit and the size 1533 respectively of the field extracted. */ 1534 #define b0s6_op(x) ((x) & 0x3f) 1535 #define b0s11_op(x) ((x) & 0x7ff) 1536 #define b0s12_imm(x) ((x) & 0xfff) 1537 #define b0s16_imm(x) ((x) & 0xffff) 1538 #define b0s26_imm(x) ((x) & 0x3ffffff) 1539 #define b6s10_ext(x) (((x) >> 6) & 0x3ff) 1540 #define b11s5_reg(x) (((x) >> 11) & 0x1f) 1541 #define b12s4_op(x) (((x) >> 12) & 0xf) 1542 1543 /* Return the size in bytes of the instruction INSN encoded in the ISA 1544 instruction set. */ 1545 1546 static int 1547 mips_insn_size (enum mips_isa isa, ULONGEST insn) 1548 { 1549 switch (isa) 1550 { 1551 case ISA_MICROMIPS: 1552 if ((micromips_op (insn) & 0x4) == 0x4 1553 || (micromips_op (insn) & 0x7) == 0x0) 1554 return 2 * MIPS_INSN16_SIZE; 1555 else 1556 return MIPS_INSN16_SIZE; 1557 case ISA_MIPS16: 1558 if ((insn & 0xf800) == 0xf000) 1559 return 2 * MIPS_INSN16_SIZE; 1560 else 1561 return MIPS_INSN16_SIZE; 1562 case ISA_MIPS: 1563 return MIPS_INSN32_SIZE; 1564 } 1565 internal_error (_("invalid ISA")); 1566 } 1567 1568 static LONGEST 1569 mips32_relative_offset (ULONGEST inst) 1570 { 1571 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; 1572 } 1573 1574 /* Determine the address of the next instruction executed after the INST 1575 floating condition branch instruction at PC. COUNT specifies the 1576 number of the floating condition bits tested by the branch. */ 1577 1578 static CORE_ADDR 1579 mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, 1580 ULONGEST inst, CORE_ADDR pc, int count) 1581 { 1582 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1583 int cnum = (itype_rt (inst) >> 2) & (count - 1); 1584 int tf = itype_rt (inst) & 1; 1585 int mask = (1 << count) - 1; 1586 ULONGEST fcs; 1587 int cond; 1588 1589 if (fcsr == -1) 1590 /* No way to handle; it'll most likely trap anyway. */ 1591 return pc; 1592 1593 fcs = regcache_raw_get_unsigned (regcache, fcsr); 1594 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1595 1596 if (((cond >> cnum) & mask) != mask * !tf) 1597 pc += mips32_relative_offset (inst); 1598 else 1599 pc += 4; 1600 1601 return pc; 1602 } 1603 1604 /* Return nonzero if the gdbarch is an Octeon series. */ 1605 1606 static int 1607 is_octeon (struct gdbarch *gdbarch) 1608 { 1609 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); 1610 1611 return (info->mach == bfd_mach_mips_octeon 1612 || info->mach == bfd_mach_mips_octeonp 1613 || info->mach == bfd_mach_mips_octeon2); 1614 } 1615 1616 /* Return true if the OP represents the Octeon's BBIT instruction. */ 1617 1618 static int 1619 is_octeon_bbit_op (int op, struct gdbarch *gdbarch) 1620 { 1621 if (!is_octeon (gdbarch)) 1622 return 0; 1623 /* BBIT0 is encoded as LWC2: 110 010. */ 1624 /* BBIT032 is encoded as LDC2: 110 110. */ 1625 /* BBIT1 is encoded as SWC2: 111 010. */ 1626 /* BBIT132 is encoded as SDC2: 111 110. */ 1627 if (op == 50 || op == 54 || op == 58 || op == 62) 1628 return 1; 1629 return 0; 1630 } 1631 1632 1633 /* Determine where to set a single step breakpoint while considering 1634 branch prediction. */ 1635 1636 static CORE_ADDR 1637 mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) 1638 { 1639 struct gdbarch *gdbarch = regcache->arch (); 1640 unsigned long inst; 1641 int op; 1642 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 1643 op = itype_op (inst); 1644 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch 1645 instruction. */ 1646 { 1647 if (op >> 2 == 5) 1648 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 1649 { 1650 switch (op & 0x03) 1651 { 1652 case 0: /* BEQL */ 1653 goto equal_branch; 1654 case 1: /* BNEL */ 1655 goto neq_branch; 1656 case 2: /* BLEZL */ 1657 goto less_branch; 1658 case 3: /* BGTZL */ 1659 goto greater_branch; 1660 default: 1661 pc += 4; 1662 } 1663 } 1664 else if (op == 17 && itype_rs (inst) == 8) 1665 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 1666 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); 1667 else if (op == 17 && itype_rs (inst) == 9 1668 && (itype_rt (inst) & 2) == 0) 1669 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ 1670 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); 1671 else if (op == 17 && itype_rs (inst) == 10 1672 && (itype_rt (inst) & 2) == 0) 1673 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ 1674 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); 1675 else if (op == 29) 1676 /* JALX: 011101 */ 1677 /* The new PC will be alternate mode. */ 1678 { 1679 unsigned long reg; 1680 1681 reg = jtype_target (inst) << 2; 1682 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ 1683 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; 1684 } 1685 else if (is_octeon_bbit_op (op, gdbarch)) 1686 { 1687 int bit, branch_if; 1688 1689 branch_if = op == 58 || op == 62; 1690 bit = itype_rt (inst); 1691 1692 /* Take into account the *32 instructions. */ 1693 if (op == 54 || op == 62) 1694 bit += 32; 1695 1696 if (((regcache_raw_get_signed (regcache, 1697 itype_rs (inst)) >> bit) & 1) 1698 == branch_if) 1699 pc += mips32_relative_offset (inst) + 4; 1700 else 1701 pc += 8; /* After the delay slot. */ 1702 } 1703 1704 else 1705 pc += 4; /* Not a branch, next instruction is easy. */ 1706 } 1707 else 1708 { /* This gets way messy. */ 1709 1710 /* Further subdivide into SPECIAL, REGIMM and other. */ 1711 switch (op & 0x07) /* Extract bits 28,27,26. */ 1712 { 1713 case 0: /* SPECIAL */ 1714 op = rtype_funct (inst); 1715 switch (op) 1716 { 1717 case 8: /* JR */ 1718 case 9: /* JALR */ 1719 /* Set PC to that address. */ 1720 pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); 1721 break; 1722 case 12: /* SYSCALL */ 1723 { 1724 mips_gdbarch_tdep *tdep 1725 = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 1726 1727 if (tdep->syscall_next_pc != NULL) 1728 pc = tdep->syscall_next_pc (get_current_frame ()); 1729 else 1730 pc += 4; 1731 } 1732 break; 1733 default: 1734 pc += 4; 1735 } 1736 1737 break; /* end SPECIAL */ 1738 case 1: /* REGIMM */ 1739 { 1740 op = itype_rt (inst); /* branch condition */ 1741 switch (op) 1742 { 1743 case 0: /* BLTZ */ 1744 case 2: /* BLTZL */ 1745 case 16: /* BLTZAL */ 1746 case 18: /* BLTZALL */ 1747 less_branch: 1748 if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) 1749 pc += mips32_relative_offset (inst) + 4; 1750 else 1751 pc += 8; /* after the delay slot */ 1752 break; 1753 case 1: /* BGEZ */ 1754 case 3: /* BGEZL */ 1755 case 17: /* BGEZAL */ 1756 case 19: /* BGEZALL */ 1757 if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) 1758 pc += mips32_relative_offset (inst) + 4; 1759 else 1760 pc += 8; /* after the delay slot */ 1761 break; 1762 case 0x1c: /* BPOSGE32 */ 1763 case 0x1e: /* BPOSGE64 */ 1764 pc += 4; 1765 if (itype_rs (inst) == 0) 1766 { 1767 unsigned int pos = (op & 2) ? 64 : 32; 1768 int dspctl = mips_regnum (gdbarch)->dspctl; 1769 1770 if (dspctl == -1) 1771 /* No way to handle; it'll most likely trap anyway. */ 1772 break; 1773 1774 if ((regcache_raw_get_unsigned (regcache, 1775 dspctl) & 0x7f) >= pos) 1776 pc += mips32_relative_offset (inst); 1777 else 1778 pc += 4; 1779 } 1780 break; 1781 /* All of the other instructions in the REGIMM category */ 1782 default: 1783 pc += 4; 1784 } 1785 } 1786 break; /* end REGIMM */ 1787 case 2: /* J */ 1788 case 3: /* JAL */ 1789 { 1790 unsigned long reg; 1791 reg = jtype_target (inst) << 2; 1792 /* Upper four bits get never changed... */ 1793 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 1794 } 1795 break; 1796 case 4: /* BEQ, BEQL */ 1797 equal_branch: 1798 if (regcache_raw_get_signed (regcache, itype_rs (inst)) == 1799 regcache_raw_get_signed (regcache, itype_rt (inst))) 1800 pc += mips32_relative_offset (inst) + 4; 1801 else 1802 pc += 8; 1803 break; 1804 case 5: /* BNE, BNEL */ 1805 neq_branch: 1806 if (regcache_raw_get_signed (regcache, itype_rs (inst)) != 1807 regcache_raw_get_signed (regcache, itype_rt (inst))) 1808 pc += mips32_relative_offset (inst) + 4; 1809 else 1810 pc += 8; 1811 break; 1812 case 6: /* BLEZ, BLEZL */ 1813 if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) 1814 pc += mips32_relative_offset (inst) + 4; 1815 else 1816 pc += 8; 1817 break; 1818 case 7: 1819 default: 1820 greater_branch: /* BGTZ, BGTZL */ 1821 if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) 1822 pc += mips32_relative_offset (inst) + 4; 1823 else 1824 pc += 8; 1825 break; 1826 } /* switch */ 1827 } /* else */ 1828 return pc; 1829 } /* mips32_next_pc */ 1830 1831 /* Extract the 7-bit signed immediate offset from the microMIPS instruction 1832 INSN. */ 1833 1834 static LONGEST 1835 micromips_relative_offset7 (ULONGEST insn) 1836 { 1837 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; 1838 } 1839 1840 /* Extract the 10-bit signed immediate offset from the microMIPS instruction 1841 INSN. */ 1842 1843 static LONGEST 1844 micromips_relative_offset10 (ULONGEST insn) 1845 { 1846 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; 1847 } 1848 1849 /* Extract the 16-bit signed immediate offset from the microMIPS instruction 1850 INSN. */ 1851 1852 static LONGEST 1853 micromips_relative_offset16 (ULONGEST insn) 1854 { 1855 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; 1856 } 1857 1858 /* Return the size in bytes of the microMIPS instruction at the address PC. */ 1859 1860 static int 1861 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) 1862 { 1863 ULONGEST insn; 1864 1865 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1866 return mips_insn_size (ISA_MICROMIPS, insn); 1867 } 1868 1869 /* Calculate the address of the next microMIPS instruction to execute 1870 after the INSN coprocessor 1 conditional branch instruction at the 1871 address PC. COUNT denotes the number of coprocessor condition bits 1872 examined by the branch. */ 1873 1874 static CORE_ADDR 1875 micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, 1876 ULONGEST insn, CORE_ADDR pc, int count) 1877 { 1878 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1879 int cnum = b2s3_cc (insn >> 16) & (count - 1); 1880 int tf = b5s5_op (insn >> 16) & 1; 1881 int mask = (1 << count) - 1; 1882 ULONGEST fcs; 1883 int cond; 1884 1885 if (fcsr == -1) 1886 /* No way to handle; it'll most likely trap anyway. */ 1887 return pc; 1888 1889 fcs = regcache_raw_get_unsigned (regcache, fcsr); 1890 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1891 1892 if (((cond >> cnum) & mask) != mask * !tf) 1893 pc += micromips_relative_offset16 (insn); 1894 else 1895 pc += micromips_pc_insn_size (gdbarch, pc); 1896 1897 return pc; 1898 } 1899 1900 /* Calculate the address of the next microMIPS instruction to execute 1901 after the instruction at the address PC. */ 1902 1903 static CORE_ADDR 1904 micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) 1905 { 1906 struct gdbarch *gdbarch = regcache->arch (); 1907 ULONGEST insn; 1908 1909 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1910 pc += MIPS_INSN16_SIZE; 1911 switch (mips_insn_size (ISA_MICROMIPS, insn)) 1912 { 1913 /* 32-bit instructions. */ 1914 case 2 * MIPS_INSN16_SIZE: 1915 insn <<= 16; 1916 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1917 pc += MIPS_INSN16_SIZE; 1918 switch (micromips_op (insn >> 16)) 1919 { 1920 case 0x00: /* POOL32A: bits 000000 */ 1921 switch (b0s6_op (insn)) 1922 { 1923 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ 1924 switch (b6s10_ext (insn)) 1925 { 1926 case 0x3c: /* JALR: 000000 0000111100 111100 */ 1927 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ 1928 case 0x13c: /* JALRS: 000000 0100111100 111100 */ 1929 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ 1930 pc = regcache_raw_get_signed (regcache, 1931 b0s5_reg (insn >> 16)); 1932 break; 1933 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ 1934 { 1935 mips_gdbarch_tdep *tdep 1936 = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 1937 1938 if (tdep->syscall_next_pc != NULL) 1939 pc = tdep->syscall_next_pc (get_current_frame ()); 1940 } 1941 break; 1942 } 1943 break; 1944 } 1945 break; 1946 1947 case 0x10: /* POOL32I: bits 010000 */ 1948 switch (b5s5_op (insn >> 16)) 1949 { 1950 case 0x00: /* BLTZ: bits 010000 00000 */ 1951 case 0x01: /* BLTZAL: bits 010000 00001 */ 1952 case 0x11: /* BLTZALS: bits 010000 10001 */ 1953 if (regcache_raw_get_signed (regcache, 1954 b0s5_reg (insn >> 16)) < 0) 1955 pc += micromips_relative_offset16 (insn); 1956 else 1957 pc += micromips_pc_insn_size (gdbarch, pc); 1958 break; 1959 1960 case 0x02: /* BGEZ: bits 010000 00010 */ 1961 case 0x03: /* BGEZAL: bits 010000 00011 */ 1962 case 0x13: /* BGEZALS: bits 010000 10011 */ 1963 if (regcache_raw_get_signed (regcache, 1964 b0s5_reg (insn >> 16)) >= 0) 1965 pc += micromips_relative_offset16 (insn); 1966 else 1967 pc += micromips_pc_insn_size (gdbarch, pc); 1968 break; 1969 1970 case 0x04: /* BLEZ: bits 010000 00100 */ 1971 if (regcache_raw_get_signed (regcache, 1972 b0s5_reg (insn >> 16)) <= 0) 1973 pc += micromips_relative_offset16 (insn); 1974 else 1975 pc += micromips_pc_insn_size (gdbarch, pc); 1976 break; 1977 1978 case 0x05: /* BNEZC: bits 010000 00101 */ 1979 if (regcache_raw_get_signed (regcache, 1980 b0s5_reg (insn >> 16)) != 0) 1981 pc += micromips_relative_offset16 (insn); 1982 break; 1983 1984 case 0x06: /* BGTZ: bits 010000 00110 */ 1985 if (regcache_raw_get_signed (regcache, 1986 b0s5_reg (insn >> 16)) > 0) 1987 pc += micromips_relative_offset16 (insn); 1988 else 1989 pc += micromips_pc_insn_size (gdbarch, pc); 1990 break; 1991 1992 case 0x07: /* BEQZC: bits 010000 00111 */ 1993 if (regcache_raw_get_signed (regcache, 1994 b0s5_reg (insn >> 16)) == 0) 1995 pc += micromips_relative_offset16 (insn); 1996 break; 1997 1998 case 0x14: /* BC2F: bits 010000 10100 xxx00 */ 1999 case 0x15: /* BC2T: bits 010000 10101 xxx00 */ 2000 if (((insn >> 16) & 0x3) == 0x0) 2001 /* BC2F, BC2T: don't know how to handle these. */ 2002 break; 2003 break; 2004 2005 case 0x1a: /* BPOSGE64: bits 010000 11010 */ 2006 case 0x1b: /* BPOSGE32: bits 010000 11011 */ 2007 { 2008 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; 2009 int dspctl = mips_regnum (gdbarch)->dspctl; 2010 2011 if (dspctl == -1) 2012 /* No way to handle; it'll most likely trap anyway. */ 2013 break; 2014 2015 if ((regcache_raw_get_unsigned (regcache, 2016 dspctl) & 0x7f) >= pos) 2017 pc += micromips_relative_offset16 (insn); 2018 else 2019 pc += micromips_pc_insn_size (gdbarch, pc); 2020 } 2021 break; 2022 2023 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ 2024 /* BC1ANY2F: bits 010000 11100 xxx01 */ 2025 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ 2026 /* BC1ANY2T: bits 010000 11101 xxx01 */ 2027 if (((insn >> 16) & 0x2) == 0x0) 2028 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 2029 ((insn >> 16) & 0x1) + 1); 2030 break; 2031 2032 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ 2033 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ 2034 if (((insn >> 16) & 0x3) == 0x1) 2035 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); 2036 break; 2037 } 2038 break; 2039 2040 case 0x1d: /* JALS: bits 011101 */ 2041 case 0x35: /* J: bits 110101 */ 2042 case 0x3d: /* JAL: bits 111101 */ 2043 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); 2044 break; 2045 2046 case 0x25: /* BEQ: bits 100101 */ 2047 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) 2048 == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) 2049 pc += micromips_relative_offset16 (insn); 2050 else 2051 pc += micromips_pc_insn_size (gdbarch, pc); 2052 break; 2053 2054 case 0x2d: /* BNE: bits 101101 */ 2055 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) 2056 != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) 2057 pc += micromips_relative_offset16 (insn); 2058 else 2059 pc += micromips_pc_insn_size (gdbarch, pc); 2060 break; 2061 2062 case 0x3c: /* JALX: bits 111100 */ 2063 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); 2064 break; 2065 } 2066 break; 2067 2068 /* 16-bit instructions. */ 2069 case MIPS_INSN16_SIZE: 2070 switch (micromips_op (insn)) 2071 { 2072 case 0x11: /* POOL16C: bits 010001 */ 2073 if ((b5s5_op (insn) & 0x1c) == 0xc) 2074 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 2075 pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); 2076 else if (b5s5_op (insn) == 0x18) 2077 /* JRADDIUSP: bits 010001 11000 */ 2078 pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); 2079 break; 2080 2081 case 0x23: /* BEQZ16: bits 100011 */ 2082 { 2083 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2084 2085 if (regcache_raw_get_signed (regcache, rs) == 0) 2086 pc += micromips_relative_offset7 (insn); 2087 else 2088 pc += micromips_pc_insn_size (gdbarch, pc); 2089 } 2090 break; 2091 2092 case 0x2b: /* BNEZ16: bits 101011 */ 2093 { 2094 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2095 2096 if (regcache_raw_get_signed (regcache, rs) != 0) 2097 pc += micromips_relative_offset7 (insn); 2098 else 2099 pc += micromips_pc_insn_size (gdbarch, pc); 2100 } 2101 break; 2102 2103 case 0x33: /* B16: bits 110011 */ 2104 pc += micromips_relative_offset10 (insn); 2105 break; 2106 } 2107 break; 2108 } 2109 2110 return pc; 2111 } 2112 2113 /* Decoding the next place to set a breakpoint is irregular for the 2114 mips 16 variant, but fortunately, there fewer instructions. We have 2115 to cope ith extensions for 16 bit instructions and a pair of actual 2116 32 bit instructions. We dont want to set a single step instruction 2117 on the extend instruction either. */ 2118 2119 /* Lots of mips16 instruction formats */ 2120 /* Predicting jumps requires itype,ritype,i8type 2121 and their extensions extItype,extritype,extI8type. */ 2122 enum mips16_inst_fmts 2123 { 2124 itype, /* 0 immediate 5,10 */ 2125 ritype, /* 1 5,3,8 */ 2126 rrtype, /* 2 5,3,3,5 */ 2127 rritype, /* 3 5,3,3,5 */ 2128 rrrtype, /* 4 5,3,3,3,2 */ 2129 rriatype, /* 5 5,3,3,1,4 */ 2130 shifttype, /* 6 5,3,3,3,2 */ 2131 i8type, /* 7 5,3,8 */ 2132 i8movtype, /* 8 5,3,3,5 */ 2133 i8mov32rtype, /* 9 5,3,5,3 */ 2134 i64type, /* 10 5,3,8 */ 2135 ri64type, /* 11 5,3,3,5 */ 2136 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ 2137 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ 2138 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ 2139 extRRItype, /* 15 5,5,5,5,3,3,5 */ 2140 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ 2141 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ 2142 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ 2143 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ 2144 extRi64type, /* 20 5,6,5,5,3,3,5 */ 2145 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ 2146 }; 2147 /* I am heaping all the fields of the formats into one structure and 2148 then, only the fields which are involved in instruction extension. */ 2149 struct upk_mips16 2150 { 2151 CORE_ADDR offset; 2152 unsigned int regx; /* Function in i8 type. */ 2153 unsigned int regy; 2154 }; 2155 2156 2157 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format 2158 for the bits which make up the immediate extension. */ 2159 2160 static CORE_ADDR 2161 extended_offset (unsigned int extension) 2162 { 2163 CORE_ADDR value; 2164 2165 value = (extension >> 16) & 0x1f; /* Extract 15:11. */ 2166 value = value << 6; 2167 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ 2168 value = value << 5; 2169 value |= extension & 0x1f; /* Extract 4:0. */ 2170 2171 return value; 2172 } 2173 2174 /* Only call this function if you know that this is an extendable 2175 instruction. It won't malfunction, but why make excess remote memory 2176 references? If the immediate operands get sign extended or something, 2177 do it after the extension is performed. */ 2178 /* FIXME: Every one of these cases needs to worry about sign extension 2179 when the offset is to be used in relative addressing. */ 2180 2181 static unsigned int 2182 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) 2183 { 2184 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2185 gdb_byte buf[8]; 2186 2187 pc = unmake_compact_addr (pc); /* Clear the low order bit. */ 2188 target_read_memory (pc, buf, 2); 2189 return extract_unsigned_integer (buf, 2, byte_order); 2190 } 2191 2192 static void 2193 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, 2194 unsigned int extension, 2195 unsigned int inst, 2196 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) 2197 { 2198 CORE_ADDR offset; 2199 int regx; 2200 int regy; 2201 switch (insn_format) 2202 { 2203 case itype: 2204 { 2205 CORE_ADDR value; 2206 if (extension) 2207 { 2208 value = extended_offset ((extension << 16) | inst); 2209 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2210 } 2211 else 2212 { 2213 value = inst & 0x7ff; 2214 value = (value ^ 0x400) - 0x400; /* Sign-extend. */ 2215 } 2216 offset = value; 2217 regx = -1; 2218 regy = -1; 2219 } 2220 break; 2221 case ritype: 2222 case i8type: 2223 { /* A register identifier and an offset. */ 2224 /* Most of the fields are the same as I type but the 2225 immediate value is of a different length. */ 2226 CORE_ADDR value; 2227 if (extension) 2228 { 2229 value = extended_offset ((extension << 16) | inst); 2230 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2231 } 2232 else 2233 { 2234 value = inst & 0xff; /* 8 bits */ 2235 value = (value ^ 0x80) - 0x80; /* Sign-extend. */ 2236 } 2237 offset = value; 2238 regx = (inst >> 8) & 0x07; /* i8 funct */ 2239 regy = -1; 2240 break; 2241 } 2242 case jalxtype: 2243 { 2244 unsigned long value; 2245 unsigned int nexthalf; 2246 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); 2247 value = value << 16; 2248 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); 2249 /* Low bit still set. */ 2250 value |= nexthalf; 2251 offset = value; 2252 regx = -1; 2253 regy = -1; 2254 break; 2255 } 2256 default: 2257 internal_error (_("bad switch")); 2258 } 2259 upk->offset = offset; 2260 upk->regx = regx; 2261 upk->regy = regy; 2262 } 2263 2264 2265 /* Calculate the destination of a branch whose 16-bit opcode word is at PC, 2266 and having a signed 16-bit OFFSET. */ 2267 2268 static CORE_ADDR 2269 add_offset_16 (CORE_ADDR pc, int offset) 2270 { 2271 return pc + (offset << 1) + 2; 2272 } 2273 2274 static CORE_ADDR 2275 extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, 2276 unsigned int extension, unsigned int insn) 2277 { 2278 struct gdbarch *gdbarch = regcache->arch (); 2279 int op = (insn >> 11); 2280 switch (op) 2281 { 2282 case 2: /* Branch */ 2283 { 2284 struct upk_mips16 upk; 2285 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); 2286 pc = add_offset_16 (pc, upk.offset); 2287 break; 2288 } 2289 case 3: /* JAL , JALX - Watch out, these are 32 bit 2290 instructions. */ 2291 { 2292 struct upk_mips16 upk; 2293 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); 2294 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); 2295 if ((insn >> 10) & 0x01) /* Exchange mode */ 2296 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ 2297 else 2298 pc |= 0x01; 2299 break; 2300 } 2301 case 4: /* beqz */ 2302 { 2303 struct upk_mips16 upk; 2304 int reg; 2305 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2306 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); 2307 if (reg == 0) 2308 pc = add_offset_16 (pc, upk.offset); 2309 else 2310 pc += 2; 2311 break; 2312 } 2313 case 5: /* bnez */ 2314 { 2315 struct upk_mips16 upk; 2316 int reg; 2317 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2318 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); 2319 if (reg != 0) 2320 pc = add_offset_16 (pc, upk.offset); 2321 else 2322 pc += 2; 2323 break; 2324 } 2325 case 12: /* I8 Formats btez btnez */ 2326 { 2327 struct upk_mips16 upk; 2328 int reg; 2329 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); 2330 /* upk.regx contains the opcode */ 2331 /* Test register is 24 */ 2332 reg = regcache_raw_get_signed (regcache, 24); 2333 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ 2334 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ 2335 pc = add_offset_16 (pc, upk.offset); 2336 else 2337 pc += 2; 2338 break; 2339 } 2340 case 29: /* RR Formats JR, JALR, JALR-RA */ 2341 { 2342 struct upk_mips16 upk; 2343 /* upk.fmt = rrtype; */ 2344 op = insn & 0x1f; 2345 if (op == 0) 2346 { 2347 int reg; 2348 upk.regx = (insn >> 8) & 0x07; 2349 upk.regy = (insn >> 5) & 0x07; 2350 if ((upk.regy & 1) == 0) 2351 reg = mips_reg3_to_reg[upk.regx]; 2352 else 2353 reg = 31; /* Function return instruction. */ 2354 pc = regcache_raw_get_signed (regcache, reg); 2355 } 2356 else 2357 pc += 2; 2358 break; 2359 } 2360 case 30: 2361 /* This is an instruction extension. Fetch the real instruction 2362 (which follows the extension) and decode things based on 2363 that. */ 2364 { 2365 pc += 2; 2366 pc = extended_mips16_next_pc (regcache, pc, insn, 2367 fetch_mips_16 (gdbarch, pc)); 2368 break; 2369 } 2370 default: 2371 { 2372 pc += 2; 2373 break; 2374 } 2375 } 2376 return pc; 2377 } 2378 2379 static CORE_ADDR 2380 mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) 2381 { 2382 struct gdbarch *gdbarch = regcache->arch (); 2383 unsigned int insn = fetch_mips_16 (gdbarch, pc); 2384 return extended_mips16_next_pc (regcache, pc, 0, insn); 2385 } 2386 2387 /* The mips_next_pc function supports single_step when the remote 2388 target monitor or stub is not developed enough to do a single_step. 2389 It works by decoding the current instruction and predicting where a 2390 branch will go. This isn't hard because all the data is available. 2391 The MIPS32, MIPS16 and microMIPS variants are quite different. */ 2392 static CORE_ADDR 2393 mips_next_pc (struct regcache *regcache, CORE_ADDR pc) 2394 { 2395 struct gdbarch *gdbarch = regcache->arch (); 2396 2397 if (mips_pc_is_mips16 (gdbarch, pc)) 2398 return mips16_next_pc (regcache, pc); 2399 else if (mips_pc_is_micromips (gdbarch, pc)) 2400 return micromips_next_pc (regcache, pc); 2401 else 2402 return mips32_next_pc (regcache, pc); 2403 } 2404 2405 /* Return non-zero if the MIPS16 instruction INSN is a compact branch 2406 or jump. */ 2407 2408 static int 2409 mips16_instruction_is_compact_branch (unsigned short insn) 2410 { 2411 switch (insn & 0xf800) 2412 { 2413 case 0xe800: 2414 return (insn & 0x009f) == 0x80; /* JALRC/JRC */ 2415 case 0x6000: 2416 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ 2417 case 0x2800: /* BNEZ */ 2418 case 0x2000: /* BEQZ */ 2419 case 0x1000: /* B */ 2420 return 1; 2421 default: 2422 return 0; 2423 } 2424 } 2425 2426 /* Return non-zero if the microMIPS instruction INSN is a compact branch 2427 or jump. */ 2428 2429 static int 2430 micromips_instruction_is_compact_branch (unsigned short insn) 2431 { 2432 switch (micromips_op (insn)) 2433 { 2434 case 0x11: /* POOL16C: bits 010001 */ 2435 return (b5s5_op (insn) == 0x18 2436 /* JRADDIUSP: bits 010001 11000 */ 2437 || b5s5_op (insn) == 0xd); 2438 /* JRC: bits 010011 01101 */ 2439 case 0x10: /* POOL32I: bits 010000 */ 2440 return (b5s5_op (insn) & 0x1d) == 0x5; 2441 /* BEQZC/BNEZC: bits 010000 001x1 */ 2442 default: 2443 return 0; 2444 } 2445 } 2446 2447 struct mips_frame_cache 2448 { 2449 CORE_ADDR base; 2450 trad_frame_saved_reg *saved_regs; 2451 }; 2452 2453 /* Set a register's saved stack address in temp_saved_regs. If an 2454 address has already been set for this register, do nothing; this 2455 way we will only recognize the first save of a given register in a 2456 function prologue. 2457 2458 For simplicity, save the address in both [0 .. gdbarch_num_regs) and 2459 [gdbarch_num_regs .. 2*gdbarch_num_regs). 2460 Strictly speaking, only the second range is used as it is only second 2461 range (the ABI instead of ISA registers) that comes into play when finding 2462 saved registers in a frame. */ 2463 2464 static void 2465 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, 2466 int regnum, CORE_ADDR offset) 2467 { 2468 if (this_cache != NULL 2469 && this_cache->saved_regs[regnum].is_realreg () 2470 && this_cache->saved_regs[regnum].realreg () == regnum) 2471 { 2472 this_cache->saved_regs[regnum + 0 2473 * gdbarch_num_regs (gdbarch)].set_addr (offset); 2474 this_cache->saved_regs[regnum + 1 2475 * gdbarch_num_regs (gdbarch)].set_addr (offset); 2476 } 2477 } 2478 2479 2480 /* Fetch the immediate value from a MIPS16 instruction. 2481 If the previous instruction was an EXTEND, use it to extend 2482 the upper bits of the immediate value. This is a helper function 2483 for mips16_scan_prologue. */ 2484 2485 static int 2486 mips16_get_imm (unsigned short prev_inst, /* previous instruction */ 2487 unsigned short inst, /* current instruction */ 2488 int nbits, /* number of bits in imm field */ 2489 int scale, /* scale factor to be applied to imm */ 2490 int is_signed) /* is the imm field signed? */ 2491 { 2492 int offset; 2493 2494 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ 2495 { 2496 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); 2497 if (offset & 0x8000) /* check for negative extend */ 2498 offset = 0 - (0x10000 - (offset & 0xffff)); 2499 return offset | (inst & 0x1f); 2500 } 2501 else 2502 { 2503 int max_imm = 1 << nbits; 2504 int mask = max_imm - 1; 2505 int sign_bit = max_imm >> 1; 2506 2507 offset = inst & mask; 2508 if (is_signed && (offset & sign_bit)) 2509 offset = 0 - (max_imm - offset); 2510 return offset * scale; 2511 } 2512 } 2513 2514 2515 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 2516 the associated FRAME_CACHE if not null. 2517 Return the address of the first instruction past the prologue. */ 2518 2519 static CORE_ADDR 2520 mips16_scan_prologue (struct gdbarch *gdbarch, 2521 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2522 frame_info_ptr this_frame, 2523 struct mips_frame_cache *this_cache) 2524 { 2525 int prev_non_prologue_insn = 0; 2526 int this_non_prologue_insn; 2527 int non_prologue_insns = 0; 2528 CORE_ADDR prev_pc; 2529 CORE_ADDR cur_pc; 2530 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ 2531 CORE_ADDR sp; 2532 long frame_offset = 0; /* Size of stack frame. */ 2533 long frame_adjust = 0; /* Offset of FP from SP. */ 2534 int frame_reg = MIPS_SP_REGNUM; 2535 unsigned short prev_inst = 0; /* saved copy of previous instruction. */ 2536 unsigned inst = 0; /* current instruction */ 2537 unsigned entry_inst = 0; /* the entry instruction */ 2538 unsigned save_inst = 0; /* the save instruction */ 2539 int prev_delay_slot = 0; 2540 int in_delay_slot; 2541 int reg, offset; 2542 2543 int extend_bytes = 0; 2544 int prev_extend_bytes = 0; 2545 CORE_ADDR end_prologue_addr; 2546 2547 /* Can be called when there's no process, and hence when there's no 2548 THIS_FRAME. */ 2549 if (this_frame != NULL) 2550 sp = get_frame_register_signed (this_frame, 2551 gdbarch_num_regs (gdbarch) 2552 + MIPS_SP_REGNUM); 2553 else 2554 sp = 0; 2555 2556 if (limit_pc > start_pc + 200) 2557 limit_pc = start_pc + 200; 2558 prev_pc = start_pc; 2559 2560 /* Permit at most one non-prologue non-control-transfer instruction 2561 in the middle which may have been reordered by the compiler for 2562 optimisation. */ 2563 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) 2564 { 2565 this_non_prologue_insn = 0; 2566 in_delay_slot = 0; 2567 2568 /* Save the previous instruction. If it's an EXTEND, we'll extract 2569 the immediate offset extension from it in mips16_get_imm. */ 2570 prev_inst = inst; 2571 2572 /* Fetch and decode the instruction. */ 2573 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, 2574 cur_pc, NULL); 2575 2576 /* Normally we ignore extend instructions. However, if it is 2577 not followed by a valid prologue instruction, then this 2578 instruction is not part of the prologue either. We must 2579 remember in this case to adjust the end_prologue_addr back 2580 over the extend. */ 2581 if ((inst & 0xf800) == 0xf000) /* extend */ 2582 { 2583 extend_bytes = MIPS_INSN16_SIZE; 2584 continue; 2585 } 2586 2587 prev_extend_bytes = extend_bytes; 2588 extend_bytes = 0; 2589 2590 if ((inst & 0xff00) == 0x6300 /* addiu sp */ 2591 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 2592 { 2593 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); 2594 if (offset < 0) /* Negative stack adjustment? */ 2595 frame_offset -= offset; 2596 else 2597 /* Exit loop if a positive stack adjustment is found, which 2598 usually means that the stack cleanup code in the function 2599 epilogue is reached. */ 2600 break; 2601 } 2602 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ 2603 { 2604 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2605 reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; 2606 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2607 } 2608 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ 2609 { 2610 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2611 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2612 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2613 } 2614 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ 2615 { 2616 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2617 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2618 } 2619 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ 2620 { 2621 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); 2622 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2623 } 2624 else if (inst == 0x673d) /* move $s1, $sp */ 2625 { 2626 frame_addr = sp; 2627 frame_reg = 17; 2628 } 2629 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ 2630 { 2631 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2632 frame_addr = sp + offset; 2633 frame_reg = 17; 2634 frame_adjust = offset; 2635 } 2636 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ 2637 { 2638 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); 2639 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2640 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2641 } 2642 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ 2643 { 2644 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2645 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2646 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2647 } 2648 else if ((inst & 0xf81f) == 0xe809 2649 && (inst & 0x700) != 0x700) /* entry */ 2650 entry_inst = inst; /* Save for later processing. */ 2651 else if ((inst & 0xff80) == 0x6480) /* save */ 2652 { 2653 save_inst = inst; /* Save for later processing. */ 2654 if (prev_extend_bytes) /* extend */ 2655 save_inst |= prev_inst << 16; 2656 } 2657 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ 2658 { 2659 /* This instruction is part of the prologue, but we don't 2660 need to do anything special to handle it. */ 2661 } 2662 else if (mips16_instruction_has_delay_slot (inst, 0)) 2663 /* JAL/JALR/JALX/JR */ 2664 { 2665 /* The instruction in the delay slot can be a part 2666 of the prologue, so move forward once more. */ 2667 in_delay_slot = 1; 2668 if (mips16_instruction_has_delay_slot (inst, 1)) 2669 /* JAL/JALX */ 2670 { 2671 prev_extend_bytes = MIPS_INSN16_SIZE; 2672 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ 2673 } 2674 } 2675 else 2676 { 2677 this_non_prologue_insn = 1; 2678 } 2679 2680 non_prologue_insns += this_non_prologue_insn; 2681 2682 /* A jump or branch, or enough non-prologue insns seen? If so, 2683 then we must have reached the end of the prologue by now. */ 2684 if (prev_delay_slot || non_prologue_insns > 1 2685 || mips16_instruction_is_compact_branch (inst)) 2686 break; 2687 2688 prev_non_prologue_insn = this_non_prologue_insn; 2689 prev_delay_slot = in_delay_slot; 2690 prev_pc = cur_pc - prev_extend_bytes; 2691 } 2692 2693 /* The entry instruction is typically the first instruction in a function, 2694 and it stores registers at offsets relative to the value of the old SP 2695 (before the prologue). But the value of the sp parameter to this 2696 function is the new SP (after the prologue has been executed). So we 2697 can't calculate those offsets until we've seen the entire prologue, 2698 and can calculate what the old SP must have been. */ 2699 if (entry_inst != 0) 2700 { 2701 int areg_count = (entry_inst >> 8) & 7; 2702 int sreg_count = (entry_inst >> 6) & 3; 2703 2704 /* The entry instruction always subtracts 32 from the SP. */ 2705 frame_offset += 32; 2706 2707 /* Now we can calculate what the SP must have been at the 2708 start of the function prologue. */ 2709 sp += frame_offset; 2710 2711 /* Check if a0-a3 were saved in the caller's argument save area. */ 2712 for (reg = 4, offset = 0; reg < areg_count + 4; reg++) 2713 { 2714 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2715 offset += mips_abi_regsize (gdbarch); 2716 } 2717 2718 /* Check if the ra register was pushed on the stack. */ 2719 offset = -4; 2720 if (entry_inst & 0x20) 2721 { 2722 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2723 offset -= mips_abi_regsize (gdbarch); 2724 } 2725 2726 /* Check if the s0 and s1 registers were pushed on the stack. */ 2727 for (reg = 16; reg < sreg_count + 16; reg++) 2728 { 2729 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2730 offset -= mips_abi_regsize (gdbarch); 2731 } 2732 } 2733 2734 /* The SAVE instruction is similar to ENTRY, except that defined by the 2735 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the 2736 size of the frame is specified as an immediate field of instruction 2737 and an extended variation exists which lets additional registers and 2738 frame space to be specified. The instruction always treats registers 2739 as 32-bit so its usefulness for 64-bit ABIs is questionable. */ 2740 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) 2741 { 2742 static int args_table[16] = { 2743 0, 0, 0, 0, 1, 1, 1, 1, 2744 2, 2, 2, 0, 3, 3, 4, -1, 2745 }; 2746 static int astatic_table[16] = { 2747 0, 1, 2, 3, 0, 1, 2, 3, 2748 0, 1, 2, 4, 0, 1, 0, -1, 2749 }; 2750 int aregs = (save_inst >> 16) & 0xf; 2751 int xsregs = (save_inst >> 24) & 0x7; 2752 int args = args_table[aregs]; 2753 int astatic = astatic_table[aregs]; 2754 long frame_size; 2755 2756 if (args < 0) 2757 { 2758 warning (_("Invalid number of argument registers encoded in SAVE.")); 2759 args = 0; 2760 } 2761 if (astatic < 0) 2762 { 2763 warning (_("Invalid number of static registers encoded in SAVE.")); 2764 astatic = 0; 2765 } 2766 2767 /* For standard SAVE the frame size of 0 means 128. */ 2768 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); 2769 if (frame_size == 0 && (save_inst >> 16) == 0) 2770 frame_size = 16; 2771 frame_size *= 8; 2772 frame_offset += frame_size; 2773 2774 /* Now we can calculate what the SP must have been at the 2775 start of the function prologue. */ 2776 sp += frame_offset; 2777 2778 /* Check if A0-A3 were saved in the caller's argument save area. */ 2779 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) 2780 { 2781 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2782 offset += mips_abi_regsize (gdbarch); 2783 } 2784 2785 offset = -4; 2786 2787 /* Check if the RA register was pushed on the stack. */ 2788 if (save_inst & 0x40) 2789 { 2790 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2791 offset -= mips_abi_regsize (gdbarch); 2792 } 2793 2794 /* Check if the S8 register was pushed on the stack. */ 2795 if (xsregs > 6) 2796 { 2797 set_reg_offset (gdbarch, this_cache, 30, sp + offset); 2798 offset -= mips_abi_regsize (gdbarch); 2799 xsregs--; 2800 } 2801 /* Check if S2-S7 were pushed on the stack. */ 2802 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) 2803 { 2804 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2805 offset -= mips_abi_regsize (gdbarch); 2806 } 2807 2808 /* Check if the S1 register was pushed on the stack. */ 2809 if (save_inst & 0x10) 2810 { 2811 set_reg_offset (gdbarch, this_cache, 17, sp + offset); 2812 offset -= mips_abi_regsize (gdbarch); 2813 } 2814 /* Check if the S0 register was pushed on the stack. */ 2815 if (save_inst & 0x20) 2816 { 2817 set_reg_offset (gdbarch, this_cache, 16, sp + offset); 2818 offset -= mips_abi_regsize (gdbarch); 2819 } 2820 2821 /* Check if A0-A3 were pushed on the stack. */ 2822 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) 2823 { 2824 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2825 offset -= mips_abi_regsize (gdbarch); 2826 } 2827 } 2828 2829 if (this_cache != NULL) 2830 { 2831 this_cache->base = 2832 (get_frame_register_signed (this_frame, 2833 gdbarch_num_regs (gdbarch) + frame_reg) 2834 + frame_offset - frame_adjust); 2835 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 2836 be able to get rid of the assignment below, evetually. But it's 2837 still needed for now. */ 2838 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 2839 + mips_regnum (gdbarch)->pc] 2840 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 2841 } 2842 2843 /* Set end_prologue_addr to the address of the instruction immediately 2844 after the last one we scanned. Unless the last one looked like a 2845 non-prologue instruction (and we looked ahead), in which case use 2846 its address instead. */ 2847 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot 2848 ? prev_pc : cur_pc - prev_extend_bytes); 2849 2850 return end_prologue_addr; 2851 } 2852 2853 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). 2854 Procedures that use the 32-bit instruction set are handled by the 2855 mips_insn32 unwinder. */ 2856 2857 static struct mips_frame_cache * 2858 mips_insn16_frame_cache (frame_info_ptr this_frame, void **this_cache) 2859 { 2860 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2861 struct mips_frame_cache *cache; 2862 2863 if ((*this_cache) != NULL) 2864 return (struct mips_frame_cache *) (*this_cache); 2865 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 2866 (*this_cache) = cache; 2867 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 2868 2869 /* Analyze the function prologue. */ 2870 { 2871 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 2872 CORE_ADDR start_addr; 2873 2874 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2875 if (start_addr == 0) 2876 start_addr = heuristic_proc_start (gdbarch, pc); 2877 /* We can't analyze the prologue if we couldn't find the begining 2878 of the function. */ 2879 if (start_addr == 0) 2880 return cache; 2881 2882 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, 2883 (struct mips_frame_cache *) *this_cache); 2884 } 2885 2886 /* gdbarch_sp_regnum contains the value and not the address. */ 2887 cache->saved_regs[gdbarch_num_regs (gdbarch) 2888 + MIPS_SP_REGNUM].set_value (cache->base); 2889 2890 return (struct mips_frame_cache *) (*this_cache); 2891 } 2892 2893 static void 2894 mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache, 2895 struct frame_id *this_id) 2896 { 2897 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2898 this_cache); 2899 /* This marks the outermost frame. */ 2900 if (info->base == 0) 2901 return; 2902 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 2903 } 2904 2905 static struct value * 2906 mips_insn16_frame_prev_register (frame_info_ptr this_frame, 2907 void **this_cache, int regnum) 2908 { 2909 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2910 this_cache); 2911 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 2912 } 2913 2914 static int 2915 mips_insn16_frame_sniffer (const struct frame_unwind *self, 2916 frame_info_ptr this_frame, void **this_cache) 2917 { 2918 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2919 CORE_ADDR pc = get_frame_pc (this_frame); 2920 if (mips_pc_is_mips16 (gdbarch, pc)) 2921 return 1; 2922 return 0; 2923 } 2924 2925 static const struct frame_unwind mips_insn16_frame_unwind = 2926 { 2927 "mips insn16 prologue", 2928 NORMAL_FRAME, 2929 default_frame_unwind_stop_reason, 2930 mips_insn16_frame_this_id, 2931 mips_insn16_frame_prev_register, 2932 NULL, 2933 mips_insn16_frame_sniffer 2934 }; 2935 2936 static CORE_ADDR 2937 mips_insn16_frame_base_address (frame_info_ptr this_frame, 2938 void **this_cache) 2939 { 2940 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2941 this_cache); 2942 return info->base; 2943 } 2944 2945 static const struct frame_base mips_insn16_frame_base = 2946 { 2947 &mips_insn16_frame_unwind, 2948 mips_insn16_frame_base_address, 2949 mips_insn16_frame_base_address, 2950 mips_insn16_frame_base_address 2951 }; 2952 2953 static const struct frame_base * 2954 mips_insn16_frame_base_sniffer (frame_info_ptr this_frame) 2955 { 2956 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2957 CORE_ADDR pc = get_frame_pc (this_frame); 2958 if (mips_pc_is_mips16 (gdbarch, pc)) 2959 return &mips_insn16_frame_base; 2960 else 2961 return NULL; 2962 } 2963 2964 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped 2965 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are 2966 interpreted directly, and then multiplied by 4. */ 2967 2968 static int 2969 micromips_decode_imm9 (int imm) 2970 { 2971 imm = (imm ^ 0x100) - 0x100; 2972 if (imm > -3 && imm < 2) 2973 imm ^= 0x100; 2974 return imm << 2; 2975 } 2976 2977 /* Analyze the function prologue from START_PC to LIMIT_PC. Return 2978 the address of the first instruction past the prologue. */ 2979 2980 static CORE_ADDR 2981 micromips_scan_prologue (struct gdbarch *gdbarch, 2982 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2983 frame_info_ptr this_frame, 2984 struct mips_frame_cache *this_cache) 2985 { 2986 CORE_ADDR end_prologue_addr; 2987 int prev_non_prologue_insn = 0; 2988 int frame_reg = MIPS_SP_REGNUM; 2989 int this_non_prologue_insn; 2990 int non_prologue_insns = 0; 2991 long frame_offset = 0; /* Size of stack frame. */ 2992 long frame_adjust = 0; /* Offset of FP from SP. */ 2993 int prev_delay_slot = 0; 2994 int in_delay_slot; 2995 CORE_ADDR prev_pc; 2996 CORE_ADDR cur_pc; 2997 ULONGEST insn; /* current instruction */ 2998 CORE_ADDR sp; 2999 long offset; 3000 long sp_adj; 3001 long v1_off = 0; /* The assumption is LUI will replace it. */ 3002 int reglist; 3003 int breg; 3004 int dreg; 3005 int sreg; 3006 int treg; 3007 int loc; 3008 int op; 3009 int s; 3010 int i; 3011 3012 /* Can be called when there's no process, and hence when there's no 3013 THIS_FRAME. */ 3014 if (this_frame != NULL) 3015 sp = get_frame_register_signed (this_frame, 3016 gdbarch_num_regs (gdbarch) 3017 + MIPS_SP_REGNUM); 3018 else 3019 sp = 0; 3020 3021 if (limit_pc > start_pc + 200) 3022 limit_pc = start_pc + 200; 3023 prev_pc = start_pc; 3024 3025 /* Permit at most one non-prologue non-control-transfer instruction 3026 in the middle which may have been reordered by the compiler for 3027 optimisation. */ 3028 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) 3029 { 3030 this_non_prologue_insn = 0; 3031 in_delay_slot = 0; 3032 sp_adj = 0; 3033 loc = 0; 3034 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); 3035 loc += MIPS_INSN16_SIZE; 3036 switch (mips_insn_size (ISA_MICROMIPS, insn)) 3037 { 3038 /* 32-bit instructions. */ 3039 case 2 * MIPS_INSN16_SIZE: 3040 insn <<= 16; 3041 insn |= mips_fetch_instruction (gdbarch, 3042 ISA_MICROMIPS, cur_pc + loc, NULL); 3043 loc += MIPS_INSN16_SIZE; 3044 switch (micromips_op (insn >> 16)) 3045 { 3046 /* Record $sp/$fp adjustment. */ 3047 /* Discard (D)ADDU $gp,$jp used for PIC code. */ 3048 case 0x0: /* POOL32A: bits 000000 */ 3049 case 0x16: /* POOL32S: bits 010110 */ 3050 op = b0s11_op (insn); 3051 sreg = b0s5_reg (insn >> 16); 3052 treg = b5s5_reg (insn >> 16); 3053 dreg = b11s5_reg (insn); 3054 if (op == 0x1d0 3055 /* SUBU: bits 000000 00111010000 */ 3056 /* DSUBU: bits 010110 00111010000 */ 3057 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM 3058 && treg == 3) 3059 /* (D)SUBU $sp, $v1 */ 3060 sp_adj = v1_off; 3061 else if (op != 0x150 3062 /* ADDU: bits 000000 00101010000 */ 3063 /* DADDU: bits 010110 00101010000 */ 3064 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) 3065 this_non_prologue_insn = 1; 3066 break; 3067 3068 case 0x8: /* POOL32B: bits 001000 */ 3069 op = b12s4_op (insn); 3070 breg = b0s5_reg (insn >> 16); 3071 reglist = sreg = b5s5_reg (insn >> 16); 3072 offset = (b0s12_imm (insn) ^ 0x800) - 0x800; 3073 if ((op == 0x9 || op == 0xc) 3074 /* SWP: bits 001000 1001 */ 3075 /* SDP: bits 001000 1100 */ 3076 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) 3077 /* S[DW]P reg,offset($sp) */ 3078 { 3079 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); 3080 set_reg_offset (gdbarch, this_cache, 3081 sreg, sp + offset); 3082 set_reg_offset (gdbarch, this_cache, 3083 sreg + 1, sp + offset + s); 3084 } 3085 else if ((op == 0xd || op == 0xf) 3086 /* SWM: bits 001000 1101 */ 3087 /* SDM: bits 001000 1111 */ 3088 && breg == MIPS_SP_REGNUM 3089 /* SWM reglist,offset($sp) */ 3090 && ((reglist >= 1 && reglist <= 9) 3091 || (reglist >= 16 && reglist <= 25))) 3092 { 3093 int sreglist = std::min(reglist & 0xf, 8); 3094 3095 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); 3096 for (i = 0; i < sreglist; i++) 3097 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); 3098 if ((reglist & 0xf) > 8) 3099 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); 3100 if ((reglist & 0x10) == 0x10) 3101 set_reg_offset (gdbarch, this_cache, 3102 MIPS_RA_REGNUM, sp + s * i++); 3103 } 3104 else 3105 this_non_prologue_insn = 1; 3106 break; 3107 3108 /* Record $sp/$fp adjustment. */ 3109 /* Discard (D)ADDIU $gp used for PIC code. */ 3110 case 0xc: /* ADDIU: bits 001100 */ 3111 case 0x17: /* DADDIU: bits 010111 */ 3112 sreg = b0s5_reg (insn >> 16); 3113 dreg = b5s5_reg (insn >> 16); 3114 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3115 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) 3116 /* (D)ADDIU $sp, imm */ 3117 sp_adj = offset; 3118 else if (sreg == MIPS_SP_REGNUM && dreg == 30) 3119 /* (D)ADDIU $fp, $sp, imm */ 3120 { 3121 frame_adjust = offset; 3122 frame_reg = 30; 3123 } 3124 else if (sreg != 28 || dreg != 28) 3125 /* (D)ADDIU $gp, imm */ 3126 this_non_prologue_insn = 1; 3127 break; 3128 3129 /* LUI $v1 is used for larger $sp adjustments. */ 3130 /* Discard LUI $gp used for PIC code. */ 3131 case 0x10: /* POOL32I: bits 010000 */ 3132 if (b5s5_op (insn >> 16) == 0xd 3133 /* LUI: bits 010000 001101 */ 3134 && b0s5_reg (insn >> 16) == 3) 3135 /* LUI $v1, imm */ 3136 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; 3137 else if (b5s5_op (insn >> 16) != 0xd 3138 /* LUI: bits 010000 001101 */ 3139 || b0s5_reg (insn >> 16) != 28) 3140 /* LUI $gp, imm */ 3141 this_non_prologue_insn = 1; 3142 break; 3143 3144 /* ORI $v1 is used for larger $sp adjustments. */ 3145 case 0x14: /* ORI: bits 010100 */ 3146 sreg = b0s5_reg (insn >> 16); 3147 dreg = b5s5_reg (insn >> 16); 3148 if (sreg == 3 && dreg == 3) 3149 /* ORI $v1, imm */ 3150 v1_off |= b0s16_imm (insn); 3151 else 3152 this_non_prologue_insn = 1; 3153 break; 3154 3155 case 0x26: /* SWC1: bits 100110 */ 3156 case 0x2e: /* SDC1: bits 101110 */ 3157 breg = b0s5_reg (insn >> 16); 3158 if (breg != MIPS_SP_REGNUM) 3159 /* S[DW]C1 reg,offset($sp) */ 3160 this_non_prologue_insn = 1; 3161 break; 3162 3163 case 0x36: /* SD: bits 110110 */ 3164 case 0x3e: /* SW: bits 111110 */ 3165 breg = b0s5_reg (insn >> 16); 3166 sreg = b5s5_reg (insn >> 16); 3167 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3168 if (breg == MIPS_SP_REGNUM) 3169 /* S[DW] reg,offset($sp) */ 3170 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3171 else 3172 this_non_prologue_insn = 1; 3173 break; 3174 3175 default: 3176 /* The instruction in the delay slot can be a part 3177 of the prologue, so move forward once more. */ 3178 if (micromips_instruction_has_delay_slot (insn, 0)) 3179 in_delay_slot = 1; 3180 else 3181 this_non_prologue_insn = 1; 3182 break; 3183 } 3184 insn >>= 16; 3185 break; 3186 3187 /* 16-bit instructions. */ 3188 case MIPS_INSN16_SIZE: 3189 switch (micromips_op (insn)) 3190 { 3191 case 0x3: /* MOVE: bits 000011 */ 3192 sreg = b0s5_reg (insn); 3193 dreg = b5s5_reg (insn); 3194 if (sreg == MIPS_SP_REGNUM && dreg == 30) 3195 /* MOVE $fp, $sp */ 3196 frame_reg = 30; 3197 else if ((sreg & 0x1c) != 0x4) 3198 /* MOVE reg, $a0-$a3 */ 3199 this_non_prologue_insn = 1; 3200 break; 3201 3202 case 0x11: /* POOL16C: bits 010001 */ 3203 if (b6s4_op (insn) == 0x5) 3204 /* SWM: bits 010001 0101 */ 3205 { 3206 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; 3207 reglist = b4s2_regl (insn); 3208 for (i = 0; i <= reglist; i++) 3209 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); 3210 set_reg_offset (gdbarch, this_cache, 3211 MIPS_RA_REGNUM, sp + 4 * i++); 3212 } 3213 else 3214 this_non_prologue_insn = 1; 3215 break; 3216 3217 case 0x13: /* POOL16D: bits 010011 */ 3218 if ((insn & 0x1) == 0x1) 3219 /* ADDIUSP: bits 010011 1 */ 3220 sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); 3221 else if (b5s5_reg (insn) == MIPS_SP_REGNUM) 3222 /* ADDIUS5: bits 010011 0 */ 3223 /* ADDIUS5 $sp, imm */ 3224 sp_adj = (b1s4_imm (insn) ^ 8) - 8; 3225 else 3226 this_non_prologue_insn = 1; 3227 break; 3228 3229 case 0x32: /* SWSP: bits 110010 */ 3230 offset = b0s5_imm (insn) << 2; 3231 sreg = b5s5_reg (insn); 3232 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3233 break; 3234 3235 default: 3236 /* The instruction in the delay slot can be a part 3237 of the prologue, so move forward once more. */ 3238 if (micromips_instruction_has_delay_slot (insn << 16, 0)) 3239 in_delay_slot = 1; 3240 else 3241 this_non_prologue_insn = 1; 3242 break; 3243 } 3244 break; 3245 } 3246 if (sp_adj < 0) 3247 frame_offset -= sp_adj; 3248 3249 non_prologue_insns += this_non_prologue_insn; 3250 3251 /* A jump or branch, enough non-prologue insns seen or positive 3252 stack adjustment? If so, then we must have reached the end 3253 of the prologue by now. */ 3254 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 3255 || micromips_instruction_is_compact_branch (insn)) 3256 break; 3257 3258 prev_non_prologue_insn = this_non_prologue_insn; 3259 prev_delay_slot = in_delay_slot; 3260 prev_pc = cur_pc; 3261 } 3262 3263 if (this_cache != NULL) 3264 { 3265 this_cache->base = 3266 (get_frame_register_signed (this_frame, 3267 gdbarch_num_regs (gdbarch) + frame_reg) 3268 + frame_offset - frame_adjust); 3269 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 3270 be able to get rid of the assignment below, evetually. But it's 3271 still needed for now. */ 3272 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3273 + mips_regnum (gdbarch)->pc] 3274 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 3275 } 3276 3277 /* Set end_prologue_addr to the address of the instruction immediately 3278 after the last one we scanned. Unless the last one looked like a 3279 non-prologue instruction (and we looked ahead), in which case use 3280 its address instead. */ 3281 end_prologue_addr 3282 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3283 3284 return end_prologue_addr; 3285 } 3286 3287 /* Heuristic unwinder for procedures using microMIPS instructions. 3288 Procedures that use the 32-bit instruction set are handled by the 3289 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ 3290 3291 static struct mips_frame_cache * 3292 mips_micro_frame_cache (frame_info_ptr this_frame, void **this_cache) 3293 { 3294 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3295 struct mips_frame_cache *cache; 3296 3297 if ((*this_cache) != NULL) 3298 return (struct mips_frame_cache *) (*this_cache); 3299 3300 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3301 (*this_cache) = cache; 3302 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3303 3304 /* Analyze the function prologue. */ 3305 { 3306 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3307 CORE_ADDR start_addr; 3308 3309 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3310 if (start_addr == 0) 3311 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); 3312 /* We can't analyze the prologue if we couldn't find the begining 3313 of the function. */ 3314 if (start_addr == 0) 3315 return cache; 3316 3317 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, 3318 (struct mips_frame_cache *) *this_cache); 3319 } 3320 3321 /* gdbarch_sp_regnum contains the value and not the address. */ 3322 cache->saved_regs[gdbarch_num_regs (gdbarch) 3323 + MIPS_SP_REGNUM].set_value (cache->base); 3324 3325 return (struct mips_frame_cache *) (*this_cache); 3326 } 3327 3328 static void 3329 mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache, 3330 struct frame_id *this_id) 3331 { 3332 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3333 this_cache); 3334 /* This marks the outermost frame. */ 3335 if (info->base == 0) 3336 return; 3337 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3338 } 3339 3340 static struct value * 3341 mips_micro_frame_prev_register (frame_info_ptr this_frame, 3342 void **this_cache, int regnum) 3343 { 3344 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3345 this_cache); 3346 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3347 } 3348 3349 static int 3350 mips_micro_frame_sniffer (const struct frame_unwind *self, 3351 frame_info_ptr this_frame, void **this_cache) 3352 { 3353 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3354 CORE_ADDR pc = get_frame_pc (this_frame); 3355 3356 if (mips_pc_is_micromips (gdbarch, pc)) 3357 return 1; 3358 return 0; 3359 } 3360 3361 static const struct frame_unwind mips_micro_frame_unwind = 3362 { 3363 "mips micro prologue", 3364 NORMAL_FRAME, 3365 default_frame_unwind_stop_reason, 3366 mips_micro_frame_this_id, 3367 mips_micro_frame_prev_register, 3368 NULL, 3369 mips_micro_frame_sniffer 3370 }; 3371 3372 static CORE_ADDR 3373 mips_micro_frame_base_address (frame_info_ptr this_frame, 3374 void **this_cache) 3375 { 3376 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3377 this_cache); 3378 return info->base; 3379 } 3380 3381 static const struct frame_base mips_micro_frame_base = 3382 { 3383 &mips_micro_frame_unwind, 3384 mips_micro_frame_base_address, 3385 mips_micro_frame_base_address, 3386 mips_micro_frame_base_address 3387 }; 3388 3389 static const struct frame_base * 3390 mips_micro_frame_base_sniffer (frame_info_ptr this_frame) 3391 { 3392 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3393 CORE_ADDR pc = get_frame_pc (this_frame); 3394 3395 if (mips_pc_is_micromips (gdbarch, pc)) 3396 return &mips_micro_frame_base; 3397 else 3398 return NULL; 3399 } 3400 3401 /* Mark all the registers as unset in the saved_regs array 3402 of THIS_CACHE. Do nothing if THIS_CACHE is null. */ 3403 3404 static void 3405 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) 3406 { 3407 if (this_cache == NULL || this_cache->saved_regs == NULL) 3408 return; 3409 3410 { 3411 const int num_regs = gdbarch_num_regs (gdbarch); 3412 int i; 3413 3414 /* Reset the register values to their default state. Register i's value 3415 is in register i. */ 3416 for (i = 0; i < num_regs; i++) 3417 this_cache->saved_regs[i].set_realreg (i); 3418 } 3419 } 3420 3421 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 3422 the associated FRAME_CACHE if not null. 3423 Return the address of the first instruction past the prologue. */ 3424 3425 static CORE_ADDR 3426 mips32_scan_prologue (struct gdbarch *gdbarch, 3427 CORE_ADDR start_pc, CORE_ADDR limit_pc, 3428 frame_info_ptr this_frame, 3429 struct mips_frame_cache *this_cache) 3430 { 3431 int prev_non_prologue_insn; 3432 int this_non_prologue_insn; 3433 int non_prologue_insns; 3434 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for 3435 frame-pointer. */ 3436 int prev_delay_slot; 3437 CORE_ADDR prev_pc; 3438 CORE_ADDR cur_pc; 3439 CORE_ADDR sp; 3440 long frame_offset; 3441 int frame_reg = MIPS_SP_REGNUM; 3442 3443 CORE_ADDR end_prologue_addr; 3444 int seen_sp_adjust = 0; 3445 int load_immediate_bytes = 0; 3446 int in_delay_slot; 3447 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); 3448 3449 /* Can be called when there's no process, and hence when there's no 3450 THIS_FRAME. */ 3451 if (this_frame != NULL) 3452 sp = get_frame_register_signed (this_frame, 3453 gdbarch_num_regs (gdbarch) 3454 + MIPS_SP_REGNUM); 3455 else 3456 sp = 0; 3457 3458 if (limit_pc > start_pc + 200) 3459 limit_pc = start_pc + 200; 3460 3461 restart: 3462 prev_non_prologue_insn = 0; 3463 non_prologue_insns = 0; 3464 prev_delay_slot = 0; 3465 prev_pc = start_pc; 3466 3467 /* Permit at most one non-prologue non-control-transfer instruction 3468 in the middle which may have been reordered by the compiler for 3469 optimisation. */ 3470 frame_offset = 0; 3471 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) 3472 { 3473 unsigned long inst, high_word; 3474 long offset; 3475 int reg; 3476 3477 this_non_prologue_insn = 0; 3478 in_delay_slot = 0; 3479 3480 /* Fetch the instruction. */ 3481 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, 3482 cur_pc, NULL); 3483 3484 /* Save some code by pre-extracting some useful fields. */ 3485 high_word = (inst >> 16) & 0xffff; 3486 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; 3487 reg = high_word & 0x1f; 3488 3489 if (high_word == 0x27bd /* addiu $sp,$sp,-i */ 3490 || high_word == 0x23bd /* addi $sp,$sp,-i */ 3491 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ 3492 { 3493 if (offset < 0) /* Negative stack adjustment? */ 3494 frame_offset -= offset; 3495 else 3496 /* Exit loop if a positive stack adjustment is found, which 3497 usually means that the stack cleanup code in the function 3498 epilogue is reached. */ 3499 break; 3500 seen_sp_adjust = 1; 3501 } 3502 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ 3503 && !regsize_is_64_bits) 3504 { 3505 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3506 } 3507 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ 3508 && regsize_is_64_bits) 3509 { 3510 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ 3511 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3512 } 3513 else if (high_word == 0x27be) /* addiu $30,$sp,size */ 3514 { 3515 /* Old gcc frame, r30 is virtual frame pointer. */ 3516 if (offset != frame_offset) 3517 frame_addr = sp + offset; 3518 else if (this_frame && frame_reg == MIPS_SP_REGNUM) 3519 { 3520 unsigned alloca_adjust; 3521 3522 frame_reg = 30; 3523 frame_addr = get_frame_register_signed 3524 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3525 frame_offset = 0; 3526 3527 alloca_adjust = (unsigned) (frame_addr - (sp + offset)); 3528 if (alloca_adjust > 0) 3529 { 3530 /* FP > SP + frame_size. This may be because of 3531 an alloca or somethings similar. Fix sp to 3532 "pre-alloca" value, and try again. */ 3533 sp += alloca_adjust; 3534 /* Need to reset the status of all registers. Otherwise, 3535 we will hit a guard that prevents the new address 3536 for each register to be recomputed during the second 3537 pass. */ 3538 reset_saved_regs (gdbarch, this_cache); 3539 goto restart; 3540 } 3541 } 3542 } 3543 /* move $30,$sp. With different versions of gas this will be either 3544 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. 3545 Accept any one of these. */ 3546 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) 3547 { 3548 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ 3549 if (this_frame && frame_reg == MIPS_SP_REGNUM) 3550 { 3551 unsigned alloca_adjust; 3552 3553 frame_reg = 30; 3554 frame_addr = get_frame_register_signed 3555 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3556 3557 alloca_adjust = (unsigned) (frame_addr - sp); 3558 if (alloca_adjust > 0) 3559 { 3560 /* FP > SP + frame_size. This may be because of 3561 an alloca or somethings similar. Fix sp to 3562 "pre-alloca" value, and try again. */ 3563 sp = frame_addr; 3564 /* Need to reset the status of all registers. Otherwise, 3565 we will hit a guard that prevents the new address 3566 for each register to be recomputed during the second 3567 pass. */ 3568 reset_saved_regs (gdbarch, this_cache); 3569 goto restart; 3570 } 3571 } 3572 } 3573 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ 3574 && !regsize_is_64_bits) 3575 { 3576 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 3577 } 3578 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ 3579 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ 3580 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ 3581 || high_word == 0x3c1c /* lui $gp,n */ 3582 || high_word == 0x279c /* addiu $gp,$gp,n */ 3583 || high_word == 0x679c /* daddiu $gp,$gp,n */ 3584 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ 3585 || inst == 0x033ce021 /* addu $gp,$t9,$gp */ 3586 || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */ 3587 || inst == 0x033ce02d /* daddu $gp,$t9,$gp */ 3588 ) 3589 { 3590 /* These instructions are part of the prologue, but we don't 3591 need to do anything special to handle them. */ 3592 } 3593 /* The instructions below load $at or $t0 with an immediate 3594 value in preparation for a stack adjustment via 3595 subu $sp,$sp,[$at,$t0]. These instructions could also 3596 initialize a local variable, so we accept them only before 3597 a stack adjustment instruction was seen. */ 3598 else if (!seen_sp_adjust 3599 && !prev_delay_slot 3600 && (high_word == 0x3c01 /* lui $at,n */ 3601 || high_word == 0x3c08 /* lui $t0,n */ 3602 || high_word == 0x3421 /* ori $at,$at,n */ 3603 || high_word == 0x3508 /* ori $t0,$t0,n */ 3604 || high_word == 0x3401 /* ori $at,$zero,n */ 3605 || high_word == 0x3408 /* ori $t0,$zero,n */ 3606 )) 3607 { 3608 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ 3609 } 3610 /* Check for branches and jumps. The instruction in the delay 3611 slot can be a part of the prologue, so move forward once more. */ 3612 else if (mips32_instruction_has_delay_slot (gdbarch, inst)) 3613 { 3614 in_delay_slot = 1; 3615 } 3616 /* This instruction is not an instruction typically found 3617 in a prologue, so we must have reached the end of the 3618 prologue. */ 3619 else 3620 { 3621 this_non_prologue_insn = 1; 3622 } 3623 3624 non_prologue_insns += this_non_prologue_insn; 3625 3626 /* A jump or branch, or enough non-prologue insns seen? If so, 3627 then we must have reached the end of the prologue by now. */ 3628 if (prev_delay_slot || non_prologue_insns > 1) 3629 break; 3630 3631 prev_non_prologue_insn = this_non_prologue_insn; 3632 prev_delay_slot = in_delay_slot; 3633 prev_pc = cur_pc; 3634 } 3635 3636 if (this_cache != NULL) 3637 { 3638 this_cache->base = 3639 (get_frame_register_signed (this_frame, 3640 gdbarch_num_regs (gdbarch) + frame_reg) 3641 + frame_offset); 3642 /* FIXME: brobecker/2004-09-15: We should be able to get rid of 3643 this assignment below, eventually. But it's still needed 3644 for now. */ 3645 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3646 + mips_regnum (gdbarch)->pc] 3647 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3648 + MIPS_RA_REGNUM]; 3649 } 3650 3651 /* Set end_prologue_addr to the address of the instruction immediately 3652 after the last one we scanned. Unless the last one looked like a 3653 non-prologue instruction (and we looked ahead), in which case use 3654 its address instead. */ 3655 end_prologue_addr 3656 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3657 3658 /* In a frameless function, we might have incorrectly 3659 skipped some load immediate instructions. Undo the skipping 3660 if the load immediate was not followed by a stack adjustment. */ 3661 if (load_immediate_bytes && !seen_sp_adjust) 3662 end_prologue_addr -= load_immediate_bytes; 3663 3664 return end_prologue_addr; 3665 } 3666 3667 /* Heuristic unwinder for procedures using 32-bit instructions (covers 3668 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit 3669 instructions (a.k.a. MIPS16) are handled by the mips_insn16 3670 unwinder. Likewise microMIPS and the mips_micro unwinder. */ 3671 3672 static struct mips_frame_cache * 3673 mips_insn32_frame_cache (frame_info_ptr this_frame, void **this_cache) 3674 { 3675 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3676 struct mips_frame_cache *cache; 3677 3678 if ((*this_cache) != NULL) 3679 return (struct mips_frame_cache *) (*this_cache); 3680 3681 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3682 (*this_cache) = cache; 3683 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3684 3685 /* Analyze the function prologue. */ 3686 { 3687 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3688 CORE_ADDR start_addr; 3689 3690 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3691 if (start_addr == 0) 3692 start_addr = heuristic_proc_start (gdbarch, pc); 3693 /* We can't analyze the prologue if we couldn't find the begining 3694 of the function. */ 3695 if (start_addr == 0) 3696 return cache; 3697 3698 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, 3699 (struct mips_frame_cache *) *this_cache); 3700 } 3701 3702 /* gdbarch_sp_regnum contains the value and not the address. */ 3703 cache->saved_regs[gdbarch_num_regs (gdbarch) 3704 + MIPS_SP_REGNUM].set_value (cache->base); 3705 3706 return (struct mips_frame_cache *) (*this_cache); 3707 } 3708 3709 static void 3710 mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache, 3711 struct frame_id *this_id) 3712 { 3713 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3714 this_cache); 3715 /* This marks the outermost frame. */ 3716 if (info->base == 0) 3717 return; 3718 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3719 } 3720 3721 static struct value * 3722 mips_insn32_frame_prev_register (frame_info_ptr this_frame, 3723 void **this_cache, int regnum) 3724 { 3725 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3726 this_cache); 3727 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3728 } 3729 3730 static int 3731 mips_insn32_frame_sniffer (const struct frame_unwind *self, 3732 frame_info_ptr this_frame, void **this_cache) 3733 { 3734 CORE_ADDR pc = get_frame_pc (this_frame); 3735 if (mips_pc_is_mips (pc)) 3736 return 1; 3737 return 0; 3738 } 3739 3740 static const struct frame_unwind mips_insn32_frame_unwind = 3741 { 3742 "mips insn32 prologue", 3743 NORMAL_FRAME, 3744 default_frame_unwind_stop_reason, 3745 mips_insn32_frame_this_id, 3746 mips_insn32_frame_prev_register, 3747 NULL, 3748 mips_insn32_frame_sniffer 3749 }; 3750 3751 static CORE_ADDR 3752 mips_insn32_frame_base_address (frame_info_ptr this_frame, 3753 void **this_cache) 3754 { 3755 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3756 this_cache); 3757 return info->base; 3758 } 3759 3760 static const struct frame_base mips_insn32_frame_base = 3761 { 3762 &mips_insn32_frame_unwind, 3763 mips_insn32_frame_base_address, 3764 mips_insn32_frame_base_address, 3765 mips_insn32_frame_base_address 3766 }; 3767 3768 static const struct frame_base * 3769 mips_insn32_frame_base_sniffer (frame_info_ptr this_frame) 3770 { 3771 CORE_ADDR pc = get_frame_pc (this_frame); 3772 if (mips_pc_is_mips (pc)) 3773 return &mips_insn32_frame_base; 3774 else 3775 return NULL; 3776 } 3777 3778 static struct trad_frame_cache * 3779 mips_stub_frame_cache (frame_info_ptr this_frame, void **this_cache) 3780 { 3781 CORE_ADDR pc; 3782 CORE_ADDR start_addr; 3783 CORE_ADDR stack_addr; 3784 struct trad_frame_cache *this_trad_cache; 3785 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3786 int num_regs = gdbarch_num_regs (gdbarch); 3787 3788 if ((*this_cache) != NULL) 3789 return (struct trad_frame_cache *) (*this_cache); 3790 this_trad_cache = trad_frame_cache_zalloc (this_frame); 3791 (*this_cache) = this_trad_cache; 3792 3793 /* The return address is in the link register. */ 3794 trad_frame_set_reg_realreg (this_trad_cache, 3795 gdbarch_pc_regnum (gdbarch), 3796 num_regs + MIPS_RA_REGNUM); 3797 3798 /* Frame ID, since it's a frameless / stackless function, no stack 3799 space is allocated and SP on entry is the current SP. */ 3800 pc = get_frame_pc (this_frame); 3801 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3802 stack_addr = get_frame_register_signed (this_frame, 3803 num_regs + MIPS_SP_REGNUM); 3804 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); 3805 3806 /* Assume that the frame's base is the same as the 3807 stack-pointer. */ 3808 trad_frame_set_this_base (this_trad_cache, stack_addr); 3809 3810 return this_trad_cache; 3811 } 3812 3813 static void 3814 mips_stub_frame_this_id (frame_info_ptr this_frame, void **this_cache, 3815 struct frame_id *this_id) 3816 { 3817 struct trad_frame_cache *this_trad_cache 3818 = mips_stub_frame_cache (this_frame, this_cache); 3819 trad_frame_get_id (this_trad_cache, this_id); 3820 } 3821 3822 static struct value * 3823 mips_stub_frame_prev_register (frame_info_ptr this_frame, 3824 void **this_cache, int regnum) 3825 { 3826 struct trad_frame_cache *this_trad_cache 3827 = mips_stub_frame_cache (this_frame, this_cache); 3828 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 3829 } 3830 3831 static int 3832 mips_stub_frame_sniffer (const struct frame_unwind *self, 3833 frame_info_ptr this_frame, void **this_cache) 3834 { 3835 gdb_byte dummy[4]; 3836 CORE_ADDR pc = get_frame_address_in_block (this_frame); 3837 struct bound_minimal_symbol msym; 3838 3839 /* Use the stub unwinder for unreadable code. */ 3840 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 3841 return 1; 3842 3843 if (in_plt_section (pc) || in_mips_stubs_section (pc)) 3844 return 1; 3845 3846 /* Calling a PIC function from a non-PIC function passes through a 3847 stub. The stub for foo is named ".pic.foo". */ 3848 msym = lookup_minimal_symbol_by_pc (pc); 3849 if (msym.minsym != NULL 3850 && msym.minsym->linkage_name () != NULL 3851 && startswith (msym.minsym->linkage_name (), ".pic.")) 3852 return 1; 3853 3854 return 0; 3855 } 3856 3857 static const struct frame_unwind mips_stub_frame_unwind = 3858 { 3859 "mips stub", 3860 NORMAL_FRAME, 3861 default_frame_unwind_stop_reason, 3862 mips_stub_frame_this_id, 3863 mips_stub_frame_prev_register, 3864 NULL, 3865 mips_stub_frame_sniffer 3866 }; 3867 3868 static CORE_ADDR 3869 mips_stub_frame_base_address (frame_info_ptr this_frame, 3870 void **this_cache) 3871 { 3872 struct trad_frame_cache *this_trad_cache 3873 = mips_stub_frame_cache (this_frame, this_cache); 3874 return trad_frame_get_this_base (this_trad_cache); 3875 } 3876 3877 static const struct frame_base mips_stub_frame_base = 3878 { 3879 &mips_stub_frame_unwind, 3880 mips_stub_frame_base_address, 3881 mips_stub_frame_base_address, 3882 mips_stub_frame_base_address 3883 }; 3884 3885 static const struct frame_base * 3886 mips_stub_frame_base_sniffer (frame_info_ptr this_frame) 3887 { 3888 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) 3889 return &mips_stub_frame_base; 3890 else 3891 return NULL; 3892 } 3893 3894 /* mips_addr_bits_remove - remove useless address bits */ 3895 3896 static CORE_ADDR 3897 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) 3898 { 3899 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 3900 3901 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) 3902 /* This hack is a work-around for existing boards using PMON, the 3903 simulator, and any other 64-bit targets that doesn't have true 3904 64-bit addressing. On these targets, the upper 32 bits of 3905 addresses are ignored by the hardware. Thus, the PC or SP are 3906 likely to have been sign extended to all 1s by instruction 3907 sequences that load 32-bit addresses. For example, a typical 3908 piece of code that loads an address is this: 3909 3910 lui $r2, <upper 16 bits> 3911 ori $r2, <lower 16 bits> 3912 3913 But the lui sign-extends the value such that the upper 32 bits 3914 may be all 1s. The workaround is simply to mask off these 3915 bits. In the future, gcc may be changed to support true 64-bit 3916 addressing, and this masking will have to be disabled. */ 3917 return addr &= 0xffffffffUL; 3918 else 3919 return addr; 3920 } 3921 3922 3923 /* Checks for an atomic sequence of instructions beginning with a LL/LLD 3924 instruction and ending with a SC/SCD instruction. If such a sequence 3925 is found, attempt to step through it. A breakpoint is placed at the end of 3926 the sequence. */ 3927 3928 /* Instructions used during single-stepping of atomic sequences, standard 3929 ISA version. */ 3930 #define LL_OPCODE 0x30 3931 #define LLD_OPCODE 0x34 3932 #define SC_OPCODE 0x38 3933 #define SCD_OPCODE 0x3c 3934 3935 static std::vector<CORE_ADDR> 3936 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) 3937 { 3938 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; 3939 CORE_ADDR loc = pc; 3940 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ 3941 ULONGEST insn; 3942 int insn_count; 3943 int index; 3944 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 3945 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 3946 3947 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3948 /* Assume all atomic sequences start with a ll/lld instruction. */ 3949 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) 3950 return {}; 3951 3952 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 3953 instructions. */ 3954 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 3955 { 3956 int is_branch = 0; 3957 loc += MIPS_INSN32_SIZE; 3958 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3959 3960 /* Assume that there is at most one branch in the atomic 3961 sequence. If a branch is found, put a breakpoint in its 3962 destination address. */ 3963 switch (itype_op (insn)) 3964 { 3965 case 0: /* SPECIAL */ 3966 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ 3967 return {}; /* fallback to the standard single-step code. */ 3968 break; 3969 case 1: /* REGIMM */ 3970 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ 3971 || ((itype_rt (insn) & 0x1e) == 0 3972 && itype_rs (insn) == 0)); /* BPOSGE* */ 3973 break; 3974 case 2: /* J */ 3975 case 3: /* JAL */ 3976 return {}; /* fallback to the standard single-step code. */ 3977 case 4: /* BEQ */ 3978 case 5: /* BNE */ 3979 case 6: /* BLEZ */ 3980 case 7: /* BGTZ */ 3981 case 20: /* BEQL */ 3982 case 21: /* BNEL */ 3983 case 22: /* BLEZL */ 3984 case 23: /* BGTTL */ 3985 is_branch = 1; 3986 break; 3987 case 17: /* COP1 */ 3988 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) 3989 && (itype_rt (insn) & 0x2) == 0); 3990 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ 3991 break; 3992 /* Fall through. */ 3993 case 18: /* COP2 */ 3994 case 19: /* COP3 */ 3995 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ 3996 break; 3997 } 3998 if (is_branch) 3999 { 4000 branch_bp = loc + mips32_relative_offset (insn) + 4; 4001 if (last_breakpoint >= 1) 4002 return {}; /* More than one branch found, fallback to the 4003 standard single-step code. */ 4004 breaks[1] = branch_bp; 4005 last_breakpoint++; 4006 } 4007 4008 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) 4009 break; 4010 } 4011 4012 /* Assume that the atomic sequence ends with a sc/scd instruction. */ 4013 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) 4014 return {}; 4015 4016 loc += MIPS_INSN32_SIZE; 4017 4018 /* Insert a breakpoint right after the end of the atomic sequence. */ 4019 breaks[0] = loc; 4020 4021 /* Check for duplicated breakpoints. Check also for a breakpoint 4022 placed (branch instruction's destination) in the atomic sequence. */ 4023 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 4024 last_breakpoint = 0; 4025 4026 std::vector<CORE_ADDR> next_pcs; 4027 4028 /* Effectively inserts the breakpoints. */ 4029 for (index = 0; index <= last_breakpoint; index++) 4030 next_pcs.push_back (breaks[index]); 4031 4032 return next_pcs; 4033 } 4034 4035 static std::vector<CORE_ADDR> 4036 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, 4037 CORE_ADDR pc) 4038 { 4039 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 4040 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 4041 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; 4042 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's 4043 destination. */ 4044 CORE_ADDR loc = pc; 4045 int sc_found = 0; 4046 ULONGEST insn; 4047 int insn_count; 4048 int index; 4049 4050 /* Assume all atomic sequences start with a ll/lld instruction. */ 4051 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4052 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ 4053 return {}; 4054 loc += MIPS_INSN16_SIZE; 4055 insn <<= 16; 4056 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4057 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ 4058 return {}; 4059 loc += MIPS_INSN16_SIZE; 4060 4061 /* Assume all atomic sequences end with an sc/scd instruction. Assume 4062 that no atomic sequence is longer than "atomic_sequence_length" 4063 instructions. */ 4064 for (insn_count = 0; 4065 !sc_found && insn_count < atomic_sequence_length; 4066 ++insn_count) 4067 { 4068 int is_branch = 0; 4069 4070 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4071 loc += MIPS_INSN16_SIZE; 4072 4073 /* Assume that there is at most one conditional branch in the 4074 atomic sequence. If a branch is found, put a breakpoint in 4075 its destination address. */ 4076 switch (mips_insn_size (ISA_MICROMIPS, insn)) 4077 { 4078 /* 32-bit instructions. */ 4079 case 2 * MIPS_INSN16_SIZE: 4080 switch (micromips_op (insn)) 4081 { 4082 case 0x10: /* POOL32I: bits 010000 */ 4083 if ((b5s5_op (insn) & 0x18) != 0x0 4084 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 4085 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ 4086 && (b5s5_op (insn) & 0x1d) != 0x11 4087 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 4088 && ((b5s5_op (insn) & 0x1e) != 0x14 4089 || (insn & 0x3) != 0x0) 4090 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 4091 && (b5s5_op (insn) & 0x1e) != 0x1a 4092 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 4093 && ((b5s5_op (insn) & 0x1e) != 0x1c 4094 || (insn & 0x3) != 0x0) 4095 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 4096 && ((b5s5_op (insn) & 0x1c) != 0x1c 4097 || (insn & 0x3) != 0x1)) 4098 /* BC1ANY*: bits 010000 111xx xxx01 */ 4099 break; 4100 /* Fall through. */ 4101 4102 case 0x25: /* BEQ: bits 100101 */ 4103 case 0x2d: /* BNE: bits 101101 */ 4104 insn <<= 16; 4105 insn |= mips_fetch_instruction (gdbarch, 4106 ISA_MICROMIPS, loc, NULL); 4107 branch_bp = (loc + MIPS_INSN16_SIZE 4108 + micromips_relative_offset16 (insn)); 4109 is_branch = 1; 4110 break; 4111 4112 case 0x00: /* POOL32A: bits 000000 */ 4113 insn <<= 16; 4114 insn |= mips_fetch_instruction (gdbarch, 4115 ISA_MICROMIPS, loc, NULL); 4116 if (b0s6_op (insn) != 0x3c 4117 /* POOL32Axf: bits 000000 ... 111100 */ 4118 || (b6s10_ext (insn) & 0x2bf) != 0x3c) 4119 /* JALR, JALR.HB: 000000 000x111100 111100 */ 4120 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 4121 break; 4122 /* Fall through. */ 4123 4124 case 0x1d: /* JALS: bits 011101 */ 4125 case 0x35: /* J: bits 110101 */ 4126 case 0x3d: /* JAL: bits 111101 */ 4127 case 0x3c: /* JALX: bits 111100 */ 4128 return {}; /* Fall back to the standard single-step code. */ 4129 4130 case 0x18: /* POOL32C: bits 011000 */ 4131 if ((b12s4_op (insn) & 0xb) == 0xb) 4132 /* SC, SCD: bits 011000 1x11 */ 4133 sc_found = 1; 4134 break; 4135 } 4136 loc += MIPS_INSN16_SIZE; 4137 break; 4138 4139 /* 16-bit instructions. */ 4140 case MIPS_INSN16_SIZE: 4141 switch (micromips_op (insn)) 4142 { 4143 case 0x23: /* BEQZ16: bits 100011 */ 4144 case 0x2b: /* BNEZ16: bits 101011 */ 4145 branch_bp = loc + micromips_relative_offset7 (insn); 4146 is_branch = 1; 4147 break; 4148 4149 case 0x11: /* POOL16C: bits 010001 */ 4150 if ((b5s5_op (insn) & 0x1c) != 0xc 4151 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 4152 && b5s5_op (insn) != 0x18) 4153 /* JRADDIUSP: bits 010001 11000 */ 4154 break; 4155 return {}; /* Fall back to the standard single-step code. */ 4156 4157 case 0x33: /* B16: bits 110011 */ 4158 return {}; /* Fall back to the standard single-step code. */ 4159 } 4160 break; 4161 } 4162 if (is_branch) 4163 { 4164 if (last_breakpoint >= 1) 4165 return {}; /* More than one branch found, fallback to the 4166 standard single-step code. */ 4167 breaks[1] = branch_bp; 4168 last_breakpoint++; 4169 } 4170 } 4171 if (!sc_found) 4172 return {}; 4173 4174 /* Insert a breakpoint right after the end of the atomic sequence. */ 4175 breaks[0] = loc; 4176 4177 /* Check for duplicated breakpoints. Check also for a breakpoint 4178 placed (branch instruction's destination) in the atomic sequence */ 4179 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 4180 last_breakpoint = 0; 4181 4182 std::vector<CORE_ADDR> next_pcs; 4183 4184 /* Effectively inserts the breakpoints. */ 4185 for (index = 0; index <= last_breakpoint; index++) 4186 next_pcs.push_back (breaks[index]); 4187 4188 return next_pcs; 4189 } 4190 4191 static std::vector<CORE_ADDR> 4192 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) 4193 { 4194 if (mips_pc_is_mips (pc)) 4195 return mips_deal_with_atomic_sequence (gdbarch, pc); 4196 else if (mips_pc_is_micromips (gdbarch, pc)) 4197 return micromips_deal_with_atomic_sequence (gdbarch, pc); 4198 else 4199 return {}; 4200 } 4201 4202 /* mips_software_single_step() is called just before we want to resume 4203 the inferior, if we want to single-step it but there is no hardware 4204 or kernel single-step support (MIPS on GNU/Linux for example). We find 4205 the target of the coming instruction and breakpoint it. */ 4206 4207 std::vector<CORE_ADDR> 4208 mips_software_single_step (struct regcache *regcache) 4209 { 4210 struct gdbarch *gdbarch = regcache->arch (); 4211 CORE_ADDR pc, next_pc; 4212 4213 pc = regcache_read_pc (regcache); 4214 std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); 4215 4216 if (!next_pcs.empty ()) 4217 return next_pcs; 4218 4219 next_pc = mips_next_pc (regcache, pc); 4220 4221 return {next_pc}; 4222 } 4223 4224 /* Test whether the PC points to the return instruction at the 4225 end of a function. */ 4226 4227 static int 4228 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) 4229 { 4230 ULONGEST insn; 4231 ULONGEST hint; 4232 4233 /* This used to check for MIPS16, but this piece of code is never 4234 called for MIPS16 functions. And likewise microMIPS ones. */ 4235 gdb_assert (mips_pc_is_mips (pc)); 4236 4237 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 4238 hint = 0x7c0; 4239 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ 4240 } 4241 4242 4243 /* This fencepost looks highly suspicious to me. Removing it also 4244 seems suspicious as it could affect remote debugging across serial 4245 lines. */ 4246 4247 static CORE_ADDR 4248 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) 4249 { 4250 CORE_ADDR start_pc; 4251 CORE_ADDR fence; 4252 int instlen; 4253 int seen_adjsp = 0; 4254 struct inferior *inf; 4255 4256 pc = gdbarch_addr_bits_remove (gdbarch, pc); 4257 start_pc = pc; 4258 fence = start_pc - heuristic_fence_post; 4259 if (start_pc == 0) 4260 return 0; 4261 4262 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) 4263 fence = VM_MIN_ADDRESS; 4264 4265 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; 4266 4267 inf = current_inferior (); 4268 4269 /* Search back for previous return. */ 4270 for (start_pc -= instlen;; start_pc -= instlen) 4271 if (start_pc < fence) 4272 { 4273 /* It's not clear to me why we reach this point when 4274 stop_soon, but with this test, at least we 4275 don't print out warnings for every child forked (eg, on 4276 decstation). 22apr93 rich@cygnus.com. */ 4277 if (inf->control.stop_soon == NO_STOP_QUIETLY) 4278 { 4279 static int blurb_printed = 0; 4280 4281 warning (_("GDB can't find the start of the function at %s."), 4282 paddress (gdbarch, pc)); 4283 4284 if (!blurb_printed) 4285 { 4286 /* This actually happens frequently in embedded 4287 development, when you first connect to a board 4288 and your stack pointer and pc are nowhere in 4289 particular. This message needs to give people 4290 in that situation enough information to 4291 determine that it's no big deal. */ 4292 gdb_printf ("\n\ 4293 GDB is unable to find the start of the function at %s\n\ 4294 and thus can't determine the size of that function's stack frame.\n\ 4295 This means that GDB may be unable to access that stack frame, or\n\ 4296 the frames below it.\n\ 4297 This problem is most likely caused by an invalid program counter or\n\ 4298 stack pointer.\n\ 4299 However, if you think GDB should simply search farther back\n\ 4300 from %s for code which looks like the beginning of a\n\ 4301 function, you can increase the range of the search using the `set\n\ 4302 heuristic-fence-post' command.\n", 4303 paddress (gdbarch, pc), paddress (gdbarch, pc)); 4304 blurb_printed = 1; 4305 } 4306 } 4307 4308 return 0; 4309 } 4310 else if (mips_pc_is_mips16 (gdbarch, start_pc)) 4311 { 4312 unsigned short inst; 4313 4314 /* On MIPS16, any one of the following is likely to be the 4315 start of a function: 4316 extend save 4317 save 4318 entry 4319 addiu sp,-n 4320 daddiu sp,-n 4321 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ 4322 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); 4323 if ((inst & 0xff80) == 0x6480) /* save */ 4324 { 4325 if (start_pc - instlen >= fence) 4326 { 4327 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, 4328 start_pc - instlen, NULL); 4329 if ((inst & 0xf800) == 0xf000) /* extend */ 4330 start_pc -= instlen; 4331 } 4332 break; 4333 } 4334 else if (((inst & 0xf81f) == 0xe809 4335 && (inst & 0x700) != 0x700) /* entry */ 4336 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ 4337 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ 4338 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ 4339 break; 4340 else if ((inst & 0xff00) == 0x6300 /* addiu sp */ 4341 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 4342 seen_adjsp = 1; 4343 else 4344 seen_adjsp = 0; 4345 } 4346 else if (mips_pc_is_micromips (gdbarch, start_pc)) 4347 { 4348 ULONGEST insn; 4349 int stop = 0; 4350 long offset; 4351 int dreg; 4352 int sreg; 4353 4354 /* On microMIPS, any one of the following is likely to be the 4355 start of a function: 4356 ADDIUSP -imm 4357 (D)ADDIU $sp, -imm 4358 LUI $gp, imm */ 4359 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 4360 switch (micromips_op (insn)) 4361 { 4362 case 0xc: /* ADDIU: bits 001100 */ 4363 case 0x17: /* DADDIU: bits 010111 */ 4364 sreg = b0s5_reg (insn); 4365 dreg = b5s5_reg (insn); 4366 insn <<= 16; 4367 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, 4368 pc + MIPS_INSN16_SIZE, NULL); 4369 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 4370 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 4371 /* (D)ADDIU $sp, imm */ 4372 && offset < 0) 4373 stop = 1; 4374 break; 4375 4376 case 0x10: /* POOL32I: bits 010000 */ 4377 if (b5s5_op (insn) == 0xd 4378 /* LUI: bits 010000 001101 */ 4379 && b0s5_reg (insn >> 16) == 28) 4380 /* LUI $gp, imm */ 4381 stop = 1; 4382 break; 4383 4384 case 0x13: /* POOL16D: bits 010011 */ 4385 if ((insn & 0x1) == 0x1) 4386 /* ADDIUSP: bits 010011 1 */ 4387 { 4388 offset = micromips_decode_imm9 (b1s9_imm (insn)); 4389 if (offset < 0) 4390 /* ADDIUSP -imm */ 4391 stop = 1; 4392 } 4393 else 4394 /* ADDIUS5: bits 010011 0 */ 4395 { 4396 dreg = b5s5_reg (insn); 4397 offset = (b1s4_imm (insn) ^ 8) - 8; 4398 if (dreg == MIPS_SP_REGNUM && offset < 0) 4399 /* ADDIUS5 $sp, -imm */ 4400 stop = 1; 4401 } 4402 break; 4403 } 4404 if (stop) 4405 break; 4406 } 4407 else if (mips_about_to_return (gdbarch, start_pc)) 4408 { 4409 /* Skip return and its delay slot. */ 4410 start_pc += 2 * MIPS_INSN32_SIZE; 4411 break; 4412 } 4413 4414 return start_pc; 4415 } 4416 4417 struct mips_objfile_private 4418 { 4419 bfd_size_type size; 4420 char *contents; 4421 }; 4422 4423 /* According to the current ABI, should the type be passed in a 4424 floating-point register (assuming that there is space)? When there 4425 is no FPU, FP are not even considered as possible candidates for 4426 FP registers and, consequently this returns false - forces FP 4427 arguments into integer registers. */ 4428 4429 static int 4430 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, 4431 struct type *arg_type) 4432 { 4433 return ((typecode == TYPE_CODE_FLT 4434 || (mips_eabi (gdbarch) 4435 && (typecode == TYPE_CODE_STRUCT 4436 || typecode == TYPE_CODE_UNION) 4437 && arg_type->num_fields () == 1 4438 && check_typedef (arg_type->field (0).type ())->code () 4439 == TYPE_CODE_FLT)) 4440 && mips_get_fpu_type (gdbarch) != MIPS_FPU_NONE); 4441 } 4442 4443 /* On o32, argument passing in GPRs depends on the alignment of the type being 4444 passed. Return 1 if this type must be aligned to a doubleword boundary. */ 4445 4446 static int 4447 mips_type_needs_double_align (struct type *type) 4448 { 4449 enum type_code typecode = type->code (); 4450 4451 if (typecode == TYPE_CODE_FLT && type->length () == 8) 4452 return 1; 4453 else if (typecode == TYPE_CODE_STRUCT) 4454 { 4455 if (type->num_fields () < 1) 4456 return 0; 4457 return mips_type_needs_double_align (type->field (0).type ()); 4458 } 4459 else if (typecode == TYPE_CODE_UNION) 4460 { 4461 int i, n; 4462 4463 n = type->num_fields (); 4464 for (i = 0; i < n; i++) 4465 if (mips_type_needs_double_align (type->field (i).type ())) 4466 return 1; 4467 return 0; 4468 } 4469 return 0; 4470 } 4471 4472 /* Adjust the address downward (direction of stack growth) so that it 4473 is correctly aligned for a new stack frame. */ 4474 static CORE_ADDR 4475 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 4476 { 4477 return align_down (addr, 16); 4478 } 4479 4480 /* Implement the "push_dummy_code" gdbarch method. */ 4481 4482 static CORE_ADDR 4483 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 4484 CORE_ADDR funaddr, struct value **args, 4485 int nargs, struct type *value_type, 4486 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 4487 struct regcache *regcache) 4488 { 4489 static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; 4490 CORE_ADDR nop_addr; 4491 CORE_ADDR bp_slot; 4492 4493 /* Reserve enough room on the stack for our breakpoint instruction. */ 4494 bp_slot = sp - sizeof (nop_insn); 4495 4496 /* Return to microMIPS mode if calling microMIPS code to avoid 4497 triggering an address error exception on processors that only 4498 support microMIPS execution. */ 4499 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) 4500 ? make_compact_addr (bp_slot) : bp_slot); 4501 4502 /* The breakpoint layer automatically adjusts the address of 4503 breakpoints inserted in a branch delay slot. With enough 4504 bad luck, the 4 bytes located just before our breakpoint 4505 instruction could look like a branch instruction, and thus 4506 trigger the adjustement, and break the function call entirely. 4507 So, we reserve those 4 bytes and write a nop instruction 4508 to prevent that from happening. */ 4509 nop_addr = bp_slot - sizeof (nop_insn); 4510 write_memory (nop_addr, nop_insn, sizeof (nop_insn)); 4511 sp = mips_frame_align (gdbarch, nop_addr); 4512 4513 /* Inferior resumes at the function entry point. */ 4514 *real_pc = funaddr; 4515 4516 return sp; 4517 } 4518 4519 static CORE_ADDR 4520 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4521 struct regcache *regcache, CORE_ADDR bp_addr, 4522 int nargs, struct value **args, CORE_ADDR sp, 4523 function_call_return_method return_method, 4524 CORE_ADDR struct_addr) 4525 { 4526 int argreg; 4527 int float_argreg; 4528 int argnum; 4529 int arg_space = 0; 4530 int stack_offset = 0; 4531 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4532 CORE_ADDR func_addr = find_function_addr (function, NULL); 4533 int abi_regsize = mips_abi_regsize (gdbarch); 4534 4535 /* For shared libraries, "t9" needs to point at the function 4536 address. */ 4537 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4538 4539 /* Set the return address register to point to the entry point of 4540 the program, where a breakpoint lies in wait. */ 4541 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4542 4543 /* First ensure that the stack and structure return address (if any) 4544 are properly aligned. The stack has to be at least 64-bit 4545 aligned even on 32-bit machines, because doubles must be 64-bit 4546 aligned. For n32 and n64, stack frames need to be 128-bit 4547 aligned, so we round to this widest known alignment. */ 4548 4549 sp = align_down (sp, 16); 4550 struct_addr = align_down (struct_addr, 16); 4551 4552 /* Now make space on the stack for the args. We allocate more 4553 than necessary for EABI, because the first few arguments are 4554 passed in registers, but that's OK. */ 4555 for (argnum = 0; argnum < nargs; argnum++) 4556 arg_space += align_up (value_type (args[argnum])->length (), 4557 abi_regsize); 4558 sp -= align_up (arg_space, 16); 4559 4560 if (mips_debug) 4561 gdb_printf (gdb_stdlog, 4562 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", 4563 paddress (gdbarch, sp), 4564 (long) align_up (arg_space, 16)); 4565 4566 /* Initialize the integer and float register pointers. */ 4567 argreg = MIPS_A0_REGNUM; 4568 float_argreg = mips_fpa0_regnum (gdbarch); 4569 4570 /* The struct_return pointer occupies the first parameter-passing reg. */ 4571 if (return_method == return_method_struct) 4572 { 4573 if (mips_debug) 4574 gdb_printf (gdb_stdlog, 4575 "mips_eabi_push_dummy_call: " 4576 "struct_return reg=%d %s\n", 4577 argreg, paddress (gdbarch, struct_addr)); 4578 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4579 } 4580 4581 /* Now load as many as possible of the first arguments into 4582 registers, and push the rest onto the stack. Loop thru args 4583 from first to last. */ 4584 for (argnum = 0; argnum < nargs; argnum++) 4585 { 4586 const gdb_byte *val; 4587 /* This holds the address of structures that are passed by 4588 reference. */ 4589 gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; 4590 struct value *arg = args[argnum]; 4591 struct type *arg_type = check_typedef (value_type (arg)); 4592 int len = arg_type->length (); 4593 enum type_code typecode = arg_type->code (); 4594 4595 if (mips_debug) 4596 gdb_printf (gdb_stdlog, 4597 "mips_eabi_push_dummy_call: %d len=%d type=%d", 4598 argnum + 1, len, (int) typecode); 4599 4600 /* The EABI passes structures that do not fit in a register by 4601 reference. */ 4602 if (len > abi_regsize 4603 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 4604 { 4605 gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); 4606 store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, 4607 value_address (arg)); 4608 typecode = TYPE_CODE_PTR; 4609 len = abi_regsize; 4610 val = ref_valbuf; 4611 if (mips_debug) 4612 gdb_printf (gdb_stdlog, " push"); 4613 } 4614 else 4615 val = value_contents (arg).data (); 4616 4617 /* 32-bit ABIs always start floating point arguments in an 4618 even-numbered floating point register. Round the FP register 4619 up before the check to see if there are any FP registers 4620 left. Non MIPS_EABI targets also pass the FP in the integer 4621 registers so also round up normal registers. */ 4622 if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) 4623 { 4624 if ((float_argreg & 1)) 4625 float_argreg++; 4626 } 4627 4628 /* Floating point arguments passed in registers have to be 4629 treated specially. On 32-bit architectures, doubles 4630 are passed in register pairs; the even register gets 4631 the low word, and the odd register gets the high word. 4632 On non-EABI processors, the first two floating point arguments are 4633 also copied to general registers, because MIPS16 functions 4634 don't use float registers for arguments. This duplication of 4635 arguments in general registers can't hurt non-MIPS16 functions 4636 because those registers are normally skipped. */ 4637 /* MIPS_EABI squeezes a struct that contains a single floating 4638 point value into an FP register instead of pushing it onto the 4639 stack. */ 4640 if (fp_register_arg_p (gdbarch, typecode, arg_type) 4641 && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) 4642 { 4643 /* EABI32 will pass doubles in consecutive registers, even on 4644 64-bit cores. At one time, we used to check the size of 4645 `float_argreg' to determine whether or not to pass doubles 4646 in consecutive registers, but this is not sufficient for 4647 making the ABI determination. */ 4648 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) 4649 { 4650 int low_offset = gdbarch_byte_order (gdbarch) 4651 == BFD_ENDIAN_BIG ? 4 : 0; 4652 long regval; 4653 4654 /* Write the low word of the double to the even register(s). */ 4655 regval = extract_signed_integer (val + low_offset, 4656 4, byte_order); 4657 if (mips_debug) 4658 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 4659 float_argreg, phex (regval, 4)); 4660 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4661 4662 /* Write the high word of the double to the odd register(s). */ 4663 regval = extract_signed_integer (val + 4 - low_offset, 4664 4, byte_order); 4665 if (mips_debug) 4666 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 4667 float_argreg, phex (regval, 4)); 4668 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4669 } 4670 else 4671 { 4672 /* This is a floating point value that fits entirely 4673 in a single register. */ 4674 /* On 32 bit ABI's the float_argreg is further adjusted 4675 above to ensure that it is even register aligned. */ 4676 LONGEST regval = extract_signed_integer (val, len, byte_order); 4677 if (mips_debug) 4678 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 4679 float_argreg, phex (regval, len)); 4680 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4681 } 4682 } 4683 else 4684 { 4685 /* Copy the argument to general registers or the stack in 4686 register-sized pieces. Large arguments are split between 4687 registers and stack. */ 4688 /* Note: structs whose size is not a multiple of abi_regsize 4689 are treated specially: Irix cc passes 4690 them in registers where gcc sometimes puts them on the 4691 stack. For maximum compatibility, we will put them in 4692 both places. */ 4693 int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); 4694 4695 /* Note: Floating-point values that didn't fit into an FP 4696 register are only written to memory. */ 4697 while (len > 0) 4698 { 4699 /* Remember if the argument was written to the stack. */ 4700 int stack_used_p = 0; 4701 int partial_len = (len < abi_regsize ? len : abi_regsize); 4702 4703 if (mips_debug) 4704 gdb_printf (gdb_stdlog, " -- partial=%d", 4705 partial_len); 4706 4707 /* Write this portion of the argument to the stack. */ 4708 if (argreg > mips_last_arg_regnum (gdbarch) 4709 || odd_sized_struct 4710 || fp_register_arg_p (gdbarch, typecode, arg_type)) 4711 { 4712 /* Should shorter than int integer values be 4713 promoted to int before being stored? */ 4714 int longword_offset = 0; 4715 CORE_ADDR addr; 4716 stack_used_p = 1; 4717 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 4718 { 4719 if (abi_regsize == 8 4720 && (typecode == TYPE_CODE_INT 4721 || typecode == TYPE_CODE_PTR 4722 || typecode == TYPE_CODE_FLT) && len <= 4) 4723 longword_offset = abi_regsize - len; 4724 else if ((typecode == TYPE_CODE_STRUCT 4725 || typecode == TYPE_CODE_UNION) 4726 && arg_type->length () < abi_regsize) 4727 longword_offset = abi_regsize - len; 4728 } 4729 4730 if (mips_debug) 4731 { 4732 gdb_printf (gdb_stdlog, " - stack_offset=%s", 4733 paddress (gdbarch, stack_offset)); 4734 gdb_printf (gdb_stdlog, " longword_offset=%s", 4735 paddress (gdbarch, longword_offset)); 4736 } 4737 4738 addr = sp + stack_offset + longword_offset; 4739 4740 if (mips_debug) 4741 { 4742 int i; 4743 gdb_printf (gdb_stdlog, " @%s ", 4744 paddress (gdbarch, addr)); 4745 for (i = 0; i < partial_len; i++) 4746 { 4747 gdb_printf (gdb_stdlog, "%02x", 4748 val[i] & 0xff); 4749 } 4750 } 4751 write_memory (addr, val, partial_len); 4752 } 4753 4754 /* Note!!! This is NOT an else clause. Odd sized 4755 structs may go thru BOTH paths. Floating point 4756 arguments will not. */ 4757 /* Write this portion of the argument to a general 4758 purpose register. */ 4759 if (argreg <= mips_last_arg_regnum (gdbarch) 4760 && !fp_register_arg_p (gdbarch, typecode, arg_type)) 4761 { 4762 LONGEST regval = 4763 extract_signed_integer (val, partial_len, byte_order); 4764 4765 if (mips_debug) 4766 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 4767 argreg, 4768 phex (regval, abi_regsize)); 4769 regcache_cooked_write_signed (regcache, argreg, regval); 4770 argreg++; 4771 } 4772 4773 len -= partial_len; 4774 val += partial_len; 4775 4776 /* Compute the offset into the stack at which we will 4777 copy the next parameter. 4778 4779 In the new EABI (and the NABI32), the stack_offset 4780 only needs to be adjusted when it has been used. */ 4781 4782 if (stack_used_p) 4783 stack_offset += align_up (partial_len, abi_regsize); 4784 } 4785 } 4786 if (mips_debug) 4787 gdb_printf (gdb_stdlog, "\n"); 4788 } 4789 4790 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 4791 4792 /* Return adjusted stack pointer. */ 4793 return sp; 4794 } 4795 4796 /* Determine the return value convention being used. */ 4797 4798 static enum return_value_convention 4799 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, 4800 struct type *type, struct regcache *regcache, 4801 gdb_byte *readbuf, const gdb_byte *writebuf) 4802 { 4803 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 4804 int fp_return_type = 0; 4805 int offset, regnum, xfer; 4806 4807 if (type->length () > 2 * mips_abi_regsize (gdbarch)) 4808 return RETURN_VALUE_STRUCT_CONVENTION; 4809 4810 /* Floating point type? */ 4811 if (tdep->mips_fpu_type != MIPS_FPU_NONE) 4812 { 4813 if (type->code () == TYPE_CODE_FLT) 4814 fp_return_type = 1; 4815 /* Structs with a single field of float type 4816 are returned in a floating point register. */ 4817 if ((type->code () == TYPE_CODE_STRUCT 4818 || type->code () == TYPE_CODE_UNION) 4819 && type->num_fields () == 1) 4820 { 4821 struct type *fieldtype = type->field (0).type (); 4822 4823 if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT) 4824 fp_return_type = 1; 4825 } 4826 } 4827 4828 if (fp_return_type) 4829 { 4830 /* A floating-point value belongs in the least significant part 4831 of FP0/FP1. */ 4832 if (mips_debug) 4833 gdb_printf (gdb_stderr, "Return float in $fp0\n"); 4834 regnum = mips_regnum (gdbarch)->fp0; 4835 } 4836 else 4837 { 4838 /* An integer value goes in V0/V1. */ 4839 if (mips_debug) 4840 gdb_printf (gdb_stderr, "Return scalar in $v0\n"); 4841 regnum = MIPS_V0_REGNUM; 4842 } 4843 for (offset = 0; 4844 offset < type->length (); 4845 offset += mips_abi_regsize (gdbarch), regnum++) 4846 { 4847 xfer = mips_abi_regsize (gdbarch); 4848 if (offset + xfer > type->length ()) 4849 xfer = type->length () - offset; 4850 mips_xfer_register (gdbarch, regcache, 4851 gdbarch_num_regs (gdbarch) + regnum, xfer, 4852 gdbarch_byte_order (gdbarch), readbuf, writebuf, 4853 offset); 4854 } 4855 4856 return RETURN_VALUE_REGISTER_CONVENTION; 4857 } 4858 4859 4860 /* N32/N64 ABI stuff. */ 4861 4862 /* Search for a naturally aligned double at OFFSET inside a struct 4863 ARG_TYPE. The N32 / N64 ABIs pass these in floating point 4864 registers. */ 4865 4866 static int 4867 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, 4868 int offset) 4869 { 4870 int i; 4871 4872 if (arg_type->code () != TYPE_CODE_STRUCT) 4873 return 0; 4874 4875 if (mips_get_fpu_type (gdbarch) != MIPS_FPU_DOUBLE) 4876 return 0; 4877 4878 if (arg_type->length () < offset + MIPS64_REGSIZE) 4879 return 0; 4880 4881 for (i = 0; i < arg_type->num_fields (); i++) 4882 { 4883 int pos; 4884 struct type *field_type; 4885 4886 /* We're only looking at normal fields. */ 4887 if (field_is_static (&arg_type->field (i)) 4888 || (arg_type->field (i).loc_bitpos () % 8) != 0) 4889 continue; 4890 4891 /* If we have gone past the offset, there is no double to pass. */ 4892 pos = arg_type->field (i).loc_bitpos () / 8; 4893 if (pos > offset) 4894 return 0; 4895 4896 field_type = check_typedef (arg_type->field (i).type ()); 4897 4898 /* If this field is entirely before the requested offset, go 4899 on to the next one. */ 4900 if (pos + field_type->length () <= offset) 4901 continue; 4902 4903 /* If this is our special aligned double, we can stop. */ 4904 if (field_type->code () == TYPE_CODE_FLT 4905 && field_type->length () == MIPS64_REGSIZE) 4906 return 1; 4907 4908 /* This field starts at or before the requested offset, and 4909 overlaps it. If it is a structure, recurse inwards. */ 4910 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); 4911 } 4912 4913 return 0; 4914 } 4915 4916 static CORE_ADDR 4917 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4918 struct regcache *regcache, CORE_ADDR bp_addr, 4919 int nargs, struct value **args, CORE_ADDR sp, 4920 function_call_return_method return_method, 4921 CORE_ADDR struct_addr) 4922 { 4923 int argreg; 4924 int float_argreg; 4925 int argnum; 4926 int arg_space = 0; 4927 int stack_offset = 0; 4928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4929 CORE_ADDR func_addr = find_function_addr (function, NULL); 4930 4931 /* For shared libraries, "t9" needs to point at the function 4932 address. */ 4933 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4934 4935 /* Set the return address register to point to the entry point of 4936 the program, where a breakpoint lies in wait. */ 4937 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4938 4939 /* First ensure that the stack and structure return address (if any) 4940 are properly aligned. The stack has to be at least 64-bit 4941 aligned even on 32-bit machines, because doubles must be 64-bit 4942 aligned. For n32 and n64, stack frames need to be 128-bit 4943 aligned, so we round to this widest known alignment. */ 4944 4945 sp = align_down (sp, 16); 4946 struct_addr = align_down (struct_addr, 16); 4947 4948 /* Now make space on the stack for the args. */ 4949 for (argnum = 0; argnum < nargs; argnum++) 4950 arg_space += align_up (value_type (args[argnum])->length (), 4951 MIPS64_REGSIZE); 4952 sp -= align_up (arg_space, 16); 4953 4954 if (mips_debug) 4955 gdb_printf (gdb_stdlog, 4956 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", 4957 paddress (gdbarch, sp), 4958 (long) align_up (arg_space, 16)); 4959 4960 /* Initialize the integer and float register pointers. */ 4961 argreg = MIPS_A0_REGNUM; 4962 float_argreg = mips_fpa0_regnum (gdbarch); 4963 4964 /* The struct_return pointer occupies the first parameter-passing reg. */ 4965 if (return_method == return_method_struct) 4966 { 4967 if (mips_debug) 4968 gdb_printf (gdb_stdlog, 4969 "mips_n32n64_push_dummy_call: " 4970 "struct_return reg=%d %s\n", 4971 argreg, paddress (gdbarch, struct_addr)); 4972 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4973 } 4974 4975 /* Now load as many as possible of the first arguments into 4976 registers, and push the rest onto the stack. Loop thru args 4977 from first to last. */ 4978 for (argnum = 0; argnum < nargs; argnum++) 4979 { 4980 const gdb_byte *val; 4981 struct value *arg = args[argnum]; 4982 struct type *arg_type = check_typedef (value_type (arg)); 4983 int len = arg_type->length (); 4984 enum type_code typecode = arg_type->code (); 4985 4986 if (mips_debug) 4987 gdb_printf (gdb_stdlog, 4988 "mips_n32n64_push_dummy_call: %d len=%d type=%d", 4989 argnum + 1, len, (int) typecode); 4990 4991 val = value_contents (arg).data (); 4992 4993 /* A 128-bit long double value requires an even-odd pair of 4994 floating-point registers. */ 4995 if (len == 16 4996 && fp_register_arg_p (gdbarch, typecode, arg_type) 4997 && (float_argreg & 1)) 4998 { 4999 float_argreg++; 5000 argreg++; 5001 } 5002 5003 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5004 && argreg <= mips_last_arg_regnum (gdbarch)) 5005 { 5006 /* This is a floating point value that fits entirely 5007 in a single register or a pair of registers. */ 5008 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 5009 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); 5010 if (mips_debug) 5011 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5012 float_argreg, phex (regval, reglen)); 5013 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 5014 5015 if (mips_debug) 5016 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5017 argreg, phex (regval, reglen)); 5018 regcache_cooked_write_unsigned (regcache, argreg, regval); 5019 float_argreg++; 5020 argreg++; 5021 if (len == 16) 5022 { 5023 regval = extract_unsigned_integer (val + reglen, 5024 reglen, byte_order); 5025 if (mips_debug) 5026 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5027 float_argreg, phex (regval, reglen)); 5028 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 5029 5030 if (mips_debug) 5031 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5032 argreg, phex (regval, reglen)); 5033 regcache_cooked_write_unsigned (regcache, argreg, regval); 5034 float_argreg++; 5035 argreg++; 5036 } 5037 } 5038 else 5039 { 5040 /* Copy the argument to general registers or the stack in 5041 register-sized pieces. Large arguments are split between 5042 registers and stack. */ 5043 /* For N32/N64, structs, unions, or other composite types are 5044 treated as a sequence of doublewords, and are passed in integer 5045 or floating point registers as though they were simple scalar 5046 parameters to the extent that they fit, with any excess on the 5047 stack packed according to the normal memory layout of the 5048 object. 5049 The caller does not reserve space for the register arguments; 5050 the callee is responsible for reserving it if required. */ 5051 /* Note: Floating-point values that didn't fit into an FP 5052 register are only written to memory. */ 5053 while (len > 0) 5054 { 5055 /* Remember if the argument was written to the stack. */ 5056 int stack_used_p = 0; 5057 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 5058 5059 if (mips_debug) 5060 gdb_printf (gdb_stdlog, " -- partial=%d", 5061 partial_len); 5062 5063 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5064 gdb_assert (argreg > mips_last_arg_regnum (gdbarch)); 5065 5066 /* Write this portion of the argument to the stack. */ 5067 if (argreg > mips_last_arg_regnum (gdbarch)) 5068 { 5069 /* Should shorter than int integer values be 5070 promoted to int before being stored? */ 5071 int longword_offset = 0; 5072 CORE_ADDR addr; 5073 stack_used_p = 1; 5074 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 5075 { 5076 if ((typecode == TYPE_CODE_INT 5077 || typecode == TYPE_CODE_PTR) 5078 && len <= 4) 5079 longword_offset = MIPS64_REGSIZE - len; 5080 } 5081 5082 if (mips_debug) 5083 { 5084 gdb_printf (gdb_stdlog, " - stack_offset=%s", 5085 paddress (gdbarch, stack_offset)); 5086 gdb_printf (gdb_stdlog, " longword_offset=%s", 5087 paddress (gdbarch, longword_offset)); 5088 } 5089 5090 addr = sp + stack_offset + longword_offset; 5091 5092 if (mips_debug) 5093 { 5094 int i; 5095 gdb_printf (gdb_stdlog, " @%s ", 5096 paddress (gdbarch, addr)); 5097 for (i = 0; i < partial_len; i++) 5098 { 5099 gdb_printf (gdb_stdlog, "%02x", 5100 val[i] & 0xff); 5101 } 5102 } 5103 write_memory (addr, val, partial_len); 5104 } 5105 5106 /* Note!!! This is NOT an else clause. Odd sized 5107 structs may go thru BOTH paths. */ 5108 /* Write this portion of the argument to a general 5109 purpose register. */ 5110 if (argreg <= mips_last_arg_regnum (gdbarch)) 5111 { 5112 LONGEST regval; 5113 5114 /* Sign extend pointers, 32-bit integers and signed 5115 16-bit and 8-bit integers; everything else is taken 5116 as is. */ 5117 5118 if ((partial_len == 4 5119 && (typecode == TYPE_CODE_PTR 5120 || typecode == TYPE_CODE_INT)) 5121 || (partial_len < 4 5122 && typecode == TYPE_CODE_INT 5123 && !arg_type->is_unsigned ())) 5124 regval = extract_signed_integer (val, partial_len, 5125 byte_order); 5126 else 5127 regval = extract_unsigned_integer (val, partial_len, 5128 byte_order); 5129 5130 /* A non-floating-point argument being passed in a 5131 general register. If a struct or union, and if 5132 the remaining length is smaller than the register 5133 size, we have to adjust the register value on 5134 big endian targets. 5135 5136 It does not seem to be necessary to do the 5137 same for integral types. */ 5138 5139 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5140 && partial_len < MIPS64_REGSIZE 5141 && (typecode == TYPE_CODE_STRUCT 5142 || typecode == TYPE_CODE_UNION)) 5143 regval <<= ((MIPS64_REGSIZE - partial_len) 5144 * TARGET_CHAR_BIT); 5145 5146 if (mips_debug) 5147 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5148 argreg, 5149 phex (regval, MIPS64_REGSIZE)); 5150 regcache_cooked_write_unsigned (regcache, argreg, regval); 5151 5152 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, 5153 arg_type->length () - len)) 5154 { 5155 if (mips_debug) 5156 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5157 float_argreg, 5158 phex (regval, MIPS64_REGSIZE)); 5159 regcache_cooked_write_unsigned (regcache, float_argreg, 5160 regval); 5161 } 5162 5163 float_argreg++; 5164 argreg++; 5165 } 5166 5167 len -= partial_len; 5168 val += partial_len; 5169 5170 /* Compute the offset into the stack at which we will 5171 copy the next parameter. 5172 5173 In N32 (N64?), the stack_offset only needs to be 5174 adjusted when it has been used. */ 5175 5176 if (stack_used_p) 5177 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 5178 } 5179 } 5180 if (mips_debug) 5181 gdb_printf (gdb_stdlog, "\n"); 5182 } 5183 5184 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5185 5186 /* Return adjusted stack pointer. */ 5187 return sp; 5188 } 5189 5190 static enum return_value_convention 5191 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, 5192 struct type *type, struct regcache *regcache, 5193 gdb_byte *readbuf, const gdb_byte *writebuf) 5194 { 5195 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 5196 5197 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 5198 5199 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 5200 if needed), as appropriate for the type. Composite results (struct, 5201 union, or array) are returned in $2/$f0 and $3/$f2 according to the 5202 following rules: 5203 5204 * A struct with only one or two floating point fields is returned in $f0 5205 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX 5206 case. 5207 5208 * Any other composite results of at most 128 bits are returned in 5209 $2 (first 64 bits) and $3 (remainder, if necessary). 5210 5211 * Larger composite results are handled by converting the function to a 5212 procedure with an implicit first parameter, which is a pointer to an area 5213 reserved by the caller to receive the result. [The o32-bit ABI requires 5214 that all composite results be handled by conversion to implicit first 5215 parameters. The MIPS/SGI Fortran implementation has always made a 5216 specific exception to return COMPLEX results in the floating point 5217 registers.] 5218 5219 From MIPSpro Assembly Language Programmer's Guide, Document Number: 5220 007-2418-004 5221 5222 Software 5223 Register Name(from 5224 Name fgregdef.h) Use and Linkage 5225 ----------------------------------------------------------------- 5226 $f0, $f2 fv0, fv1 Hold results of floating-point type function 5227 ($f0) and complex type function ($f0 has the 5228 real part, $f2 has the imaginary part.) */ 5229 5230 if (type->length () > 2 * MIPS64_REGSIZE) 5231 return RETURN_VALUE_STRUCT_CONVENTION; 5232 else if ((type->code () == TYPE_CODE_COMPLEX 5233 || (type->code () == TYPE_CODE_FLT && type->length () == 16)) 5234 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5235 { 5236 /* A complex value of up to 128 bits in width as well as a 128-bit 5237 floating-point value goes in both $f0 and $f2. A single complex 5238 value is held in the lower halves only of the respective registers. 5239 The two registers are used in the same as memory order, so the 5240 bytes with the lower memory address are in $f0. */ 5241 if (mips_debug) 5242 gdb_printf (gdb_stderr, "Return float in $f0 and $f2\n"); 5243 mips_xfer_register (gdbarch, regcache, 5244 (gdbarch_num_regs (gdbarch) 5245 + mips_regnum (gdbarch)->fp0), 5246 type->length () / 2, gdbarch_byte_order (gdbarch), 5247 readbuf, writebuf, 0); 5248 mips_xfer_register (gdbarch, regcache, 5249 (gdbarch_num_regs (gdbarch) 5250 + mips_regnum (gdbarch)->fp0 + 2), 5251 type->length () / 2, gdbarch_byte_order (gdbarch), 5252 readbuf ? readbuf + type->length () / 2 : readbuf, 5253 (writebuf 5254 ? writebuf + type->length () / 2 : writebuf), 0); 5255 return RETURN_VALUE_REGISTER_CONVENTION; 5256 } 5257 else if (type->code () == TYPE_CODE_FLT 5258 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5259 { 5260 /* A single or double floating-point value that fits in FP0. */ 5261 if (mips_debug) 5262 gdb_printf (gdb_stderr, "Return float in $fp0\n"); 5263 mips_xfer_register (gdbarch, regcache, 5264 (gdbarch_num_regs (gdbarch) 5265 + mips_regnum (gdbarch)->fp0), 5266 type->length (), 5267 gdbarch_byte_order (gdbarch), 5268 readbuf, writebuf, 0); 5269 return RETURN_VALUE_REGISTER_CONVENTION; 5270 } 5271 else if (type->code () == TYPE_CODE_STRUCT 5272 && type->num_fields () <= 2 5273 && type->num_fields () >= 1 5274 && ((type->num_fields () == 1 5275 && (check_typedef (type->field (0).type ())->code () 5276 == TYPE_CODE_FLT)) 5277 || (type->num_fields () == 2 5278 && (check_typedef (type->field (0).type ())->code () 5279 == TYPE_CODE_FLT) 5280 && (check_typedef (type->field (1).type ())->code () 5281 == TYPE_CODE_FLT)))) 5282 { 5283 /* A struct that contains one or two floats. Each value is part 5284 in the least significant part of their floating point 5285 register (or GPR, for soft float). */ 5286 int regnum; 5287 int field; 5288 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE 5289 ? mips_regnum (gdbarch)->fp0 5290 : MIPS_V0_REGNUM); 5291 field < type->num_fields (); field++, regnum += 2) 5292 { 5293 int offset = type->field (field).loc_bitpos () / TARGET_CHAR_BIT; 5294 if (mips_debug) 5295 gdb_printf (gdb_stderr, "Return float struct+%d\n", 5296 offset); 5297 if (type->field (field).type ()->length () == 16) 5298 { 5299 /* A 16-byte long double field goes in two consecutive 5300 registers. */ 5301 mips_xfer_register (gdbarch, regcache, 5302 gdbarch_num_regs (gdbarch) + regnum, 5303 8, 5304 gdbarch_byte_order (gdbarch), 5305 readbuf, writebuf, offset); 5306 mips_xfer_register (gdbarch, regcache, 5307 gdbarch_num_regs (gdbarch) + regnum + 1, 5308 8, 5309 gdbarch_byte_order (gdbarch), 5310 readbuf, writebuf, offset + 8); 5311 } 5312 else 5313 mips_xfer_register (gdbarch, regcache, 5314 gdbarch_num_regs (gdbarch) + regnum, 5315 type->field (field).type ()->length (), 5316 gdbarch_byte_order (gdbarch), 5317 readbuf, writebuf, offset); 5318 } 5319 return RETURN_VALUE_REGISTER_CONVENTION; 5320 } 5321 else if (type->code () == TYPE_CODE_STRUCT 5322 || type->code () == TYPE_CODE_UNION 5323 || type->code () == TYPE_CODE_ARRAY) 5324 { 5325 /* A composite type. Extract the left justified value, 5326 regardless of the byte order. I.e. DO NOT USE 5327 mips_xfer_lower. */ 5328 int offset; 5329 int regnum; 5330 for (offset = 0, regnum = MIPS_V0_REGNUM; 5331 offset < type->length (); 5332 offset += register_size (gdbarch, regnum), regnum++) 5333 { 5334 int xfer = register_size (gdbarch, regnum); 5335 if (offset + xfer > type->length ()) 5336 xfer = type->length () - offset; 5337 if (mips_debug) 5338 gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", 5339 offset, xfer, regnum); 5340 mips_xfer_register (gdbarch, regcache, 5341 gdbarch_num_regs (gdbarch) + regnum, 5342 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, 5343 offset); 5344 } 5345 return RETURN_VALUE_REGISTER_CONVENTION; 5346 } 5347 else 5348 { 5349 /* A scalar extract each part but least-significant-byte 5350 justified. */ 5351 int offset; 5352 int regnum; 5353 for (offset = 0, regnum = MIPS_V0_REGNUM; 5354 offset < type->length (); 5355 offset += register_size (gdbarch, regnum), regnum++) 5356 { 5357 int xfer = register_size (gdbarch, regnum); 5358 if (offset + xfer > type->length ()) 5359 xfer = type->length () - offset; 5360 if (mips_debug) 5361 gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5362 offset, xfer, regnum); 5363 mips_xfer_register (gdbarch, regcache, 5364 gdbarch_num_regs (gdbarch) + regnum, 5365 xfer, gdbarch_byte_order (gdbarch), 5366 readbuf, writebuf, offset); 5367 } 5368 return RETURN_VALUE_REGISTER_CONVENTION; 5369 } 5370 } 5371 5372 /* Which registers to use for passing floating-point values between 5373 function calls, one of floating-point, general and both kinds of 5374 registers. O32 and O64 use different register kinds for standard 5375 MIPS and MIPS16 code; to make the handling of cases where we may 5376 not know what kind of code is being used (e.g. no debug information) 5377 easier we sometimes use both kinds. */ 5378 5379 enum mips_fval_reg 5380 { 5381 mips_fval_fpr, 5382 mips_fval_gpr, 5383 mips_fval_both 5384 }; 5385 5386 /* O32 ABI stuff. */ 5387 5388 static CORE_ADDR 5389 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5390 struct regcache *regcache, CORE_ADDR bp_addr, 5391 int nargs, struct value **args, CORE_ADDR sp, 5392 function_call_return_method return_method, 5393 CORE_ADDR struct_addr) 5394 { 5395 int argreg; 5396 int float_argreg; 5397 int argnum; 5398 int arg_space = 0; 5399 int stack_offset = 0; 5400 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5401 CORE_ADDR func_addr = find_function_addr (function, NULL); 5402 5403 /* For shared libraries, "t9" needs to point at the function 5404 address. */ 5405 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5406 5407 /* Set the return address register to point to the entry point of 5408 the program, where a breakpoint lies in wait. */ 5409 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5410 5411 /* First ensure that the stack and structure return address (if any) 5412 are properly aligned. The stack has to be at least 64-bit 5413 aligned even on 32-bit machines, because doubles must be 64-bit 5414 aligned. For n32 and n64, stack frames need to be 128-bit 5415 aligned, so we round to this widest known alignment. */ 5416 5417 sp = align_down (sp, 16); 5418 struct_addr = align_down (struct_addr, 16); 5419 5420 /* Now make space on the stack for the args. */ 5421 for (argnum = 0; argnum < nargs; argnum++) 5422 { 5423 struct type *arg_type = check_typedef (value_type (args[argnum])); 5424 5425 /* Align to double-word if necessary. */ 5426 if (mips_type_needs_double_align (arg_type)) 5427 arg_space = align_up (arg_space, MIPS32_REGSIZE * 2); 5428 /* Allocate space on the stack. */ 5429 arg_space += align_up (arg_type->length (), MIPS32_REGSIZE); 5430 } 5431 sp -= align_up (arg_space, 16); 5432 5433 if (mips_debug) 5434 gdb_printf (gdb_stdlog, 5435 "mips_o32_push_dummy_call: sp=%s allocated %ld\n", 5436 paddress (gdbarch, sp), 5437 (long) align_up (arg_space, 16)); 5438 5439 /* Initialize the integer and float register pointers. */ 5440 argreg = MIPS_A0_REGNUM; 5441 float_argreg = mips_fpa0_regnum (gdbarch); 5442 5443 /* The struct_return pointer occupies the first parameter-passing reg. */ 5444 if (return_method == return_method_struct) 5445 { 5446 if (mips_debug) 5447 gdb_printf (gdb_stdlog, 5448 "mips_o32_push_dummy_call: " 5449 "struct_return reg=%d %s\n", 5450 argreg, paddress (gdbarch, struct_addr)); 5451 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5452 stack_offset += MIPS32_REGSIZE; 5453 } 5454 5455 /* Now load as many as possible of the first arguments into 5456 registers, and push the rest onto the stack. Loop thru args 5457 from first to last. */ 5458 for (argnum = 0; argnum < nargs; argnum++) 5459 { 5460 const gdb_byte *val; 5461 struct value *arg = args[argnum]; 5462 struct type *arg_type = check_typedef (value_type (arg)); 5463 int len = arg_type->length (); 5464 enum type_code typecode = arg_type->code (); 5465 5466 if (mips_debug) 5467 gdb_printf (gdb_stdlog, 5468 "mips_o32_push_dummy_call: %d len=%d type=%d", 5469 argnum + 1, len, (int) typecode); 5470 5471 val = value_contents (arg).data (); 5472 5473 /* 32-bit ABIs always start floating point arguments in an 5474 even-numbered floating point register. Round the FP register 5475 up before the check to see if there are any FP registers 5476 left. O32 targets also pass the FP in the integer registers 5477 so also round up normal registers. */ 5478 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5479 { 5480 if ((float_argreg & 1)) 5481 float_argreg++; 5482 } 5483 5484 /* Floating point arguments passed in registers have to be 5485 treated specially. On 32-bit architectures, doubles are 5486 passed in register pairs; the even FP register gets the 5487 low word, and the odd FP register gets the high word. 5488 On O32, the first two floating point arguments are also 5489 copied to general registers, following their memory order, 5490 because MIPS16 functions don't use float registers for 5491 arguments. This duplication of arguments in general 5492 registers can't hurt non-MIPS16 functions, because those 5493 registers are normally skipped. */ 5494 5495 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5496 && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) 5497 { 5498 if (register_size (gdbarch, float_argreg) < 8 && len == 8) 5499 { 5500 int freg_offset = gdbarch_byte_order (gdbarch) 5501 == BFD_ENDIAN_BIG ? 1 : 0; 5502 unsigned long regval; 5503 5504 /* First word. */ 5505 regval = extract_unsigned_integer (val, 4, byte_order); 5506 if (mips_debug) 5507 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5508 float_argreg + freg_offset, 5509 phex (regval, 4)); 5510 regcache_cooked_write_unsigned (regcache, 5511 float_argreg++ + freg_offset, 5512 regval); 5513 if (mips_debug) 5514 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5515 argreg, phex (regval, 4)); 5516 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5517 5518 /* Second word. */ 5519 regval = extract_unsigned_integer (val + 4, 4, byte_order); 5520 if (mips_debug) 5521 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5522 float_argreg - freg_offset, 5523 phex (regval, 4)); 5524 regcache_cooked_write_unsigned (regcache, 5525 float_argreg++ - freg_offset, 5526 regval); 5527 if (mips_debug) 5528 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5529 argreg, phex (regval, 4)); 5530 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5531 } 5532 else 5533 { 5534 /* This is a floating point value that fits entirely 5535 in a single register. */ 5536 /* On 32 bit ABI's the float_argreg is further adjusted 5537 above to ensure that it is even register aligned. */ 5538 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 5539 if (mips_debug) 5540 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 5541 float_argreg, phex (regval, len)); 5542 regcache_cooked_write_unsigned (regcache, 5543 float_argreg++, regval); 5544 /* Although two FP registers are reserved for each 5545 argument, only one corresponding integer register is 5546 reserved. */ 5547 if (mips_debug) 5548 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5549 argreg, phex (regval, len)); 5550 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5551 } 5552 /* Reserve space for the FP register. */ 5553 stack_offset += align_up (len, MIPS32_REGSIZE); 5554 } 5555 else 5556 { 5557 /* Copy the argument to general registers or the stack in 5558 register-sized pieces. Large arguments are split between 5559 registers and stack. */ 5560 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE 5561 are treated specially: Irix cc passes 5562 them in registers where gcc sometimes puts them on the 5563 stack. For maximum compatibility, we will put them in 5564 both places. */ 5565 int odd_sized_struct = (len > MIPS32_REGSIZE 5566 && len % MIPS32_REGSIZE != 0); 5567 /* Structures should be aligned to eight bytes (even arg registers) 5568 on MIPS_ABI_O32, if their first member has double precision. */ 5569 if (mips_type_needs_double_align (arg_type)) 5570 { 5571 if ((argreg & 1)) 5572 { 5573 argreg++; 5574 stack_offset += MIPS32_REGSIZE; 5575 } 5576 } 5577 while (len > 0) 5578 { 5579 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); 5580 5581 if (mips_debug) 5582 gdb_printf (gdb_stdlog, " -- partial=%d", 5583 partial_len); 5584 5585 /* Write this portion of the argument to the stack. */ 5586 if (argreg > mips_last_arg_regnum (gdbarch) 5587 || odd_sized_struct) 5588 { 5589 /* Should shorter than int integer values be 5590 promoted to int before being stored? */ 5591 int longword_offset = 0; 5592 CORE_ADDR addr; 5593 5594 if (mips_debug) 5595 { 5596 gdb_printf (gdb_stdlog, " - stack_offset=%s", 5597 paddress (gdbarch, stack_offset)); 5598 gdb_printf (gdb_stdlog, " longword_offset=%s", 5599 paddress (gdbarch, longword_offset)); 5600 } 5601 5602 addr = sp + stack_offset + longword_offset; 5603 5604 if (mips_debug) 5605 { 5606 int i; 5607 gdb_printf (gdb_stdlog, " @%s ", 5608 paddress (gdbarch, addr)); 5609 for (i = 0; i < partial_len; i++) 5610 { 5611 gdb_printf (gdb_stdlog, "%02x", 5612 val[i] & 0xff); 5613 } 5614 } 5615 write_memory (addr, val, partial_len); 5616 } 5617 5618 /* Note!!! This is NOT an else clause. Odd sized 5619 structs may go thru BOTH paths. */ 5620 /* Write this portion of the argument to a general 5621 purpose register. */ 5622 if (argreg <= mips_last_arg_regnum (gdbarch)) 5623 { 5624 LONGEST regval = extract_signed_integer (val, partial_len, 5625 byte_order); 5626 /* Value may need to be sign extended, because 5627 mips_isa_regsize() != mips_abi_regsize(). */ 5628 5629 /* A non-floating-point argument being passed in a 5630 general register. If a struct or union, and if 5631 the remaining length is smaller than the register 5632 size, we have to adjust the register value on 5633 big endian targets. 5634 5635 It does not seem to be necessary to do the 5636 same for integral types. 5637 5638 Also don't do this adjustment on O64 binaries. 5639 5640 cagney/2001-07-23: gdb/179: Also, GCC, when 5641 outputting LE O32 with sizeof (struct) < 5642 mips_abi_regsize(), generates a left shift 5643 as part of storing the argument in a register 5644 (the left shift isn't generated when 5645 sizeof (struct) >= mips_abi_regsize()). Since 5646 it is quite possible that this is GCC 5647 contradicting the LE/O32 ABI, GDB has not been 5648 adjusted to accommodate this. Either someone 5649 needs to demonstrate that the LE/O32 ABI 5650 specifies such a left shift OR this new ABI gets 5651 identified as such and GDB gets tweaked 5652 accordingly. */ 5653 5654 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5655 && partial_len < MIPS32_REGSIZE 5656 && (typecode == TYPE_CODE_STRUCT 5657 || typecode == TYPE_CODE_UNION)) 5658 regval <<= ((MIPS32_REGSIZE - partial_len) 5659 * TARGET_CHAR_BIT); 5660 5661 if (mips_debug) 5662 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 5663 argreg, 5664 phex (regval, MIPS32_REGSIZE)); 5665 regcache_cooked_write_unsigned (regcache, argreg, regval); 5666 argreg++; 5667 5668 /* Prevent subsequent floating point arguments from 5669 being passed in floating point registers. */ 5670 float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; 5671 } 5672 5673 len -= partial_len; 5674 val += partial_len; 5675 5676 /* Compute the offset into the stack at which we will 5677 copy the next parameter. 5678 5679 In older ABIs, the caller reserved space for 5680 registers that contained arguments. This was loosely 5681 refered to as their "home". Consequently, space is 5682 always allocated. */ 5683 5684 stack_offset += align_up (partial_len, MIPS32_REGSIZE); 5685 } 5686 } 5687 if (mips_debug) 5688 gdb_printf (gdb_stdlog, "\n"); 5689 } 5690 5691 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5692 5693 /* Return adjusted stack pointer. */ 5694 return sp; 5695 } 5696 5697 static enum return_value_convention 5698 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, 5699 struct type *type, struct regcache *regcache, 5700 gdb_byte *readbuf, const gdb_byte *writebuf) 5701 { 5702 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 5703 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 5704 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 5705 enum mips_fval_reg fval_reg; 5706 5707 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 5708 if (type->code () == TYPE_CODE_STRUCT 5709 || type->code () == TYPE_CODE_UNION 5710 || type->code () == TYPE_CODE_ARRAY) 5711 return RETURN_VALUE_STRUCT_CONVENTION; 5712 else if (type->code () == TYPE_CODE_FLT 5713 && type->length () == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5714 { 5715 /* A single-precision floating-point value. If reading in or copying, 5716 then we get it from/put it to FP0 for standard MIPS code or GPR2 5717 for MIPS16 code. If writing out only, then we put it to both FP0 5718 and GPR2. We do not support reading in with no function known, if 5719 this safety check ever triggers, then we'll have to try harder. */ 5720 gdb_assert (function || !readbuf); 5721 if (mips_debug) 5722 switch (fval_reg) 5723 { 5724 case mips_fval_fpr: 5725 gdb_printf (gdb_stderr, "Return float in $fp0\n"); 5726 break; 5727 case mips_fval_gpr: 5728 gdb_printf (gdb_stderr, "Return float in $2\n"); 5729 break; 5730 case mips_fval_both: 5731 gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); 5732 break; 5733 } 5734 if (fval_reg != mips_fval_gpr) 5735 mips_xfer_register (gdbarch, regcache, 5736 (gdbarch_num_regs (gdbarch) 5737 + mips_regnum (gdbarch)->fp0), 5738 type->length (), 5739 gdbarch_byte_order (gdbarch), 5740 readbuf, writebuf, 0); 5741 if (fval_reg != mips_fval_fpr) 5742 mips_xfer_register (gdbarch, regcache, 5743 gdbarch_num_regs (gdbarch) + 2, 5744 type->length (), 5745 gdbarch_byte_order (gdbarch), 5746 readbuf, writebuf, 0); 5747 return RETURN_VALUE_REGISTER_CONVENTION; 5748 } 5749 else if (type->code () == TYPE_CODE_FLT 5750 && type->length () == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5751 { 5752 /* A double-precision floating-point value. If reading in or copying, 5753 then we get it from/put it to FP1 and FP0 for standard MIPS code or 5754 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it 5755 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with 5756 no function known, if this safety check ever triggers, then we'll 5757 have to try harder. */ 5758 gdb_assert (function || !readbuf); 5759 if (mips_debug) 5760 switch (fval_reg) 5761 { 5762 case mips_fval_fpr: 5763 gdb_printf (gdb_stderr, "Return float in $fp1/$fp0\n"); 5764 break; 5765 case mips_fval_gpr: 5766 gdb_printf (gdb_stderr, "Return float in $2/$3\n"); 5767 break; 5768 case mips_fval_both: 5769 gdb_printf (gdb_stderr, 5770 "Return float in $fp1/$fp0 and $2/$3\n"); 5771 break; 5772 } 5773 if (fval_reg != mips_fval_gpr) 5774 { 5775 /* The most significant part goes in FP1, and the least significant 5776 in FP0. */ 5777 switch (gdbarch_byte_order (gdbarch)) 5778 { 5779 case BFD_ENDIAN_LITTLE: 5780 mips_xfer_register (gdbarch, regcache, 5781 (gdbarch_num_regs (gdbarch) 5782 + mips_regnum (gdbarch)->fp0 + 0), 5783 4, gdbarch_byte_order (gdbarch), 5784 readbuf, writebuf, 0); 5785 mips_xfer_register (gdbarch, regcache, 5786 (gdbarch_num_regs (gdbarch) 5787 + mips_regnum (gdbarch)->fp0 + 1), 5788 4, gdbarch_byte_order (gdbarch), 5789 readbuf, writebuf, 4); 5790 break; 5791 case BFD_ENDIAN_BIG: 5792 mips_xfer_register (gdbarch, regcache, 5793 (gdbarch_num_regs (gdbarch) 5794 + mips_regnum (gdbarch)->fp0 + 1), 5795 4, gdbarch_byte_order (gdbarch), 5796 readbuf, writebuf, 0); 5797 mips_xfer_register (gdbarch, regcache, 5798 (gdbarch_num_regs (gdbarch) 5799 + mips_regnum (gdbarch)->fp0 + 0), 5800 4, gdbarch_byte_order (gdbarch), 5801 readbuf, writebuf, 4); 5802 break; 5803 default: 5804 internal_error (_("bad switch")); 5805 } 5806 } 5807 if (fval_reg != mips_fval_fpr) 5808 { 5809 /* The two 32-bit parts are always placed in GPR2 and GPR3 5810 following these registers' memory order. */ 5811 mips_xfer_register (gdbarch, regcache, 5812 gdbarch_num_regs (gdbarch) + 2, 5813 4, gdbarch_byte_order (gdbarch), 5814 readbuf, writebuf, 0); 5815 mips_xfer_register (gdbarch, regcache, 5816 gdbarch_num_regs (gdbarch) + 3, 5817 4, gdbarch_byte_order (gdbarch), 5818 readbuf, writebuf, 4); 5819 } 5820 return RETURN_VALUE_REGISTER_CONVENTION; 5821 } 5822 #if 0 5823 else if (type->code () == TYPE_CODE_STRUCT 5824 && type->num_fields () <= 2 5825 && type->num_fields () >= 1 5826 && ((type->num_fields () == 1 5827 && (TYPE_CODE (type->field (0).type ()) 5828 == TYPE_CODE_FLT)) 5829 || (type->num_fields () == 2 5830 && (TYPE_CODE (type->field (0).type ()) 5831 == TYPE_CODE_FLT) 5832 && (TYPE_CODE (type->field (1).type ()) 5833 == TYPE_CODE_FLT))) 5834 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5835 { 5836 /* A struct that contains one or two floats. Each value is part 5837 in the least significant part of their floating point 5838 register.. */ 5839 int regnum; 5840 int field; 5841 for (field = 0, regnum = mips_regnum (gdbarch)->fp0; 5842 field < type->num_fields (); field++, regnum += 2) 5843 { 5844 int offset = (type->fields ()[field].loc_bitpos () / TARGET_CHAR_BIT); 5845 if (mips_debug) 5846 gdb_printf (gdb_stderr, "Return float struct+%d\n", 5847 offset); 5848 mips_xfer_register (gdbarch, regcache, 5849 gdbarch_num_regs (gdbarch) + regnum, 5850 TYPE_LENGTH (type->field (field).type ()), 5851 gdbarch_byte_order (gdbarch), 5852 readbuf, writebuf, offset); 5853 } 5854 return RETURN_VALUE_REGISTER_CONVENTION; 5855 } 5856 #endif 5857 #if 0 5858 else if (type->code () == TYPE_CODE_STRUCT 5859 || type->code () == TYPE_CODE_UNION) 5860 { 5861 /* A structure or union. Extract the left justified value, 5862 regardless of the byte order. I.e. DO NOT USE 5863 mips_xfer_lower. */ 5864 int offset; 5865 int regnum; 5866 for (offset = 0, regnum = MIPS_V0_REGNUM; 5867 offset < type->length (); 5868 offset += register_size (gdbarch, regnum), regnum++) 5869 { 5870 int xfer = register_size (gdbarch, regnum); 5871 if (offset + xfer > type->length ()) 5872 xfer = type->length () - offset; 5873 if (mips_debug) 5874 gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", 5875 offset, xfer, regnum); 5876 mips_xfer_register (gdbarch, regcache, 5877 gdbarch_num_regs (gdbarch) + regnum, xfer, 5878 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); 5879 } 5880 return RETURN_VALUE_REGISTER_CONVENTION; 5881 } 5882 #endif 5883 else 5884 { 5885 /* A scalar extract each part but least-significant-byte 5886 justified. o32 thinks registers are 4 byte, regardless of 5887 the ISA. */ 5888 int offset; 5889 int regnum; 5890 for (offset = 0, regnum = MIPS_V0_REGNUM; 5891 offset < type->length (); 5892 offset += MIPS32_REGSIZE, regnum++) 5893 { 5894 int xfer = MIPS32_REGSIZE; 5895 if (offset + xfer > type->length ()) 5896 xfer = type->length () - offset; 5897 if (mips_debug) 5898 gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5899 offset, xfer, regnum); 5900 mips_xfer_register (gdbarch, regcache, 5901 gdbarch_num_regs (gdbarch) + regnum, xfer, 5902 gdbarch_byte_order (gdbarch), 5903 readbuf, writebuf, offset); 5904 } 5905 return RETURN_VALUE_REGISTER_CONVENTION; 5906 } 5907 } 5908 5909 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 5910 ABI. */ 5911 5912 static CORE_ADDR 5913 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5914 struct regcache *regcache, CORE_ADDR bp_addr, 5915 int nargs, 5916 struct value **args, CORE_ADDR sp, 5917 function_call_return_method return_method, CORE_ADDR struct_addr) 5918 { 5919 int argreg; 5920 int float_argreg; 5921 int argnum; 5922 int arg_space = 0; 5923 int stack_offset = 0; 5924 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5925 CORE_ADDR func_addr = find_function_addr (function, NULL); 5926 5927 /* For shared libraries, "t9" needs to point at the function 5928 address. */ 5929 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5930 5931 /* Set the return address register to point to the entry point of 5932 the program, where a breakpoint lies in wait. */ 5933 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5934 5935 /* First ensure that the stack and structure return address (if any) 5936 are properly aligned. The stack has to be at least 64-bit 5937 aligned even on 32-bit machines, because doubles must be 64-bit 5938 aligned. For n32 and n64, stack frames need to be 128-bit 5939 aligned, so we round to this widest known alignment. */ 5940 5941 sp = align_down (sp, 16); 5942 struct_addr = align_down (struct_addr, 16); 5943 5944 /* Now make space on the stack for the args. */ 5945 for (argnum = 0; argnum < nargs; argnum++) 5946 { 5947 struct type *arg_type = check_typedef (value_type (args[argnum])); 5948 5949 /* Allocate space on the stack. */ 5950 arg_space += align_up (arg_type->length (), MIPS64_REGSIZE); 5951 } 5952 sp -= align_up (arg_space, 16); 5953 5954 if (mips_debug) 5955 gdb_printf (gdb_stdlog, 5956 "mips_o64_push_dummy_call: sp=%s allocated %ld\n", 5957 paddress (gdbarch, sp), 5958 (long) align_up (arg_space, 16)); 5959 5960 /* Initialize the integer and float register pointers. */ 5961 argreg = MIPS_A0_REGNUM; 5962 float_argreg = mips_fpa0_regnum (gdbarch); 5963 5964 /* The struct_return pointer occupies the first parameter-passing reg. */ 5965 if (return_method == return_method_struct) 5966 { 5967 if (mips_debug) 5968 gdb_printf (gdb_stdlog, 5969 "mips_o64_push_dummy_call: " 5970 "struct_return reg=%d %s\n", 5971 argreg, paddress (gdbarch, struct_addr)); 5972 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5973 stack_offset += MIPS64_REGSIZE; 5974 } 5975 5976 /* Now load as many as possible of the first arguments into 5977 registers, and push the rest onto the stack. Loop thru args 5978 from first to last. */ 5979 for (argnum = 0; argnum < nargs; argnum++) 5980 { 5981 const gdb_byte *val; 5982 struct value *arg = args[argnum]; 5983 struct type *arg_type = check_typedef (value_type (arg)); 5984 int len = arg_type->length (); 5985 enum type_code typecode = arg_type->code (); 5986 5987 if (mips_debug) 5988 gdb_printf (gdb_stdlog, 5989 "mips_o64_push_dummy_call: %d len=%d type=%d", 5990 argnum + 1, len, (int) typecode); 5991 5992 val = value_contents (arg).data (); 5993 5994 /* Floating point arguments passed in registers have to be 5995 treated specially. On 32-bit architectures, doubles are 5996 passed in register pairs; the even FP register gets the 5997 low word, and the odd FP register gets the high word. 5998 On O64, the first two floating point arguments are also 5999 copied to general registers, because MIPS16 functions 6000 don't use float registers for arguments. This duplication 6001 of arguments in general registers can't hurt non-MIPS16 6002 functions because those registers are normally skipped. */ 6003 6004 if (fp_register_arg_p (gdbarch, typecode, arg_type) 6005 && float_argreg <= mips_last_fp_arg_regnum (gdbarch)) 6006 { 6007 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 6008 if (mips_debug) 6009 gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", 6010 float_argreg, phex (regval, len)); 6011 regcache_cooked_write_unsigned (regcache, float_argreg++, regval); 6012 if (mips_debug) 6013 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 6014 argreg, phex (regval, len)); 6015 regcache_cooked_write_unsigned (regcache, argreg, regval); 6016 argreg++; 6017 /* Reserve space for the FP register. */ 6018 stack_offset += align_up (len, MIPS64_REGSIZE); 6019 } 6020 else 6021 { 6022 /* Copy the argument to general registers or the stack in 6023 register-sized pieces. Large arguments are split between 6024 registers and stack. */ 6025 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE 6026 are treated specially: Irix cc passes them in registers 6027 where gcc sometimes puts them on the stack. For maximum 6028 compatibility, we will put them in both places. */ 6029 int odd_sized_struct = (len > MIPS64_REGSIZE 6030 && len % MIPS64_REGSIZE != 0); 6031 while (len > 0) 6032 { 6033 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 6034 6035 if (mips_debug) 6036 gdb_printf (gdb_stdlog, " -- partial=%d", 6037 partial_len); 6038 6039 /* Write this portion of the argument to the stack. */ 6040 if (argreg > mips_last_arg_regnum (gdbarch) 6041 || odd_sized_struct) 6042 { 6043 /* Should shorter than int integer values be 6044 promoted to int before being stored? */ 6045 int longword_offset = 0; 6046 CORE_ADDR addr; 6047 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6048 { 6049 if ((typecode == TYPE_CODE_INT 6050 || typecode == TYPE_CODE_PTR 6051 || typecode == TYPE_CODE_FLT) 6052 && len <= 4) 6053 longword_offset = MIPS64_REGSIZE - len; 6054 } 6055 6056 if (mips_debug) 6057 { 6058 gdb_printf (gdb_stdlog, " - stack_offset=%s", 6059 paddress (gdbarch, stack_offset)); 6060 gdb_printf (gdb_stdlog, " longword_offset=%s", 6061 paddress (gdbarch, longword_offset)); 6062 } 6063 6064 addr = sp + stack_offset + longword_offset; 6065 6066 if (mips_debug) 6067 { 6068 int i; 6069 gdb_printf (gdb_stdlog, " @%s ", 6070 paddress (gdbarch, addr)); 6071 for (i = 0; i < partial_len; i++) 6072 { 6073 gdb_printf (gdb_stdlog, "%02x", 6074 val[i] & 0xff); 6075 } 6076 } 6077 write_memory (addr, val, partial_len); 6078 } 6079 6080 /* Note!!! This is NOT an else clause. Odd sized 6081 structs may go thru BOTH paths. */ 6082 /* Write this portion of the argument to a general 6083 purpose register. */ 6084 if (argreg <= mips_last_arg_regnum (gdbarch)) 6085 { 6086 LONGEST regval = extract_signed_integer (val, partial_len, 6087 byte_order); 6088 /* Value may need to be sign extended, because 6089 mips_isa_regsize() != mips_abi_regsize(). */ 6090 6091 /* A non-floating-point argument being passed in a 6092 general register. If a struct or union, and if 6093 the remaining length is smaller than the register 6094 size, we have to adjust the register value on 6095 big endian targets. 6096 6097 It does not seem to be necessary to do the 6098 same for integral types. */ 6099 6100 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 6101 && partial_len < MIPS64_REGSIZE 6102 && (typecode == TYPE_CODE_STRUCT 6103 || typecode == TYPE_CODE_UNION)) 6104 regval <<= ((MIPS64_REGSIZE - partial_len) 6105 * TARGET_CHAR_BIT); 6106 6107 if (mips_debug) 6108 gdb_printf (gdb_stdlog, " - reg=%d val=%s", 6109 argreg, 6110 phex (regval, MIPS64_REGSIZE)); 6111 regcache_cooked_write_unsigned (regcache, argreg, regval); 6112 argreg++; 6113 6114 /* Prevent subsequent floating point arguments from 6115 being passed in floating point registers. */ 6116 float_argreg = mips_last_fp_arg_regnum (gdbarch) + 1; 6117 } 6118 6119 len -= partial_len; 6120 val += partial_len; 6121 6122 /* Compute the offset into the stack at which we will 6123 copy the next parameter. 6124 6125 In older ABIs, the caller reserved space for 6126 registers that contained arguments. This was loosely 6127 refered to as their "home". Consequently, space is 6128 always allocated. */ 6129 6130 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 6131 } 6132 } 6133 if (mips_debug) 6134 gdb_printf (gdb_stdlog, "\n"); 6135 } 6136 6137 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 6138 6139 /* Return adjusted stack pointer. */ 6140 return sp; 6141 } 6142 6143 static enum return_value_convention 6144 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, 6145 struct type *type, struct regcache *regcache, 6146 gdb_byte *readbuf, const gdb_byte *writebuf) 6147 { 6148 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 6149 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 6150 enum mips_fval_reg fval_reg; 6151 6152 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 6153 if (type->code () == TYPE_CODE_STRUCT 6154 || type->code () == TYPE_CODE_UNION 6155 || type->code () == TYPE_CODE_ARRAY) 6156 return RETURN_VALUE_STRUCT_CONVENTION; 6157 else if (fp_register_arg_p (gdbarch, type->code (), type)) 6158 { 6159 /* A floating-point value. If reading in or copying, then we get it 6160 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. 6161 If writing out only, then we put it to both FP0 and GPR2. We do 6162 not support reading in with no function known, if this safety 6163 check ever triggers, then we'll have to try harder. */ 6164 gdb_assert (function || !readbuf); 6165 if (mips_debug) 6166 switch (fval_reg) 6167 { 6168 case mips_fval_fpr: 6169 gdb_printf (gdb_stderr, "Return float in $fp0\n"); 6170 break; 6171 case mips_fval_gpr: 6172 gdb_printf (gdb_stderr, "Return float in $2\n"); 6173 break; 6174 case mips_fval_both: 6175 gdb_printf (gdb_stderr, "Return float in $fp0 and $2\n"); 6176 break; 6177 } 6178 if (fval_reg != mips_fval_gpr) 6179 mips_xfer_register (gdbarch, regcache, 6180 (gdbarch_num_regs (gdbarch) 6181 + mips_regnum (gdbarch)->fp0), 6182 type->length (), 6183 gdbarch_byte_order (gdbarch), 6184 readbuf, writebuf, 0); 6185 if (fval_reg != mips_fval_fpr) 6186 mips_xfer_register (gdbarch, regcache, 6187 gdbarch_num_regs (gdbarch) + 2, 6188 type->length (), 6189 gdbarch_byte_order (gdbarch), 6190 readbuf, writebuf, 0); 6191 return RETURN_VALUE_REGISTER_CONVENTION; 6192 } 6193 else 6194 { 6195 /* A scalar extract each part but least-significant-byte 6196 justified. */ 6197 int offset; 6198 int regnum; 6199 for (offset = 0, regnum = MIPS_V0_REGNUM; 6200 offset < type->length (); 6201 offset += MIPS64_REGSIZE, regnum++) 6202 { 6203 int xfer = MIPS64_REGSIZE; 6204 if (offset + xfer > type->length ()) 6205 xfer = type->length () - offset; 6206 if (mips_debug) 6207 gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", 6208 offset, xfer, regnum); 6209 mips_xfer_register (gdbarch, regcache, 6210 gdbarch_num_regs (gdbarch) + regnum, 6211 xfer, gdbarch_byte_order (gdbarch), 6212 readbuf, writebuf, offset); 6213 } 6214 return RETURN_VALUE_REGISTER_CONVENTION; 6215 } 6216 } 6217 6218 /* Floating point register management. 6219 6220 Background: MIPS1 & 2 fp registers are 32 bits wide. To support 6221 64bit operations, these early MIPS cpus treat fp register pairs 6222 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp 6223 registers and offer a compatibility mode that emulates the MIPS2 fp 6224 model. When operating in MIPS2 fp compat mode, later cpu's split 6225 double precision floats into two 32-bit chunks and store them in 6226 consecutive fp regs. To display 64-bit floats stored in this 6227 fashion, we have to combine 32 bits from f0 and 32 bits from f1. 6228 Throw in user-configurable endianness and you have a real mess. 6229 6230 The way this works is: 6231 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit 6232 double-precision value will be split across two logical registers. 6233 The lower-numbered logical register will hold the low-order bits, 6234 regardless of the processor's endianness. 6235 - If we are on a 64-bit processor, and we are looking for a 6236 single-precision value, it will be in the low ordered bits 6237 of a 64-bit GPR (after mfc1, for example) or a 64-bit register 6238 save slot in memory. 6239 - If we are in 64-bit mode, everything is straightforward. 6240 6241 Note that this code only deals with "live" registers at the top of the 6242 stack. We will attempt to deal with saved registers later, when 6243 the raw/cooked register interface is in place. (We need a general 6244 interface that can deal with dynamic saved register sizes -- fp 6245 regs could be 32 bits wide in one frame and 64 on the frame above 6246 and below). */ 6247 6248 /* Copy a 32-bit single-precision value from the current frame 6249 into rare_buffer. */ 6250 6251 static void 6252 mips_read_fp_register_single (frame_info_ptr frame, int regno, 6253 gdb_byte *rare_buffer) 6254 { 6255 struct gdbarch *gdbarch = get_frame_arch (frame); 6256 int raw_size = register_size (gdbarch, regno); 6257 gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); 6258 6259 if (!deprecated_frame_register_read (frame, regno, raw_buffer)) 6260 error (_("can't read register %d (%s)"), 6261 regno, gdbarch_register_name (gdbarch, regno)); 6262 if (raw_size == 8) 6263 { 6264 /* We have a 64-bit value for this register. Find the low-order 6265 32 bits. */ 6266 int offset; 6267 6268 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6269 offset = 4; 6270 else 6271 offset = 0; 6272 6273 memcpy (rare_buffer, raw_buffer + offset, 4); 6274 } 6275 else 6276 { 6277 memcpy (rare_buffer, raw_buffer, 4); 6278 } 6279 } 6280 6281 /* Copy a 64-bit double-precision value from the current frame into 6282 rare_buffer. This may include getting half of it from the next 6283 register. */ 6284 6285 static void 6286 mips_read_fp_register_double (frame_info_ptr frame, int regno, 6287 gdb_byte *rare_buffer) 6288 { 6289 struct gdbarch *gdbarch = get_frame_arch (frame); 6290 int raw_size = register_size (gdbarch, regno); 6291 6292 if (raw_size == 8 && !mips2_fp_compat (frame)) 6293 { 6294 /* We have a 64-bit value for this register, and we should use 6295 all 64 bits. */ 6296 if (!deprecated_frame_register_read (frame, regno, rare_buffer)) 6297 error (_("can't read register %d (%s)"), 6298 regno, gdbarch_register_name (gdbarch, regno)); 6299 } 6300 else 6301 { 6302 int rawnum = regno % gdbarch_num_regs (gdbarch); 6303 6304 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) 6305 internal_error (_("mips_read_fp_register_double: bad access to " 6306 "odd-numbered FP register")); 6307 6308 /* mips_read_fp_register_single will find the correct 32 bits from 6309 each register. */ 6310 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6311 { 6312 mips_read_fp_register_single (frame, regno, rare_buffer + 4); 6313 mips_read_fp_register_single (frame, regno + 1, rare_buffer); 6314 } 6315 else 6316 { 6317 mips_read_fp_register_single (frame, regno, rare_buffer); 6318 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); 6319 } 6320 } 6321 } 6322 6323 static void 6324 mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, 6325 int regnum) 6326 { /* Do values for FP (float) regs. */ 6327 struct gdbarch *gdbarch = get_frame_arch (frame); 6328 gdb_byte *raw_buffer; 6329 std::string flt_str, dbl_str; 6330 6331 const struct type *flt_type = builtin_type (gdbarch)->builtin_float; 6332 const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; 6333 6334 raw_buffer 6335 = ((gdb_byte *) 6336 alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); 6337 6338 gdb_printf (file, "%s:", gdbarch_register_name (gdbarch, regnum)); 6339 gdb_printf (file, "%*s", 6340 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), 6341 ""); 6342 6343 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) 6344 { 6345 struct value_print_options opts; 6346 6347 /* 4-byte registers: Print hex and floating. Also print even 6348 numbered registers as doubles. */ 6349 mips_read_fp_register_single (frame, regnum, raw_buffer); 6350 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); 6351 6352 get_formatted_print_options (&opts, 'x'); 6353 print_scalar_formatted (raw_buffer, 6354 builtin_type (gdbarch)->builtin_uint32, 6355 &opts, 'w', file); 6356 6357 gdb_printf (file, " flt: %s", flt_str.c_str ()); 6358 6359 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) 6360 { 6361 mips_read_fp_register_double (frame, regnum, raw_buffer); 6362 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); 6363 6364 gdb_printf (file, " dbl: %s", dbl_str.c_str ()); 6365 } 6366 } 6367 else 6368 { 6369 struct value_print_options opts; 6370 6371 /* Eight byte registers: print each one as hex, float and double. */ 6372 mips_read_fp_register_single (frame, regnum, raw_buffer); 6373 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); 6374 6375 mips_read_fp_register_double (frame, regnum, raw_buffer); 6376 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); 6377 6378 get_formatted_print_options (&opts, 'x'); 6379 print_scalar_formatted (raw_buffer, 6380 builtin_type (gdbarch)->builtin_uint64, 6381 &opts, 'g', file); 6382 6383 gdb_printf (file, " flt: %s", flt_str.c_str ()); 6384 gdb_printf (file, " dbl: %s", dbl_str.c_str ()); 6385 } 6386 } 6387 6388 static void 6389 mips_print_register (struct ui_file *file, frame_info_ptr frame, 6390 int regnum) 6391 { 6392 struct gdbarch *gdbarch = get_frame_arch (frame); 6393 struct value_print_options opts; 6394 struct value *val; 6395 6396 if (mips_float_register_p (gdbarch, regnum)) 6397 { 6398 mips_print_fp_register (file, frame, regnum); 6399 return; 6400 } 6401 6402 val = get_frame_register_value (frame, regnum); 6403 6404 gdb_puts (gdbarch_register_name (gdbarch, regnum), file); 6405 6406 /* The problem with printing numeric register names (r26, etc.) is that 6407 the user can't use them on input. Probably the best solution is to 6408 fix it so that either the numeric or the funky (a2, etc.) names 6409 are accepted on input. */ 6410 if (regnum < MIPS_NUMREGS) 6411 gdb_printf (file, "(r%d): ", regnum); 6412 else 6413 gdb_printf (file, ": "); 6414 6415 get_formatted_print_options (&opts, 'x'); 6416 value_print_scalar_formatted (val, &opts, 0, file); 6417 } 6418 6419 /* Print IEEE exception condition bits in FLAGS. */ 6420 6421 static void 6422 print_fpu_flags (struct ui_file *file, int flags) 6423 { 6424 if (flags & (1 << 0)) 6425 gdb_puts (" inexact", file); 6426 if (flags & (1 << 1)) 6427 gdb_puts (" uflow", file); 6428 if (flags & (1 << 2)) 6429 gdb_puts (" oflow", file); 6430 if (flags & (1 << 3)) 6431 gdb_puts (" div0", file); 6432 if (flags & (1 << 4)) 6433 gdb_puts (" inval", file); 6434 if (flags & (1 << 5)) 6435 gdb_puts (" unimp", file); 6436 gdb_putc ('\n', file); 6437 } 6438 6439 /* Print interesting information about the floating point processor 6440 (if present) or emulator. */ 6441 6442 static void 6443 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, 6444 frame_info_ptr frame, const char *args) 6445 { 6446 int fcsr = mips_regnum (gdbarch)->fp_control_status; 6447 enum mips_fpu_type type = mips_get_fpu_type (gdbarch); 6448 ULONGEST fcs = 0; 6449 int i; 6450 6451 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) 6452 type = MIPS_FPU_NONE; 6453 6454 gdb_printf (file, "fpu type: %s\n", 6455 type == MIPS_FPU_DOUBLE ? "double-precision" 6456 : type == MIPS_FPU_SINGLE ? "single-precision" 6457 : "none / unused"); 6458 6459 if (type == MIPS_FPU_NONE) 6460 return; 6461 6462 gdb_printf (file, "reg size: %d bits\n", 6463 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); 6464 6465 gdb_puts ("cond :", file); 6466 if (fcs & (1 << 23)) 6467 gdb_puts (" 0", file); 6468 for (i = 1; i <= 7; i++) 6469 if (fcs & (1 << (24 + i))) 6470 gdb_printf (file, " %d", i); 6471 gdb_putc ('\n', file); 6472 6473 gdb_puts ("cause :", file); 6474 print_fpu_flags (file, (fcs >> 12) & 0x3f); 6475 fputs ("mask :", stdout); 6476 print_fpu_flags (file, (fcs >> 7) & 0x1f); 6477 fputs ("flags :", stdout); 6478 print_fpu_flags (file, (fcs >> 2) & 0x1f); 6479 6480 gdb_puts ("rounding: ", file); 6481 switch (fcs & 3) 6482 { 6483 case 0: gdb_puts ("nearest\n", file); break; 6484 case 1: gdb_puts ("zero\n", file); break; 6485 case 2: gdb_puts ("+inf\n", file); break; 6486 case 3: gdb_puts ("-inf\n", file); break; 6487 } 6488 6489 gdb_puts ("flush :", file); 6490 if (fcs & (1 << 21)) 6491 gdb_puts (" nearest", file); 6492 if (fcs & (1 << 22)) 6493 gdb_puts (" override", file); 6494 if (fcs & (1 << 24)) 6495 gdb_puts (" zero", file); 6496 if ((fcs & (0xb << 21)) == 0) 6497 gdb_puts (" no", file); 6498 gdb_putc ('\n', file); 6499 6500 gdb_printf (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); 6501 gdb_printf (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); 6502 gdb_putc ('\n', file); 6503 6504 default_print_float_info (gdbarch, file, frame, args); 6505 } 6506 6507 /* Replacement for generic do_registers_info. 6508 Print regs in pretty columns. */ 6509 6510 static int 6511 print_fp_register_row (struct ui_file *file, frame_info_ptr frame, 6512 int regnum) 6513 { 6514 gdb_printf (file, " "); 6515 mips_print_fp_register (file, frame, regnum); 6516 gdb_printf (file, "\n"); 6517 return regnum + 1; 6518 } 6519 6520 6521 /* Print a row's worth of GP (int) registers, with name labels above. */ 6522 6523 static int 6524 print_gp_register_row (struct ui_file *file, frame_info_ptr frame, 6525 int start_regnum) 6526 { 6527 struct gdbarch *gdbarch = get_frame_arch (frame); 6528 /* Do values for GP (int) regs. */ 6529 const gdb_byte *raw_buffer; 6530 struct value *value; 6531 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols 6532 per row. */ 6533 int col, byte; 6534 int regnum; 6535 6536 /* For GP registers, we print a separate row of names above the vals. */ 6537 for (col = 0, regnum = start_regnum; 6538 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); 6539 regnum++) 6540 { 6541 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6542 continue; /* unused register */ 6543 if (mips_float_register_p (gdbarch, regnum)) 6544 break; /* End the row: reached FP register. */ 6545 /* Large registers are handled separately. */ 6546 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6547 { 6548 if (col > 0) 6549 break; /* End the row before this register. */ 6550 6551 /* Print this register on a row by itself. */ 6552 mips_print_register (file, frame, regnum); 6553 gdb_printf (file, "\n"); 6554 return regnum + 1; 6555 } 6556 if (col == 0) 6557 gdb_printf (file, " "); 6558 gdb_printf (file, 6559 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", 6560 gdbarch_register_name (gdbarch, regnum)); 6561 col++; 6562 } 6563 6564 if (col == 0) 6565 return regnum; 6566 6567 /* Print the R0 to R31 names. */ 6568 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) 6569 gdb_printf (file, "\n R%-4d", 6570 start_regnum % gdbarch_num_regs (gdbarch)); 6571 else 6572 gdb_printf (file, "\n "); 6573 6574 /* Now print the values in hex, 4 or 8 to the row. */ 6575 for (col = 0, regnum = start_regnum; 6576 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); 6577 regnum++) 6578 { 6579 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6580 continue; /* unused register */ 6581 if (mips_float_register_p (gdbarch, regnum)) 6582 break; /* End row: reached FP register. */ 6583 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6584 break; /* End row: large register. */ 6585 6586 /* OK: get the data in raw format. */ 6587 value = get_frame_register_value (frame, regnum); 6588 if (value_optimized_out (value) 6589 || !value_entirely_available (value)) 6590 { 6591 gdb_printf (file, "%*s ", 6592 (int) mips_abi_regsize (gdbarch) * 2, 6593 (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" 6594 : "<unavailable>")); 6595 col++; 6596 continue; 6597 } 6598 raw_buffer = value_contents_all (value).data (); 6599 /* pad small registers */ 6600 for (byte = 0; 6601 byte < (mips_abi_regsize (gdbarch) 6602 - register_size (gdbarch, regnum)); byte++) 6603 gdb_printf (file, " "); 6604 /* Now print the register value in hex, endian order. */ 6605 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6606 for (byte = 6607 register_size (gdbarch, regnum) - register_size (gdbarch, regnum); 6608 byte < register_size (gdbarch, regnum); byte++) 6609 gdb_printf (file, "%02x", raw_buffer[byte]); 6610 else 6611 for (byte = register_size (gdbarch, regnum) - 1; 6612 byte >= 0; byte--) 6613 gdb_printf (file, "%02x", raw_buffer[byte]); 6614 gdb_printf (file, " "); 6615 col++; 6616 } 6617 if (col > 0) /* ie. if we actually printed anything... */ 6618 gdb_printf (file, "\n"); 6619 6620 return regnum; 6621 } 6622 6623 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ 6624 6625 static void 6626 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 6627 frame_info_ptr frame, int regnum, int all) 6628 { 6629 if (regnum != -1) /* Do one specified register. */ 6630 { 6631 gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); 6632 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') 6633 error (_("Not a valid register for the current processor type")); 6634 6635 mips_print_register (file, frame, regnum); 6636 gdb_printf (file, "\n"); 6637 } 6638 else 6639 /* Do all (or most) registers. */ 6640 { 6641 regnum = gdbarch_num_regs (gdbarch); 6642 while (regnum < gdbarch_num_cooked_regs (gdbarch)) 6643 { 6644 if (mips_float_register_p (gdbarch, regnum)) 6645 { 6646 if (all) /* True for "INFO ALL-REGISTERS" command. */ 6647 regnum = print_fp_register_row (file, frame, regnum); 6648 else 6649 regnum += MIPS_NUMREGS; /* Skip floating point regs. */ 6650 } 6651 else 6652 regnum = print_gp_register_row (file, frame, regnum); 6653 } 6654 } 6655 } 6656 6657 static int 6658 mips_single_step_through_delay (struct gdbarch *gdbarch, 6659 frame_info_ptr frame) 6660 { 6661 CORE_ADDR pc = get_frame_pc (frame); 6662 enum mips_isa isa; 6663 ULONGEST insn; 6664 int size; 6665 6666 if ((mips_pc_is_mips (pc) 6667 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) 6668 || (mips_pc_is_micromips (gdbarch, pc) 6669 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) 6670 || (mips_pc_is_mips16 (gdbarch, pc) 6671 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) 6672 return 0; 6673 6674 isa = mips_pc_isa (gdbarch, pc); 6675 /* _has_delay_slot above will have validated the read. */ 6676 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); 6677 size = mips_insn_size (isa, insn); 6678 6679 const address_space *aspace = get_frame_address_space (frame); 6680 6681 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; 6682 } 6683 6684 /* To skip prologues, I use this predicate. Returns either PC itself 6685 if the code at PC does not look like a function prologue; otherwise 6686 returns an address that (if we're lucky) follows the prologue. If 6687 LENIENT, then we must skip everything which is involved in setting 6688 up the frame (it's OK to skip more, just so long as we don't skip 6689 anything which might clobber the registers which are being saved. 6690 We must skip more in the case where part of the prologue is in the 6691 delay slot of a non-prologue instruction). */ 6692 6693 static CORE_ADDR 6694 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 6695 { 6696 CORE_ADDR limit_pc; 6697 CORE_ADDR func_addr; 6698 6699 /* See if we can determine the end of the prologue via the symbol table. 6700 If so, then return either PC, or the PC after the prologue, whichever 6701 is greater. */ 6702 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 6703 { 6704 CORE_ADDR post_prologue_pc 6705 = skip_prologue_using_sal (gdbarch, func_addr); 6706 if (post_prologue_pc != 0) 6707 return std::max (pc, post_prologue_pc); 6708 } 6709 6710 /* Can't determine prologue from the symbol table, need to examine 6711 instructions. */ 6712 6713 /* Find an upper limit on the function prologue using the debug 6714 information. If the debug information could not be used to provide 6715 that bound, then use an arbitrary large number as the upper bound. */ 6716 limit_pc = skip_prologue_using_sal (gdbarch, pc); 6717 if (limit_pc == 0) 6718 limit_pc = pc + 100; /* Magic. */ 6719 6720 if (mips_pc_is_mips16 (gdbarch, pc)) 6721 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6722 else if (mips_pc_is_micromips (gdbarch, pc)) 6723 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6724 else 6725 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6726 } 6727 6728 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). 6729 This is a helper function for mips_stack_frame_destroyed_p. */ 6730 6731 static int 6732 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6733 { 6734 CORE_ADDR func_addr = 0, func_end = 0; 6735 6736 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6737 { 6738 /* The MIPS epilogue is max. 12 bytes long. */ 6739 CORE_ADDR addr = func_end - 12; 6740 6741 if (addr < func_addr + 4) 6742 addr = func_addr + 4; 6743 if (pc < addr) 6744 return 0; 6745 6746 for (; pc < func_end; pc += MIPS_INSN32_SIZE) 6747 { 6748 unsigned long high_word; 6749 unsigned long inst; 6750 6751 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 6752 high_word = (inst >> 16) & 0xffff; 6753 6754 if (high_word != 0x27bd /* addiu $sp,$sp,offset */ 6755 && high_word != 0x67bd /* daddiu $sp,$sp,offset */ 6756 && inst != 0x03e00008 /* jr $ra */ 6757 && inst != 0x00000000) /* nop */ 6758 return 0; 6759 } 6760 6761 return 1; 6762 } 6763 6764 return 0; 6765 } 6766 6767 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). 6768 This is a helper function for mips_stack_frame_destroyed_p. */ 6769 6770 static int 6771 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6772 { 6773 CORE_ADDR func_addr = 0; 6774 CORE_ADDR func_end = 0; 6775 CORE_ADDR addr; 6776 ULONGEST insn; 6777 long offset; 6778 int dreg; 6779 int sreg; 6780 int loc; 6781 6782 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6783 return 0; 6784 6785 /* The microMIPS epilogue is max. 12 bytes long. */ 6786 addr = func_end - 12; 6787 6788 if (addr < func_addr + 2) 6789 addr = func_addr + 2; 6790 if (pc < addr) 6791 return 0; 6792 6793 for (; pc < func_end; pc += loc) 6794 { 6795 loc = 0; 6796 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 6797 loc += MIPS_INSN16_SIZE; 6798 switch (mips_insn_size (ISA_MICROMIPS, insn)) 6799 { 6800 /* 32-bit instructions. */ 6801 case 2 * MIPS_INSN16_SIZE: 6802 insn <<= 16; 6803 insn |= mips_fetch_instruction (gdbarch, 6804 ISA_MICROMIPS, pc + loc, NULL); 6805 loc += MIPS_INSN16_SIZE; 6806 switch (micromips_op (insn >> 16)) 6807 { 6808 case 0xc: /* ADDIU: bits 001100 */ 6809 case 0x17: /* DADDIU: bits 010111 */ 6810 sreg = b0s5_reg (insn >> 16); 6811 dreg = b5s5_reg (insn >> 16); 6812 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 6813 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 6814 /* (D)ADDIU $sp, imm */ 6815 && offset >= 0) 6816 break; 6817 return 0; 6818 6819 default: 6820 return 0; 6821 } 6822 break; 6823 6824 /* 16-bit instructions. */ 6825 case MIPS_INSN16_SIZE: 6826 switch (micromips_op (insn)) 6827 { 6828 case 0x3: /* MOVE: bits 000011 */ 6829 sreg = b0s5_reg (insn); 6830 dreg = b5s5_reg (insn); 6831 if (sreg == 0 && dreg == 0) 6832 /* MOVE $zero, $zero aka NOP */ 6833 break; 6834 return 0; 6835 6836 case 0x11: /* POOL16C: bits 010001 */ 6837 if (b5s5_op (insn) == 0x18 6838 /* JRADDIUSP: bits 010011 11000 */ 6839 || (b5s5_op (insn) == 0xd 6840 /* JRC: bits 010011 01101 */ 6841 && b0s5_reg (insn) == MIPS_RA_REGNUM)) 6842 /* JRC $ra */ 6843 break; 6844 return 0; 6845 6846 case 0x13: /* POOL16D: bits 010011 */ 6847 offset = micromips_decode_imm9 (b1s9_imm (insn)); 6848 if ((insn & 0x1) == 0x1 6849 /* ADDIUSP: bits 010011 1 */ 6850 && offset > 0) 6851 break; 6852 return 0; 6853 6854 default: 6855 return 0; 6856 } 6857 } 6858 } 6859 6860 return 1; 6861 } 6862 6863 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). 6864 This is a helper function for mips_stack_frame_destroyed_p. */ 6865 6866 static int 6867 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6868 { 6869 CORE_ADDR func_addr = 0, func_end = 0; 6870 6871 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6872 { 6873 /* The MIPS epilogue is max. 12 bytes long. */ 6874 CORE_ADDR addr = func_end - 12; 6875 6876 if (addr < func_addr + 4) 6877 addr = func_addr + 4; 6878 if (pc < addr) 6879 return 0; 6880 6881 for (; pc < func_end; pc += MIPS_INSN16_SIZE) 6882 { 6883 unsigned short inst; 6884 6885 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); 6886 6887 if ((inst & 0xf800) == 0xf000) /* extend */ 6888 continue; 6889 6890 if (inst != 0x6300 /* addiu $sp,offset */ 6891 && inst != 0xfb00 /* daddiu $sp,$sp,offset */ 6892 && inst != 0xe820 /* jr $ra */ 6893 && inst != 0xe8a0 /* jrc $ra */ 6894 && inst != 0x6500) /* nop */ 6895 return 0; 6896 } 6897 6898 return 1; 6899 } 6900 6901 return 0; 6902 } 6903 6904 /* Implement the stack_frame_destroyed_p gdbarch method. 6905 6906 The epilogue is defined here as the area at the end of a function, 6907 after an instruction which destroys the function's stack frame. */ 6908 6909 static int 6910 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6911 { 6912 if (mips_pc_is_mips16 (gdbarch, pc)) 6913 return mips16_stack_frame_destroyed_p (gdbarch, pc); 6914 else if (mips_pc_is_micromips (gdbarch, pc)) 6915 return micromips_stack_frame_destroyed_p (gdbarch, pc); 6916 else 6917 return mips32_stack_frame_destroyed_p (gdbarch, pc); 6918 } 6919 6920 /* Commands to show/set the MIPS FPU type. */ 6921 6922 static void 6923 show_mipsfpu_command (const char *args, int from_tty) 6924 { 6925 const char *fpu; 6926 6927 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 6928 { 6929 gdb_printf 6930 ("The MIPS floating-point coprocessor is unknown " 6931 "because the current architecture is not MIPS.\n"); 6932 return; 6933 } 6934 6935 switch (mips_get_fpu_type (target_gdbarch ())) 6936 { 6937 case MIPS_FPU_SINGLE: 6938 fpu = "single-precision"; 6939 break; 6940 case MIPS_FPU_DOUBLE: 6941 fpu = "double-precision"; 6942 break; 6943 case MIPS_FPU_NONE: 6944 fpu = "absent (none)"; 6945 break; 6946 default: 6947 internal_error (_("bad switch")); 6948 } 6949 if (mips_fpu_type_auto) 6950 gdb_printf ("The MIPS floating-point coprocessor " 6951 "is set automatically (currently %s)\n", 6952 fpu); 6953 else 6954 gdb_printf 6955 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); 6956 } 6957 6958 6959 static void 6960 set_mipsfpu_single_command (const char *args, int from_tty) 6961 { 6962 struct gdbarch_info info; 6963 mips_fpu_type = MIPS_FPU_SINGLE; 6964 mips_fpu_type_auto = 0; 6965 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6966 instead of relying on globals. Doing that would let generic code 6967 handle the search for this specific architecture. */ 6968 if (!gdbarch_update_p (info)) 6969 internal_error (_("set mipsfpu failed")); 6970 } 6971 6972 static void 6973 set_mipsfpu_double_command (const char *args, int from_tty) 6974 { 6975 struct gdbarch_info info; 6976 mips_fpu_type = MIPS_FPU_DOUBLE; 6977 mips_fpu_type_auto = 0; 6978 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6979 instead of relying on globals. Doing that would let generic code 6980 handle the search for this specific architecture. */ 6981 if (!gdbarch_update_p (info)) 6982 internal_error (_("set mipsfpu failed")); 6983 } 6984 6985 static void 6986 set_mipsfpu_none_command (const char *args, int from_tty) 6987 { 6988 struct gdbarch_info info; 6989 mips_fpu_type = MIPS_FPU_NONE; 6990 mips_fpu_type_auto = 0; 6991 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6992 instead of relying on globals. Doing that would let generic code 6993 handle the search for this specific architecture. */ 6994 if (!gdbarch_update_p (info)) 6995 internal_error (_("set mipsfpu failed")); 6996 } 6997 6998 static void 6999 set_mipsfpu_auto_command (const char *args, int from_tty) 7000 { 7001 mips_fpu_type_auto = 1; 7002 } 7003 7004 /* Just like reinit_frame_cache, but with the right arguments to be 7005 callable as an sfunc. */ 7006 7007 static void 7008 reinit_frame_cache_sfunc (const char *args, int from_tty, 7009 struct cmd_list_element *c) 7010 { 7011 reinit_frame_cache (); 7012 } 7013 7014 static int 7015 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) 7016 { 7017 gdb_disassemble_info *di 7018 = static_cast<gdb_disassemble_info *> (info->application_data); 7019 struct gdbarch *gdbarch = di->arch (); 7020 7021 /* FIXME: cagney/2003-06-26: Is this even necessary? The 7022 disassembler needs to be able to locally determine the ISA, and 7023 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not 7024 work. */ 7025 if (mips_pc_is_mips16 (gdbarch, memaddr)) 7026 info->mach = bfd_mach_mips16; 7027 else if (mips_pc_is_micromips (gdbarch, memaddr)) 7028 info->mach = bfd_mach_mips_micromips; 7029 7030 /* Round down the instruction address to the appropriate boundary. */ 7031 memaddr &= (info->mach == bfd_mach_mips16 7032 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; 7033 7034 return default_print_insn (memaddr, info); 7035 } 7036 7037 /* Implement the breakpoint_kind_from_pc gdbarch method. */ 7038 7039 static int 7040 mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 7041 { 7042 CORE_ADDR pc = *pcptr; 7043 7044 if (mips_pc_is_mips16 (gdbarch, pc)) 7045 { 7046 *pcptr = unmake_compact_addr (pc); 7047 return MIPS_BP_KIND_MIPS16; 7048 } 7049 else if (mips_pc_is_micromips (gdbarch, pc)) 7050 { 7051 ULONGEST insn; 7052 int status; 7053 7054 *pcptr = unmake_compact_addr (pc); 7055 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); 7056 if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) 7057 return MIPS_BP_KIND_MICROMIPS16; 7058 else 7059 return MIPS_BP_KIND_MICROMIPS32; 7060 } 7061 else 7062 return MIPS_BP_KIND_MIPS32; 7063 } 7064 7065 /* Implement the sw_breakpoint_from_kind gdbarch method. */ 7066 7067 static const gdb_byte * 7068 mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 7069 { 7070 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); 7071 7072 switch (kind) 7073 { 7074 case MIPS_BP_KIND_MIPS16: 7075 { 7076 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; 7077 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; 7078 7079 *size = 2; 7080 if (byte_order_for_code == BFD_ENDIAN_BIG) 7081 return mips16_big_breakpoint; 7082 else 7083 return mips16_little_breakpoint; 7084 } 7085 case MIPS_BP_KIND_MICROMIPS16: 7086 { 7087 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; 7088 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; 7089 7090 *size = 2; 7091 7092 if (byte_order_for_code == BFD_ENDIAN_BIG) 7093 return micromips16_big_breakpoint; 7094 else 7095 return micromips16_little_breakpoint; 7096 } 7097 case MIPS_BP_KIND_MICROMIPS32: 7098 { 7099 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; 7100 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; 7101 7102 *size = 4; 7103 if (byte_order_for_code == BFD_ENDIAN_BIG) 7104 return micromips32_big_breakpoint; 7105 else 7106 return micromips32_little_breakpoint; 7107 } 7108 case MIPS_BP_KIND_MIPS32: 7109 { 7110 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; 7111 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; 7112 7113 *size = 4; 7114 if (byte_order_for_code == BFD_ENDIAN_BIG) 7115 return big_breakpoint; 7116 else 7117 return little_breakpoint; 7118 } 7119 default: 7120 gdb_assert_not_reached ("unexpected mips breakpoint kind"); 7121 }; 7122 } 7123 7124 /* Return non-zero if the standard MIPS instruction INST has a branch 7125 delay slot (i.e. it is a jump or branch instruction). This function 7126 is based on mips32_next_pc. */ 7127 7128 static int 7129 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) 7130 { 7131 int op; 7132 int rs; 7133 int rt; 7134 7135 op = itype_op (inst); 7136 if ((inst & 0xe0000000) != 0) 7137 { 7138 rs = itype_rs (inst); 7139 rt = itype_rt (inst); 7140 return (is_octeon_bbit_op (op, gdbarch) 7141 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 7142 || op == 29 /* JALX: bits 011101 */ 7143 || (op == 17 7144 && (rs == 8 7145 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 7146 || (rs == 9 && (rt & 0x2) == 0) 7147 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ 7148 || (rs == 10 && (rt & 0x2) == 0)))); 7149 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ 7150 } 7151 else 7152 switch (op & 0x07) /* extract bits 28,27,26 */ 7153 { 7154 case 0: /* SPECIAL */ 7155 op = rtype_funct (inst); 7156 return (op == 8 /* JR */ 7157 || op == 9); /* JALR */ 7158 break; /* end SPECIAL */ 7159 case 1: /* REGIMM */ 7160 rs = itype_rs (inst); 7161 rt = itype_rt (inst); /* branch condition */ 7162 return ((rt & 0xc) == 0 7163 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ 7164 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ 7165 || ((rt & 0x1e) == 0x1c && rs == 0)); 7166 /* BPOSGE32, BPOSGE64: bits 1110x */ 7167 break; /* end REGIMM */ 7168 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ 7169 return 1; 7170 break; 7171 } 7172 } 7173 7174 /* Return non-zero if a standard MIPS instruction at ADDR has a branch 7175 delay slot (i.e. it is a jump or branch instruction). */ 7176 7177 static int 7178 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) 7179 { 7180 ULONGEST insn; 7181 int status; 7182 7183 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); 7184 if (status) 7185 return 0; 7186 7187 return mips32_instruction_has_delay_slot (gdbarch, insn); 7188 } 7189 7190 /* Return non-zero if the microMIPS instruction INSN, comprising the 7191 16-bit major opcode word in the high 16 bits and any second word 7192 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact 7193 jump or branch instruction). The instruction must be 32-bit if 7194 MUSTBE32 is set or can be any instruction otherwise. */ 7195 7196 static int 7197 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) 7198 { 7199 ULONGEST major = insn >> 16; 7200 7201 switch (micromips_op (major)) 7202 { 7203 /* 16-bit instructions. */ 7204 case 0x33: /* B16: bits 110011 */ 7205 case 0x2b: /* BNEZ16: bits 101011 */ 7206 case 0x23: /* BEQZ16: bits 100011 */ 7207 return !mustbe32; 7208 case 0x11: /* POOL16C: bits 010001 */ 7209 return (!mustbe32 7210 && ((b5s5_op (major) == 0xc 7211 /* JR16: bits 010001 01100 */ 7212 || (b5s5_op (major) & 0x1e) == 0xe))); 7213 /* JALR16, JALRS16: bits 010001 0111x */ 7214 /* 32-bit instructions. */ 7215 case 0x3d: /* JAL: bits 111101 */ 7216 case 0x3c: /* JALX: bits 111100 */ 7217 case 0x35: /* J: bits 110101 */ 7218 case 0x2d: /* BNE: bits 101101 */ 7219 case 0x25: /* BEQ: bits 100101 */ 7220 case 0x1d: /* JALS: bits 011101 */ 7221 return 1; 7222 case 0x10: /* POOL32I: bits 010000 */ 7223 return ((b5s5_op (major) & 0x1c) == 0x0 7224 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 7225 || (b5s5_op (major) & 0x1d) == 0x4 7226 /* BLEZ, BGTZ: bits 010000 001x0 */ 7227 || (b5s5_op (major) & 0x1d) == 0x11 7228 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 7229 || ((b5s5_op (major) & 0x1e) == 0x14 7230 && (major & 0x3) == 0x0) 7231 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 7232 || (b5s5_op (major) & 0x1e) == 0x1a 7233 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 7234 || ((b5s5_op (major) & 0x1e) == 0x1c 7235 && (major & 0x3) == 0x0) 7236 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 7237 || ((b5s5_op (major) & 0x1c) == 0x1c 7238 && (major & 0x3) == 0x1)); 7239 /* BC1ANY*: bits 010000 111xx xxx01 */ 7240 case 0x0: /* POOL32A: bits 000000 */ 7241 return (b0s6_op (insn) == 0x3c 7242 /* POOL32Axf: bits 000000 ... 111100 */ 7243 && (b6s10_ext (insn) & 0x2bf) == 0x3c); 7244 /* JALR, JALR.HB: 000000 000x111100 111100 */ 7245 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 7246 default: 7247 return 0; 7248 } 7249 } 7250 7251 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay 7252 slot (i.e. it is a non-compact jump instruction). The instruction 7253 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7254 7255 static int 7256 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7257 CORE_ADDR addr, int mustbe32) 7258 { 7259 ULONGEST insn; 7260 int status; 7261 int size; 7262 7263 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7264 if (status) 7265 return 0; 7266 size = mips_insn_size (ISA_MICROMIPS, insn); 7267 insn <<= 16; 7268 if (size == 2 * MIPS_INSN16_SIZE) 7269 { 7270 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7271 if (status) 7272 return 0; 7273 } 7274 7275 return micromips_instruction_has_delay_slot (insn, mustbe32); 7276 } 7277 7278 /* Return non-zero if the MIPS16 instruction INST, which must be 7279 a 32-bit instruction if MUSTBE32 is set or can be any instruction 7280 otherwise, has a branch delay slot (i.e. it is a non-compact jump 7281 instruction). This function is based on mips16_next_pc. */ 7282 7283 static int 7284 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) 7285 { 7286 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ 7287 return !mustbe32; 7288 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ 7289 } 7290 7291 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay 7292 slot (i.e. it is a non-compact jump instruction). The instruction 7293 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7294 7295 static int 7296 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7297 CORE_ADDR addr, int mustbe32) 7298 { 7299 unsigned short insn; 7300 int status; 7301 7302 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); 7303 if (status) 7304 return 0; 7305 7306 return mips16_instruction_has_delay_slot (insn, mustbe32); 7307 } 7308 7309 /* Calculate the starting address of the MIPS memory segment BPADDR is in. 7310 This assumes KSSEG exists. */ 7311 7312 static CORE_ADDR 7313 mips_segment_boundary (CORE_ADDR bpaddr) 7314 { 7315 CORE_ADDR mask = CORE_ADDR_MAX; 7316 int segsize; 7317 7318 if (sizeof (CORE_ADDR) == 8) 7319 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid 7320 a compiler warning produced where CORE_ADDR is a 32-bit type even 7321 though in that case this is dead code). */ 7322 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) 7323 { 7324 case 3: 7325 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) 7326 segsize = 29; /* 32-bit compatibility segment */ 7327 else 7328 segsize = 62; /* xkseg */ 7329 break; 7330 case 2: /* xkphys */ 7331 segsize = 59; 7332 break; 7333 default: /* xksseg (1), xkuseg/kuseg (0) */ 7334 segsize = 62; 7335 break; 7336 } 7337 else if (bpaddr & 0x80000000) /* kernel segment */ 7338 segsize = 29; 7339 else 7340 segsize = 31; /* user segment */ 7341 mask <<= segsize; 7342 return bpaddr & mask; 7343 } 7344 7345 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting 7346 it backwards if necessary. Return the address of the new location. */ 7347 7348 static CORE_ADDR 7349 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) 7350 { 7351 CORE_ADDR prev_addr; 7352 CORE_ADDR boundary; 7353 CORE_ADDR func_addr; 7354 7355 /* If a breakpoint is set on the instruction in a branch delay slot, 7356 GDB gets confused. When the breakpoint is hit, the PC isn't on 7357 the instruction in the branch delay slot, the PC will point to 7358 the branch instruction. Since the PC doesn't match any known 7359 breakpoints, GDB reports a trap exception. 7360 7361 There are two possible fixes for this problem. 7362 7363 1) When the breakpoint gets hit, see if the BD bit is set in the 7364 Cause register (which indicates the last exception occurred in a 7365 branch delay slot). If the BD bit is set, fix the PC to point to 7366 the instruction in the branch delay slot. 7367 7368 2) When the user sets the breakpoint, don't allow him to set the 7369 breakpoint on the instruction in the branch delay slot. Instead 7370 move the breakpoint to the branch instruction (which will have 7371 the same result). 7372 7373 The problem with the first solution is that if the user then 7374 single-steps the processor, the branch instruction will get 7375 skipped (since GDB thinks the PC is on the instruction in the 7376 branch delay slot). 7377 7378 So, we'll use the second solution. To do this we need to know if 7379 the instruction we're trying to set the breakpoint on is in the 7380 branch delay slot. */ 7381 7382 boundary = mips_segment_boundary (bpaddr); 7383 7384 /* Make sure we don't scan back before the beginning of the current 7385 function, since we may fetch constant data or insns that look like 7386 a jump. Of course we might do that anyway if the compiler has 7387 moved constants inline. :-( */ 7388 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) 7389 && func_addr > boundary && func_addr <= bpaddr) 7390 boundary = func_addr; 7391 7392 if (mips_pc_is_mips (bpaddr)) 7393 { 7394 if (bpaddr == boundary) 7395 return bpaddr; 7396 7397 /* If the previous instruction has a branch delay slot, we have 7398 to move the breakpoint to the branch instruction. */ 7399 prev_addr = bpaddr - 4; 7400 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) 7401 bpaddr = prev_addr; 7402 } 7403 else 7404 { 7405 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); 7406 CORE_ADDR addr, jmpaddr; 7407 int i; 7408 7409 boundary = unmake_compact_addr (boundary); 7410 7411 /* The only MIPS16 instructions with delay slots are JAL, JALX, 7412 JALR and JR. An absolute JAL/JALX is always 4 bytes long, 7413 so try for that first, then try the 2 byte JALR/JR. 7414 The microMIPS ASE has a whole range of jumps and branches 7415 with delay slots, some of which take 4 bytes and some take 7416 2 bytes, so the idea is the same. 7417 FIXME: We have to assume that bpaddr is not the second half 7418 of an extended instruction. */ 7419 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) 7420 ? micromips_insn_at_pc_has_delay_slot 7421 : mips16_insn_at_pc_has_delay_slot); 7422 7423 jmpaddr = 0; 7424 addr = bpaddr; 7425 for (i = 1; i < 4; i++) 7426 { 7427 if (unmake_compact_addr (addr) == boundary) 7428 break; 7429 addr -= MIPS_INSN16_SIZE; 7430 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) 7431 /* Looks like a JR/JALR at [target-1], but it could be 7432 the second word of a previous JAL/JALX, so record it 7433 and check back one more. */ 7434 jmpaddr = addr; 7435 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) 7436 { 7437 if (i == 2) 7438 /* Looks like a JAL/JALX at [target-2], but it could also 7439 be the second word of a previous JAL/JALX, record it, 7440 and check back one more. */ 7441 jmpaddr = addr; 7442 else 7443 /* Looks like a JAL/JALX at [target-3], so any previously 7444 recorded JAL/JALX or JR/JALR must be wrong, because: 7445 7446 >-3: JAL 7447 -2: JAL-ext (can't be JAL/JALX) 7448 -1: bdslot (can't be JR/JALR) 7449 0: target insn 7450 7451 Of course it could be another JAL-ext which looks 7452 like a JAL, but in that case we'd have broken out 7453 of this loop at [target-2]: 7454 7455 -4: JAL 7456 >-3: JAL-ext 7457 -2: bdslot (can't be jmp) 7458 -1: JR/JALR 7459 0: target insn */ 7460 jmpaddr = 0; 7461 } 7462 else 7463 { 7464 /* Not a jump instruction: if we're at [target-1] this 7465 could be the second word of a JAL/JALX, so continue; 7466 otherwise we're done. */ 7467 if (i > 1) 7468 break; 7469 } 7470 } 7471 7472 if (jmpaddr) 7473 bpaddr = jmpaddr; 7474 } 7475 7476 return bpaddr; 7477 } 7478 7479 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 7480 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ 7481 7482 static int 7483 mips_is_stub_suffix (const char *suffix, int zero) 7484 { 7485 switch (suffix[0]) 7486 { 7487 case '0': 7488 return zero && suffix[1] == '\0'; 7489 case '1': 7490 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); 7491 case '2': 7492 case '5': 7493 case '6': 7494 case '9': 7495 return suffix[1] == '\0'; 7496 default: 7497 return 0; 7498 } 7499 } 7500 7501 /* Return non-zero if MODE is one of the mode infixes used for MIPS16 7502 call stubs, one of sf, df, sc, or dc. */ 7503 7504 static int 7505 mips_is_stub_mode (const char *mode) 7506 { 7507 return ((mode[0] == 's' || mode[0] == 'd') 7508 && (mode[1] == 'f' || mode[1] == 'c')); 7509 } 7510 7511 /* Code at PC is a compiler-generated stub. Such a stub for a function 7512 bar might have a name like __fn_stub_bar, and might look like this: 7513 7514 mfc1 $4, $f13 7515 mfc1 $5, $f12 7516 mfc1 $6, $f15 7517 mfc1 $7, $f14 7518 7519 followed by (or interspersed with): 7520 7521 j bar 7522 7523 or: 7524 7525 lui $25, %hi(bar) 7526 addiu $25, $25, %lo(bar) 7527 jr $25 7528 7529 ($1 may be used in old code; for robustness we accept any register) 7530 or, in PIC code: 7531 7532 lui $28, %hi(_gp_disp) 7533 addiu $28, $28, %lo(_gp_disp) 7534 addu $28, $28, $25 7535 lw $25, %got(bar) 7536 addiu $25, $25, %lo(bar) 7537 jr $25 7538 7539 In the case of a __call_stub_bar stub, the sequence to set up 7540 arguments might look like this: 7541 7542 mtc1 $4, $f13 7543 mtc1 $5, $f12 7544 mtc1 $6, $f15 7545 mtc1 $7, $f14 7546 7547 followed by (or interspersed with) one of the jump sequences above. 7548 7549 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead 7550 of J or JR, respectively, followed by: 7551 7552 mfc1 $2, $f0 7553 mfc1 $3, $f1 7554 jr $18 7555 7556 We are at the beginning of the stub here, and scan down and extract 7557 the target address from the jump immediate instruction or, if a jump 7558 register instruction is used, from the register referred. Return 7559 the value of PC calculated or 0 if inconclusive. 7560 7561 The limit on the search is arbitrarily set to 20 instructions. FIXME. */ 7562 7563 static CORE_ADDR 7564 mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) 7565 { 7566 struct gdbarch *gdbarch = get_frame_arch (frame); 7567 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7568 int addrreg = MIPS_ZERO_REGNUM; 7569 CORE_ADDR start_pc = pc; 7570 CORE_ADDR target_pc = 0; 7571 CORE_ADDR addr = 0; 7572 CORE_ADDR gp = 0; 7573 int status = 0; 7574 int i; 7575 7576 for (i = 0; 7577 status == 0 && target_pc == 0 && i < 20; 7578 i++, pc += MIPS_INSN32_SIZE) 7579 { 7580 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 7581 CORE_ADDR imm; 7582 int rt; 7583 int rs; 7584 int rd; 7585 7586 switch (itype_op (inst)) 7587 { 7588 case 0: /* SPECIAL */ 7589 switch (rtype_funct (inst)) 7590 { 7591 case 8: /* JR */ 7592 case 9: /* JALR */ 7593 rs = rtype_rs (inst); 7594 if (rs == MIPS_GP_REGNUM) 7595 target_pc = gp; /* Hmm... */ 7596 else if (rs == addrreg) 7597 target_pc = addr; 7598 break; 7599 7600 case 0x21: /* ADDU */ 7601 rt = rtype_rt (inst); 7602 rs = rtype_rs (inst); 7603 rd = rtype_rd (inst); 7604 if (rd == MIPS_GP_REGNUM 7605 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) 7606 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) 7607 gp += start_pc; 7608 break; 7609 } 7610 break; 7611 7612 case 2: /* J */ 7613 case 3: /* JAL */ 7614 target_pc = jtype_target (inst) << 2; 7615 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 7616 break; 7617 7618 case 9: /* ADDIU */ 7619 rt = itype_rt (inst); 7620 rs = itype_rs (inst); 7621 if (rt == rs) 7622 { 7623 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7624 if (rt == MIPS_GP_REGNUM) 7625 gp += imm; 7626 else if (rt == addrreg) 7627 addr += imm; 7628 } 7629 break; 7630 7631 case 0xf: /* LUI */ 7632 rt = itype_rt (inst); 7633 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; 7634 if (rt == MIPS_GP_REGNUM) 7635 gp = imm; 7636 else if (rt != MIPS_ZERO_REGNUM) 7637 { 7638 addrreg = rt; 7639 addr = imm; 7640 } 7641 break; 7642 7643 case 0x23: /* LW */ 7644 rt = itype_rt (inst); 7645 rs = itype_rs (inst); 7646 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7647 if (gp != 0 && rs == MIPS_GP_REGNUM) 7648 { 7649 gdb_byte buf[4]; 7650 7651 memset (buf, 0, sizeof (buf)); 7652 status = target_read_memory (gp + imm, buf, sizeof (buf)); 7653 addrreg = rt; 7654 addr = extract_signed_integer (buf, sizeof (buf), byte_order); 7655 } 7656 break; 7657 } 7658 } 7659 7660 return target_pc; 7661 } 7662 7663 /* If PC is in a MIPS16 call or return stub, return the address of the 7664 target PC, which is either the callee or the caller. There are several 7665 cases which must be handled: 7666 7667 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7668 and the target PC is in $31 ($ra). 7669 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7670 and the target PC is in $2. 7671 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7672 i.e. before the JALR instruction, this is effectively a call stub 7673 and the target PC is in $2. Otherwise this is effectively 7674 a return stub and the target PC is in $18. 7675 * If the PC is at the start of __call_stub_fp_*, i.e. before the 7676 JAL or JALR instruction, this is effectively a call stub and the 7677 target PC is buried in the instruction stream. Otherwise this 7678 is effectively a return stub and the target PC is in $18. 7679 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call 7680 stub and the target PC is buried in the instruction stream. 7681 7682 See the source code for the stubs in gcc/config/mips/mips16.S, or the 7683 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the 7684 gory details. */ 7685 7686 static CORE_ADDR 7687 mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) 7688 { 7689 struct gdbarch *gdbarch = get_frame_arch (frame); 7690 CORE_ADDR start_addr; 7691 const char *name; 7692 size_t prefixlen; 7693 7694 /* Find the starting address and name of the function containing the PC. */ 7695 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 7696 return 0; 7697 7698 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7699 and the target PC is in $31 ($ra). */ 7700 prefixlen = strlen (mips_str_mips16_ret_stub); 7701 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7702 && mips_is_stub_mode (name + prefixlen) 7703 && name[prefixlen + 2] == '\0') 7704 return get_frame_register_signed 7705 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 7706 7707 /* If the PC is in __mips16_call_stub_*, this is one of the call 7708 call/return stubs. */ 7709 prefixlen = strlen (mips_str_mips16_call_stub); 7710 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) 7711 { 7712 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7713 and the target PC is in $2. */ 7714 if (mips_is_stub_suffix (name + prefixlen, 0)) 7715 return get_frame_register_signed 7716 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7717 7718 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7719 i.e. before the JALR instruction, this is effectively a call stub 7720 and the target PC is in $2. Otherwise this is effectively 7721 a return stub and the target PC is in $18. */ 7722 else if (mips_is_stub_mode (name + prefixlen) 7723 && name[prefixlen + 2] == '_' 7724 && mips_is_stub_suffix (name + prefixlen + 3, 0)) 7725 { 7726 if (pc == start_addr) 7727 /* This is the 'call' part of a call stub. The return 7728 address is in $2. */ 7729 return get_frame_register_signed 7730 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7731 else 7732 /* This is the 'return' part of a call stub. The return 7733 address is in $18. */ 7734 return get_frame_register_signed 7735 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7736 } 7737 else 7738 return 0; /* Not a stub. */ 7739 } 7740 7741 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the 7742 compiler-generated call or call/return stubs. */ 7743 if (startswith (name, mips_str_fn_stub) 7744 || startswith (name, mips_str_call_stub)) 7745 { 7746 if (pc == start_addr) 7747 /* This is the 'call' part of a call stub. Call this helper 7748 to scan through this code for interesting instructions 7749 and determine the final PC. */ 7750 return mips_get_mips16_fn_stub_pc (frame, pc); 7751 else 7752 /* This is the 'return' part of a call stub. The return address 7753 is in $18. */ 7754 return get_frame_register_signed 7755 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7756 } 7757 7758 return 0; /* Not a stub. */ 7759 } 7760 7761 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). 7762 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ 7763 7764 static int 7765 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) 7766 { 7767 CORE_ADDR start_addr; 7768 size_t prefixlen; 7769 7770 /* Find the starting address of the function containing the PC. */ 7771 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) 7772 return 0; 7773 7774 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at 7775 the start, i.e. after the JALR instruction, this is effectively 7776 a return stub. */ 7777 prefixlen = strlen (mips_str_mips16_call_stub); 7778 if (pc != start_addr 7779 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 7780 && mips_is_stub_mode (name + prefixlen) 7781 && name[prefixlen + 2] == '_' 7782 && mips_is_stub_suffix (name + prefixlen + 3, 1)) 7783 return 1; 7784 7785 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after 7786 the JAL or JALR instruction, this is effectively a return stub. */ 7787 prefixlen = strlen (mips_str_call_fp_stub); 7788 if (pc != start_addr 7789 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) 7790 return 1; 7791 7792 /* Consume the .pic. prefix of any PIC stub, this function must return 7793 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub 7794 or the call stub path will trigger in handle_inferior_event causing 7795 it to go astray. */ 7796 prefixlen = strlen (mips_str_pic); 7797 if (strncmp (name, mips_str_pic, prefixlen) == 0) 7798 name += prefixlen; 7799 7800 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ 7801 prefixlen = strlen (mips_str_mips16_ret_stub); 7802 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7803 && mips_is_stub_mode (name + prefixlen) 7804 && name[prefixlen + 2] == '\0') 7805 return 1; 7806 7807 return 0; /* Not a stub. */ 7808 } 7809 7810 /* If the current PC is the start of a non-PIC-to-PIC stub, return the 7811 PC of the stub target. The stub just loads $t9 and jumps to it, 7812 so that $t9 has the correct value at function entry. */ 7813 7814 static CORE_ADDR 7815 mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) 7816 { 7817 struct gdbarch *gdbarch = get_frame_arch (frame); 7818 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7819 struct bound_minimal_symbol msym; 7820 int i; 7821 gdb_byte stub_code[16]; 7822 int32_t stub_words[4]; 7823 7824 /* The stub for foo is named ".pic.foo", and is either two 7825 instructions inserted before foo or a three instruction sequence 7826 which jumps to foo. */ 7827 msym = lookup_minimal_symbol_by_pc (pc); 7828 if (msym.minsym == NULL 7829 || msym.value_address () != pc 7830 || msym.minsym->linkage_name () == NULL 7831 || !startswith (msym.minsym->linkage_name (), ".pic.")) 7832 return 0; 7833 7834 /* A two-instruction header. */ 7835 if (msym.minsym->size () == 8) 7836 return pc + 8; 7837 7838 /* A three-instruction (plus delay slot) trampoline. */ 7839 if (msym.minsym->size () == 16) 7840 { 7841 if (target_read_memory (pc, stub_code, 16) != 0) 7842 return 0; 7843 for (i = 0; i < 4; i++) 7844 stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 7845 4, byte_order); 7846 7847 /* A stub contains these instructions: 7848 lui t9, %hi(target) 7849 j target 7850 addiu t9, t9, %lo(target) 7851 nop 7852 7853 This works even for N64, since stubs are only generated with 7854 -msym32. */ 7855 if ((stub_words[0] & 0xffff0000U) == 0x3c190000 7856 && (stub_words[1] & 0xfc000000U) == 0x08000000 7857 && (stub_words[2] & 0xffff0000U) == 0x27390000 7858 && stub_words[3] == 0x00000000) 7859 return ((((stub_words[0] & 0x0000ffff) << 16) 7860 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; 7861 } 7862 7863 /* Not a recognized stub. */ 7864 return 0; 7865 } 7866 7867 static CORE_ADDR 7868 mips_skip_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) 7869 { 7870 CORE_ADDR requested_pc = pc; 7871 CORE_ADDR target_pc; 7872 CORE_ADDR new_pc; 7873 7874 do 7875 { 7876 target_pc = pc; 7877 7878 new_pc = mips_skip_mips16_trampoline_code (frame, pc); 7879 if (new_pc) 7880 pc = new_pc; 7881 7882 new_pc = find_solib_trampoline_target (frame, pc); 7883 if (new_pc) 7884 pc = new_pc; 7885 7886 new_pc = mips_skip_pic_trampoline_code (frame, pc); 7887 if (new_pc) 7888 pc = new_pc; 7889 } 7890 while (pc != target_pc); 7891 7892 return pc != requested_pc ? pc : 0; 7893 } 7894 7895 /* Convert a dbx stab register number (from `r' declaration) to a GDB 7896 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7897 7898 static int 7899 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) 7900 { 7901 int regnum; 7902 if (num >= 0 && num < 32) 7903 regnum = num; 7904 else if (num >= 38 && num < 70) 7905 regnum = num + mips_regnum (gdbarch)->fp0 - 38; 7906 else if (num == 70) 7907 regnum = mips_regnum (gdbarch)->hi; 7908 else if (num == 71) 7909 regnum = mips_regnum (gdbarch)->lo; 7910 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) 7911 regnum = num + mips_regnum (gdbarch)->dspacc - 72; 7912 else 7913 return -1; 7914 return gdbarch_num_regs (gdbarch) + regnum; 7915 } 7916 7917 7918 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * 7919 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7920 7921 static int 7922 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) 7923 { 7924 int regnum; 7925 if (num >= 0 && num < 32) 7926 regnum = num; 7927 else if (num >= 32 && num < 64) 7928 regnum = num + mips_regnum (gdbarch)->fp0 - 32; 7929 else if (num == 64) 7930 regnum = mips_regnum (gdbarch)->hi; 7931 else if (num == 65) 7932 regnum = mips_regnum (gdbarch)->lo; 7933 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) 7934 regnum = num + mips_regnum (gdbarch)->dspacc - 66; 7935 else 7936 return -1; 7937 return gdbarch_num_regs (gdbarch) + regnum; 7938 } 7939 7940 static int 7941 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) 7942 { 7943 /* Only makes sense to supply raw registers. */ 7944 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); 7945 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to 7946 decide if it is valid. Should instead define a standard sim/gdb 7947 register numbering scheme. */ 7948 if (gdbarch_register_name (gdbarch, 7949 gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') 7950 return regnum; 7951 else 7952 return LEGACY_SIM_REGNO_IGNORE; 7953 } 7954 7955 7956 /* Convert an integer into an address. Extracting the value signed 7957 guarantees a correctly sign extended address. */ 7958 7959 static CORE_ADDR 7960 mips_integer_to_address (struct gdbarch *gdbarch, 7961 struct type *type, const gdb_byte *buf) 7962 { 7963 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7964 return extract_signed_integer (buf, type->length (), byte_order); 7965 } 7966 7967 /* Dummy virtual frame pointer method. This is no more or less accurate 7968 than most other architectures; we just need to be explicit about it, 7969 because the pseudo-register gdbarch_sp_regnum will otherwise lead to 7970 an assertion failure. */ 7971 7972 static void 7973 mips_virtual_frame_pointer (struct gdbarch *gdbarch, 7974 CORE_ADDR pc, int *reg, LONGEST *offset) 7975 { 7976 *reg = MIPS_SP_REGNUM; 7977 *offset = 0; 7978 } 7979 7980 static void 7981 mips_find_abi_section (bfd *abfd, asection *sect, void *obj) 7982 { 7983 enum mips_abi *abip = (enum mips_abi *) obj; 7984 const char *name = bfd_section_name (sect); 7985 7986 if (*abip != MIPS_ABI_UNKNOWN) 7987 return; 7988 7989 if (!startswith (name, ".mdebug.")) 7990 return; 7991 7992 if (strcmp (name, ".mdebug.abi32") == 0) 7993 *abip = MIPS_ABI_O32; 7994 else if (strcmp (name, ".mdebug.abiN32") == 0) 7995 *abip = MIPS_ABI_N32; 7996 else if (strcmp (name, ".mdebug.abi64") == 0) 7997 *abip = MIPS_ABI_N64; 7998 else if (strcmp (name, ".mdebug.abiO64") == 0) 7999 *abip = MIPS_ABI_O64; 8000 else if (strcmp (name, ".mdebug.eabi32") == 0) 8001 *abip = MIPS_ABI_EABI32; 8002 else if (strcmp (name, ".mdebug.eabi64") == 0) 8003 *abip = MIPS_ABI_EABI64; 8004 else 8005 warning (_("unsupported ABI %s."), name + 8); 8006 } 8007 8008 static void 8009 mips_find_long_section (bfd *abfd, asection *sect, void *obj) 8010 { 8011 int *lbp = (int *) obj; 8012 const char *name = bfd_section_name (sect); 8013 8014 if (startswith (name, ".gcc_compiled_long32")) 8015 *lbp = 32; 8016 else if (startswith (name, ".gcc_compiled_long64")) 8017 *lbp = 64; 8018 else if (startswith (name, ".gcc_compiled_long")) 8019 warning (_("unrecognized .gcc_compiled_longXX")); 8020 } 8021 8022 static enum mips_abi 8023 global_mips_abi (void) 8024 { 8025 int i; 8026 8027 for (i = 0; mips_abi_strings[i] != NULL; i++) 8028 if (mips_abi_strings[i] == mips_abi_string) 8029 return (enum mips_abi) i; 8030 8031 internal_error (_("unknown ABI string")); 8032 } 8033 8034 /* Return the default compressed instruction set, either of MIPS16 8035 or microMIPS, selected when none could have been determined from 8036 the ELF header of the binary being executed (or no binary has been 8037 selected. */ 8038 8039 static enum mips_isa 8040 global_mips_compression (void) 8041 { 8042 int i; 8043 8044 for (i = 0; mips_compression_strings[i] != NULL; i++) 8045 if (mips_compression_strings[i] == mips_compression_string) 8046 return (enum mips_isa) i; 8047 8048 internal_error (_("unknown compressed ISA string")); 8049 } 8050 8051 static void 8052 mips_register_g_packet_guesses (struct gdbarch *gdbarch) 8053 { 8054 /* If the size matches the set of 32-bit or 64-bit integer registers, 8055 assume that's what we've got. */ 8056 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); 8057 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); 8058 8059 /* If the size matches the full set of registers GDB traditionally 8060 knows about, including floating point, for either 32-bit or 8061 64-bit, assume that's what we've got. */ 8062 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); 8063 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); 8064 8065 /* Otherwise we don't have a useful guess. */ 8066 } 8067 8068 static struct value * 8069 value_of_mips_user_reg (frame_info_ptr frame, const void *baton) 8070 { 8071 const int *reg_p = (const int *) baton; 8072 return value_of_register (*reg_p, frame); 8073 } 8074 8075 static struct gdbarch * 8076 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 8077 { 8078 struct gdbarch *gdbarch; 8079 int elf_flags; 8080 enum mips_abi mips_abi, found_abi, wanted_abi; 8081 int i, num_regs; 8082 enum mips_fpu_type fpu_type; 8083 tdesc_arch_data_up tdesc_data; 8084 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; 8085 const char * const *reg_names; 8086 struct mips_regnum mips_regnum, *regnum; 8087 enum mips_isa mips_isa; 8088 int dspacc; 8089 int dspctl; 8090 8091 /* First of all, extract the elf_flags, if available. */ 8092 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8093 elf_flags = elf_elfheader (info.abfd)->e_flags; 8094 else if (arches != NULL) 8095 { 8096 mips_gdbarch_tdep *tdep 8097 = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); 8098 elf_flags = tdep->elf_flags; 8099 } 8100 else 8101 elf_flags = 0; 8102 if (gdbarch_debug) 8103 gdb_printf (gdb_stdlog, 8104 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); 8105 8106 /* Check ELF_FLAGS to see if it specifies the ABI being used. */ 8107 switch ((elf_flags & EF_MIPS_ABI)) 8108 { 8109 case E_MIPS_ABI_O32: 8110 found_abi = MIPS_ABI_O32; 8111 break; 8112 case E_MIPS_ABI_O64: 8113 found_abi = MIPS_ABI_O64; 8114 break; 8115 case E_MIPS_ABI_EABI32: 8116 found_abi = MIPS_ABI_EABI32; 8117 break; 8118 case E_MIPS_ABI_EABI64: 8119 found_abi = MIPS_ABI_EABI64; 8120 break; 8121 default: 8122 if ((elf_flags & EF_MIPS_ABI2)) 8123 found_abi = MIPS_ABI_N32; 8124 else 8125 found_abi = MIPS_ABI_UNKNOWN; 8126 break; 8127 } 8128 8129 /* GCC creates a pseudo-section whose name describes the ABI. */ 8130 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) 8131 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); 8132 8133 /* If we have no useful BFD information, use the ABI from the last 8134 MIPS architecture (if there is one). */ 8135 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) 8136 { 8137 mips_gdbarch_tdep *tdep 8138 = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); 8139 found_abi = tdep->found_abi; 8140 } 8141 8142 /* Try the architecture for any hint of the correct ABI. */ 8143 if (found_abi == MIPS_ABI_UNKNOWN 8144 && info.bfd_arch_info != NULL 8145 && info.bfd_arch_info->arch == bfd_arch_mips) 8146 { 8147 switch (info.bfd_arch_info->mach) 8148 { 8149 case bfd_mach_mips3900: 8150 found_abi = MIPS_ABI_EABI32; 8151 break; 8152 case bfd_mach_mips4100: 8153 case bfd_mach_mips5000: 8154 found_abi = MIPS_ABI_EABI64; 8155 break; 8156 case bfd_mach_mips8000: 8157 case bfd_mach_mips10000: 8158 /* On Irix, ELF64 executables use the N64 ABI. The 8159 pseudo-sections which describe the ABI aren't present 8160 on IRIX. (Even for executables created by gcc.) */ 8161 if (info.abfd != NULL 8162 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8163 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8164 found_abi = MIPS_ABI_N64; 8165 else 8166 found_abi = MIPS_ABI_N32; 8167 break; 8168 } 8169 } 8170 8171 /* Default 64-bit objects to N64 instead of O32. */ 8172 if (found_abi == MIPS_ABI_UNKNOWN 8173 && info.abfd != NULL 8174 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8175 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8176 found_abi = MIPS_ABI_N64; 8177 8178 if (gdbarch_debug) 8179 gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", 8180 found_abi); 8181 8182 /* What has the user specified from the command line? */ 8183 wanted_abi = global_mips_abi (); 8184 if (gdbarch_debug) 8185 gdb_printf (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", 8186 wanted_abi); 8187 8188 /* Now that we have found what the ABI for this binary would be, 8189 check whether the user is overriding it. */ 8190 if (wanted_abi != MIPS_ABI_UNKNOWN) 8191 mips_abi = wanted_abi; 8192 else if (found_abi != MIPS_ABI_UNKNOWN) 8193 mips_abi = found_abi; 8194 else 8195 mips_abi = MIPS_ABI_O32; 8196 if (gdbarch_debug) 8197 gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", 8198 mips_abi); 8199 8200 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ 8201 if (mips_abi != MIPS_ABI_EABI32 8202 && mips_abi != MIPS_ABI_O32 8203 && info.bfd_arch_info != NULL 8204 && info.bfd_arch_info->arch == bfd_arch_mips 8205 && info.bfd_arch_info->bits_per_word < 64) 8206 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); 8207 8208 /* Determine the default compressed ISA. */ 8209 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 8210 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) 8211 mips_isa = ISA_MICROMIPS; 8212 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 8213 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) 8214 mips_isa = ISA_MIPS16; 8215 else 8216 mips_isa = global_mips_compression (); 8217 mips_compression_string = mips_compression_strings[mips_isa]; 8218 8219 /* Also used when doing an architecture lookup. */ 8220 if (gdbarch_debug) 8221 gdb_printf (gdb_stdlog, 8222 "mips_gdbarch_init: " 8223 "mips64_transfers_32bit_regs_p = %d\n", 8224 mips64_transfers_32bit_regs_p); 8225 8226 /* Determine the MIPS FPU type. */ 8227 #ifdef HAVE_ELF 8228 if (info.abfd 8229 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8230 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8231 Tag_GNU_MIPS_ABI_FP); 8232 #endif /* HAVE_ELF */ 8233 8234 if (!mips_fpu_type_auto) 8235 fpu_type = mips_fpu_type; 8236 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) 8237 { 8238 switch (elf_fpu_type) 8239 { 8240 case Val_GNU_MIPS_ABI_FP_DOUBLE: 8241 fpu_type = MIPS_FPU_DOUBLE; 8242 break; 8243 case Val_GNU_MIPS_ABI_FP_SINGLE: 8244 fpu_type = MIPS_FPU_SINGLE; 8245 break; 8246 case Val_GNU_MIPS_ABI_FP_SOFT: 8247 default: 8248 /* Soft float or unknown. */ 8249 fpu_type = MIPS_FPU_NONE; 8250 break; 8251 } 8252 } 8253 else if (info.bfd_arch_info != NULL 8254 && info.bfd_arch_info->arch == bfd_arch_mips) 8255 switch (info.bfd_arch_info->mach) 8256 { 8257 case bfd_mach_mips3900: 8258 case bfd_mach_mips4100: 8259 case bfd_mach_mips4111: 8260 case bfd_mach_mips4120: 8261 fpu_type = MIPS_FPU_NONE; 8262 break; 8263 case bfd_mach_mips4650: 8264 fpu_type = MIPS_FPU_SINGLE; 8265 break; 8266 default: 8267 fpu_type = MIPS_FPU_DOUBLE; 8268 break; 8269 } 8270 else if (arches != NULL) 8271 fpu_type = mips_get_fpu_type (arches->gdbarch); 8272 else 8273 fpu_type = MIPS_FPU_DOUBLE; 8274 if (gdbarch_debug) 8275 gdb_printf (gdb_stdlog, 8276 "mips_gdbarch_init: fpu_type = %d\n", fpu_type); 8277 8278 /* Check for blatant incompatibilities. */ 8279 8280 /* If we have only 32-bit registers, then we can't debug a 64-bit 8281 ABI. */ 8282 if (info.target_desc 8283 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL 8284 && mips_abi != MIPS_ABI_EABI32 8285 && mips_abi != MIPS_ABI_O32) 8286 return NULL; 8287 8288 /* Fill in the OS dependent register numbers and names. */ 8289 if (info.osabi == GDB_OSABI_LINUX) 8290 { 8291 mips_regnum.fp0 = 38; 8292 mips_regnum.pc = 37; 8293 mips_regnum.cause = 36; 8294 mips_regnum.badvaddr = 35; 8295 mips_regnum.hi = 34; 8296 mips_regnum.lo = 33; 8297 mips_regnum.fp_control_status = 70; 8298 mips_regnum.fp_implementation_revision = 71; 8299 mips_regnum.dspacc = -1; 8300 mips_regnum.dspctl = -1; 8301 dspacc = 72; 8302 dspctl = 78; 8303 num_regs = 90; 8304 reg_names = mips_linux_reg_names; 8305 } 8306 else 8307 { 8308 mips_regnum.lo = MIPS_EMBED_LO_REGNUM; 8309 mips_regnum.hi = MIPS_EMBED_HI_REGNUM; 8310 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; 8311 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; 8312 mips_regnum.pc = MIPS_EMBED_PC_REGNUM; 8313 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; 8314 mips_regnum.fp_control_status = 70; 8315 mips_regnum.fp_implementation_revision = 71; 8316 mips_regnum.dspacc = dspacc = -1; 8317 mips_regnum.dspctl = dspctl = -1; 8318 num_regs = MIPS_LAST_EMBED_REGNUM + 1; 8319 if (info.bfd_arch_info != NULL 8320 && info.bfd_arch_info->mach == bfd_mach_mips3900) 8321 reg_names = mips_tx39_reg_names; 8322 else 8323 reg_names = mips_generic_reg_names; 8324 } 8325 8326 /* Check any target description for validity. */ 8327 if (tdesc_has_registers (info.target_desc)) 8328 { 8329 static const char *const mips_gprs[] = { 8330 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8331 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8332 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8333 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 8334 }; 8335 static const char *const mips_fprs[] = { 8336 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 8337 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 8338 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 8339 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 8340 }; 8341 8342 const struct tdesc_feature *feature; 8343 int valid_p; 8344 8345 feature = tdesc_find_feature (info.target_desc, 8346 "org.gnu.gdb.mips.cpu"); 8347 if (feature == NULL) 8348 return NULL; 8349 8350 tdesc_data = tdesc_data_alloc (); 8351 8352 valid_p = 1; 8353 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) 8354 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, 8355 mips_gprs[i]); 8356 8357 8358 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8359 mips_regnum.lo, "lo"); 8360 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8361 mips_regnum.hi, "hi"); 8362 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8363 mips_regnum.pc, "pc"); 8364 8365 if (!valid_p) 8366 return NULL; 8367 8368 feature = tdesc_find_feature (info.target_desc, 8369 "org.gnu.gdb.mips.cp0"); 8370 if (feature == NULL) 8371 return NULL; 8372 8373 valid_p = 1; 8374 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8375 mips_regnum.badvaddr, "badvaddr"); 8376 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8377 MIPS_PS_REGNUM, "status"); 8378 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8379 mips_regnum.cause, "cause"); 8380 8381 if (!valid_p) 8382 return NULL; 8383 8384 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS 8385 backend is not prepared for that, though. */ 8386 feature = tdesc_find_feature (info.target_desc, 8387 "org.gnu.gdb.mips.fpu"); 8388 if (feature == NULL) 8389 return NULL; 8390 8391 valid_p = 1; 8392 for (i = 0; i < 32; i++) 8393 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8394 i + mips_regnum.fp0, mips_fprs[i]); 8395 8396 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8397 mips_regnum.fp_control_status, 8398 "fcsr"); 8399 valid_p 8400 &= tdesc_numbered_register (feature, tdesc_data.get (), 8401 mips_regnum.fp_implementation_revision, 8402 "fir"); 8403 8404 if (!valid_p) 8405 return NULL; 8406 8407 num_regs = mips_regnum.fp_implementation_revision + 1; 8408 8409 if (dspacc >= 0) 8410 { 8411 feature = tdesc_find_feature (info.target_desc, 8412 "org.gnu.gdb.mips.dsp"); 8413 /* The DSP registers are optional; it's OK if they are absent. */ 8414 if (feature != NULL) 8415 { 8416 i = 0; 8417 valid_p = 1; 8418 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8419 dspacc + i++, "hi1"); 8420 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8421 dspacc + i++, "lo1"); 8422 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8423 dspacc + i++, "hi2"); 8424 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8425 dspacc + i++, "lo2"); 8426 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8427 dspacc + i++, "hi3"); 8428 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8429 dspacc + i++, "lo3"); 8430 8431 valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), 8432 dspctl, "dspctl"); 8433 8434 if (!valid_p) 8435 return NULL; 8436 8437 mips_regnum.dspacc = dspacc; 8438 mips_regnum.dspctl = dspctl; 8439 8440 num_regs = mips_regnum.dspctl + 1; 8441 } 8442 } 8443 8444 /* It would be nice to detect an attempt to use a 64-bit ABI 8445 when only 32-bit registers are provided. */ 8446 reg_names = NULL; 8447 } 8448 8449 /* Try to find a pre-existing architecture. */ 8450 for (arches = gdbarch_list_lookup_by_info (arches, &info); 8451 arches != NULL; 8452 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 8453 { 8454 mips_gdbarch_tdep *tdep 8455 = gdbarch_tdep<mips_gdbarch_tdep> (arches->gdbarch); 8456 8457 /* MIPS needs to be pedantic about which ABI and the compressed 8458 ISA variation the object is using. */ 8459 if (tdep->elf_flags != elf_flags) 8460 continue; 8461 if (tdep->mips_abi != mips_abi) 8462 continue; 8463 if (tdep->mips_isa != mips_isa) 8464 continue; 8465 /* Need to be pedantic about which register virtual size is 8466 used. */ 8467 if (tdep->mips64_transfers_32bit_regs_p 8468 != mips64_transfers_32bit_regs_p) 8469 continue; 8470 /* Be pedantic about which FPU is selected. */ 8471 if (mips_get_fpu_type (arches->gdbarch) != fpu_type) 8472 continue; 8473 8474 return arches->gdbarch; 8475 } 8476 8477 /* Need a new architecture. Fill in a target specific vector. */ 8478 mips_gdbarch_tdep *tdep = new mips_gdbarch_tdep; 8479 gdbarch = gdbarch_alloc (&info, tdep); 8480 tdep->elf_flags = elf_flags; 8481 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; 8482 tdep->found_abi = found_abi; 8483 tdep->mips_abi = mips_abi; 8484 tdep->mips_isa = mips_isa; 8485 tdep->mips_fpu_type = fpu_type; 8486 tdep->register_size_valid_p = 0; 8487 tdep->register_size = 0; 8488 8489 if (info.target_desc) 8490 { 8491 /* Some useful properties can be inferred from the target. */ 8492 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) 8493 { 8494 tdep->register_size_valid_p = 1; 8495 tdep->register_size = 4; 8496 } 8497 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) 8498 { 8499 tdep->register_size_valid_p = 1; 8500 tdep->register_size = 8; 8501 } 8502 } 8503 8504 /* Initially set everything according to the default ABI/ISA. */ 8505 set_gdbarch_short_bit (gdbarch, 16); 8506 set_gdbarch_int_bit (gdbarch, 32); 8507 set_gdbarch_float_bit (gdbarch, 32); 8508 set_gdbarch_double_bit (gdbarch, 64); 8509 set_gdbarch_long_double_bit (gdbarch, 64); 8510 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); 8511 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); 8512 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); 8513 8514 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8515 mips_ax_pseudo_register_collect); 8516 set_gdbarch_ax_pseudo_register_push_stack 8517 (gdbarch, mips_ax_pseudo_register_push_stack); 8518 8519 set_gdbarch_elf_make_msymbol_special (gdbarch, 8520 mips_elf_make_msymbol_special); 8521 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); 8522 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); 8523 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); 8524 8525 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); 8526 *regnum = mips_regnum; 8527 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); 8528 set_gdbarch_num_regs (gdbarch, num_regs); 8529 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8530 set_gdbarch_register_name (gdbarch, mips_register_name); 8531 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); 8532 tdep->mips_processor_reg_names = reg_names; 8533 tdep->regnum = regnum; 8534 8535 switch (mips_abi) 8536 { 8537 case MIPS_ABI_O32: 8538 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); 8539 set_gdbarch_return_value (gdbarch, mips_o32_return_value); 8540 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8541 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8542 tdep->default_mask_address_p = 0; 8543 set_gdbarch_long_bit (gdbarch, 32); 8544 set_gdbarch_ptr_bit (gdbarch, 32); 8545 set_gdbarch_long_long_bit (gdbarch, 64); 8546 break; 8547 case MIPS_ABI_O64: 8548 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); 8549 set_gdbarch_return_value (gdbarch, mips_o64_return_value); 8550 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8551 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8552 tdep->default_mask_address_p = 0; 8553 set_gdbarch_long_bit (gdbarch, 32); 8554 set_gdbarch_ptr_bit (gdbarch, 32); 8555 set_gdbarch_long_long_bit (gdbarch, 64); 8556 break; 8557 case MIPS_ABI_EABI32: 8558 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8559 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8560 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8561 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8562 tdep->default_mask_address_p = 0; 8563 set_gdbarch_long_bit (gdbarch, 32); 8564 set_gdbarch_ptr_bit (gdbarch, 32); 8565 set_gdbarch_long_long_bit (gdbarch, 64); 8566 break; 8567 case MIPS_ABI_EABI64: 8568 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8569 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8570 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8571 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8572 tdep->default_mask_address_p = 0; 8573 set_gdbarch_long_bit (gdbarch, 64); 8574 set_gdbarch_ptr_bit (gdbarch, 64); 8575 set_gdbarch_long_long_bit (gdbarch, 64); 8576 break; 8577 case MIPS_ABI_N32: 8578 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8579 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8580 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8581 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8582 tdep->default_mask_address_p = 0; 8583 set_gdbarch_long_bit (gdbarch, 32); 8584 set_gdbarch_ptr_bit (gdbarch, 32); 8585 set_gdbarch_long_long_bit (gdbarch, 64); 8586 set_gdbarch_long_double_bit (gdbarch, 128); 8587 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8588 break; 8589 case MIPS_ABI_N64: 8590 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8591 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8592 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8593 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8594 tdep->default_mask_address_p = 0; 8595 set_gdbarch_long_bit (gdbarch, 64); 8596 set_gdbarch_ptr_bit (gdbarch, 64); 8597 set_gdbarch_long_long_bit (gdbarch, 64); 8598 set_gdbarch_long_double_bit (gdbarch, 128); 8599 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8600 break; 8601 default: 8602 internal_error (_("unknown ABI in switch")); 8603 } 8604 8605 /* GCC creates a pseudo-section whose name specifies the size of 8606 longs, since -mlong32 or -mlong64 may be used independent of 8607 other options. How those options affect pointer sizes is ABI and 8608 architecture dependent, so use them to override the default sizes 8609 set by the ABI. This table shows the relationship between ABI, 8610 -mlongXX, and size of pointers: 8611 8612 ABI -mlongXX ptr bits 8613 --- -------- -------- 8614 o32 32 32 8615 o32 64 32 8616 n32 32 32 8617 n32 64 64 8618 o64 32 32 8619 o64 64 64 8620 n64 32 32 8621 n64 64 64 8622 eabi32 32 32 8623 eabi32 64 32 8624 eabi64 32 32 8625 eabi64 64 64 8626 8627 Note that for o32 and eabi32, pointers are always 32 bits 8628 regardless of any -mlongXX option. For all others, pointers and 8629 longs are the same, as set by -mlongXX or set by defaults. */ 8630 8631 if (info.abfd != NULL) 8632 { 8633 int long_bit = 0; 8634 8635 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); 8636 if (long_bit) 8637 { 8638 set_gdbarch_long_bit (gdbarch, long_bit); 8639 switch (mips_abi) 8640 { 8641 case MIPS_ABI_O32: 8642 case MIPS_ABI_EABI32: 8643 break; 8644 case MIPS_ABI_N32: 8645 case MIPS_ABI_O64: 8646 case MIPS_ABI_N64: 8647 case MIPS_ABI_EABI64: 8648 set_gdbarch_ptr_bit (gdbarch, long_bit); 8649 break; 8650 default: 8651 internal_error (_("unknown ABI in switch")); 8652 } 8653 } 8654 } 8655 8656 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE 8657 that could indicate -gp32 BUT gas/config/tc-mips.c contains the 8658 comment: 8659 8660 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE 8661 flag in object files because to do so would make it impossible to 8662 link with libraries compiled without "-gp32". This is 8663 unnecessarily restrictive. 8664 8665 We could solve this problem by adding "-gp32" multilibs to gcc, 8666 but to set this flag before gcc is built with such multilibs will 8667 break too many systems.'' 8668 8669 But even more unhelpfully, the default linker output target for 8670 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even 8671 for 64-bit programs - you need to change the ABI to change this, 8672 and not all gcc targets support that currently. Therefore using 8673 this flag to detect 32-bit mode would do the wrong thing given 8674 the current gcc - it would make GDB treat these 64-bit programs 8675 as 32-bit programs by default. */ 8676 8677 set_gdbarch_read_pc (gdbarch, mips_read_pc); 8678 set_gdbarch_write_pc (gdbarch, mips_write_pc); 8679 8680 /* Add/remove bits from an address. The MIPS needs be careful to 8681 ensure that all 32 bit addresses are sign extended to 64 bits. */ 8682 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); 8683 8684 /* Unwind the frame. */ 8685 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); 8686 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); 8687 set_gdbarch_dummy_id (gdbarch, mips_dummy_id); 8688 8689 /* Map debug register numbers onto internal register numbers. */ 8690 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); 8691 set_gdbarch_ecoff_reg_to_regnum (gdbarch, 8692 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8693 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, 8694 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8695 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); 8696 8697 /* MIPS version of CALL_DUMMY. */ 8698 8699 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 8700 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); 8701 set_gdbarch_frame_align (gdbarch, mips_frame_align); 8702 8703 set_gdbarch_print_float_info (gdbarch, mips_print_float_info); 8704 8705 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); 8706 set_gdbarch_register_to_value (gdbarch, mips_register_to_value); 8707 set_gdbarch_value_to_register (gdbarch, mips_value_to_register); 8708 8709 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8710 set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); 8711 set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); 8712 set_gdbarch_adjust_breakpoint_address (gdbarch, 8713 mips_adjust_breakpoint_address); 8714 8715 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); 8716 8717 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); 8718 8719 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); 8720 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); 8721 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); 8722 8723 set_gdbarch_register_type (gdbarch, mips_register_type); 8724 8725 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); 8726 8727 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); 8728 if (mips_abi == MIPS_ABI_N64) 8729 set_gdbarch_disassembler_options_implicit 8730 (gdbarch, (const char *) mips_disassembler_options_n64); 8731 else if (mips_abi == MIPS_ABI_N32) 8732 set_gdbarch_disassembler_options_implicit 8733 (gdbarch, (const char *) mips_disassembler_options_n32); 8734 else 8735 set_gdbarch_disassembler_options_implicit 8736 (gdbarch, (const char *) mips_disassembler_options_o32); 8737 set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); 8738 set_gdbarch_valid_disassembler_options (gdbarch, 8739 disassembler_options_mips ()); 8740 8741 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, 8742 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint 8743 need to all be folded into the target vector. Since they are 8744 being used as guards for target_stopped_by_watchpoint, why not have 8745 target_stopped_by_watchpoint return the type of watchpoint that the code 8746 is sitting on? */ 8747 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 8748 8749 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); 8750 8751 /* NOTE drow/2012-04-25: We overload the core solib trampoline code 8752 to support MIPS16. This is a bad thing. Make sure not to do it 8753 if we have an OS ABI that actually supports shared libraries, since 8754 shared library support is more important. If we have an OS someday 8755 that supports both shared libraries and MIPS16, we'll have to find 8756 a better place for these. 8757 macro/2012-04-25: But that applies to return trampolines only and 8758 currently no MIPS OS ABI uses shared libraries that have them. */ 8759 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); 8760 8761 set_gdbarch_single_step_through_delay (gdbarch, 8762 mips_single_step_through_delay); 8763 8764 /* Virtual tables. */ 8765 set_gdbarch_vbit_in_delta (gdbarch, 1); 8766 8767 mips_register_g_packet_guesses (gdbarch); 8768 8769 /* Hook in OS ABI-specific overrides, if they have been registered. */ 8770 info.tdesc_data = tdesc_data.get (); 8771 gdbarch_init_osabi (info, gdbarch); 8772 8773 /* The hook may have adjusted num_regs, fetch the final value and 8774 set pc_regnum and sp_regnum now that it has been fixed. */ 8775 num_regs = gdbarch_num_regs (gdbarch); 8776 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); 8777 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8778 8779 /* Unwind the frame. */ 8780 dwarf2_append_unwinders (gdbarch); 8781 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); 8782 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); 8783 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); 8784 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); 8785 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); 8786 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); 8787 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); 8788 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); 8789 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); 8790 8791 if (tdesc_data != nullptr) 8792 { 8793 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); 8794 tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data)); 8795 8796 /* Override the normal target description methods to handle our 8797 dual real and pseudo registers. */ 8798 set_gdbarch_register_name (gdbarch, mips_register_name); 8799 set_gdbarch_register_reggroup_p (gdbarch, 8800 mips_tdesc_register_reggroup_p); 8801 8802 num_regs = gdbarch_num_regs (gdbarch); 8803 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8804 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); 8805 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8806 } 8807 8808 /* Add ABI-specific aliases for the registers. */ 8809 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) 8810 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) 8811 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, 8812 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); 8813 else 8814 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) 8815 user_reg_add (gdbarch, mips_o32_aliases[i].name, 8816 value_of_mips_user_reg, &mips_o32_aliases[i].regnum); 8817 8818 /* Add some other standard aliases. */ 8819 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) 8820 user_reg_add (gdbarch, mips_register_aliases[i].name, 8821 value_of_mips_user_reg, &mips_register_aliases[i].regnum); 8822 8823 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) 8824 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, 8825 value_of_mips_user_reg, 8826 &mips_numeric_register_aliases[i].regnum); 8827 8828 return gdbarch; 8829 } 8830 8831 static void 8832 mips_abi_update (const char *ignore_args, 8833 int from_tty, struct cmd_list_element *c) 8834 { 8835 struct gdbarch_info info; 8836 8837 /* Force the architecture to update, and (if it's a MIPS architecture) 8838 mips_gdbarch_init will take care of the rest. */ 8839 gdbarch_update_p (info); 8840 } 8841 8842 /* Print out which MIPS ABI is in use. */ 8843 8844 static void 8845 show_mips_abi (struct ui_file *file, 8846 int from_tty, 8847 struct cmd_list_element *ignored_cmd, 8848 const char *ignored_value) 8849 { 8850 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 8851 gdb_printf 8852 (file, 8853 "The MIPS ABI is unknown because the current architecture " 8854 "is not MIPS.\n"); 8855 else 8856 { 8857 enum mips_abi global_abi = global_mips_abi (); 8858 enum mips_abi actual_abi = mips_abi (target_gdbarch ()); 8859 const char *actual_abi_str = mips_abi_strings[actual_abi]; 8860 8861 if (global_abi == MIPS_ABI_UNKNOWN) 8862 gdb_printf 8863 (file, 8864 "The MIPS ABI is set automatically (currently \"%s\").\n", 8865 actual_abi_str); 8866 else if (global_abi == actual_abi) 8867 gdb_printf 8868 (file, 8869 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", 8870 actual_abi_str); 8871 else 8872 { 8873 /* Probably shouldn't happen... */ 8874 gdb_printf (file, 8875 "The (auto detected) MIPS ABI \"%s\" is in use " 8876 "even though the user setting was \"%s\".\n", 8877 actual_abi_str, mips_abi_strings[global_abi]); 8878 } 8879 } 8880 } 8881 8882 /* Print out which MIPS compressed ISA encoding is used. */ 8883 8884 static void 8885 show_mips_compression (struct ui_file *file, int from_tty, 8886 struct cmd_list_element *c, const char *value) 8887 { 8888 gdb_printf (file, _("The compressed ISA encoding used is %s.\n"), 8889 value); 8890 } 8891 8892 /* Return a textual name for MIPS FPU type FPU_TYPE. */ 8893 8894 static const char * 8895 mips_fpu_type_str (enum mips_fpu_type fpu_type) 8896 { 8897 switch (fpu_type) 8898 { 8899 case MIPS_FPU_NONE: 8900 return "none"; 8901 case MIPS_FPU_SINGLE: 8902 return "single"; 8903 case MIPS_FPU_DOUBLE: 8904 return "double"; 8905 default: 8906 return "???"; 8907 } 8908 } 8909 8910 static void 8911 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 8912 { 8913 mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); 8914 if (tdep != NULL) 8915 { 8916 int ef_mips_arch; 8917 int ef_mips_32bitmode; 8918 /* Determine the ISA. */ 8919 switch (tdep->elf_flags & EF_MIPS_ARCH) 8920 { 8921 case E_MIPS_ARCH_1: 8922 ef_mips_arch = 1; 8923 break; 8924 case E_MIPS_ARCH_2: 8925 ef_mips_arch = 2; 8926 break; 8927 case E_MIPS_ARCH_3: 8928 ef_mips_arch = 3; 8929 break; 8930 case E_MIPS_ARCH_4: 8931 ef_mips_arch = 4; 8932 break; 8933 default: 8934 ef_mips_arch = 0; 8935 break; 8936 } 8937 /* Determine the size of a pointer. */ 8938 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); 8939 gdb_printf (file, 8940 "mips_dump_tdep: tdep->elf_flags = 0x%x\n", 8941 tdep->elf_flags); 8942 gdb_printf (file, 8943 "mips_dump_tdep: ef_mips_32bitmode = %d\n", 8944 ef_mips_32bitmode); 8945 gdb_printf (file, 8946 "mips_dump_tdep: ef_mips_arch = %d\n", 8947 ef_mips_arch); 8948 gdb_printf (file, 8949 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", 8950 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); 8951 gdb_printf (file, 8952 "mips_dump_tdep: " 8953 "mips_mask_address_p() %d (default %d)\n", 8954 mips_mask_address_p (tdep), 8955 tdep->default_mask_address_p); 8956 } 8957 gdb_printf (file, 8958 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", 8959 MIPS_DEFAULT_FPU_TYPE, 8960 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); 8961 gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n", 8962 mips_eabi (gdbarch)); 8963 gdb_printf (file, 8964 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", 8965 mips_get_fpu_type (gdbarch), 8966 mips_fpu_type_str (mips_get_fpu_type (gdbarch))); 8967 } 8968 8969 void _initialize_mips_tdep (); 8970 void 8971 _initialize_mips_tdep () 8972 { 8973 static struct cmd_list_element *mipsfpulist = NULL; 8974 8975 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; 8976 if (MIPS_ABI_LAST + 1 8977 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) 8978 internal_error (_("mips_abi_strings out of sync")); 8979 8980 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); 8981 8982 /* Create feature sets with the appropriate properties. The values 8983 are not important. */ 8984 mips_tdesc_gp32 = allocate_target_description ().release (); 8985 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); 8986 8987 mips_tdesc_gp64 = allocate_target_description ().release (); 8988 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); 8989 8990 /* Add root prefix command for all "set mips"/"show mips" commands. */ 8991 add_setshow_prefix_cmd ("mips", no_class, 8992 _("Various MIPS specific commands."), 8993 _("Various MIPS specific commands."), 8994 &setmipscmdlist, &showmipscmdlist, 8995 &setlist, &showlist); 8996 8997 /* Allow the user to override the ABI. */ 8998 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, 8999 &mips_abi_string, _("\ 9000 Set the MIPS ABI used by this program."), _("\ 9001 Show the MIPS ABI used by this program."), _("\ 9002 This option can be set to one of:\n\ 9003 auto - the default ABI associated with the current binary\n\ 9004 o32\n\ 9005 o64\n\ 9006 n32\n\ 9007 n64\n\ 9008 eabi32\n\ 9009 eabi64"), 9010 mips_abi_update, 9011 show_mips_abi, 9012 &setmipscmdlist, &showmipscmdlist); 9013 9014 /* Allow the user to set the ISA to assume for compressed code if ELF 9015 file flags don't tell or there is no program file selected. This 9016 setting is updated whenever unambiguous ELF file flags are interpreted, 9017 and carried over to subsequent sessions. */ 9018 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, 9019 &mips_compression_string, _("\ 9020 Set the compressed ISA encoding used by MIPS code."), _("\ 9021 Show the compressed ISA encoding used by MIPS code."), _("\ 9022 Select the compressed ISA encoding used in functions that have no symbol\n\ 9023 information available. The encoding can be set to either of:\n\ 9024 mips16\n\ 9025 micromips\n\ 9026 and is updated automatically from ELF file flags if available."), 9027 mips_abi_update, 9028 show_mips_compression, 9029 &setmipscmdlist, &showmipscmdlist); 9030 9031 /* Let the user turn off floating point and set the fence post for 9032 heuristic_proc_start. */ 9033 9034 add_basic_prefix_cmd ("mipsfpu", class_support, 9035 _("Set use of MIPS floating-point coprocessor."), 9036 &mipsfpulist, 0, &setlist); 9037 add_cmd ("single", class_support, set_mipsfpu_single_command, 9038 _("Select single-precision MIPS floating-point coprocessor."), 9039 &mipsfpulist); 9040 cmd_list_element *set_mipsfpu_double_cmd 9041 = add_cmd ("double", class_support, set_mipsfpu_double_command, 9042 _("Select double-precision MIPS floating-point coprocessor."), 9043 &mipsfpulist); 9044 add_alias_cmd ("on", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); 9045 add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); 9046 add_alias_cmd ("1", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); 9047 9048 cmd_list_element *set_mipsfpu_none_cmd 9049 = add_cmd ("none", class_support, set_mipsfpu_none_command, 9050 _("Select no MIPS floating-point coprocessor."), &mipsfpulist); 9051 add_alias_cmd ("off", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); 9052 add_alias_cmd ("no", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); 9053 add_alias_cmd ("0", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); 9054 add_cmd ("auto", class_support, set_mipsfpu_auto_command, 9055 _("Select MIPS floating-point coprocessor automatically."), 9056 &mipsfpulist); 9057 add_cmd ("mipsfpu", class_support, show_mipsfpu_command, 9058 _("Show current use of MIPS floating-point coprocessor target."), 9059 &showlist); 9060 9061 /* We really would like to have both "0" and "unlimited" work, but 9062 command.c doesn't deal with that. So make it a var_zinteger 9063 because the user can always use "999999" or some such for unlimited. */ 9064 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, 9065 &heuristic_fence_post, _("\ 9066 Set the distance searched for the start of a function."), _("\ 9067 Show the distance searched for the start of a function."), _("\ 9068 If you are debugging a stripped executable, GDB needs to search through the\n\ 9069 program for the start of a function. This command sets the distance of the\n\ 9070 search. The only need to set it is when debugging a stripped executable."), 9071 reinit_frame_cache_sfunc, 9072 NULL, /* FIXME: i18n: The distance searched for 9073 the start of a function is %s. */ 9074 &setlist, &showlist); 9075 9076 /* Allow the user to control whether the upper bits of 64-bit 9077 addresses should be zeroed. */ 9078 add_setshow_auto_boolean_cmd ("mask-address", no_class, 9079 &mask_address_var, _("\ 9080 Set zeroing of upper 32 bits of 64-bit addresses."), _("\ 9081 Show zeroing of upper 32 bits of 64-bit addresses."), _("\ 9082 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ 9083 allow GDB to determine the correct value."), 9084 NULL, show_mask_address, 9085 &setmipscmdlist, &showmipscmdlist); 9086 9087 /* Allow the user to control the size of 32 bit registers within the 9088 raw remote packet. */ 9089 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, 9090 &mips64_transfers_32bit_regs_p, _("\ 9091 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9092 _("\ 9093 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9094 _("\ 9095 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ 9096 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 9097 64 bits for others. Use \"off\" to disable compatibility mode"), 9098 set_mips64_transfers_32bit_regs, 9099 NULL, /* FIXME: i18n: Compatibility with 64-bit 9100 MIPS target that transfers 32-bit 9101 quantities is %s. */ 9102 &setlist, &showlist); 9103 9104 /* Debug this files internals. */ 9105 add_setshow_zuinteger_cmd ("mips", class_maintenance, 9106 &mips_debug, _("\ 9107 Set mips debugging."), _("\ 9108 Show mips debugging."), _("\ 9109 When non-zero, mips specific debugging is enabled."), 9110 NULL, 9111 NULL, /* FIXME: i18n: Mips debugging is 9112 currently %s. */ 9113 &setdebuglist, &showdebuglist); 9114 } 9115