1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger. 2 3 Copyright (C) 1988-2020 Free Software Foundation, Inc. 4 5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU 6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23 #include "defs.h" 24 #include "frame.h" 25 #include "inferior.h" 26 #include "symtab.h" 27 #include "value.h" 28 #include "gdbcmd.h" 29 #include "language.h" 30 #include "gdbcore.h" 31 #include "symfile.h" 32 #include "objfiles.h" 33 #include "gdbtypes.h" 34 #include "target.h" 35 #include "arch-utils.h" 36 #include "regcache.h" 37 #include "osabi.h" 38 #include "mips-tdep.h" 39 #include "block.h" 40 #include "reggroups.h" 41 #include "opcode/mips.h" 42 #include "elf/mips.h" 43 #include "elf-bfd.h" 44 #include "symcat.h" 45 #include "sim-regno.h" 46 #include "dis-asm.h" 47 #include "disasm.h" 48 #include "frame-unwind.h" 49 #include "frame-base.h" 50 #include "trad-frame.h" 51 #include "infcall.h" 52 #include "remote.h" 53 #include "target-descriptions.h" 54 #include "dwarf2/frame.h" 55 #include "user-regs.h" 56 #include "valprint.h" 57 #include "ax.h" 58 #include "target-float.h" 59 #include <algorithm> 60 61 static struct type *mips_register_type (struct gdbarch *gdbarch, int regnum); 62 63 static int mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, 64 ULONGEST inst); 65 static int micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32); 66 static int mips16_instruction_has_delay_slot (unsigned short inst, 67 int mustbe32); 68 69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 70 CORE_ADDR addr); 71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 72 CORE_ADDR addr, int mustbe32); 73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 74 CORE_ADDR addr, int mustbe32); 75 76 static void mips_print_float_info (struct gdbarch *, struct ui_file *, 77 struct frame_info *, const char *); 78 79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */ 80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */ 81 #define ST0_FR (1 << 26) 82 83 /* The sizes of floating point registers. */ 84 85 enum 86 { 87 MIPS_FPU_SINGLE_REGSIZE = 4, 88 MIPS_FPU_DOUBLE_REGSIZE = 8 89 }; 90 91 enum 92 { 93 MIPS32_REGSIZE = 4, 94 MIPS64_REGSIZE = 8 95 }; 96 97 static const char *mips_abi_string; 98 99 static const char *const mips_abi_strings[] = { 100 "auto", 101 "n32", 102 "o32", 103 "n64", 104 "o64", 105 "eabi32", 106 "eabi64", 107 NULL 108 }; 109 110 /* Enum describing the different kinds of breakpoints. */ 111 112 enum mips_breakpoint_kind 113 { 114 /* 16-bit MIPS16 mode breakpoint. */ 115 MIPS_BP_KIND_MIPS16 = 2, 116 117 /* 16-bit microMIPS mode breakpoint. */ 118 MIPS_BP_KIND_MICROMIPS16 = 3, 119 120 /* 32-bit standard MIPS mode breakpoint. */ 121 MIPS_BP_KIND_MIPS32 = 4, 122 123 /* 32-bit microMIPS mode breakpoint. */ 124 MIPS_BP_KIND_MICROMIPS32 = 5, 125 }; 126 127 /* For backwards compatibility we default to MIPS16. This flag is 128 overridden as soon as unambiguous ELF file flags tell us the 129 compressed ISA encoding used. */ 130 static const char mips_compression_mips16[] = "mips16"; 131 static const char mips_compression_micromips[] = "micromips"; 132 static const char *const mips_compression_strings[] = 133 { 134 mips_compression_mips16, 135 mips_compression_micromips, 136 NULL 137 }; 138 139 static const char *mips_compression_string = mips_compression_mips16; 140 141 /* The standard register names, and all the valid aliases for them. */ 142 struct register_alias 143 { 144 const char *name; 145 int regnum; 146 }; 147 148 /* Aliases for o32 and most other ABIs. */ 149 const struct register_alias mips_o32_aliases[] = { 150 { "ta0", 12 }, 151 { "ta1", 13 }, 152 { "ta2", 14 }, 153 { "ta3", 15 } 154 }; 155 156 /* Aliases for n32 and n64. */ 157 const struct register_alias mips_n32_n64_aliases[] = { 158 { "ta0", 8 }, 159 { "ta1", 9 }, 160 { "ta2", 10 }, 161 { "ta3", 11 } 162 }; 163 164 /* Aliases for ABI-independent registers. */ 165 const struct register_alias mips_register_aliases[] = { 166 /* The architecture manuals specify these ABI-independent names for 167 the GPRs. */ 168 #define R(n) { "r" #n, n } 169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 173 #undef R 174 175 /* k0 and k1 are sometimes called these instead (for "kernel 176 temp"). */ 177 { "kt0", 26 }, 178 { "kt1", 27 }, 179 180 /* This is the traditional GDB name for the CP0 status register. */ 181 { "sr", MIPS_PS_REGNUM }, 182 183 /* This is the traditional GDB name for the CP0 BadVAddr register. */ 184 { "bad", MIPS_EMBED_BADVADDR_REGNUM }, 185 186 /* This is the traditional GDB name for the FCSR. */ 187 { "fsr", MIPS_EMBED_FP0_REGNUM + 32 } 188 }; 189 190 const struct register_alias mips_numeric_register_aliases[] = { 191 #define R(n) { #n, n } 192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 196 #undef R 197 }; 198 199 #ifndef MIPS_DEFAULT_FPU_TYPE 200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE 201 #endif 202 static int mips_fpu_type_auto = 1; 203 static enum mips_fpu_type mips_fpu_type = MIPS_DEFAULT_FPU_TYPE; 204 205 static unsigned int mips_debug = 0; 206 207 /* Properties (for struct target_desc) describing the g/G packet 208 layout. */ 209 #define PROPERTY_GP32 "internal: transfers-32bit-registers" 210 #define PROPERTY_GP64 "internal: transfers-64bit-registers" 211 212 struct target_desc *mips_tdesc_gp32; 213 struct target_desc *mips_tdesc_gp64; 214 215 /* The current set of options to be passed to the disassembler. */ 216 static char *mips_disassembler_options; 217 218 /* Implicit disassembler options for individual ABIs. These tell 219 libopcodes to use general-purpose register names corresponding 220 to the ABI we have selected, perhaps via a `set mips abi ...' 221 override, rather than ones inferred from the ABI set in the ELF 222 headers of the binary file selected for debugging. */ 223 static const char mips_disassembler_options_o32[] = "gpr-names=32"; 224 static const char mips_disassembler_options_n32[] = "gpr-names=n32"; 225 static const char mips_disassembler_options_n64[] = "gpr-names=64"; 226 227 const struct mips_regnum * 228 mips_regnum (struct gdbarch *gdbarch) 229 { 230 return gdbarch_tdep (gdbarch)->regnum; 231 } 232 233 static int 234 mips_fpa0_regnum (struct gdbarch *gdbarch) 235 { 236 return mips_regnum (gdbarch)->fp0 + 12; 237 } 238 239 /* Return 1 if REGNUM refers to a floating-point general register, raw 240 or cooked. Otherwise return 0. */ 241 242 static int 243 mips_float_register_p (struct gdbarch *gdbarch, int regnum) 244 { 245 int rawnum = regnum % gdbarch_num_regs (gdbarch); 246 247 return (rawnum >= mips_regnum (gdbarch)->fp0 248 && rawnum < mips_regnum (gdbarch)->fp0 + 32); 249 } 250 251 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \ 252 == MIPS_ABI_EABI32 \ 253 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64) 254 255 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \ 256 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum) 257 258 #define MIPS_LAST_ARG_REGNUM(gdbarch) \ 259 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum) 260 261 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type) 262 263 /* Return the MIPS ABI associated with GDBARCH. */ 264 enum mips_abi 265 mips_abi (struct gdbarch *gdbarch) 266 { 267 return gdbarch_tdep (gdbarch)->mips_abi; 268 } 269 270 int 271 mips_isa_regsize (struct gdbarch *gdbarch) 272 { 273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 274 275 /* If we know how big the registers are, use that size. */ 276 if (tdep->register_size_valid_p) 277 return tdep->register_size; 278 279 /* Fall back to the previous behavior. */ 280 return (gdbarch_bfd_arch_info (gdbarch)->bits_per_word 281 / gdbarch_bfd_arch_info (gdbarch)->bits_per_byte); 282 } 283 284 /* Max saved register size. */ 285 #define MAX_MIPS_ABI_REGSIZE 8 286 287 /* Return the currently configured (or set) saved register size. */ 288 289 unsigned int 290 mips_abi_regsize (struct gdbarch *gdbarch) 291 { 292 switch (mips_abi (gdbarch)) 293 { 294 case MIPS_ABI_EABI32: 295 case MIPS_ABI_O32: 296 return 4; 297 case MIPS_ABI_N32: 298 case MIPS_ABI_N64: 299 case MIPS_ABI_O64: 300 case MIPS_ABI_EABI64: 301 return 8; 302 case MIPS_ABI_UNKNOWN: 303 case MIPS_ABI_LAST: 304 default: 305 internal_error (__FILE__, __LINE__, _("bad switch")); 306 } 307 } 308 309 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here 310 are some functions to handle addresses associated with compressed 311 code including but not limited to testing, setting, or clearing 312 bit 0 of such addresses. */ 313 314 /* Return one iff compressed code is the MIPS16 instruction set. */ 315 316 static int 317 is_mips16_isa (struct gdbarch *gdbarch) 318 { 319 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MIPS16; 320 } 321 322 /* Return one iff compressed code is the microMIPS instruction set. */ 323 324 static int 325 is_micromips_isa (struct gdbarch *gdbarch) 326 { 327 return gdbarch_tdep (gdbarch)->mips_isa == ISA_MICROMIPS; 328 } 329 330 /* Return one iff ADDR denotes compressed code. */ 331 332 static int 333 is_compact_addr (CORE_ADDR addr) 334 { 335 return ((addr) & 1); 336 } 337 338 /* Return one iff ADDR denotes standard ISA code. */ 339 340 static int 341 is_mips_addr (CORE_ADDR addr) 342 { 343 return !is_compact_addr (addr); 344 } 345 346 /* Return one iff ADDR denotes MIPS16 code. */ 347 348 static int 349 is_mips16_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 350 { 351 return is_compact_addr (addr) && is_mips16_isa (gdbarch); 352 } 353 354 /* Return one iff ADDR denotes microMIPS code. */ 355 356 static int 357 is_micromips_addr (struct gdbarch *gdbarch, CORE_ADDR addr) 358 { 359 return is_compact_addr (addr) && is_micromips_isa (gdbarch); 360 } 361 362 /* Strip the ISA (compression) bit off from ADDR. */ 363 364 static CORE_ADDR 365 unmake_compact_addr (CORE_ADDR addr) 366 { 367 return ((addr) & ~(CORE_ADDR) 1); 368 } 369 370 /* Add the ISA (compression) bit to ADDR. */ 371 372 static CORE_ADDR 373 make_compact_addr (CORE_ADDR addr) 374 { 375 return ((addr) | (CORE_ADDR) 1); 376 } 377 378 /* Extern version of unmake_compact_addr; we use a separate function 379 so that unmake_compact_addr can be inlined throughout this file. */ 380 381 CORE_ADDR 382 mips_unmake_compact_addr (CORE_ADDR addr) 383 { 384 return unmake_compact_addr (addr); 385 } 386 387 /* Functions for setting and testing a bit in a minimal symbol that 388 marks it as MIPS16 or microMIPS function. The MSB of the minimal 389 symbol's "info" field is used for this purpose. 390 391 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is 392 "special", i.e. refers to a MIPS16 or microMIPS function, and sets 393 one of the "special" bits in a minimal symbol to mark it accordingly. 394 The test checks an ELF-private flag that is valid for true function 395 symbols only; for synthetic symbols such as for PLT stubs that have 396 no ELF-private part at all the MIPS BFD backend arranges for this 397 information to be carried in the asymbol's udata field instead. 398 399 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit 400 in a minimal symbol. */ 401 402 static void 403 mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) 404 { 405 elf_symbol_type *elfsym = (elf_symbol_type *) sym; 406 unsigned char st_other; 407 408 if ((sym->flags & BSF_SYNTHETIC) == 0) 409 st_other = elfsym->internal_elf_sym.st_other; 410 else if ((sym->flags & BSF_FUNCTION) != 0) 411 st_other = sym->udata.i; 412 else 413 return; 414 415 if (ELF_ST_IS_MICROMIPS (st_other)) 416 { 417 MSYMBOL_TARGET_FLAG_MICROMIPS (msym) = 1; 418 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); 419 } 420 else if (ELF_ST_IS_MIPS16 (st_other)) 421 { 422 MSYMBOL_TARGET_FLAG_MIPS16 (msym) = 1; 423 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1); 424 } 425 } 426 427 /* Return one iff MSYM refers to standard ISA code. */ 428 429 static int 430 msymbol_is_mips (struct minimal_symbol *msym) 431 { 432 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym) 433 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym)); 434 } 435 436 /* Return one iff MSYM refers to MIPS16 code. */ 437 438 static int 439 msymbol_is_mips16 (struct minimal_symbol *msym) 440 { 441 return MSYMBOL_TARGET_FLAG_MIPS16 (msym); 442 } 443 444 /* Return one iff MSYM refers to microMIPS code. */ 445 446 static int 447 msymbol_is_micromips (struct minimal_symbol *msym) 448 { 449 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym); 450 } 451 452 /* Set the ISA bit in the main symbol too, complementing the corresponding 453 minimal symbol setting and reflecting the run-time value of the symbol. 454 The need for comes from the ISA bit having been cleared as code in 455 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's 456 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values 457 of symbols referring to compressed code different in GDB to the values 458 used by actual code. That in turn makes them evaluate incorrectly in 459 expressions, producing results different to what the same expressions 460 yield when compiled into the program being debugged. */ 461 462 static void 463 mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) 464 { 465 if (SYMBOL_CLASS (sym) == LOC_BLOCK) 466 { 467 /* We are in symbol reading so it is OK to cast away constness. */ 468 struct block *block = (struct block *) SYMBOL_BLOCK_VALUE (sym); 469 CORE_ADDR compact_block_start; 470 struct bound_minimal_symbol msym; 471 472 compact_block_start = BLOCK_START (block) | 1; 473 msym = lookup_minimal_symbol_by_pc (compact_block_start); 474 if (msym.minsym && !msymbol_is_mips (msym.minsym)) 475 { 476 BLOCK_START (block) = compact_block_start; 477 } 478 } 479 } 480 481 /* XFER a value from the big/little/left end of the register. 482 Depending on the size of the value it might occupy the entire 483 register or just part of it. Make an allowance for this, aligning 484 things accordingly. */ 485 486 static void 487 mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, 488 int reg_num, int length, 489 enum bfd_endian endian, gdb_byte *in, 490 const gdb_byte *out, int buf_offset) 491 { 492 int reg_offset = 0; 493 494 gdb_assert (reg_num >= gdbarch_num_regs (gdbarch)); 495 /* Need to transfer the left or right part of the register, based on 496 the targets byte order. */ 497 switch (endian) 498 { 499 case BFD_ENDIAN_BIG: 500 reg_offset = register_size (gdbarch, reg_num) - length; 501 break; 502 case BFD_ENDIAN_LITTLE: 503 reg_offset = 0; 504 break; 505 case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ 506 reg_offset = 0; 507 break; 508 default: 509 internal_error (__FILE__, __LINE__, _("bad switch")); 510 } 511 if (mips_debug) 512 fprintf_unfiltered (gdb_stderr, 513 "xfer $%d, reg offset %d, buf offset %d, length %d, ", 514 reg_num, reg_offset, buf_offset, length); 515 if (mips_debug && out != NULL) 516 { 517 int i; 518 fprintf_unfiltered (gdb_stdlog, "out "); 519 for (i = 0; i < length; i++) 520 fprintf_unfiltered (gdb_stdlog, "%02x", out[buf_offset + i]); 521 } 522 if (in != NULL) 523 regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); 524 if (out != NULL) 525 regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); 526 if (mips_debug && in != NULL) 527 { 528 int i; 529 fprintf_unfiltered (gdb_stdlog, "in "); 530 for (i = 0; i < length; i++) 531 fprintf_unfiltered (gdb_stdlog, "%02x", in[buf_offset + i]); 532 } 533 if (mips_debug) 534 fprintf_unfiltered (gdb_stdlog, "\n"); 535 } 536 537 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU 538 compatiblity mode. A return value of 1 means that we have 539 physical 64-bit registers, but should treat them as 32-bit registers. */ 540 541 static int 542 mips2_fp_compat (struct frame_info *frame) 543 { 544 struct gdbarch *gdbarch = get_frame_arch (frame); 545 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not 546 meaningful. */ 547 if (register_size (gdbarch, mips_regnum (gdbarch)->fp0) == 4) 548 return 0; 549 550 #if 0 551 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently, 552 in all the places we deal with FP registers. PR gdb/413. */ 553 /* Otherwise check the FR bit in the status register - it controls 554 the FP compatiblity mode. If it is clear we are in compatibility 555 mode. */ 556 if ((get_frame_register_unsigned (frame, MIPS_PS_REGNUM) & ST0_FR) == 0) 557 return 1; 558 #endif 559 560 return 0; 561 } 562 563 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000 564 565 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); 566 567 /* The list of available "set mips " and "show mips " commands. */ 568 569 static struct cmd_list_element *setmipscmdlist = NULL; 570 static struct cmd_list_element *showmipscmdlist = NULL; 571 572 /* Integer registers 0 thru 31 are handled explicitly by 573 mips_register_name(). Processor specific registers 32 and above 574 are listed in the following tables. */ 575 576 enum 577 { NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; 578 579 /* Generic MIPS. */ 580 581 static const char *mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 582 "sr", "lo", "hi", "bad", "cause", "pc", 583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 587 "fsr", "fir", 588 }; 589 590 /* Names of tx39 registers. */ 591 592 static const char *mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 593 "sr", "lo", "hi", "bad", "cause", "pc", 594 "", "", "", "", "", "", "", "", 595 "", "", "", "", "", "", "", "", 596 "", "", "", "", "", "", "", "", 597 "", "", "", "", "", "", "", "", 598 "", "", "", "", 599 "", "", "", "", "", "", "", "", 600 "", "", "config", "cache", "debug", "depc", "epc", 601 }; 602 603 /* Names of registers with Linux kernels. */ 604 static const char *mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { 605 "sr", "lo", "hi", "bad", "cause", "pc", 606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 610 "fsr", "fir" 611 }; 612 613 614 /* Return the name of the register corresponding to REGNO. */ 615 static const char * 616 mips_register_name (struct gdbarch *gdbarch, int regno) 617 { 618 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 619 /* GPR names for all ABIs other than n32/n64. */ 620 static const char *mips_gpr_names[] = { 621 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 622 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 623 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 624 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 625 }; 626 627 /* GPR names for n32 and n64 ABIs. */ 628 static const char *mips_n32_n64_gpr_names[] = { 629 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", 630 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", 631 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 632 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" 633 }; 634 635 enum mips_abi abi = mips_abi (gdbarch); 636 637 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers, 638 but then don't make the raw register names visible. This (upper) 639 range of user visible register numbers are the pseudo-registers. 640 641 This approach was adopted accommodate the following scenario: 642 It is possible to debug a 64-bit device using a 32-bit 643 programming model. In such instances, the raw registers are 644 configured to be 64-bits wide, while the pseudo registers are 645 configured to be 32-bits wide. The registers that the user 646 sees - the pseudo registers - match the users expectations 647 given the programming model being used. */ 648 int rawnum = regno % gdbarch_num_regs (gdbarch); 649 if (regno < gdbarch_num_regs (gdbarch)) 650 return ""; 651 652 /* The MIPS integer registers are always mapped from 0 to 31. The 653 names of the registers (which reflects the conventions regarding 654 register use) vary depending on the ABI. */ 655 if (0 <= rawnum && rawnum < 32) 656 { 657 if (abi == MIPS_ABI_N32 || abi == MIPS_ABI_N64) 658 return mips_n32_n64_gpr_names[rawnum]; 659 else 660 return mips_gpr_names[rawnum]; 661 } 662 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch))) 663 return tdesc_register_name (gdbarch, rawnum); 664 else if (32 <= rawnum && rawnum < gdbarch_num_regs (gdbarch)) 665 { 666 gdb_assert (rawnum - 32 < NUM_MIPS_PROCESSOR_REGS); 667 if (tdep->mips_processor_reg_names[rawnum - 32]) 668 return tdep->mips_processor_reg_names[rawnum - 32]; 669 return ""; 670 } 671 else 672 internal_error (__FILE__, __LINE__, 673 _("mips_register_name: bad register number %d"), rawnum); 674 } 675 676 /* Return the groups that a MIPS register can be categorised into. */ 677 678 static int 679 mips_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 680 struct reggroup *reggroup) 681 { 682 int vector_p; 683 int float_p; 684 int raw_p; 685 int rawnum = regnum % gdbarch_num_regs (gdbarch); 686 int pseudo = regnum / gdbarch_num_regs (gdbarch); 687 if (reggroup == all_reggroup) 688 return pseudo; 689 vector_p = TYPE_VECTOR (register_type (gdbarch, regnum)); 690 float_p = register_type (gdbarch, regnum)->code () == TYPE_CODE_FLT; 691 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs 692 (gdbarch), as not all architectures are multi-arch. */ 693 raw_p = rawnum < gdbarch_num_regs (gdbarch); 694 if (gdbarch_register_name (gdbarch, regnum) == NULL 695 || gdbarch_register_name (gdbarch, regnum)[0] == '\0') 696 return 0; 697 if (reggroup == float_reggroup) 698 return float_p && pseudo; 699 if (reggroup == vector_reggroup) 700 return vector_p && pseudo; 701 if (reggroup == general_reggroup) 702 return (!vector_p && !float_p) && pseudo; 703 /* Save the pseudo registers. Need to make certain that any code 704 extracting register values from a saved register cache also uses 705 pseudo registers. */ 706 if (reggroup == save_reggroup) 707 return raw_p && pseudo; 708 /* Restore the same pseudo register. */ 709 if (reggroup == restore_reggroup) 710 return raw_p && pseudo; 711 return 0; 712 } 713 714 /* Return the groups that a MIPS register can be categorised into. 715 This version is only used if we have a target description which 716 describes real registers (and their groups). */ 717 718 static int 719 mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 720 struct reggroup *reggroup) 721 { 722 int rawnum = regnum % gdbarch_num_regs (gdbarch); 723 int pseudo = regnum / gdbarch_num_regs (gdbarch); 724 int ret; 725 726 /* Only save, restore, and display the pseudo registers. Need to 727 make certain that any code extracting register values from a 728 saved register cache also uses pseudo registers. 729 730 Note: saving and restoring the pseudo registers is slightly 731 strange; if we have 64 bits, we should save and restore all 732 64 bits. But this is hard and has little benefit. */ 733 if (!pseudo) 734 return 0; 735 736 ret = tdesc_register_in_reggroup_p (gdbarch, rawnum, reggroup); 737 if (ret != -1) 738 return ret; 739 740 return mips_register_reggroup_p (gdbarch, regnum, reggroup); 741 } 742 743 /* Map the symbol table registers which live in the range [1 * 744 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw 745 registers. Take care of alignment and size problems. */ 746 747 static enum register_status 748 mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, 749 int cookednum, gdb_byte *buf) 750 { 751 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 752 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 753 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 754 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 755 return regcache->raw_read (rawnum, buf); 756 else if (register_size (gdbarch, rawnum) > 757 register_size (gdbarch, cookednum)) 758 { 759 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 760 return regcache->raw_read_part (rawnum, 0, 4, buf); 761 else 762 { 763 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 764 LONGEST regval; 765 enum register_status status; 766 767 status = regcache->raw_read (rawnum, ®val); 768 if (status == REG_VALID) 769 store_signed_integer (buf, 4, byte_order, regval); 770 return status; 771 } 772 } 773 else 774 internal_error (__FILE__, __LINE__, _("bad register size")); 775 } 776 777 static void 778 mips_pseudo_register_write (struct gdbarch *gdbarch, 779 struct regcache *regcache, int cookednum, 780 const gdb_byte *buf) 781 { 782 int rawnum = cookednum % gdbarch_num_regs (gdbarch); 783 gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) 784 && cookednum < 2 * gdbarch_num_regs (gdbarch)); 785 if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) 786 regcache->raw_write (rawnum, buf); 787 else if (register_size (gdbarch, rawnum) > 788 register_size (gdbarch, cookednum)) 789 { 790 if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 791 regcache->raw_write_part (rawnum, 0, 4, buf); 792 else 793 { 794 /* Sign extend the shortened version of the register prior 795 to placing it in the raw register. This is required for 796 some mips64 parts in order to avoid unpredictable behavior. */ 797 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 798 LONGEST regval = extract_signed_integer (buf, 4, byte_order); 799 regcache_raw_write_signed (regcache, rawnum, regval); 800 } 801 } 802 else 803 internal_error (__FILE__, __LINE__, _("bad register size")); 804 } 805 806 static int 807 mips_ax_pseudo_register_collect (struct gdbarch *gdbarch, 808 struct agent_expr *ax, int reg) 809 { 810 int rawnum = reg % gdbarch_num_regs (gdbarch); 811 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 812 && reg < 2 * gdbarch_num_regs (gdbarch)); 813 814 ax_reg_mask (ax, rawnum); 815 816 return 0; 817 } 818 819 static int 820 mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, 821 struct agent_expr *ax, int reg) 822 { 823 int rawnum = reg % gdbarch_num_regs (gdbarch); 824 gdb_assert (reg >= gdbarch_num_regs (gdbarch) 825 && reg < 2 * gdbarch_num_regs (gdbarch)); 826 if (register_size (gdbarch, rawnum) >= register_size (gdbarch, reg)) 827 { 828 ax_reg (ax, rawnum); 829 830 if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) 831 { 832 if (!gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p 833 || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) 834 { 835 ax_const_l (ax, 32); 836 ax_simple (ax, aop_lsh); 837 } 838 ax_const_l (ax, 32); 839 ax_simple (ax, aop_rsh_signed); 840 } 841 } 842 else 843 internal_error (__FILE__, __LINE__, _("bad register size")); 844 845 return 0; 846 } 847 848 /* Table to translate 3-bit register field to actual register number. */ 849 static const signed char mips_reg3_to_reg[8] = { 16, 17, 2, 3, 4, 5, 6, 7 }; 850 851 /* Heuristic_proc_start may hunt through the text section for a long 852 time across a 2400 baud serial line. Allows the user to limit this 853 search. */ 854 855 static int heuristic_fence_post = 0; 856 857 /* Number of bytes of storage in the actual machine representation for 858 register N. NOTE: This defines the pseudo register type so need to 859 rebuild the architecture vector. */ 860 861 static bool mips64_transfers_32bit_regs_p = false; 862 863 static void 864 set_mips64_transfers_32bit_regs (const char *args, int from_tty, 865 struct cmd_list_element *c) 866 { 867 struct gdbarch_info info; 868 gdbarch_info_init (&info); 869 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 870 instead of relying on globals. Doing that would let generic code 871 handle the search for this specific architecture. */ 872 if (!gdbarch_update_p (info)) 873 { 874 mips64_transfers_32bit_regs_p = 0; 875 error (_("32-bit compatibility mode not supported")); 876 } 877 } 878 879 /* Convert to/from a register and the corresponding memory value. */ 880 881 /* This predicate tests for the case of an 8 byte floating point 882 value that is being transferred to or from a pair of floating point 883 registers each of which are (or are considered to be) only 4 bytes 884 wide. */ 885 static int 886 mips_convert_register_float_case_p (struct gdbarch *gdbarch, int regnum, 887 struct type *type) 888 { 889 return (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 890 && register_size (gdbarch, regnum) == 4 891 && mips_float_register_p (gdbarch, regnum) 892 && type->code () == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8); 893 } 894 895 /* This predicate tests for the case of a value of less than 8 896 bytes in width that is being transfered to or from an 8 byte 897 general purpose register. */ 898 static int 899 mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, 900 struct type *type) 901 { 902 int num_regs = gdbarch_num_regs (gdbarch); 903 904 return (register_size (gdbarch, regnum) == 8 905 && regnum % num_regs > 0 && regnum % num_regs < 32 906 && TYPE_LENGTH (type) < 8); 907 } 908 909 static int 910 mips_convert_register_p (struct gdbarch *gdbarch, 911 int regnum, struct type *type) 912 { 913 return (mips_convert_register_float_case_p (gdbarch, regnum, type) 914 || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); 915 } 916 917 static int 918 mips_register_to_value (struct frame_info *frame, int regnum, 919 struct type *type, gdb_byte *to, 920 int *optimizedp, int *unavailablep) 921 { 922 struct gdbarch *gdbarch = get_frame_arch (frame); 923 924 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 925 { 926 get_frame_register (frame, regnum + 0, to + 4); 927 get_frame_register (frame, regnum + 1, to + 0); 928 929 if (!get_frame_register_bytes (frame, regnum + 0, 0, 4, to + 4, 930 optimizedp, unavailablep)) 931 return 0; 932 933 if (!get_frame_register_bytes (frame, regnum + 1, 0, 4, to + 0, 934 optimizedp, unavailablep)) 935 return 0; 936 *optimizedp = *unavailablep = 0; 937 return 1; 938 } 939 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 940 { 941 int len = TYPE_LENGTH (type); 942 CORE_ADDR offset; 943 944 offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; 945 if (!get_frame_register_bytes (frame, regnum, offset, len, to, 946 optimizedp, unavailablep)) 947 return 0; 948 949 *optimizedp = *unavailablep = 0; 950 return 1; 951 } 952 else 953 { 954 internal_error (__FILE__, __LINE__, 955 _("mips_register_to_value: unrecognized case")); 956 } 957 } 958 959 static void 960 mips_value_to_register (struct frame_info *frame, int regnum, 961 struct type *type, const gdb_byte *from) 962 { 963 struct gdbarch *gdbarch = get_frame_arch (frame); 964 965 if (mips_convert_register_float_case_p (gdbarch, regnum, type)) 966 { 967 put_frame_register (frame, regnum + 0, from + 4); 968 put_frame_register (frame, regnum + 1, from + 0); 969 } 970 else if (mips_convert_register_gpreg_case_p (gdbarch, regnum, type)) 971 { 972 gdb_byte fill[8]; 973 int len = TYPE_LENGTH (type); 974 975 /* Sign extend values, irrespective of type, that are stored to 976 a 64-bit general purpose register. (32-bit unsigned values 977 are stored as signed quantities within a 64-bit register. 978 When performing an operation, in compiled code, that combines 979 a 32-bit unsigned value with a signed 64-bit value, a type 980 conversion is first performed that zeroes out the high 32 bits.) */ 981 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 982 { 983 if (from[0] & 0x80) 984 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); 985 else 986 store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); 987 put_frame_register_bytes (frame, regnum, 0, 8 - len, fill); 988 put_frame_register_bytes (frame, regnum, 8 - len, len, from); 989 } 990 else 991 { 992 if (from[len-1] & 0x80) 993 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); 994 else 995 store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); 996 put_frame_register_bytes (frame, regnum, 0, len, from); 997 put_frame_register_bytes (frame, regnum, len, 8 - len, fill); 998 } 999 } 1000 else 1001 { 1002 internal_error (__FILE__, __LINE__, 1003 _("mips_value_to_register: unrecognized case")); 1004 } 1005 } 1006 1007 /* Return the GDB type object for the "standard" data type of data in 1008 register REG. */ 1009 1010 static struct type * 1011 mips_register_type (struct gdbarch *gdbarch, int regnum) 1012 { 1013 gdb_assert (regnum >= 0 && regnum < 2 * gdbarch_num_regs (gdbarch)); 1014 if (mips_float_register_p (gdbarch, regnum)) 1015 { 1016 /* The floating-point registers raw, or cooked, always match 1017 mips_isa_regsize(), and also map 1:1, byte for byte. */ 1018 if (mips_isa_regsize (gdbarch) == 4) 1019 return builtin_type (gdbarch)->builtin_float; 1020 else 1021 return builtin_type (gdbarch)->builtin_double; 1022 } 1023 else if (regnum < gdbarch_num_regs (gdbarch)) 1024 { 1025 /* The raw or ISA registers. These are all sized according to 1026 the ISA regsize. */ 1027 if (mips_isa_regsize (gdbarch) == 4) 1028 return builtin_type (gdbarch)->builtin_int32; 1029 else 1030 return builtin_type (gdbarch)->builtin_int64; 1031 } 1032 else 1033 { 1034 int rawnum = regnum - gdbarch_num_regs (gdbarch); 1035 1036 /* The cooked or ABI registers. These are sized according to 1037 the ABI (with a few complications). */ 1038 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1039 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1040 return builtin_type (gdbarch)->builtin_int32; 1041 else if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1042 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1043 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1044 /* The pseudo/cooked view of the embedded registers is always 1045 32-bit. The raw view is handled below. */ 1046 return builtin_type (gdbarch)->builtin_int32; 1047 else if (gdbarch_tdep (gdbarch)->mips64_transfers_32bit_regs_p) 1048 /* The target, while possibly using a 64-bit register buffer, 1049 is only transfering 32-bits of each integer register. 1050 Reflect this in the cooked/pseudo (ABI) register value. */ 1051 return builtin_type (gdbarch)->builtin_int32; 1052 else if (mips_abi_regsize (gdbarch) == 4) 1053 /* The ABI is restricted to 32-bit registers (the ISA could be 1054 32- or 64-bit). */ 1055 return builtin_type (gdbarch)->builtin_int32; 1056 else 1057 /* 64-bit ABI. */ 1058 return builtin_type (gdbarch)->builtin_int64; 1059 } 1060 } 1061 1062 /* Return the GDB type for the pseudo register REGNUM, which is the 1063 ABI-level view. This function is only called if there is a target 1064 description which includes registers, so we know precisely the 1065 types of hardware registers. */ 1066 1067 static struct type * 1068 mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) 1069 { 1070 const int num_regs = gdbarch_num_regs (gdbarch); 1071 int rawnum = regnum % num_regs; 1072 struct type *rawtype; 1073 1074 gdb_assert (regnum >= num_regs && regnum < 2 * num_regs); 1075 1076 /* Absent registers are still absent. */ 1077 rawtype = gdbarch_register_type (gdbarch, rawnum); 1078 if (TYPE_LENGTH (rawtype) == 0) 1079 return rawtype; 1080 1081 /* Present the floating point registers however the hardware did; 1082 do not try to convert between FPU layouts. */ 1083 if (mips_float_register_p (gdbarch, rawnum)) 1084 return rawtype; 1085 1086 /* Floating-point control registers are always 32-bit even though for 1087 backwards compatibility reasons 64-bit targets will transfer them 1088 as 64-bit quantities even if using XML descriptions. */ 1089 if (rawnum == mips_regnum (gdbarch)->fp_control_status 1090 || rawnum == mips_regnum (gdbarch)->fp_implementation_revision) 1091 return builtin_type (gdbarch)->builtin_int32; 1092 1093 /* Use pointer types for registers if we can. For n32 we can not, 1094 since we do not have a 64-bit pointer type. */ 1095 if (mips_abi_regsize (gdbarch) 1096 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_data_ptr)) 1097 { 1098 if (rawnum == MIPS_SP_REGNUM 1099 || rawnum == mips_regnum (gdbarch)->badvaddr) 1100 return builtin_type (gdbarch)->builtin_data_ptr; 1101 else if (rawnum == mips_regnum (gdbarch)->pc) 1102 return builtin_type (gdbarch)->builtin_func_ptr; 1103 } 1104 1105 if (mips_abi_regsize (gdbarch) == 4 && TYPE_LENGTH (rawtype) == 8 1106 && ((rawnum >= MIPS_ZERO_REGNUM && rawnum <= MIPS_PS_REGNUM) 1107 || rawnum == mips_regnum (gdbarch)->lo 1108 || rawnum == mips_regnum (gdbarch)->hi 1109 || rawnum == mips_regnum (gdbarch)->badvaddr 1110 || rawnum == mips_regnum (gdbarch)->cause 1111 || rawnum == mips_regnum (gdbarch)->pc 1112 || (mips_regnum (gdbarch)->dspacc != -1 1113 && rawnum >= mips_regnum (gdbarch)->dspacc 1114 && rawnum < mips_regnum (gdbarch)->dspacc + 6))) 1115 return builtin_type (gdbarch)->builtin_int32; 1116 1117 /* The pseudo/cooked view of embedded registers is always 1118 32-bit, even if the target transfers 64-bit values for them. 1119 New targets relying on XML descriptions should only transfer 1120 the necessary 32 bits, but older versions of GDB expected 64, 1121 so allow the target to provide 64 bits without interfering 1122 with the displayed type. */ 1123 if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX 1124 && rawnum >= MIPS_FIRST_EMBED_REGNUM 1125 && rawnum <= MIPS_LAST_EMBED_REGNUM) 1126 return builtin_type (gdbarch)->builtin_int32; 1127 1128 /* For all other registers, pass through the hardware type. */ 1129 return rawtype; 1130 } 1131 1132 /* Should the upper word of 64-bit addresses be zeroed? */ 1133 static enum auto_boolean mask_address_var = AUTO_BOOLEAN_AUTO; 1134 1135 static int 1136 mips_mask_address_p (struct gdbarch_tdep *tdep) 1137 { 1138 switch (mask_address_var) 1139 { 1140 case AUTO_BOOLEAN_TRUE: 1141 return 1; 1142 case AUTO_BOOLEAN_FALSE: 1143 return 0; 1144 break; 1145 case AUTO_BOOLEAN_AUTO: 1146 return tdep->default_mask_address_p; 1147 default: 1148 internal_error (__FILE__, __LINE__, 1149 _("mips_mask_address_p: bad switch")); 1150 return -1; 1151 } 1152 } 1153 1154 static void 1155 show_mask_address (struct ui_file *file, int from_tty, 1156 struct cmd_list_element *c, const char *value) 1157 { 1158 struct gdbarch_tdep *tdep = gdbarch_tdep (target_gdbarch ()); 1159 1160 deprecated_show_value_hack (file, from_tty, c, value); 1161 switch (mask_address_var) 1162 { 1163 case AUTO_BOOLEAN_TRUE: 1164 printf_filtered ("The 32 bit mips address mask is enabled\n"); 1165 break; 1166 case AUTO_BOOLEAN_FALSE: 1167 printf_filtered ("The 32 bit mips address mask is disabled\n"); 1168 break; 1169 case AUTO_BOOLEAN_AUTO: 1170 printf_filtered 1171 ("The 32 bit address mask is set automatically. Currently %s\n", 1172 mips_mask_address_p (tdep) ? "enabled" : "disabled"); 1173 break; 1174 default: 1175 internal_error (__FILE__, __LINE__, _("show_mask_address: bad switch")); 1176 break; 1177 } 1178 } 1179 1180 /* Tell if the program counter value in MEMADDR is in a standard ISA 1181 function. */ 1182 1183 int 1184 mips_pc_is_mips (CORE_ADDR memaddr) 1185 { 1186 struct bound_minimal_symbol sym; 1187 1188 /* Flags indicating that this is a MIPS16 or microMIPS function is 1189 stored by elfread.c in the high bit of the info field. Use this 1190 to decide if the function is standard MIPS. Otherwise if bit 0 1191 of the address is clear, then this is a standard MIPS function. */ 1192 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1193 if (sym.minsym) 1194 return msymbol_is_mips (sym.minsym); 1195 else 1196 return is_mips_addr (memaddr); 1197 } 1198 1199 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */ 1200 1201 int 1202 mips_pc_is_mips16 (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1203 { 1204 struct bound_minimal_symbol sym; 1205 1206 /* A flag indicating that this is a MIPS16 function is stored by 1207 elfread.c in the high bit of the info field. Use this to decide 1208 if the function is MIPS16. Otherwise if bit 0 of the address is 1209 set, then ELF file flags will tell if this is a MIPS16 function. */ 1210 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1211 if (sym.minsym) 1212 return msymbol_is_mips16 (sym.minsym); 1213 else 1214 return is_mips16_addr (gdbarch, memaddr); 1215 } 1216 1217 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */ 1218 1219 int 1220 mips_pc_is_micromips (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1221 { 1222 struct bound_minimal_symbol sym; 1223 1224 /* A flag indicating that this is a microMIPS function is stored by 1225 elfread.c in the high bit of the info field. Use this to decide 1226 if the function is microMIPS. Otherwise if bit 0 of the address 1227 is set, then ELF file flags will tell if this is a microMIPS 1228 function. */ 1229 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1230 if (sym.minsym) 1231 return msymbol_is_micromips (sym.minsym); 1232 else 1233 return is_micromips_addr (gdbarch, memaddr); 1234 } 1235 1236 /* Tell the ISA type of the function the program counter value in MEMADDR 1237 is in. */ 1238 1239 static enum mips_isa 1240 mips_pc_isa (struct gdbarch *gdbarch, CORE_ADDR memaddr) 1241 { 1242 struct bound_minimal_symbol sym; 1243 1244 /* A flag indicating that this is a MIPS16 or a microMIPS function 1245 is stored by elfread.c in the high bit of the info field. Use 1246 this to decide if the function is MIPS16 or microMIPS or normal 1247 MIPS. Otherwise if bit 0 of the address is set, then ELF file 1248 flags will tell if this is a MIPS16 or a microMIPS function. */ 1249 sym = lookup_minimal_symbol_by_pc (make_compact_addr (memaddr)); 1250 if (sym.minsym) 1251 { 1252 if (msymbol_is_micromips (sym.minsym)) 1253 return ISA_MICROMIPS; 1254 else if (msymbol_is_mips16 (sym.minsym)) 1255 return ISA_MIPS16; 1256 else 1257 return ISA_MIPS; 1258 } 1259 else 1260 { 1261 if (is_mips_addr (memaddr)) 1262 return ISA_MIPS; 1263 else if (is_micromips_addr (gdbarch, memaddr)) 1264 return ISA_MICROMIPS; 1265 else 1266 return ISA_MIPS16; 1267 } 1268 } 1269 1270 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery. 1271 The need for comes from the ISA bit having been cleared, making 1272 addresses in FDE, range records, etc. referring to compressed code 1273 different to those in line information, the symbol table and finally 1274 the PC register. That in turn confuses many operations. */ 1275 1276 static CORE_ADDR 1277 mips_adjust_dwarf2_addr (CORE_ADDR pc) 1278 { 1279 pc = unmake_compact_addr (pc); 1280 return mips_pc_is_mips (pc) ? pc : make_compact_addr (pc); 1281 } 1282 1283 /* Recalculate the line record requested so that the resulting PC has 1284 the ISA bit set correctly, used by DWARF-2 machinery. The need for 1285 this adjustment comes from some records associated with compressed 1286 code having the ISA bit cleared, most notably at function prologue 1287 ends. The ISA bit is in this context retrieved from the minimal 1288 symbol covering the address requested, which in turn has been 1289 constructed from the binary's symbol table rather than DWARF-2 1290 information. The correct setting of the ISA bit is required for 1291 breakpoint addresses to correctly match against the stop PC. 1292 1293 As line entries can specify relative address adjustments we need to 1294 keep track of the absolute value of the last line address recorded 1295 in line information, so that we can calculate the actual address to 1296 apply the ISA bit adjustment to. We use PC for this tracking and 1297 keep the original address there. 1298 1299 As such relative address adjustments can be odd within compressed 1300 code we need to keep track of the last line address with the ISA 1301 bit adjustment applied too, as the original address may or may not 1302 have had the ISA bit set. We use ADJ_PC for this tracking and keep 1303 the adjusted address there. 1304 1305 For relative address adjustments we then use these variables to 1306 calculate the address intended by line information, which will be 1307 PC-relative, and return an updated adjustment carrying ISA bit 1308 information, which will be ADJ_PC-relative. For absolute address 1309 adjustments we just return the same address that we store in ADJ_PC 1310 too. 1311 1312 As the first line entry can be relative to an implied address value 1313 of 0 we need to have the initial address set up that we store in PC 1314 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1' 1315 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */ 1316 1317 static CORE_ADDR 1318 mips_adjust_dwarf2_line (CORE_ADDR addr, int rel) 1319 { 1320 static CORE_ADDR adj_pc; 1321 static CORE_ADDR pc; 1322 CORE_ADDR isa_pc; 1323 1324 pc = rel ? pc + addr : addr; 1325 isa_pc = mips_adjust_dwarf2_addr (pc); 1326 addr = rel ? isa_pc - adj_pc : isa_pc; 1327 adj_pc = isa_pc; 1328 return addr; 1329 } 1330 1331 /* Various MIPS16 thunk (aka stub or trampoline) names. */ 1332 1333 static const char mips_str_mips16_call_stub[] = "__mips16_call_stub_"; 1334 static const char mips_str_mips16_ret_stub[] = "__mips16_ret_"; 1335 static const char mips_str_call_fp_stub[] = "__call_stub_fp_"; 1336 static const char mips_str_call_stub[] = "__call_stub_"; 1337 static const char mips_str_fn_stub[] = "__fn_stub_"; 1338 1339 /* This is used as a PIC thunk prefix. */ 1340 1341 static const char mips_str_pic[] = ".pic."; 1342 1343 /* Return non-zero if the PC is inside a call thunk (aka stub or 1344 trampoline) that should be treated as a temporary frame. */ 1345 1346 static int 1347 mips_in_frame_stub (CORE_ADDR pc) 1348 { 1349 CORE_ADDR start_addr; 1350 const char *name; 1351 1352 /* Find the starting address of the function containing the PC. */ 1353 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 1354 return 0; 1355 1356 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */ 1357 if (startswith (name, mips_str_mips16_call_stub)) 1358 return 1; 1359 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */ 1360 if (startswith (name, mips_str_call_stub)) 1361 return 1; 1362 /* If the PC is in __fn_stub_*, this is a call stub. */ 1363 if (startswith (name, mips_str_fn_stub)) 1364 return 1; 1365 1366 return 0; /* Not a stub. */ 1367 } 1368 1369 /* MIPS believes that the PC has a sign extended value. Perhaps the 1370 all registers should be sign extended for simplicity? */ 1371 1372 static CORE_ADDR 1373 mips_read_pc (readable_regcache *regcache) 1374 { 1375 int regnum = gdbarch_pc_regnum (regcache->arch ()); 1376 LONGEST pc; 1377 1378 regcache->cooked_read (regnum, &pc); 1379 return pc; 1380 } 1381 1382 static CORE_ADDR 1383 mips_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 1384 { 1385 CORE_ADDR pc; 1386 1387 pc = frame_unwind_register_signed (next_frame, gdbarch_pc_regnum (gdbarch)); 1388 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as 1389 intermediate frames. In this case we can get the caller's address 1390 from $ra, or if $ra contains an address within a thunk as well, then 1391 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10} 1392 and thus the caller's address is in $s2. */ 1393 if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) 1394 { 1395 pc = frame_unwind_register_signed 1396 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 1397 if (mips_in_frame_stub (pc)) 1398 pc = frame_unwind_register_signed 1399 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 1400 } 1401 return pc; 1402 } 1403 1404 static CORE_ADDR 1405 mips_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 1406 { 1407 return frame_unwind_register_signed 1408 (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); 1409 } 1410 1411 /* Assuming THIS_FRAME is a dummy, return the frame ID of that 1412 dummy frame. The frame ID's base needs to match the TOS value 1413 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 1414 breakpoint. */ 1415 1416 static struct frame_id 1417 mips_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 1418 { 1419 return frame_id_build 1420 (get_frame_register_signed (this_frame, 1421 gdbarch_num_regs (gdbarch) 1422 + MIPS_SP_REGNUM), 1423 get_frame_pc (this_frame)); 1424 } 1425 1426 /* Implement the "write_pc" gdbarch method. */ 1427 1428 void 1429 mips_write_pc (struct regcache *regcache, CORE_ADDR pc) 1430 { 1431 int regnum = gdbarch_pc_regnum (regcache->arch ()); 1432 1433 regcache_cooked_write_unsigned (regcache, regnum, pc); 1434 } 1435 1436 /* Fetch and return instruction from the specified location. Handle 1437 MIPS16/microMIPS as appropriate. */ 1438 1439 static ULONGEST 1440 mips_fetch_instruction (struct gdbarch *gdbarch, 1441 enum mips_isa isa, CORE_ADDR addr, int *errp) 1442 { 1443 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1444 gdb_byte buf[MIPS_INSN32_SIZE]; 1445 int instlen; 1446 int err; 1447 1448 switch (isa) 1449 { 1450 case ISA_MICROMIPS: 1451 case ISA_MIPS16: 1452 instlen = MIPS_INSN16_SIZE; 1453 addr = unmake_compact_addr (addr); 1454 break; 1455 case ISA_MIPS: 1456 instlen = MIPS_INSN32_SIZE; 1457 break; 1458 default: 1459 internal_error (__FILE__, __LINE__, _("invalid ISA")); 1460 break; 1461 } 1462 err = target_read_memory (addr, buf, instlen); 1463 if (errp != NULL) 1464 *errp = err; 1465 if (err != 0) 1466 { 1467 if (errp == NULL) 1468 memory_error (TARGET_XFER_E_IO, addr); 1469 return 0; 1470 } 1471 return extract_unsigned_integer (buf, instlen, byte_order); 1472 } 1473 1474 /* These are the fields of 32 bit mips instructions. */ 1475 #define mips32_op(x) (x >> 26) 1476 #define itype_op(x) (x >> 26) 1477 #define itype_rs(x) ((x >> 21) & 0x1f) 1478 #define itype_rt(x) ((x >> 16) & 0x1f) 1479 #define itype_immediate(x) (x & 0xffff) 1480 1481 #define jtype_op(x) (x >> 26) 1482 #define jtype_target(x) (x & 0x03ffffff) 1483 1484 #define rtype_op(x) (x >> 26) 1485 #define rtype_rs(x) ((x >> 21) & 0x1f) 1486 #define rtype_rt(x) ((x >> 16) & 0x1f) 1487 #define rtype_rd(x) ((x >> 11) & 0x1f) 1488 #define rtype_shamt(x) ((x >> 6) & 0x1f) 1489 #define rtype_funct(x) (x & 0x3f) 1490 1491 /* MicroMIPS instruction fields. */ 1492 #define micromips_op(x) ((x) >> 10) 1493 1494 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest 1495 bit and the size respectively of the field extracted. */ 1496 #define b0s4_imm(x) ((x) & 0xf) 1497 #define b0s5_imm(x) ((x) & 0x1f) 1498 #define b0s5_reg(x) ((x) & 0x1f) 1499 #define b0s7_imm(x) ((x) & 0x7f) 1500 #define b0s10_imm(x) ((x) & 0x3ff) 1501 #define b1s4_imm(x) (((x) >> 1) & 0xf) 1502 #define b1s9_imm(x) (((x) >> 1) & 0x1ff) 1503 #define b2s3_cc(x) (((x) >> 2) & 0x7) 1504 #define b4s2_regl(x) (((x) >> 4) & 0x3) 1505 #define b5s5_op(x) (((x) >> 5) & 0x1f) 1506 #define b5s5_reg(x) (((x) >> 5) & 0x1f) 1507 #define b6s4_op(x) (((x) >> 6) & 0xf) 1508 #define b7s3_reg(x) (((x) >> 7) & 0x7) 1509 1510 /* 32-bit instruction formats, B and S refer to the lowest bit and the size 1511 respectively of the field extracted. */ 1512 #define b0s6_op(x) ((x) & 0x3f) 1513 #define b0s11_op(x) ((x) & 0x7ff) 1514 #define b0s12_imm(x) ((x) & 0xfff) 1515 #define b0s16_imm(x) ((x) & 0xffff) 1516 #define b0s26_imm(x) ((x) & 0x3ffffff) 1517 #define b6s10_ext(x) (((x) >> 6) & 0x3ff) 1518 #define b11s5_reg(x) (((x) >> 11) & 0x1f) 1519 #define b12s4_op(x) (((x) >> 12) & 0xf) 1520 1521 /* Return the size in bytes of the instruction INSN encoded in the ISA 1522 instruction set. */ 1523 1524 static int 1525 mips_insn_size (enum mips_isa isa, ULONGEST insn) 1526 { 1527 switch (isa) 1528 { 1529 case ISA_MICROMIPS: 1530 if ((micromips_op (insn) & 0x4) == 0x4 1531 || (micromips_op (insn) & 0x7) == 0x0) 1532 return 2 * MIPS_INSN16_SIZE; 1533 else 1534 return MIPS_INSN16_SIZE; 1535 case ISA_MIPS16: 1536 if ((insn & 0xf800) == 0xf000) 1537 return 2 * MIPS_INSN16_SIZE; 1538 else 1539 return MIPS_INSN16_SIZE; 1540 case ISA_MIPS: 1541 return MIPS_INSN32_SIZE; 1542 } 1543 internal_error (__FILE__, __LINE__, _("invalid ISA")); 1544 } 1545 1546 static LONGEST 1547 mips32_relative_offset (ULONGEST inst) 1548 { 1549 return ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 2; 1550 } 1551 1552 /* Determine the address of the next instruction executed after the INST 1553 floating condition branch instruction at PC. COUNT specifies the 1554 number of the floating condition bits tested by the branch. */ 1555 1556 static CORE_ADDR 1557 mips32_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, 1558 ULONGEST inst, CORE_ADDR pc, int count) 1559 { 1560 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1561 int cnum = (itype_rt (inst) >> 2) & (count - 1); 1562 int tf = itype_rt (inst) & 1; 1563 int mask = (1 << count) - 1; 1564 ULONGEST fcs; 1565 int cond; 1566 1567 if (fcsr == -1) 1568 /* No way to handle; it'll most likely trap anyway. */ 1569 return pc; 1570 1571 fcs = regcache_raw_get_unsigned (regcache, fcsr); 1572 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1573 1574 if (((cond >> cnum) & mask) != mask * !tf) 1575 pc += mips32_relative_offset (inst); 1576 else 1577 pc += 4; 1578 1579 return pc; 1580 } 1581 1582 /* Return nonzero if the gdbarch is an Octeon series. */ 1583 1584 static int 1585 is_octeon (struct gdbarch *gdbarch) 1586 { 1587 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); 1588 1589 return (info->mach == bfd_mach_mips_octeon 1590 || info->mach == bfd_mach_mips_octeonp 1591 || info->mach == bfd_mach_mips_octeon2); 1592 } 1593 1594 /* Return true if the OP represents the Octeon's BBIT instruction. */ 1595 1596 static int 1597 is_octeon_bbit_op (int op, struct gdbarch *gdbarch) 1598 { 1599 if (!is_octeon (gdbarch)) 1600 return 0; 1601 /* BBIT0 is encoded as LWC2: 110 010. */ 1602 /* BBIT032 is encoded as LDC2: 110 110. */ 1603 /* BBIT1 is encoded as SWC2: 111 010. */ 1604 /* BBIT132 is encoded as SDC2: 111 110. */ 1605 if (op == 50 || op == 54 || op == 58 || op == 62) 1606 return 1; 1607 return 0; 1608 } 1609 1610 1611 /* Determine where to set a single step breakpoint while considering 1612 branch prediction. */ 1613 1614 static CORE_ADDR 1615 mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) 1616 { 1617 struct gdbarch *gdbarch = regcache->arch (); 1618 unsigned long inst; 1619 int op; 1620 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 1621 op = itype_op (inst); 1622 if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch 1623 instruction. */ 1624 { 1625 if (op >> 2 == 5) 1626 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 1627 { 1628 switch (op & 0x03) 1629 { 1630 case 0: /* BEQL */ 1631 goto equal_branch; 1632 case 1: /* BNEL */ 1633 goto neq_branch; 1634 case 2: /* BLEZL */ 1635 goto less_branch; 1636 case 3: /* BGTZL */ 1637 goto greater_branch; 1638 default: 1639 pc += 4; 1640 } 1641 } 1642 else if (op == 17 && itype_rs (inst) == 8) 1643 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 1644 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); 1645 else if (op == 17 && itype_rs (inst) == 9 1646 && (itype_rt (inst) & 2) == 0) 1647 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ 1648 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); 1649 else if (op == 17 && itype_rs (inst) == 10 1650 && (itype_rt (inst) & 2) == 0) 1651 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ 1652 pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); 1653 else if (op == 29) 1654 /* JALX: 011101 */ 1655 /* The new PC will be alternate mode. */ 1656 { 1657 unsigned long reg; 1658 1659 reg = jtype_target (inst) << 2; 1660 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */ 1661 pc = ((pc + 4) & ~(CORE_ADDR) 0x0fffffff) + reg + 1; 1662 } 1663 else if (is_octeon_bbit_op (op, gdbarch)) 1664 { 1665 int bit, branch_if; 1666 1667 branch_if = op == 58 || op == 62; 1668 bit = itype_rt (inst); 1669 1670 /* Take into account the *32 instructions. */ 1671 if (op == 54 || op == 62) 1672 bit += 32; 1673 1674 if (((regcache_raw_get_signed (regcache, 1675 itype_rs (inst)) >> bit) & 1) 1676 == branch_if) 1677 pc += mips32_relative_offset (inst) + 4; 1678 else 1679 pc += 8; /* After the delay slot. */ 1680 } 1681 1682 else 1683 pc += 4; /* Not a branch, next instruction is easy. */ 1684 } 1685 else 1686 { /* This gets way messy. */ 1687 1688 /* Further subdivide into SPECIAL, REGIMM and other. */ 1689 switch (op & 0x07) /* Extract bits 28,27,26. */ 1690 { 1691 case 0: /* SPECIAL */ 1692 op = rtype_funct (inst); 1693 switch (op) 1694 { 1695 case 8: /* JR */ 1696 case 9: /* JALR */ 1697 /* Set PC to that address. */ 1698 pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); 1699 break; 1700 case 12: /* SYSCALL */ 1701 { 1702 struct gdbarch_tdep *tdep; 1703 1704 tdep = gdbarch_tdep (gdbarch); 1705 if (tdep->syscall_next_pc != NULL) 1706 pc = tdep->syscall_next_pc (get_current_frame ()); 1707 else 1708 pc += 4; 1709 } 1710 break; 1711 default: 1712 pc += 4; 1713 } 1714 1715 break; /* end SPECIAL */ 1716 case 1: /* REGIMM */ 1717 { 1718 op = itype_rt (inst); /* branch condition */ 1719 switch (op) 1720 { 1721 case 0: /* BLTZ */ 1722 case 2: /* BLTZL */ 1723 case 16: /* BLTZAL */ 1724 case 18: /* BLTZALL */ 1725 less_branch: 1726 if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) 1727 pc += mips32_relative_offset (inst) + 4; 1728 else 1729 pc += 8; /* after the delay slot */ 1730 break; 1731 case 1: /* BGEZ */ 1732 case 3: /* BGEZL */ 1733 case 17: /* BGEZAL */ 1734 case 19: /* BGEZALL */ 1735 if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) 1736 pc += mips32_relative_offset (inst) + 4; 1737 else 1738 pc += 8; /* after the delay slot */ 1739 break; 1740 case 0x1c: /* BPOSGE32 */ 1741 case 0x1e: /* BPOSGE64 */ 1742 pc += 4; 1743 if (itype_rs (inst) == 0) 1744 { 1745 unsigned int pos = (op & 2) ? 64 : 32; 1746 int dspctl = mips_regnum (gdbarch)->dspctl; 1747 1748 if (dspctl == -1) 1749 /* No way to handle; it'll most likely trap anyway. */ 1750 break; 1751 1752 if ((regcache_raw_get_unsigned (regcache, 1753 dspctl) & 0x7f) >= pos) 1754 pc += mips32_relative_offset (inst); 1755 else 1756 pc += 4; 1757 } 1758 break; 1759 /* All of the other instructions in the REGIMM category */ 1760 default: 1761 pc += 4; 1762 } 1763 } 1764 break; /* end REGIMM */ 1765 case 2: /* J */ 1766 case 3: /* JAL */ 1767 { 1768 unsigned long reg; 1769 reg = jtype_target (inst) << 2; 1770 /* Upper four bits get never changed... */ 1771 pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 1772 } 1773 break; 1774 case 4: /* BEQ, BEQL */ 1775 equal_branch: 1776 if (regcache_raw_get_signed (regcache, itype_rs (inst)) == 1777 regcache_raw_get_signed (regcache, itype_rt (inst))) 1778 pc += mips32_relative_offset (inst) + 4; 1779 else 1780 pc += 8; 1781 break; 1782 case 5: /* BNE, BNEL */ 1783 neq_branch: 1784 if (regcache_raw_get_signed (regcache, itype_rs (inst)) != 1785 regcache_raw_get_signed (regcache, itype_rt (inst))) 1786 pc += mips32_relative_offset (inst) + 4; 1787 else 1788 pc += 8; 1789 break; 1790 case 6: /* BLEZ, BLEZL */ 1791 if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) 1792 pc += mips32_relative_offset (inst) + 4; 1793 else 1794 pc += 8; 1795 break; 1796 case 7: 1797 default: 1798 greater_branch: /* BGTZ, BGTZL */ 1799 if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) 1800 pc += mips32_relative_offset (inst) + 4; 1801 else 1802 pc += 8; 1803 break; 1804 } /* switch */ 1805 } /* else */ 1806 return pc; 1807 } /* mips32_next_pc */ 1808 1809 /* Extract the 7-bit signed immediate offset from the microMIPS instruction 1810 INSN. */ 1811 1812 static LONGEST 1813 micromips_relative_offset7 (ULONGEST insn) 1814 { 1815 return ((b0s7_imm (insn) ^ 0x40) - 0x40) << 1; 1816 } 1817 1818 /* Extract the 10-bit signed immediate offset from the microMIPS instruction 1819 INSN. */ 1820 1821 static LONGEST 1822 micromips_relative_offset10 (ULONGEST insn) 1823 { 1824 return ((b0s10_imm (insn) ^ 0x200) - 0x200) << 1; 1825 } 1826 1827 /* Extract the 16-bit signed immediate offset from the microMIPS instruction 1828 INSN. */ 1829 1830 static LONGEST 1831 micromips_relative_offset16 (ULONGEST insn) 1832 { 1833 return ((b0s16_imm (insn) ^ 0x8000) - 0x8000) << 1; 1834 } 1835 1836 /* Return the size in bytes of the microMIPS instruction at the address PC. */ 1837 1838 static int 1839 micromips_pc_insn_size (struct gdbarch *gdbarch, CORE_ADDR pc) 1840 { 1841 ULONGEST insn; 1842 1843 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1844 return mips_insn_size (ISA_MICROMIPS, insn); 1845 } 1846 1847 /* Calculate the address of the next microMIPS instruction to execute 1848 after the INSN coprocessor 1 conditional branch instruction at the 1849 address PC. COUNT denotes the number of coprocessor condition bits 1850 examined by the branch. */ 1851 1852 static CORE_ADDR 1853 micromips_bc1_pc (struct gdbarch *gdbarch, struct regcache *regcache, 1854 ULONGEST insn, CORE_ADDR pc, int count) 1855 { 1856 int fcsr = mips_regnum (gdbarch)->fp_control_status; 1857 int cnum = b2s3_cc (insn >> 16) & (count - 1); 1858 int tf = b5s5_op (insn >> 16) & 1; 1859 int mask = (1 << count) - 1; 1860 ULONGEST fcs; 1861 int cond; 1862 1863 if (fcsr == -1) 1864 /* No way to handle; it'll most likely trap anyway. */ 1865 return pc; 1866 1867 fcs = regcache_raw_get_unsigned (regcache, fcsr); 1868 cond = ((fcs >> 24) & 0xfe) | ((fcs >> 23) & 0x01); 1869 1870 if (((cond >> cnum) & mask) != mask * !tf) 1871 pc += micromips_relative_offset16 (insn); 1872 else 1873 pc += micromips_pc_insn_size (gdbarch, pc); 1874 1875 return pc; 1876 } 1877 1878 /* Calculate the address of the next microMIPS instruction to execute 1879 after the instruction at the address PC. */ 1880 1881 static CORE_ADDR 1882 micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) 1883 { 1884 struct gdbarch *gdbarch = regcache->arch (); 1885 ULONGEST insn; 1886 1887 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1888 pc += MIPS_INSN16_SIZE; 1889 switch (mips_insn_size (ISA_MICROMIPS, insn)) 1890 { 1891 /* 32-bit instructions. */ 1892 case 2 * MIPS_INSN16_SIZE: 1893 insn <<= 16; 1894 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 1895 pc += MIPS_INSN16_SIZE; 1896 switch (micromips_op (insn >> 16)) 1897 { 1898 case 0x00: /* POOL32A: bits 000000 */ 1899 switch (b0s6_op (insn)) 1900 { 1901 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */ 1902 switch (b6s10_ext (insn)) 1903 { 1904 case 0x3c: /* JALR: 000000 0000111100 111100 */ 1905 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */ 1906 case 0x13c: /* JALRS: 000000 0100111100 111100 */ 1907 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */ 1908 pc = regcache_raw_get_signed (regcache, 1909 b0s5_reg (insn >> 16)); 1910 break; 1911 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */ 1912 { 1913 struct gdbarch_tdep *tdep; 1914 1915 tdep = gdbarch_tdep (gdbarch); 1916 if (tdep->syscall_next_pc != NULL) 1917 pc = tdep->syscall_next_pc (get_current_frame ()); 1918 } 1919 break; 1920 } 1921 break; 1922 } 1923 break; 1924 1925 case 0x10: /* POOL32I: bits 010000 */ 1926 switch (b5s5_op (insn >> 16)) 1927 { 1928 case 0x00: /* BLTZ: bits 010000 00000 */ 1929 case 0x01: /* BLTZAL: bits 010000 00001 */ 1930 case 0x11: /* BLTZALS: bits 010000 10001 */ 1931 if (regcache_raw_get_signed (regcache, 1932 b0s5_reg (insn >> 16)) < 0) 1933 pc += micromips_relative_offset16 (insn); 1934 else 1935 pc += micromips_pc_insn_size (gdbarch, pc); 1936 break; 1937 1938 case 0x02: /* BGEZ: bits 010000 00010 */ 1939 case 0x03: /* BGEZAL: bits 010000 00011 */ 1940 case 0x13: /* BGEZALS: bits 010000 10011 */ 1941 if (regcache_raw_get_signed (regcache, 1942 b0s5_reg (insn >> 16)) >= 0) 1943 pc += micromips_relative_offset16 (insn); 1944 else 1945 pc += micromips_pc_insn_size (gdbarch, pc); 1946 break; 1947 1948 case 0x04: /* BLEZ: bits 010000 00100 */ 1949 if (regcache_raw_get_signed (regcache, 1950 b0s5_reg (insn >> 16)) <= 0) 1951 pc += micromips_relative_offset16 (insn); 1952 else 1953 pc += micromips_pc_insn_size (gdbarch, pc); 1954 break; 1955 1956 case 0x05: /* BNEZC: bits 010000 00101 */ 1957 if (regcache_raw_get_signed (regcache, 1958 b0s5_reg (insn >> 16)) != 0) 1959 pc += micromips_relative_offset16 (insn); 1960 break; 1961 1962 case 0x06: /* BGTZ: bits 010000 00110 */ 1963 if (regcache_raw_get_signed (regcache, 1964 b0s5_reg (insn >> 16)) > 0) 1965 pc += micromips_relative_offset16 (insn); 1966 else 1967 pc += micromips_pc_insn_size (gdbarch, pc); 1968 break; 1969 1970 case 0x07: /* BEQZC: bits 010000 00111 */ 1971 if (regcache_raw_get_signed (regcache, 1972 b0s5_reg (insn >> 16)) == 0) 1973 pc += micromips_relative_offset16 (insn); 1974 break; 1975 1976 case 0x14: /* BC2F: bits 010000 10100 xxx00 */ 1977 case 0x15: /* BC2T: bits 010000 10101 xxx00 */ 1978 if (((insn >> 16) & 0x3) == 0x0) 1979 /* BC2F, BC2T: don't know how to handle these. */ 1980 break; 1981 break; 1982 1983 case 0x1a: /* BPOSGE64: bits 010000 11010 */ 1984 case 0x1b: /* BPOSGE32: bits 010000 11011 */ 1985 { 1986 unsigned int pos = (b5s5_op (insn >> 16) & 1) ? 32 : 64; 1987 int dspctl = mips_regnum (gdbarch)->dspctl; 1988 1989 if (dspctl == -1) 1990 /* No way to handle; it'll most likely trap anyway. */ 1991 break; 1992 1993 if ((regcache_raw_get_unsigned (regcache, 1994 dspctl) & 0x7f) >= pos) 1995 pc += micromips_relative_offset16 (insn); 1996 else 1997 pc += micromips_pc_insn_size (gdbarch, pc); 1998 } 1999 break; 2000 2001 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ 2002 /* BC1ANY2F: bits 010000 11100 xxx01 */ 2003 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ 2004 /* BC1ANY2T: bits 010000 11101 xxx01 */ 2005 if (((insn >> 16) & 0x2) == 0x0) 2006 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 2007 ((insn >> 16) & 0x1) + 1); 2008 break; 2009 2010 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */ 2011 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */ 2012 if (((insn >> 16) & 0x3) == 0x1) 2013 pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, 4); 2014 break; 2015 } 2016 break; 2017 2018 case 0x1d: /* JALS: bits 011101 */ 2019 case 0x35: /* J: bits 110101 */ 2020 case 0x3d: /* JAL: bits 111101 */ 2021 pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); 2022 break; 2023 2024 case 0x25: /* BEQ: bits 100101 */ 2025 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) 2026 == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) 2027 pc += micromips_relative_offset16 (insn); 2028 else 2029 pc += micromips_pc_insn_size (gdbarch, pc); 2030 break; 2031 2032 case 0x2d: /* BNE: bits 101101 */ 2033 if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) 2034 != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) 2035 pc += micromips_relative_offset16 (insn); 2036 else 2037 pc += micromips_pc_insn_size (gdbarch, pc); 2038 break; 2039 2040 case 0x3c: /* JALX: bits 111100 */ 2041 pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); 2042 break; 2043 } 2044 break; 2045 2046 /* 16-bit instructions. */ 2047 case MIPS_INSN16_SIZE: 2048 switch (micromips_op (insn)) 2049 { 2050 case 0x11: /* POOL16C: bits 010001 */ 2051 if ((b5s5_op (insn) & 0x1c) == 0xc) 2052 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 2053 pc = regcache_raw_get_signed (regcache, b0s5_reg (insn)); 2054 else if (b5s5_op (insn) == 0x18) 2055 /* JRADDIUSP: bits 010001 11000 */ 2056 pc = regcache_raw_get_signed (regcache, MIPS_RA_REGNUM); 2057 break; 2058 2059 case 0x23: /* BEQZ16: bits 100011 */ 2060 { 2061 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2062 2063 if (regcache_raw_get_signed (regcache, rs) == 0) 2064 pc += micromips_relative_offset7 (insn); 2065 else 2066 pc += micromips_pc_insn_size (gdbarch, pc); 2067 } 2068 break; 2069 2070 case 0x2b: /* BNEZ16: bits 101011 */ 2071 { 2072 int rs = mips_reg3_to_reg[b7s3_reg (insn)]; 2073 2074 if (regcache_raw_get_signed (regcache, rs) != 0) 2075 pc += micromips_relative_offset7 (insn); 2076 else 2077 pc += micromips_pc_insn_size (gdbarch, pc); 2078 } 2079 break; 2080 2081 case 0x33: /* B16: bits 110011 */ 2082 pc += micromips_relative_offset10 (insn); 2083 break; 2084 } 2085 break; 2086 } 2087 2088 return pc; 2089 } 2090 2091 /* Decoding the next place to set a breakpoint is irregular for the 2092 mips 16 variant, but fortunately, there fewer instructions. We have 2093 to cope ith extensions for 16 bit instructions and a pair of actual 2094 32 bit instructions. We dont want to set a single step instruction 2095 on the extend instruction either. */ 2096 2097 /* Lots of mips16 instruction formats */ 2098 /* Predicting jumps requires itype,ritype,i8type 2099 and their extensions extItype,extritype,extI8type. */ 2100 enum mips16_inst_fmts 2101 { 2102 itype, /* 0 immediate 5,10 */ 2103 ritype, /* 1 5,3,8 */ 2104 rrtype, /* 2 5,3,3,5 */ 2105 rritype, /* 3 5,3,3,5 */ 2106 rrrtype, /* 4 5,3,3,3,2 */ 2107 rriatype, /* 5 5,3,3,1,4 */ 2108 shifttype, /* 6 5,3,3,3,2 */ 2109 i8type, /* 7 5,3,8 */ 2110 i8movtype, /* 8 5,3,3,5 */ 2111 i8mov32rtype, /* 9 5,3,5,3 */ 2112 i64type, /* 10 5,3,8 */ 2113 ri64type, /* 11 5,3,3,5 */ 2114 jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ 2115 exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ 2116 extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ 2117 extRRItype, /* 15 5,5,5,5,3,3,5 */ 2118 extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ 2119 EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ 2120 extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ 2121 extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ 2122 extRi64type, /* 20 5,6,5,5,3,3,5 */ 2123 extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ 2124 }; 2125 /* I am heaping all the fields of the formats into one structure and 2126 then, only the fields which are involved in instruction extension. */ 2127 struct upk_mips16 2128 { 2129 CORE_ADDR offset; 2130 unsigned int regx; /* Function in i8 type. */ 2131 unsigned int regy; 2132 }; 2133 2134 2135 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format 2136 for the bits which make up the immediate extension. */ 2137 2138 static CORE_ADDR 2139 extended_offset (unsigned int extension) 2140 { 2141 CORE_ADDR value; 2142 2143 value = (extension >> 16) & 0x1f; /* Extract 15:11. */ 2144 value = value << 6; 2145 value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ 2146 value = value << 5; 2147 value |= extension & 0x1f; /* Extract 4:0. */ 2148 2149 return value; 2150 } 2151 2152 /* Only call this function if you know that this is an extendable 2153 instruction. It won't malfunction, but why make excess remote memory 2154 references? If the immediate operands get sign extended or something, 2155 do it after the extension is performed. */ 2156 /* FIXME: Every one of these cases needs to worry about sign extension 2157 when the offset is to be used in relative addressing. */ 2158 2159 static unsigned int 2160 fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) 2161 { 2162 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2163 gdb_byte buf[8]; 2164 2165 pc = unmake_compact_addr (pc); /* Clear the low order bit. */ 2166 target_read_memory (pc, buf, 2); 2167 return extract_unsigned_integer (buf, 2, byte_order); 2168 } 2169 2170 static void 2171 unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, 2172 unsigned int extension, 2173 unsigned int inst, 2174 enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) 2175 { 2176 CORE_ADDR offset; 2177 int regx; 2178 int regy; 2179 switch (insn_format) 2180 { 2181 case itype: 2182 { 2183 CORE_ADDR value; 2184 if (extension) 2185 { 2186 value = extended_offset ((extension << 16) | inst); 2187 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2188 } 2189 else 2190 { 2191 value = inst & 0x7ff; 2192 value = (value ^ 0x400) - 0x400; /* Sign-extend. */ 2193 } 2194 offset = value; 2195 regx = -1; 2196 regy = -1; 2197 } 2198 break; 2199 case ritype: 2200 case i8type: 2201 { /* A register identifier and an offset. */ 2202 /* Most of the fields are the same as I type but the 2203 immediate value is of a different length. */ 2204 CORE_ADDR value; 2205 if (extension) 2206 { 2207 value = extended_offset ((extension << 16) | inst); 2208 value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ 2209 } 2210 else 2211 { 2212 value = inst & 0xff; /* 8 bits */ 2213 value = (value ^ 0x80) - 0x80; /* Sign-extend. */ 2214 } 2215 offset = value; 2216 regx = (inst >> 8) & 0x07; /* i8 funct */ 2217 regy = -1; 2218 break; 2219 } 2220 case jalxtype: 2221 { 2222 unsigned long value; 2223 unsigned int nexthalf; 2224 value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); 2225 value = value << 16; 2226 nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); 2227 /* Low bit still set. */ 2228 value |= nexthalf; 2229 offset = value; 2230 regx = -1; 2231 regy = -1; 2232 break; 2233 } 2234 default: 2235 internal_error (__FILE__, __LINE__, _("bad switch")); 2236 } 2237 upk->offset = offset; 2238 upk->regx = regx; 2239 upk->regy = regy; 2240 } 2241 2242 2243 /* Calculate the destination of a branch whose 16-bit opcode word is at PC, 2244 and having a signed 16-bit OFFSET. */ 2245 2246 static CORE_ADDR 2247 add_offset_16 (CORE_ADDR pc, int offset) 2248 { 2249 return pc + (offset << 1) + 2; 2250 } 2251 2252 static CORE_ADDR 2253 extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, 2254 unsigned int extension, unsigned int insn) 2255 { 2256 struct gdbarch *gdbarch = regcache->arch (); 2257 int op = (insn >> 11); 2258 switch (op) 2259 { 2260 case 2: /* Branch */ 2261 { 2262 struct upk_mips16 upk; 2263 unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); 2264 pc = add_offset_16 (pc, upk.offset); 2265 break; 2266 } 2267 case 3: /* JAL , JALX - Watch out, these are 32 bit 2268 instructions. */ 2269 { 2270 struct upk_mips16 upk; 2271 unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); 2272 pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); 2273 if ((insn >> 10) & 0x01) /* Exchange mode */ 2274 pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ 2275 else 2276 pc |= 0x01; 2277 break; 2278 } 2279 case 4: /* beqz */ 2280 { 2281 struct upk_mips16 upk; 2282 int reg; 2283 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2284 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); 2285 if (reg == 0) 2286 pc = add_offset_16 (pc, upk.offset); 2287 else 2288 pc += 2; 2289 break; 2290 } 2291 case 5: /* bnez */ 2292 { 2293 struct upk_mips16 upk; 2294 int reg; 2295 unpack_mips16 (gdbarch, pc, extension, insn, ritype, &upk); 2296 reg = regcache_raw_get_signed (regcache, mips_reg3_to_reg[upk.regx]); 2297 if (reg != 0) 2298 pc = add_offset_16 (pc, upk.offset); 2299 else 2300 pc += 2; 2301 break; 2302 } 2303 case 12: /* I8 Formats btez btnez */ 2304 { 2305 struct upk_mips16 upk; 2306 int reg; 2307 unpack_mips16 (gdbarch, pc, extension, insn, i8type, &upk); 2308 /* upk.regx contains the opcode */ 2309 /* Test register is 24 */ 2310 reg = regcache_raw_get_signed (regcache, 24); 2311 if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ 2312 || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ 2313 pc = add_offset_16 (pc, upk.offset); 2314 else 2315 pc += 2; 2316 break; 2317 } 2318 case 29: /* RR Formats JR, JALR, JALR-RA */ 2319 { 2320 struct upk_mips16 upk; 2321 /* upk.fmt = rrtype; */ 2322 op = insn & 0x1f; 2323 if (op == 0) 2324 { 2325 int reg; 2326 upk.regx = (insn >> 8) & 0x07; 2327 upk.regy = (insn >> 5) & 0x07; 2328 if ((upk.regy & 1) == 0) 2329 reg = mips_reg3_to_reg[upk.regx]; 2330 else 2331 reg = 31; /* Function return instruction. */ 2332 pc = regcache_raw_get_signed (regcache, reg); 2333 } 2334 else 2335 pc += 2; 2336 break; 2337 } 2338 case 30: 2339 /* This is an instruction extension. Fetch the real instruction 2340 (which follows the extension) and decode things based on 2341 that. */ 2342 { 2343 pc += 2; 2344 pc = extended_mips16_next_pc (regcache, pc, insn, 2345 fetch_mips_16 (gdbarch, pc)); 2346 break; 2347 } 2348 default: 2349 { 2350 pc += 2; 2351 break; 2352 } 2353 } 2354 return pc; 2355 } 2356 2357 static CORE_ADDR 2358 mips16_next_pc (struct regcache *regcache, CORE_ADDR pc) 2359 { 2360 struct gdbarch *gdbarch = regcache->arch (); 2361 unsigned int insn = fetch_mips_16 (gdbarch, pc); 2362 return extended_mips16_next_pc (regcache, pc, 0, insn); 2363 } 2364 2365 /* The mips_next_pc function supports single_step when the remote 2366 target monitor or stub is not developed enough to do a single_step. 2367 It works by decoding the current instruction and predicting where a 2368 branch will go. This isn't hard because all the data is available. 2369 The MIPS32, MIPS16 and microMIPS variants are quite different. */ 2370 static CORE_ADDR 2371 mips_next_pc (struct regcache *regcache, CORE_ADDR pc) 2372 { 2373 struct gdbarch *gdbarch = regcache->arch (); 2374 2375 if (mips_pc_is_mips16 (gdbarch, pc)) 2376 return mips16_next_pc (regcache, pc); 2377 else if (mips_pc_is_micromips (gdbarch, pc)) 2378 return micromips_next_pc (regcache, pc); 2379 else 2380 return mips32_next_pc (regcache, pc); 2381 } 2382 2383 /* Return non-zero if the MIPS16 instruction INSN is a compact branch 2384 or jump. */ 2385 2386 static int 2387 mips16_instruction_is_compact_branch (unsigned short insn) 2388 { 2389 switch (insn & 0xf800) 2390 { 2391 case 0xe800: 2392 return (insn & 0x009f) == 0x80; /* JALRC/JRC */ 2393 case 0x6000: 2394 return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ 2395 case 0x2800: /* BNEZ */ 2396 case 0x2000: /* BEQZ */ 2397 case 0x1000: /* B */ 2398 return 1; 2399 default: 2400 return 0; 2401 } 2402 } 2403 2404 /* Return non-zero if the microMIPS instruction INSN is a compact branch 2405 or jump. */ 2406 2407 static int 2408 micromips_instruction_is_compact_branch (unsigned short insn) 2409 { 2410 switch (micromips_op (insn)) 2411 { 2412 case 0x11: /* POOL16C: bits 010001 */ 2413 return (b5s5_op (insn) == 0x18 2414 /* JRADDIUSP: bits 010001 11000 */ 2415 || b5s5_op (insn) == 0xd); 2416 /* JRC: bits 010011 01101 */ 2417 case 0x10: /* POOL32I: bits 010000 */ 2418 return (b5s5_op (insn) & 0x1d) == 0x5; 2419 /* BEQZC/BNEZC: bits 010000 001x1 */ 2420 default: 2421 return 0; 2422 } 2423 } 2424 2425 struct mips_frame_cache 2426 { 2427 CORE_ADDR base; 2428 struct trad_frame_saved_reg *saved_regs; 2429 }; 2430 2431 /* Set a register's saved stack address in temp_saved_regs. If an 2432 address has already been set for this register, do nothing; this 2433 way we will only recognize the first save of a given register in a 2434 function prologue. 2435 2436 For simplicity, save the address in both [0 .. gdbarch_num_regs) and 2437 [gdbarch_num_regs .. 2*gdbarch_num_regs). 2438 Strictly speaking, only the second range is used as it is only second 2439 range (the ABI instead of ISA registers) that comes into play when finding 2440 saved registers in a frame. */ 2441 2442 static void 2443 set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, 2444 int regnum, CORE_ADDR offset) 2445 { 2446 if (this_cache != NULL 2447 && this_cache->saved_regs[regnum].addr == -1) 2448 { 2449 this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)].addr 2450 = offset; 2451 this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)].addr 2452 = offset; 2453 } 2454 } 2455 2456 2457 /* Fetch the immediate value from a MIPS16 instruction. 2458 If the previous instruction was an EXTEND, use it to extend 2459 the upper bits of the immediate value. This is a helper function 2460 for mips16_scan_prologue. */ 2461 2462 static int 2463 mips16_get_imm (unsigned short prev_inst, /* previous instruction */ 2464 unsigned short inst, /* current instruction */ 2465 int nbits, /* number of bits in imm field */ 2466 int scale, /* scale factor to be applied to imm */ 2467 int is_signed) /* is the imm field signed? */ 2468 { 2469 int offset; 2470 2471 if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ 2472 { 2473 offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); 2474 if (offset & 0x8000) /* check for negative extend */ 2475 offset = 0 - (0x10000 - (offset & 0xffff)); 2476 return offset | (inst & 0x1f); 2477 } 2478 else 2479 { 2480 int max_imm = 1 << nbits; 2481 int mask = max_imm - 1; 2482 int sign_bit = max_imm >> 1; 2483 2484 offset = inst & mask; 2485 if (is_signed && (offset & sign_bit)) 2486 offset = 0 - (max_imm - offset); 2487 return offset * scale; 2488 } 2489 } 2490 2491 2492 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 2493 the associated FRAME_CACHE if not null. 2494 Return the address of the first instruction past the prologue. */ 2495 2496 static CORE_ADDR 2497 mips16_scan_prologue (struct gdbarch *gdbarch, 2498 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2499 struct frame_info *this_frame, 2500 struct mips_frame_cache *this_cache) 2501 { 2502 int prev_non_prologue_insn = 0; 2503 int this_non_prologue_insn; 2504 int non_prologue_insns = 0; 2505 CORE_ADDR prev_pc; 2506 CORE_ADDR cur_pc; 2507 CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ 2508 CORE_ADDR sp; 2509 long frame_offset = 0; /* Size of stack frame. */ 2510 long frame_adjust = 0; /* Offset of FP from SP. */ 2511 int frame_reg = MIPS_SP_REGNUM; 2512 unsigned short prev_inst = 0; /* saved copy of previous instruction. */ 2513 unsigned inst = 0; /* current instruction */ 2514 unsigned entry_inst = 0; /* the entry instruction */ 2515 unsigned save_inst = 0; /* the save instruction */ 2516 int prev_delay_slot = 0; 2517 int in_delay_slot; 2518 int reg, offset; 2519 2520 int extend_bytes = 0; 2521 int prev_extend_bytes = 0; 2522 CORE_ADDR end_prologue_addr; 2523 2524 /* Can be called when there's no process, and hence when there's no 2525 THIS_FRAME. */ 2526 if (this_frame != NULL) 2527 sp = get_frame_register_signed (this_frame, 2528 gdbarch_num_regs (gdbarch) 2529 + MIPS_SP_REGNUM); 2530 else 2531 sp = 0; 2532 2533 if (limit_pc > start_pc + 200) 2534 limit_pc = start_pc + 200; 2535 prev_pc = start_pc; 2536 2537 /* Permit at most one non-prologue non-control-transfer instruction 2538 in the middle which may have been reordered by the compiler for 2539 optimisation. */ 2540 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN16_SIZE) 2541 { 2542 this_non_prologue_insn = 0; 2543 in_delay_slot = 0; 2544 2545 /* Save the previous instruction. If it's an EXTEND, we'll extract 2546 the immediate offset extension from it in mips16_get_imm. */ 2547 prev_inst = inst; 2548 2549 /* Fetch and decode the instruction. */ 2550 inst = (unsigned short) mips_fetch_instruction (gdbarch, ISA_MIPS16, 2551 cur_pc, NULL); 2552 2553 /* Normally we ignore extend instructions. However, if it is 2554 not followed by a valid prologue instruction, then this 2555 instruction is not part of the prologue either. We must 2556 remember in this case to adjust the end_prologue_addr back 2557 over the extend. */ 2558 if ((inst & 0xf800) == 0xf000) /* extend */ 2559 { 2560 extend_bytes = MIPS_INSN16_SIZE; 2561 continue; 2562 } 2563 2564 prev_extend_bytes = extend_bytes; 2565 extend_bytes = 0; 2566 2567 if ((inst & 0xff00) == 0x6300 /* addiu sp */ 2568 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 2569 { 2570 offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); 2571 if (offset < 0) /* Negative stack adjustment? */ 2572 frame_offset -= offset; 2573 else 2574 /* Exit loop if a positive stack adjustment is found, which 2575 usually means that the stack cleanup code in the function 2576 epilogue is reached. */ 2577 break; 2578 } 2579 else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ 2580 { 2581 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2582 reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; 2583 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2584 } 2585 else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ 2586 { 2587 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2588 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2589 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2590 } 2591 else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ 2592 { 2593 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2594 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2595 } 2596 else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ 2597 { 2598 offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); 2599 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2600 } 2601 else if (inst == 0x673d) /* move $s1, $sp */ 2602 { 2603 frame_addr = sp; 2604 frame_reg = 17; 2605 } 2606 else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ 2607 { 2608 offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); 2609 frame_addr = sp + offset; 2610 frame_reg = 17; 2611 frame_adjust = offset; 2612 } 2613 else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ 2614 { 2615 offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); 2616 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2617 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2618 } 2619 else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ 2620 { 2621 offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); 2622 reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; 2623 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 2624 } 2625 else if ((inst & 0xf81f) == 0xe809 2626 && (inst & 0x700) != 0x700) /* entry */ 2627 entry_inst = inst; /* Save for later processing. */ 2628 else if ((inst & 0xff80) == 0x6480) /* save */ 2629 { 2630 save_inst = inst; /* Save for later processing. */ 2631 if (prev_extend_bytes) /* extend */ 2632 save_inst |= prev_inst << 16; 2633 } 2634 else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ 2635 { 2636 /* This instruction is part of the prologue, but we don't 2637 need to do anything special to handle it. */ 2638 } 2639 else if (mips16_instruction_has_delay_slot (inst, 0)) 2640 /* JAL/JALR/JALX/JR */ 2641 { 2642 /* The instruction in the delay slot can be a part 2643 of the prologue, so move forward once more. */ 2644 in_delay_slot = 1; 2645 if (mips16_instruction_has_delay_slot (inst, 1)) 2646 /* JAL/JALX */ 2647 { 2648 prev_extend_bytes = MIPS_INSN16_SIZE; 2649 cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ 2650 } 2651 } 2652 else 2653 { 2654 this_non_prologue_insn = 1; 2655 } 2656 2657 non_prologue_insns += this_non_prologue_insn; 2658 2659 /* A jump or branch, or enough non-prologue insns seen? If so, 2660 then we must have reached the end of the prologue by now. */ 2661 if (prev_delay_slot || non_prologue_insns > 1 2662 || mips16_instruction_is_compact_branch (inst)) 2663 break; 2664 2665 prev_non_prologue_insn = this_non_prologue_insn; 2666 prev_delay_slot = in_delay_slot; 2667 prev_pc = cur_pc - prev_extend_bytes; 2668 } 2669 2670 /* The entry instruction is typically the first instruction in a function, 2671 and it stores registers at offsets relative to the value of the old SP 2672 (before the prologue). But the value of the sp parameter to this 2673 function is the new SP (after the prologue has been executed). So we 2674 can't calculate those offsets until we've seen the entire prologue, 2675 and can calculate what the old SP must have been. */ 2676 if (entry_inst != 0) 2677 { 2678 int areg_count = (entry_inst >> 8) & 7; 2679 int sreg_count = (entry_inst >> 6) & 3; 2680 2681 /* The entry instruction always subtracts 32 from the SP. */ 2682 frame_offset += 32; 2683 2684 /* Now we can calculate what the SP must have been at the 2685 start of the function prologue. */ 2686 sp += frame_offset; 2687 2688 /* Check if a0-a3 were saved in the caller's argument save area. */ 2689 for (reg = 4, offset = 0; reg < areg_count + 4; reg++) 2690 { 2691 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2692 offset += mips_abi_regsize (gdbarch); 2693 } 2694 2695 /* Check if the ra register was pushed on the stack. */ 2696 offset = -4; 2697 if (entry_inst & 0x20) 2698 { 2699 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2700 offset -= mips_abi_regsize (gdbarch); 2701 } 2702 2703 /* Check if the s0 and s1 registers were pushed on the stack. */ 2704 for (reg = 16; reg < sreg_count + 16; reg++) 2705 { 2706 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2707 offset -= mips_abi_regsize (gdbarch); 2708 } 2709 } 2710 2711 /* The SAVE instruction is similar to ENTRY, except that defined by the 2712 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the 2713 size of the frame is specified as an immediate field of instruction 2714 and an extended variation exists which lets additional registers and 2715 frame space to be specified. The instruction always treats registers 2716 as 32-bit so its usefulness for 64-bit ABIs is questionable. */ 2717 if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) 2718 { 2719 static int args_table[16] = { 2720 0, 0, 0, 0, 1, 1, 1, 1, 2721 2, 2, 2, 0, 3, 3, 4, -1, 2722 }; 2723 static int astatic_table[16] = { 2724 0, 1, 2, 3, 0, 1, 2, 3, 2725 0, 1, 2, 4, 0, 1, 0, -1, 2726 }; 2727 int aregs = (save_inst >> 16) & 0xf; 2728 int xsregs = (save_inst >> 24) & 0x7; 2729 int args = args_table[aregs]; 2730 int astatic = astatic_table[aregs]; 2731 long frame_size; 2732 2733 if (args < 0) 2734 { 2735 warning (_("Invalid number of argument registers encoded in SAVE.")); 2736 args = 0; 2737 } 2738 if (astatic < 0) 2739 { 2740 warning (_("Invalid number of static registers encoded in SAVE.")); 2741 astatic = 0; 2742 } 2743 2744 /* For standard SAVE the frame size of 0 means 128. */ 2745 frame_size = ((save_inst >> 16) & 0xf0) | (save_inst & 0xf); 2746 if (frame_size == 0 && (save_inst >> 16) == 0) 2747 frame_size = 16; 2748 frame_size *= 8; 2749 frame_offset += frame_size; 2750 2751 /* Now we can calculate what the SP must have been at the 2752 start of the function prologue. */ 2753 sp += frame_offset; 2754 2755 /* Check if A0-A3 were saved in the caller's argument save area. */ 2756 for (reg = MIPS_A0_REGNUM, offset = 0; reg < args + 4; reg++) 2757 { 2758 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2759 offset += mips_abi_regsize (gdbarch); 2760 } 2761 2762 offset = -4; 2763 2764 /* Check if the RA register was pushed on the stack. */ 2765 if (save_inst & 0x40) 2766 { 2767 set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); 2768 offset -= mips_abi_regsize (gdbarch); 2769 } 2770 2771 /* Check if the S8 register was pushed on the stack. */ 2772 if (xsregs > 6) 2773 { 2774 set_reg_offset (gdbarch, this_cache, 30, sp + offset); 2775 offset -= mips_abi_regsize (gdbarch); 2776 xsregs--; 2777 } 2778 /* Check if S2-S7 were pushed on the stack. */ 2779 for (reg = 18 + xsregs - 1; reg > 18 - 1; reg--) 2780 { 2781 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2782 offset -= mips_abi_regsize (gdbarch); 2783 } 2784 2785 /* Check if the S1 register was pushed on the stack. */ 2786 if (save_inst & 0x10) 2787 { 2788 set_reg_offset (gdbarch, this_cache, 17, sp + offset); 2789 offset -= mips_abi_regsize (gdbarch); 2790 } 2791 /* Check if the S0 register was pushed on the stack. */ 2792 if (save_inst & 0x20) 2793 { 2794 set_reg_offset (gdbarch, this_cache, 16, sp + offset); 2795 offset -= mips_abi_regsize (gdbarch); 2796 } 2797 2798 /* Check if A0-A3 were pushed on the stack. */ 2799 for (reg = MIPS_A0_REGNUM + 3; reg > MIPS_A0_REGNUM + 3 - astatic; reg--) 2800 { 2801 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 2802 offset -= mips_abi_regsize (gdbarch); 2803 } 2804 } 2805 2806 if (this_cache != NULL) 2807 { 2808 this_cache->base = 2809 (get_frame_register_signed (this_frame, 2810 gdbarch_num_regs (gdbarch) + frame_reg) 2811 + frame_offset - frame_adjust); 2812 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 2813 be able to get rid of the assignment below, evetually. But it's 2814 still needed for now. */ 2815 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 2816 + mips_regnum (gdbarch)->pc] 2817 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 2818 } 2819 2820 /* Set end_prologue_addr to the address of the instruction immediately 2821 after the last one we scanned. Unless the last one looked like a 2822 non-prologue instruction (and we looked ahead), in which case use 2823 its address instead. */ 2824 end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot 2825 ? prev_pc : cur_pc - prev_extend_bytes); 2826 2827 return end_prologue_addr; 2828 } 2829 2830 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16). 2831 Procedures that use the 32-bit instruction set are handled by the 2832 mips_insn32 unwinder. */ 2833 2834 static struct mips_frame_cache * 2835 mips_insn16_frame_cache (struct frame_info *this_frame, void **this_cache) 2836 { 2837 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2838 struct mips_frame_cache *cache; 2839 2840 if ((*this_cache) != NULL) 2841 return (struct mips_frame_cache *) (*this_cache); 2842 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 2843 (*this_cache) = cache; 2844 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 2845 2846 /* Analyze the function prologue. */ 2847 { 2848 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 2849 CORE_ADDR start_addr; 2850 2851 find_pc_partial_function (pc, NULL, &start_addr, NULL); 2852 if (start_addr == 0) 2853 start_addr = heuristic_proc_start (gdbarch, pc); 2854 /* We can't analyze the prologue if we couldn't find the begining 2855 of the function. */ 2856 if (start_addr == 0) 2857 return cache; 2858 2859 mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, 2860 (struct mips_frame_cache *) *this_cache); 2861 } 2862 2863 /* gdbarch_sp_regnum contains the value and not the address. */ 2864 trad_frame_set_value (cache->saved_regs, 2865 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 2866 cache->base); 2867 2868 return (struct mips_frame_cache *) (*this_cache); 2869 } 2870 2871 static void 2872 mips_insn16_frame_this_id (struct frame_info *this_frame, void **this_cache, 2873 struct frame_id *this_id) 2874 { 2875 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2876 this_cache); 2877 /* This marks the outermost frame. */ 2878 if (info->base == 0) 2879 return; 2880 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 2881 } 2882 2883 static struct value * 2884 mips_insn16_frame_prev_register (struct frame_info *this_frame, 2885 void **this_cache, int regnum) 2886 { 2887 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2888 this_cache); 2889 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 2890 } 2891 2892 static int 2893 mips_insn16_frame_sniffer (const struct frame_unwind *self, 2894 struct frame_info *this_frame, void **this_cache) 2895 { 2896 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2897 CORE_ADDR pc = get_frame_pc (this_frame); 2898 if (mips_pc_is_mips16 (gdbarch, pc)) 2899 return 1; 2900 return 0; 2901 } 2902 2903 static const struct frame_unwind mips_insn16_frame_unwind = 2904 { 2905 NORMAL_FRAME, 2906 default_frame_unwind_stop_reason, 2907 mips_insn16_frame_this_id, 2908 mips_insn16_frame_prev_register, 2909 NULL, 2910 mips_insn16_frame_sniffer 2911 }; 2912 2913 static CORE_ADDR 2914 mips_insn16_frame_base_address (struct frame_info *this_frame, 2915 void **this_cache) 2916 { 2917 struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, 2918 this_cache); 2919 return info->base; 2920 } 2921 2922 static const struct frame_base mips_insn16_frame_base = 2923 { 2924 &mips_insn16_frame_unwind, 2925 mips_insn16_frame_base_address, 2926 mips_insn16_frame_base_address, 2927 mips_insn16_frame_base_address 2928 }; 2929 2930 static const struct frame_base * 2931 mips_insn16_frame_base_sniffer (struct frame_info *this_frame) 2932 { 2933 struct gdbarch *gdbarch = get_frame_arch (this_frame); 2934 CORE_ADDR pc = get_frame_pc (this_frame); 2935 if (mips_pc_is_mips16 (gdbarch, pc)) 2936 return &mips_insn16_frame_base; 2937 else 2938 return NULL; 2939 } 2940 2941 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped 2942 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are 2943 interpreted directly, and then multiplied by 4. */ 2944 2945 static int 2946 micromips_decode_imm9 (int imm) 2947 { 2948 imm = (imm ^ 0x100) - 0x100; 2949 if (imm > -3 && imm < 2) 2950 imm ^= 0x100; 2951 return imm << 2; 2952 } 2953 2954 /* Analyze the function prologue from START_PC to LIMIT_PC. Return 2955 the address of the first instruction past the prologue. */ 2956 2957 static CORE_ADDR 2958 micromips_scan_prologue (struct gdbarch *gdbarch, 2959 CORE_ADDR start_pc, CORE_ADDR limit_pc, 2960 struct frame_info *this_frame, 2961 struct mips_frame_cache *this_cache) 2962 { 2963 CORE_ADDR end_prologue_addr; 2964 int prev_non_prologue_insn = 0; 2965 int frame_reg = MIPS_SP_REGNUM; 2966 int this_non_prologue_insn; 2967 int non_prologue_insns = 0; 2968 long frame_offset = 0; /* Size of stack frame. */ 2969 long frame_adjust = 0; /* Offset of FP from SP. */ 2970 int prev_delay_slot = 0; 2971 int in_delay_slot; 2972 CORE_ADDR prev_pc; 2973 CORE_ADDR cur_pc; 2974 ULONGEST insn; /* current instruction */ 2975 CORE_ADDR sp; 2976 long offset; 2977 long sp_adj; 2978 long v1_off = 0; /* The assumption is LUI will replace it. */ 2979 int reglist; 2980 int breg; 2981 int dreg; 2982 int sreg; 2983 int treg; 2984 int loc; 2985 int op; 2986 int s; 2987 int i; 2988 2989 /* Can be called when there's no process, and hence when there's no 2990 THIS_FRAME. */ 2991 if (this_frame != NULL) 2992 sp = get_frame_register_signed (this_frame, 2993 gdbarch_num_regs (gdbarch) 2994 + MIPS_SP_REGNUM); 2995 else 2996 sp = 0; 2997 2998 if (limit_pc > start_pc + 200) 2999 limit_pc = start_pc + 200; 3000 prev_pc = start_pc; 3001 3002 /* Permit at most one non-prologue non-control-transfer instruction 3003 in the middle which may have been reordered by the compiler for 3004 optimisation. */ 3005 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += loc) 3006 { 3007 this_non_prologue_insn = 0; 3008 in_delay_slot = 0; 3009 sp_adj = 0; 3010 loc = 0; 3011 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc, NULL); 3012 loc += MIPS_INSN16_SIZE; 3013 switch (mips_insn_size (ISA_MICROMIPS, insn)) 3014 { 3015 /* 32-bit instructions. */ 3016 case 2 * MIPS_INSN16_SIZE: 3017 insn <<= 16; 3018 insn |= mips_fetch_instruction (gdbarch, 3019 ISA_MICROMIPS, cur_pc + loc, NULL); 3020 loc += MIPS_INSN16_SIZE; 3021 switch (micromips_op (insn >> 16)) 3022 { 3023 /* Record $sp/$fp adjustment. */ 3024 /* Discard (D)ADDU $gp,$jp used for PIC code. */ 3025 case 0x0: /* POOL32A: bits 000000 */ 3026 case 0x16: /* POOL32S: bits 010110 */ 3027 op = b0s11_op (insn); 3028 sreg = b0s5_reg (insn >> 16); 3029 treg = b5s5_reg (insn >> 16); 3030 dreg = b11s5_reg (insn); 3031 if (op == 0x1d0 3032 /* SUBU: bits 000000 00111010000 */ 3033 /* DSUBU: bits 010110 00111010000 */ 3034 && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM 3035 && treg == 3) 3036 /* (D)SUBU $sp, $v1 */ 3037 sp_adj = v1_off; 3038 else if (op != 0x150 3039 /* ADDU: bits 000000 00101010000 */ 3040 /* DADDU: bits 010110 00101010000 */ 3041 || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) 3042 this_non_prologue_insn = 1; 3043 break; 3044 3045 case 0x8: /* POOL32B: bits 001000 */ 3046 op = b12s4_op (insn); 3047 breg = b0s5_reg (insn >> 16); 3048 reglist = sreg = b5s5_reg (insn >> 16); 3049 offset = (b0s12_imm (insn) ^ 0x800) - 0x800; 3050 if ((op == 0x9 || op == 0xc) 3051 /* SWP: bits 001000 1001 */ 3052 /* SDP: bits 001000 1100 */ 3053 && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) 3054 /* S[DW]P reg,offset($sp) */ 3055 { 3056 s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); 3057 set_reg_offset (gdbarch, this_cache, 3058 sreg, sp + offset); 3059 set_reg_offset (gdbarch, this_cache, 3060 sreg + 1, sp + offset + s); 3061 } 3062 else if ((op == 0xd || op == 0xf) 3063 /* SWM: bits 001000 1101 */ 3064 /* SDM: bits 001000 1111 */ 3065 && breg == MIPS_SP_REGNUM 3066 /* SWM reglist,offset($sp) */ 3067 && ((reglist >= 1 && reglist <= 9) 3068 || (reglist >= 16 && reglist <= 25))) 3069 { 3070 int sreglist = std::min(reglist & 0xf, 8); 3071 3072 s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); 3073 for (i = 0; i < sreglist; i++) 3074 set_reg_offset (gdbarch, this_cache, 16 + i, sp + s * i); 3075 if ((reglist & 0xf) > 8) 3076 set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); 3077 if ((reglist & 0x10) == 0x10) 3078 set_reg_offset (gdbarch, this_cache, 3079 MIPS_RA_REGNUM, sp + s * i++); 3080 } 3081 else 3082 this_non_prologue_insn = 1; 3083 break; 3084 3085 /* Record $sp/$fp adjustment. */ 3086 /* Discard (D)ADDIU $gp used for PIC code. */ 3087 case 0xc: /* ADDIU: bits 001100 */ 3088 case 0x17: /* DADDIU: bits 010111 */ 3089 sreg = b0s5_reg (insn >> 16); 3090 dreg = b5s5_reg (insn >> 16); 3091 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3092 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) 3093 /* (D)ADDIU $sp, imm */ 3094 sp_adj = offset; 3095 else if (sreg == MIPS_SP_REGNUM && dreg == 30) 3096 /* (D)ADDIU $fp, $sp, imm */ 3097 { 3098 frame_adjust = offset; 3099 frame_reg = 30; 3100 } 3101 else if (sreg != 28 || dreg != 28) 3102 /* (D)ADDIU $gp, imm */ 3103 this_non_prologue_insn = 1; 3104 break; 3105 3106 /* LUI $v1 is used for larger $sp adjustments. */ 3107 /* Discard LUI $gp used for PIC code. */ 3108 case 0x10: /* POOL32I: bits 010000 */ 3109 if (b5s5_op (insn >> 16) == 0xd 3110 /* LUI: bits 010000 001101 */ 3111 && b0s5_reg (insn >> 16) == 3) 3112 /* LUI $v1, imm */ 3113 v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; 3114 else if (b5s5_op (insn >> 16) != 0xd 3115 /* LUI: bits 010000 001101 */ 3116 || b0s5_reg (insn >> 16) != 28) 3117 /* LUI $gp, imm */ 3118 this_non_prologue_insn = 1; 3119 break; 3120 3121 /* ORI $v1 is used for larger $sp adjustments. */ 3122 case 0x14: /* ORI: bits 010100 */ 3123 sreg = b0s5_reg (insn >> 16); 3124 dreg = b5s5_reg (insn >> 16); 3125 if (sreg == 3 && dreg == 3) 3126 /* ORI $v1, imm */ 3127 v1_off |= b0s16_imm (insn); 3128 else 3129 this_non_prologue_insn = 1; 3130 break; 3131 3132 case 0x26: /* SWC1: bits 100110 */ 3133 case 0x2e: /* SDC1: bits 101110 */ 3134 breg = b0s5_reg (insn >> 16); 3135 if (breg != MIPS_SP_REGNUM) 3136 /* S[DW]C1 reg,offset($sp) */ 3137 this_non_prologue_insn = 1; 3138 break; 3139 3140 case 0x36: /* SD: bits 110110 */ 3141 case 0x3e: /* SW: bits 111110 */ 3142 breg = b0s5_reg (insn >> 16); 3143 sreg = b5s5_reg (insn >> 16); 3144 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 3145 if (breg == MIPS_SP_REGNUM) 3146 /* S[DW] reg,offset($sp) */ 3147 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3148 else 3149 this_non_prologue_insn = 1; 3150 break; 3151 3152 default: 3153 /* The instruction in the delay slot can be a part 3154 of the prologue, so move forward once more. */ 3155 if (micromips_instruction_has_delay_slot (insn, 0)) 3156 in_delay_slot = 1; 3157 else 3158 this_non_prologue_insn = 1; 3159 break; 3160 } 3161 insn >>= 16; 3162 break; 3163 3164 /* 16-bit instructions. */ 3165 case MIPS_INSN16_SIZE: 3166 switch (micromips_op (insn)) 3167 { 3168 case 0x3: /* MOVE: bits 000011 */ 3169 sreg = b0s5_reg (insn); 3170 dreg = b5s5_reg (insn); 3171 if (sreg == MIPS_SP_REGNUM && dreg == 30) 3172 /* MOVE $fp, $sp */ 3173 frame_reg = 30; 3174 else if ((sreg & 0x1c) != 0x4) 3175 /* MOVE reg, $a0-$a3 */ 3176 this_non_prologue_insn = 1; 3177 break; 3178 3179 case 0x11: /* POOL16C: bits 010001 */ 3180 if (b6s4_op (insn) == 0x5) 3181 /* SWM: bits 010001 0101 */ 3182 { 3183 offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; 3184 reglist = b4s2_regl (insn); 3185 for (i = 0; i <= reglist; i++) 3186 set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); 3187 set_reg_offset (gdbarch, this_cache, 3188 MIPS_RA_REGNUM, sp + 4 * i++); 3189 } 3190 else 3191 this_non_prologue_insn = 1; 3192 break; 3193 3194 case 0x13: /* POOL16D: bits 010011 */ 3195 if ((insn & 0x1) == 0x1) 3196 /* ADDIUSP: bits 010011 1 */ 3197 sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); 3198 else if (b5s5_reg (insn) == MIPS_SP_REGNUM) 3199 /* ADDIUS5: bits 010011 0 */ 3200 /* ADDIUS5 $sp, imm */ 3201 sp_adj = (b1s4_imm (insn) ^ 8) - 8; 3202 else 3203 this_non_prologue_insn = 1; 3204 break; 3205 3206 case 0x32: /* SWSP: bits 110010 */ 3207 offset = b0s5_imm (insn) << 2; 3208 sreg = b5s5_reg (insn); 3209 set_reg_offset (gdbarch, this_cache, sreg, sp + offset); 3210 break; 3211 3212 default: 3213 /* The instruction in the delay slot can be a part 3214 of the prologue, so move forward once more. */ 3215 if (micromips_instruction_has_delay_slot (insn << 16, 0)) 3216 in_delay_slot = 1; 3217 else 3218 this_non_prologue_insn = 1; 3219 break; 3220 } 3221 break; 3222 } 3223 if (sp_adj < 0) 3224 frame_offset -= sp_adj; 3225 3226 non_prologue_insns += this_non_prologue_insn; 3227 3228 /* A jump or branch, enough non-prologue insns seen or positive 3229 stack adjustment? If so, then we must have reached the end 3230 of the prologue by now. */ 3231 if (prev_delay_slot || non_prologue_insns > 1 || sp_adj > 0 3232 || micromips_instruction_is_compact_branch (insn)) 3233 break; 3234 3235 prev_non_prologue_insn = this_non_prologue_insn; 3236 prev_delay_slot = in_delay_slot; 3237 prev_pc = cur_pc; 3238 } 3239 3240 if (this_cache != NULL) 3241 { 3242 this_cache->base = 3243 (get_frame_register_signed (this_frame, 3244 gdbarch_num_regs (gdbarch) + frame_reg) 3245 + frame_offset - frame_adjust); 3246 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should 3247 be able to get rid of the assignment below, evetually. But it's 3248 still needed for now. */ 3249 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3250 + mips_regnum (gdbarch)->pc] 3251 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; 3252 } 3253 3254 /* Set end_prologue_addr to the address of the instruction immediately 3255 after the last one we scanned. Unless the last one looked like a 3256 non-prologue instruction (and we looked ahead), in which case use 3257 its address instead. */ 3258 end_prologue_addr 3259 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3260 3261 return end_prologue_addr; 3262 } 3263 3264 /* Heuristic unwinder for procedures using microMIPS instructions. 3265 Procedures that use the 32-bit instruction set are handled by the 3266 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */ 3267 3268 static struct mips_frame_cache * 3269 mips_micro_frame_cache (struct frame_info *this_frame, void **this_cache) 3270 { 3271 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3272 struct mips_frame_cache *cache; 3273 3274 if ((*this_cache) != NULL) 3275 return (struct mips_frame_cache *) (*this_cache); 3276 3277 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3278 (*this_cache) = cache; 3279 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3280 3281 /* Analyze the function prologue. */ 3282 { 3283 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3284 CORE_ADDR start_addr; 3285 3286 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3287 if (start_addr == 0) 3288 start_addr = heuristic_proc_start (get_frame_arch (this_frame), pc); 3289 /* We can't analyze the prologue if we couldn't find the begining 3290 of the function. */ 3291 if (start_addr == 0) 3292 return cache; 3293 3294 micromips_scan_prologue (gdbarch, start_addr, pc, this_frame, 3295 (struct mips_frame_cache *) *this_cache); 3296 } 3297 3298 /* gdbarch_sp_regnum contains the value and not the address. */ 3299 trad_frame_set_value (cache->saved_regs, 3300 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 3301 cache->base); 3302 3303 return (struct mips_frame_cache *) (*this_cache); 3304 } 3305 3306 static void 3307 mips_micro_frame_this_id (struct frame_info *this_frame, void **this_cache, 3308 struct frame_id *this_id) 3309 { 3310 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3311 this_cache); 3312 /* This marks the outermost frame. */ 3313 if (info->base == 0) 3314 return; 3315 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3316 } 3317 3318 static struct value * 3319 mips_micro_frame_prev_register (struct frame_info *this_frame, 3320 void **this_cache, int regnum) 3321 { 3322 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3323 this_cache); 3324 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3325 } 3326 3327 static int 3328 mips_micro_frame_sniffer (const struct frame_unwind *self, 3329 struct frame_info *this_frame, void **this_cache) 3330 { 3331 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3332 CORE_ADDR pc = get_frame_pc (this_frame); 3333 3334 if (mips_pc_is_micromips (gdbarch, pc)) 3335 return 1; 3336 return 0; 3337 } 3338 3339 static const struct frame_unwind mips_micro_frame_unwind = 3340 { 3341 NORMAL_FRAME, 3342 default_frame_unwind_stop_reason, 3343 mips_micro_frame_this_id, 3344 mips_micro_frame_prev_register, 3345 NULL, 3346 mips_micro_frame_sniffer 3347 }; 3348 3349 static CORE_ADDR 3350 mips_micro_frame_base_address (struct frame_info *this_frame, 3351 void **this_cache) 3352 { 3353 struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, 3354 this_cache); 3355 return info->base; 3356 } 3357 3358 static const struct frame_base mips_micro_frame_base = 3359 { 3360 &mips_micro_frame_unwind, 3361 mips_micro_frame_base_address, 3362 mips_micro_frame_base_address, 3363 mips_micro_frame_base_address 3364 }; 3365 3366 static const struct frame_base * 3367 mips_micro_frame_base_sniffer (struct frame_info *this_frame) 3368 { 3369 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3370 CORE_ADDR pc = get_frame_pc (this_frame); 3371 3372 if (mips_pc_is_micromips (gdbarch, pc)) 3373 return &mips_micro_frame_base; 3374 else 3375 return NULL; 3376 } 3377 3378 /* Mark all the registers as unset in the saved_regs array 3379 of THIS_CACHE. Do nothing if THIS_CACHE is null. */ 3380 3381 static void 3382 reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) 3383 { 3384 if (this_cache == NULL || this_cache->saved_regs == NULL) 3385 return; 3386 3387 { 3388 const int num_regs = gdbarch_num_regs (gdbarch); 3389 int i; 3390 3391 for (i = 0; i < num_regs; i++) 3392 { 3393 this_cache->saved_regs[i].addr = -1; 3394 } 3395 } 3396 } 3397 3398 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds 3399 the associated FRAME_CACHE if not null. 3400 Return the address of the first instruction past the prologue. */ 3401 3402 static CORE_ADDR 3403 mips32_scan_prologue (struct gdbarch *gdbarch, 3404 CORE_ADDR start_pc, CORE_ADDR limit_pc, 3405 struct frame_info *this_frame, 3406 struct mips_frame_cache *this_cache) 3407 { 3408 int prev_non_prologue_insn; 3409 int this_non_prologue_insn; 3410 int non_prologue_insns; 3411 CORE_ADDR frame_addr = 0; /* Value of $r30. Used by gcc for 3412 frame-pointer. */ 3413 int prev_delay_slot; 3414 CORE_ADDR prev_pc; 3415 CORE_ADDR cur_pc; 3416 CORE_ADDR sp; 3417 long frame_offset; 3418 int frame_reg = MIPS_SP_REGNUM; 3419 3420 CORE_ADDR end_prologue_addr; 3421 int seen_sp_adjust = 0; 3422 int load_immediate_bytes = 0; 3423 int in_delay_slot; 3424 int regsize_is_64_bits = (mips_abi_regsize (gdbarch) == 8); 3425 3426 /* Can be called when there's no process, and hence when there's no 3427 THIS_FRAME. */ 3428 if (this_frame != NULL) 3429 sp = get_frame_register_signed (this_frame, 3430 gdbarch_num_regs (gdbarch) 3431 + MIPS_SP_REGNUM); 3432 else 3433 sp = 0; 3434 3435 if (limit_pc > start_pc + 200) 3436 limit_pc = start_pc + 200; 3437 3438 restart: 3439 prev_non_prologue_insn = 0; 3440 non_prologue_insns = 0; 3441 prev_delay_slot = 0; 3442 prev_pc = start_pc; 3443 3444 /* Permit at most one non-prologue non-control-transfer instruction 3445 in the middle which may have been reordered by the compiler for 3446 optimisation. */ 3447 frame_offset = 0; 3448 for (cur_pc = start_pc; cur_pc < limit_pc; cur_pc += MIPS_INSN32_SIZE) 3449 { 3450 unsigned long inst, high_word; 3451 long offset; 3452 int reg; 3453 3454 this_non_prologue_insn = 0; 3455 in_delay_slot = 0; 3456 3457 /* Fetch the instruction. */ 3458 inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, 3459 cur_pc, NULL); 3460 3461 /* Save some code by pre-extracting some useful fields. */ 3462 high_word = (inst >> 16) & 0xffff; 3463 offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; 3464 reg = high_word & 0x1f; 3465 3466 if (high_word == 0x27bd /* addiu $sp,$sp,-i */ 3467 || high_word == 0x23bd /* addi $sp,$sp,-i */ 3468 || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ 3469 { 3470 if (offset < 0) /* Negative stack adjustment? */ 3471 frame_offset -= offset; 3472 else 3473 /* Exit loop if a positive stack adjustment is found, which 3474 usually means that the stack cleanup code in the function 3475 epilogue is reached. */ 3476 break; 3477 seen_sp_adjust = 1; 3478 } 3479 else if (((high_word & 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */ 3480 && !regsize_is_64_bits) 3481 { 3482 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3483 } 3484 else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ 3485 && regsize_is_64_bits) 3486 { 3487 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ 3488 set_reg_offset (gdbarch, this_cache, reg, sp + offset); 3489 } 3490 else if (high_word == 0x27be) /* addiu $30,$sp,size */ 3491 { 3492 /* Old gcc frame, r30 is virtual frame pointer. */ 3493 if (offset != frame_offset) 3494 frame_addr = sp + offset; 3495 else if (this_frame && frame_reg == MIPS_SP_REGNUM) 3496 { 3497 unsigned alloca_adjust; 3498 3499 frame_reg = 30; 3500 frame_addr = get_frame_register_signed 3501 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3502 frame_offset = 0; 3503 3504 alloca_adjust = (unsigned) (frame_addr - (sp + offset)); 3505 if (alloca_adjust > 0) 3506 { 3507 /* FP > SP + frame_size. This may be because of 3508 an alloca or somethings similar. Fix sp to 3509 "pre-alloca" value, and try again. */ 3510 sp += alloca_adjust; 3511 /* Need to reset the status of all registers. Otherwise, 3512 we will hit a guard that prevents the new address 3513 for each register to be recomputed during the second 3514 pass. */ 3515 reset_saved_regs (gdbarch, this_cache); 3516 goto restart; 3517 } 3518 } 3519 } 3520 /* move $30,$sp. With different versions of gas this will be either 3521 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'. 3522 Accept any one of these. */ 3523 else if (inst == 0x03A0F021 || inst == 0x03a0f025 || inst == 0x03a0f02d) 3524 { 3525 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */ 3526 if (this_frame && frame_reg == MIPS_SP_REGNUM) 3527 { 3528 unsigned alloca_adjust; 3529 3530 frame_reg = 30; 3531 frame_addr = get_frame_register_signed 3532 (this_frame, gdbarch_num_regs (gdbarch) + 30); 3533 3534 alloca_adjust = (unsigned) (frame_addr - sp); 3535 if (alloca_adjust > 0) 3536 { 3537 /* FP > SP + frame_size. This may be because of 3538 an alloca or somethings similar. Fix sp to 3539 "pre-alloca" value, and try again. */ 3540 sp = frame_addr; 3541 /* Need to reset the status of all registers. Otherwise, 3542 we will hit a guard that prevents the new address 3543 for each register to be recomputed during the second 3544 pass. */ 3545 reset_saved_regs (gdbarch, this_cache); 3546 goto restart; 3547 } 3548 } 3549 } 3550 else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ 3551 && !regsize_is_64_bits) 3552 { 3553 set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); 3554 } 3555 else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ 3556 || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ 3557 || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ 3558 || high_word == 0x3c1c /* lui $gp,n */ 3559 || high_word == 0x279c /* addiu $gp,$gp,n */ 3560 || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ 3561 || inst == 0x033ce021 /* addu $gp,$t9,$gp */ 3562 ) 3563 { 3564 /* These instructions are part of the prologue, but we don't 3565 need to do anything special to handle them. */ 3566 } 3567 /* The instructions below load $at or $t0 with an immediate 3568 value in preparation for a stack adjustment via 3569 subu $sp,$sp,[$at,$t0]. These instructions could also 3570 initialize a local variable, so we accept them only before 3571 a stack adjustment instruction was seen. */ 3572 else if (!seen_sp_adjust 3573 && !prev_delay_slot 3574 && (high_word == 0x3c01 /* lui $at,n */ 3575 || high_word == 0x3c08 /* lui $t0,n */ 3576 || high_word == 0x3421 /* ori $at,$at,n */ 3577 || high_word == 0x3508 /* ori $t0,$t0,n */ 3578 || high_word == 0x3401 /* ori $at,$zero,n */ 3579 || high_word == 0x3408 /* ori $t0,$zero,n */ 3580 )) 3581 { 3582 load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ 3583 } 3584 /* Check for branches and jumps. The instruction in the delay 3585 slot can be a part of the prologue, so move forward once more. */ 3586 else if (mips32_instruction_has_delay_slot (gdbarch, inst)) 3587 { 3588 in_delay_slot = 1; 3589 } 3590 /* This instruction is not an instruction typically found 3591 in a prologue, so we must have reached the end of the 3592 prologue. */ 3593 else 3594 { 3595 this_non_prologue_insn = 1; 3596 } 3597 3598 non_prologue_insns += this_non_prologue_insn; 3599 3600 /* A jump or branch, or enough non-prologue insns seen? If so, 3601 then we must have reached the end of the prologue by now. */ 3602 if (prev_delay_slot || non_prologue_insns > 1) 3603 break; 3604 3605 prev_non_prologue_insn = this_non_prologue_insn; 3606 prev_delay_slot = in_delay_slot; 3607 prev_pc = cur_pc; 3608 } 3609 3610 if (this_cache != NULL) 3611 { 3612 this_cache->base = 3613 (get_frame_register_signed (this_frame, 3614 gdbarch_num_regs (gdbarch) + frame_reg) 3615 + frame_offset); 3616 /* FIXME: brobecker/2004-09-15: We should be able to get rid of 3617 this assignment below, eventually. But it's still needed 3618 for now. */ 3619 this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3620 + mips_regnum (gdbarch)->pc] 3621 = this_cache->saved_regs[gdbarch_num_regs (gdbarch) 3622 + MIPS_RA_REGNUM]; 3623 } 3624 3625 /* Set end_prologue_addr to the address of the instruction immediately 3626 after the last one we scanned. Unless the last one looked like a 3627 non-prologue instruction (and we looked ahead), in which case use 3628 its address instead. */ 3629 end_prologue_addr 3630 = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; 3631 3632 /* In a frameless function, we might have incorrectly 3633 skipped some load immediate instructions. Undo the skipping 3634 if the load immediate was not followed by a stack adjustment. */ 3635 if (load_immediate_bytes && !seen_sp_adjust) 3636 end_prologue_addr -= load_immediate_bytes; 3637 3638 return end_prologue_addr; 3639 } 3640 3641 /* Heuristic unwinder for procedures using 32-bit instructions (covers 3642 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit 3643 instructions (a.k.a. MIPS16) are handled by the mips_insn16 3644 unwinder. Likewise microMIPS and the mips_micro unwinder. */ 3645 3646 static struct mips_frame_cache * 3647 mips_insn32_frame_cache (struct frame_info *this_frame, void **this_cache) 3648 { 3649 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3650 struct mips_frame_cache *cache; 3651 3652 if ((*this_cache) != NULL) 3653 return (struct mips_frame_cache *) (*this_cache); 3654 3655 cache = FRAME_OBSTACK_ZALLOC (struct mips_frame_cache); 3656 (*this_cache) = cache; 3657 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame); 3658 3659 /* Analyze the function prologue. */ 3660 { 3661 const CORE_ADDR pc = get_frame_address_in_block (this_frame); 3662 CORE_ADDR start_addr; 3663 3664 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3665 if (start_addr == 0) 3666 start_addr = heuristic_proc_start (gdbarch, pc); 3667 /* We can't analyze the prologue if we couldn't find the begining 3668 of the function. */ 3669 if (start_addr == 0) 3670 return cache; 3671 3672 mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, 3673 (struct mips_frame_cache *) *this_cache); 3674 } 3675 3676 /* gdbarch_sp_regnum contains the value and not the address. */ 3677 trad_frame_set_value (cache->saved_regs, 3678 gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM, 3679 cache->base); 3680 3681 return (struct mips_frame_cache *) (*this_cache); 3682 } 3683 3684 static void 3685 mips_insn32_frame_this_id (struct frame_info *this_frame, void **this_cache, 3686 struct frame_id *this_id) 3687 { 3688 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3689 this_cache); 3690 /* This marks the outermost frame. */ 3691 if (info->base == 0) 3692 return; 3693 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame)); 3694 } 3695 3696 static struct value * 3697 mips_insn32_frame_prev_register (struct frame_info *this_frame, 3698 void **this_cache, int regnum) 3699 { 3700 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3701 this_cache); 3702 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); 3703 } 3704 3705 static int 3706 mips_insn32_frame_sniffer (const struct frame_unwind *self, 3707 struct frame_info *this_frame, void **this_cache) 3708 { 3709 CORE_ADDR pc = get_frame_pc (this_frame); 3710 if (mips_pc_is_mips (pc)) 3711 return 1; 3712 return 0; 3713 } 3714 3715 static const struct frame_unwind mips_insn32_frame_unwind = 3716 { 3717 NORMAL_FRAME, 3718 default_frame_unwind_stop_reason, 3719 mips_insn32_frame_this_id, 3720 mips_insn32_frame_prev_register, 3721 NULL, 3722 mips_insn32_frame_sniffer 3723 }; 3724 3725 static CORE_ADDR 3726 mips_insn32_frame_base_address (struct frame_info *this_frame, 3727 void **this_cache) 3728 { 3729 struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, 3730 this_cache); 3731 return info->base; 3732 } 3733 3734 static const struct frame_base mips_insn32_frame_base = 3735 { 3736 &mips_insn32_frame_unwind, 3737 mips_insn32_frame_base_address, 3738 mips_insn32_frame_base_address, 3739 mips_insn32_frame_base_address 3740 }; 3741 3742 static const struct frame_base * 3743 mips_insn32_frame_base_sniffer (struct frame_info *this_frame) 3744 { 3745 CORE_ADDR pc = get_frame_pc (this_frame); 3746 if (mips_pc_is_mips (pc)) 3747 return &mips_insn32_frame_base; 3748 else 3749 return NULL; 3750 } 3751 3752 static struct trad_frame_cache * 3753 mips_stub_frame_cache (struct frame_info *this_frame, void **this_cache) 3754 { 3755 CORE_ADDR pc; 3756 CORE_ADDR start_addr; 3757 CORE_ADDR stack_addr; 3758 struct trad_frame_cache *this_trad_cache; 3759 struct gdbarch *gdbarch = get_frame_arch (this_frame); 3760 int num_regs = gdbarch_num_regs (gdbarch); 3761 3762 if ((*this_cache) != NULL) 3763 return (struct trad_frame_cache *) (*this_cache); 3764 this_trad_cache = trad_frame_cache_zalloc (this_frame); 3765 (*this_cache) = this_trad_cache; 3766 3767 /* The return address is in the link register. */ 3768 trad_frame_set_reg_realreg (this_trad_cache, 3769 gdbarch_pc_regnum (gdbarch), 3770 num_regs + MIPS_RA_REGNUM); 3771 3772 /* Frame ID, since it's a frameless / stackless function, no stack 3773 space is allocated and SP on entry is the current SP. */ 3774 pc = get_frame_pc (this_frame); 3775 find_pc_partial_function (pc, NULL, &start_addr, NULL); 3776 stack_addr = get_frame_register_signed (this_frame, 3777 num_regs + MIPS_SP_REGNUM); 3778 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); 3779 3780 /* Assume that the frame's base is the same as the 3781 stack-pointer. */ 3782 trad_frame_set_this_base (this_trad_cache, stack_addr); 3783 3784 return this_trad_cache; 3785 } 3786 3787 static void 3788 mips_stub_frame_this_id (struct frame_info *this_frame, void **this_cache, 3789 struct frame_id *this_id) 3790 { 3791 struct trad_frame_cache *this_trad_cache 3792 = mips_stub_frame_cache (this_frame, this_cache); 3793 trad_frame_get_id (this_trad_cache, this_id); 3794 } 3795 3796 static struct value * 3797 mips_stub_frame_prev_register (struct frame_info *this_frame, 3798 void **this_cache, int regnum) 3799 { 3800 struct trad_frame_cache *this_trad_cache 3801 = mips_stub_frame_cache (this_frame, this_cache); 3802 return trad_frame_get_register (this_trad_cache, this_frame, regnum); 3803 } 3804 3805 static int 3806 mips_stub_frame_sniffer (const struct frame_unwind *self, 3807 struct frame_info *this_frame, void **this_cache) 3808 { 3809 gdb_byte dummy[4]; 3810 CORE_ADDR pc = get_frame_address_in_block (this_frame); 3811 struct bound_minimal_symbol msym; 3812 3813 /* Use the stub unwinder for unreadable code. */ 3814 if (target_read_memory (get_frame_pc (this_frame), dummy, 4) != 0) 3815 return 1; 3816 3817 if (in_plt_section (pc) || in_mips_stubs_section (pc)) 3818 return 1; 3819 3820 /* Calling a PIC function from a non-PIC function passes through a 3821 stub. The stub for foo is named ".pic.foo". */ 3822 msym = lookup_minimal_symbol_by_pc (pc); 3823 if (msym.minsym != NULL 3824 && msym.minsym->linkage_name () != NULL 3825 && startswith (msym.minsym->linkage_name (), ".pic.")) 3826 return 1; 3827 3828 return 0; 3829 } 3830 3831 static const struct frame_unwind mips_stub_frame_unwind = 3832 { 3833 NORMAL_FRAME, 3834 default_frame_unwind_stop_reason, 3835 mips_stub_frame_this_id, 3836 mips_stub_frame_prev_register, 3837 NULL, 3838 mips_stub_frame_sniffer 3839 }; 3840 3841 static CORE_ADDR 3842 mips_stub_frame_base_address (struct frame_info *this_frame, 3843 void **this_cache) 3844 { 3845 struct trad_frame_cache *this_trad_cache 3846 = mips_stub_frame_cache (this_frame, this_cache); 3847 return trad_frame_get_this_base (this_trad_cache); 3848 } 3849 3850 static const struct frame_base mips_stub_frame_base = 3851 { 3852 &mips_stub_frame_unwind, 3853 mips_stub_frame_base_address, 3854 mips_stub_frame_base_address, 3855 mips_stub_frame_base_address 3856 }; 3857 3858 static const struct frame_base * 3859 mips_stub_frame_base_sniffer (struct frame_info *this_frame) 3860 { 3861 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind, this_frame, NULL)) 3862 return &mips_stub_frame_base; 3863 else 3864 return NULL; 3865 } 3866 3867 /* mips_addr_bits_remove - remove useless address bits */ 3868 3869 static CORE_ADDR 3870 mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) 3871 { 3872 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3873 3874 if (mips_mask_address_p (tdep) && (((ULONGEST) addr) >> 32 == 0xffffffffUL)) 3875 /* This hack is a work-around for existing boards using PMON, the 3876 simulator, and any other 64-bit targets that doesn't have true 3877 64-bit addressing. On these targets, the upper 32 bits of 3878 addresses are ignored by the hardware. Thus, the PC or SP are 3879 likely to have been sign extended to all 1s by instruction 3880 sequences that load 32-bit addresses. For example, a typical 3881 piece of code that loads an address is this: 3882 3883 lui $r2, <upper 16 bits> 3884 ori $r2, <lower 16 bits> 3885 3886 But the lui sign-extends the value such that the upper 32 bits 3887 may be all 1s. The workaround is simply to mask off these 3888 bits. In the future, gcc may be changed to support true 64-bit 3889 addressing, and this masking will have to be disabled. */ 3890 return addr &= 0xffffffffUL; 3891 else 3892 return addr; 3893 } 3894 3895 3896 /* Checks for an atomic sequence of instructions beginning with a LL/LLD 3897 instruction and ending with a SC/SCD instruction. If such a sequence 3898 is found, attempt to step through it. A breakpoint is placed at the end of 3899 the sequence. */ 3900 3901 /* Instructions used during single-stepping of atomic sequences, standard 3902 ISA version. */ 3903 #define LL_OPCODE 0x30 3904 #define LLD_OPCODE 0x34 3905 #define SC_OPCODE 0x38 3906 #define SCD_OPCODE 0x3c 3907 3908 static std::vector<CORE_ADDR> 3909 mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) 3910 { 3911 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; 3912 CORE_ADDR loc = pc; 3913 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ 3914 ULONGEST insn; 3915 int insn_count; 3916 int index; 3917 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 3918 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 3919 3920 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3921 /* Assume all atomic sequences start with a ll/lld instruction. */ 3922 if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE) 3923 return {}; 3924 3925 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 3926 instructions. */ 3927 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 3928 { 3929 int is_branch = 0; 3930 loc += MIPS_INSN32_SIZE; 3931 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); 3932 3933 /* Assume that there is at most one branch in the atomic 3934 sequence. If a branch is found, put a breakpoint in its 3935 destination address. */ 3936 switch (itype_op (insn)) 3937 { 3938 case 0: /* SPECIAL */ 3939 if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ 3940 return {}; /* fallback to the standard single-step code. */ 3941 break; 3942 case 1: /* REGIMM */ 3943 is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ 3944 || ((itype_rt (insn) & 0x1e) == 0 3945 && itype_rs (insn) == 0)); /* BPOSGE* */ 3946 break; 3947 case 2: /* J */ 3948 case 3: /* JAL */ 3949 return {}; /* fallback to the standard single-step code. */ 3950 case 4: /* BEQ */ 3951 case 5: /* BNE */ 3952 case 6: /* BLEZ */ 3953 case 7: /* BGTZ */ 3954 case 20: /* BEQL */ 3955 case 21: /* BNEL */ 3956 case 22: /* BLEZL */ 3957 case 23: /* BGTTL */ 3958 is_branch = 1; 3959 break; 3960 case 17: /* COP1 */ 3961 is_branch = ((itype_rs (insn) == 9 || itype_rs (insn) == 10) 3962 && (itype_rt (insn) & 0x2) == 0); 3963 if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ 3964 break; 3965 /* Fall through. */ 3966 case 18: /* COP2 */ 3967 case 19: /* COP3 */ 3968 is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ 3969 break; 3970 } 3971 if (is_branch) 3972 { 3973 branch_bp = loc + mips32_relative_offset (insn) + 4; 3974 if (last_breakpoint >= 1) 3975 return {}; /* More than one branch found, fallback to the 3976 standard single-step code. */ 3977 breaks[1] = branch_bp; 3978 last_breakpoint++; 3979 } 3980 3981 if (itype_op (insn) == SC_OPCODE || itype_op (insn) == SCD_OPCODE) 3982 break; 3983 } 3984 3985 /* Assume that the atomic sequence ends with a sc/scd instruction. */ 3986 if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE) 3987 return {}; 3988 3989 loc += MIPS_INSN32_SIZE; 3990 3991 /* Insert a breakpoint right after the end of the atomic sequence. */ 3992 breaks[0] = loc; 3993 3994 /* Check for duplicated breakpoints. Check also for a breakpoint 3995 placed (branch instruction's destination) in the atomic sequence. */ 3996 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 3997 last_breakpoint = 0; 3998 3999 std::vector<CORE_ADDR> next_pcs; 4000 4001 /* Effectively inserts the breakpoints. */ 4002 for (index = 0; index <= last_breakpoint; index++) 4003 next_pcs.push_back (breaks[index]); 4004 4005 return next_pcs; 4006 } 4007 4008 static std::vector<CORE_ADDR> 4009 micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, 4010 CORE_ADDR pc) 4011 { 4012 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 4013 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 4014 CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; 4015 CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's 4016 destination. */ 4017 CORE_ADDR loc = pc; 4018 int sc_found = 0; 4019 ULONGEST insn; 4020 int insn_count; 4021 int index; 4022 4023 /* Assume all atomic sequences start with a ll/lld instruction. */ 4024 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4025 if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ 4026 return {}; 4027 loc += MIPS_INSN16_SIZE; 4028 insn <<= 16; 4029 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4030 if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ 4031 return {}; 4032 loc += MIPS_INSN16_SIZE; 4033 4034 /* Assume all atomic sequences end with an sc/scd instruction. Assume 4035 that no atomic sequence is longer than "atomic_sequence_length" 4036 instructions. */ 4037 for (insn_count = 0; 4038 !sc_found && insn_count < atomic_sequence_length; 4039 ++insn_count) 4040 { 4041 int is_branch = 0; 4042 4043 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); 4044 loc += MIPS_INSN16_SIZE; 4045 4046 /* Assume that there is at most one conditional branch in the 4047 atomic sequence. If a branch is found, put a breakpoint in 4048 its destination address. */ 4049 switch (mips_insn_size (ISA_MICROMIPS, insn)) 4050 { 4051 /* 32-bit instructions. */ 4052 case 2 * MIPS_INSN16_SIZE: 4053 switch (micromips_op (insn)) 4054 { 4055 case 0x10: /* POOL32I: bits 010000 */ 4056 if ((b5s5_op (insn) & 0x18) != 0x0 4057 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 4058 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ 4059 && (b5s5_op (insn) & 0x1d) != 0x11 4060 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 4061 && ((b5s5_op (insn) & 0x1e) != 0x14 4062 || (insn & 0x3) != 0x0) 4063 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 4064 && (b5s5_op (insn) & 0x1e) != 0x1a 4065 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 4066 && ((b5s5_op (insn) & 0x1e) != 0x1c 4067 || (insn & 0x3) != 0x0) 4068 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 4069 && ((b5s5_op (insn) & 0x1c) != 0x1c 4070 || (insn & 0x3) != 0x1)) 4071 /* BC1ANY*: bits 010000 111xx xxx01 */ 4072 break; 4073 /* Fall through. */ 4074 4075 case 0x25: /* BEQ: bits 100101 */ 4076 case 0x2d: /* BNE: bits 101101 */ 4077 insn <<= 16; 4078 insn |= mips_fetch_instruction (gdbarch, 4079 ISA_MICROMIPS, loc, NULL); 4080 branch_bp = (loc + MIPS_INSN16_SIZE 4081 + micromips_relative_offset16 (insn)); 4082 is_branch = 1; 4083 break; 4084 4085 case 0x00: /* POOL32A: bits 000000 */ 4086 insn <<= 16; 4087 insn |= mips_fetch_instruction (gdbarch, 4088 ISA_MICROMIPS, loc, NULL); 4089 if (b0s6_op (insn) != 0x3c 4090 /* POOL32Axf: bits 000000 ... 111100 */ 4091 || (b6s10_ext (insn) & 0x2bf) != 0x3c) 4092 /* JALR, JALR.HB: 000000 000x111100 111100 */ 4093 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 4094 break; 4095 /* Fall through. */ 4096 4097 case 0x1d: /* JALS: bits 011101 */ 4098 case 0x35: /* J: bits 110101 */ 4099 case 0x3d: /* JAL: bits 111101 */ 4100 case 0x3c: /* JALX: bits 111100 */ 4101 return {}; /* Fall back to the standard single-step code. */ 4102 4103 case 0x18: /* POOL32C: bits 011000 */ 4104 if ((b12s4_op (insn) & 0xb) == 0xb) 4105 /* SC, SCD: bits 011000 1x11 */ 4106 sc_found = 1; 4107 break; 4108 } 4109 loc += MIPS_INSN16_SIZE; 4110 break; 4111 4112 /* 16-bit instructions. */ 4113 case MIPS_INSN16_SIZE: 4114 switch (micromips_op (insn)) 4115 { 4116 case 0x23: /* BEQZ16: bits 100011 */ 4117 case 0x2b: /* BNEZ16: bits 101011 */ 4118 branch_bp = loc + micromips_relative_offset7 (insn); 4119 is_branch = 1; 4120 break; 4121 4122 case 0x11: /* POOL16C: bits 010001 */ 4123 if ((b5s5_op (insn) & 0x1c) != 0xc 4124 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ 4125 && b5s5_op (insn) != 0x18) 4126 /* JRADDIUSP: bits 010001 11000 */ 4127 break; 4128 return {}; /* Fall back to the standard single-step code. */ 4129 4130 case 0x33: /* B16: bits 110011 */ 4131 return {}; /* Fall back to the standard single-step code. */ 4132 } 4133 break; 4134 } 4135 if (is_branch) 4136 { 4137 if (last_breakpoint >= 1) 4138 return {}; /* More than one branch found, fallback to the 4139 standard single-step code. */ 4140 breaks[1] = branch_bp; 4141 last_breakpoint++; 4142 } 4143 } 4144 if (!sc_found) 4145 return {}; 4146 4147 /* Insert a breakpoint right after the end of the atomic sequence. */ 4148 breaks[0] = loc; 4149 4150 /* Check for duplicated breakpoints. Check also for a breakpoint 4151 placed (branch instruction's destination) in the atomic sequence */ 4152 if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0]) 4153 last_breakpoint = 0; 4154 4155 std::vector<CORE_ADDR> next_pcs; 4156 4157 /* Effectively inserts the breakpoints. */ 4158 for (index = 0; index <= last_breakpoint; index++) 4159 next_pcs.push_back (breaks[index]); 4160 4161 return next_pcs; 4162 } 4163 4164 static std::vector<CORE_ADDR> 4165 deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) 4166 { 4167 if (mips_pc_is_mips (pc)) 4168 return mips_deal_with_atomic_sequence (gdbarch, pc); 4169 else if (mips_pc_is_micromips (gdbarch, pc)) 4170 return micromips_deal_with_atomic_sequence (gdbarch, pc); 4171 else 4172 return {}; 4173 } 4174 4175 /* mips_software_single_step() is called just before we want to resume 4176 the inferior, if we want to single-step it but there is no hardware 4177 or kernel single-step support (MIPS on GNU/Linux for example). We find 4178 the target of the coming instruction and breakpoint it. */ 4179 4180 std::vector<CORE_ADDR> 4181 mips_software_single_step (struct regcache *regcache) 4182 { 4183 struct gdbarch *gdbarch = regcache->arch (); 4184 CORE_ADDR pc, next_pc; 4185 4186 pc = regcache_read_pc (regcache); 4187 std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc); 4188 4189 if (!next_pcs.empty ()) 4190 return next_pcs; 4191 4192 next_pc = mips_next_pc (regcache, pc); 4193 4194 return {next_pc}; 4195 } 4196 4197 /* Test whether the PC points to the return instruction at the 4198 end of a function. */ 4199 4200 static int 4201 mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) 4202 { 4203 ULONGEST insn; 4204 ULONGEST hint; 4205 4206 /* This used to check for MIPS16, but this piece of code is never 4207 called for MIPS16 functions. And likewise microMIPS ones. */ 4208 gdb_assert (mips_pc_is_mips (pc)); 4209 4210 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 4211 hint = 0x7c0; 4212 return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ 4213 } 4214 4215 4216 /* This fencepost looks highly suspicious to me. Removing it also 4217 seems suspicious as it could affect remote debugging across serial 4218 lines. */ 4219 4220 static CORE_ADDR 4221 heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) 4222 { 4223 CORE_ADDR start_pc; 4224 CORE_ADDR fence; 4225 int instlen; 4226 int seen_adjsp = 0; 4227 struct inferior *inf; 4228 4229 pc = gdbarch_addr_bits_remove (gdbarch, pc); 4230 start_pc = pc; 4231 fence = start_pc - heuristic_fence_post; 4232 if (start_pc == 0) 4233 return 0; 4234 4235 if (heuristic_fence_post == -1 || fence < VM_MIN_ADDRESS) 4236 fence = VM_MIN_ADDRESS; 4237 4238 instlen = mips_pc_is_mips (pc) ? MIPS_INSN32_SIZE : MIPS_INSN16_SIZE; 4239 4240 inf = current_inferior (); 4241 4242 /* Search back for previous return. */ 4243 for (start_pc -= instlen;; start_pc -= instlen) 4244 if (start_pc < fence) 4245 { 4246 /* It's not clear to me why we reach this point when 4247 stop_soon, but with this test, at least we 4248 don't print out warnings for every child forked (eg, on 4249 decstation). 22apr93 rich@cygnus.com. */ 4250 if (inf->control.stop_soon == NO_STOP_QUIETLY) 4251 { 4252 static int blurb_printed = 0; 4253 4254 warning (_("GDB can't find the start of the function at %s."), 4255 paddress (gdbarch, pc)); 4256 4257 if (!blurb_printed) 4258 { 4259 /* This actually happens frequently in embedded 4260 development, when you first connect to a board 4261 and your stack pointer and pc are nowhere in 4262 particular. This message needs to give people 4263 in that situation enough information to 4264 determine that it's no big deal. */ 4265 printf_filtered ("\n\ 4266 GDB is unable to find the start of the function at %s\n\ 4267 and thus can't determine the size of that function's stack frame.\n\ 4268 This means that GDB may be unable to access that stack frame, or\n\ 4269 the frames below it.\n\ 4270 This problem is most likely caused by an invalid program counter or\n\ 4271 stack pointer.\n\ 4272 However, if you think GDB should simply search farther back\n\ 4273 from %s for code which looks like the beginning of a\n\ 4274 function, you can increase the range of the search using the `set\n\ 4275 heuristic-fence-post' command.\n", 4276 paddress (gdbarch, pc), paddress (gdbarch, pc)); 4277 blurb_printed = 1; 4278 } 4279 } 4280 4281 return 0; 4282 } 4283 else if (mips_pc_is_mips16 (gdbarch, start_pc)) 4284 { 4285 unsigned short inst; 4286 4287 /* On MIPS16, any one of the following is likely to be the 4288 start of a function: 4289 extend save 4290 save 4291 entry 4292 addiu sp,-n 4293 daddiu sp,-n 4294 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ 4295 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); 4296 if ((inst & 0xff80) == 0x6480) /* save */ 4297 { 4298 if (start_pc - instlen >= fence) 4299 { 4300 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, 4301 start_pc - instlen, NULL); 4302 if ((inst & 0xf800) == 0xf000) /* extend */ 4303 start_pc -= instlen; 4304 } 4305 break; 4306 } 4307 else if (((inst & 0xf81f) == 0xe809 4308 && (inst & 0x700) != 0x700) /* entry */ 4309 || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ 4310 || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ 4311 || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ 4312 break; 4313 else if ((inst & 0xff00) == 0x6300 /* addiu sp */ 4314 || (inst & 0xff00) == 0xfb00) /* daddiu sp */ 4315 seen_adjsp = 1; 4316 else 4317 seen_adjsp = 0; 4318 } 4319 else if (mips_pc_is_micromips (gdbarch, start_pc)) 4320 { 4321 ULONGEST insn; 4322 int stop = 0; 4323 long offset; 4324 int dreg; 4325 int sreg; 4326 4327 /* On microMIPS, any one of the following is likely to be the 4328 start of a function: 4329 ADDIUSP -imm 4330 (D)ADDIU $sp, -imm 4331 LUI $gp, imm */ 4332 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 4333 switch (micromips_op (insn)) 4334 { 4335 case 0xc: /* ADDIU: bits 001100 */ 4336 case 0x17: /* DADDIU: bits 010111 */ 4337 sreg = b0s5_reg (insn); 4338 dreg = b5s5_reg (insn); 4339 insn <<= 16; 4340 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, 4341 pc + MIPS_INSN16_SIZE, NULL); 4342 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 4343 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 4344 /* (D)ADDIU $sp, imm */ 4345 && offset < 0) 4346 stop = 1; 4347 break; 4348 4349 case 0x10: /* POOL32I: bits 010000 */ 4350 if (b5s5_op (insn) == 0xd 4351 /* LUI: bits 010000 001101 */ 4352 && b0s5_reg (insn >> 16) == 28) 4353 /* LUI $gp, imm */ 4354 stop = 1; 4355 break; 4356 4357 case 0x13: /* POOL16D: bits 010011 */ 4358 if ((insn & 0x1) == 0x1) 4359 /* ADDIUSP: bits 010011 1 */ 4360 { 4361 offset = micromips_decode_imm9 (b1s9_imm (insn)); 4362 if (offset < 0) 4363 /* ADDIUSP -imm */ 4364 stop = 1; 4365 } 4366 else 4367 /* ADDIUS5: bits 010011 0 */ 4368 { 4369 dreg = b5s5_reg (insn); 4370 offset = (b1s4_imm (insn) ^ 8) - 8; 4371 if (dreg == MIPS_SP_REGNUM && offset < 0) 4372 /* ADDIUS5 $sp, -imm */ 4373 stop = 1; 4374 } 4375 break; 4376 } 4377 if (stop) 4378 break; 4379 } 4380 else if (mips_about_to_return (gdbarch, start_pc)) 4381 { 4382 /* Skip return and its delay slot. */ 4383 start_pc += 2 * MIPS_INSN32_SIZE; 4384 break; 4385 } 4386 4387 return start_pc; 4388 } 4389 4390 struct mips_objfile_private 4391 { 4392 bfd_size_type size; 4393 char *contents; 4394 }; 4395 4396 /* According to the current ABI, should the type be passed in a 4397 floating-point register (assuming that there is space)? When there 4398 is no FPU, FP are not even considered as possible candidates for 4399 FP registers and, consequently this returns false - forces FP 4400 arguments into integer registers. */ 4401 4402 static int 4403 fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, 4404 struct type *arg_type) 4405 { 4406 return ((typecode == TYPE_CODE_FLT 4407 || (MIPS_EABI (gdbarch) 4408 && (typecode == TYPE_CODE_STRUCT 4409 || typecode == TYPE_CODE_UNION) 4410 && arg_type->num_fields () == 1 4411 && check_typedef (arg_type->field (0).type ())->code () 4412 == TYPE_CODE_FLT)) 4413 && MIPS_FPU_TYPE(gdbarch) != MIPS_FPU_NONE); 4414 } 4415 4416 /* On o32, argument passing in GPRs depends on the alignment of the type being 4417 passed. Return 1 if this type must be aligned to a doubleword boundary. */ 4418 4419 static int 4420 mips_type_needs_double_align (struct type *type) 4421 { 4422 enum type_code typecode = type->code (); 4423 4424 if (typecode == TYPE_CODE_FLT && TYPE_LENGTH (type) == 8) 4425 return 1; 4426 else if (typecode == TYPE_CODE_STRUCT) 4427 { 4428 if (type->num_fields () < 1) 4429 return 0; 4430 return mips_type_needs_double_align (type->field (0).type ()); 4431 } 4432 else if (typecode == TYPE_CODE_UNION) 4433 { 4434 int i, n; 4435 4436 n = type->num_fields (); 4437 for (i = 0; i < n; i++) 4438 if (mips_type_needs_double_align (type->field (i).type ())) 4439 return 1; 4440 return 0; 4441 } 4442 return 0; 4443 } 4444 4445 /* Adjust the address downward (direction of stack growth) so that it 4446 is correctly aligned for a new stack frame. */ 4447 static CORE_ADDR 4448 mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 4449 { 4450 return align_down (addr, 16); 4451 } 4452 4453 /* Implement the "push_dummy_code" gdbarch method. */ 4454 4455 static CORE_ADDR 4456 mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, 4457 CORE_ADDR funaddr, struct value **args, 4458 int nargs, struct type *value_type, 4459 CORE_ADDR *real_pc, CORE_ADDR *bp_addr, 4460 struct regcache *regcache) 4461 { 4462 static gdb_byte nop_insn[] = { 0, 0, 0, 0 }; 4463 CORE_ADDR nop_addr; 4464 CORE_ADDR bp_slot; 4465 4466 /* Reserve enough room on the stack for our breakpoint instruction. */ 4467 bp_slot = sp - sizeof (nop_insn); 4468 4469 /* Return to microMIPS mode if calling microMIPS code to avoid 4470 triggering an address error exception on processors that only 4471 support microMIPS execution. */ 4472 *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) 4473 ? make_compact_addr (bp_slot) : bp_slot); 4474 4475 /* The breakpoint layer automatically adjusts the address of 4476 breakpoints inserted in a branch delay slot. With enough 4477 bad luck, the 4 bytes located just before our breakpoint 4478 instruction could look like a branch instruction, and thus 4479 trigger the adjustement, and break the function call entirely. 4480 So, we reserve those 4 bytes and write a nop instruction 4481 to prevent that from happening. */ 4482 nop_addr = bp_slot - sizeof (nop_insn); 4483 write_memory (nop_addr, nop_insn, sizeof (nop_insn)); 4484 sp = mips_frame_align (gdbarch, nop_addr); 4485 4486 /* Inferior resumes at the function entry point. */ 4487 *real_pc = funaddr; 4488 4489 return sp; 4490 } 4491 4492 static CORE_ADDR 4493 mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4494 struct regcache *regcache, CORE_ADDR bp_addr, 4495 int nargs, struct value **args, CORE_ADDR sp, 4496 function_call_return_method return_method, 4497 CORE_ADDR struct_addr) 4498 { 4499 int argreg; 4500 int float_argreg; 4501 int argnum; 4502 int arg_space = 0; 4503 int stack_offset = 0; 4504 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4505 CORE_ADDR func_addr = find_function_addr (function, NULL); 4506 int abi_regsize = mips_abi_regsize (gdbarch); 4507 4508 /* For shared libraries, "t9" needs to point at the function 4509 address. */ 4510 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4511 4512 /* Set the return address register to point to the entry point of 4513 the program, where a breakpoint lies in wait. */ 4514 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4515 4516 /* First ensure that the stack and structure return address (if any) 4517 are properly aligned. The stack has to be at least 64-bit 4518 aligned even on 32-bit machines, because doubles must be 64-bit 4519 aligned. For n32 and n64, stack frames need to be 128-bit 4520 aligned, so we round to this widest known alignment. */ 4521 4522 sp = align_down (sp, 16); 4523 struct_addr = align_down (struct_addr, 16); 4524 4525 /* Now make space on the stack for the args. We allocate more 4526 than necessary for EABI, because the first few arguments are 4527 passed in registers, but that's OK. */ 4528 for (argnum = 0; argnum < nargs; argnum++) 4529 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), abi_regsize); 4530 sp -= align_up (arg_space, 16); 4531 4532 if (mips_debug) 4533 fprintf_unfiltered (gdb_stdlog, 4534 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", 4535 paddress (gdbarch, sp), 4536 (long) align_up (arg_space, 16)); 4537 4538 /* Initialize the integer and float register pointers. */ 4539 argreg = MIPS_A0_REGNUM; 4540 float_argreg = mips_fpa0_regnum (gdbarch); 4541 4542 /* The struct_return pointer occupies the first parameter-passing reg. */ 4543 if (return_method == return_method_struct) 4544 { 4545 if (mips_debug) 4546 fprintf_unfiltered (gdb_stdlog, 4547 "mips_eabi_push_dummy_call: " 4548 "struct_return reg=%d %s\n", 4549 argreg, paddress (gdbarch, struct_addr)); 4550 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4551 } 4552 4553 /* Now load as many as possible of the first arguments into 4554 registers, and push the rest onto the stack. Loop thru args 4555 from first to last. */ 4556 for (argnum = 0; argnum < nargs; argnum++) 4557 { 4558 const gdb_byte *val; 4559 /* This holds the address of structures that are passed by 4560 reference. */ 4561 gdb_byte ref_valbuf[MAX_MIPS_ABI_REGSIZE]; 4562 struct value *arg = args[argnum]; 4563 struct type *arg_type = check_typedef (value_type (arg)); 4564 int len = TYPE_LENGTH (arg_type); 4565 enum type_code typecode = arg_type->code (); 4566 4567 if (mips_debug) 4568 fprintf_unfiltered (gdb_stdlog, 4569 "mips_eabi_push_dummy_call: %d len=%d type=%d", 4570 argnum + 1, len, (int) typecode); 4571 4572 /* The EABI passes structures that do not fit in a register by 4573 reference. */ 4574 if (len > abi_regsize 4575 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 4576 { 4577 gdb_assert (abi_regsize <= ARRAY_SIZE (ref_valbuf)); 4578 store_unsigned_integer (ref_valbuf, abi_regsize, byte_order, 4579 value_address (arg)); 4580 typecode = TYPE_CODE_PTR; 4581 len = abi_regsize; 4582 val = ref_valbuf; 4583 if (mips_debug) 4584 fprintf_unfiltered (gdb_stdlog, " push"); 4585 } 4586 else 4587 val = value_contents (arg); 4588 4589 /* 32-bit ABIs always start floating point arguments in an 4590 even-numbered floating point register. Round the FP register 4591 up before the check to see if there are any FP registers 4592 left. Non MIPS_EABI targets also pass the FP in the integer 4593 registers so also round up normal registers. */ 4594 if (abi_regsize < 8 && fp_register_arg_p (gdbarch, typecode, arg_type)) 4595 { 4596 if ((float_argreg & 1)) 4597 float_argreg++; 4598 } 4599 4600 /* Floating point arguments passed in registers have to be 4601 treated specially. On 32-bit architectures, doubles 4602 are passed in register pairs; the even register gets 4603 the low word, and the odd register gets the high word. 4604 On non-EABI processors, the first two floating point arguments are 4605 also copied to general registers, because MIPS16 functions 4606 don't use float registers for arguments. This duplication of 4607 arguments in general registers can't hurt non-MIPS16 functions 4608 because those registers are normally skipped. */ 4609 /* MIPS_EABI squeezes a struct that contains a single floating 4610 point value into an FP register instead of pushing it onto the 4611 stack. */ 4612 if (fp_register_arg_p (gdbarch, typecode, arg_type) 4613 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 4614 { 4615 /* EABI32 will pass doubles in consecutive registers, even on 4616 64-bit cores. At one time, we used to check the size of 4617 `float_argreg' to determine whether or not to pass doubles 4618 in consecutive registers, but this is not sufficient for 4619 making the ABI determination. */ 4620 if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) 4621 { 4622 int low_offset = gdbarch_byte_order (gdbarch) 4623 == BFD_ENDIAN_BIG ? 4 : 0; 4624 long regval; 4625 4626 /* Write the low word of the double to the even register(s). */ 4627 regval = extract_signed_integer (val + low_offset, 4628 4, byte_order); 4629 if (mips_debug) 4630 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4631 float_argreg, phex (regval, 4)); 4632 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4633 4634 /* Write the high word of the double to the odd register(s). */ 4635 regval = extract_signed_integer (val + 4 - low_offset, 4636 4, byte_order); 4637 if (mips_debug) 4638 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4639 float_argreg, phex (regval, 4)); 4640 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4641 } 4642 else 4643 { 4644 /* This is a floating point value that fits entirely 4645 in a single register. */ 4646 /* On 32 bit ABI's the float_argreg is further adjusted 4647 above to ensure that it is even register aligned. */ 4648 LONGEST regval = extract_signed_integer (val, len, byte_order); 4649 if (mips_debug) 4650 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4651 float_argreg, phex (regval, len)); 4652 regcache_cooked_write_signed (regcache, float_argreg++, regval); 4653 } 4654 } 4655 else 4656 { 4657 /* Copy the argument to general registers or the stack in 4658 register-sized pieces. Large arguments are split between 4659 registers and stack. */ 4660 /* Note: structs whose size is not a multiple of abi_regsize 4661 are treated specially: Irix cc passes 4662 them in registers where gcc sometimes puts them on the 4663 stack. For maximum compatibility, we will put them in 4664 both places. */ 4665 int odd_sized_struct = (len > abi_regsize && len % abi_regsize != 0); 4666 4667 /* Note: Floating-point values that didn't fit into an FP 4668 register are only written to memory. */ 4669 while (len > 0) 4670 { 4671 /* Remember if the argument was written to the stack. */ 4672 int stack_used_p = 0; 4673 int partial_len = (len < abi_regsize ? len : abi_regsize); 4674 4675 if (mips_debug) 4676 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 4677 partial_len); 4678 4679 /* Write this portion of the argument to the stack. */ 4680 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 4681 || odd_sized_struct 4682 || fp_register_arg_p (gdbarch, typecode, arg_type)) 4683 { 4684 /* Should shorter than int integer values be 4685 promoted to int before being stored? */ 4686 int longword_offset = 0; 4687 CORE_ADDR addr; 4688 stack_used_p = 1; 4689 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 4690 { 4691 if (abi_regsize == 8 4692 && (typecode == TYPE_CODE_INT 4693 || typecode == TYPE_CODE_PTR 4694 || typecode == TYPE_CODE_FLT) && len <= 4) 4695 longword_offset = abi_regsize - len; 4696 else if ((typecode == TYPE_CODE_STRUCT 4697 || typecode == TYPE_CODE_UNION) 4698 && TYPE_LENGTH (arg_type) < abi_regsize) 4699 longword_offset = abi_regsize - len; 4700 } 4701 4702 if (mips_debug) 4703 { 4704 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 4705 paddress (gdbarch, stack_offset)); 4706 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 4707 paddress (gdbarch, longword_offset)); 4708 } 4709 4710 addr = sp + stack_offset + longword_offset; 4711 4712 if (mips_debug) 4713 { 4714 int i; 4715 fprintf_unfiltered (gdb_stdlog, " @%s ", 4716 paddress (gdbarch, addr)); 4717 for (i = 0; i < partial_len; i++) 4718 { 4719 fprintf_unfiltered (gdb_stdlog, "%02x", 4720 val[i] & 0xff); 4721 } 4722 } 4723 write_memory (addr, val, partial_len); 4724 } 4725 4726 /* Note!!! This is NOT an else clause. Odd sized 4727 structs may go thru BOTH paths. Floating point 4728 arguments will not. */ 4729 /* Write this portion of the argument to a general 4730 purpose register. */ 4731 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch) 4732 && !fp_register_arg_p (gdbarch, typecode, arg_type)) 4733 { 4734 LONGEST regval = 4735 extract_signed_integer (val, partial_len, byte_order); 4736 4737 if (mips_debug) 4738 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 4739 argreg, 4740 phex (regval, abi_regsize)); 4741 regcache_cooked_write_signed (regcache, argreg, regval); 4742 argreg++; 4743 } 4744 4745 len -= partial_len; 4746 val += partial_len; 4747 4748 /* Compute the offset into the stack at which we will 4749 copy the next parameter. 4750 4751 In the new EABI (and the NABI32), the stack_offset 4752 only needs to be adjusted when it has been used. */ 4753 4754 if (stack_used_p) 4755 stack_offset += align_up (partial_len, abi_regsize); 4756 } 4757 } 4758 if (mips_debug) 4759 fprintf_unfiltered (gdb_stdlog, "\n"); 4760 } 4761 4762 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 4763 4764 /* Return adjusted stack pointer. */ 4765 return sp; 4766 } 4767 4768 /* Determine the return value convention being used. */ 4769 4770 static enum return_value_convention 4771 mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, 4772 struct type *type, struct regcache *regcache, 4773 gdb_byte *readbuf, const gdb_byte *writebuf) 4774 { 4775 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 4776 int fp_return_type = 0; 4777 int offset, regnum, xfer; 4778 4779 if (TYPE_LENGTH (type) > 2 * mips_abi_regsize (gdbarch)) 4780 return RETURN_VALUE_STRUCT_CONVENTION; 4781 4782 /* Floating point type? */ 4783 if (tdep->mips_fpu_type != MIPS_FPU_NONE) 4784 { 4785 if (type->code () == TYPE_CODE_FLT) 4786 fp_return_type = 1; 4787 /* Structs with a single field of float type 4788 are returned in a floating point register. */ 4789 if ((type->code () == TYPE_CODE_STRUCT 4790 || type->code () == TYPE_CODE_UNION) 4791 && type->num_fields () == 1) 4792 { 4793 struct type *fieldtype = type->field (0).type (); 4794 4795 if (check_typedef (fieldtype)->code () == TYPE_CODE_FLT) 4796 fp_return_type = 1; 4797 } 4798 } 4799 4800 if (fp_return_type) 4801 { 4802 /* A floating-point value belongs in the least significant part 4803 of FP0/FP1. */ 4804 if (mips_debug) 4805 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 4806 regnum = mips_regnum (gdbarch)->fp0; 4807 } 4808 else 4809 { 4810 /* An integer value goes in V0/V1. */ 4811 if (mips_debug) 4812 fprintf_unfiltered (gdb_stderr, "Return scalar in $v0\n"); 4813 regnum = MIPS_V0_REGNUM; 4814 } 4815 for (offset = 0; 4816 offset < TYPE_LENGTH (type); 4817 offset += mips_abi_regsize (gdbarch), regnum++) 4818 { 4819 xfer = mips_abi_regsize (gdbarch); 4820 if (offset + xfer > TYPE_LENGTH (type)) 4821 xfer = TYPE_LENGTH (type) - offset; 4822 mips_xfer_register (gdbarch, regcache, 4823 gdbarch_num_regs (gdbarch) + regnum, xfer, 4824 gdbarch_byte_order (gdbarch), readbuf, writebuf, 4825 offset); 4826 } 4827 4828 return RETURN_VALUE_REGISTER_CONVENTION; 4829 } 4830 4831 4832 /* N32/N64 ABI stuff. */ 4833 4834 /* Search for a naturally aligned double at OFFSET inside a struct 4835 ARG_TYPE. The N32 / N64 ABIs pass these in floating point 4836 registers. */ 4837 4838 static int 4839 mips_n32n64_fp_arg_chunk_p (struct gdbarch *gdbarch, struct type *arg_type, 4840 int offset) 4841 { 4842 int i; 4843 4844 if (arg_type->code () != TYPE_CODE_STRUCT) 4845 return 0; 4846 4847 if (MIPS_FPU_TYPE (gdbarch) != MIPS_FPU_DOUBLE) 4848 return 0; 4849 4850 if (TYPE_LENGTH (arg_type) < offset + MIPS64_REGSIZE) 4851 return 0; 4852 4853 for (i = 0; i < arg_type->num_fields (); i++) 4854 { 4855 int pos; 4856 struct type *field_type; 4857 4858 /* We're only looking at normal fields. */ 4859 if (field_is_static (&arg_type->field (i)) 4860 || (TYPE_FIELD_BITPOS (arg_type, i) % 8) != 0) 4861 continue; 4862 4863 /* If we have gone past the offset, there is no double to pass. */ 4864 pos = TYPE_FIELD_BITPOS (arg_type, i) / 8; 4865 if (pos > offset) 4866 return 0; 4867 4868 field_type = check_typedef (arg_type->field (i).type ()); 4869 4870 /* If this field is entirely before the requested offset, go 4871 on to the next one. */ 4872 if (pos + TYPE_LENGTH (field_type) <= offset) 4873 continue; 4874 4875 /* If this is our special aligned double, we can stop. */ 4876 if (field_type->code () == TYPE_CODE_FLT 4877 && TYPE_LENGTH (field_type) == MIPS64_REGSIZE) 4878 return 1; 4879 4880 /* This field starts at or before the requested offset, and 4881 overlaps it. If it is a structure, recurse inwards. */ 4882 return mips_n32n64_fp_arg_chunk_p (gdbarch, field_type, offset - pos); 4883 } 4884 4885 return 0; 4886 } 4887 4888 static CORE_ADDR 4889 mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 4890 struct regcache *regcache, CORE_ADDR bp_addr, 4891 int nargs, struct value **args, CORE_ADDR sp, 4892 function_call_return_method return_method, 4893 CORE_ADDR struct_addr) 4894 { 4895 int argreg; 4896 int float_argreg; 4897 int argnum; 4898 int arg_space = 0; 4899 int stack_offset = 0; 4900 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 4901 CORE_ADDR func_addr = find_function_addr (function, NULL); 4902 4903 /* For shared libraries, "t9" needs to point at the function 4904 address. */ 4905 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 4906 4907 /* Set the return address register to point to the entry point of 4908 the program, where a breakpoint lies in wait. */ 4909 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 4910 4911 /* First ensure that the stack and structure return address (if any) 4912 are properly aligned. The stack has to be at least 64-bit 4913 aligned even on 32-bit machines, because doubles must be 64-bit 4914 aligned. For n32 and n64, stack frames need to be 128-bit 4915 aligned, so we round to this widest known alignment. */ 4916 4917 sp = align_down (sp, 16); 4918 struct_addr = align_down (struct_addr, 16); 4919 4920 /* Now make space on the stack for the args. */ 4921 for (argnum = 0; argnum < nargs; argnum++) 4922 arg_space += align_up (TYPE_LENGTH (value_type (args[argnum])), MIPS64_REGSIZE); 4923 sp -= align_up (arg_space, 16); 4924 4925 if (mips_debug) 4926 fprintf_unfiltered (gdb_stdlog, 4927 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", 4928 paddress (gdbarch, sp), 4929 (long) align_up (arg_space, 16)); 4930 4931 /* Initialize the integer and float register pointers. */ 4932 argreg = MIPS_A0_REGNUM; 4933 float_argreg = mips_fpa0_regnum (gdbarch); 4934 4935 /* The struct_return pointer occupies the first parameter-passing reg. */ 4936 if (return_method == return_method_struct) 4937 { 4938 if (mips_debug) 4939 fprintf_unfiltered (gdb_stdlog, 4940 "mips_n32n64_push_dummy_call: " 4941 "struct_return reg=%d %s\n", 4942 argreg, paddress (gdbarch, struct_addr)); 4943 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 4944 } 4945 4946 /* Now load as many as possible of the first arguments into 4947 registers, and push the rest onto the stack. Loop thru args 4948 from first to last. */ 4949 for (argnum = 0; argnum < nargs; argnum++) 4950 { 4951 const gdb_byte *val; 4952 struct value *arg = args[argnum]; 4953 struct type *arg_type = check_typedef (value_type (arg)); 4954 int len = TYPE_LENGTH (arg_type); 4955 enum type_code typecode = arg_type->code (); 4956 4957 if (mips_debug) 4958 fprintf_unfiltered (gdb_stdlog, 4959 "mips_n32n64_push_dummy_call: %d len=%d type=%d", 4960 argnum + 1, len, (int) typecode); 4961 4962 val = value_contents (arg); 4963 4964 /* A 128-bit long double value requires an even-odd pair of 4965 floating-point registers. */ 4966 if (len == 16 4967 && fp_register_arg_p (gdbarch, typecode, arg_type) 4968 && (float_argreg & 1)) 4969 { 4970 float_argreg++; 4971 argreg++; 4972 } 4973 4974 if (fp_register_arg_p (gdbarch, typecode, arg_type) 4975 && argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 4976 { 4977 /* This is a floating point value that fits entirely 4978 in a single register or a pair of registers. */ 4979 int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 4980 LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); 4981 if (mips_debug) 4982 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4983 float_argreg, phex (regval, reglen)); 4984 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 4985 4986 if (mips_debug) 4987 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 4988 argreg, phex (regval, reglen)); 4989 regcache_cooked_write_unsigned (regcache, argreg, regval); 4990 float_argreg++; 4991 argreg++; 4992 if (len == 16) 4993 { 4994 regval = extract_unsigned_integer (val + reglen, 4995 reglen, byte_order); 4996 if (mips_debug) 4997 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 4998 float_argreg, phex (regval, reglen)); 4999 regcache_cooked_write_unsigned (regcache, float_argreg, regval); 5000 5001 if (mips_debug) 5002 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5003 argreg, phex (regval, reglen)); 5004 regcache_cooked_write_unsigned (regcache, argreg, regval); 5005 float_argreg++; 5006 argreg++; 5007 } 5008 } 5009 else 5010 { 5011 /* Copy the argument to general registers or the stack in 5012 register-sized pieces. Large arguments are split between 5013 registers and stack. */ 5014 /* For N32/N64, structs, unions, or other composite types are 5015 treated as a sequence of doublewords, and are passed in integer 5016 or floating point registers as though they were simple scalar 5017 parameters to the extent that they fit, with any excess on the 5018 stack packed according to the normal memory layout of the 5019 object. 5020 The caller does not reserve space for the register arguments; 5021 the callee is responsible for reserving it if required. */ 5022 /* Note: Floating-point values that didn't fit into an FP 5023 register are only written to memory. */ 5024 while (len > 0) 5025 { 5026 /* Remember if the argument was written to the stack. */ 5027 int stack_used_p = 0; 5028 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 5029 5030 if (mips_debug) 5031 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5032 partial_len); 5033 5034 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5035 gdb_assert (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)); 5036 5037 /* Write this portion of the argument to the stack. */ 5038 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch)) 5039 { 5040 /* Should shorter than int integer values be 5041 promoted to int before being stored? */ 5042 int longword_offset = 0; 5043 CORE_ADDR addr; 5044 stack_used_p = 1; 5045 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 5046 { 5047 if ((typecode == TYPE_CODE_INT 5048 || typecode == TYPE_CODE_PTR) 5049 && len <= 4) 5050 longword_offset = MIPS64_REGSIZE - len; 5051 } 5052 5053 if (mips_debug) 5054 { 5055 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 5056 paddress (gdbarch, stack_offset)); 5057 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 5058 paddress (gdbarch, longword_offset)); 5059 } 5060 5061 addr = sp + stack_offset + longword_offset; 5062 5063 if (mips_debug) 5064 { 5065 int i; 5066 fprintf_unfiltered (gdb_stdlog, " @%s ", 5067 paddress (gdbarch, addr)); 5068 for (i = 0; i < partial_len; i++) 5069 { 5070 fprintf_unfiltered (gdb_stdlog, "%02x", 5071 val[i] & 0xff); 5072 } 5073 } 5074 write_memory (addr, val, partial_len); 5075 } 5076 5077 /* Note!!! This is NOT an else clause. Odd sized 5078 structs may go thru BOTH paths. */ 5079 /* Write this portion of the argument to a general 5080 purpose register. */ 5081 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 5082 { 5083 LONGEST regval; 5084 5085 /* Sign extend pointers, 32-bit integers and signed 5086 16-bit and 8-bit integers; everything else is taken 5087 as is. */ 5088 5089 if ((partial_len == 4 5090 && (typecode == TYPE_CODE_PTR 5091 || typecode == TYPE_CODE_INT)) 5092 || (partial_len < 4 5093 && typecode == TYPE_CODE_INT 5094 && !TYPE_UNSIGNED (arg_type))) 5095 regval = extract_signed_integer (val, partial_len, 5096 byte_order); 5097 else 5098 regval = extract_unsigned_integer (val, partial_len, 5099 byte_order); 5100 5101 /* A non-floating-point argument being passed in a 5102 general register. If a struct or union, and if 5103 the remaining length is smaller than the register 5104 size, we have to adjust the register value on 5105 big endian targets. 5106 5107 It does not seem to be necessary to do the 5108 same for integral types. */ 5109 5110 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5111 && partial_len < MIPS64_REGSIZE 5112 && (typecode == TYPE_CODE_STRUCT 5113 || typecode == TYPE_CODE_UNION)) 5114 regval <<= ((MIPS64_REGSIZE - partial_len) 5115 * TARGET_CHAR_BIT); 5116 5117 if (mips_debug) 5118 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 5119 argreg, 5120 phex (regval, MIPS64_REGSIZE)); 5121 regcache_cooked_write_unsigned (regcache, argreg, regval); 5122 5123 if (mips_n32n64_fp_arg_chunk_p (gdbarch, arg_type, 5124 TYPE_LENGTH (arg_type) - len)) 5125 { 5126 if (mips_debug) 5127 fprintf_filtered (gdb_stdlog, " - fpreg=%d val=%s", 5128 float_argreg, 5129 phex (regval, MIPS64_REGSIZE)); 5130 regcache_cooked_write_unsigned (regcache, float_argreg, 5131 regval); 5132 } 5133 5134 float_argreg++; 5135 argreg++; 5136 } 5137 5138 len -= partial_len; 5139 val += partial_len; 5140 5141 /* Compute the offset into the stack at which we will 5142 copy the next parameter. 5143 5144 In N32 (N64?), the stack_offset only needs to be 5145 adjusted when it has been used. */ 5146 5147 if (stack_used_p) 5148 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 5149 } 5150 } 5151 if (mips_debug) 5152 fprintf_unfiltered (gdb_stdlog, "\n"); 5153 } 5154 5155 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5156 5157 /* Return adjusted stack pointer. */ 5158 return sp; 5159 } 5160 5161 static enum return_value_convention 5162 mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, 5163 struct type *type, struct regcache *regcache, 5164 gdb_byte *readbuf, const gdb_byte *writebuf) 5165 { 5166 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5167 5168 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004 5169 5170 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2 5171 if needed), as appropriate for the type. Composite results (struct, 5172 union, or array) are returned in $2/$f0 and $3/$f2 according to the 5173 following rules: 5174 5175 * A struct with only one or two floating point fields is returned in $f0 5176 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX 5177 case. 5178 5179 * Any other composite results of at most 128 bits are returned in 5180 $2 (first 64 bits) and $3 (remainder, if necessary). 5181 5182 * Larger composite results are handled by converting the function to a 5183 procedure with an implicit first parameter, which is a pointer to an area 5184 reserved by the caller to receive the result. [The o32-bit ABI requires 5185 that all composite results be handled by conversion to implicit first 5186 parameters. The MIPS/SGI Fortran implementation has always made a 5187 specific exception to return COMPLEX results in the floating point 5188 registers.] */ 5189 5190 if (TYPE_LENGTH (type) > 2 * MIPS64_REGSIZE) 5191 return RETURN_VALUE_STRUCT_CONVENTION; 5192 else if (type->code () == TYPE_CODE_FLT 5193 && TYPE_LENGTH (type) == 16 5194 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5195 { 5196 /* A 128-bit floating-point value fills both $f0 and $f2. The 5197 two registers are used in the same as memory order, so the 5198 eight bytes with the lower memory address are in $f0. */ 5199 if (mips_debug) 5200 fprintf_unfiltered (gdb_stderr, "Return float in $f0 and $f2\n"); 5201 mips_xfer_register (gdbarch, regcache, 5202 (gdbarch_num_regs (gdbarch) 5203 + mips_regnum (gdbarch)->fp0), 5204 8, gdbarch_byte_order (gdbarch), 5205 readbuf, writebuf, 0); 5206 mips_xfer_register (gdbarch, regcache, 5207 (gdbarch_num_regs (gdbarch) 5208 + mips_regnum (gdbarch)->fp0 + 2), 5209 8, gdbarch_byte_order (gdbarch), 5210 readbuf ? readbuf + 8 : readbuf, 5211 writebuf ? writebuf + 8 : writebuf, 0); 5212 return RETURN_VALUE_REGISTER_CONVENTION; 5213 } 5214 else if (type->code () == TYPE_CODE_FLT 5215 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5216 { 5217 /* A single or double floating-point value that fits in FP0. */ 5218 if (mips_debug) 5219 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 5220 mips_xfer_register (gdbarch, regcache, 5221 (gdbarch_num_regs (gdbarch) 5222 + mips_regnum (gdbarch)->fp0), 5223 TYPE_LENGTH (type), 5224 gdbarch_byte_order (gdbarch), 5225 readbuf, writebuf, 0); 5226 return RETURN_VALUE_REGISTER_CONVENTION; 5227 } 5228 else if (type->code () == TYPE_CODE_STRUCT 5229 && type->num_fields () <= 2 5230 && type->num_fields () >= 1 5231 && ((type->num_fields () == 1 5232 && (check_typedef (type->field (0).type ())->code () 5233 == TYPE_CODE_FLT)) 5234 || (type->num_fields () == 2 5235 && (check_typedef (type->field (0).type ())->code () 5236 == TYPE_CODE_FLT) 5237 && (check_typedef (type->field (1).type ())->code () 5238 == TYPE_CODE_FLT)))) 5239 { 5240 /* A struct that contains one or two floats. Each value is part 5241 in the least significant part of their floating point 5242 register (or GPR, for soft float). */ 5243 int regnum; 5244 int field; 5245 for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE 5246 ? mips_regnum (gdbarch)->fp0 5247 : MIPS_V0_REGNUM); 5248 field < type->num_fields (); field++, regnum += 2) 5249 { 5250 int offset = (FIELD_BITPOS (type->field (field)) 5251 / TARGET_CHAR_BIT); 5252 if (mips_debug) 5253 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 5254 offset); 5255 if (TYPE_LENGTH (type->field (field).type ()) == 16) 5256 { 5257 /* A 16-byte long double field goes in two consecutive 5258 registers. */ 5259 mips_xfer_register (gdbarch, regcache, 5260 gdbarch_num_regs (gdbarch) + regnum, 5261 8, 5262 gdbarch_byte_order (gdbarch), 5263 readbuf, writebuf, offset); 5264 mips_xfer_register (gdbarch, regcache, 5265 gdbarch_num_regs (gdbarch) + regnum + 1, 5266 8, 5267 gdbarch_byte_order (gdbarch), 5268 readbuf, writebuf, offset + 8); 5269 } 5270 else 5271 mips_xfer_register (gdbarch, regcache, 5272 gdbarch_num_regs (gdbarch) + regnum, 5273 TYPE_LENGTH (type->field (field).type ()), 5274 gdbarch_byte_order (gdbarch), 5275 readbuf, writebuf, offset); 5276 } 5277 return RETURN_VALUE_REGISTER_CONVENTION; 5278 } 5279 else if (type->code () == TYPE_CODE_STRUCT 5280 || type->code () == TYPE_CODE_UNION 5281 || type->code () == TYPE_CODE_ARRAY) 5282 { 5283 /* A composite type. Extract the left justified value, 5284 regardless of the byte order. I.e. DO NOT USE 5285 mips_xfer_lower. */ 5286 int offset; 5287 int regnum; 5288 for (offset = 0, regnum = MIPS_V0_REGNUM; 5289 offset < TYPE_LENGTH (type); 5290 offset += register_size (gdbarch, regnum), regnum++) 5291 { 5292 int xfer = register_size (gdbarch, regnum); 5293 if (offset + xfer > TYPE_LENGTH (type)) 5294 xfer = TYPE_LENGTH (type) - offset; 5295 if (mips_debug) 5296 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 5297 offset, xfer, regnum); 5298 mips_xfer_register (gdbarch, regcache, 5299 gdbarch_num_regs (gdbarch) + regnum, 5300 xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, 5301 offset); 5302 } 5303 return RETURN_VALUE_REGISTER_CONVENTION; 5304 } 5305 else 5306 { 5307 /* A scalar extract each part but least-significant-byte 5308 justified. */ 5309 int offset; 5310 int regnum; 5311 for (offset = 0, regnum = MIPS_V0_REGNUM; 5312 offset < TYPE_LENGTH (type); 5313 offset += register_size (gdbarch, regnum), regnum++) 5314 { 5315 int xfer = register_size (gdbarch, regnum); 5316 if (offset + xfer > TYPE_LENGTH (type)) 5317 xfer = TYPE_LENGTH (type) - offset; 5318 if (mips_debug) 5319 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5320 offset, xfer, regnum); 5321 mips_xfer_register (gdbarch, regcache, 5322 gdbarch_num_regs (gdbarch) + regnum, 5323 xfer, gdbarch_byte_order (gdbarch), 5324 readbuf, writebuf, offset); 5325 } 5326 return RETURN_VALUE_REGISTER_CONVENTION; 5327 } 5328 } 5329 5330 /* Which registers to use for passing floating-point values between 5331 function calls, one of floating-point, general and both kinds of 5332 registers. O32 and O64 use different register kinds for standard 5333 MIPS and MIPS16 code; to make the handling of cases where we may 5334 not know what kind of code is being used (e.g. no debug information) 5335 easier we sometimes use both kinds. */ 5336 5337 enum mips_fval_reg 5338 { 5339 mips_fval_fpr, 5340 mips_fval_gpr, 5341 mips_fval_both 5342 }; 5343 5344 /* O32 ABI stuff. */ 5345 5346 static CORE_ADDR 5347 mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5348 struct regcache *regcache, CORE_ADDR bp_addr, 5349 int nargs, struct value **args, CORE_ADDR sp, 5350 function_call_return_method return_method, 5351 CORE_ADDR struct_addr) 5352 { 5353 int argreg; 5354 int float_argreg; 5355 int argnum; 5356 int arg_space = 0; 5357 int stack_offset = 0; 5358 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5359 CORE_ADDR func_addr = find_function_addr (function, NULL); 5360 5361 /* For shared libraries, "t9" needs to point at the function 5362 address. */ 5363 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5364 5365 /* Set the return address register to point to the entry point of 5366 the program, where a breakpoint lies in wait. */ 5367 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5368 5369 /* First ensure that the stack and structure return address (if any) 5370 are properly aligned. The stack has to be at least 64-bit 5371 aligned even on 32-bit machines, because doubles must be 64-bit 5372 aligned. For n32 and n64, stack frames need to be 128-bit 5373 aligned, so we round to this widest known alignment. */ 5374 5375 sp = align_down (sp, 16); 5376 struct_addr = align_down (struct_addr, 16); 5377 5378 /* Now make space on the stack for the args. */ 5379 for (argnum = 0; argnum < nargs; argnum++) 5380 { 5381 struct type *arg_type = check_typedef (value_type (args[argnum])); 5382 5383 /* Align to double-word if necessary. */ 5384 if (mips_type_needs_double_align (arg_type)) 5385 arg_space = align_up (arg_space, MIPS32_REGSIZE * 2); 5386 /* Allocate space on the stack. */ 5387 arg_space += align_up (TYPE_LENGTH (arg_type), MIPS32_REGSIZE); 5388 } 5389 sp -= align_up (arg_space, 16); 5390 5391 if (mips_debug) 5392 fprintf_unfiltered (gdb_stdlog, 5393 "mips_o32_push_dummy_call: sp=%s allocated %ld\n", 5394 paddress (gdbarch, sp), 5395 (long) align_up (arg_space, 16)); 5396 5397 /* Initialize the integer and float register pointers. */ 5398 argreg = MIPS_A0_REGNUM; 5399 float_argreg = mips_fpa0_regnum (gdbarch); 5400 5401 /* The struct_return pointer occupies the first parameter-passing reg. */ 5402 if (return_method == return_method_struct) 5403 { 5404 if (mips_debug) 5405 fprintf_unfiltered (gdb_stdlog, 5406 "mips_o32_push_dummy_call: " 5407 "struct_return reg=%d %s\n", 5408 argreg, paddress (gdbarch, struct_addr)); 5409 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5410 stack_offset += MIPS32_REGSIZE; 5411 } 5412 5413 /* Now load as many as possible of the first arguments into 5414 registers, and push the rest onto the stack. Loop thru args 5415 from first to last. */ 5416 for (argnum = 0; argnum < nargs; argnum++) 5417 { 5418 const gdb_byte *val; 5419 struct value *arg = args[argnum]; 5420 struct type *arg_type = check_typedef (value_type (arg)); 5421 int len = TYPE_LENGTH (arg_type); 5422 enum type_code typecode = arg_type->code (); 5423 5424 if (mips_debug) 5425 fprintf_unfiltered (gdb_stdlog, 5426 "mips_o32_push_dummy_call: %d len=%d type=%d", 5427 argnum + 1, len, (int) typecode); 5428 5429 val = value_contents (arg); 5430 5431 /* 32-bit ABIs always start floating point arguments in an 5432 even-numbered floating point register. Round the FP register 5433 up before the check to see if there are any FP registers 5434 left. O32 targets also pass the FP in the integer registers 5435 so also round up normal registers. */ 5436 if (fp_register_arg_p (gdbarch, typecode, arg_type)) 5437 { 5438 if ((float_argreg & 1)) 5439 float_argreg++; 5440 } 5441 5442 /* Floating point arguments passed in registers have to be 5443 treated specially. On 32-bit architectures, doubles are 5444 passed in register pairs; the even FP register gets the 5445 low word, and the odd FP register gets the high word. 5446 On O32, the first two floating point arguments are also 5447 copied to general registers, following their memory order, 5448 because MIPS16 functions don't use float registers for 5449 arguments. This duplication of arguments in general 5450 registers can't hurt non-MIPS16 functions, because those 5451 registers are normally skipped. */ 5452 5453 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5454 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 5455 { 5456 if (register_size (gdbarch, float_argreg) < 8 && len == 8) 5457 { 5458 int freg_offset = gdbarch_byte_order (gdbarch) 5459 == BFD_ENDIAN_BIG ? 1 : 0; 5460 unsigned long regval; 5461 5462 /* First word. */ 5463 regval = extract_unsigned_integer (val, 4, byte_order); 5464 if (mips_debug) 5465 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5466 float_argreg + freg_offset, 5467 phex (regval, 4)); 5468 regcache_cooked_write_unsigned (regcache, 5469 float_argreg++ + freg_offset, 5470 regval); 5471 if (mips_debug) 5472 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5473 argreg, phex (regval, 4)); 5474 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5475 5476 /* Second word. */ 5477 regval = extract_unsigned_integer (val + 4, 4, byte_order); 5478 if (mips_debug) 5479 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5480 float_argreg - freg_offset, 5481 phex (regval, 4)); 5482 regcache_cooked_write_unsigned (regcache, 5483 float_argreg++ - freg_offset, 5484 regval); 5485 if (mips_debug) 5486 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5487 argreg, phex (regval, 4)); 5488 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5489 } 5490 else 5491 { 5492 /* This is a floating point value that fits entirely 5493 in a single register. */ 5494 /* On 32 bit ABI's the float_argreg is further adjusted 5495 above to ensure that it is even register aligned. */ 5496 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 5497 if (mips_debug) 5498 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5499 float_argreg, phex (regval, len)); 5500 regcache_cooked_write_unsigned (regcache, 5501 float_argreg++, regval); 5502 /* Although two FP registers are reserved for each 5503 argument, only one corresponding integer register is 5504 reserved. */ 5505 if (mips_debug) 5506 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5507 argreg, phex (regval, len)); 5508 regcache_cooked_write_unsigned (regcache, argreg++, regval); 5509 } 5510 /* Reserve space for the FP register. */ 5511 stack_offset += align_up (len, MIPS32_REGSIZE); 5512 } 5513 else 5514 { 5515 /* Copy the argument to general registers or the stack in 5516 register-sized pieces. Large arguments are split between 5517 registers and stack. */ 5518 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE 5519 are treated specially: Irix cc passes 5520 them in registers where gcc sometimes puts them on the 5521 stack. For maximum compatibility, we will put them in 5522 both places. */ 5523 int odd_sized_struct = (len > MIPS32_REGSIZE 5524 && len % MIPS32_REGSIZE != 0); 5525 /* Structures should be aligned to eight bytes (even arg registers) 5526 on MIPS_ABI_O32, if their first member has double precision. */ 5527 if (mips_type_needs_double_align (arg_type)) 5528 { 5529 if ((argreg & 1)) 5530 { 5531 argreg++; 5532 stack_offset += MIPS32_REGSIZE; 5533 } 5534 } 5535 while (len > 0) 5536 { 5537 int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); 5538 5539 if (mips_debug) 5540 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5541 partial_len); 5542 5543 /* Write this portion of the argument to the stack. */ 5544 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 5545 || odd_sized_struct) 5546 { 5547 /* Should shorter than int integer values be 5548 promoted to int before being stored? */ 5549 int longword_offset = 0; 5550 CORE_ADDR addr; 5551 5552 if (mips_debug) 5553 { 5554 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 5555 paddress (gdbarch, stack_offset)); 5556 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 5557 paddress (gdbarch, longword_offset)); 5558 } 5559 5560 addr = sp + stack_offset + longword_offset; 5561 5562 if (mips_debug) 5563 { 5564 int i; 5565 fprintf_unfiltered (gdb_stdlog, " @%s ", 5566 paddress (gdbarch, addr)); 5567 for (i = 0; i < partial_len; i++) 5568 { 5569 fprintf_unfiltered (gdb_stdlog, "%02x", 5570 val[i] & 0xff); 5571 } 5572 } 5573 write_memory (addr, val, partial_len); 5574 } 5575 5576 /* Note!!! This is NOT an else clause. Odd sized 5577 structs may go thru BOTH paths. */ 5578 /* Write this portion of the argument to a general 5579 purpose register. */ 5580 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 5581 { 5582 LONGEST regval = extract_signed_integer (val, partial_len, 5583 byte_order); 5584 /* Value may need to be sign extended, because 5585 mips_isa_regsize() != mips_abi_regsize(). */ 5586 5587 /* A non-floating-point argument being passed in a 5588 general register. If a struct or union, and if 5589 the remaining length is smaller than the register 5590 size, we have to adjust the register value on 5591 big endian targets. 5592 5593 It does not seem to be necessary to do the 5594 same for integral types. 5595 5596 Also don't do this adjustment on O64 binaries. 5597 5598 cagney/2001-07-23: gdb/179: Also, GCC, when 5599 outputting LE O32 with sizeof (struct) < 5600 mips_abi_regsize(), generates a left shift 5601 as part of storing the argument in a register 5602 (the left shift isn't generated when 5603 sizeof (struct) >= mips_abi_regsize()). Since 5604 it is quite possible that this is GCC 5605 contradicting the LE/O32 ABI, GDB has not been 5606 adjusted to accommodate this. Either someone 5607 needs to demonstrate that the LE/O32 ABI 5608 specifies such a left shift OR this new ABI gets 5609 identified as such and GDB gets tweaked 5610 accordingly. */ 5611 5612 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 5613 && partial_len < MIPS32_REGSIZE 5614 && (typecode == TYPE_CODE_STRUCT 5615 || typecode == TYPE_CODE_UNION)) 5616 regval <<= ((MIPS32_REGSIZE - partial_len) 5617 * TARGET_CHAR_BIT); 5618 5619 if (mips_debug) 5620 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 5621 argreg, 5622 phex (regval, MIPS32_REGSIZE)); 5623 regcache_cooked_write_unsigned (regcache, argreg, regval); 5624 argreg++; 5625 5626 /* Prevent subsequent floating point arguments from 5627 being passed in floating point registers. */ 5628 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; 5629 } 5630 5631 len -= partial_len; 5632 val += partial_len; 5633 5634 /* Compute the offset into the stack at which we will 5635 copy the next parameter. 5636 5637 In older ABIs, the caller reserved space for 5638 registers that contained arguments. This was loosely 5639 refered to as their "home". Consequently, space is 5640 always allocated. */ 5641 5642 stack_offset += align_up (partial_len, MIPS32_REGSIZE); 5643 } 5644 } 5645 if (mips_debug) 5646 fprintf_unfiltered (gdb_stdlog, "\n"); 5647 } 5648 5649 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 5650 5651 /* Return adjusted stack pointer. */ 5652 return sp; 5653 } 5654 5655 static enum return_value_convention 5656 mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, 5657 struct type *type, struct regcache *regcache, 5658 gdb_byte *readbuf, const gdb_byte *writebuf) 5659 { 5660 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 5661 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 5662 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 5663 enum mips_fval_reg fval_reg; 5664 5665 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 5666 if (type->code () == TYPE_CODE_STRUCT 5667 || type->code () == TYPE_CODE_UNION 5668 || type->code () == TYPE_CODE_ARRAY) 5669 return RETURN_VALUE_STRUCT_CONVENTION; 5670 else if (type->code () == TYPE_CODE_FLT 5671 && TYPE_LENGTH (type) == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5672 { 5673 /* A single-precision floating-point value. If reading in or copying, 5674 then we get it from/put it to FP0 for standard MIPS code or GPR2 5675 for MIPS16 code. If writing out only, then we put it to both FP0 5676 and GPR2. We do not support reading in with no function known, if 5677 this safety check ever triggers, then we'll have to try harder. */ 5678 gdb_assert (function || !readbuf); 5679 if (mips_debug) 5680 switch (fval_reg) 5681 { 5682 case mips_fval_fpr: 5683 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 5684 break; 5685 case mips_fval_gpr: 5686 fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); 5687 break; 5688 case mips_fval_both: 5689 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); 5690 break; 5691 } 5692 if (fval_reg != mips_fval_gpr) 5693 mips_xfer_register (gdbarch, regcache, 5694 (gdbarch_num_regs (gdbarch) 5695 + mips_regnum (gdbarch)->fp0), 5696 TYPE_LENGTH (type), 5697 gdbarch_byte_order (gdbarch), 5698 readbuf, writebuf, 0); 5699 if (fval_reg != mips_fval_fpr) 5700 mips_xfer_register (gdbarch, regcache, 5701 gdbarch_num_regs (gdbarch) + 2, 5702 TYPE_LENGTH (type), 5703 gdbarch_byte_order (gdbarch), 5704 readbuf, writebuf, 0); 5705 return RETURN_VALUE_REGISTER_CONVENTION; 5706 } 5707 else if (type->code () == TYPE_CODE_FLT 5708 && TYPE_LENGTH (type) == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5709 { 5710 /* A double-precision floating-point value. If reading in or copying, 5711 then we get it from/put it to FP1 and FP0 for standard MIPS code or 5712 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it 5713 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with 5714 no function known, if this safety check ever triggers, then we'll 5715 have to try harder. */ 5716 gdb_assert (function || !readbuf); 5717 if (mips_debug) 5718 switch (fval_reg) 5719 { 5720 case mips_fval_fpr: 5721 fprintf_unfiltered (gdb_stderr, "Return float in $fp1/$fp0\n"); 5722 break; 5723 case mips_fval_gpr: 5724 fprintf_unfiltered (gdb_stderr, "Return float in $2/$3\n"); 5725 break; 5726 case mips_fval_both: 5727 fprintf_unfiltered (gdb_stderr, 5728 "Return float in $fp1/$fp0 and $2/$3\n"); 5729 break; 5730 } 5731 if (fval_reg != mips_fval_gpr) 5732 { 5733 /* The most significant part goes in FP1, and the least significant 5734 in FP0. */ 5735 switch (gdbarch_byte_order (gdbarch)) 5736 { 5737 case BFD_ENDIAN_LITTLE: 5738 mips_xfer_register (gdbarch, regcache, 5739 (gdbarch_num_regs (gdbarch) 5740 + mips_regnum (gdbarch)->fp0 + 0), 5741 4, gdbarch_byte_order (gdbarch), 5742 readbuf, writebuf, 0); 5743 mips_xfer_register (gdbarch, regcache, 5744 (gdbarch_num_regs (gdbarch) 5745 + mips_regnum (gdbarch)->fp0 + 1), 5746 4, gdbarch_byte_order (gdbarch), 5747 readbuf, writebuf, 4); 5748 break; 5749 case BFD_ENDIAN_BIG: 5750 mips_xfer_register (gdbarch, regcache, 5751 (gdbarch_num_regs (gdbarch) 5752 + mips_regnum (gdbarch)->fp0 + 1), 5753 4, gdbarch_byte_order (gdbarch), 5754 readbuf, writebuf, 0); 5755 mips_xfer_register (gdbarch, regcache, 5756 (gdbarch_num_regs (gdbarch) 5757 + mips_regnum (gdbarch)->fp0 + 0), 5758 4, gdbarch_byte_order (gdbarch), 5759 readbuf, writebuf, 4); 5760 break; 5761 default: 5762 internal_error (__FILE__, __LINE__, _("bad switch")); 5763 } 5764 } 5765 if (fval_reg != mips_fval_fpr) 5766 { 5767 /* The two 32-bit parts are always placed in GPR2 and GPR3 5768 following these registers' memory order. */ 5769 mips_xfer_register (gdbarch, regcache, 5770 gdbarch_num_regs (gdbarch) + 2, 5771 4, gdbarch_byte_order (gdbarch), 5772 readbuf, writebuf, 0); 5773 mips_xfer_register (gdbarch, regcache, 5774 gdbarch_num_regs (gdbarch) + 3, 5775 4, gdbarch_byte_order (gdbarch), 5776 readbuf, writebuf, 4); 5777 } 5778 return RETURN_VALUE_REGISTER_CONVENTION; 5779 } 5780 #if 0 5781 else if (type->code () == TYPE_CODE_STRUCT 5782 && type->num_fields () <= 2 5783 && type->num_fields () >= 1 5784 && ((type->num_fields () == 1 5785 && (TYPE_CODE (type->field (0).type ()) 5786 == TYPE_CODE_FLT)) 5787 || (type->num_fields () == 2 5788 && (TYPE_CODE (type->field (0).type ()) 5789 == TYPE_CODE_FLT) 5790 && (TYPE_CODE (type->field (1).type ()) 5791 == TYPE_CODE_FLT))) 5792 && tdep->mips_fpu_type != MIPS_FPU_NONE) 5793 { 5794 /* A struct that contains one or two floats. Each value is part 5795 in the least significant part of their floating point 5796 register.. */ 5797 int regnum; 5798 int field; 5799 for (field = 0, regnum = mips_regnum (gdbarch)->fp0; 5800 field < type->num_fields (); field++, regnum += 2) 5801 { 5802 int offset = (FIELD_BITPOS (type->fields ()[field]) 5803 / TARGET_CHAR_BIT); 5804 if (mips_debug) 5805 fprintf_unfiltered (gdb_stderr, "Return float struct+%d\n", 5806 offset); 5807 mips_xfer_register (gdbarch, regcache, 5808 gdbarch_num_regs (gdbarch) + regnum, 5809 TYPE_LENGTH (type->field (field).type ()), 5810 gdbarch_byte_order (gdbarch), 5811 readbuf, writebuf, offset); 5812 } 5813 return RETURN_VALUE_REGISTER_CONVENTION; 5814 } 5815 #endif 5816 #if 0 5817 else if (type->code () == TYPE_CODE_STRUCT 5818 || type->code () == TYPE_CODE_UNION) 5819 { 5820 /* A structure or union. Extract the left justified value, 5821 regardless of the byte order. I.e. DO NOT USE 5822 mips_xfer_lower. */ 5823 int offset; 5824 int regnum; 5825 for (offset = 0, regnum = MIPS_V0_REGNUM; 5826 offset < TYPE_LENGTH (type); 5827 offset += register_size (gdbarch, regnum), regnum++) 5828 { 5829 int xfer = register_size (gdbarch, regnum); 5830 if (offset + xfer > TYPE_LENGTH (type)) 5831 xfer = TYPE_LENGTH (type) - offset; 5832 if (mips_debug) 5833 fprintf_unfiltered (gdb_stderr, "Return struct+%d:%d in $%d\n", 5834 offset, xfer, regnum); 5835 mips_xfer_register (gdbarch, regcache, 5836 gdbarch_num_regs (gdbarch) + regnum, xfer, 5837 BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); 5838 } 5839 return RETURN_VALUE_REGISTER_CONVENTION; 5840 } 5841 #endif 5842 else 5843 { 5844 /* A scalar extract each part but least-significant-byte 5845 justified. o32 thinks registers are 4 byte, regardless of 5846 the ISA. */ 5847 int offset; 5848 int regnum; 5849 for (offset = 0, regnum = MIPS_V0_REGNUM; 5850 offset < TYPE_LENGTH (type); 5851 offset += MIPS32_REGSIZE, regnum++) 5852 { 5853 int xfer = MIPS32_REGSIZE; 5854 if (offset + xfer > TYPE_LENGTH (type)) 5855 xfer = TYPE_LENGTH (type) - offset; 5856 if (mips_debug) 5857 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 5858 offset, xfer, regnum); 5859 mips_xfer_register (gdbarch, regcache, 5860 gdbarch_num_regs (gdbarch) + regnum, xfer, 5861 gdbarch_byte_order (gdbarch), 5862 readbuf, writebuf, offset); 5863 } 5864 return RETURN_VALUE_REGISTER_CONVENTION; 5865 } 5866 } 5867 5868 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32 5869 ABI. */ 5870 5871 static CORE_ADDR 5872 mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 5873 struct regcache *regcache, CORE_ADDR bp_addr, 5874 int nargs, 5875 struct value **args, CORE_ADDR sp, 5876 function_call_return_method return_method, CORE_ADDR struct_addr) 5877 { 5878 int argreg; 5879 int float_argreg; 5880 int argnum; 5881 int arg_space = 0; 5882 int stack_offset = 0; 5883 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 5884 CORE_ADDR func_addr = find_function_addr (function, NULL); 5885 5886 /* For shared libraries, "t9" needs to point at the function 5887 address. */ 5888 regcache_cooked_write_signed (regcache, MIPS_T9_REGNUM, func_addr); 5889 5890 /* Set the return address register to point to the entry point of 5891 the program, where a breakpoint lies in wait. */ 5892 regcache_cooked_write_signed (regcache, MIPS_RA_REGNUM, bp_addr); 5893 5894 /* First ensure that the stack and structure return address (if any) 5895 are properly aligned. The stack has to be at least 64-bit 5896 aligned even on 32-bit machines, because doubles must be 64-bit 5897 aligned. For n32 and n64, stack frames need to be 128-bit 5898 aligned, so we round to this widest known alignment. */ 5899 5900 sp = align_down (sp, 16); 5901 struct_addr = align_down (struct_addr, 16); 5902 5903 /* Now make space on the stack for the args. */ 5904 for (argnum = 0; argnum < nargs; argnum++) 5905 { 5906 struct type *arg_type = check_typedef (value_type (args[argnum])); 5907 5908 /* Allocate space on the stack. */ 5909 arg_space += align_up (TYPE_LENGTH (arg_type), MIPS64_REGSIZE); 5910 } 5911 sp -= align_up (arg_space, 16); 5912 5913 if (mips_debug) 5914 fprintf_unfiltered (gdb_stdlog, 5915 "mips_o64_push_dummy_call: sp=%s allocated %ld\n", 5916 paddress (gdbarch, sp), 5917 (long) align_up (arg_space, 16)); 5918 5919 /* Initialize the integer and float register pointers. */ 5920 argreg = MIPS_A0_REGNUM; 5921 float_argreg = mips_fpa0_regnum (gdbarch); 5922 5923 /* The struct_return pointer occupies the first parameter-passing reg. */ 5924 if (return_method == return_method_struct) 5925 { 5926 if (mips_debug) 5927 fprintf_unfiltered (gdb_stdlog, 5928 "mips_o64_push_dummy_call: " 5929 "struct_return reg=%d %s\n", 5930 argreg, paddress (gdbarch, struct_addr)); 5931 regcache_cooked_write_unsigned (regcache, argreg++, struct_addr); 5932 stack_offset += MIPS64_REGSIZE; 5933 } 5934 5935 /* Now load as many as possible of the first arguments into 5936 registers, and push the rest onto the stack. Loop thru args 5937 from first to last. */ 5938 for (argnum = 0; argnum < nargs; argnum++) 5939 { 5940 const gdb_byte *val; 5941 struct value *arg = args[argnum]; 5942 struct type *arg_type = check_typedef (value_type (arg)); 5943 int len = TYPE_LENGTH (arg_type); 5944 enum type_code typecode = arg_type->code (); 5945 5946 if (mips_debug) 5947 fprintf_unfiltered (gdb_stdlog, 5948 "mips_o64_push_dummy_call: %d len=%d type=%d", 5949 argnum + 1, len, (int) typecode); 5950 5951 val = value_contents (arg); 5952 5953 /* Floating point arguments passed in registers have to be 5954 treated specially. On 32-bit architectures, doubles are 5955 passed in register pairs; the even FP register gets the 5956 low word, and the odd FP register gets the high word. 5957 On O64, the first two floating point arguments are also 5958 copied to general registers, because MIPS16 functions 5959 don't use float registers for arguments. This duplication 5960 of arguments in general registers can't hurt non-MIPS16 5961 functions because those registers are normally skipped. */ 5962 5963 if (fp_register_arg_p (gdbarch, typecode, arg_type) 5964 && float_argreg <= MIPS_LAST_FP_ARG_REGNUM (gdbarch)) 5965 { 5966 LONGEST regval = extract_unsigned_integer (val, len, byte_order); 5967 if (mips_debug) 5968 fprintf_unfiltered (gdb_stdlog, " - fpreg=%d val=%s", 5969 float_argreg, phex (regval, len)); 5970 regcache_cooked_write_unsigned (regcache, float_argreg++, regval); 5971 if (mips_debug) 5972 fprintf_unfiltered (gdb_stdlog, " - reg=%d val=%s", 5973 argreg, phex (regval, len)); 5974 regcache_cooked_write_unsigned (regcache, argreg, regval); 5975 argreg++; 5976 /* Reserve space for the FP register. */ 5977 stack_offset += align_up (len, MIPS64_REGSIZE); 5978 } 5979 else 5980 { 5981 /* Copy the argument to general registers or the stack in 5982 register-sized pieces. Large arguments are split between 5983 registers and stack. */ 5984 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE 5985 are treated specially: Irix cc passes them in registers 5986 where gcc sometimes puts them on the stack. For maximum 5987 compatibility, we will put them in both places. */ 5988 int odd_sized_struct = (len > MIPS64_REGSIZE 5989 && len % MIPS64_REGSIZE != 0); 5990 while (len > 0) 5991 { 5992 int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); 5993 5994 if (mips_debug) 5995 fprintf_unfiltered (gdb_stdlog, " -- partial=%d", 5996 partial_len); 5997 5998 /* Write this portion of the argument to the stack. */ 5999 if (argreg > MIPS_LAST_ARG_REGNUM (gdbarch) 6000 || odd_sized_struct) 6001 { 6002 /* Should shorter than int integer values be 6003 promoted to int before being stored? */ 6004 int longword_offset = 0; 6005 CORE_ADDR addr; 6006 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6007 { 6008 if ((typecode == TYPE_CODE_INT 6009 || typecode == TYPE_CODE_PTR 6010 || typecode == TYPE_CODE_FLT) 6011 && len <= 4) 6012 longword_offset = MIPS64_REGSIZE - len; 6013 } 6014 6015 if (mips_debug) 6016 { 6017 fprintf_unfiltered (gdb_stdlog, " - stack_offset=%s", 6018 paddress (gdbarch, stack_offset)); 6019 fprintf_unfiltered (gdb_stdlog, " longword_offset=%s", 6020 paddress (gdbarch, longword_offset)); 6021 } 6022 6023 addr = sp + stack_offset + longword_offset; 6024 6025 if (mips_debug) 6026 { 6027 int i; 6028 fprintf_unfiltered (gdb_stdlog, " @%s ", 6029 paddress (gdbarch, addr)); 6030 for (i = 0; i < partial_len; i++) 6031 { 6032 fprintf_unfiltered (gdb_stdlog, "%02x", 6033 val[i] & 0xff); 6034 } 6035 } 6036 write_memory (addr, val, partial_len); 6037 } 6038 6039 /* Note!!! This is NOT an else clause. Odd sized 6040 structs may go thru BOTH paths. */ 6041 /* Write this portion of the argument to a general 6042 purpose register. */ 6043 if (argreg <= MIPS_LAST_ARG_REGNUM (gdbarch)) 6044 { 6045 LONGEST regval = extract_signed_integer (val, partial_len, 6046 byte_order); 6047 /* Value may need to be sign extended, because 6048 mips_isa_regsize() != mips_abi_regsize(). */ 6049 6050 /* A non-floating-point argument being passed in a 6051 general register. If a struct or union, and if 6052 the remaining length is smaller than the register 6053 size, we have to adjust the register value on 6054 big endian targets. 6055 6056 It does not seem to be necessary to do the 6057 same for integral types. */ 6058 6059 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG 6060 && partial_len < MIPS64_REGSIZE 6061 && (typecode == TYPE_CODE_STRUCT 6062 || typecode == TYPE_CODE_UNION)) 6063 regval <<= ((MIPS64_REGSIZE - partial_len) 6064 * TARGET_CHAR_BIT); 6065 6066 if (mips_debug) 6067 fprintf_filtered (gdb_stdlog, " - reg=%d val=%s", 6068 argreg, 6069 phex (regval, MIPS64_REGSIZE)); 6070 regcache_cooked_write_unsigned (regcache, argreg, regval); 6071 argreg++; 6072 6073 /* Prevent subsequent floating point arguments from 6074 being passed in floating point registers. */ 6075 float_argreg = MIPS_LAST_FP_ARG_REGNUM (gdbarch) + 1; 6076 } 6077 6078 len -= partial_len; 6079 val += partial_len; 6080 6081 /* Compute the offset into the stack at which we will 6082 copy the next parameter. 6083 6084 In older ABIs, the caller reserved space for 6085 registers that contained arguments. This was loosely 6086 refered to as their "home". Consequently, space is 6087 always allocated. */ 6088 6089 stack_offset += align_up (partial_len, MIPS64_REGSIZE); 6090 } 6091 } 6092 if (mips_debug) 6093 fprintf_unfiltered (gdb_stdlog, "\n"); 6094 } 6095 6096 regcache_cooked_write_signed (regcache, MIPS_SP_REGNUM, sp); 6097 6098 /* Return adjusted stack pointer. */ 6099 return sp; 6100 } 6101 6102 static enum return_value_convention 6103 mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, 6104 struct type *type, struct regcache *regcache, 6105 gdb_byte *readbuf, const gdb_byte *writebuf) 6106 { 6107 CORE_ADDR func_addr = function ? find_function_addr (function, NULL) : 0; 6108 int mips16 = mips_pc_is_mips16 (gdbarch, func_addr); 6109 enum mips_fval_reg fval_reg; 6110 6111 fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; 6112 if (type->code () == TYPE_CODE_STRUCT 6113 || type->code () == TYPE_CODE_UNION 6114 || type->code () == TYPE_CODE_ARRAY) 6115 return RETURN_VALUE_STRUCT_CONVENTION; 6116 else if (fp_register_arg_p (gdbarch, type->code (), type)) 6117 { 6118 /* A floating-point value. If reading in or copying, then we get it 6119 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code. 6120 If writing out only, then we put it to both FP0 and GPR2. We do 6121 not support reading in with no function known, if this safety 6122 check ever triggers, then we'll have to try harder. */ 6123 gdb_assert (function || !readbuf); 6124 if (mips_debug) 6125 switch (fval_reg) 6126 { 6127 case mips_fval_fpr: 6128 fprintf_unfiltered (gdb_stderr, "Return float in $fp0\n"); 6129 break; 6130 case mips_fval_gpr: 6131 fprintf_unfiltered (gdb_stderr, "Return float in $2\n"); 6132 break; 6133 case mips_fval_both: 6134 fprintf_unfiltered (gdb_stderr, "Return float in $fp0 and $2\n"); 6135 break; 6136 } 6137 if (fval_reg != mips_fval_gpr) 6138 mips_xfer_register (gdbarch, regcache, 6139 (gdbarch_num_regs (gdbarch) 6140 + mips_regnum (gdbarch)->fp0), 6141 TYPE_LENGTH (type), 6142 gdbarch_byte_order (gdbarch), 6143 readbuf, writebuf, 0); 6144 if (fval_reg != mips_fval_fpr) 6145 mips_xfer_register (gdbarch, regcache, 6146 gdbarch_num_regs (gdbarch) + 2, 6147 TYPE_LENGTH (type), 6148 gdbarch_byte_order (gdbarch), 6149 readbuf, writebuf, 0); 6150 return RETURN_VALUE_REGISTER_CONVENTION; 6151 } 6152 else 6153 { 6154 /* A scalar extract each part but least-significant-byte 6155 justified. */ 6156 int offset; 6157 int regnum; 6158 for (offset = 0, regnum = MIPS_V0_REGNUM; 6159 offset < TYPE_LENGTH (type); 6160 offset += MIPS64_REGSIZE, regnum++) 6161 { 6162 int xfer = MIPS64_REGSIZE; 6163 if (offset + xfer > TYPE_LENGTH (type)) 6164 xfer = TYPE_LENGTH (type) - offset; 6165 if (mips_debug) 6166 fprintf_unfiltered (gdb_stderr, "Return scalar+%d:%d in $%d\n", 6167 offset, xfer, regnum); 6168 mips_xfer_register (gdbarch, regcache, 6169 gdbarch_num_regs (gdbarch) + regnum, 6170 xfer, gdbarch_byte_order (gdbarch), 6171 readbuf, writebuf, offset); 6172 } 6173 return RETURN_VALUE_REGISTER_CONVENTION; 6174 } 6175 } 6176 6177 /* Floating point register management. 6178 6179 Background: MIPS1 & 2 fp registers are 32 bits wide. To support 6180 64bit operations, these early MIPS cpus treat fp register pairs 6181 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp 6182 registers and offer a compatibility mode that emulates the MIPS2 fp 6183 model. When operating in MIPS2 fp compat mode, later cpu's split 6184 double precision floats into two 32-bit chunks and store them in 6185 consecutive fp regs. To display 64-bit floats stored in this 6186 fashion, we have to combine 32 bits from f0 and 32 bits from f1. 6187 Throw in user-configurable endianness and you have a real mess. 6188 6189 The way this works is: 6190 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit 6191 double-precision value will be split across two logical registers. 6192 The lower-numbered logical register will hold the low-order bits, 6193 regardless of the processor's endianness. 6194 - If we are on a 64-bit processor, and we are looking for a 6195 single-precision value, it will be in the low ordered bits 6196 of a 64-bit GPR (after mfc1, for example) or a 64-bit register 6197 save slot in memory. 6198 - If we are in 64-bit mode, everything is straightforward. 6199 6200 Note that this code only deals with "live" registers at the top of the 6201 stack. We will attempt to deal with saved registers later, when 6202 the raw/cooked register interface is in place. (We need a general 6203 interface that can deal with dynamic saved register sizes -- fp 6204 regs could be 32 bits wide in one frame and 64 on the frame above 6205 and below). */ 6206 6207 /* Copy a 32-bit single-precision value from the current frame 6208 into rare_buffer. */ 6209 6210 static void 6211 mips_read_fp_register_single (struct frame_info *frame, int regno, 6212 gdb_byte *rare_buffer) 6213 { 6214 struct gdbarch *gdbarch = get_frame_arch (frame); 6215 int raw_size = register_size (gdbarch, regno); 6216 gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); 6217 6218 if (!deprecated_frame_register_read (frame, regno, raw_buffer)) 6219 error (_("can't read register %d (%s)"), 6220 regno, gdbarch_register_name (gdbarch, regno)); 6221 if (raw_size == 8) 6222 { 6223 /* We have a 64-bit value for this register. Find the low-order 6224 32 bits. */ 6225 int offset; 6226 6227 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6228 offset = 4; 6229 else 6230 offset = 0; 6231 6232 memcpy (rare_buffer, raw_buffer + offset, 4); 6233 } 6234 else 6235 { 6236 memcpy (rare_buffer, raw_buffer, 4); 6237 } 6238 } 6239 6240 /* Copy a 64-bit double-precision value from the current frame into 6241 rare_buffer. This may include getting half of it from the next 6242 register. */ 6243 6244 static void 6245 mips_read_fp_register_double (struct frame_info *frame, int regno, 6246 gdb_byte *rare_buffer) 6247 { 6248 struct gdbarch *gdbarch = get_frame_arch (frame); 6249 int raw_size = register_size (gdbarch, regno); 6250 6251 if (raw_size == 8 && !mips2_fp_compat (frame)) 6252 { 6253 /* We have a 64-bit value for this register, and we should use 6254 all 64 bits. */ 6255 if (!deprecated_frame_register_read (frame, regno, rare_buffer)) 6256 error (_("can't read register %d (%s)"), 6257 regno, gdbarch_register_name (gdbarch, regno)); 6258 } 6259 else 6260 { 6261 int rawnum = regno % gdbarch_num_regs (gdbarch); 6262 6263 if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) 6264 internal_error (__FILE__, __LINE__, 6265 _("mips_read_fp_register_double: bad access to " 6266 "odd-numbered FP register")); 6267 6268 /* mips_read_fp_register_single will find the correct 32 bits from 6269 each register. */ 6270 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6271 { 6272 mips_read_fp_register_single (frame, regno, rare_buffer + 4); 6273 mips_read_fp_register_single (frame, regno + 1, rare_buffer); 6274 } 6275 else 6276 { 6277 mips_read_fp_register_single (frame, regno, rare_buffer); 6278 mips_read_fp_register_single (frame, regno + 1, rare_buffer + 4); 6279 } 6280 } 6281 } 6282 6283 static void 6284 mips_print_fp_register (struct ui_file *file, struct frame_info *frame, 6285 int regnum) 6286 { /* Do values for FP (float) regs. */ 6287 struct gdbarch *gdbarch = get_frame_arch (frame); 6288 gdb_byte *raw_buffer; 6289 std::string flt_str, dbl_str; 6290 6291 const struct type *flt_type = builtin_type (gdbarch)->builtin_float; 6292 const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; 6293 6294 raw_buffer 6295 = ((gdb_byte *) 6296 alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); 6297 6298 fprintf_filtered (file, "%s:", gdbarch_register_name (gdbarch, regnum)); 6299 fprintf_filtered (file, "%*s", 6300 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), 6301 ""); 6302 6303 if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) 6304 { 6305 struct value_print_options opts; 6306 6307 /* 4-byte registers: Print hex and floating. Also print even 6308 numbered registers as doubles. */ 6309 mips_read_fp_register_single (frame, regnum, raw_buffer); 6310 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); 6311 6312 get_formatted_print_options (&opts, 'x'); 6313 print_scalar_formatted (raw_buffer, 6314 builtin_type (gdbarch)->builtin_uint32, 6315 &opts, 'w', file); 6316 6317 fprintf_filtered (file, " flt: %s", flt_str.c_str ()); 6318 6319 if ((regnum - gdbarch_num_regs (gdbarch)) % 2 == 0) 6320 { 6321 mips_read_fp_register_double (frame, regnum, raw_buffer); 6322 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); 6323 6324 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); 6325 } 6326 } 6327 else 6328 { 6329 struct value_print_options opts; 6330 6331 /* Eight byte registers: print each one as hex, float and double. */ 6332 mips_read_fp_register_single (frame, regnum, raw_buffer); 6333 flt_str = target_float_to_string (raw_buffer, flt_type, "%-17.9g"); 6334 6335 mips_read_fp_register_double (frame, regnum, raw_buffer); 6336 dbl_str = target_float_to_string (raw_buffer, dbl_type, "%-24.17g"); 6337 6338 get_formatted_print_options (&opts, 'x'); 6339 print_scalar_formatted (raw_buffer, 6340 builtin_type (gdbarch)->builtin_uint64, 6341 &opts, 'g', file); 6342 6343 fprintf_filtered (file, " flt: %s", flt_str.c_str ()); 6344 fprintf_filtered (file, " dbl: %s", dbl_str.c_str ()); 6345 } 6346 } 6347 6348 static void 6349 mips_print_register (struct ui_file *file, struct frame_info *frame, 6350 int regnum) 6351 { 6352 struct gdbarch *gdbarch = get_frame_arch (frame); 6353 struct value_print_options opts; 6354 struct value *val; 6355 6356 if (mips_float_register_p (gdbarch, regnum)) 6357 { 6358 mips_print_fp_register (file, frame, regnum); 6359 return; 6360 } 6361 6362 val = get_frame_register_value (frame, regnum); 6363 6364 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file); 6365 6366 /* The problem with printing numeric register names (r26, etc.) is that 6367 the user can't use them on input. Probably the best solution is to 6368 fix it so that either the numeric or the funky (a2, etc.) names 6369 are accepted on input. */ 6370 if (regnum < MIPS_NUMREGS) 6371 fprintf_filtered (file, "(r%d): ", regnum); 6372 else 6373 fprintf_filtered (file, ": "); 6374 6375 get_formatted_print_options (&opts, 'x'); 6376 value_print_scalar_formatted (val, &opts, 0, file); 6377 } 6378 6379 /* Print IEEE exception condition bits in FLAGS. */ 6380 6381 static void 6382 print_fpu_flags (struct ui_file *file, int flags) 6383 { 6384 if (flags & (1 << 0)) 6385 fputs_filtered (" inexact", file); 6386 if (flags & (1 << 1)) 6387 fputs_filtered (" uflow", file); 6388 if (flags & (1 << 2)) 6389 fputs_filtered (" oflow", file); 6390 if (flags & (1 << 3)) 6391 fputs_filtered (" div0", file); 6392 if (flags & (1 << 4)) 6393 fputs_filtered (" inval", file); 6394 if (flags & (1 << 5)) 6395 fputs_filtered (" unimp", file); 6396 fputc_filtered ('\n', file); 6397 } 6398 6399 /* Print interesting information about the floating point processor 6400 (if present) or emulator. */ 6401 6402 static void 6403 mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, 6404 struct frame_info *frame, const char *args) 6405 { 6406 int fcsr = mips_regnum (gdbarch)->fp_control_status; 6407 enum mips_fpu_type type = MIPS_FPU_TYPE (gdbarch); 6408 ULONGEST fcs = 0; 6409 int i; 6410 6411 if (fcsr == -1 || !read_frame_register_unsigned (frame, fcsr, &fcs)) 6412 type = MIPS_FPU_NONE; 6413 6414 fprintf_filtered (file, "fpu type: %s\n", 6415 type == MIPS_FPU_DOUBLE ? "double-precision" 6416 : type == MIPS_FPU_SINGLE ? "single-precision" 6417 : "none / unused"); 6418 6419 if (type == MIPS_FPU_NONE) 6420 return; 6421 6422 fprintf_filtered (file, "reg size: %d bits\n", 6423 register_size (gdbarch, mips_regnum (gdbarch)->fp0) * 8); 6424 6425 fputs_filtered ("cond :", file); 6426 if (fcs & (1 << 23)) 6427 fputs_filtered (" 0", file); 6428 for (i = 1; i <= 7; i++) 6429 if (fcs & (1 << (24 + i))) 6430 fprintf_filtered (file, " %d", i); 6431 fputc_filtered ('\n', file); 6432 6433 fputs_filtered ("cause :", file); 6434 print_fpu_flags (file, (fcs >> 12) & 0x3f); 6435 fputs ("mask :", stdout); 6436 print_fpu_flags (file, (fcs >> 7) & 0x1f); 6437 fputs ("flags :", stdout); 6438 print_fpu_flags (file, (fcs >> 2) & 0x1f); 6439 6440 fputs_filtered ("rounding: ", file); 6441 switch (fcs & 3) 6442 { 6443 case 0: fputs_filtered ("nearest\n", file); break; 6444 case 1: fputs_filtered ("zero\n", file); break; 6445 case 2: fputs_filtered ("+inf\n", file); break; 6446 case 3: fputs_filtered ("-inf\n", file); break; 6447 } 6448 6449 fputs_filtered ("flush :", file); 6450 if (fcs & (1 << 21)) 6451 fputs_filtered (" nearest", file); 6452 if (fcs & (1 << 22)) 6453 fputs_filtered (" override", file); 6454 if (fcs & (1 << 24)) 6455 fputs_filtered (" zero", file); 6456 if ((fcs & (0xb << 21)) == 0) 6457 fputs_filtered (" no", file); 6458 fputc_filtered ('\n', file); 6459 6460 fprintf_filtered (file, "nan2008 : %s\n", fcs & (1 << 18) ? "yes" : "no"); 6461 fprintf_filtered (file, "abs2008 : %s\n", fcs & (1 << 19) ? "yes" : "no"); 6462 fputc_filtered ('\n', file); 6463 6464 default_print_float_info (gdbarch, file, frame, args); 6465 } 6466 6467 /* Replacement for generic do_registers_info. 6468 Print regs in pretty columns. */ 6469 6470 static int 6471 print_fp_register_row (struct ui_file *file, struct frame_info *frame, 6472 int regnum) 6473 { 6474 fprintf_filtered (file, " "); 6475 mips_print_fp_register (file, frame, regnum); 6476 fprintf_filtered (file, "\n"); 6477 return regnum + 1; 6478 } 6479 6480 6481 /* Print a row's worth of GP (int) registers, with name labels above. */ 6482 6483 static int 6484 print_gp_register_row (struct ui_file *file, struct frame_info *frame, 6485 int start_regnum) 6486 { 6487 struct gdbarch *gdbarch = get_frame_arch (frame); 6488 /* Do values for GP (int) regs. */ 6489 const gdb_byte *raw_buffer; 6490 struct value *value; 6491 int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols 6492 per row. */ 6493 int col, byte; 6494 int regnum; 6495 6496 /* For GP registers, we print a separate row of names above the vals. */ 6497 for (col = 0, regnum = start_regnum; 6498 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); 6499 regnum++) 6500 { 6501 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6502 continue; /* unused register */ 6503 if (mips_float_register_p (gdbarch, regnum)) 6504 break; /* End the row: reached FP register. */ 6505 /* Large registers are handled separately. */ 6506 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6507 { 6508 if (col > 0) 6509 break; /* End the row before this register. */ 6510 6511 /* Print this register on a row by itself. */ 6512 mips_print_register (file, frame, regnum); 6513 fprintf_filtered (file, "\n"); 6514 return regnum + 1; 6515 } 6516 if (col == 0) 6517 fprintf_filtered (file, " "); 6518 fprintf_filtered (file, 6519 mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", 6520 gdbarch_register_name (gdbarch, regnum)); 6521 col++; 6522 } 6523 6524 if (col == 0) 6525 return regnum; 6526 6527 /* Print the R0 to R31 names. */ 6528 if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) 6529 fprintf_filtered (file, "\n R%-4d", 6530 start_regnum % gdbarch_num_regs (gdbarch)); 6531 else 6532 fprintf_filtered (file, "\n "); 6533 6534 /* Now print the values in hex, 4 or 8 to the row. */ 6535 for (col = 0, regnum = start_regnum; 6536 col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); 6537 regnum++) 6538 { 6539 if (*gdbarch_register_name (gdbarch, regnum) == '\0') 6540 continue; /* unused register */ 6541 if (mips_float_register_p (gdbarch, regnum)) 6542 break; /* End row: reached FP register. */ 6543 if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) 6544 break; /* End row: large register. */ 6545 6546 /* OK: get the data in raw format. */ 6547 value = get_frame_register_value (frame, regnum); 6548 if (value_optimized_out (value) 6549 || !value_entirely_available (value)) 6550 { 6551 fprintf_filtered (file, "%*s ", 6552 (int) mips_abi_regsize (gdbarch) * 2, 6553 (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" 6554 : "<unavailable>")); 6555 col++; 6556 continue; 6557 } 6558 raw_buffer = value_contents_all (value); 6559 /* pad small registers */ 6560 for (byte = 0; 6561 byte < (mips_abi_regsize (gdbarch) 6562 - register_size (gdbarch, regnum)); byte++) 6563 fprintf_filtered (file, " "); 6564 /* Now print the register value in hex, endian order. */ 6565 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 6566 for (byte = 6567 register_size (gdbarch, regnum) - register_size (gdbarch, regnum); 6568 byte < register_size (gdbarch, regnum); byte++) 6569 fprintf_filtered (file, "%02x", raw_buffer[byte]); 6570 else 6571 for (byte = register_size (gdbarch, regnum) - 1; 6572 byte >= 0; byte--) 6573 fprintf_filtered (file, "%02x", raw_buffer[byte]); 6574 fprintf_filtered (file, " "); 6575 col++; 6576 } 6577 if (col > 0) /* ie. if we actually printed anything... */ 6578 fprintf_filtered (file, "\n"); 6579 6580 return regnum; 6581 } 6582 6583 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */ 6584 6585 static void 6586 mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, 6587 struct frame_info *frame, int regnum, int all) 6588 { 6589 if (regnum != -1) /* Do one specified register. */ 6590 { 6591 gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); 6592 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') 6593 error (_("Not a valid register for the current processor type")); 6594 6595 mips_print_register (file, frame, regnum); 6596 fprintf_filtered (file, "\n"); 6597 } 6598 else 6599 /* Do all (or most) registers. */ 6600 { 6601 regnum = gdbarch_num_regs (gdbarch); 6602 while (regnum < gdbarch_num_cooked_regs (gdbarch)) 6603 { 6604 if (mips_float_register_p (gdbarch, regnum)) 6605 { 6606 if (all) /* True for "INFO ALL-REGISTERS" command. */ 6607 regnum = print_fp_register_row (file, frame, regnum); 6608 else 6609 regnum += MIPS_NUMREGS; /* Skip floating point regs. */ 6610 } 6611 else 6612 regnum = print_gp_register_row (file, frame, regnum); 6613 } 6614 } 6615 } 6616 6617 static int 6618 mips_single_step_through_delay (struct gdbarch *gdbarch, 6619 struct frame_info *frame) 6620 { 6621 CORE_ADDR pc = get_frame_pc (frame); 6622 enum mips_isa isa; 6623 ULONGEST insn; 6624 int size; 6625 6626 if ((mips_pc_is_mips (pc) 6627 && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) 6628 || (mips_pc_is_micromips (gdbarch, pc) 6629 && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) 6630 || (mips_pc_is_mips16 (gdbarch, pc) 6631 && !mips16_insn_at_pc_has_delay_slot (gdbarch, pc, 0))) 6632 return 0; 6633 6634 isa = mips_pc_isa (gdbarch, pc); 6635 /* _has_delay_slot above will have validated the read. */ 6636 insn = mips_fetch_instruction (gdbarch, isa, pc, NULL); 6637 size = mips_insn_size (isa, insn); 6638 6639 const address_space *aspace = get_frame_address_space (frame); 6640 6641 return breakpoint_here_p (aspace, pc + size) != no_breakpoint_here; 6642 } 6643 6644 /* To skip prologues, I use this predicate. Returns either PC itself 6645 if the code at PC does not look like a function prologue; otherwise 6646 returns an address that (if we're lucky) follows the prologue. If 6647 LENIENT, then we must skip everything which is involved in setting 6648 up the frame (it's OK to skip more, just so long as we don't skip 6649 anything which might clobber the registers which are being saved. 6650 We must skip more in the case where part of the prologue is in the 6651 delay slot of a non-prologue instruction). */ 6652 6653 static CORE_ADDR 6654 mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 6655 { 6656 CORE_ADDR limit_pc; 6657 CORE_ADDR func_addr; 6658 6659 /* See if we can determine the end of the prologue via the symbol table. 6660 If so, then return either PC, or the PC after the prologue, whichever 6661 is greater. */ 6662 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 6663 { 6664 CORE_ADDR post_prologue_pc 6665 = skip_prologue_using_sal (gdbarch, func_addr); 6666 if (post_prologue_pc != 0) 6667 return std::max (pc, post_prologue_pc); 6668 } 6669 6670 /* Can't determine prologue from the symbol table, need to examine 6671 instructions. */ 6672 6673 /* Find an upper limit on the function prologue using the debug 6674 information. If the debug information could not be used to provide 6675 that bound, then use an arbitrary large number as the upper bound. */ 6676 limit_pc = skip_prologue_using_sal (gdbarch, pc); 6677 if (limit_pc == 0) 6678 limit_pc = pc + 100; /* Magic. */ 6679 6680 if (mips_pc_is_mips16 (gdbarch, pc)) 6681 return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6682 else if (mips_pc_is_micromips (gdbarch, pc)) 6683 return micromips_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6684 else 6685 return mips32_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); 6686 } 6687 6688 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version). 6689 This is a helper function for mips_stack_frame_destroyed_p. */ 6690 6691 static int 6692 mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6693 { 6694 CORE_ADDR func_addr = 0, func_end = 0; 6695 6696 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6697 { 6698 /* The MIPS epilogue is max. 12 bytes long. */ 6699 CORE_ADDR addr = func_end - 12; 6700 6701 if (addr < func_addr + 4) 6702 addr = func_addr + 4; 6703 if (pc < addr) 6704 return 0; 6705 6706 for (; pc < func_end; pc += MIPS_INSN32_SIZE) 6707 { 6708 unsigned long high_word; 6709 unsigned long inst; 6710 6711 inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 6712 high_word = (inst >> 16) & 0xffff; 6713 6714 if (high_word != 0x27bd /* addiu $sp,$sp,offset */ 6715 && high_word != 0x67bd /* daddiu $sp,$sp,offset */ 6716 && inst != 0x03e00008 /* jr $ra */ 6717 && inst != 0x00000000) /* nop */ 6718 return 0; 6719 } 6720 6721 return 1; 6722 } 6723 6724 return 0; 6725 } 6726 6727 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version). 6728 This is a helper function for mips_stack_frame_destroyed_p. */ 6729 6730 static int 6731 micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6732 { 6733 CORE_ADDR func_addr = 0; 6734 CORE_ADDR func_end = 0; 6735 CORE_ADDR addr; 6736 ULONGEST insn; 6737 long offset; 6738 int dreg; 6739 int sreg; 6740 int loc; 6741 6742 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6743 return 0; 6744 6745 /* The microMIPS epilogue is max. 12 bytes long. */ 6746 addr = func_end - 12; 6747 6748 if (addr < func_addr + 2) 6749 addr = func_addr + 2; 6750 if (pc < addr) 6751 return 0; 6752 6753 for (; pc < func_end; pc += loc) 6754 { 6755 loc = 0; 6756 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); 6757 loc += MIPS_INSN16_SIZE; 6758 switch (mips_insn_size (ISA_MICROMIPS, insn)) 6759 { 6760 /* 32-bit instructions. */ 6761 case 2 * MIPS_INSN16_SIZE: 6762 insn <<= 16; 6763 insn |= mips_fetch_instruction (gdbarch, 6764 ISA_MICROMIPS, pc + loc, NULL); 6765 loc += MIPS_INSN16_SIZE; 6766 switch (micromips_op (insn >> 16)) 6767 { 6768 case 0xc: /* ADDIU: bits 001100 */ 6769 case 0x17: /* DADDIU: bits 010111 */ 6770 sreg = b0s5_reg (insn >> 16); 6771 dreg = b5s5_reg (insn >> 16); 6772 offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; 6773 if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM 6774 /* (D)ADDIU $sp, imm */ 6775 && offset >= 0) 6776 break; 6777 return 0; 6778 6779 default: 6780 return 0; 6781 } 6782 break; 6783 6784 /* 16-bit instructions. */ 6785 case MIPS_INSN16_SIZE: 6786 switch (micromips_op (insn)) 6787 { 6788 case 0x3: /* MOVE: bits 000011 */ 6789 sreg = b0s5_reg (insn); 6790 dreg = b5s5_reg (insn); 6791 if (sreg == 0 && dreg == 0) 6792 /* MOVE $zero, $zero aka NOP */ 6793 break; 6794 return 0; 6795 6796 case 0x11: /* POOL16C: bits 010001 */ 6797 if (b5s5_op (insn) == 0x18 6798 /* JRADDIUSP: bits 010011 11000 */ 6799 || (b5s5_op (insn) == 0xd 6800 /* JRC: bits 010011 01101 */ 6801 && b0s5_reg (insn) == MIPS_RA_REGNUM)) 6802 /* JRC $ra */ 6803 break; 6804 return 0; 6805 6806 case 0x13: /* POOL16D: bits 010011 */ 6807 offset = micromips_decode_imm9 (b1s9_imm (insn)); 6808 if ((insn & 0x1) == 0x1 6809 /* ADDIUSP: bits 010011 1 */ 6810 && offset > 0) 6811 break; 6812 return 0; 6813 6814 default: 6815 return 0; 6816 } 6817 } 6818 } 6819 6820 return 1; 6821 } 6822 6823 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version). 6824 This is a helper function for mips_stack_frame_destroyed_p. */ 6825 6826 static int 6827 mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6828 { 6829 CORE_ADDR func_addr = 0, func_end = 0; 6830 6831 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 6832 { 6833 /* The MIPS epilogue is max. 12 bytes long. */ 6834 CORE_ADDR addr = func_end - 12; 6835 6836 if (addr < func_addr + 4) 6837 addr = func_addr + 4; 6838 if (pc < addr) 6839 return 0; 6840 6841 for (; pc < func_end; pc += MIPS_INSN16_SIZE) 6842 { 6843 unsigned short inst; 6844 6845 inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); 6846 6847 if ((inst & 0xf800) == 0xf000) /* extend */ 6848 continue; 6849 6850 if (inst != 0x6300 /* addiu $sp,offset */ 6851 && inst != 0xfb00 /* daddiu $sp,$sp,offset */ 6852 && inst != 0xe820 /* jr $ra */ 6853 && inst != 0xe8a0 /* jrc $ra */ 6854 && inst != 0x6500) /* nop */ 6855 return 0; 6856 } 6857 6858 return 1; 6859 } 6860 6861 return 0; 6862 } 6863 6864 /* Implement the stack_frame_destroyed_p gdbarch method. 6865 6866 The epilogue is defined here as the area at the end of a function, 6867 after an instruction which destroys the function's stack frame. */ 6868 6869 static int 6870 mips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) 6871 { 6872 if (mips_pc_is_mips16 (gdbarch, pc)) 6873 return mips16_stack_frame_destroyed_p (gdbarch, pc); 6874 else if (mips_pc_is_micromips (gdbarch, pc)) 6875 return micromips_stack_frame_destroyed_p (gdbarch, pc); 6876 else 6877 return mips32_stack_frame_destroyed_p (gdbarch, pc); 6878 } 6879 6880 /* Commands to show/set the MIPS FPU type. */ 6881 6882 static void 6883 show_mipsfpu_command (const char *args, int from_tty) 6884 { 6885 const char *fpu; 6886 6887 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 6888 { 6889 printf_unfiltered 6890 ("The MIPS floating-point coprocessor is unknown " 6891 "because the current architecture is not MIPS.\n"); 6892 return; 6893 } 6894 6895 switch (MIPS_FPU_TYPE (target_gdbarch ())) 6896 { 6897 case MIPS_FPU_SINGLE: 6898 fpu = "single-precision"; 6899 break; 6900 case MIPS_FPU_DOUBLE: 6901 fpu = "double-precision"; 6902 break; 6903 case MIPS_FPU_NONE: 6904 fpu = "absent (none)"; 6905 break; 6906 default: 6907 internal_error (__FILE__, __LINE__, _("bad switch")); 6908 } 6909 if (mips_fpu_type_auto) 6910 printf_unfiltered ("The MIPS floating-point coprocessor " 6911 "is set automatically (currently %s)\n", 6912 fpu); 6913 else 6914 printf_unfiltered 6915 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); 6916 } 6917 6918 6919 static void 6920 set_mipsfpu_single_command (const char *args, int from_tty) 6921 { 6922 struct gdbarch_info info; 6923 gdbarch_info_init (&info); 6924 mips_fpu_type = MIPS_FPU_SINGLE; 6925 mips_fpu_type_auto = 0; 6926 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6927 instead of relying on globals. Doing that would let generic code 6928 handle the search for this specific architecture. */ 6929 if (!gdbarch_update_p (info)) 6930 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6931 } 6932 6933 static void 6934 set_mipsfpu_double_command (const char *args, int from_tty) 6935 { 6936 struct gdbarch_info info; 6937 gdbarch_info_init (&info); 6938 mips_fpu_type = MIPS_FPU_DOUBLE; 6939 mips_fpu_type_auto = 0; 6940 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6941 instead of relying on globals. Doing that would let generic code 6942 handle the search for this specific architecture. */ 6943 if (!gdbarch_update_p (info)) 6944 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6945 } 6946 6947 static void 6948 set_mipsfpu_none_command (const char *args, int from_tty) 6949 { 6950 struct gdbarch_info info; 6951 gdbarch_info_init (&info); 6952 mips_fpu_type = MIPS_FPU_NONE; 6953 mips_fpu_type_auto = 0; 6954 /* FIXME: cagney/2003-11-15: Should be setting a field in "info" 6955 instead of relying on globals. Doing that would let generic code 6956 handle the search for this specific architecture. */ 6957 if (!gdbarch_update_p (info)) 6958 internal_error (__FILE__, __LINE__, _("set mipsfpu failed")); 6959 } 6960 6961 static void 6962 set_mipsfpu_auto_command (const char *args, int from_tty) 6963 { 6964 mips_fpu_type_auto = 1; 6965 } 6966 6967 /* Just like reinit_frame_cache, but with the right arguments to be 6968 callable as an sfunc. */ 6969 6970 static void 6971 reinit_frame_cache_sfunc (const char *args, int from_tty, 6972 struct cmd_list_element *c) 6973 { 6974 reinit_frame_cache (); 6975 } 6976 6977 static int 6978 gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) 6979 { 6980 gdb_disassembler *di 6981 = static_cast<gdb_disassembler *>(info->application_data); 6982 struct gdbarch *gdbarch = di->arch (); 6983 6984 /* FIXME: cagney/2003-06-26: Is this even necessary? The 6985 disassembler needs to be able to locally determine the ISA, and 6986 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not 6987 work. */ 6988 if (mips_pc_is_mips16 (gdbarch, memaddr)) 6989 info->mach = bfd_mach_mips16; 6990 else if (mips_pc_is_micromips (gdbarch, memaddr)) 6991 info->mach = bfd_mach_mips_micromips; 6992 6993 /* Round down the instruction address to the appropriate boundary. */ 6994 memaddr &= (info->mach == bfd_mach_mips16 6995 || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; 6996 6997 return default_print_insn (memaddr, info); 6998 } 6999 7000 /* Implement the breakpoint_kind_from_pc gdbarch method. */ 7001 7002 static int 7003 mips_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) 7004 { 7005 CORE_ADDR pc = *pcptr; 7006 7007 if (mips_pc_is_mips16 (gdbarch, pc)) 7008 { 7009 *pcptr = unmake_compact_addr (pc); 7010 return MIPS_BP_KIND_MIPS16; 7011 } 7012 else if (mips_pc_is_micromips (gdbarch, pc)) 7013 { 7014 ULONGEST insn; 7015 int status; 7016 7017 *pcptr = unmake_compact_addr (pc); 7018 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, &status); 7019 if (status || (mips_insn_size (ISA_MICROMIPS, insn) == 2)) 7020 return MIPS_BP_KIND_MICROMIPS16; 7021 else 7022 return MIPS_BP_KIND_MICROMIPS32; 7023 } 7024 else 7025 return MIPS_BP_KIND_MIPS32; 7026 } 7027 7028 /* Implement the sw_breakpoint_from_kind gdbarch method. */ 7029 7030 static const gdb_byte * 7031 mips_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) 7032 { 7033 enum bfd_endian byte_order_for_code = gdbarch_byte_order_for_code (gdbarch); 7034 7035 switch (kind) 7036 { 7037 case MIPS_BP_KIND_MIPS16: 7038 { 7039 static gdb_byte mips16_big_breakpoint[] = { 0xe8, 0xa5 }; 7040 static gdb_byte mips16_little_breakpoint[] = { 0xa5, 0xe8 }; 7041 7042 *size = 2; 7043 if (byte_order_for_code == BFD_ENDIAN_BIG) 7044 return mips16_big_breakpoint; 7045 else 7046 return mips16_little_breakpoint; 7047 } 7048 case MIPS_BP_KIND_MICROMIPS16: 7049 { 7050 static gdb_byte micromips16_big_breakpoint[] = { 0x46, 0x85 }; 7051 static gdb_byte micromips16_little_breakpoint[] = { 0x85, 0x46 }; 7052 7053 *size = 2; 7054 7055 if (byte_order_for_code == BFD_ENDIAN_BIG) 7056 return micromips16_big_breakpoint; 7057 else 7058 return micromips16_little_breakpoint; 7059 } 7060 case MIPS_BP_KIND_MICROMIPS32: 7061 { 7062 static gdb_byte micromips32_big_breakpoint[] = { 0, 0x5, 0, 0x7 }; 7063 static gdb_byte micromips32_little_breakpoint[] = { 0x5, 0, 0x7, 0 }; 7064 7065 *size = 4; 7066 if (byte_order_for_code == BFD_ENDIAN_BIG) 7067 return micromips32_big_breakpoint; 7068 else 7069 return micromips32_little_breakpoint; 7070 } 7071 case MIPS_BP_KIND_MIPS32: 7072 { 7073 static gdb_byte big_breakpoint[] = { 0, 0x5, 0, 0xd }; 7074 static gdb_byte little_breakpoint[] = { 0xd, 0, 0x5, 0 }; 7075 7076 *size = 4; 7077 if (byte_order_for_code == BFD_ENDIAN_BIG) 7078 return big_breakpoint; 7079 else 7080 return little_breakpoint; 7081 } 7082 default: 7083 gdb_assert_not_reached ("unexpected mips breakpoint kind"); 7084 }; 7085 } 7086 7087 /* Return non-zero if the standard MIPS instruction INST has a branch 7088 delay slot (i.e. it is a jump or branch instruction). This function 7089 is based on mips32_next_pc. */ 7090 7091 static int 7092 mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) 7093 { 7094 int op; 7095 int rs; 7096 int rt; 7097 7098 op = itype_op (inst); 7099 if ((inst & 0xe0000000) != 0) 7100 { 7101 rs = itype_rs (inst); 7102 rt = itype_rt (inst); 7103 return (is_octeon_bbit_op (op, gdbarch) 7104 || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ 7105 || op == 29 /* JALX: bits 011101 */ 7106 || (op == 17 7107 && (rs == 8 7108 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ 7109 || (rs == 9 && (rt & 0x2) == 0) 7110 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ 7111 || (rs == 10 && (rt & 0x2) == 0)))); 7112 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ 7113 } 7114 else 7115 switch (op & 0x07) /* extract bits 28,27,26 */ 7116 { 7117 case 0: /* SPECIAL */ 7118 op = rtype_funct (inst); 7119 return (op == 8 /* JR */ 7120 || op == 9); /* JALR */ 7121 break; /* end SPECIAL */ 7122 case 1: /* REGIMM */ 7123 rs = itype_rs (inst); 7124 rt = itype_rt (inst); /* branch condition */ 7125 return ((rt & 0xc) == 0 7126 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ 7127 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ 7128 || ((rt & 0x1e) == 0x1c && rs == 0)); 7129 /* BPOSGE32, BPOSGE64: bits 1110x */ 7130 break; /* end REGIMM */ 7131 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ 7132 return 1; 7133 break; 7134 } 7135 } 7136 7137 /* Return non-zero if a standard MIPS instruction at ADDR has a branch 7138 delay slot (i.e. it is a jump or branch instruction). */ 7139 7140 static int 7141 mips32_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr) 7142 { 7143 ULONGEST insn; 7144 int status; 7145 7146 insn = mips_fetch_instruction (gdbarch, ISA_MIPS, addr, &status); 7147 if (status) 7148 return 0; 7149 7150 return mips32_instruction_has_delay_slot (gdbarch, insn); 7151 } 7152 7153 /* Return non-zero if the microMIPS instruction INSN, comprising the 7154 16-bit major opcode word in the high 16 bits and any second word 7155 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact 7156 jump or branch instruction). The instruction must be 32-bit if 7157 MUSTBE32 is set or can be any instruction otherwise. */ 7158 7159 static int 7160 micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) 7161 { 7162 ULONGEST major = insn >> 16; 7163 7164 switch (micromips_op (major)) 7165 { 7166 /* 16-bit instructions. */ 7167 case 0x33: /* B16: bits 110011 */ 7168 case 0x2b: /* BNEZ16: bits 101011 */ 7169 case 0x23: /* BEQZ16: bits 100011 */ 7170 return !mustbe32; 7171 case 0x11: /* POOL16C: bits 010001 */ 7172 return (!mustbe32 7173 && ((b5s5_op (major) == 0xc 7174 /* JR16: bits 010001 01100 */ 7175 || (b5s5_op (major) & 0x1e) == 0xe))); 7176 /* JALR16, JALRS16: bits 010001 0111x */ 7177 /* 32-bit instructions. */ 7178 case 0x3d: /* JAL: bits 111101 */ 7179 case 0x3c: /* JALX: bits 111100 */ 7180 case 0x35: /* J: bits 110101 */ 7181 case 0x2d: /* BNE: bits 101101 */ 7182 case 0x25: /* BEQ: bits 100101 */ 7183 case 0x1d: /* JALS: bits 011101 */ 7184 return 1; 7185 case 0x10: /* POOL32I: bits 010000 */ 7186 return ((b5s5_op (major) & 0x1c) == 0x0 7187 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ 7188 || (b5s5_op (major) & 0x1d) == 0x4 7189 /* BLEZ, BGTZ: bits 010000 001x0 */ 7190 || (b5s5_op (major) & 0x1d) == 0x11 7191 /* BLTZALS, BGEZALS: bits 010000 100x1 */ 7192 || ((b5s5_op (major) & 0x1e) == 0x14 7193 && (major & 0x3) == 0x0) 7194 /* BC2F, BC2T: bits 010000 1010x xxx00 */ 7195 || (b5s5_op (major) & 0x1e) == 0x1a 7196 /* BPOSGE64, BPOSGE32: bits 010000 1101x */ 7197 || ((b5s5_op (major) & 0x1e) == 0x1c 7198 && (major & 0x3) == 0x0) 7199 /* BC1F, BC1T: bits 010000 1110x xxx00 */ 7200 || ((b5s5_op (major) & 0x1c) == 0x1c 7201 && (major & 0x3) == 0x1)); 7202 /* BC1ANY*: bits 010000 111xx xxx01 */ 7203 case 0x0: /* POOL32A: bits 000000 */ 7204 return (b0s6_op (insn) == 0x3c 7205 /* POOL32Axf: bits 000000 ... 111100 */ 7206 && (b6s10_ext (insn) & 0x2bf) == 0x3c); 7207 /* JALR, JALR.HB: 000000 000x111100 111100 */ 7208 /* JALRS, JALRS.HB: 000000 010x111100 111100 */ 7209 default: 7210 return 0; 7211 } 7212 } 7213 7214 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay 7215 slot (i.e. it is a non-compact jump instruction). The instruction 7216 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7217 7218 static int 7219 micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7220 CORE_ADDR addr, int mustbe32) 7221 { 7222 ULONGEST insn; 7223 int status; 7224 int size; 7225 7226 insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7227 if (status) 7228 return 0; 7229 size = mips_insn_size (ISA_MICROMIPS, insn); 7230 insn <<= 16; 7231 if (size == 2 * MIPS_INSN16_SIZE) 7232 { 7233 insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, addr, &status); 7234 if (status) 7235 return 0; 7236 } 7237 7238 return micromips_instruction_has_delay_slot (insn, mustbe32); 7239 } 7240 7241 /* Return non-zero if the MIPS16 instruction INST, which must be 7242 a 32-bit instruction if MUSTBE32 is set or can be any instruction 7243 otherwise, has a branch delay slot (i.e. it is a non-compact jump 7244 instruction). This function is based on mips16_next_pc. */ 7245 7246 static int 7247 mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) 7248 { 7249 if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ 7250 return !mustbe32; 7251 return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ 7252 } 7253 7254 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay 7255 slot (i.e. it is a non-compact jump instruction). The instruction 7256 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ 7257 7258 static int 7259 mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, 7260 CORE_ADDR addr, int mustbe32) 7261 { 7262 unsigned short insn; 7263 int status; 7264 7265 insn = mips_fetch_instruction (gdbarch, ISA_MIPS16, addr, &status); 7266 if (status) 7267 return 0; 7268 7269 return mips16_instruction_has_delay_slot (insn, mustbe32); 7270 } 7271 7272 /* Calculate the starting address of the MIPS memory segment BPADDR is in. 7273 This assumes KSSEG exists. */ 7274 7275 static CORE_ADDR 7276 mips_segment_boundary (CORE_ADDR bpaddr) 7277 { 7278 CORE_ADDR mask = CORE_ADDR_MAX; 7279 int segsize; 7280 7281 if (sizeof (CORE_ADDR) == 8) 7282 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid 7283 a compiler warning produced where CORE_ADDR is a 32-bit type even 7284 though in that case this is dead code). */ 7285 switch (bpaddr >> ((sizeof (CORE_ADDR) << 3) - 2) & 3) 7286 { 7287 case 3: 7288 if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) 7289 segsize = 29; /* 32-bit compatibility segment */ 7290 else 7291 segsize = 62; /* xkseg */ 7292 break; 7293 case 2: /* xkphys */ 7294 segsize = 59; 7295 break; 7296 default: /* xksseg (1), xkuseg/kuseg (0) */ 7297 segsize = 62; 7298 break; 7299 } 7300 else if (bpaddr & 0x80000000) /* kernel segment */ 7301 segsize = 29; 7302 else 7303 segsize = 31; /* user segment */ 7304 mask <<= segsize; 7305 return bpaddr & mask; 7306 } 7307 7308 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting 7309 it backwards if necessary. Return the address of the new location. */ 7310 7311 static CORE_ADDR 7312 mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) 7313 { 7314 CORE_ADDR prev_addr; 7315 CORE_ADDR boundary; 7316 CORE_ADDR func_addr; 7317 7318 /* If a breakpoint is set on the instruction in a branch delay slot, 7319 GDB gets confused. When the breakpoint is hit, the PC isn't on 7320 the instruction in the branch delay slot, the PC will point to 7321 the branch instruction. Since the PC doesn't match any known 7322 breakpoints, GDB reports a trap exception. 7323 7324 There are two possible fixes for this problem. 7325 7326 1) When the breakpoint gets hit, see if the BD bit is set in the 7327 Cause register (which indicates the last exception occurred in a 7328 branch delay slot). If the BD bit is set, fix the PC to point to 7329 the instruction in the branch delay slot. 7330 7331 2) When the user sets the breakpoint, don't allow him to set the 7332 breakpoint on the instruction in the branch delay slot. Instead 7333 move the breakpoint to the branch instruction (which will have 7334 the same result). 7335 7336 The problem with the first solution is that if the user then 7337 single-steps the processor, the branch instruction will get 7338 skipped (since GDB thinks the PC is on the instruction in the 7339 branch delay slot). 7340 7341 So, we'll use the second solution. To do this we need to know if 7342 the instruction we're trying to set the breakpoint on is in the 7343 branch delay slot. */ 7344 7345 boundary = mips_segment_boundary (bpaddr); 7346 7347 /* Make sure we don't scan back before the beginning of the current 7348 function, since we may fetch constant data or insns that look like 7349 a jump. Of course we might do that anyway if the compiler has 7350 moved constants inline. :-( */ 7351 if (find_pc_partial_function (bpaddr, NULL, &func_addr, NULL) 7352 && func_addr > boundary && func_addr <= bpaddr) 7353 boundary = func_addr; 7354 7355 if (mips_pc_is_mips (bpaddr)) 7356 { 7357 if (bpaddr == boundary) 7358 return bpaddr; 7359 7360 /* If the previous instruction has a branch delay slot, we have 7361 to move the breakpoint to the branch instruction. */ 7362 prev_addr = bpaddr - 4; 7363 if (mips32_insn_at_pc_has_delay_slot (gdbarch, prev_addr)) 7364 bpaddr = prev_addr; 7365 } 7366 else 7367 { 7368 int (*insn_at_pc_has_delay_slot) (struct gdbarch *, CORE_ADDR, int); 7369 CORE_ADDR addr, jmpaddr; 7370 int i; 7371 7372 boundary = unmake_compact_addr (boundary); 7373 7374 /* The only MIPS16 instructions with delay slots are JAL, JALX, 7375 JALR and JR. An absolute JAL/JALX is always 4 bytes long, 7376 so try for that first, then try the 2 byte JALR/JR. 7377 The microMIPS ASE has a whole range of jumps and branches 7378 with delay slots, some of which take 4 bytes and some take 7379 2 bytes, so the idea is the same. 7380 FIXME: We have to assume that bpaddr is not the second half 7381 of an extended instruction. */ 7382 insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) 7383 ? micromips_insn_at_pc_has_delay_slot 7384 : mips16_insn_at_pc_has_delay_slot); 7385 7386 jmpaddr = 0; 7387 addr = bpaddr; 7388 for (i = 1; i < 4; i++) 7389 { 7390 if (unmake_compact_addr (addr) == boundary) 7391 break; 7392 addr -= MIPS_INSN16_SIZE; 7393 if (i == 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 0)) 7394 /* Looks like a JR/JALR at [target-1], but it could be 7395 the second word of a previous JAL/JALX, so record it 7396 and check back one more. */ 7397 jmpaddr = addr; 7398 else if (i > 1 && insn_at_pc_has_delay_slot (gdbarch, addr, 1)) 7399 { 7400 if (i == 2) 7401 /* Looks like a JAL/JALX at [target-2], but it could also 7402 be the second word of a previous JAL/JALX, record it, 7403 and check back one more. */ 7404 jmpaddr = addr; 7405 else 7406 /* Looks like a JAL/JALX at [target-3], so any previously 7407 recorded JAL/JALX or JR/JALR must be wrong, because: 7408 7409 >-3: JAL 7410 -2: JAL-ext (can't be JAL/JALX) 7411 -1: bdslot (can't be JR/JALR) 7412 0: target insn 7413 7414 Of course it could be another JAL-ext which looks 7415 like a JAL, but in that case we'd have broken out 7416 of this loop at [target-2]: 7417 7418 -4: JAL 7419 >-3: JAL-ext 7420 -2: bdslot (can't be jmp) 7421 -1: JR/JALR 7422 0: target insn */ 7423 jmpaddr = 0; 7424 } 7425 else 7426 { 7427 /* Not a jump instruction: if we're at [target-1] this 7428 could be the second word of a JAL/JALX, so continue; 7429 otherwise we're done. */ 7430 if (i > 1) 7431 break; 7432 } 7433 } 7434 7435 if (jmpaddr) 7436 bpaddr = jmpaddr; 7437 } 7438 7439 return bpaddr; 7440 } 7441 7442 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16 7443 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */ 7444 7445 static int 7446 mips_is_stub_suffix (const char *suffix, int zero) 7447 { 7448 switch (suffix[0]) 7449 { 7450 case '0': 7451 return zero && suffix[1] == '\0'; 7452 case '1': 7453 return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); 7454 case '2': 7455 case '5': 7456 case '6': 7457 case '9': 7458 return suffix[1] == '\0'; 7459 default: 7460 return 0; 7461 } 7462 } 7463 7464 /* Return non-zero if MODE is one of the mode infixes used for MIPS16 7465 call stubs, one of sf, df, sc, or dc. */ 7466 7467 static int 7468 mips_is_stub_mode (const char *mode) 7469 { 7470 return ((mode[0] == 's' || mode[0] == 'd') 7471 && (mode[1] == 'f' || mode[1] == 'c')); 7472 } 7473 7474 /* Code at PC is a compiler-generated stub. Such a stub for a function 7475 bar might have a name like __fn_stub_bar, and might look like this: 7476 7477 mfc1 $4, $f13 7478 mfc1 $5, $f12 7479 mfc1 $6, $f15 7480 mfc1 $7, $f14 7481 7482 followed by (or interspersed with): 7483 7484 j bar 7485 7486 or: 7487 7488 lui $25, %hi(bar) 7489 addiu $25, $25, %lo(bar) 7490 jr $25 7491 7492 ($1 may be used in old code; for robustness we accept any register) 7493 or, in PIC code: 7494 7495 lui $28, %hi(_gp_disp) 7496 addiu $28, $28, %lo(_gp_disp) 7497 addu $28, $28, $25 7498 lw $25, %got(bar) 7499 addiu $25, $25, %lo(bar) 7500 jr $25 7501 7502 In the case of a __call_stub_bar stub, the sequence to set up 7503 arguments might look like this: 7504 7505 mtc1 $4, $f13 7506 mtc1 $5, $f12 7507 mtc1 $6, $f15 7508 mtc1 $7, $f14 7509 7510 followed by (or interspersed with) one of the jump sequences above. 7511 7512 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead 7513 of J or JR, respectively, followed by: 7514 7515 mfc1 $2, $f0 7516 mfc1 $3, $f1 7517 jr $18 7518 7519 We are at the beginning of the stub here, and scan down and extract 7520 the target address from the jump immediate instruction or, if a jump 7521 register instruction is used, from the register referred. Return 7522 the value of PC calculated or 0 if inconclusive. 7523 7524 The limit on the search is arbitrarily set to 20 instructions. FIXME. */ 7525 7526 static CORE_ADDR 7527 mips_get_mips16_fn_stub_pc (struct frame_info *frame, CORE_ADDR pc) 7528 { 7529 struct gdbarch *gdbarch = get_frame_arch (frame); 7530 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7531 int addrreg = MIPS_ZERO_REGNUM; 7532 CORE_ADDR start_pc = pc; 7533 CORE_ADDR target_pc = 0; 7534 CORE_ADDR addr = 0; 7535 CORE_ADDR gp = 0; 7536 int status = 0; 7537 int i; 7538 7539 for (i = 0; 7540 status == 0 && target_pc == 0 && i < 20; 7541 i++, pc += MIPS_INSN32_SIZE) 7542 { 7543 ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); 7544 CORE_ADDR imm; 7545 int rt; 7546 int rs; 7547 int rd; 7548 7549 switch (itype_op (inst)) 7550 { 7551 case 0: /* SPECIAL */ 7552 switch (rtype_funct (inst)) 7553 { 7554 case 8: /* JR */ 7555 case 9: /* JALR */ 7556 rs = rtype_rs (inst); 7557 if (rs == MIPS_GP_REGNUM) 7558 target_pc = gp; /* Hmm... */ 7559 else if (rs == addrreg) 7560 target_pc = addr; 7561 break; 7562 7563 case 0x21: /* ADDU */ 7564 rt = rtype_rt (inst); 7565 rs = rtype_rs (inst); 7566 rd = rtype_rd (inst); 7567 if (rd == MIPS_GP_REGNUM 7568 && ((rs == MIPS_GP_REGNUM && rt == MIPS_T9_REGNUM) 7569 || (rs == MIPS_T9_REGNUM && rt == MIPS_GP_REGNUM))) 7570 gp += start_pc; 7571 break; 7572 } 7573 break; 7574 7575 case 2: /* J */ 7576 case 3: /* JAL */ 7577 target_pc = jtype_target (inst) << 2; 7578 target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); 7579 break; 7580 7581 case 9: /* ADDIU */ 7582 rt = itype_rt (inst); 7583 rs = itype_rs (inst); 7584 if (rt == rs) 7585 { 7586 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7587 if (rt == MIPS_GP_REGNUM) 7588 gp += imm; 7589 else if (rt == addrreg) 7590 addr += imm; 7591 } 7592 break; 7593 7594 case 0xf: /* LUI */ 7595 rt = itype_rt (inst); 7596 imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; 7597 if (rt == MIPS_GP_REGNUM) 7598 gp = imm; 7599 else if (rt != MIPS_ZERO_REGNUM) 7600 { 7601 addrreg = rt; 7602 addr = imm; 7603 } 7604 break; 7605 7606 case 0x23: /* LW */ 7607 rt = itype_rt (inst); 7608 rs = itype_rs (inst); 7609 imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; 7610 if (gp != 0 && rs == MIPS_GP_REGNUM) 7611 { 7612 gdb_byte buf[4]; 7613 7614 memset (buf, 0, sizeof (buf)); 7615 status = target_read_memory (gp + imm, buf, sizeof (buf)); 7616 addrreg = rt; 7617 addr = extract_signed_integer (buf, sizeof (buf), byte_order); 7618 } 7619 break; 7620 } 7621 } 7622 7623 return target_pc; 7624 } 7625 7626 /* If PC is in a MIPS16 call or return stub, return the address of the 7627 target PC, which is either the callee or the caller. There are several 7628 cases which must be handled: 7629 7630 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7631 and the target PC is in $31 ($ra). 7632 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7633 and the target PC is in $2. 7634 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7635 i.e. before the JALR instruction, this is effectively a call stub 7636 and the target PC is in $2. Otherwise this is effectively 7637 a return stub and the target PC is in $18. 7638 * If the PC is at the start of __call_stub_fp_*, i.e. before the 7639 JAL or JALR instruction, this is effectively a call stub and the 7640 target PC is buried in the instruction stream. Otherwise this 7641 is effectively a return stub and the target PC is in $18. 7642 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call 7643 stub and the target PC is buried in the instruction stream. 7644 7645 See the source code for the stubs in gcc/config/mips/mips16.S, or the 7646 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the 7647 gory details. */ 7648 7649 static CORE_ADDR 7650 mips_skip_mips16_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7651 { 7652 struct gdbarch *gdbarch = get_frame_arch (frame); 7653 CORE_ADDR start_addr; 7654 const char *name; 7655 size_t prefixlen; 7656 7657 /* Find the starting address and name of the function containing the PC. */ 7658 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0) 7659 return 0; 7660 7661 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub 7662 and the target PC is in $31 ($ra). */ 7663 prefixlen = strlen (mips_str_mips16_ret_stub); 7664 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7665 && mips_is_stub_mode (name + prefixlen) 7666 && name[prefixlen + 2] == '\0') 7667 return get_frame_register_signed 7668 (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); 7669 7670 /* If the PC is in __mips16_call_stub_*, this is one of the call 7671 call/return stubs. */ 7672 prefixlen = strlen (mips_str_mips16_call_stub); 7673 if (strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0) 7674 { 7675 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub 7676 and the target PC is in $2. */ 7677 if (mips_is_stub_suffix (name + prefixlen, 0)) 7678 return get_frame_register_signed 7679 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7680 7681 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, 7682 i.e. before the JALR instruction, this is effectively a call stub 7683 and the target PC is in $2. Otherwise this is effectively 7684 a return stub and the target PC is in $18. */ 7685 else if (mips_is_stub_mode (name + prefixlen) 7686 && name[prefixlen + 2] == '_' 7687 && mips_is_stub_suffix (name + prefixlen + 3, 0)) 7688 { 7689 if (pc == start_addr) 7690 /* This is the 'call' part of a call stub. The return 7691 address is in $2. */ 7692 return get_frame_register_signed 7693 (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); 7694 else 7695 /* This is the 'return' part of a call stub. The return 7696 address is in $18. */ 7697 return get_frame_register_signed 7698 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7699 } 7700 else 7701 return 0; /* Not a stub. */ 7702 } 7703 7704 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the 7705 compiler-generated call or call/return stubs. */ 7706 if (startswith (name, mips_str_fn_stub) 7707 || startswith (name, mips_str_call_stub)) 7708 { 7709 if (pc == start_addr) 7710 /* This is the 'call' part of a call stub. Call this helper 7711 to scan through this code for interesting instructions 7712 and determine the final PC. */ 7713 return mips_get_mips16_fn_stub_pc (frame, pc); 7714 else 7715 /* This is the 'return' part of a call stub. The return address 7716 is in $18. */ 7717 return get_frame_register_signed 7718 (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); 7719 } 7720 7721 return 0; /* Not a stub. */ 7722 } 7723 7724 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). 7725 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */ 7726 7727 static int 7728 mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) 7729 { 7730 CORE_ADDR start_addr; 7731 size_t prefixlen; 7732 7733 /* Find the starting address of the function containing the PC. */ 7734 if (find_pc_partial_function (pc, NULL, &start_addr, NULL) == 0) 7735 return 0; 7736 7737 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at 7738 the start, i.e. after the JALR instruction, this is effectively 7739 a return stub. */ 7740 prefixlen = strlen (mips_str_mips16_call_stub); 7741 if (pc != start_addr 7742 && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 7743 && mips_is_stub_mode (name + prefixlen) 7744 && name[prefixlen + 2] == '_' 7745 && mips_is_stub_suffix (name + prefixlen + 3, 1)) 7746 return 1; 7747 7748 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after 7749 the JAL or JALR instruction, this is effectively a return stub. */ 7750 prefixlen = strlen (mips_str_call_fp_stub); 7751 if (pc != start_addr 7752 && strncmp (name, mips_str_call_fp_stub, prefixlen) == 0) 7753 return 1; 7754 7755 /* Consume the .pic. prefix of any PIC stub, this function must return 7756 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub 7757 or the call stub path will trigger in handle_inferior_event causing 7758 it to go astray. */ 7759 prefixlen = strlen (mips_str_pic); 7760 if (strncmp (name, mips_str_pic, prefixlen) == 0) 7761 name += prefixlen; 7762 7763 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ 7764 prefixlen = strlen (mips_str_mips16_ret_stub); 7765 if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 7766 && mips_is_stub_mode (name + prefixlen) 7767 && name[prefixlen + 2] == '\0') 7768 return 1; 7769 7770 return 0; /* Not a stub. */ 7771 } 7772 7773 /* If the current PC is the start of a non-PIC-to-PIC stub, return the 7774 PC of the stub target. The stub just loads $t9 and jumps to it, 7775 so that $t9 has the correct value at function entry. */ 7776 7777 static CORE_ADDR 7778 mips_skip_pic_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7779 { 7780 struct gdbarch *gdbarch = get_frame_arch (frame); 7781 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7782 struct bound_minimal_symbol msym; 7783 int i; 7784 gdb_byte stub_code[16]; 7785 int32_t stub_words[4]; 7786 7787 /* The stub for foo is named ".pic.foo", and is either two 7788 instructions inserted before foo or a three instruction sequence 7789 which jumps to foo. */ 7790 msym = lookup_minimal_symbol_by_pc (pc); 7791 if (msym.minsym == NULL 7792 || BMSYMBOL_VALUE_ADDRESS (msym) != pc 7793 || msym.minsym->linkage_name () == NULL 7794 || !startswith (msym.minsym->linkage_name (), ".pic.")) 7795 return 0; 7796 7797 /* A two-instruction header. */ 7798 if (MSYMBOL_SIZE (msym.minsym) == 8) 7799 return pc + 8; 7800 7801 /* A three-instruction (plus delay slot) trampoline. */ 7802 if (MSYMBOL_SIZE (msym.minsym) == 16) 7803 { 7804 if (target_read_memory (pc, stub_code, 16) != 0) 7805 return 0; 7806 for (i = 0; i < 4; i++) 7807 stub_words[i] = extract_unsigned_integer (stub_code + i * 4, 7808 4, byte_order); 7809 7810 /* A stub contains these instructions: 7811 lui t9, %hi(target) 7812 j target 7813 addiu t9, t9, %lo(target) 7814 nop 7815 7816 This works even for N64, since stubs are only generated with 7817 -msym32. */ 7818 if ((stub_words[0] & 0xffff0000U) == 0x3c190000 7819 && (stub_words[1] & 0xfc000000U) == 0x08000000 7820 && (stub_words[2] & 0xffff0000U) == 0x27390000 7821 && stub_words[3] == 0x00000000) 7822 return ((((stub_words[0] & 0x0000ffff) << 16) 7823 + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; 7824 } 7825 7826 /* Not a recognized stub. */ 7827 return 0; 7828 } 7829 7830 static CORE_ADDR 7831 mips_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 7832 { 7833 CORE_ADDR requested_pc = pc; 7834 CORE_ADDR target_pc; 7835 CORE_ADDR new_pc; 7836 7837 do 7838 { 7839 target_pc = pc; 7840 7841 new_pc = mips_skip_mips16_trampoline_code (frame, pc); 7842 if (new_pc) 7843 pc = new_pc; 7844 7845 new_pc = find_solib_trampoline_target (frame, pc); 7846 if (new_pc) 7847 pc = new_pc; 7848 7849 new_pc = mips_skip_pic_trampoline_code (frame, pc); 7850 if (new_pc) 7851 pc = new_pc; 7852 } 7853 while (pc != target_pc); 7854 7855 return pc != requested_pc ? pc : 0; 7856 } 7857 7858 /* Convert a dbx stab register number (from `r' declaration) to a GDB 7859 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7860 7861 static int 7862 mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) 7863 { 7864 int regnum; 7865 if (num >= 0 && num < 32) 7866 regnum = num; 7867 else if (num >= 38 && num < 70) 7868 regnum = num + mips_regnum (gdbarch)->fp0 - 38; 7869 else if (num == 70) 7870 regnum = mips_regnum (gdbarch)->hi; 7871 else if (num == 71) 7872 regnum = mips_regnum (gdbarch)->lo; 7873 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 72 && num < 78) 7874 regnum = num + mips_regnum (gdbarch)->dspacc - 72; 7875 else 7876 return -1; 7877 return gdbarch_num_regs (gdbarch) + regnum; 7878 } 7879 7880 7881 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * 7882 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ 7883 7884 static int 7885 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch *gdbarch, int num) 7886 { 7887 int regnum; 7888 if (num >= 0 && num < 32) 7889 regnum = num; 7890 else if (num >= 32 && num < 64) 7891 regnum = num + mips_regnum (gdbarch)->fp0 - 32; 7892 else if (num == 64) 7893 regnum = mips_regnum (gdbarch)->hi; 7894 else if (num == 65) 7895 regnum = mips_regnum (gdbarch)->lo; 7896 else if (mips_regnum (gdbarch)->dspacc != -1 && num >= 66 && num < 72) 7897 regnum = num + mips_regnum (gdbarch)->dspacc - 66; 7898 else 7899 return -1; 7900 return gdbarch_num_regs (gdbarch) + regnum; 7901 } 7902 7903 static int 7904 mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) 7905 { 7906 /* Only makes sense to supply raw registers. */ 7907 gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); 7908 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to 7909 decide if it is valid. Should instead define a standard sim/gdb 7910 register numbering scheme. */ 7911 if (gdbarch_register_name (gdbarch, 7912 gdbarch_num_regs (gdbarch) + regnum) != NULL 7913 && gdbarch_register_name (gdbarch, 7914 gdbarch_num_regs (gdbarch) 7915 + regnum)[0] != '\0') 7916 return regnum; 7917 else 7918 return LEGACY_SIM_REGNO_IGNORE; 7919 } 7920 7921 7922 /* Convert an integer into an address. Extracting the value signed 7923 guarantees a correctly sign extended address. */ 7924 7925 static CORE_ADDR 7926 mips_integer_to_address (struct gdbarch *gdbarch, 7927 struct type *type, const gdb_byte *buf) 7928 { 7929 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 7930 return extract_signed_integer (buf, TYPE_LENGTH (type), byte_order); 7931 } 7932 7933 /* Dummy virtual frame pointer method. This is no more or less accurate 7934 than most other architectures; we just need to be explicit about it, 7935 because the pseudo-register gdbarch_sp_regnum will otherwise lead to 7936 an assertion failure. */ 7937 7938 static void 7939 mips_virtual_frame_pointer (struct gdbarch *gdbarch, 7940 CORE_ADDR pc, int *reg, LONGEST *offset) 7941 { 7942 *reg = MIPS_SP_REGNUM; 7943 *offset = 0; 7944 } 7945 7946 static void 7947 mips_find_abi_section (bfd *abfd, asection *sect, void *obj) 7948 { 7949 enum mips_abi *abip = (enum mips_abi *) obj; 7950 const char *name = bfd_section_name (sect); 7951 7952 if (*abip != MIPS_ABI_UNKNOWN) 7953 return; 7954 7955 if (!startswith (name, ".mdebug.")) 7956 return; 7957 7958 if (strcmp (name, ".mdebug.abi32") == 0) 7959 *abip = MIPS_ABI_O32; 7960 else if (strcmp (name, ".mdebug.abiN32") == 0) 7961 *abip = MIPS_ABI_N32; 7962 else if (strcmp (name, ".mdebug.abi64") == 0) 7963 *abip = MIPS_ABI_N64; 7964 else if (strcmp (name, ".mdebug.abiO64") == 0) 7965 *abip = MIPS_ABI_O64; 7966 else if (strcmp (name, ".mdebug.eabi32") == 0) 7967 *abip = MIPS_ABI_EABI32; 7968 else if (strcmp (name, ".mdebug.eabi64") == 0) 7969 *abip = MIPS_ABI_EABI64; 7970 else 7971 warning (_("unsupported ABI %s."), name + 8); 7972 } 7973 7974 static void 7975 mips_find_long_section (bfd *abfd, asection *sect, void *obj) 7976 { 7977 int *lbp = (int *) obj; 7978 const char *name = bfd_section_name (sect); 7979 7980 if (startswith (name, ".gcc_compiled_long32")) 7981 *lbp = 32; 7982 else if (startswith (name, ".gcc_compiled_long64")) 7983 *lbp = 64; 7984 else if (startswith (name, ".gcc_compiled_long")) 7985 warning (_("unrecognized .gcc_compiled_longXX")); 7986 } 7987 7988 static enum mips_abi 7989 global_mips_abi (void) 7990 { 7991 int i; 7992 7993 for (i = 0; mips_abi_strings[i] != NULL; i++) 7994 if (mips_abi_strings[i] == mips_abi_string) 7995 return (enum mips_abi) i; 7996 7997 internal_error (__FILE__, __LINE__, _("unknown ABI string")); 7998 } 7999 8000 /* Return the default compressed instruction set, either of MIPS16 8001 or microMIPS, selected when none could have been determined from 8002 the ELF header of the binary being executed (or no binary has been 8003 selected. */ 8004 8005 static enum mips_isa 8006 global_mips_compression (void) 8007 { 8008 int i; 8009 8010 for (i = 0; mips_compression_strings[i] != NULL; i++) 8011 if (mips_compression_strings[i] == mips_compression_string) 8012 return (enum mips_isa) i; 8013 8014 internal_error (__FILE__, __LINE__, _("unknown compressed ISA string")); 8015 } 8016 8017 static void 8018 mips_register_g_packet_guesses (struct gdbarch *gdbarch) 8019 { 8020 /* If the size matches the set of 32-bit or 64-bit integer registers, 8021 assume that's what we've got. */ 8022 register_remote_g_packet_guess (gdbarch, 38 * 4, mips_tdesc_gp32); 8023 register_remote_g_packet_guess (gdbarch, 38 * 8, mips_tdesc_gp64); 8024 8025 /* If the size matches the full set of registers GDB traditionally 8026 knows about, including floating point, for either 32-bit or 8027 64-bit, assume that's what we've got. */ 8028 register_remote_g_packet_guess (gdbarch, 90 * 4, mips_tdesc_gp32); 8029 register_remote_g_packet_guess (gdbarch, 90 * 8, mips_tdesc_gp64); 8030 8031 /* Otherwise we don't have a useful guess. */ 8032 } 8033 8034 static struct value * 8035 value_of_mips_user_reg (struct frame_info *frame, const void *baton) 8036 { 8037 const int *reg_p = (const int *) baton; 8038 return value_of_register (*reg_p, frame); 8039 } 8040 8041 static struct gdbarch * 8042 mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 8043 { 8044 struct gdbarch *gdbarch; 8045 struct gdbarch_tdep *tdep; 8046 int elf_flags; 8047 enum mips_abi mips_abi, found_abi, wanted_abi; 8048 int i, num_regs; 8049 enum mips_fpu_type fpu_type; 8050 struct tdesc_arch_data *tdesc_data = NULL; 8051 int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; 8052 const char **reg_names; 8053 struct mips_regnum mips_regnum, *regnum; 8054 enum mips_isa mips_isa; 8055 int dspacc; 8056 int dspctl; 8057 8058 /* First of all, extract the elf_flags, if available. */ 8059 if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8060 elf_flags = elf_elfheader (info.abfd)->e_flags; 8061 else if (arches != NULL) 8062 elf_flags = gdbarch_tdep (arches->gdbarch)->elf_flags; 8063 else 8064 elf_flags = 0; 8065 if (gdbarch_debug) 8066 fprintf_unfiltered (gdb_stdlog, 8067 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); 8068 8069 /* Check ELF_FLAGS to see if it specifies the ABI being used. */ 8070 switch ((elf_flags & EF_MIPS_ABI)) 8071 { 8072 case E_MIPS_ABI_O32: 8073 found_abi = MIPS_ABI_O32; 8074 break; 8075 case E_MIPS_ABI_O64: 8076 found_abi = MIPS_ABI_O64; 8077 break; 8078 case E_MIPS_ABI_EABI32: 8079 found_abi = MIPS_ABI_EABI32; 8080 break; 8081 case E_MIPS_ABI_EABI64: 8082 found_abi = MIPS_ABI_EABI64; 8083 break; 8084 default: 8085 if ((elf_flags & EF_MIPS_ABI2)) 8086 found_abi = MIPS_ABI_N32; 8087 else 8088 found_abi = MIPS_ABI_UNKNOWN; 8089 break; 8090 } 8091 8092 /* GCC creates a pseudo-section whose name describes the ABI. */ 8093 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL) 8094 bfd_map_over_sections (info.abfd, mips_find_abi_section, &found_abi); 8095 8096 /* If we have no useful BFD information, use the ABI from the last 8097 MIPS architecture (if there is one). */ 8098 if (found_abi == MIPS_ABI_UNKNOWN && info.abfd == NULL && arches != NULL) 8099 found_abi = gdbarch_tdep (arches->gdbarch)->found_abi; 8100 8101 /* Try the architecture for any hint of the correct ABI. */ 8102 if (found_abi == MIPS_ABI_UNKNOWN 8103 && info.bfd_arch_info != NULL 8104 && info.bfd_arch_info->arch == bfd_arch_mips) 8105 { 8106 switch (info.bfd_arch_info->mach) 8107 { 8108 case bfd_mach_mips3900: 8109 found_abi = MIPS_ABI_EABI32; 8110 break; 8111 case bfd_mach_mips4100: 8112 case bfd_mach_mips5000: 8113 found_abi = MIPS_ABI_EABI64; 8114 break; 8115 case bfd_mach_mips8000: 8116 case bfd_mach_mips10000: 8117 /* On Irix, ELF64 executables use the N64 ABI. The 8118 pseudo-sections which describe the ABI aren't present 8119 on IRIX. (Even for executables created by gcc.) */ 8120 if (info.abfd != NULL 8121 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8122 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8123 found_abi = MIPS_ABI_N64; 8124 else 8125 found_abi = MIPS_ABI_N32; 8126 break; 8127 } 8128 } 8129 8130 /* Default 64-bit objects to N64 instead of O32. */ 8131 if (found_abi == MIPS_ABI_UNKNOWN 8132 && info.abfd != NULL 8133 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour 8134 && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 8135 found_abi = MIPS_ABI_N64; 8136 8137 if (gdbarch_debug) 8138 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", 8139 found_abi); 8140 8141 /* What has the user specified from the command line? */ 8142 wanted_abi = global_mips_abi (); 8143 if (gdbarch_debug) 8144 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: wanted_abi = %d\n", 8145 wanted_abi); 8146 8147 /* Now that we have found what the ABI for this binary would be, 8148 check whether the user is overriding it. */ 8149 if (wanted_abi != MIPS_ABI_UNKNOWN) 8150 mips_abi = wanted_abi; 8151 else if (found_abi != MIPS_ABI_UNKNOWN) 8152 mips_abi = found_abi; 8153 else 8154 mips_abi = MIPS_ABI_O32; 8155 if (gdbarch_debug) 8156 fprintf_unfiltered (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", 8157 mips_abi); 8158 8159 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ 8160 if (mips_abi != MIPS_ABI_EABI32 8161 && mips_abi != MIPS_ABI_O32 8162 && info.bfd_arch_info != NULL 8163 && info.bfd_arch_info->arch == bfd_arch_mips 8164 && info.bfd_arch_info->bits_per_word < 64) 8165 info.bfd_arch_info = bfd_lookup_arch (bfd_arch_mips, bfd_mach_mips4000); 8166 8167 /* Determine the default compressed ISA. */ 8168 if ((elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) != 0 8169 && (elf_flags & EF_MIPS_ARCH_ASE_M16) == 0) 8170 mips_isa = ISA_MICROMIPS; 8171 else if ((elf_flags & EF_MIPS_ARCH_ASE_M16) != 0 8172 && (elf_flags & EF_MIPS_ARCH_ASE_MICROMIPS) == 0) 8173 mips_isa = ISA_MIPS16; 8174 else 8175 mips_isa = global_mips_compression (); 8176 mips_compression_string = mips_compression_strings[mips_isa]; 8177 8178 /* Also used when doing an architecture lookup. */ 8179 if (gdbarch_debug) 8180 fprintf_unfiltered (gdb_stdlog, 8181 "mips_gdbarch_init: " 8182 "mips64_transfers_32bit_regs_p = %d\n", 8183 mips64_transfers_32bit_regs_p); 8184 8185 /* Determine the MIPS FPU type. */ 8186 #ifdef HAVE_ELF 8187 if (info.abfd 8188 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 8189 elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, 8190 Tag_GNU_MIPS_ABI_FP); 8191 #endif /* HAVE_ELF */ 8192 8193 if (!mips_fpu_type_auto) 8194 fpu_type = mips_fpu_type; 8195 else if (elf_fpu_type != Val_GNU_MIPS_ABI_FP_ANY) 8196 { 8197 switch (elf_fpu_type) 8198 { 8199 case Val_GNU_MIPS_ABI_FP_DOUBLE: 8200 fpu_type = MIPS_FPU_DOUBLE; 8201 break; 8202 case Val_GNU_MIPS_ABI_FP_SINGLE: 8203 fpu_type = MIPS_FPU_SINGLE; 8204 break; 8205 case Val_GNU_MIPS_ABI_FP_SOFT: 8206 default: 8207 /* Soft float or unknown. */ 8208 fpu_type = MIPS_FPU_NONE; 8209 break; 8210 } 8211 } 8212 else if (info.bfd_arch_info != NULL 8213 && info.bfd_arch_info->arch == bfd_arch_mips) 8214 switch (info.bfd_arch_info->mach) 8215 { 8216 case bfd_mach_mips3900: 8217 case bfd_mach_mips4100: 8218 case bfd_mach_mips4111: 8219 case bfd_mach_mips4120: 8220 fpu_type = MIPS_FPU_NONE; 8221 break; 8222 case bfd_mach_mips4650: 8223 fpu_type = MIPS_FPU_SINGLE; 8224 break; 8225 default: 8226 fpu_type = MIPS_FPU_DOUBLE; 8227 break; 8228 } 8229 else if (arches != NULL) 8230 fpu_type = MIPS_FPU_TYPE (arches->gdbarch); 8231 else 8232 fpu_type = MIPS_FPU_DOUBLE; 8233 if (gdbarch_debug) 8234 fprintf_unfiltered (gdb_stdlog, 8235 "mips_gdbarch_init: fpu_type = %d\n", fpu_type); 8236 8237 /* Check for blatant incompatibilities. */ 8238 8239 /* If we have only 32-bit registers, then we can't debug a 64-bit 8240 ABI. */ 8241 if (info.target_desc 8242 && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL 8243 && mips_abi != MIPS_ABI_EABI32 8244 && mips_abi != MIPS_ABI_O32) 8245 return NULL; 8246 8247 /* Fill in the OS dependent register numbers and names. */ 8248 if (info.osabi == GDB_OSABI_LINUX) 8249 { 8250 mips_regnum.fp0 = 38; 8251 mips_regnum.pc = 37; 8252 mips_regnum.cause = 36; 8253 mips_regnum.badvaddr = 35; 8254 mips_regnum.hi = 34; 8255 mips_regnum.lo = 33; 8256 mips_regnum.fp_control_status = 70; 8257 mips_regnum.fp_implementation_revision = 71; 8258 mips_regnum.dspacc = -1; 8259 mips_regnum.dspctl = -1; 8260 dspacc = 72; 8261 dspctl = 78; 8262 num_regs = 90; 8263 reg_names = mips_linux_reg_names; 8264 } 8265 else 8266 { 8267 mips_regnum.lo = MIPS_EMBED_LO_REGNUM; 8268 mips_regnum.hi = MIPS_EMBED_HI_REGNUM; 8269 mips_regnum.badvaddr = MIPS_EMBED_BADVADDR_REGNUM; 8270 mips_regnum.cause = MIPS_EMBED_CAUSE_REGNUM; 8271 mips_regnum.pc = MIPS_EMBED_PC_REGNUM; 8272 mips_regnum.fp0 = MIPS_EMBED_FP0_REGNUM; 8273 mips_regnum.fp_control_status = 70; 8274 mips_regnum.fp_implementation_revision = 71; 8275 mips_regnum.dspacc = dspacc = -1; 8276 mips_regnum.dspctl = dspctl = -1; 8277 num_regs = MIPS_LAST_EMBED_REGNUM + 1; 8278 if (info.bfd_arch_info != NULL 8279 && info.bfd_arch_info->mach == bfd_mach_mips3900) 8280 reg_names = mips_tx39_reg_names; 8281 else 8282 reg_names = mips_generic_reg_names; 8283 } 8284 8285 /* Check any target description for validity. */ 8286 if (tdesc_has_registers (info.target_desc)) 8287 { 8288 static const char *const mips_gprs[] = { 8289 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8290 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8291 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8292 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 8293 }; 8294 static const char *const mips_fprs[] = { 8295 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 8296 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 8297 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 8298 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 8299 }; 8300 8301 const struct tdesc_feature *feature; 8302 int valid_p; 8303 8304 feature = tdesc_find_feature (info.target_desc, 8305 "org.gnu.gdb.mips.cpu"); 8306 if (feature == NULL) 8307 return NULL; 8308 8309 tdesc_data = tdesc_data_alloc (); 8310 8311 valid_p = 1; 8312 for (i = MIPS_ZERO_REGNUM; i <= MIPS_RA_REGNUM; i++) 8313 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, 8314 mips_gprs[i]); 8315 8316 8317 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8318 mips_regnum.lo, "lo"); 8319 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8320 mips_regnum.hi, "hi"); 8321 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8322 mips_regnum.pc, "pc"); 8323 8324 if (!valid_p) 8325 { 8326 tdesc_data_cleanup (tdesc_data); 8327 return NULL; 8328 } 8329 8330 feature = tdesc_find_feature (info.target_desc, 8331 "org.gnu.gdb.mips.cp0"); 8332 if (feature == NULL) 8333 { 8334 tdesc_data_cleanup (tdesc_data); 8335 return NULL; 8336 } 8337 8338 valid_p = 1; 8339 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8340 mips_regnum.badvaddr, "badvaddr"); 8341 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8342 MIPS_PS_REGNUM, "status"); 8343 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8344 mips_regnum.cause, "cause"); 8345 8346 if (!valid_p) 8347 { 8348 tdesc_data_cleanup (tdesc_data); 8349 return NULL; 8350 } 8351 8352 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS 8353 backend is not prepared for that, though. */ 8354 feature = tdesc_find_feature (info.target_desc, 8355 "org.gnu.gdb.mips.fpu"); 8356 if (feature == NULL) 8357 { 8358 tdesc_data_cleanup (tdesc_data); 8359 return NULL; 8360 } 8361 8362 valid_p = 1; 8363 for (i = 0; i < 32; i++) 8364 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8365 i + mips_regnum.fp0, mips_fprs[i]); 8366 8367 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8368 mips_regnum.fp_control_status, 8369 "fcsr"); 8370 valid_p 8371 &= tdesc_numbered_register (feature, tdesc_data, 8372 mips_regnum.fp_implementation_revision, 8373 "fir"); 8374 8375 if (!valid_p) 8376 { 8377 tdesc_data_cleanup (tdesc_data); 8378 return NULL; 8379 } 8380 8381 num_regs = mips_regnum.fp_implementation_revision + 1; 8382 8383 if (dspacc >= 0) 8384 { 8385 feature = tdesc_find_feature (info.target_desc, 8386 "org.gnu.gdb.mips.dsp"); 8387 /* The DSP registers are optional; it's OK if they are absent. */ 8388 if (feature != NULL) 8389 { 8390 i = 0; 8391 valid_p = 1; 8392 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8393 dspacc + i++, "hi1"); 8394 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8395 dspacc + i++, "lo1"); 8396 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8397 dspacc + i++, "hi2"); 8398 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8399 dspacc + i++, "lo2"); 8400 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8401 dspacc + i++, "hi3"); 8402 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8403 dspacc + i++, "lo3"); 8404 8405 valid_p &= tdesc_numbered_register (feature, tdesc_data, 8406 dspctl, "dspctl"); 8407 8408 if (!valid_p) 8409 { 8410 tdesc_data_cleanup (tdesc_data); 8411 return NULL; 8412 } 8413 8414 mips_regnum.dspacc = dspacc; 8415 mips_regnum.dspctl = dspctl; 8416 8417 num_regs = mips_regnum.dspctl + 1; 8418 } 8419 } 8420 8421 /* It would be nice to detect an attempt to use a 64-bit ABI 8422 when only 32-bit registers are provided. */ 8423 reg_names = NULL; 8424 } 8425 8426 /* Try to find a pre-existing architecture. */ 8427 for (arches = gdbarch_list_lookup_by_info (arches, &info); 8428 arches != NULL; 8429 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 8430 { 8431 /* MIPS needs to be pedantic about which ABI and the compressed 8432 ISA variation the object is using. */ 8433 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags) 8434 continue; 8435 if (gdbarch_tdep (arches->gdbarch)->mips_abi != mips_abi) 8436 continue; 8437 if (gdbarch_tdep (arches->gdbarch)->mips_isa != mips_isa) 8438 continue; 8439 /* Need to be pedantic about which register virtual size is 8440 used. */ 8441 if (gdbarch_tdep (arches->gdbarch)->mips64_transfers_32bit_regs_p 8442 != mips64_transfers_32bit_regs_p) 8443 continue; 8444 /* Be pedantic about which FPU is selected. */ 8445 if (MIPS_FPU_TYPE (arches->gdbarch) != fpu_type) 8446 continue; 8447 8448 if (tdesc_data != NULL) 8449 tdesc_data_cleanup (tdesc_data); 8450 return arches->gdbarch; 8451 } 8452 8453 /* Need a new architecture. Fill in a target specific vector. */ 8454 tdep = XCNEW (struct gdbarch_tdep); 8455 gdbarch = gdbarch_alloc (&info, tdep); 8456 tdep->elf_flags = elf_flags; 8457 tdep->mips64_transfers_32bit_regs_p = mips64_transfers_32bit_regs_p; 8458 tdep->found_abi = found_abi; 8459 tdep->mips_abi = mips_abi; 8460 tdep->mips_isa = mips_isa; 8461 tdep->mips_fpu_type = fpu_type; 8462 tdep->register_size_valid_p = 0; 8463 tdep->register_size = 0; 8464 8465 if (info.target_desc) 8466 { 8467 /* Some useful properties can be inferred from the target. */ 8468 if (tdesc_property (info.target_desc, PROPERTY_GP32) != NULL) 8469 { 8470 tdep->register_size_valid_p = 1; 8471 tdep->register_size = 4; 8472 } 8473 else if (tdesc_property (info.target_desc, PROPERTY_GP64) != NULL) 8474 { 8475 tdep->register_size_valid_p = 1; 8476 tdep->register_size = 8; 8477 } 8478 } 8479 8480 /* Initially set everything according to the default ABI/ISA. */ 8481 set_gdbarch_short_bit (gdbarch, 16); 8482 set_gdbarch_int_bit (gdbarch, 32); 8483 set_gdbarch_float_bit (gdbarch, 32); 8484 set_gdbarch_double_bit (gdbarch, 64); 8485 set_gdbarch_long_double_bit (gdbarch, 64); 8486 set_gdbarch_register_reggroup_p (gdbarch, mips_register_reggroup_p); 8487 set_gdbarch_pseudo_register_read (gdbarch, mips_pseudo_register_read); 8488 set_gdbarch_pseudo_register_write (gdbarch, mips_pseudo_register_write); 8489 8490 set_gdbarch_ax_pseudo_register_collect (gdbarch, 8491 mips_ax_pseudo_register_collect); 8492 set_gdbarch_ax_pseudo_register_push_stack 8493 (gdbarch, mips_ax_pseudo_register_push_stack); 8494 8495 set_gdbarch_elf_make_msymbol_special (gdbarch, 8496 mips_elf_make_msymbol_special); 8497 set_gdbarch_make_symbol_special (gdbarch, mips_make_symbol_special); 8498 set_gdbarch_adjust_dwarf2_addr (gdbarch, mips_adjust_dwarf2_addr); 8499 set_gdbarch_adjust_dwarf2_line (gdbarch, mips_adjust_dwarf2_line); 8500 8501 regnum = GDBARCH_OBSTACK_ZALLOC (gdbarch, struct mips_regnum); 8502 *regnum = mips_regnum; 8503 set_gdbarch_fp0_regnum (gdbarch, regnum->fp0); 8504 set_gdbarch_num_regs (gdbarch, num_regs); 8505 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8506 set_gdbarch_register_name (gdbarch, mips_register_name); 8507 set_gdbarch_virtual_frame_pointer (gdbarch, mips_virtual_frame_pointer); 8508 tdep->mips_processor_reg_names = reg_names; 8509 tdep->regnum = regnum; 8510 8511 switch (mips_abi) 8512 { 8513 case MIPS_ABI_O32: 8514 set_gdbarch_push_dummy_call (gdbarch, mips_o32_push_dummy_call); 8515 set_gdbarch_return_value (gdbarch, mips_o32_return_value); 8516 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8517 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8518 tdep->default_mask_address_p = 0; 8519 set_gdbarch_long_bit (gdbarch, 32); 8520 set_gdbarch_ptr_bit (gdbarch, 32); 8521 set_gdbarch_long_long_bit (gdbarch, 64); 8522 break; 8523 case MIPS_ABI_O64: 8524 set_gdbarch_push_dummy_call (gdbarch, mips_o64_push_dummy_call); 8525 set_gdbarch_return_value (gdbarch, mips_o64_return_value); 8526 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 4 - 1; 8527 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 4 - 1; 8528 tdep->default_mask_address_p = 0; 8529 set_gdbarch_long_bit (gdbarch, 32); 8530 set_gdbarch_ptr_bit (gdbarch, 32); 8531 set_gdbarch_long_long_bit (gdbarch, 64); 8532 break; 8533 case MIPS_ABI_EABI32: 8534 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8535 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8536 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8537 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8538 tdep->default_mask_address_p = 0; 8539 set_gdbarch_long_bit (gdbarch, 32); 8540 set_gdbarch_ptr_bit (gdbarch, 32); 8541 set_gdbarch_long_long_bit (gdbarch, 64); 8542 break; 8543 case MIPS_ABI_EABI64: 8544 set_gdbarch_push_dummy_call (gdbarch, mips_eabi_push_dummy_call); 8545 set_gdbarch_return_value (gdbarch, mips_eabi_return_value); 8546 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8547 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8548 tdep->default_mask_address_p = 0; 8549 set_gdbarch_long_bit (gdbarch, 64); 8550 set_gdbarch_ptr_bit (gdbarch, 64); 8551 set_gdbarch_long_long_bit (gdbarch, 64); 8552 break; 8553 case MIPS_ABI_N32: 8554 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8555 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8556 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8557 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8558 tdep->default_mask_address_p = 0; 8559 set_gdbarch_long_bit (gdbarch, 32); 8560 set_gdbarch_ptr_bit (gdbarch, 32); 8561 set_gdbarch_long_long_bit (gdbarch, 64); 8562 set_gdbarch_long_double_bit (gdbarch, 128); 8563 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8564 break; 8565 case MIPS_ABI_N64: 8566 set_gdbarch_push_dummy_call (gdbarch, mips_n32n64_push_dummy_call); 8567 set_gdbarch_return_value (gdbarch, mips_n32n64_return_value); 8568 tdep->mips_last_arg_regnum = MIPS_A0_REGNUM + 8 - 1; 8569 tdep->mips_last_fp_arg_regnum = tdep->regnum->fp0 + 12 + 8 - 1; 8570 tdep->default_mask_address_p = 0; 8571 set_gdbarch_long_bit (gdbarch, 64); 8572 set_gdbarch_ptr_bit (gdbarch, 64); 8573 set_gdbarch_long_long_bit (gdbarch, 64); 8574 set_gdbarch_long_double_bit (gdbarch, 128); 8575 set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); 8576 break; 8577 default: 8578 internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); 8579 } 8580 8581 /* GCC creates a pseudo-section whose name specifies the size of 8582 longs, since -mlong32 or -mlong64 may be used independent of 8583 other options. How those options affect pointer sizes is ABI and 8584 architecture dependent, so use them to override the default sizes 8585 set by the ABI. This table shows the relationship between ABI, 8586 -mlongXX, and size of pointers: 8587 8588 ABI -mlongXX ptr bits 8589 --- -------- -------- 8590 o32 32 32 8591 o32 64 32 8592 n32 32 32 8593 n32 64 64 8594 o64 32 32 8595 o64 64 64 8596 n64 32 32 8597 n64 64 64 8598 eabi32 32 32 8599 eabi32 64 32 8600 eabi64 32 32 8601 eabi64 64 64 8602 8603 Note that for o32 and eabi32, pointers are always 32 bits 8604 regardless of any -mlongXX option. For all others, pointers and 8605 longs are the same, as set by -mlongXX or set by defaults. */ 8606 8607 if (info.abfd != NULL) 8608 { 8609 int long_bit = 0; 8610 8611 bfd_map_over_sections (info.abfd, mips_find_long_section, &long_bit); 8612 if (long_bit) 8613 { 8614 set_gdbarch_long_bit (gdbarch, long_bit); 8615 switch (mips_abi) 8616 { 8617 case MIPS_ABI_O32: 8618 case MIPS_ABI_EABI32: 8619 break; 8620 case MIPS_ABI_N32: 8621 case MIPS_ABI_O64: 8622 case MIPS_ABI_N64: 8623 case MIPS_ABI_EABI64: 8624 set_gdbarch_ptr_bit (gdbarch, long_bit); 8625 break; 8626 default: 8627 internal_error (__FILE__, __LINE__, _("unknown ABI in switch")); 8628 } 8629 } 8630 } 8631 8632 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE 8633 that could indicate -gp32 BUT gas/config/tc-mips.c contains the 8634 comment: 8635 8636 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE 8637 flag in object files because to do so would make it impossible to 8638 link with libraries compiled without "-gp32". This is 8639 unnecessarily restrictive. 8640 8641 We could solve this problem by adding "-gp32" multilibs to gcc, 8642 but to set this flag before gcc is built with such multilibs will 8643 break too many systems.'' 8644 8645 But even more unhelpfully, the default linker output target for 8646 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even 8647 for 64-bit programs - you need to change the ABI to change this, 8648 and not all gcc targets support that currently. Therefore using 8649 this flag to detect 32-bit mode would do the wrong thing given 8650 the current gcc - it would make GDB treat these 64-bit programs 8651 as 32-bit programs by default. */ 8652 8653 set_gdbarch_read_pc (gdbarch, mips_read_pc); 8654 set_gdbarch_write_pc (gdbarch, mips_write_pc); 8655 8656 /* Add/remove bits from an address. The MIPS needs be careful to 8657 ensure that all 32 bit addresses are sign extended to 64 bits. */ 8658 set_gdbarch_addr_bits_remove (gdbarch, mips_addr_bits_remove); 8659 8660 /* Unwind the frame. */ 8661 set_gdbarch_unwind_pc (gdbarch, mips_unwind_pc); 8662 set_gdbarch_unwind_sp (gdbarch, mips_unwind_sp); 8663 set_gdbarch_dummy_id (gdbarch, mips_dummy_id); 8664 8665 /* Map debug register numbers onto internal register numbers. */ 8666 set_gdbarch_stab_reg_to_regnum (gdbarch, mips_stab_reg_to_regnum); 8667 set_gdbarch_ecoff_reg_to_regnum (gdbarch, 8668 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8669 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, 8670 mips_dwarf_dwarf2_ecoff_reg_to_regnum); 8671 set_gdbarch_register_sim_regno (gdbarch, mips_register_sim_regno); 8672 8673 /* MIPS version of CALL_DUMMY. */ 8674 8675 set_gdbarch_call_dummy_location (gdbarch, ON_STACK); 8676 set_gdbarch_push_dummy_code (gdbarch, mips_push_dummy_code); 8677 set_gdbarch_frame_align (gdbarch, mips_frame_align); 8678 8679 set_gdbarch_print_float_info (gdbarch, mips_print_float_info); 8680 8681 set_gdbarch_convert_register_p (gdbarch, mips_convert_register_p); 8682 set_gdbarch_register_to_value (gdbarch, mips_register_to_value); 8683 set_gdbarch_value_to_register (gdbarch, mips_value_to_register); 8684 8685 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 8686 set_gdbarch_breakpoint_kind_from_pc (gdbarch, mips_breakpoint_kind_from_pc); 8687 set_gdbarch_sw_breakpoint_from_kind (gdbarch, mips_sw_breakpoint_from_kind); 8688 set_gdbarch_adjust_breakpoint_address (gdbarch, 8689 mips_adjust_breakpoint_address); 8690 8691 set_gdbarch_skip_prologue (gdbarch, mips_skip_prologue); 8692 8693 set_gdbarch_stack_frame_destroyed_p (gdbarch, mips_stack_frame_destroyed_p); 8694 8695 set_gdbarch_pointer_to_address (gdbarch, signed_pointer_to_address); 8696 set_gdbarch_address_to_pointer (gdbarch, address_to_signed_pointer); 8697 set_gdbarch_integer_to_address (gdbarch, mips_integer_to_address); 8698 8699 set_gdbarch_register_type (gdbarch, mips_register_type); 8700 8701 set_gdbarch_print_registers_info (gdbarch, mips_print_registers_info); 8702 8703 set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); 8704 if (mips_abi == MIPS_ABI_N64) 8705 set_gdbarch_disassembler_options_implicit 8706 (gdbarch, (const char *) mips_disassembler_options_n64); 8707 else if (mips_abi == MIPS_ABI_N32) 8708 set_gdbarch_disassembler_options_implicit 8709 (gdbarch, (const char *) mips_disassembler_options_n32); 8710 else 8711 set_gdbarch_disassembler_options_implicit 8712 (gdbarch, (const char *) mips_disassembler_options_o32); 8713 set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); 8714 set_gdbarch_valid_disassembler_options (gdbarch, 8715 disassembler_options_mips ()); 8716 8717 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint, 8718 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint 8719 need to all be folded into the target vector. Since they are 8720 being used as guards for target_stopped_by_watchpoint, why not have 8721 target_stopped_by_watchpoint return the type of watchpoint that the code 8722 is sitting on? */ 8723 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 8724 8725 set_gdbarch_skip_trampoline_code (gdbarch, mips_skip_trampoline_code); 8726 8727 /* NOTE drow/2012-04-25: We overload the core solib trampoline code 8728 to support MIPS16. This is a bad thing. Make sure not to do it 8729 if we have an OS ABI that actually supports shared libraries, since 8730 shared library support is more important. If we have an OS someday 8731 that supports both shared libraries and MIPS16, we'll have to find 8732 a better place for these. 8733 macro/2012-04-25: But that applies to return trampolines only and 8734 currently no MIPS OS ABI uses shared libraries that have them. */ 8735 set_gdbarch_in_solib_return_trampoline (gdbarch, mips_in_return_stub); 8736 8737 set_gdbarch_single_step_through_delay (gdbarch, 8738 mips_single_step_through_delay); 8739 8740 /* Virtual tables. */ 8741 set_gdbarch_vbit_in_delta (gdbarch, 1); 8742 8743 mips_register_g_packet_guesses (gdbarch); 8744 8745 /* Hook in OS ABI-specific overrides, if they have been registered. */ 8746 info.tdesc_data = tdesc_data; 8747 gdbarch_init_osabi (info, gdbarch); 8748 8749 /* The hook may have adjusted num_regs, fetch the final value and 8750 set pc_regnum and sp_regnum now that it has been fixed. */ 8751 num_regs = gdbarch_num_regs (gdbarch); 8752 set_gdbarch_pc_regnum (gdbarch, regnum->pc + num_regs); 8753 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8754 8755 /* Unwind the frame. */ 8756 dwarf2_append_unwinders (gdbarch); 8757 frame_unwind_append_unwinder (gdbarch, &mips_stub_frame_unwind); 8758 frame_unwind_append_unwinder (gdbarch, &mips_insn16_frame_unwind); 8759 frame_unwind_append_unwinder (gdbarch, &mips_micro_frame_unwind); 8760 frame_unwind_append_unwinder (gdbarch, &mips_insn32_frame_unwind); 8761 frame_base_append_sniffer (gdbarch, dwarf2_frame_base_sniffer); 8762 frame_base_append_sniffer (gdbarch, mips_stub_frame_base_sniffer); 8763 frame_base_append_sniffer (gdbarch, mips_insn16_frame_base_sniffer); 8764 frame_base_append_sniffer (gdbarch, mips_micro_frame_base_sniffer); 8765 frame_base_append_sniffer (gdbarch, mips_insn32_frame_base_sniffer); 8766 8767 if (tdesc_data) 8768 { 8769 set_tdesc_pseudo_register_type (gdbarch, mips_pseudo_register_type); 8770 tdesc_use_registers (gdbarch, info.target_desc, tdesc_data); 8771 8772 /* Override the normal target description methods to handle our 8773 dual real and pseudo registers. */ 8774 set_gdbarch_register_name (gdbarch, mips_register_name); 8775 set_gdbarch_register_reggroup_p (gdbarch, 8776 mips_tdesc_register_reggroup_p); 8777 8778 num_regs = gdbarch_num_regs (gdbarch); 8779 set_gdbarch_num_pseudo_regs (gdbarch, num_regs); 8780 set_gdbarch_pc_regnum (gdbarch, tdep->regnum->pc + num_regs); 8781 set_gdbarch_sp_regnum (gdbarch, MIPS_SP_REGNUM + num_regs); 8782 } 8783 8784 /* Add ABI-specific aliases for the registers. */ 8785 if (mips_abi == MIPS_ABI_N32 || mips_abi == MIPS_ABI_N64) 8786 for (i = 0; i < ARRAY_SIZE (mips_n32_n64_aliases); i++) 8787 user_reg_add (gdbarch, mips_n32_n64_aliases[i].name, 8788 value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); 8789 else 8790 for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) 8791 user_reg_add (gdbarch, mips_o32_aliases[i].name, 8792 value_of_mips_user_reg, &mips_o32_aliases[i].regnum); 8793 8794 /* Add some other standard aliases. */ 8795 for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) 8796 user_reg_add (gdbarch, mips_register_aliases[i].name, 8797 value_of_mips_user_reg, &mips_register_aliases[i].regnum); 8798 8799 for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) 8800 user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, 8801 value_of_mips_user_reg, 8802 &mips_numeric_register_aliases[i].regnum); 8803 8804 return gdbarch; 8805 } 8806 8807 static void 8808 mips_abi_update (const char *ignore_args, 8809 int from_tty, struct cmd_list_element *c) 8810 { 8811 struct gdbarch_info info; 8812 8813 /* Force the architecture to update, and (if it's a MIPS architecture) 8814 mips_gdbarch_init will take care of the rest. */ 8815 gdbarch_info_init (&info); 8816 gdbarch_update_p (info); 8817 } 8818 8819 /* Print out which MIPS ABI is in use. */ 8820 8821 static void 8822 show_mips_abi (struct ui_file *file, 8823 int from_tty, 8824 struct cmd_list_element *ignored_cmd, 8825 const char *ignored_value) 8826 { 8827 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) 8828 fprintf_filtered 8829 (file, 8830 "The MIPS ABI is unknown because the current architecture " 8831 "is not MIPS.\n"); 8832 else 8833 { 8834 enum mips_abi global_abi = global_mips_abi (); 8835 enum mips_abi actual_abi = mips_abi (target_gdbarch ()); 8836 const char *actual_abi_str = mips_abi_strings[actual_abi]; 8837 8838 if (global_abi == MIPS_ABI_UNKNOWN) 8839 fprintf_filtered 8840 (file, 8841 "The MIPS ABI is set automatically (currently \"%s\").\n", 8842 actual_abi_str); 8843 else if (global_abi == actual_abi) 8844 fprintf_filtered 8845 (file, 8846 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", 8847 actual_abi_str); 8848 else 8849 { 8850 /* Probably shouldn't happen... */ 8851 fprintf_filtered (file, 8852 "The (auto detected) MIPS ABI \"%s\" is in use " 8853 "even though the user setting was \"%s\".\n", 8854 actual_abi_str, mips_abi_strings[global_abi]); 8855 } 8856 } 8857 } 8858 8859 /* Print out which MIPS compressed ISA encoding is used. */ 8860 8861 static void 8862 show_mips_compression (struct ui_file *file, int from_tty, 8863 struct cmd_list_element *c, const char *value) 8864 { 8865 fprintf_filtered (file, _("The compressed ISA encoding used is %s.\n"), 8866 value); 8867 } 8868 8869 /* Return a textual name for MIPS FPU type FPU_TYPE. */ 8870 8871 static const char * 8872 mips_fpu_type_str (enum mips_fpu_type fpu_type) 8873 { 8874 switch (fpu_type) 8875 { 8876 case MIPS_FPU_NONE: 8877 return "none"; 8878 case MIPS_FPU_SINGLE: 8879 return "single"; 8880 case MIPS_FPU_DOUBLE: 8881 return "double"; 8882 default: 8883 return "???"; 8884 } 8885 } 8886 8887 static void 8888 mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) 8889 { 8890 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 8891 if (tdep != NULL) 8892 { 8893 int ef_mips_arch; 8894 int ef_mips_32bitmode; 8895 /* Determine the ISA. */ 8896 switch (tdep->elf_flags & EF_MIPS_ARCH) 8897 { 8898 case E_MIPS_ARCH_1: 8899 ef_mips_arch = 1; 8900 break; 8901 case E_MIPS_ARCH_2: 8902 ef_mips_arch = 2; 8903 break; 8904 case E_MIPS_ARCH_3: 8905 ef_mips_arch = 3; 8906 break; 8907 case E_MIPS_ARCH_4: 8908 ef_mips_arch = 4; 8909 break; 8910 default: 8911 ef_mips_arch = 0; 8912 break; 8913 } 8914 /* Determine the size of a pointer. */ 8915 ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); 8916 fprintf_unfiltered (file, 8917 "mips_dump_tdep: tdep->elf_flags = 0x%x\n", 8918 tdep->elf_flags); 8919 fprintf_unfiltered (file, 8920 "mips_dump_tdep: ef_mips_32bitmode = %d\n", 8921 ef_mips_32bitmode); 8922 fprintf_unfiltered (file, 8923 "mips_dump_tdep: ef_mips_arch = %d\n", 8924 ef_mips_arch); 8925 fprintf_unfiltered (file, 8926 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", 8927 tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); 8928 fprintf_unfiltered (file, 8929 "mips_dump_tdep: " 8930 "mips_mask_address_p() %d (default %d)\n", 8931 mips_mask_address_p (tdep), 8932 tdep->default_mask_address_p); 8933 } 8934 fprintf_unfiltered (file, 8935 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", 8936 MIPS_DEFAULT_FPU_TYPE, 8937 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); 8938 fprintf_unfiltered (file, "mips_dump_tdep: MIPS_EABI = %d\n", 8939 MIPS_EABI (gdbarch)); 8940 fprintf_unfiltered (file, 8941 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", 8942 MIPS_FPU_TYPE (gdbarch), 8943 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch))); 8944 } 8945 8946 void _initialize_mips_tdep (); 8947 void 8948 _initialize_mips_tdep () 8949 { 8950 static struct cmd_list_element *mipsfpulist = NULL; 8951 8952 mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; 8953 if (MIPS_ABI_LAST + 1 8954 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) 8955 internal_error (__FILE__, __LINE__, _("mips_abi_strings out of sync")); 8956 8957 gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); 8958 8959 /* Create feature sets with the appropriate properties. The values 8960 are not important. */ 8961 mips_tdesc_gp32 = allocate_target_description (); 8962 set_tdesc_property (mips_tdesc_gp32, PROPERTY_GP32, ""); 8963 8964 mips_tdesc_gp64 = allocate_target_description (); 8965 set_tdesc_property (mips_tdesc_gp64, PROPERTY_GP64, ""); 8966 8967 /* Add root prefix command for all "set mips"/"show mips" commands. */ 8968 add_basic_prefix_cmd ("mips", no_class, 8969 _("Various MIPS specific commands."), 8970 &setmipscmdlist, "set mips ", 0, &setlist); 8971 8972 add_show_prefix_cmd ("mips", no_class, 8973 _("Various MIPS specific commands."), 8974 &showmipscmdlist, "show mips ", 0, &showlist); 8975 8976 /* Allow the user to override the ABI. */ 8977 add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, 8978 &mips_abi_string, _("\ 8979 Set the MIPS ABI used by this program."), _("\ 8980 Show the MIPS ABI used by this program."), _("\ 8981 This option can be set to one of:\n\ 8982 auto - the default ABI associated with the current binary\n\ 8983 o32\n\ 8984 o64\n\ 8985 n32\n\ 8986 n64\n\ 8987 eabi32\n\ 8988 eabi64"), 8989 mips_abi_update, 8990 show_mips_abi, 8991 &setmipscmdlist, &showmipscmdlist); 8992 8993 /* Allow the user to set the ISA to assume for compressed code if ELF 8994 file flags don't tell or there is no program file selected. This 8995 setting is updated whenever unambiguous ELF file flags are interpreted, 8996 and carried over to subsequent sessions. */ 8997 add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, 8998 &mips_compression_string, _("\ 8999 Set the compressed ISA encoding used by MIPS code."), _("\ 9000 Show the compressed ISA encoding used by MIPS code."), _("\ 9001 Select the compressed ISA encoding used in functions that have no symbol\n\ 9002 information available. The encoding can be set to either of:\n\ 9003 mips16\n\ 9004 micromips\n\ 9005 and is updated automatically from ELF file flags if available."), 9006 mips_abi_update, 9007 show_mips_compression, 9008 &setmipscmdlist, &showmipscmdlist); 9009 9010 /* Let the user turn off floating point and set the fence post for 9011 heuristic_proc_start. */ 9012 9013 add_basic_prefix_cmd ("mipsfpu", class_support, 9014 _("Set use of MIPS floating-point coprocessor."), 9015 &mipsfpulist, "set mipsfpu ", 0, &setlist); 9016 add_cmd ("single", class_support, set_mipsfpu_single_command, 9017 _("Select single-precision MIPS floating-point coprocessor."), 9018 &mipsfpulist); 9019 add_cmd ("double", class_support, set_mipsfpu_double_command, 9020 _("Select double-precision MIPS floating-point coprocessor."), 9021 &mipsfpulist); 9022 add_alias_cmd ("on", "double", class_support, 1, &mipsfpulist); 9023 add_alias_cmd ("yes", "double", class_support, 1, &mipsfpulist); 9024 add_alias_cmd ("1", "double", class_support, 1, &mipsfpulist); 9025 add_cmd ("none", class_support, set_mipsfpu_none_command, 9026 _("Select no MIPS floating-point coprocessor."), &mipsfpulist); 9027 add_alias_cmd ("off", "none", class_support, 1, &mipsfpulist); 9028 add_alias_cmd ("no", "none", class_support, 1, &mipsfpulist); 9029 add_alias_cmd ("0", "none", class_support, 1, &mipsfpulist); 9030 add_cmd ("auto", class_support, set_mipsfpu_auto_command, 9031 _("Select MIPS floating-point coprocessor automatically."), 9032 &mipsfpulist); 9033 add_cmd ("mipsfpu", class_support, show_mipsfpu_command, 9034 _("Show current use of MIPS floating-point coprocessor target."), 9035 &showlist); 9036 9037 /* We really would like to have both "0" and "unlimited" work, but 9038 command.c doesn't deal with that. So make it a var_zinteger 9039 because the user can always use "999999" or some such for unlimited. */ 9040 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, 9041 &heuristic_fence_post, _("\ 9042 Set the distance searched for the start of a function."), _("\ 9043 Show the distance searched for the start of a function."), _("\ 9044 If you are debugging a stripped executable, GDB needs to search through the\n\ 9045 program for the start of a function. This command sets the distance of the\n\ 9046 search. The only need to set it is when debugging a stripped executable."), 9047 reinit_frame_cache_sfunc, 9048 NULL, /* FIXME: i18n: The distance searched for 9049 the start of a function is %s. */ 9050 &setlist, &showlist); 9051 9052 /* Allow the user to control whether the upper bits of 64-bit 9053 addresses should be zeroed. */ 9054 add_setshow_auto_boolean_cmd ("mask-address", no_class, 9055 &mask_address_var, _("\ 9056 Set zeroing of upper 32 bits of 64-bit addresses."), _("\ 9057 Show zeroing of upper 32 bits of 64-bit addresses."), _("\ 9058 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ 9059 allow GDB to determine the correct value."), 9060 NULL, show_mask_address, 9061 &setmipscmdlist, &showmipscmdlist); 9062 9063 /* Allow the user to control the size of 32 bit registers within the 9064 raw remote packet. */ 9065 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, 9066 &mips64_transfers_32bit_regs_p, _("\ 9067 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9068 _("\ 9069 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), 9070 _("\ 9071 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ 9072 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 9073 64 bits for others. Use \"off\" to disable compatibility mode"), 9074 set_mips64_transfers_32bit_regs, 9075 NULL, /* FIXME: i18n: Compatibility with 64-bit 9076 MIPS target that transfers 32-bit 9077 quantities is %s. */ 9078 &setlist, &showlist); 9079 9080 /* Debug this files internals. */ 9081 add_setshow_zuinteger_cmd ("mips", class_maintenance, 9082 &mips_debug, _("\ 9083 Set mips debugging."), _("\ 9084 Show mips debugging."), _("\ 9085 When non-zero, mips specific debugging is enabled."), 9086 NULL, 9087 NULL, /* FIXME: i18n: Mips debugging is 9088 currently %s. */ 9089 &setdebuglist, &showdebuglist); 9090 } 9091