1 /* Target-dependent code for the Toshiba MeP for GDB, the GNU debugger. 2 3 Copyright (C) 2001-2017 Free Software Foundation, Inc. 4 5 Contributed by Red Hat, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22 #include "defs.h" 23 #include "frame.h" 24 #include "frame-unwind.h" 25 #include "frame-base.h" 26 #include "symtab.h" 27 #include "gdbtypes.h" 28 #include "gdbcmd.h" 29 #include "gdbcore.h" 30 #include "value.h" 31 #include "inferior.h" 32 #include "dis-asm.h" 33 #include "symfile.h" 34 #include "objfiles.h" 35 #include "language.h" 36 #include "arch-utils.h" 37 #include "regcache.h" 38 #include "remote.h" 39 #include "floatformat.h" 40 #include "sim-regno.h" 41 #include "disasm.h" 42 #include "trad-frame.h" 43 #include "reggroups.h" 44 #include "elf-bfd.h" 45 #include "elf/mep.h" 46 #include "prologue-value.h" 47 #include "cgen/bitset.h" 48 #include "infcall.h" 49 50 /* Get the user's customized MeP coprocessor register names from 51 libopcodes. */ 52 #include "opcodes/mep-desc.h" 53 #include "opcodes/mep-opc.h" 54 55 56 /* The gdbarch_tdep structure. */ 57 58 /* A quick recap for GDB hackers not familiar with the whole Toshiba 59 Media Processor story: 60 61 The MeP media engine is a configureable processor: users can design 62 their own coprocessors, implement custom instructions, adjust cache 63 sizes, select optional standard facilities like add-and-saturate 64 instructions, and so on. Then, they can build custom versions of 65 the GNU toolchain to support their customized chips. The 66 MeP-Integrator program (see utils/mep) takes a GNU toolchain source 67 tree, and a config file pointing to various files provided by the 68 user describing their customizations, and edits the source tree to 69 produce a compiler that can generate their custom instructions, an 70 assembler that can assemble them and recognize their custom 71 register names, and so on. 72 73 Furthermore, the user can actually specify several of these custom 74 configurations, called 'me_modules', and get a toolchain which can 75 produce code for any of them, given a compiler/assembler switch; 76 you say something like 'gcc -mconfig=mm_max' to generate code for 77 the me_module named 'mm_max'. 78 79 GDB, in particular, needs to: 80 81 - use the coprocessor control register names provided by the user 82 in their hardware description, in expressions, 'info register' 83 output, and disassembly, 84 85 - know the number, names, and types of the coprocessor's 86 general-purpose registers, adjust the 'info all-registers' output 87 accordingly, and print error messages if the user refers to one 88 that doesn't exist 89 90 - allow access to the control bus space only when the configuration 91 actually has a control bus, and recognize which regions of the 92 control bus space are actually populated, 93 94 - disassemble using the user's provided mnemonics for their custom 95 instructions, and 96 97 - recognize whether the $hi and $lo registers are present, and 98 allow access to them only when they are actually there. 99 100 There are three sources of information about what sort of me_module 101 we're actually dealing with: 102 103 - A MeP executable file indicates which me_module it was compiled 104 for, and libopcodes has tables describing each module. So, given 105 an executable file, we can find out about the processor it was 106 compiled for. 107 108 - There are SID command-line options to select a particular 109 me_module, overriding the one specified in the ELF file. SID 110 provides GDB with a fake read-only register, 'module', which 111 indicates which me_module GDB is communicating with an instance 112 of. 113 114 - There are SID command-line options to enable or disable certain 115 optional processor features, overriding the defaults for the 116 selected me_module. The MeP $OPT register indicates which 117 options are present on the current processor. */ 118 119 120 struct gdbarch_tdep 121 { 122 /* A CGEN cpu descriptor for this BFD architecture and machine. 123 124 Note: this is *not* customized for any particular me_module; the 125 MeP libopcodes machinery actually puts off module-specific 126 customization until the last minute. So this contains 127 information about all supported me_modules. */ 128 CGEN_CPU_DESC cpu_desc; 129 130 /* The me_module index from the ELF file we used to select this 131 architecture, or CONFIG_NONE if there was none. 132 133 Note that we should prefer to use the me_module number available 134 via the 'module' register, whenever we're actually talking to a 135 real target. 136 137 In the absence of live information, we'd like to get the 138 me_module number from the ELF file. But which ELF file: the 139 executable file, the core file, ... ? The answer is, "the last 140 ELF file we used to set the current architecture". Thus, we 141 create a separate instance of the gdbarch structure for each 142 me_module value mep_gdbarch_init sees, and store the me_module 143 value from the ELF file here. */ 144 CONFIG_ATTR me_module; 145 }; 146 147 148 149 /* Getting me_module information from the CGEN tables. */ 150 151 152 /* Find an entry in the DESC's hardware table whose name begins with 153 PREFIX, and whose ISA mask intersects COPRO_ISA_MASK, but does not 154 intersect with GENERIC_ISA_MASK. If there is no matching entry, 155 return zero. */ 156 static const CGEN_HW_ENTRY * 157 find_hw_entry_by_prefix_and_isa (CGEN_CPU_DESC desc, 158 const char *prefix, 159 CGEN_BITSET *copro_isa_mask, 160 CGEN_BITSET *generic_isa_mask) 161 { 162 int prefix_len = strlen (prefix); 163 int i; 164 165 for (i = 0; i < desc->hw_table.num_entries; i++) 166 { 167 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; 168 if (strncmp (prefix, hw->name, prefix_len) == 0) 169 { 170 CGEN_BITSET *hw_isa_mask 171 = ((CGEN_BITSET *) 172 &CGEN_ATTR_CGEN_HW_ISA_VALUE (CGEN_HW_ATTRS (hw))); 173 174 if (cgen_bitset_intersect_p (hw_isa_mask, copro_isa_mask) 175 && ! cgen_bitset_intersect_p (hw_isa_mask, generic_isa_mask)) 176 return hw; 177 } 178 } 179 180 return 0; 181 } 182 183 184 /* Find an entry in DESC's hardware table whose type is TYPE. Return 185 zero if there is none. */ 186 static const CGEN_HW_ENTRY * 187 find_hw_entry_by_type (CGEN_CPU_DESC desc, CGEN_HW_TYPE type) 188 { 189 int i; 190 191 for (i = 0; i < desc->hw_table.num_entries; i++) 192 { 193 const CGEN_HW_ENTRY *hw = desc->hw_table.entries[i]; 194 195 if (hw->type == type) 196 return hw; 197 } 198 199 return 0; 200 } 201 202 203 /* Return the CGEN hardware table entry for the coprocessor register 204 set for ME_MODULE, whose name prefix is PREFIX. If ME_MODULE has 205 no such register set, return zero. If ME_MODULE is the generic 206 me_module CONFIG_NONE, return the table entry for the register set 207 whose hardware type is GENERIC_TYPE. */ 208 static const CGEN_HW_ENTRY * 209 me_module_register_set (CONFIG_ATTR me_module, 210 const char *prefix, 211 CGEN_HW_TYPE generic_type) 212 { 213 /* This is kind of tricky, because the hardware table is constructed 214 in a way that isn't very helpful. Perhaps we can fix that, but 215 here's how it works at the moment: 216 217 The configuration map, `mep_config_map', is indexed by me_module 218 number, and indicates which coprocessor and core ISAs that 219 me_module supports. The 'core_isa' mask includes all the core 220 ISAs, and the 'cop_isa' mask includes all the coprocessor ISAs. 221 The entry for the generic me_module, CONFIG_NONE, has an empty 222 'cop_isa', and its 'core_isa' selects only the standard MeP 223 instruction set. 224 225 The CGEN CPU descriptor's hardware table, desc->hw_table, has 226 entries for all the register sets, for all me_modules. Each 227 entry has a mask indicating which ISAs use that register set. 228 So, if an me_module supports some coprocessor ISA, we can find 229 applicable register sets by scanning the hardware table for 230 register sets whose masks include (at least some of) those ISAs. 231 232 Each hardware table entry also has a name, whose prefix says 233 whether it's a general-purpose ("h-cr") or control ("h-ccr") 234 coprocessor register set. It might be nicer to have an attribute 235 indicating what sort of register set it was, that we could use 236 instead of pattern-matching on the name. 237 238 When there is no hardware table entry whose mask includes a 239 particular coprocessor ISA and whose name starts with a given 240 prefix, then that means that that coprocessor doesn't have any 241 registers of that type. In such cases, this function must return 242 a null pointer. 243 244 Coprocessor register sets' masks may or may not include the core 245 ISA for the me_module they belong to. Those generated by a2cgen 246 do, but the sample me_module included in the unconfigured tree, 247 'ccfx', does not. 248 249 There are generic coprocessor register sets, intended only for 250 use with the generic me_module. Unfortunately, their masks 251 include *all* ISAs --- even those for coprocessors that don't 252 have such register sets. This makes detecting the case where a 253 coprocessor lacks a particular register set more complicated. 254 255 So, here's the approach we take: 256 257 - For CONFIG_NONE, we return the generic coprocessor register set. 258 259 - For any other me_module, we search for a register set whose 260 mask contains any of the me_module's coprocessor ISAs, 261 specifically excluding the generic coprocessor register sets. */ 262 263 CGEN_CPU_DESC desc = gdbarch_tdep (target_gdbarch ())->cpu_desc; 264 const CGEN_HW_ENTRY *hw; 265 266 if (me_module == CONFIG_NONE) 267 hw = find_hw_entry_by_type (desc, generic_type); 268 else 269 { 270 CGEN_BITSET *cop = &mep_config_map[me_module].cop_isa; 271 CGEN_BITSET *core = &mep_config_map[me_module].core_isa; 272 CGEN_BITSET *generic = &mep_config_map[CONFIG_NONE].core_isa; 273 CGEN_BITSET *cop_and_core; 274 275 /* The coprocessor ISAs include the ISA for the specific core which 276 has that coprocessor. */ 277 cop_and_core = cgen_bitset_copy (cop); 278 cgen_bitset_union (cop, core, cop_and_core); 279 hw = find_hw_entry_by_prefix_and_isa (desc, prefix, cop_and_core, generic); 280 } 281 282 return hw; 283 } 284 285 286 /* Given a hardware table entry HW representing a register set, return 287 a pointer to the keyword table with all the register names. If HW 288 is NULL, return NULL, to propage the "no such register set" info 289 along. */ 290 static CGEN_KEYWORD * 291 register_set_keyword_table (const CGEN_HW_ENTRY *hw) 292 { 293 if (! hw) 294 return NULL; 295 296 /* Check that HW is actually a keyword table. */ 297 gdb_assert (hw->asm_type == CGEN_ASM_KEYWORD); 298 299 /* The 'asm_data' field of a register set's hardware table entry 300 refers to a keyword table. */ 301 return (CGEN_KEYWORD *) hw->asm_data; 302 } 303 304 305 /* Given a keyword table KEYWORD and a register number REGNUM, return 306 the name of the register, or "" if KEYWORD contains no register 307 whose number is REGNUM. */ 308 static const char * 309 register_name_from_keyword (CGEN_KEYWORD *keyword_table, int regnum) 310 { 311 const CGEN_KEYWORD_ENTRY *entry 312 = cgen_keyword_lookup_value (keyword_table, regnum); 313 314 if (entry) 315 { 316 char *name = entry->name; 317 318 /* The CGEN keyword entries for register names include the 319 leading $, which appears in MeP assembly as well as in GDB. 320 But we don't want to return that; GDB core code adds that 321 itself. */ 322 if (name[0] == '$') 323 name++; 324 325 return name; 326 } 327 else 328 return ""; 329 } 330 331 332 /* Masks for option bits in the OPT special-purpose register. */ 333 enum { 334 MEP_OPT_DIV = 1 << 25, /* 32-bit divide instruction option */ 335 MEP_OPT_MUL = 1 << 24, /* 32-bit multiply instruction option */ 336 MEP_OPT_BIT = 1 << 23, /* bit manipulation instruction option */ 337 MEP_OPT_SAT = 1 << 22, /* saturation instruction option */ 338 MEP_OPT_CLP = 1 << 21, /* clip instruction option */ 339 MEP_OPT_MIN = 1 << 20, /* min/max instruction option */ 340 MEP_OPT_AVE = 1 << 19, /* average instruction option */ 341 MEP_OPT_ABS = 1 << 18, /* absolute difference instruction option */ 342 MEP_OPT_LDZ = 1 << 16, /* leading zero instruction option */ 343 MEP_OPT_VL64 = 1 << 6, /* 64-bit VLIW operation mode option */ 344 MEP_OPT_VL32 = 1 << 5, /* 32-bit VLIW operation mode option */ 345 MEP_OPT_COP = 1 << 4, /* coprocessor option */ 346 MEP_OPT_DSP = 1 << 2, /* DSP option */ 347 MEP_OPT_UCI = 1 << 1, /* UCI option */ 348 MEP_OPT_DBG = 1 << 0, /* DBG function option */ 349 }; 350 351 352 /* Given the option_mask value for a particular entry in 353 mep_config_map, produce the value the processor's OPT register 354 would use to represent the same set of options. */ 355 static unsigned int 356 opt_from_option_mask (unsigned int option_mask) 357 { 358 /* A table mapping OPT register bits onto CGEN config map option 359 bits. */ 360 struct { 361 unsigned int opt_bit, option_mask_bit; 362 } bits[] = { 363 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, 364 { MEP_OPT_MUL, 1 << CGEN_INSN_OPTIONAL_MUL_INSN }, 365 { MEP_OPT_DIV, 1 << CGEN_INSN_OPTIONAL_DIV_INSN }, 366 { MEP_OPT_DBG, 1 << CGEN_INSN_OPTIONAL_DEBUG_INSN }, 367 { MEP_OPT_LDZ, 1 << CGEN_INSN_OPTIONAL_LDZ_INSN }, 368 { MEP_OPT_ABS, 1 << CGEN_INSN_OPTIONAL_ABS_INSN }, 369 { MEP_OPT_AVE, 1 << CGEN_INSN_OPTIONAL_AVE_INSN }, 370 { MEP_OPT_MIN, 1 << CGEN_INSN_OPTIONAL_MINMAX_INSN }, 371 { MEP_OPT_CLP, 1 << CGEN_INSN_OPTIONAL_CLIP_INSN }, 372 { MEP_OPT_SAT, 1 << CGEN_INSN_OPTIONAL_SAT_INSN }, 373 { MEP_OPT_UCI, 1 << CGEN_INSN_OPTIONAL_UCI_INSN }, 374 { MEP_OPT_DSP, 1 << CGEN_INSN_OPTIONAL_DSP_INSN }, 375 { MEP_OPT_COP, 1 << CGEN_INSN_OPTIONAL_CP_INSN }, 376 }; 377 378 int i; 379 unsigned int opt = 0; 380 381 for (i = 0; i < (sizeof (bits) / sizeof (bits[0])); i++) 382 if (option_mask & bits[i].option_mask_bit) 383 opt |= bits[i].opt_bit; 384 385 return opt; 386 } 387 388 389 /* Return the value the $OPT register would use to represent the set 390 of options for ME_MODULE. */ 391 static unsigned int 392 me_module_opt (CONFIG_ATTR me_module) 393 { 394 return opt_from_option_mask (mep_config_map[me_module].option_mask); 395 } 396 397 398 /* Return the width of ME_MODULE's coprocessor data bus, in bits. 399 This is either 32 or 64. */ 400 static int 401 me_module_cop_data_bus_width (CONFIG_ATTR me_module) 402 { 403 if (mep_config_map[me_module].option_mask 404 & (1 << CGEN_INSN_OPTIONAL_CP64_INSN)) 405 return 64; 406 else 407 return 32; 408 } 409 410 411 /* Return true if ME_MODULE is big-endian, false otherwise. */ 412 static int 413 me_module_big_endian (CONFIG_ATTR me_module) 414 { 415 return mep_config_map[me_module].big_endian; 416 } 417 418 419 /* Return the name of ME_MODULE, or NULL if it has no name. */ 420 static const char * 421 me_module_name (CONFIG_ATTR me_module) 422 { 423 /* The default me_module has "" as its name, but it's easier for our 424 callers to test for NULL. */ 425 if (! mep_config_map[me_module].name 426 || mep_config_map[me_module].name[0] == '\0') 427 return NULL; 428 else 429 return mep_config_map[me_module].name; 430 } 431 432 /* Register set. */ 433 434 435 /* The MeP spec defines the following registers: 436 16 general purpose registers (r0-r15) 437 32 control/special registers (csr0-csr31) 438 32 coprocessor general-purpose registers (c0 -- c31) 439 64 coprocessor control registers (ccr0 -- ccr63) 440 441 For the raw registers, we assign numbers here explicitly, instead 442 of letting the enum assign them for us; the numbers are a matter of 443 external protocol, and shouldn't shift around as things are edited. 444 445 We access the control/special registers via pseudoregisters, to 446 enforce read-only portions that some registers have. 447 448 We access the coprocessor general purpose and control registers via 449 pseudoregisters, to make sure they appear in the proper order in 450 the 'info all-registers' command (which uses the register number 451 ordering), and also to allow them to be renamed and resized 452 depending on the me_module in use. 453 454 The MeP allows coprocessor general-purpose registers to be either 455 32 or 64 bits long, depending on the configuration. Since we don't 456 want the format of the 'g' packet to vary from one core to another, 457 the raw coprocessor GPRs are always 64 bits. GDB doesn't allow the 458 types of registers to change (see the implementation of 459 register_type), so we have four banks of pseudoregisters for the 460 coprocessor gprs --- 32-bit vs. 64-bit, and integer 461 vs. floating-point --- and we show or hide them depending on the 462 configuration. */ 463 enum 464 { 465 MEP_FIRST_RAW_REGNUM = 0, 466 467 MEP_FIRST_GPR_REGNUM = 0, 468 MEP_R0_REGNUM = 0, 469 MEP_R1_REGNUM = 1, 470 MEP_R2_REGNUM = 2, 471 MEP_R3_REGNUM = 3, 472 MEP_R4_REGNUM = 4, 473 MEP_R5_REGNUM = 5, 474 MEP_R6_REGNUM = 6, 475 MEP_R7_REGNUM = 7, 476 MEP_R8_REGNUM = 8, 477 MEP_R9_REGNUM = 9, 478 MEP_R10_REGNUM = 10, 479 MEP_R11_REGNUM = 11, 480 MEP_R12_REGNUM = 12, 481 MEP_FP_REGNUM = MEP_R8_REGNUM, 482 MEP_R13_REGNUM = 13, 483 MEP_TP_REGNUM = MEP_R13_REGNUM, /* (r13) Tiny data pointer */ 484 MEP_R14_REGNUM = 14, 485 MEP_GP_REGNUM = MEP_R14_REGNUM, /* (r14) Global pointer */ 486 MEP_R15_REGNUM = 15, 487 MEP_SP_REGNUM = MEP_R15_REGNUM, /* (r15) Stack pointer */ 488 MEP_LAST_GPR_REGNUM = MEP_R15_REGNUM, 489 490 /* The raw control registers. These are the values as received via 491 the remote protocol, directly from the target; we only let user 492 code touch the via the pseudoregisters, which enforce read-only 493 bits. */ 494 MEP_FIRST_RAW_CSR_REGNUM = 16, 495 MEP_RAW_PC_REGNUM = 16, /* Program counter */ 496 MEP_RAW_LP_REGNUM = 17, /* Link pointer */ 497 MEP_RAW_SAR_REGNUM = 18, /* Raw shift amount */ 498 MEP_RAW_CSR3_REGNUM = 19, /* csr3: reserved */ 499 MEP_RAW_RPB_REGNUM = 20, /* Raw repeat begin address */ 500 MEP_RAW_RPE_REGNUM = 21, /* Repeat end address */ 501 MEP_RAW_RPC_REGNUM = 22, /* Repeat count */ 502 MEP_RAW_HI_REGNUM = 23, /* Upper 32 bits of result of 64 bit mult/div */ 503 MEP_RAW_LO_REGNUM = 24, /* Lower 32 bits of result of 64 bit mult/div */ 504 MEP_RAW_CSR9_REGNUM = 25, /* csr3: reserved */ 505 MEP_RAW_CSR10_REGNUM = 26, /* csr3: reserved */ 506 MEP_RAW_CSR11_REGNUM = 27, /* csr3: reserved */ 507 MEP_RAW_MB0_REGNUM = 28, /* Raw modulo begin address 0 */ 508 MEP_RAW_ME0_REGNUM = 29, /* Raw modulo end address 0 */ 509 MEP_RAW_MB1_REGNUM = 30, /* Raw modulo begin address 1 */ 510 MEP_RAW_ME1_REGNUM = 31, /* Raw modulo end address 1 */ 511 MEP_RAW_PSW_REGNUM = 32, /* Raw program status word */ 512 MEP_RAW_ID_REGNUM = 33, /* Raw processor ID/revision */ 513 MEP_RAW_TMP_REGNUM = 34, /* Temporary */ 514 MEP_RAW_EPC_REGNUM = 35, /* Exception program counter */ 515 MEP_RAW_EXC_REGNUM = 36, /* Raw exception cause */ 516 MEP_RAW_CFG_REGNUM = 37, /* Raw processor configuration*/ 517 MEP_RAW_CSR22_REGNUM = 38, /* csr3: reserved */ 518 MEP_RAW_NPC_REGNUM = 39, /* Nonmaskable interrupt PC */ 519 MEP_RAW_DBG_REGNUM = 40, /* Raw debug */ 520 MEP_RAW_DEPC_REGNUM = 41, /* Debug exception PC */ 521 MEP_RAW_OPT_REGNUM = 42, /* Raw options */ 522 MEP_RAW_RCFG_REGNUM = 43, /* Raw local ram config */ 523 MEP_RAW_CCFG_REGNUM = 44, /* Raw cache config */ 524 MEP_RAW_CSR29_REGNUM = 45, /* csr3: reserved */ 525 MEP_RAW_CSR30_REGNUM = 46, /* csr3: reserved */ 526 MEP_RAW_CSR31_REGNUM = 47, /* csr3: reserved */ 527 MEP_LAST_RAW_CSR_REGNUM = MEP_RAW_CSR31_REGNUM, 528 529 /* The raw coprocessor general-purpose registers. These are all 64 530 bits wide. */ 531 MEP_FIRST_RAW_CR_REGNUM = 48, 532 MEP_LAST_RAW_CR_REGNUM = MEP_FIRST_RAW_CR_REGNUM + 31, 533 534 MEP_FIRST_RAW_CCR_REGNUM = 80, 535 MEP_LAST_RAW_CCR_REGNUM = MEP_FIRST_RAW_CCR_REGNUM + 63, 536 537 /* The module number register. This is the index of the me_module 538 of which the current target is an instance. (This is not a real 539 MeP-specified register; it's provided by SID.) */ 540 MEP_MODULE_REGNUM, 541 542 MEP_LAST_RAW_REGNUM = MEP_MODULE_REGNUM, 543 544 MEP_NUM_RAW_REGS = MEP_LAST_RAW_REGNUM + 1, 545 546 /* Pseudoregisters. See mep_pseudo_register_read and 547 mep_pseudo_register_write. */ 548 MEP_FIRST_PSEUDO_REGNUM = MEP_NUM_RAW_REGS, 549 550 /* We have a pseudoregister for every control/special register, to 551 implement registers with read-only bits. */ 552 MEP_FIRST_CSR_REGNUM = MEP_FIRST_PSEUDO_REGNUM, 553 MEP_PC_REGNUM = MEP_FIRST_CSR_REGNUM, /* Program counter */ 554 MEP_LP_REGNUM, /* Link pointer */ 555 MEP_SAR_REGNUM, /* shift amount */ 556 MEP_CSR3_REGNUM, /* csr3: reserved */ 557 MEP_RPB_REGNUM, /* repeat begin address */ 558 MEP_RPE_REGNUM, /* Repeat end address */ 559 MEP_RPC_REGNUM, /* Repeat count */ 560 MEP_HI_REGNUM, /* Upper 32 bits of the result of 64 bit mult/div */ 561 MEP_LO_REGNUM, /* Lower 32 bits of the result of 64 bit mult/div */ 562 MEP_CSR9_REGNUM, /* csr3: reserved */ 563 MEP_CSR10_REGNUM, /* csr3: reserved */ 564 MEP_CSR11_REGNUM, /* csr3: reserved */ 565 MEP_MB0_REGNUM, /* modulo begin address 0 */ 566 MEP_ME0_REGNUM, /* modulo end address 0 */ 567 MEP_MB1_REGNUM, /* modulo begin address 1 */ 568 MEP_ME1_REGNUM, /* modulo end address 1 */ 569 MEP_PSW_REGNUM, /* program status word */ 570 MEP_ID_REGNUM, /* processor ID/revision */ 571 MEP_TMP_REGNUM, /* Temporary */ 572 MEP_EPC_REGNUM, /* Exception program counter */ 573 MEP_EXC_REGNUM, /* exception cause */ 574 MEP_CFG_REGNUM, /* processor configuration*/ 575 MEP_CSR22_REGNUM, /* csr3: reserved */ 576 MEP_NPC_REGNUM, /* Nonmaskable interrupt PC */ 577 MEP_DBG_REGNUM, /* debug */ 578 MEP_DEPC_REGNUM, /* Debug exception PC */ 579 MEP_OPT_REGNUM, /* options */ 580 MEP_RCFG_REGNUM, /* local ram config */ 581 MEP_CCFG_REGNUM, /* cache config */ 582 MEP_CSR29_REGNUM, /* csr3: reserved */ 583 MEP_CSR30_REGNUM, /* csr3: reserved */ 584 MEP_CSR31_REGNUM, /* csr3: reserved */ 585 MEP_LAST_CSR_REGNUM = MEP_CSR31_REGNUM, 586 587 /* The 32-bit integer view of the coprocessor GPR's. */ 588 MEP_FIRST_CR32_REGNUM, 589 MEP_LAST_CR32_REGNUM = MEP_FIRST_CR32_REGNUM + 31, 590 591 /* The 32-bit floating-point view of the coprocessor GPR's. */ 592 MEP_FIRST_FP_CR32_REGNUM, 593 MEP_LAST_FP_CR32_REGNUM = MEP_FIRST_FP_CR32_REGNUM + 31, 594 595 /* The 64-bit integer view of the coprocessor GPR's. */ 596 MEP_FIRST_CR64_REGNUM, 597 MEP_LAST_CR64_REGNUM = MEP_FIRST_CR64_REGNUM + 31, 598 599 /* The 64-bit floating-point view of the coprocessor GPR's. */ 600 MEP_FIRST_FP_CR64_REGNUM, 601 MEP_LAST_FP_CR64_REGNUM = MEP_FIRST_FP_CR64_REGNUM + 31, 602 603 MEP_FIRST_CCR_REGNUM, 604 MEP_LAST_CCR_REGNUM = MEP_FIRST_CCR_REGNUM + 63, 605 606 MEP_LAST_PSEUDO_REGNUM = MEP_LAST_CCR_REGNUM, 607 608 MEP_NUM_PSEUDO_REGS = (MEP_LAST_PSEUDO_REGNUM - MEP_LAST_RAW_REGNUM), 609 610 MEP_NUM_REGS = MEP_NUM_RAW_REGS + MEP_NUM_PSEUDO_REGS 611 }; 612 613 614 #define IN_SET(set, n) \ 615 (MEP_FIRST_ ## set ## _REGNUM <= (n) && (n) <= MEP_LAST_ ## set ## _REGNUM) 616 617 #define IS_GPR_REGNUM(n) (IN_SET (GPR, (n))) 618 #define IS_RAW_CSR_REGNUM(n) (IN_SET (RAW_CSR, (n))) 619 #define IS_RAW_CR_REGNUM(n) (IN_SET (RAW_CR, (n))) 620 #define IS_RAW_CCR_REGNUM(n) (IN_SET (RAW_CCR, (n))) 621 622 #define IS_CSR_REGNUM(n) (IN_SET (CSR, (n))) 623 #define IS_CR32_REGNUM(n) (IN_SET (CR32, (n))) 624 #define IS_FP_CR32_REGNUM(n) (IN_SET (FP_CR32, (n))) 625 #define IS_CR64_REGNUM(n) (IN_SET (CR64, (n))) 626 #define IS_FP_CR64_REGNUM(n) (IN_SET (FP_CR64, (n))) 627 #define IS_CR_REGNUM(n) (IS_CR32_REGNUM (n) || IS_FP_CR32_REGNUM (n) \ 628 || IS_CR64_REGNUM (n) || IS_FP_CR64_REGNUM (n)) 629 #define IS_CCR_REGNUM(n) (IN_SET (CCR, (n))) 630 631 #define IS_RAW_REGNUM(n) (IN_SET (RAW, (n))) 632 #define IS_PSEUDO_REGNUM(n) (IN_SET (PSEUDO, (n))) 633 634 #define NUM_REGS_IN_SET(set) \ 635 (MEP_LAST_ ## set ## _REGNUM - MEP_FIRST_ ## set ## _REGNUM + 1) 636 637 #define MEP_GPR_SIZE (4) /* Size of a MeP general-purpose register. */ 638 #define MEP_PSW_SIZE (4) /* Size of the PSW register. */ 639 #define MEP_LP_SIZE (4) /* Size of the LP register. */ 640 641 642 /* Many of the control/special registers contain bits that cannot be 643 written to; some are entirely read-only. So we present them all as 644 pseudoregisters. 645 646 The following table describes the special properties of each CSR. */ 647 struct mep_csr_register 648 { 649 /* The number of this CSR's raw register. */ 650 int raw; 651 652 /* The number of this CSR's pseudoregister. */ 653 int pseudo; 654 655 /* A mask of the bits that are writeable: if a bit is set here, then 656 it can be modified; if the bit is clear, then it cannot. */ 657 LONGEST writeable_bits; 658 }; 659 660 661 /* mep_csr_registers[i] describes the i'th CSR. 662 We just list the register numbers here explicitly to help catch 663 typos. */ 664 #define CSR(name) MEP_RAW_ ## name ## _REGNUM, MEP_ ## name ## _REGNUM 665 struct mep_csr_register mep_csr_registers[] = { 666 { CSR(PC), 0xffffffff }, /* manual says r/o, but we can write it */ 667 { CSR(LP), 0xffffffff }, 668 { CSR(SAR), 0x0000003f }, 669 { CSR(CSR3), 0xffffffff }, 670 { CSR(RPB), 0xfffffffe }, 671 { CSR(RPE), 0xffffffff }, 672 { CSR(RPC), 0xffffffff }, 673 { CSR(HI), 0xffffffff }, 674 { CSR(LO), 0xffffffff }, 675 { CSR(CSR9), 0xffffffff }, 676 { CSR(CSR10), 0xffffffff }, 677 { CSR(CSR11), 0xffffffff }, 678 { CSR(MB0), 0x0000ffff }, 679 { CSR(ME0), 0x0000ffff }, 680 { CSR(MB1), 0x0000ffff }, 681 { CSR(ME1), 0x0000ffff }, 682 { CSR(PSW), 0x000003ff }, 683 { CSR(ID), 0x00000000 }, 684 { CSR(TMP), 0xffffffff }, 685 { CSR(EPC), 0xffffffff }, 686 { CSR(EXC), 0x000030f0 }, 687 { CSR(CFG), 0x00c0001b }, 688 { CSR(CSR22), 0xffffffff }, 689 { CSR(NPC), 0xffffffff }, 690 { CSR(DBG), 0x00000580 }, 691 { CSR(DEPC), 0xffffffff }, 692 { CSR(OPT), 0x00000000 }, 693 { CSR(RCFG), 0x00000000 }, 694 { CSR(CCFG), 0x00000000 }, 695 { CSR(CSR29), 0xffffffff }, 696 { CSR(CSR30), 0xffffffff }, 697 { CSR(CSR31), 0xffffffff }, 698 }; 699 700 701 /* If R is the number of a raw register, then mep_raw_to_pseudo[R] is 702 the number of the corresponding pseudoregister. Otherwise, 703 mep_raw_to_pseudo[R] == R. */ 704 static int mep_raw_to_pseudo[MEP_NUM_REGS]; 705 706 /* If R is the number of a pseudoregister, then mep_pseudo_to_raw[R] 707 is the number of the underlying raw register. Otherwise 708 mep_pseudo_to_raw[R] == R. */ 709 static int mep_pseudo_to_raw[MEP_NUM_REGS]; 710 711 static void 712 mep_init_pseudoregister_maps (void) 713 { 714 int i; 715 716 /* Verify that mep_csr_registers covers all the CSRs, in order. */ 717 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (CSR)); 718 gdb_assert (ARRAY_SIZE (mep_csr_registers) == NUM_REGS_IN_SET (RAW_CSR)); 719 720 /* Verify that the raw and pseudo ranges have matching sizes. */ 721 gdb_assert (NUM_REGS_IN_SET (RAW_CSR) == NUM_REGS_IN_SET (CSR)); 722 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR32)); 723 gdb_assert (NUM_REGS_IN_SET (RAW_CR) == NUM_REGS_IN_SET (CR64)); 724 gdb_assert (NUM_REGS_IN_SET (RAW_CCR) == NUM_REGS_IN_SET (CCR)); 725 726 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) 727 { 728 struct mep_csr_register *r = &mep_csr_registers[i]; 729 730 gdb_assert (r->pseudo == MEP_FIRST_CSR_REGNUM + i); 731 gdb_assert (r->raw == MEP_FIRST_RAW_CSR_REGNUM + i); 732 } 733 734 /* Set up the initial raw<->pseudo mappings. */ 735 for (i = 0; i < MEP_NUM_REGS; i++) 736 { 737 mep_raw_to_pseudo[i] = i; 738 mep_pseudo_to_raw[i] = i; 739 } 740 741 /* Add the CSR raw<->pseudo mappings. */ 742 for (i = 0; i < ARRAY_SIZE (mep_csr_registers); i++) 743 { 744 struct mep_csr_register *r = &mep_csr_registers[i]; 745 746 mep_raw_to_pseudo[r->raw] = r->pseudo; 747 mep_pseudo_to_raw[r->pseudo] = r->raw; 748 } 749 750 /* Add the CR raw<->pseudo mappings. */ 751 for (i = 0; i < NUM_REGS_IN_SET (RAW_CR); i++) 752 { 753 int raw = MEP_FIRST_RAW_CR_REGNUM + i; 754 int pseudo32 = MEP_FIRST_CR32_REGNUM + i; 755 int pseudofp32 = MEP_FIRST_FP_CR32_REGNUM + i; 756 int pseudo64 = MEP_FIRST_CR64_REGNUM + i; 757 int pseudofp64 = MEP_FIRST_FP_CR64_REGNUM + i; 758 759 /* Truly, the raw->pseudo mapping depends on the current module. 760 But we use the raw->pseudo mapping when we read the debugging 761 info; at that point, we don't know what module we'll actually 762 be running yet. So, we always supply the 64-bit register 763 numbers; GDB knows how to pick a smaller value out of a 764 larger register properly. */ 765 mep_raw_to_pseudo[raw] = pseudo64; 766 mep_pseudo_to_raw[pseudo32] = raw; 767 mep_pseudo_to_raw[pseudofp32] = raw; 768 mep_pseudo_to_raw[pseudo64] = raw; 769 mep_pseudo_to_raw[pseudofp64] = raw; 770 } 771 772 /* Add the CCR raw<->pseudo mappings. */ 773 for (i = 0; i < NUM_REGS_IN_SET (CCR); i++) 774 { 775 int raw = MEP_FIRST_RAW_CCR_REGNUM + i; 776 int pseudo = MEP_FIRST_CCR_REGNUM + i; 777 mep_raw_to_pseudo[raw] = pseudo; 778 mep_pseudo_to_raw[pseudo] = raw; 779 } 780 } 781 782 783 static int 784 mep_debug_reg_to_regnum (struct gdbarch *gdbarch, int debug_reg) 785 { 786 /* The debug info uses the raw register numbers. */ 787 if (debug_reg >= 0 && debug_reg < ARRAY_SIZE (mep_raw_to_pseudo)) 788 return mep_raw_to_pseudo[debug_reg]; 789 return -1; 790 } 791 792 793 /* Return the size, in bits, of the coprocessor pseudoregister 794 numbered PSEUDO. */ 795 static int 796 mep_pseudo_cr_size (int pseudo) 797 { 798 if (IS_CR32_REGNUM (pseudo) 799 || IS_FP_CR32_REGNUM (pseudo)) 800 return 32; 801 else if (IS_CR64_REGNUM (pseudo) 802 || IS_FP_CR64_REGNUM (pseudo)) 803 return 64; 804 else 805 gdb_assert_not_reached ("unexpected coprocessor pseudo register"); 806 } 807 808 809 /* If the coprocessor pseudoregister numbered PSEUDO is a 810 floating-point register, return non-zero; if it is an integer 811 register, return zero. */ 812 static int 813 mep_pseudo_cr_is_float (int pseudo) 814 { 815 return (IS_FP_CR32_REGNUM (pseudo) 816 || IS_FP_CR64_REGNUM (pseudo)); 817 } 818 819 820 /* Given a coprocessor GPR pseudoregister number, return its index 821 within that register bank. */ 822 static int 823 mep_pseudo_cr_index (int pseudo) 824 { 825 if (IS_CR32_REGNUM (pseudo)) 826 return pseudo - MEP_FIRST_CR32_REGNUM; 827 else if (IS_FP_CR32_REGNUM (pseudo)) 828 return pseudo - MEP_FIRST_FP_CR32_REGNUM; 829 else if (IS_CR64_REGNUM (pseudo)) 830 return pseudo - MEP_FIRST_CR64_REGNUM; 831 else if (IS_FP_CR64_REGNUM (pseudo)) 832 return pseudo - MEP_FIRST_FP_CR64_REGNUM; 833 else 834 gdb_assert_not_reached ("unexpected coprocessor pseudo register"); 835 } 836 837 838 /* Return the me_module index describing the current target. 839 840 If the current target has registers (e.g., simulator, remote 841 target), then this uses the value of the 'module' register, raw 842 register MEP_MODULE_REGNUM. Otherwise, this retrieves the value 843 from the ELF header's e_flags field of the current executable 844 file. */ 845 static CONFIG_ATTR 846 current_me_module (void) 847 { 848 if (target_has_registers) 849 { 850 ULONGEST regval; 851 regcache_cooked_read_unsigned (get_current_regcache (), 852 MEP_MODULE_REGNUM, ®val); 853 return (CONFIG_ATTR) regval; 854 } 855 else 856 return gdbarch_tdep (target_gdbarch ())->me_module; 857 } 858 859 860 /* Return the set of options for the current target, in the form that 861 the OPT register would use. 862 863 If the current target has registers (e.g., simulator, remote 864 target), then this is the actual value of the OPT register. If the 865 current target does not have registers (e.g., an executable file), 866 then use the 'module_opt' field we computed when we build the 867 gdbarch object for this module. */ 868 static unsigned int 869 current_options (void) 870 { 871 if (target_has_registers) 872 { 873 ULONGEST regval; 874 regcache_cooked_read_unsigned (get_current_regcache (), 875 MEP_OPT_REGNUM, ®val); 876 return regval; 877 } 878 else 879 return me_module_opt (current_me_module ()); 880 } 881 882 883 /* Return the width of the current me_module's coprocessor data bus, 884 in bits. This is either 32 or 64. */ 885 static int 886 current_cop_data_bus_width (void) 887 { 888 return me_module_cop_data_bus_width (current_me_module ()); 889 } 890 891 892 /* Return the keyword table of coprocessor general-purpose register 893 names appropriate for the me_module we're dealing with. */ 894 static CGEN_KEYWORD * 895 current_cr_names (void) 896 { 897 const CGEN_HW_ENTRY *hw 898 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); 899 900 return register_set_keyword_table (hw); 901 } 902 903 904 /* Return non-zero if the coprocessor general-purpose registers are 905 floating-point values, zero otherwise. */ 906 static int 907 current_cr_is_float (void) 908 { 909 const CGEN_HW_ENTRY *hw 910 = me_module_register_set (current_me_module (), "h-cr-", HW_H_CR); 911 912 return CGEN_ATTR_CGEN_HW_IS_FLOAT_VALUE (CGEN_HW_ATTRS (hw)); 913 } 914 915 916 /* Return the keyword table of coprocessor control register names 917 appropriate for the me_module we're dealing with. */ 918 static CGEN_KEYWORD * 919 current_ccr_names (void) 920 { 921 const CGEN_HW_ENTRY *hw 922 = me_module_register_set (current_me_module (), "h-ccr-", HW_H_CCR); 923 924 return register_set_keyword_table (hw); 925 } 926 927 928 static const char * 929 mep_register_name (struct gdbarch *gdbarch, int regnr) 930 { 931 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 932 933 /* General-purpose registers. */ 934 static const char *gpr_names[] = { 935 "r0", "r1", "r2", "r3", /* 0 */ 936 "r4", "r5", "r6", "r7", /* 4 */ 937 "fp", "r9", "r10", "r11", /* 8 */ 938 "r12", "tp", "gp", "sp" /* 12 */ 939 }; 940 941 /* Special-purpose registers. */ 942 static const char *csr_names[] = { 943 "pc", "lp", "sar", "", /* 0 csr3: reserved */ 944 "rpb", "rpe", "rpc", "hi", /* 4 */ 945 "lo", "", "", "", /* 8 csr9-csr11: reserved */ 946 "mb0", "me0", "mb1", "me1", /* 12 */ 947 948 "psw", "id", "tmp", "epc", /* 16 */ 949 "exc", "cfg", "", "npc", /* 20 csr22: reserved */ 950 "dbg", "depc", "opt", "rcfg", /* 24 */ 951 "ccfg", "", "", "" /* 28 csr29-csr31: reserved */ 952 }; 953 954 if (IS_GPR_REGNUM (regnr)) 955 return gpr_names[regnr - MEP_R0_REGNUM]; 956 else if (IS_CSR_REGNUM (regnr)) 957 { 958 /* The 'hi' and 'lo' registers are only present on processors 959 that have the 'MUL' or 'DIV' instructions enabled. */ 960 if ((regnr == MEP_HI_REGNUM || regnr == MEP_LO_REGNUM) 961 && (! (current_options () & (MEP_OPT_MUL | MEP_OPT_DIV)))) 962 return ""; 963 964 return csr_names[regnr - MEP_FIRST_CSR_REGNUM]; 965 } 966 else if (IS_CR_REGNUM (regnr)) 967 { 968 CGEN_KEYWORD *names; 969 int cr_size; 970 int cr_is_float; 971 972 /* Does this module have a coprocessor at all? */ 973 if (! (current_options () & MEP_OPT_COP)) 974 return ""; 975 976 names = current_cr_names (); 977 if (! names) 978 /* This module's coprocessor has no general-purpose registers. */ 979 return ""; 980 981 cr_size = current_cop_data_bus_width (); 982 if (cr_size != mep_pseudo_cr_size (regnr)) 983 /* This module's coprocessor's GPR's are of a different size. */ 984 return ""; 985 986 cr_is_float = current_cr_is_float (); 987 /* The extra ! operators ensure we get boolean equality, not 988 numeric equality. */ 989 if (! cr_is_float != ! mep_pseudo_cr_is_float (regnr)) 990 /* This module's coprocessor's GPR's are of a different type. */ 991 return ""; 992 993 return register_name_from_keyword (names, mep_pseudo_cr_index (regnr)); 994 } 995 else if (IS_CCR_REGNUM (regnr)) 996 { 997 /* Does this module have a coprocessor at all? */ 998 if (! (current_options () & MEP_OPT_COP)) 999 return ""; 1000 1001 { 1002 CGEN_KEYWORD *names = current_ccr_names (); 1003 1004 if (! names) 1005 /* This me_module's coprocessor has no control registers. */ 1006 return ""; 1007 1008 return register_name_from_keyword (names, regnr-MEP_FIRST_CCR_REGNUM); 1009 } 1010 } 1011 1012 /* It might be nice to give the 'module' register a name, but that 1013 would affect the output of 'info all-registers', which would 1014 disturb the test suites. So we leave it invisible. */ 1015 else 1016 return NULL; 1017 } 1018 1019 1020 /* Custom register groups for the MeP. */ 1021 static struct reggroup *mep_csr_reggroup; /* control/special */ 1022 static struct reggroup *mep_cr_reggroup; /* coprocessor general-purpose */ 1023 static struct reggroup *mep_ccr_reggroup; /* coprocessor control */ 1024 1025 1026 static int 1027 mep_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 1028 struct reggroup *group) 1029 { 1030 /* Filter reserved or unused register numbers. */ 1031 { 1032 const char *name = mep_register_name (gdbarch, regnum); 1033 1034 if (! name || name[0] == '\0') 1035 return 0; 1036 } 1037 1038 /* We could separate the GPRs and the CSRs. Toshiba has approved of 1039 the existing behavior, so we'd want to run that by them. */ 1040 if (group == general_reggroup) 1041 return (IS_GPR_REGNUM (regnum) 1042 || IS_CSR_REGNUM (regnum)); 1043 1044 /* Everything is in the 'all' reggroup, except for the raw CSR's. */ 1045 else if (group == all_reggroup) 1046 return (IS_GPR_REGNUM (regnum) 1047 || IS_CSR_REGNUM (regnum) 1048 || IS_CR_REGNUM (regnum) 1049 || IS_CCR_REGNUM (regnum)); 1050 1051 /* All registers should be saved and restored, except for the raw 1052 CSR's. 1053 1054 This is probably right if the coprocessor is something like a 1055 floating-point unit, but would be wrong if the coprocessor is 1056 something that does I/O, where register accesses actually cause 1057 externally-visible actions. But I get the impression that the 1058 coprocessor isn't supposed to do things like that --- you'd use a 1059 hardware engine, perhaps. */ 1060 else if (group == save_reggroup || group == restore_reggroup) 1061 return (IS_GPR_REGNUM (regnum) 1062 || IS_CSR_REGNUM (regnum) 1063 || IS_CR_REGNUM (regnum) 1064 || IS_CCR_REGNUM (regnum)); 1065 1066 else if (group == mep_csr_reggroup) 1067 return IS_CSR_REGNUM (regnum); 1068 else if (group == mep_cr_reggroup) 1069 return IS_CR_REGNUM (regnum); 1070 else if (group == mep_ccr_reggroup) 1071 return IS_CCR_REGNUM (regnum); 1072 else 1073 return 0; 1074 } 1075 1076 1077 static struct type * 1078 mep_register_type (struct gdbarch *gdbarch, int reg_nr) 1079 { 1080 /* Coprocessor general-purpose registers may be either 32 or 64 bits 1081 long. So for them, the raw registers are always 64 bits long (to 1082 keep the 'g' packet format fixed), and the pseudoregisters vary 1083 in length. */ 1084 if (IS_RAW_CR_REGNUM (reg_nr)) 1085 return builtin_type (gdbarch)->builtin_uint64; 1086 1087 /* Since GDB doesn't allow registers to change type, we have two 1088 banks of pseudoregisters for the coprocessor general-purpose 1089 registers: one that gives a 32-bit view, and one that gives a 1090 64-bit view. We hide or show one or the other depending on the 1091 current module. */ 1092 if (IS_CR_REGNUM (reg_nr)) 1093 { 1094 int size = mep_pseudo_cr_size (reg_nr); 1095 if (size == 32) 1096 { 1097 if (mep_pseudo_cr_is_float (reg_nr)) 1098 return builtin_type (gdbarch)->builtin_float; 1099 else 1100 return builtin_type (gdbarch)->builtin_uint32; 1101 } 1102 else if (size == 64) 1103 { 1104 if (mep_pseudo_cr_is_float (reg_nr)) 1105 return builtin_type (gdbarch)->builtin_double; 1106 else 1107 return builtin_type (gdbarch)->builtin_uint64; 1108 } 1109 else 1110 gdb_assert_not_reached ("unexpected cr size"); 1111 } 1112 1113 /* All other registers are 32 bits long. */ 1114 else 1115 return builtin_type (gdbarch)->builtin_uint32; 1116 } 1117 1118 1119 static CORE_ADDR 1120 mep_read_pc (struct regcache *regcache) 1121 { 1122 ULONGEST pc; 1123 regcache_cooked_read_unsigned (regcache, MEP_PC_REGNUM, &pc); 1124 return pc; 1125 } 1126 1127 static enum register_status 1128 mep_pseudo_cr32_read (struct gdbarch *gdbarch, 1129 struct regcache *regcache, 1130 int cookednum, 1131 gdb_byte *buf) 1132 { 1133 enum register_status status; 1134 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1135 /* Read the raw register into a 64-bit buffer, and then return the 1136 appropriate end of that buffer. */ 1137 int rawnum = mep_pseudo_to_raw[cookednum]; 1138 gdb_byte buf64[8]; 1139 1140 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); 1141 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); 1142 status = regcache_raw_read (regcache, rawnum, buf64); 1143 if (status == REG_VALID) 1144 { 1145 /* Slow, but legible. */ 1146 store_unsigned_integer (buf, 4, byte_order, 1147 extract_unsigned_integer (buf64, 8, byte_order)); 1148 } 1149 return status; 1150 } 1151 1152 1153 static enum register_status 1154 mep_pseudo_cr64_read (struct gdbarch *gdbarch, 1155 struct regcache *regcache, 1156 int cookednum, 1157 gdb_byte *buf) 1158 { 1159 return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); 1160 } 1161 1162 1163 static enum register_status 1164 mep_pseudo_register_read (struct gdbarch *gdbarch, 1165 struct regcache *regcache, 1166 int cookednum, 1167 gdb_byte *buf) 1168 { 1169 if (IS_CSR_REGNUM (cookednum) 1170 || IS_CCR_REGNUM (cookednum)) 1171 return regcache_raw_read (regcache, mep_pseudo_to_raw[cookednum], buf); 1172 else if (IS_CR32_REGNUM (cookednum) 1173 || IS_FP_CR32_REGNUM (cookednum)) 1174 return mep_pseudo_cr32_read (gdbarch, regcache, cookednum, buf); 1175 else if (IS_CR64_REGNUM (cookednum) 1176 || IS_FP_CR64_REGNUM (cookednum)) 1177 return mep_pseudo_cr64_read (gdbarch, regcache, cookednum, buf); 1178 else 1179 gdb_assert_not_reached ("unexpected pseudo register"); 1180 } 1181 1182 1183 static void 1184 mep_pseudo_csr_write (struct gdbarch *gdbarch, 1185 struct regcache *regcache, 1186 int cookednum, 1187 const gdb_byte *buf) 1188 { 1189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1190 int size = register_size (gdbarch, cookednum); 1191 struct mep_csr_register *r 1192 = &mep_csr_registers[cookednum - MEP_FIRST_CSR_REGNUM]; 1193 1194 if (r->writeable_bits == 0) 1195 /* A completely read-only register; avoid the read-modify- 1196 write cycle, and juts ignore the entire write. */ 1197 ; 1198 else 1199 { 1200 /* A partially writeable register; do a read-modify-write cycle. */ 1201 ULONGEST old_bits; 1202 ULONGEST new_bits; 1203 ULONGEST mixed_bits; 1204 1205 regcache_raw_read_unsigned (regcache, r->raw, &old_bits); 1206 new_bits = extract_unsigned_integer (buf, size, byte_order); 1207 mixed_bits = ((r->writeable_bits & new_bits) 1208 | (~r->writeable_bits & old_bits)); 1209 regcache_raw_write_unsigned (regcache, r->raw, mixed_bits); 1210 } 1211 } 1212 1213 1214 static void 1215 mep_pseudo_cr32_write (struct gdbarch *gdbarch, 1216 struct regcache *regcache, 1217 int cookednum, 1218 const gdb_byte *buf) 1219 { 1220 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1221 /* Expand the 32-bit value into a 64-bit value, and write that to 1222 the pseudoregister. */ 1223 int rawnum = mep_pseudo_to_raw[cookednum]; 1224 gdb_byte buf64[8]; 1225 1226 gdb_assert (TYPE_LENGTH (register_type (gdbarch, rawnum)) == sizeof (buf64)); 1227 gdb_assert (TYPE_LENGTH (register_type (gdbarch, cookednum)) == 4); 1228 /* Slow, but legible. */ 1229 store_unsigned_integer (buf64, 8, byte_order, 1230 extract_unsigned_integer (buf, 4, byte_order)); 1231 regcache_raw_write (regcache, rawnum, buf64); 1232 } 1233 1234 1235 static void 1236 mep_pseudo_cr64_write (struct gdbarch *gdbarch, 1237 struct regcache *regcache, 1238 int cookednum, 1239 const gdb_byte *buf) 1240 { 1241 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); 1242 } 1243 1244 1245 static void 1246 mep_pseudo_register_write (struct gdbarch *gdbarch, 1247 struct regcache *regcache, 1248 int cookednum, 1249 const gdb_byte *buf) 1250 { 1251 if (IS_CSR_REGNUM (cookednum)) 1252 mep_pseudo_csr_write (gdbarch, regcache, cookednum, buf); 1253 else if (IS_CR32_REGNUM (cookednum) 1254 || IS_FP_CR32_REGNUM (cookednum)) 1255 mep_pseudo_cr32_write (gdbarch, regcache, cookednum, buf); 1256 else if (IS_CR64_REGNUM (cookednum) 1257 || IS_FP_CR64_REGNUM (cookednum)) 1258 mep_pseudo_cr64_write (gdbarch, regcache, cookednum, buf); 1259 else if (IS_CCR_REGNUM (cookednum)) 1260 regcache_raw_write (regcache, mep_pseudo_to_raw[cookednum], buf); 1261 else 1262 gdb_assert_not_reached ("unexpected pseudo register"); 1263 } 1264 1265 1266 1267 /* Disassembly. */ 1268 1269 static int 1270 mep_gdb_print_insn (bfd_vma pc, disassemble_info * info) 1271 { 1272 struct obj_section * s = find_pc_section (pc); 1273 1274 info->arch = bfd_arch_mep; 1275 if (s) 1276 { 1277 /* The libopcodes disassembly code uses the section to find the 1278 BFD, the BFD to find the ELF header, the ELF header to find 1279 the me_module index, and the me_module index to select the 1280 right instructions to print. */ 1281 info->section = s->the_bfd_section; 1282 } 1283 1284 return print_insn_mep (pc, info); 1285 } 1286 1287 1288 /* Prologue analysis. */ 1289 1290 1291 /* The MeP has two classes of instructions: "core" instructions, which 1292 are pretty normal RISC chip stuff, and "coprocessor" instructions, 1293 which are mostly concerned with moving data in and out of 1294 coprocessor registers, and branching on coprocessor condition 1295 codes. There's space in the instruction set for custom coprocessor 1296 instructions, too. 1297 1298 Instructions can be 16 or 32 bits long; the top two bits of the 1299 first byte indicate the length. The coprocessor instructions are 1300 mixed in with the core instructions, and there's no easy way to 1301 distinguish them; you have to completely decode them to tell one 1302 from the other. 1303 1304 The MeP also supports a "VLIW" operation mode, where instructions 1305 always occur in fixed-width bundles. The bundles are either 32 1306 bits or 64 bits long, depending on a fixed configuration flag. You 1307 decode the first part of the bundle as normal; if it's a core 1308 instruction, and there's any space left in the bundle, the 1309 remainder of the bundle is a coprocessor instruction, which will 1310 execute in parallel with the core instruction. If the first part 1311 of the bundle is a coprocessor instruction, it occupies the entire 1312 bundle. 1313 1314 So, here are all the cases: 1315 1316 - 32-bit VLIW mode: 1317 Every bundle is four bytes long, and naturally aligned, and can hold 1318 one or two instructions: 1319 - 16-bit core instruction; 16-bit coprocessor instruction 1320 These execute in parallel. 1321 - 32-bit core instruction 1322 - 32-bit coprocessor instruction 1323 1324 - 64-bit VLIW mode: 1325 Every bundle is eight bytes long, and naturally aligned, and can hold 1326 one or two instructions: 1327 - 16-bit core instruction; 48-bit (!) coprocessor instruction 1328 These execute in parallel. 1329 - 32-bit core instruction; 32-bit coprocessor instruction 1330 These execute in parallel. 1331 - 64-bit coprocessor instruction 1332 1333 Now, the MeP manual doesn't define any 48- or 64-bit coprocessor 1334 instruction, so I don't really know what's up there; perhaps these 1335 are always the user-defined coprocessor instructions. */ 1336 1337 1338 /* Return non-zero if PC is in a VLIW code section, zero 1339 otherwise. */ 1340 static int 1341 mep_pc_in_vliw_section (CORE_ADDR pc) 1342 { 1343 struct obj_section *s = find_pc_section (pc); 1344 if (s) 1345 return (s->the_bfd_section->flags & SEC_MEP_VLIW); 1346 return 0; 1347 } 1348 1349 1350 /* Set *INSN to the next core instruction at PC, and return the 1351 address of the next instruction. 1352 1353 The MeP instruction encoding is endian-dependent. 16- and 32-bit 1354 instructions are encoded as one or two two-byte parts, and each 1355 part is byte-swapped independently. Thus: 1356 1357 void 1358 foo (void) 1359 { 1360 asm ("movu $1, 0x123456"); 1361 asm ("sb $1,0x5678($2)"); 1362 asm ("clip $1, 19"); 1363 } 1364 1365 compiles to this big-endian code: 1366 1367 0: d1 56 12 34 movu $1,0x123456 1368 4: c1 28 56 78 sb $1,22136($2) 1369 8: f1 01 10 98 clip $1,0x13 1370 c: 70 02 ret 1371 1372 and this little-endian code: 1373 1374 0: 56 d1 34 12 movu $1,0x123456 1375 4: 28 c1 78 56 sb $1,22136($2) 1376 8: 01 f1 98 10 clip $1,0x13 1377 c: 02 70 ret 1378 1379 Instructions are returned in *INSN in an endian-independent form: a 1380 given instruction always appears in *INSN the same way, regardless 1381 of whether the instruction stream is big-endian or little-endian. 1382 1383 *INSN's most significant 16 bits are the first (i.e., at lower 1384 addresses) 16 bit part of the instruction. Its least significant 1385 16 bits are the second (i.e., higher-addressed) 16 bit part of the 1386 instruction, or zero for a 16-bit instruction. Both 16-bit parts 1387 are fetched using the current endianness. 1388 1389 So, the *INSN values for the instruction sequence above would be 1390 the following, in either endianness: 1391 1392 0xd1561234 movu $1,0x123456 1393 0xc1285678 sb $1,22136($2) 1394 0xf1011098 clip $1,0x13 1395 0x70020000 ret 1396 1397 (In a sense, it would be more natural to return 16-bit instructions 1398 in the least significant 16 bits of *INSN, but that would be 1399 ambiguous. In order to tell whether you're looking at a 16- or a 1400 32-bit instruction, you have to consult the major opcode field --- 1401 the most significant four bits of the instruction's first 16-bit 1402 part. But if we put 16-bit instructions at the least significant 1403 end of *INSN, then you don't know where to find the major opcode 1404 field until you know if it's a 16- or a 32-bit instruction --- 1405 which is where we started.) 1406 1407 If PC points to a core / coprocessor bundle in a VLIW section, set 1408 *INSN to the core instruction, and return the address of the next 1409 bundle. This has the effect of skipping the bundled coprocessor 1410 instruction. That's okay, since coprocessor instructions aren't 1411 significant to prologue analysis --- for the time being, 1412 anyway. */ 1413 1414 static CORE_ADDR 1415 mep_get_insn (struct gdbarch *gdbarch, CORE_ADDR pc, unsigned long *insn) 1416 { 1417 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1418 int pc_in_vliw_section; 1419 int vliw_mode; 1420 int insn_len; 1421 gdb_byte buf[2]; 1422 1423 *insn = 0; 1424 1425 /* Are we in a VLIW section? */ 1426 pc_in_vliw_section = mep_pc_in_vliw_section (pc); 1427 if (pc_in_vliw_section) 1428 { 1429 /* Yes, find out which bundle size. */ 1430 vliw_mode = current_options () & (MEP_OPT_VL32 | MEP_OPT_VL64); 1431 1432 /* If PC is in a VLIW section, but the current core doesn't say 1433 that it supports either VLIW mode, then we don't have enough 1434 information to parse the instruction stream it contains. 1435 Since the "undifferentiated" standard core doesn't have 1436 either VLIW mode bit set, this could happen. 1437 1438 But it shouldn't be an error to (say) set a breakpoint in a 1439 VLIW section, if you know you'll never reach it. (Perhaps 1440 you have a script that sets a bunch of standard breakpoints.) 1441 1442 So we'll just return zero here, and hope for the best. */ 1443 if (! (vliw_mode & (MEP_OPT_VL32 | MEP_OPT_VL64))) 1444 return 0; 1445 1446 /* If both VL32 and VL64 are set, that's bogus, too. */ 1447 if (vliw_mode == (MEP_OPT_VL32 | MEP_OPT_VL64)) 1448 return 0; 1449 } 1450 else 1451 vliw_mode = 0; 1452 1453 read_memory (pc, buf, sizeof (buf)); 1454 *insn = extract_unsigned_integer (buf, 2, byte_order) << 16; 1455 1456 /* The major opcode --- the top four bits of the first 16-bit 1457 part --- indicates whether this instruction is 16 or 32 bits 1458 long. All 32-bit instructions have a major opcode whose top 1459 two bits are 11; all the rest are 16-bit instructions. */ 1460 if ((*insn & 0xc0000000) == 0xc0000000) 1461 { 1462 /* Fetch the second 16-bit part of the instruction. */ 1463 read_memory (pc + 2, buf, sizeof (buf)); 1464 *insn = *insn | extract_unsigned_integer (buf, 2, byte_order); 1465 } 1466 1467 /* If we're in VLIW code, then the VLIW width determines the address 1468 of the next instruction. */ 1469 if (vliw_mode) 1470 { 1471 /* In 32-bit VLIW code, all bundles are 32 bits long. We ignore the 1472 coprocessor half of a core / copro bundle. */ 1473 if (vliw_mode == MEP_OPT_VL32) 1474 insn_len = 4; 1475 1476 /* In 64-bit VLIW code, all bundles are 64 bits long. We ignore the 1477 coprocessor half of a core / copro bundle. */ 1478 else if (vliw_mode == MEP_OPT_VL64) 1479 insn_len = 8; 1480 1481 /* We'd better be in either core, 32-bit VLIW, or 64-bit VLIW mode. */ 1482 else 1483 gdb_assert_not_reached ("unexpected vliw mode"); 1484 } 1485 1486 /* Otherwise, the top two bits of the major opcode are (again) what 1487 we need to check. */ 1488 else if ((*insn & 0xc0000000) == 0xc0000000) 1489 insn_len = 4; 1490 else 1491 insn_len = 2; 1492 1493 return pc + insn_len; 1494 } 1495 1496 1497 /* Sign-extend the LEN-bit value N. */ 1498 #define SEXT(n, len) ((((int) (n)) ^ (1 << ((len) - 1))) - (1 << ((len) - 1))) 1499 1500 /* Return the LEN-bit field at POS from I. */ 1501 #define FIELD(i, pos, len) (((i) >> (pos)) & ((1 << (len)) - 1)) 1502 1503 /* Like FIELD, but sign-extend the field's value. */ 1504 #define SFIELD(i, pos, len) (SEXT (FIELD ((i), (pos), (len)), (len))) 1505 1506 1507 /* Macros for decoding instructions. 1508 1509 Remember that 16-bit instructions are placed in bits 16..31 of i, 1510 not at the least significant end; this means that the major opcode 1511 field is always in the same place, regardless of the width of the 1512 instruction. As a reminder of this, we show the lower 16 bits of a 1513 16-bit instruction as xxxx_xxxx_xxxx_xxxx. */ 1514 1515 /* SB Rn,(Rm) 0000_nnnn_mmmm_1000 */ 1516 /* SH Rn,(Rm) 0000_nnnn_mmmm_1001 */ 1517 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 */ 1518 1519 /* SW Rn,disp16(Rm) 1100_nnnn_mmmm_1010 dddd_dddd_dddd_dddd */ 1520 #define IS_SW(i) (((i) & 0xf00f0000) == 0xc00a0000) 1521 /* SB Rn,disp16(Rm) 1100_nnnn_mmmm_1000 dddd_dddd_dddd_dddd */ 1522 #define IS_SB(i) (((i) & 0xf00f0000) == 0xc0080000) 1523 /* SH Rn,disp16(Rm) 1100_nnnn_mmmm_1001 dddd_dddd_dddd_dddd */ 1524 #define IS_SH(i) (((i) & 0xf00f0000) == 0xc0090000) 1525 #define SWBH_32_BASE(i) (FIELD (i, 20, 4)) 1526 #define SWBH_32_SOURCE(i) (FIELD (i, 24, 4)) 1527 #define SWBH_32_OFFSET(i) (SFIELD (i, 0, 16)) 1528 1529 /* SW Rn,disp7.align4(SP) 0100_nnnn_0ddd_dd10 xxxx_xxxx_xxxx_xxxx */ 1530 #define IS_SW_IMMD(i) (((i) & 0xf0830000) == 0x40020000) 1531 #define SW_IMMD_SOURCE(i) (FIELD (i, 24, 4)) 1532 #define SW_IMMD_OFFSET(i) (FIELD (i, 18, 5) << 2) 1533 1534 /* SW Rn,(Rm) 0000_nnnn_mmmm_1010 xxxx_xxxx_xxxx_xxxx */ 1535 #define IS_SW_REG(i) (((i) & 0xf00f0000) == 0x000a0000) 1536 #define SW_REG_SOURCE(i) (FIELD (i, 24, 4)) 1537 #define SW_REG_BASE(i) (FIELD (i, 20, 4)) 1538 1539 /* ADD3 Rl,Rn,Rm 1001_nnnn_mmmm_llll xxxx_xxxx_xxxx_xxxx */ 1540 #define IS_ADD3_16_REG(i) (((i) & 0xf0000000) == 0x90000000) 1541 #define ADD3_16_REG_SRC1(i) (FIELD (i, 20, 4)) /* n */ 1542 #define ADD3_16_REG_SRC2(i) (FIELD (i, 24, 4)) /* m */ 1543 1544 /* ADD3 Rn,Rm,imm16 1100_nnnn_mmmm_0000 iiii_iiii_iiii_iiii */ 1545 #define IS_ADD3_32(i) (((i) & 0xf00f0000) == 0xc0000000) 1546 #define ADD3_32_TARGET(i) (FIELD (i, 24, 4)) 1547 #define ADD3_32_SOURCE(i) (FIELD (i, 20, 4)) 1548 #define ADD3_32_OFFSET(i) (SFIELD (i, 0, 16)) 1549 1550 /* ADD3 Rn,SP,imm7.align4 0100_nnnn_0iii_ii00 xxxx_xxxx_xxxx_xxxx */ 1551 #define IS_ADD3_16(i) (((i) & 0xf0830000) == 0x40000000) 1552 #define ADD3_16_TARGET(i) (FIELD (i, 24, 4)) 1553 #define ADD3_16_OFFSET(i) (FIELD (i, 18, 5) << 2) 1554 1555 /* ADD Rn,imm6 0110_nnnn_iiii_ii00 xxxx_xxxx_xxxx_xxxx */ 1556 #define IS_ADD(i) (((i) & 0xf0030000) == 0x60000000) 1557 #define ADD_TARGET(i) (FIELD (i, 24, 4)) 1558 #define ADD_OFFSET(i) (SFIELD (i, 18, 6)) 1559 1560 /* LDC Rn,imm5 0111_nnnn_iiii_101I xxxx_xxxx_xxxx_xxxx 1561 imm5 = I||i[7:4] */ 1562 #define IS_LDC(i) (((i) & 0xf00e0000) == 0x700a0000) 1563 #define LDC_IMM(i) ((FIELD (i, 16, 1) << 4) | FIELD (i, 20, 4)) 1564 #define LDC_TARGET(i) (FIELD (i, 24, 4)) 1565 1566 /* LW Rn,disp16(Rm) 1100_nnnn_mmmm_1110 dddd_dddd_dddd_dddd */ 1567 #define IS_LW(i) (((i) & 0xf00f0000) == 0xc00e0000) 1568 #define LW_TARGET(i) (FIELD (i, 24, 4)) 1569 #define LW_BASE(i) (FIELD (i, 20, 4)) 1570 #define LW_OFFSET(i) (SFIELD (i, 0, 16)) 1571 1572 /* MOV Rn,Rm 0000_nnnn_mmmm_0000 xxxx_xxxx_xxxx_xxxx */ 1573 #define IS_MOV(i) (((i) & 0xf00f0000) == 0x00000000) 1574 #define MOV_TARGET(i) (FIELD (i, 24, 4)) 1575 #define MOV_SOURCE(i) (FIELD (i, 20, 4)) 1576 1577 /* BRA disp12.align2 1011_dddd_dddd_ddd0 xxxx_xxxx_xxxx_xxxx */ 1578 #define IS_BRA(i) (((i) & 0xf0010000) == 0xb0000000) 1579 #define BRA_DISP(i) (SFIELD (i, 17, 11) << 1) 1580 1581 1582 /* This structure holds the results of a prologue analysis. */ 1583 struct mep_prologue 1584 { 1585 /* The architecture for which we generated this prologue info. */ 1586 struct gdbarch *gdbarch; 1587 1588 /* The offset from the frame base to the stack pointer --- always 1589 zero or negative. 1590 1591 Calling this a "size" is a bit misleading, but given that the 1592 stack grows downwards, using offsets for everything keeps one 1593 from going completely sign-crazy: you never change anything's 1594 sign for an ADD instruction; always change the second operand's 1595 sign for a SUB instruction; and everything takes care of 1596 itself. */ 1597 int frame_size; 1598 1599 /* Non-zero if this function has initialized the frame pointer from 1600 the stack pointer, zero otherwise. */ 1601 int has_frame_ptr; 1602 1603 /* If has_frame_ptr is non-zero, this is the offset from the frame 1604 base to where the frame pointer points. This is always zero or 1605 negative. */ 1606 int frame_ptr_offset; 1607 1608 /* The address of the first instruction at which the frame has been 1609 set up and the arguments are where the debug info says they are 1610 --- as best as we can tell. */ 1611 CORE_ADDR prologue_end; 1612 1613 /* reg_offset[R] is the offset from the CFA at which register R is 1614 saved, or 1 if register R has not been saved. (Real values are 1615 always zero or negative.) */ 1616 int reg_offset[MEP_NUM_REGS]; 1617 }; 1618 1619 /* Return non-zero if VALUE is an incoming argument register. */ 1620 1621 static int 1622 is_arg_reg (pv_t value) 1623 { 1624 return (value.kind == pvk_register 1625 && MEP_R1_REGNUM <= value.reg && value.reg <= MEP_R4_REGNUM 1626 && value.k == 0); 1627 } 1628 1629 /* Return non-zero if a store of REG's current value VALUE to ADDR is 1630 probably spilling an argument register to its stack slot in STACK. 1631 Such instructions should be included in the prologue, if possible. 1632 1633 The store is a spill if: 1634 - the value being stored is REG's original value; 1635 - the value has not already been stored somewhere in STACK; and 1636 - ADDR is a stack slot's address (e.g., relative to the original 1637 value of the SP). */ 1638 static int 1639 is_arg_spill (struct gdbarch *gdbarch, pv_t value, pv_t addr, 1640 struct pv_area *stack) 1641 { 1642 return (is_arg_reg (value) 1643 && pv_is_register (addr, MEP_SP_REGNUM) 1644 && ! pv_area_find_reg (stack, gdbarch, value.reg, 0)); 1645 } 1646 1647 1648 /* Function for finding saved registers in a 'struct pv_area'; we pass 1649 this to pv_area_scan. 1650 1651 If VALUE is a saved register, ADDR says it was saved at a constant 1652 offset from the frame base, and SIZE indicates that the whole 1653 register was saved, record its offset in RESULT_UNTYPED. */ 1654 static void 1655 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size, pv_t value) 1656 { 1657 struct mep_prologue *result = (struct mep_prologue *) result_untyped; 1658 1659 if (value.kind == pvk_register 1660 && value.k == 0 1661 && pv_is_register (addr, MEP_SP_REGNUM) 1662 && size == register_size (result->gdbarch, value.reg)) 1663 result->reg_offset[value.reg] = addr.k; 1664 } 1665 1666 1667 /* Analyze a prologue starting at START_PC, going no further than 1668 LIMIT_PC. Fill in RESULT as appropriate. */ 1669 static void 1670 mep_analyze_prologue (struct gdbarch *gdbarch, 1671 CORE_ADDR start_pc, CORE_ADDR limit_pc, 1672 struct mep_prologue *result) 1673 { 1674 CORE_ADDR pc; 1675 unsigned long insn; 1676 int rn; 1677 int found_lp = 0; 1678 pv_t reg[MEP_NUM_REGS]; 1679 struct pv_area *stack; 1680 struct cleanup *back_to; 1681 CORE_ADDR after_last_frame_setup_insn = start_pc; 1682 1683 memset (result, 0, sizeof (*result)); 1684 result->gdbarch = gdbarch; 1685 1686 for (rn = 0; rn < MEP_NUM_REGS; rn++) 1687 { 1688 reg[rn] = pv_register (rn, 0); 1689 result->reg_offset[rn] = 1; 1690 } 1691 1692 stack = make_pv_area (MEP_SP_REGNUM, gdbarch_addr_bit (gdbarch)); 1693 back_to = make_cleanup_free_pv_area (stack); 1694 1695 pc = start_pc; 1696 while (pc < limit_pc) 1697 { 1698 CORE_ADDR next_pc; 1699 pv_t pre_insn_fp, pre_insn_sp; 1700 1701 next_pc = mep_get_insn (gdbarch, pc, &insn); 1702 1703 /* A zero return from mep_get_insn means that either we weren't 1704 able to read the instruction from memory, or that we don't 1705 have enough information to be able to reliably decode it. So 1706 we'll store here and hope for the best. */ 1707 if (! next_pc) 1708 break; 1709 1710 /* Note the current values of the SP and FP, so we can tell if 1711 this instruction changed them, below. */ 1712 pre_insn_fp = reg[MEP_FP_REGNUM]; 1713 pre_insn_sp = reg[MEP_SP_REGNUM]; 1714 1715 if (IS_ADD (insn)) 1716 { 1717 int rn = ADD_TARGET (insn); 1718 CORE_ADDR imm6 = ADD_OFFSET (insn); 1719 1720 reg[rn] = pv_add_constant (reg[rn], imm6); 1721 } 1722 else if (IS_ADD3_16 (insn)) 1723 { 1724 int rn = ADD3_16_TARGET (insn); 1725 int imm7 = ADD3_16_OFFSET (insn); 1726 1727 reg[rn] = pv_add_constant (reg[MEP_SP_REGNUM], imm7); 1728 } 1729 else if (IS_ADD3_32 (insn)) 1730 { 1731 int rn = ADD3_32_TARGET (insn); 1732 int rm = ADD3_32_SOURCE (insn); 1733 int imm16 = ADD3_32_OFFSET (insn); 1734 1735 reg[rn] = pv_add_constant (reg[rm], imm16); 1736 } 1737 else if (IS_SW_REG (insn)) 1738 { 1739 int rn = SW_REG_SOURCE (insn); 1740 int rm = SW_REG_BASE (insn); 1741 1742 /* If simulating this store would require us to forget 1743 everything we know about the stack frame in the name of 1744 accuracy, it would be better to just quit now. */ 1745 if (pv_area_store_would_trash (stack, reg[rm])) 1746 break; 1747 1748 if (is_arg_spill (gdbarch, reg[rn], reg[rm], stack)) 1749 after_last_frame_setup_insn = next_pc; 1750 1751 pv_area_store (stack, reg[rm], 4, reg[rn]); 1752 } 1753 else if (IS_SW_IMMD (insn)) 1754 { 1755 int rn = SW_IMMD_SOURCE (insn); 1756 int offset = SW_IMMD_OFFSET (insn); 1757 pv_t addr = pv_add_constant (reg[MEP_SP_REGNUM], offset); 1758 1759 /* If simulating this store would require us to forget 1760 everything we know about the stack frame in the name of 1761 accuracy, it would be better to just quit now. */ 1762 if (pv_area_store_would_trash (stack, addr)) 1763 break; 1764 1765 if (is_arg_spill (gdbarch, reg[rn], addr, stack)) 1766 after_last_frame_setup_insn = next_pc; 1767 1768 pv_area_store (stack, addr, 4, reg[rn]); 1769 } 1770 else if (IS_MOV (insn)) 1771 { 1772 int rn = MOV_TARGET (insn); 1773 int rm = MOV_SOURCE (insn); 1774 1775 reg[rn] = reg[rm]; 1776 1777 if (pv_is_register (reg[rm], rm) && is_arg_reg (reg[rm])) 1778 after_last_frame_setup_insn = next_pc; 1779 } 1780 else if (IS_SB (insn) || IS_SH (insn) || IS_SW (insn)) 1781 { 1782 int rn = SWBH_32_SOURCE (insn); 1783 int rm = SWBH_32_BASE (insn); 1784 int disp = SWBH_32_OFFSET (insn); 1785 int size = (IS_SB (insn) ? 1 1786 : IS_SH (insn) ? 2 1787 : (gdb_assert (IS_SW (insn)), 4)); 1788 pv_t addr = pv_add_constant (reg[rm], disp); 1789 1790 if (pv_area_store_would_trash (stack, addr)) 1791 break; 1792 1793 if (is_arg_spill (gdbarch, reg[rn], addr, stack)) 1794 after_last_frame_setup_insn = next_pc; 1795 1796 pv_area_store (stack, addr, size, reg[rn]); 1797 } 1798 else if (IS_LDC (insn)) 1799 { 1800 int rn = LDC_TARGET (insn); 1801 int cr = LDC_IMM (insn) + MEP_FIRST_CSR_REGNUM; 1802 1803 reg[rn] = reg[cr]; 1804 } 1805 else if (IS_LW (insn)) 1806 { 1807 int rn = LW_TARGET (insn); 1808 int rm = LW_BASE (insn); 1809 int offset = LW_OFFSET (insn); 1810 pv_t addr = pv_add_constant (reg[rm], offset); 1811 1812 reg[rn] = pv_area_fetch (stack, addr, 4); 1813 } 1814 else if (IS_BRA (insn) && BRA_DISP (insn) > 0) 1815 { 1816 /* When a loop appears as the first statement of a function 1817 body, gcc 4.x will use a BRA instruction to branch to the 1818 loop condition checking code. This BRA instruction is 1819 marked as part of the prologue. We therefore set next_pc 1820 to this branch target and also stop the prologue scan. 1821 The instructions at and beyond the branch target should 1822 no longer be associated with the prologue. 1823 1824 Note that we only consider forward branches here. We 1825 presume that a forward branch is being used to skip over 1826 a loop body. 1827 1828 A backwards branch is covered by the default case below. 1829 If we were to encounter a backwards branch, that would 1830 most likely mean that we've scanned through a loop body. 1831 We definitely want to stop the prologue scan when this 1832 happens and that is precisely what is done by the default 1833 case below. */ 1834 next_pc = pc + BRA_DISP (insn); 1835 after_last_frame_setup_insn = next_pc; 1836 break; 1837 } 1838 else 1839 /* We've hit some instruction we don't know how to simulate. 1840 Strictly speaking, we should set every value we're 1841 tracking to "unknown". But we'll be optimistic, assume 1842 that we have enough information already, and stop 1843 analysis here. */ 1844 break; 1845 1846 /* If this instruction changed the FP or decreased the SP (i.e., 1847 allocated more stack space), then this may be a good place to 1848 declare the prologue finished. However, there are some 1849 exceptions: 1850 1851 - If the instruction just changed the FP back to its original 1852 value, then that's probably a restore instruction. The 1853 prologue should definitely end before that. 1854 1855 - If the instruction increased the value of the SP (that is, 1856 shrunk the frame), then it's probably part of a frame 1857 teardown sequence, and the prologue should end before that. */ 1858 1859 if (! pv_is_identical (reg[MEP_FP_REGNUM], pre_insn_fp)) 1860 { 1861 if (! pv_is_register_k (reg[MEP_FP_REGNUM], MEP_FP_REGNUM, 0)) 1862 after_last_frame_setup_insn = next_pc; 1863 } 1864 else if (! pv_is_identical (reg[MEP_SP_REGNUM], pre_insn_sp)) 1865 { 1866 /* The comparison of constants looks odd, there, because .k 1867 is unsigned. All it really means is that the new value 1868 is lower than it was before the instruction. */ 1869 if (pv_is_register (pre_insn_sp, MEP_SP_REGNUM) 1870 && pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM) 1871 && ((pre_insn_sp.k - reg[MEP_SP_REGNUM].k) 1872 < (reg[MEP_SP_REGNUM].k - pre_insn_sp.k))) 1873 after_last_frame_setup_insn = next_pc; 1874 } 1875 1876 pc = next_pc; 1877 } 1878 1879 /* Is the frame size (offset, really) a known constant? */ 1880 if (pv_is_register (reg[MEP_SP_REGNUM], MEP_SP_REGNUM)) 1881 result->frame_size = reg[MEP_SP_REGNUM].k; 1882 1883 /* Was the frame pointer initialized? */ 1884 if (pv_is_register (reg[MEP_FP_REGNUM], MEP_SP_REGNUM)) 1885 { 1886 result->has_frame_ptr = 1; 1887 result->frame_ptr_offset = reg[MEP_FP_REGNUM].k; 1888 } 1889 1890 /* Record where all the registers were saved. */ 1891 pv_area_scan (stack, check_for_saved, (void *) result); 1892 1893 result->prologue_end = after_last_frame_setup_insn; 1894 1895 do_cleanups (back_to); 1896 } 1897 1898 1899 static CORE_ADDR 1900 mep_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) 1901 { 1902 const char *name; 1903 CORE_ADDR func_addr, func_end; 1904 struct mep_prologue p; 1905 1906 /* Try to find the extent of the function that contains PC. */ 1907 if (! find_pc_partial_function (pc, &name, &func_addr, &func_end)) 1908 return pc; 1909 1910 mep_analyze_prologue (gdbarch, pc, func_end, &p); 1911 return p.prologue_end; 1912 } 1913 1914 1915 1916 /* Breakpoints. */ 1917 constexpr gdb_byte mep_break_insn[] = { 0x70, 0x32 }; 1918 1919 typedef BP_MANIPULATION (mep_break_insn) mep_breakpoint; 1920 1921 1922 /* Frames and frame unwinding. */ 1923 1924 1925 static struct mep_prologue * 1926 mep_analyze_frame_prologue (struct frame_info *this_frame, 1927 void **this_prologue_cache) 1928 { 1929 if (! *this_prologue_cache) 1930 { 1931 CORE_ADDR func_start, stop_addr; 1932 1933 *this_prologue_cache 1934 = FRAME_OBSTACK_ZALLOC (struct mep_prologue); 1935 1936 func_start = get_frame_func (this_frame); 1937 stop_addr = get_frame_pc (this_frame); 1938 1939 /* If we couldn't find any function containing the PC, then 1940 just initialize the prologue cache, but don't do anything. */ 1941 if (! func_start) 1942 stop_addr = func_start; 1943 1944 mep_analyze_prologue (get_frame_arch (this_frame), 1945 func_start, stop_addr, 1946 (struct mep_prologue *) *this_prologue_cache); 1947 } 1948 1949 return (struct mep_prologue *) *this_prologue_cache; 1950 } 1951 1952 1953 /* Given the next frame and a prologue cache, return this frame's 1954 base. */ 1955 static CORE_ADDR 1956 mep_frame_base (struct frame_info *this_frame, 1957 void **this_prologue_cache) 1958 { 1959 struct mep_prologue *p 1960 = mep_analyze_frame_prologue (this_frame, this_prologue_cache); 1961 1962 /* In functions that use alloca, the distance between the stack 1963 pointer and the frame base varies dynamically, so we can't use 1964 the SP plus static information like prologue analysis to find the 1965 frame base. However, such functions must have a frame pointer, 1966 to be able to restore the SP on exit. So whenever we do have a 1967 frame pointer, use that to find the base. */ 1968 if (p->has_frame_ptr) 1969 { 1970 CORE_ADDR fp 1971 = get_frame_register_unsigned (this_frame, MEP_FP_REGNUM); 1972 return fp - p->frame_ptr_offset; 1973 } 1974 else 1975 { 1976 CORE_ADDR sp 1977 = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM); 1978 return sp - p->frame_size; 1979 } 1980 } 1981 1982 1983 static void 1984 mep_frame_this_id (struct frame_info *this_frame, 1985 void **this_prologue_cache, 1986 struct frame_id *this_id) 1987 { 1988 *this_id = frame_id_build (mep_frame_base (this_frame, this_prologue_cache), 1989 get_frame_func (this_frame)); 1990 } 1991 1992 1993 static struct value * 1994 mep_frame_prev_register (struct frame_info *this_frame, 1995 void **this_prologue_cache, int regnum) 1996 { 1997 struct mep_prologue *p 1998 = mep_analyze_frame_prologue (this_frame, this_prologue_cache); 1999 2000 /* There are a number of complications in unwinding registers on the 2001 MeP, having to do with core functions calling VLIW functions and 2002 vice versa. 2003 2004 The least significant bit of the link register, LP.LTOM, is the 2005 VLIW mode toggle bit: it's set if a core function called a VLIW 2006 function, or vice versa, and clear when the caller and callee 2007 were both in the same mode. 2008 2009 So, if we're asked to unwind the PC, then we really want to 2010 unwind the LP and clear the least significant bit. (Real return 2011 addresses are always even.) And if we want to unwind the program 2012 status word (PSW), we need to toggle PSW.OM if LP.LTOM is set. 2013 2014 Tweaking the register values we return in this way means that the 2015 bits in BUFFERP[] are not the same as the bits you'd find at 2016 ADDRP in the inferior, so we make sure lvalp is not_lval when we 2017 do this. */ 2018 if (regnum == MEP_PC_REGNUM) 2019 { 2020 struct value *value; 2021 CORE_ADDR lp; 2022 value = mep_frame_prev_register (this_frame, this_prologue_cache, 2023 MEP_LP_REGNUM); 2024 lp = value_as_long (value); 2025 release_value (value); 2026 value_free (value); 2027 2028 return frame_unwind_got_constant (this_frame, regnum, lp & ~1); 2029 } 2030 else 2031 { 2032 CORE_ADDR frame_base = mep_frame_base (this_frame, this_prologue_cache); 2033 struct value *value; 2034 2035 /* Our caller's SP is our frame base. */ 2036 if (regnum == MEP_SP_REGNUM) 2037 return frame_unwind_got_constant (this_frame, regnum, frame_base); 2038 2039 /* If prologue analysis says we saved this register somewhere, 2040 return a description of the stack slot holding it. */ 2041 if (p->reg_offset[regnum] != 1) 2042 value = frame_unwind_got_memory (this_frame, regnum, 2043 frame_base + p->reg_offset[regnum]); 2044 2045 /* Otherwise, presume we haven't changed the value of this 2046 register, and get it from the next frame. */ 2047 else 2048 value = frame_unwind_got_register (this_frame, regnum, regnum); 2049 2050 /* If we need to toggle the operating mode, do so. */ 2051 if (regnum == MEP_PSW_REGNUM) 2052 { 2053 CORE_ADDR psw, lp; 2054 2055 psw = value_as_long (value); 2056 release_value (value); 2057 value_free (value); 2058 2059 /* Get the LP's value, too. */ 2060 value = get_frame_register_value (this_frame, MEP_LP_REGNUM); 2061 lp = value_as_long (value); 2062 release_value (value); 2063 value_free (value); 2064 2065 /* If LP.LTOM is set, then toggle PSW.OM. */ 2066 if (lp & 0x1) 2067 psw ^= 0x1000; 2068 2069 return frame_unwind_got_constant (this_frame, regnum, psw); 2070 } 2071 2072 return value; 2073 } 2074 } 2075 2076 2077 static const struct frame_unwind mep_frame_unwind = { 2078 NORMAL_FRAME, 2079 default_frame_unwind_stop_reason, 2080 mep_frame_this_id, 2081 mep_frame_prev_register, 2082 NULL, 2083 default_frame_sniffer 2084 }; 2085 2086 2087 /* Our general unwinding function can handle unwinding the PC. */ 2088 static CORE_ADDR 2089 mep_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 2090 { 2091 return frame_unwind_register_unsigned (next_frame, MEP_PC_REGNUM); 2092 } 2093 2094 2095 /* Our general unwinding function can handle unwinding the SP. */ 2096 static CORE_ADDR 2097 mep_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 2098 { 2099 return frame_unwind_register_unsigned (next_frame, MEP_SP_REGNUM); 2100 } 2101 2102 2103 2104 /* Return values. */ 2105 2106 2107 static int 2108 mep_use_struct_convention (struct type *type) 2109 { 2110 return (TYPE_LENGTH (type) > MEP_GPR_SIZE); 2111 } 2112 2113 2114 static void 2115 mep_extract_return_value (struct gdbarch *arch, 2116 struct type *type, 2117 struct regcache *regcache, 2118 gdb_byte *valbuf) 2119 { 2120 int byte_order = gdbarch_byte_order (arch); 2121 2122 /* Values that don't occupy a full register appear at the less 2123 significant end of the value. This is the offset to where the 2124 value starts. */ 2125 int offset; 2126 2127 /* Return values > MEP_GPR_SIZE bytes are returned in memory, 2128 pointed to by R0. */ 2129 gdb_assert (TYPE_LENGTH (type) <= MEP_GPR_SIZE); 2130 2131 if (byte_order == BFD_ENDIAN_BIG) 2132 offset = MEP_GPR_SIZE - TYPE_LENGTH (type); 2133 else 2134 offset = 0; 2135 2136 /* Return values that do fit in a single register are returned in R0. */ 2137 regcache_cooked_read_part (regcache, MEP_R0_REGNUM, 2138 offset, TYPE_LENGTH (type), 2139 valbuf); 2140 } 2141 2142 2143 static void 2144 mep_store_return_value (struct gdbarch *arch, 2145 struct type *type, 2146 struct regcache *regcache, 2147 const gdb_byte *valbuf) 2148 { 2149 int byte_order = gdbarch_byte_order (arch); 2150 2151 /* Values that fit in a single register go in R0. */ 2152 if (TYPE_LENGTH (type) <= MEP_GPR_SIZE) 2153 { 2154 /* Values that don't occupy a full register appear at the least 2155 significant end of the value. This is the offset to where the 2156 value starts. */ 2157 int offset; 2158 2159 if (byte_order == BFD_ENDIAN_BIG) 2160 offset = MEP_GPR_SIZE - TYPE_LENGTH (type); 2161 else 2162 offset = 0; 2163 2164 regcache_cooked_write_part (regcache, MEP_R0_REGNUM, 2165 offset, TYPE_LENGTH (type), 2166 valbuf); 2167 } 2168 2169 /* Return values larger than a single register are returned in 2170 memory, pointed to by R0. Unfortunately, we can't count on R0 2171 pointing to the return buffer, so we raise an error here. */ 2172 else 2173 error (_("\ 2174 GDB cannot set return values larger than four bytes; the Media Processor's\n\ 2175 calling conventions do not provide enough information to do this.\n\ 2176 Try using the 'return' command with no argument.")); 2177 } 2178 2179 static enum return_value_convention 2180 mep_return_value (struct gdbarch *gdbarch, struct value *function, 2181 struct type *type, struct regcache *regcache, 2182 gdb_byte *readbuf, const gdb_byte *writebuf) 2183 { 2184 if (mep_use_struct_convention (type)) 2185 { 2186 if (readbuf) 2187 { 2188 ULONGEST addr; 2189 /* Although the address of the struct buffer gets passed in R1, it's 2190 returned in R0. Fetch R0's value and then read the memory 2191 at that address. */ 2192 regcache_raw_read_unsigned (regcache, MEP_R0_REGNUM, &addr); 2193 read_memory (addr, readbuf, TYPE_LENGTH (type)); 2194 } 2195 if (writebuf) 2196 { 2197 /* Return values larger than a single register are returned in 2198 memory, pointed to by R0. Unfortunately, we can't count on R0 2199 pointing to the return buffer, so we raise an error here. */ 2200 error (_("\ 2201 GDB cannot set return values larger than four bytes; the Media Processor's\n\ 2202 calling conventions do not provide enough information to do this.\n\ 2203 Try using the 'return' command with no argument.")); 2204 } 2205 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 2206 } 2207 2208 if (readbuf) 2209 mep_extract_return_value (gdbarch, type, regcache, readbuf); 2210 if (writebuf) 2211 mep_store_return_value (gdbarch, type, regcache, writebuf); 2212 2213 return RETURN_VALUE_REGISTER_CONVENTION; 2214 } 2215 2216 2217 /* Inferior calls. */ 2218 2219 2220 static CORE_ADDR 2221 mep_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 2222 { 2223 /* Require word alignment. */ 2224 return sp & -4; 2225 } 2226 2227 2228 /* From "lang_spec2.txt": 2229 2230 4.2 Calling conventions 2231 2232 4.2.1 Core register conventions 2233 2234 - Parameters should be evaluated from left to right, and they 2235 should be held in $1,$2,$3,$4 in order. The fifth parameter or 2236 after should be held in the stack. If the size is larger than 4 2237 bytes in the first four parameters, the pointer should be held in 2238 the registers instead. If the size is larger than 4 bytes in the 2239 fifth parameter or after, the pointer should be held in the stack. 2240 2241 - Return value of a function should be held in register $0. If the 2242 size of return value is larger than 4 bytes, $1 should hold the 2243 pointer pointing memory that would hold the return value. In this 2244 case, the first parameter should be held in $2, the second one in 2245 $3, and the third one in $4, and the forth parameter or after 2246 should be held in the stack. 2247 2248 [This doesn't say so, but arguments shorter than four bytes are 2249 passed in the least significant end of a four-byte word when 2250 they're passed on the stack.] */ 2251 2252 2253 /* Traverse the list of ARGC arguments ARGV; for every ARGV[i] too 2254 large to fit in a register, save it on the stack, and place its 2255 address in COPY[i]. SP is the initial stack pointer; return the 2256 new stack pointer. */ 2257 static CORE_ADDR 2258 push_large_arguments (CORE_ADDR sp, int argc, struct value **argv, 2259 CORE_ADDR copy[]) 2260 { 2261 int i; 2262 2263 for (i = 0; i < argc; i++) 2264 { 2265 unsigned arg_len = TYPE_LENGTH (value_type (argv[i])); 2266 2267 if (arg_len > MEP_GPR_SIZE) 2268 { 2269 /* Reserve space for the copy, and then round the SP down, to 2270 make sure it's all aligned properly. */ 2271 sp = (sp - arg_len) & -4; 2272 write_memory (sp, value_contents (argv[i]), arg_len); 2273 copy[i] = sp; 2274 } 2275 } 2276 2277 return sp; 2278 } 2279 2280 2281 static CORE_ADDR 2282 mep_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 2283 struct regcache *regcache, CORE_ADDR bp_addr, 2284 int argc, struct value **argv, CORE_ADDR sp, 2285 int struct_return, 2286 CORE_ADDR struct_addr) 2287 { 2288 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 2289 CORE_ADDR *copy = (CORE_ADDR *) alloca (argc * sizeof (copy[0])); 2290 CORE_ADDR func_addr = find_function_addr (function, NULL); 2291 int i; 2292 2293 /* The number of the next register available to hold an argument. */ 2294 int arg_reg; 2295 2296 /* The address of the next stack slot available to hold an argument. */ 2297 CORE_ADDR arg_stack; 2298 2299 /* The address of the end of the stack area for arguments. This is 2300 just for error checking. */ 2301 CORE_ADDR arg_stack_end; 2302 2303 sp = push_large_arguments (sp, argc, argv, copy); 2304 2305 /* Reserve space for the stack arguments, if any. */ 2306 arg_stack_end = sp; 2307 if (argc + (struct_addr ? 1 : 0) > 4) 2308 sp -= ((argc + (struct_addr ? 1 : 0)) - 4) * MEP_GPR_SIZE; 2309 2310 arg_reg = MEP_R1_REGNUM; 2311 arg_stack = sp; 2312 2313 /* If we're returning a structure by value, push the pointer to the 2314 buffer as the first argument. */ 2315 if (struct_return) 2316 { 2317 regcache_cooked_write_unsigned (regcache, arg_reg, struct_addr); 2318 arg_reg++; 2319 } 2320 2321 for (i = 0; i < argc; i++) 2322 { 2323 ULONGEST value; 2324 2325 /* Arguments that fit in a GPR get expanded to fill the GPR. */ 2326 if (TYPE_LENGTH (value_type (argv[i])) <= MEP_GPR_SIZE) 2327 value = extract_unsigned_integer (value_contents (argv[i]), 2328 TYPE_LENGTH (value_type (argv[i])), 2329 byte_order); 2330 2331 /* Arguments too large to fit in a GPR get copied to the stack, 2332 and we pass a pointer to the copy. */ 2333 else 2334 value = copy[i]; 2335 2336 /* We use $1 -- $4 for passing arguments, then use the stack. */ 2337 if (arg_reg <= MEP_R4_REGNUM) 2338 { 2339 regcache_cooked_write_unsigned (regcache, arg_reg, value); 2340 arg_reg++; 2341 } 2342 else 2343 { 2344 gdb_byte buf[MEP_GPR_SIZE]; 2345 store_unsigned_integer (buf, MEP_GPR_SIZE, byte_order, value); 2346 write_memory (arg_stack, buf, MEP_GPR_SIZE); 2347 arg_stack += MEP_GPR_SIZE; 2348 } 2349 } 2350 2351 gdb_assert (arg_stack <= arg_stack_end); 2352 2353 /* Set the return address. */ 2354 regcache_cooked_write_unsigned (regcache, MEP_LP_REGNUM, bp_addr); 2355 2356 /* Update the stack pointer. */ 2357 regcache_cooked_write_unsigned (regcache, MEP_SP_REGNUM, sp); 2358 2359 return sp; 2360 } 2361 2362 2363 static struct frame_id 2364 mep_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame) 2365 { 2366 CORE_ADDR sp = get_frame_register_unsigned (this_frame, MEP_SP_REGNUM); 2367 return frame_id_build (sp, get_frame_pc (this_frame)); 2368 } 2369 2370 2371 2372 /* Initialization. */ 2373 2374 2375 static struct gdbarch * 2376 mep_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 2377 { 2378 struct gdbarch *gdbarch; 2379 struct gdbarch_tdep *tdep; 2380 2381 /* Which me_module are we building a gdbarch object for? */ 2382 CONFIG_ATTR me_module; 2383 2384 /* If we have a BFD in hand, figure out which me_module it was built 2385 for. Otherwise, use the no-particular-me_module code. */ 2386 if (info.abfd) 2387 { 2388 /* The way to get the me_module code depends on the object file 2389 format. At the moment, we only know how to handle ELF. */ 2390 if (bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) 2391 { 2392 int flag = elf_elfheader (info.abfd)->e_flags & EF_MEP_INDEX_MASK; 2393 me_module = (CONFIG_ATTR) flag; 2394 } 2395 else 2396 me_module = CONFIG_NONE; 2397 } 2398 else 2399 me_module = CONFIG_NONE; 2400 2401 /* If we're setting the architecture from a file, check the 2402 endianness of the file against that of the me_module. */ 2403 if (info.abfd) 2404 { 2405 /* The negations on either side make the comparison treat all 2406 non-zero (true) values as equal. */ 2407 if (! bfd_big_endian (info.abfd) != ! me_module_big_endian (me_module)) 2408 { 2409 const char *module_name = me_module_name (me_module); 2410 const char *module_endianness 2411 = me_module_big_endian (me_module) ? "big" : "little"; 2412 const char *file_name = bfd_get_filename (info.abfd); 2413 const char *file_endianness 2414 = bfd_big_endian (info.abfd) ? "big" : "little"; 2415 2416 fputc_unfiltered ('\n', gdb_stderr); 2417 if (module_name) 2418 warning (_("the MeP module '%s' is %s-endian, but the executable\n" 2419 "%s is %s-endian."), 2420 module_name, module_endianness, 2421 file_name, file_endianness); 2422 else 2423 warning (_("the selected MeP module is %s-endian, but the " 2424 "executable\n" 2425 "%s is %s-endian."), 2426 module_endianness, file_name, file_endianness); 2427 } 2428 } 2429 2430 /* Find a candidate among the list of architectures we've created 2431 already. info->bfd_arch_info needs to match, but we also want 2432 the right me_module: the ELF header's e_flags field needs to 2433 match as well. */ 2434 for (arches = gdbarch_list_lookup_by_info (arches, &info); 2435 arches != NULL; 2436 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 2437 if (gdbarch_tdep (arches->gdbarch)->me_module == me_module) 2438 return arches->gdbarch; 2439 2440 tdep = XNEW (struct gdbarch_tdep); 2441 gdbarch = gdbarch_alloc (&info, tdep); 2442 2443 /* Get a CGEN CPU descriptor for this architecture. */ 2444 { 2445 const char *mach_name = info.bfd_arch_info->printable_name; 2446 enum cgen_endian endian = (info.byte_order == BFD_ENDIAN_BIG 2447 ? CGEN_ENDIAN_BIG 2448 : CGEN_ENDIAN_LITTLE); 2449 2450 tdep->cpu_desc = mep_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name, 2451 CGEN_CPU_OPEN_ENDIAN, endian, 2452 CGEN_CPU_OPEN_END); 2453 } 2454 2455 tdep->me_module = me_module; 2456 2457 /* Register set. */ 2458 set_gdbarch_read_pc (gdbarch, mep_read_pc); 2459 set_gdbarch_num_regs (gdbarch, MEP_NUM_RAW_REGS); 2460 set_gdbarch_pc_regnum (gdbarch, MEP_PC_REGNUM); 2461 set_gdbarch_sp_regnum (gdbarch, MEP_SP_REGNUM); 2462 set_gdbarch_register_name (gdbarch, mep_register_name); 2463 set_gdbarch_register_type (gdbarch, mep_register_type); 2464 set_gdbarch_num_pseudo_regs (gdbarch, MEP_NUM_PSEUDO_REGS); 2465 set_gdbarch_pseudo_register_read (gdbarch, mep_pseudo_register_read); 2466 set_gdbarch_pseudo_register_write (gdbarch, mep_pseudo_register_write); 2467 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); 2468 set_gdbarch_stab_reg_to_regnum (gdbarch, mep_debug_reg_to_regnum); 2469 2470 set_gdbarch_register_reggroup_p (gdbarch, mep_register_reggroup_p); 2471 reggroup_add (gdbarch, all_reggroup); 2472 reggroup_add (gdbarch, general_reggroup); 2473 reggroup_add (gdbarch, save_reggroup); 2474 reggroup_add (gdbarch, restore_reggroup); 2475 reggroup_add (gdbarch, mep_csr_reggroup); 2476 reggroup_add (gdbarch, mep_cr_reggroup); 2477 reggroup_add (gdbarch, mep_ccr_reggroup); 2478 2479 /* Disassembly. */ 2480 set_gdbarch_print_insn (gdbarch, mep_gdb_print_insn); 2481 2482 /* Breakpoints. */ 2483 set_gdbarch_breakpoint_kind_from_pc (gdbarch, mep_breakpoint::kind_from_pc); 2484 set_gdbarch_sw_breakpoint_from_kind (gdbarch, mep_breakpoint::bp_from_kind); 2485 set_gdbarch_decr_pc_after_break (gdbarch, 0); 2486 set_gdbarch_skip_prologue (gdbarch, mep_skip_prologue); 2487 2488 /* Frames and frame unwinding. */ 2489 frame_unwind_append_unwinder (gdbarch, &mep_frame_unwind); 2490 set_gdbarch_unwind_pc (gdbarch, mep_unwind_pc); 2491 set_gdbarch_unwind_sp (gdbarch, mep_unwind_sp); 2492 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 2493 set_gdbarch_frame_args_skip (gdbarch, 0); 2494 2495 /* Return values. */ 2496 set_gdbarch_return_value (gdbarch, mep_return_value); 2497 2498 /* Inferior function calls. */ 2499 set_gdbarch_frame_align (gdbarch, mep_frame_align); 2500 set_gdbarch_push_dummy_call (gdbarch, mep_push_dummy_call); 2501 set_gdbarch_dummy_id (gdbarch, mep_dummy_id); 2502 2503 return gdbarch; 2504 } 2505 2506 /* Provide a prototype to silence -Wmissing-prototypes. */ 2507 extern initialize_file_ftype _initialize_mep_tdep; 2508 2509 void 2510 _initialize_mep_tdep (void) 2511 { 2512 mep_csr_reggroup = reggroup_new ("csr", USER_REGGROUP); 2513 mep_cr_reggroup = reggroup_new ("cr", USER_REGGROUP); 2514 mep_ccr_reggroup = reggroup_new ("ccr", USER_REGGROUP); 2515 2516 register_gdbarch_init (bfd_arch_mep, mep_gdbarch_init); 2517 2518 mep_init_pseudoregister_maps (); 2519 } 2520