1 /* Intel 387 floating point stuff. 2 3 Copyright (C) 1988-2023 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 #include "defs.h" 21 #include "frame.h" 22 #include "gdbcore.h" 23 #include "inferior.h" 24 #include "language.h" 25 #include "regcache.h" 26 #include "target-float.h" 27 #include "value.h" 28 29 #include "i386-tdep.h" 30 #include "i387-tdep.h" 31 #include "gdbsupport/x86-xstate.h" 32 33 /* Print the floating point number specified by RAW. */ 34 35 static void 36 print_i387_value (struct gdbarch *gdbarch, 37 const gdb_byte *raw, struct ui_file *file) 38 { 39 /* We try to print 19 digits. The last digit may or may not contain 40 garbage, but we'd better print one too many. We need enough room 41 to print the value, 1 position for the sign, 1 for the decimal 42 point, 19 for the digits and 6 for the exponent adds up to 27. */ 43 const struct type *type = i387_ext_type (gdbarch); 44 std::string str = target_float_to_string (raw, type, " %-+27.19g"); 45 gdb_printf (file, "%s", str.c_str ()); 46 } 47 48 /* Print the classification for the register contents RAW. */ 49 50 static void 51 print_i387_ext (struct gdbarch *gdbarch, 52 const gdb_byte *raw, struct ui_file *file) 53 { 54 int sign; 55 int integer; 56 unsigned int exponent; 57 unsigned long fraction[2]; 58 59 sign = raw[9] & 0x80; 60 integer = raw[7] & 0x80; 61 exponent = (((raw[9] & 0x7f) << 8) | raw[8]); 62 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); 63 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) 64 | (raw[5] << 8) | raw[4]); 65 66 if (exponent == 0x7fff && integer) 67 { 68 if (fraction[0] == 0x00000000 && fraction[1] == 0x00000000) 69 /* Infinity. */ 70 gdb_printf (file, " %cInf", (sign ? '-' : '+')); 71 else if (sign && fraction[0] == 0x00000000 && fraction[1] == 0x40000000) 72 /* Real Indefinite (QNaN). */ 73 gdb_puts (" Real Indefinite (QNaN)", file); 74 else if (fraction[1] & 0x40000000) 75 /* QNaN. */ 76 gdb_puts (" QNaN", file); 77 else 78 /* SNaN. */ 79 gdb_puts (" SNaN", file); 80 } 81 else if (exponent < 0x7fff && exponent > 0x0000 && integer) 82 /* Normal. */ 83 print_i387_value (gdbarch, raw, file); 84 else if (exponent == 0x0000) 85 { 86 /* Denormal or zero. */ 87 print_i387_value (gdbarch, raw, file); 88 89 if (integer) 90 /* Pseudo-denormal. */ 91 gdb_puts (" Pseudo-denormal", file); 92 else if (fraction[0] || fraction[1]) 93 /* Denormal. */ 94 gdb_puts (" Denormal", file); 95 } 96 else 97 /* Unsupported. */ 98 gdb_puts (" Unsupported", file); 99 } 100 101 /* Print the status word STATUS. If STATUS_P is false, then STATUS 102 was unavailable. */ 103 104 static void 105 print_i387_status_word (int status_p, 106 unsigned int status, struct ui_file *file) 107 { 108 gdb_printf (file, "Status Word: "); 109 if (!status_p) 110 { 111 gdb_printf (file, "%s\n", _("<unavailable>")); 112 return; 113 } 114 115 gdb_printf (file, "%s", hex_string_custom (status, 4)); 116 gdb_puts (" ", file); 117 gdb_printf (file, " %s", (status & 0x0001) ? "IE" : " "); 118 gdb_printf (file, " %s", (status & 0x0002) ? "DE" : " "); 119 gdb_printf (file, " %s", (status & 0x0004) ? "ZE" : " "); 120 gdb_printf (file, " %s", (status & 0x0008) ? "OE" : " "); 121 gdb_printf (file, " %s", (status & 0x0010) ? "UE" : " "); 122 gdb_printf (file, " %s", (status & 0x0020) ? "PE" : " "); 123 gdb_puts (" ", file); 124 gdb_printf (file, " %s", (status & 0x0080) ? "ES" : " "); 125 gdb_puts (" ", file); 126 gdb_printf (file, " %s", (status & 0x0040) ? "SF" : " "); 127 gdb_puts (" ", file); 128 gdb_printf (file, " %s", (status & 0x0100) ? "C0" : " "); 129 gdb_printf (file, " %s", (status & 0x0200) ? "C1" : " "); 130 gdb_printf (file, " %s", (status & 0x0400) ? "C2" : " "); 131 gdb_printf (file, " %s", (status & 0x4000) ? "C3" : " "); 132 133 gdb_puts ("\n", file); 134 135 gdb_printf (file, 136 " TOP: %d\n", ((status >> 11) & 7)); 137 } 138 139 /* Print the control word CONTROL. If CONTROL_P is false, then 140 CONTROL was unavailable. */ 141 142 static void 143 print_i387_control_word (int control_p, 144 unsigned int control, struct ui_file *file) 145 { 146 gdb_printf (file, "Control Word: "); 147 if (!control_p) 148 { 149 gdb_printf (file, "%s\n", _("<unavailable>")); 150 return; 151 } 152 153 gdb_printf (file, "%s", hex_string_custom (control, 4)); 154 gdb_puts (" ", file); 155 gdb_printf (file, " %s", (control & 0x0001) ? "IM" : " "); 156 gdb_printf (file, " %s", (control & 0x0002) ? "DM" : " "); 157 gdb_printf (file, " %s", (control & 0x0004) ? "ZM" : " "); 158 gdb_printf (file, " %s", (control & 0x0008) ? "OM" : " "); 159 gdb_printf (file, " %s", (control & 0x0010) ? "UM" : " "); 160 gdb_printf (file, " %s", (control & 0x0020) ? "PM" : " "); 161 162 gdb_puts ("\n", file); 163 164 gdb_puts (" PC: ", file); 165 switch ((control >> 8) & 3) 166 { 167 case 0: 168 gdb_puts ("Single Precision (24-bits)\n", file); 169 break; 170 case 1: 171 gdb_puts ("Reserved\n", file); 172 break; 173 case 2: 174 gdb_puts ("Double Precision (53-bits)\n", file); 175 break; 176 case 3: 177 gdb_puts ("Extended Precision (64-bits)\n", file); 178 break; 179 } 180 181 gdb_puts (" RC: ", file); 182 switch ((control >> 10) & 3) 183 { 184 case 0: 185 gdb_puts ("Round to nearest\n", file); 186 break; 187 case 1: 188 gdb_puts ("Round down\n", file); 189 break; 190 case 2: 191 gdb_puts ("Round up\n", file); 192 break; 193 case 3: 194 gdb_puts ("Round toward zero\n", file); 195 break; 196 } 197 } 198 199 /* Print out the i387 floating point state. Note that we ignore FRAME 200 in the code below. That's OK since floating-point registers are 201 never saved on the stack. */ 202 203 void 204 i387_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, 205 frame_info_ptr frame, const char *args) 206 { 207 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 208 ULONGEST fctrl; 209 int fctrl_p; 210 ULONGEST fstat; 211 int fstat_p; 212 ULONGEST ftag; 213 int ftag_p; 214 ULONGEST fiseg; 215 int fiseg_p; 216 ULONGEST fioff; 217 int fioff_p; 218 ULONGEST foseg; 219 int foseg_p; 220 ULONGEST fooff; 221 int fooff_p; 222 ULONGEST fop; 223 int fop_p; 224 int fpreg; 225 int top; 226 227 gdb_assert (gdbarch == get_frame_arch (frame)); 228 229 fctrl_p = read_frame_register_unsigned (frame, 230 I387_FCTRL_REGNUM (tdep), &fctrl); 231 fstat_p = read_frame_register_unsigned (frame, 232 I387_FSTAT_REGNUM (tdep), &fstat); 233 ftag_p = read_frame_register_unsigned (frame, 234 I387_FTAG_REGNUM (tdep), &ftag); 235 fiseg_p = read_frame_register_unsigned (frame, 236 I387_FISEG_REGNUM (tdep), &fiseg); 237 fioff_p = read_frame_register_unsigned (frame, 238 I387_FIOFF_REGNUM (tdep), &fioff); 239 foseg_p = read_frame_register_unsigned (frame, 240 I387_FOSEG_REGNUM (tdep), &foseg); 241 fooff_p = read_frame_register_unsigned (frame, 242 I387_FOOFF_REGNUM (tdep), &fooff); 243 fop_p = read_frame_register_unsigned (frame, 244 I387_FOP_REGNUM (tdep), &fop); 245 246 if (fstat_p) 247 { 248 top = ((fstat >> 11) & 7); 249 250 for (fpreg = 7; fpreg >= 0; fpreg--) 251 { 252 struct value *regval; 253 int regnum; 254 int i; 255 int tag = -1; 256 257 gdb_printf (file, "%sR%d: ", fpreg == top ? "=>" : " ", fpreg); 258 259 if (ftag_p) 260 { 261 tag = (ftag >> (fpreg * 2)) & 3; 262 263 switch (tag) 264 { 265 case 0: 266 gdb_puts ("Valid ", file); 267 break; 268 case 1: 269 gdb_puts ("Zero ", file); 270 break; 271 case 2: 272 gdb_puts ("Special ", file); 273 break; 274 case 3: 275 gdb_puts ("Empty ", file); 276 break; 277 } 278 } 279 else 280 gdb_puts ("Unknown ", file); 281 282 regnum = (fpreg + 8 - top) % 8 + I387_ST0_REGNUM (tdep); 283 regval = get_frame_register_value (frame, regnum); 284 285 if (value_entirely_available (regval)) 286 { 287 const gdb_byte *raw = value_contents (regval).data (); 288 289 gdb_puts ("0x", file); 290 for (i = 9; i >= 0; i--) 291 gdb_printf (file, "%02x", raw[i]); 292 293 if (tag != -1 && tag != 3) 294 print_i387_ext (gdbarch, raw, file); 295 } 296 else 297 gdb_printf (file, "%s", _("<unavailable>")); 298 299 gdb_puts ("\n", file); 300 } 301 } 302 303 gdb_puts ("\n", file); 304 print_i387_status_word (fstat_p, fstat, file); 305 print_i387_control_word (fctrl_p, fctrl, file); 306 gdb_printf (file, "Tag Word: %s\n", 307 ftag_p ? hex_string_custom (ftag, 4) : _("<unavailable>")); 308 gdb_printf (file, "Instruction Pointer: %s:", 309 fiseg_p ? hex_string_custom (fiseg, 2) : _("<unavailable>")); 310 gdb_printf (file, "%s\n", 311 fioff_p ? hex_string_custom (fioff, 8) : _("<unavailable>")); 312 gdb_printf (file, "Operand Pointer: %s:", 313 foseg_p ? hex_string_custom (foseg, 2) : _("<unavailable>")); 314 gdb_printf (file, "%s\n", 315 fooff_p ? hex_string_custom (fooff, 8) : _("<unavailable>")); 316 gdb_printf (file, "Opcode: %s\n", 317 fop_p 318 ? (hex_string_custom (fop ? (fop | 0xd800) : 0, 4)) 319 : _("<unavailable>")); 320 } 321 322 323 /* Return nonzero if a value of type TYPE stored in register REGNUM 324 needs any special handling. */ 325 326 int 327 i387_convert_register_p (struct gdbarch *gdbarch, int regnum, 328 struct type *type) 329 { 330 if (i386_fp_regnum_p (gdbarch, regnum)) 331 { 332 /* Floating point registers must be converted unless we are 333 accessing them in their hardware type or TYPE is not float. */ 334 if (type == i387_ext_type (gdbarch) 335 || type->code () != TYPE_CODE_FLT) 336 return 0; 337 else 338 return 1; 339 } 340 341 return 0; 342 } 343 344 /* Read a value of type TYPE from register REGNUM in frame FRAME, and 345 return its contents in TO. */ 346 347 int 348 i387_register_to_value (frame_info_ptr frame, int regnum, 349 struct type *type, gdb_byte *to, 350 int *optimizedp, int *unavailablep) 351 { 352 struct gdbarch *gdbarch = get_frame_arch (frame); 353 gdb_byte from[I386_MAX_REGISTER_SIZE]; 354 355 gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); 356 357 /* We only support floating-point values. */ 358 if (type->code () != TYPE_CODE_FLT) 359 { 360 warning (_("Cannot convert floating-point register value " 361 "to non-floating-point type.")); 362 *optimizedp = *unavailablep = 0; 363 return 0; 364 } 365 366 /* Convert to TYPE. */ 367 if (!get_frame_register_bytes (frame, regnum, 0, 368 gdb::make_array_view (from, 369 register_size (gdbarch, 370 regnum)), 371 optimizedp, unavailablep)) 372 return 0; 373 374 target_float_convert (from, i387_ext_type (gdbarch), to, type); 375 *optimizedp = *unavailablep = 0; 376 return 1; 377 } 378 379 /* Write the contents FROM of a value of type TYPE into register 380 REGNUM in frame FRAME. */ 381 382 void 383 i387_value_to_register (frame_info_ptr frame, int regnum, 384 struct type *type, const gdb_byte *from) 385 { 386 struct gdbarch *gdbarch = get_frame_arch (frame); 387 gdb_byte to[I386_MAX_REGISTER_SIZE]; 388 389 gdb_assert (i386_fp_regnum_p (gdbarch, regnum)); 390 391 /* We only support floating-point values. */ 392 if (type->code () != TYPE_CODE_FLT) 393 { 394 warning (_("Cannot convert non-floating-point type " 395 "to floating-point register value.")); 396 return; 397 } 398 399 /* Convert from TYPE. */ 400 target_float_convert (from, type, to, i387_ext_type (gdbarch)); 401 put_frame_register (frame, regnum, to); 402 } 403 404 405 /* Handle FSAVE and FXSAVE formats. */ 406 407 /* At fsave_offset[REGNUM] you'll find the offset to the location in 408 the data structure used by the "fsave" instruction where GDB 409 register REGNUM is stored. */ 410 411 static int fsave_offset[] = 412 { 413 28 + 0 * 10, /* %st(0) ... */ 414 28 + 1 * 10, 415 28 + 2 * 10, 416 28 + 3 * 10, 417 28 + 4 * 10, 418 28 + 5 * 10, 419 28 + 6 * 10, 420 28 + 7 * 10, /* ... %st(7). */ 421 0, /* `fctrl' (16 bits). */ 422 4, /* `fstat' (16 bits). */ 423 8, /* `ftag' (16 bits). */ 424 16, /* `fiseg' (16 bits). */ 425 12, /* `fioff'. */ 426 24, /* `foseg' (16 bits). */ 427 20, /* `fooff'. */ 428 18 /* `fop' (bottom 11 bits). */ 429 }; 430 431 #define FSAVE_ADDR(tdep, fsave, regnum) \ 432 (fsave + fsave_offset[regnum - I387_ST0_REGNUM (tdep)]) 433 434 435 /* Fill register REGNUM in REGCACHE with the appropriate value from 436 *FSAVE. This function masks off any of the reserved bits in 437 *FSAVE. */ 438 439 void 440 i387_supply_fsave (struct regcache *regcache, int regnum, const void *fsave) 441 { 442 struct gdbarch *gdbarch = regcache->arch (); 443 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 444 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 445 const gdb_byte *regs = (const gdb_byte *) fsave; 446 int i; 447 448 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 449 450 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) 451 if (regnum == -1 || regnum == i) 452 { 453 if (fsave == NULL) 454 { 455 regcache->raw_supply (i, NULL); 456 continue; 457 } 458 459 /* Most of the FPU control registers occupy only 16 bits in the 460 fsave area. Give those a special treatment. */ 461 if (i >= I387_FCTRL_REGNUM (tdep) 462 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) 463 { 464 gdb_byte val[4]; 465 466 memcpy (val, FSAVE_ADDR (tdep, regs, i), 2); 467 val[2] = val[3] = 0; 468 if (i == I387_FOP_REGNUM (tdep)) 469 val[1] &= ((1 << 3) - 1); 470 regcache->raw_supply (i, val); 471 } 472 else 473 regcache->raw_supply (i, FSAVE_ADDR (tdep, regs, i)); 474 } 475 476 /* Provide dummy values for the SSE registers. */ 477 for (i = I387_XMM0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) 478 if (regnum == -1 || regnum == i) 479 regcache->raw_supply (i, NULL); 480 if (regnum == -1 || regnum == I387_MXCSR_REGNUM (tdep)) 481 { 482 gdb_byte buf[4]; 483 484 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); 485 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); 486 } 487 } 488 489 /* Fill register REGNUM (if it is a floating-point register) in *FSAVE 490 with the value from REGCACHE. If REGNUM is -1, do this for all 491 registers. This function doesn't touch any of the reserved bits in 492 *FSAVE. */ 493 494 void 495 i387_collect_fsave (const struct regcache *regcache, int regnum, void *fsave) 496 { 497 gdbarch *arch = regcache->arch (); 498 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); 499 gdb_byte *regs = (gdb_byte *) fsave; 500 int i; 501 502 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 503 504 for (i = I387_ST0_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) 505 if (regnum == -1 || regnum == i) 506 { 507 /* Most of the FPU control registers occupy only 16 bits in 508 the fsave area. Give those a special treatment. */ 509 if (i >= I387_FCTRL_REGNUM (tdep) 510 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) 511 { 512 gdb_byte buf[4]; 513 514 regcache->raw_collect (i, buf); 515 516 if (i == I387_FOP_REGNUM (tdep)) 517 { 518 /* The opcode occupies only 11 bits. Make sure we 519 don't touch the other bits. */ 520 buf[1] &= ((1 << 3) - 1); 521 buf[1] |= ((FSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); 522 } 523 memcpy (FSAVE_ADDR (tdep, regs, i), buf, 2); 524 } 525 else 526 regcache->raw_collect (i, FSAVE_ADDR (tdep, regs, i)); 527 } 528 } 529 530 531 /* At fxsave_offset[REGNUM] you'll find the offset to the location in 532 the data structure used by the "fxsave" instruction where GDB 533 register REGNUM is stored. */ 534 535 static int fxsave_offset[] = 536 { 537 32, /* %st(0) through ... */ 538 48, 539 64, 540 80, 541 96, 542 112, 543 128, 544 144, /* ... %st(7) (80 bits each). */ 545 0, /* `fctrl' (16 bits). */ 546 2, /* `fstat' (16 bits). */ 547 4, /* `ftag' (16 bits). */ 548 12, /* `fiseg' (16 bits). */ 549 8, /* `fioff'. */ 550 20, /* `foseg' (16 bits). */ 551 16, /* `fooff'. */ 552 6, /* `fop' (bottom 11 bits). */ 553 160 + 0 * 16, /* %xmm0 through ... */ 554 160 + 1 * 16, 555 160 + 2 * 16, 556 160 + 3 * 16, 557 160 + 4 * 16, 558 160 + 5 * 16, 559 160 + 6 * 16, 560 160 + 7 * 16, 561 160 + 8 * 16, 562 160 + 9 * 16, 563 160 + 10 * 16, 564 160 + 11 * 16, 565 160 + 12 * 16, 566 160 + 13 * 16, 567 160 + 14 * 16, 568 160 + 15 * 16, /* ... %xmm15 (128 bits each). */ 569 }; 570 571 #define FXSAVE_ADDR(tdep, fxsave, regnum) \ 572 (fxsave + fxsave_offset[regnum - I387_ST0_REGNUM (tdep)]) 573 574 /* We made an unfortunate choice in putting %mxcsr after the SSE 575 registers %xmm0-%xmm7 instead of before, since it makes supporting 576 the registers %xmm8-%xmm15 on AMD64 a bit involved. Therefore we 577 don't include the offset for %mxcsr here above. */ 578 579 #define FXSAVE_MXCSR_ADDR(fxsave) (fxsave + 24) 580 581 static int i387_tag (const gdb_byte *raw); 582 583 584 /* Fill register REGNUM in REGCACHE with the appropriate 585 floating-point or SSE register value from *FXSAVE. This function 586 masks off any of the reserved bits in *FXSAVE. */ 587 588 void 589 i387_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) 590 { 591 gdbarch *arch = regcache->arch (); 592 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); 593 const gdb_byte *regs = (const gdb_byte *) fxsave; 594 int i; 595 596 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 597 gdb_assert (tdep->num_xmm_regs > 0); 598 599 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) 600 if (regnum == -1 || regnum == i) 601 { 602 if (regs == NULL) 603 { 604 regcache->raw_supply (i, NULL); 605 continue; 606 } 607 608 /* Most of the FPU control registers occupy only 16 bits in 609 the fxsave area. Give those a special treatment. */ 610 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) 611 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) 612 { 613 gdb_byte val[4]; 614 615 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); 616 val[2] = val[3] = 0; 617 if (i == I387_FOP_REGNUM (tdep)) 618 val[1] &= ((1 << 3) - 1); 619 else if (i== I387_FTAG_REGNUM (tdep)) 620 { 621 /* The fxsave area contains a simplified version of 622 the tag word. We have to look at the actual 80-bit 623 FP data to recreate the traditional i387 tag word. */ 624 625 unsigned long ftag = 0; 626 int fpreg; 627 int top; 628 629 top = ((FXSAVE_ADDR (tdep, regs, 630 I387_FSTAT_REGNUM (tdep)))[1] >> 3); 631 top &= 0x7; 632 633 for (fpreg = 7; fpreg >= 0; fpreg--) 634 { 635 int tag; 636 637 if (val[0] & (1 << fpreg)) 638 { 639 int thisreg = (fpreg + 8 - top) % 8 640 + I387_ST0_REGNUM (tdep); 641 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); 642 } 643 else 644 tag = 3; /* Empty */ 645 646 ftag |= tag << (2 * fpreg); 647 } 648 val[0] = ftag & 0xff; 649 val[1] = (ftag >> 8) & 0xff; 650 } 651 regcache->raw_supply (i, val); 652 } 653 else 654 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); 655 } 656 657 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) 658 { 659 if (regs == NULL) 660 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), NULL); 661 else 662 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), 663 FXSAVE_MXCSR_ADDR (regs)); 664 } 665 } 666 667 /* Fill register REGNUM (if it is a floating-point or SSE register) in 668 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 669 all registers. This function doesn't touch any of the reserved 670 bits in *FXSAVE. */ 671 672 void 673 i387_collect_fxsave (const struct regcache *regcache, int regnum, void *fxsave) 674 { 675 gdbarch *arch = regcache->arch (); 676 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); 677 gdb_byte *regs = (gdb_byte *) fxsave; 678 int i; 679 680 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 681 gdb_assert (tdep->num_xmm_regs > 0); 682 683 for (i = I387_ST0_REGNUM (tdep); i < I387_MXCSR_REGNUM (tdep); i++) 684 if (regnum == -1 || regnum == i) 685 { 686 /* Most of the FPU control registers occupy only 16 bits in 687 the fxsave area. Give those a special treatment. */ 688 if (i >= I387_FCTRL_REGNUM (tdep) && i < I387_XMM0_REGNUM (tdep) 689 && i != I387_FIOFF_REGNUM (tdep) && i != I387_FOOFF_REGNUM (tdep)) 690 { 691 gdb_byte buf[4]; 692 693 regcache->raw_collect (i, buf); 694 695 if (i == I387_FOP_REGNUM (tdep)) 696 { 697 /* The opcode occupies only 11 bits. Make sure we 698 don't touch the other bits. */ 699 buf[1] &= ((1 << 3) - 1); 700 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); 701 } 702 else if (i == I387_FTAG_REGNUM (tdep)) 703 { 704 /* Converting back is much easier. */ 705 706 unsigned short ftag; 707 int fpreg; 708 709 ftag = (buf[1] << 8) | buf[0]; 710 buf[0] = 0; 711 buf[1] = 0; 712 713 for (fpreg = 7; fpreg >= 0; fpreg--) 714 { 715 int tag = (ftag >> (fpreg * 2)) & 3; 716 717 if (tag != 3) 718 buf[0] |= (1 << fpreg); 719 } 720 } 721 memcpy (FXSAVE_ADDR (tdep, regs, i), buf, 2); 722 } 723 else 724 regcache->raw_collect (i, FXSAVE_ADDR (tdep, regs, i)); 725 } 726 727 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) 728 regcache->raw_collect (I387_MXCSR_REGNUM (tdep), 729 FXSAVE_MXCSR_ADDR (regs)); 730 } 731 732 /* `xstate_bv' is at byte offset 512. */ 733 #define XSAVE_XSTATE_BV_ADDR(xsave) (xsave + 512) 734 735 /* At xsave_avxh_offset[REGNUM] you'll find the offset to the location in 736 the upper 128bit of AVX register data structure used by the "xsave" 737 instruction where GDB register REGNUM is stored. */ 738 739 static int xsave_avxh_offset[] = 740 { 741 576 + 0 * 16, /* Upper 128bit of %ymm0 through ... */ 742 576 + 1 * 16, 743 576 + 2 * 16, 744 576 + 3 * 16, 745 576 + 4 * 16, 746 576 + 5 * 16, 747 576 + 6 * 16, 748 576 + 7 * 16, 749 576 + 8 * 16, 750 576 + 9 * 16, 751 576 + 10 * 16, 752 576 + 11 * 16, 753 576 + 12 * 16, 754 576 + 13 * 16, 755 576 + 14 * 16, 756 576 + 15 * 16 /* Upper 128bit of ... %ymm15 (128 bits each). */ 757 }; 758 759 #define XSAVE_AVXH_ADDR(tdep, xsave, regnum) \ 760 (xsave + xsave_avxh_offset[regnum - I387_YMM0H_REGNUM (tdep)]) 761 762 /* At xsave_ymm_avx512_offset[REGNUM] you'll find the offset to the location in 763 the upper 128bit of ZMM register data structure used by the "xsave" 764 instruction where GDB register REGNUM is stored. */ 765 766 static int xsave_ymm_avx512_offset[] = 767 { 768 /* HI16_ZMM_area + 16 bytes + regnum* 64 bytes. */ 769 1664 + 16 + 0 * 64, /* %ymm16 through... */ 770 1664 + 16 + 1 * 64, 771 1664 + 16 + 2 * 64, 772 1664 + 16 + 3 * 64, 773 1664 + 16 + 4 * 64, 774 1664 + 16 + 5 * 64, 775 1664 + 16 + 6 * 64, 776 1664 + 16 + 7 * 64, 777 1664 + 16 + 8 * 64, 778 1664 + 16 + 9 * 64, 779 1664 + 16 + 10 * 64, 780 1664 + 16 + 11 * 64, 781 1664 + 16 + 12 * 64, 782 1664 + 16 + 13 * 64, 783 1664 + 16 + 14 * 64, 784 1664 + 16 + 15 * 64 /* ... %ymm31 (128 bits each). */ 785 }; 786 787 #define XSAVE_YMM_AVX512_ADDR(tdep, xsave, regnum) \ 788 (xsave + xsave_ymm_avx512_offset[regnum - I387_YMM16H_REGNUM (tdep)]) 789 790 static int xsave_xmm_avx512_offset[] = 791 { 792 1664 + 0 * 64, /* %ymm16 through... */ 793 1664 + 1 * 64, 794 1664 + 2 * 64, 795 1664 + 3 * 64, 796 1664 + 4 * 64, 797 1664 + 5 * 64, 798 1664 + 6 * 64, 799 1664 + 7 * 64, 800 1664 + 8 * 64, 801 1664 + 9 * 64, 802 1664 + 10 * 64, 803 1664 + 11 * 64, 804 1664 + 12 * 64, 805 1664 + 13 * 64, 806 1664 + 14 * 64, 807 1664 + 15 * 64 /* ... %ymm31 (128 bits each). */ 808 }; 809 810 #define XSAVE_XMM_AVX512_ADDR(tdep, xsave, regnum) \ 811 (xsave + xsave_xmm_avx512_offset[regnum - I387_XMM16_REGNUM (tdep)]) 812 813 static int xsave_mpx_offset[] = { 814 960 + 0 * 16, /* bnd0r...bnd3r registers. */ 815 960 + 1 * 16, 816 960 + 2 * 16, 817 960 + 3 * 16, 818 1024 + 0 * 8, /* bndcfg ... bndstatus. */ 819 1024 + 1 * 8, 820 }; 821 822 #define XSAVE_MPX_ADDR(tdep, xsave, regnum) \ 823 (xsave + xsave_mpx_offset[regnum - I387_BND0R_REGNUM (tdep)]) 824 825 /* At xsave_avx512__h_offset[REGNUM] you find the offset to the location 826 of the AVX512 opmask register data structure used by the "xsave" 827 instruction where GDB register REGNUM is stored. */ 828 829 static int xsave_avx512_k_offset[] = 830 { 831 1088 + 0 * 8, /* %k0 through... */ 832 1088 + 1 * 8, 833 1088 + 2 * 8, 834 1088 + 3 * 8, 835 1088 + 4 * 8, 836 1088 + 5 * 8, 837 1088 + 6 * 8, 838 1088 + 7 * 8 /* %k7 (64 bits each). */ 839 }; 840 841 #define XSAVE_AVX512_K_ADDR(tdep, xsave, regnum) \ 842 (xsave + xsave_avx512_k_offset[regnum - I387_K0_REGNUM (tdep)]) 843 844 /* At xsave_avx512_zmm_h_offset[REGNUM] you find the offset to the location in 845 the upper 256bit of AVX512 ZMMH register data structure used by the "xsave" 846 instruction where GDB register REGNUM is stored. */ 847 848 static int xsave_avx512_zmm_h_offset[] = 849 { 850 1152 + 0 * 32, 851 1152 + 1 * 32, /* Upper 256bit of %zmmh0 through... */ 852 1152 + 2 * 32, 853 1152 + 3 * 32, 854 1152 + 4 * 32, 855 1152 + 5 * 32, 856 1152 + 6 * 32, 857 1152 + 7 * 32, 858 1152 + 8 * 32, 859 1152 + 9 * 32, 860 1152 + 10 * 32, 861 1152 + 11 * 32, 862 1152 + 12 * 32, 863 1152 + 13 * 32, 864 1152 + 14 * 32, 865 1152 + 15 * 32, /* Upper 256bit of... %zmmh15 (256 bits each). */ 866 1664 + 32 + 0 * 64, /* Upper 256bit of... %zmmh16 (256 bits each). */ 867 1664 + 32 + 1 * 64, 868 1664 + 32 + 2 * 64, 869 1664 + 32 + 3 * 64, 870 1664 + 32 + 4 * 64, 871 1664 + 32 + 5 * 64, 872 1664 + 32 + 6 * 64, 873 1664 + 32 + 7 * 64, 874 1664 + 32 + 8 * 64, 875 1664 + 32 + 9 * 64, 876 1664 + 32 + 10 * 64, 877 1664 + 32 + 11 * 64, 878 1664 + 32 + 12 * 64, 879 1664 + 32 + 13 * 64, 880 1664 + 32 + 14 * 64, 881 1664 + 32 + 15 * 64 /* Upper 256bit of... %zmmh31 (256 bits each). */ 882 }; 883 884 #define XSAVE_AVX512_ZMM_H_ADDR(tdep, xsave, regnum) \ 885 (xsave + xsave_avx512_zmm_h_offset[regnum - I387_ZMM0H_REGNUM (tdep)]) 886 887 /* At xsave_pkeys_offset[REGNUM] you find the offset to the location 888 of the PKRU register data structure used by the "xsave" 889 instruction where GDB register REGNUM is stored. */ 890 891 static int xsave_pkeys_offset[] = 892 { 893 2688 + 0 * 8 /* %pkru (64 bits in XSTATE, 32-bit actually used by 894 instructions and applications). */ 895 }; 896 897 #define XSAVE_PKEYS_ADDR(tdep, xsave, regnum) \ 898 (xsave + xsave_pkeys_offset[regnum - I387_PKRU_REGNUM (tdep)]) 899 900 901 /* Extract from XSAVE a bitset of the features that are available on the 902 target, but which have not yet been enabled. */ 903 904 ULONGEST 905 i387_xsave_get_clear_bv (struct gdbarch *gdbarch, const void *xsave) 906 { 907 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 908 const gdb_byte *regs = (const gdb_byte *) xsave; 909 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 910 911 /* Get `xstat_bv'. The supported bits in `xstat_bv' are 8 bytes. */ 912 ULONGEST xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), 913 8, byte_order); 914 915 /* Clear part in vector registers if its bit in xstat_bv is zero. */ 916 ULONGEST clear_bv = (~(xstate_bv)) & tdep->xcr0; 917 918 return clear_bv; 919 } 920 921 /* Similar to i387_supply_fxsave, but use XSAVE extended state. */ 922 923 void 924 i387_supply_xsave (struct regcache *regcache, int regnum, 925 const void *xsave) 926 { 927 struct gdbarch *gdbarch = regcache->arch (); 928 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 929 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 930 const gdb_byte *regs = (const gdb_byte *) xsave; 931 int i; 932 /* In 64-bit mode the split between "low" and "high" ZMM registers is at 933 ZMM16. Outside of 64-bit mode there are no "high" ZMM registers at all. 934 Precalculate the number to be used for the split point, with the all 935 registers in the "low" portion outside of 64-bit mode. */ 936 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) 937 + std::min (tdep->num_zmm_regs, 16); 938 ULONGEST clear_bv; 939 static const gdb_byte zero[I386_MAX_REGISTER_SIZE] = { 0 }; 940 enum 941 { 942 none = 0x0, 943 x87 = 0x1, 944 sse = 0x2, 945 avxh = 0x4, 946 mpx = 0x8, 947 avx512_k = 0x10, 948 avx512_zmm_h = 0x20, 949 avx512_ymmh_avx512 = 0x40, 950 avx512_xmm_avx512 = 0x80, 951 pkeys = 0x100, 952 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h 953 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys 954 } regclass; 955 956 gdb_assert (regs != NULL); 957 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 958 gdb_assert (tdep->num_xmm_regs > 0); 959 960 if (regnum == -1) 961 regclass = all; 962 else if (regnum >= I387_PKRU_REGNUM (tdep) 963 && regnum < I387_PKEYSEND_REGNUM (tdep)) 964 regclass = pkeys; 965 else if (regnum >= I387_ZMM0H_REGNUM (tdep) 966 && regnum < I387_ZMMENDH_REGNUM (tdep)) 967 regclass = avx512_zmm_h; 968 else if (regnum >= I387_K0_REGNUM (tdep) 969 && regnum < I387_KEND_REGNUM (tdep)) 970 regclass = avx512_k; 971 else if (regnum >= I387_YMM16H_REGNUM (tdep) 972 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) 973 regclass = avx512_ymmh_avx512; 974 else if (regnum >= I387_XMM16_REGNUM (tdep) 975 && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) 976 regclass = avx512_xmm_avx512; 977 else if (regnum >= I387_YMM0H_REGNUM (tdep) 978 && regnum < I387_YMMENDH_REGNUM (tdep)) 979 regclass = avxh; 980 else if (regnum >= I387_BND0R_REGNUM (tdep) 981 && regnum < I387_MPXEND_REGNUM (tdep)) 982 regclass = mpx; 983 else if (regnum >= I387_XMM0_REGNUM (tdep) 984 && regnum < I387_MXCSR_REGNUM (tdep)) 985 regclass = sse; 986 else if (regnum >= I387_ST0_REGNUM (tdep) 987 && regnum < I387_FCTRL_REGNUM (tdep)) 988 regclass = x87; 989 else 990 regclass = none; 991 992 clear_bv = i387_xsave_get_clear_bv (gdbarch, xsave); 993 994 /* With the delayed xsave mechanism, in between the program 995 starting, and the program accessing the vector registers for the 996 first time, the register's values are invalid. The kernel 997 initializes register states to zero when they are set the first 998 time in a program. This means that from the user-space programs' 999 perspective, it's the same as if the registers have always been 1000 zero from the start of the program. Therefore, the debugger 1001 should provide the same illusion to the user. */ 1002 1003 switch (regclass) 1004 { 1005 case none: 1006 break; 1007 1008 case pkeys: 1009 if ((clear_bv & X86_XSTATE_PKRU)) 1010 regcache->raw_supply (regnum, zero); 1011 else 1012 regcache->raw_supply (regnum, XSAVE_PKEYS_ADDR (tdep, regs, regnum)); 1013 return; 1014 1015 case avx512_zmm_h: 1016 if ((clear_bv & (regnum < zmm_endlo_regnum ? X86_XSTATE_ZMM_H 1017 : X86_XSTATE_ZMM))) 1018 regcache->raw_supply (regnum, zero); 1019 else 1020 regcache->raw_supply (regnum, 1021 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum)); 1022 return; 1023 1024 case avx512_k: 1025 if ((clear_bv & X86_XSTATE_K)) 1026 regcache->raw_supply (regnum, zero); 1027 else 1028 regcache->raw_supply (regnum, XSAVE_AVX512_K_ADDR (tdep, regs, regnum)); 1029 return; 1030 1031 case avx512_ymmh_avx512: 1032 if ((clear_bv & X86_XSTATE_ZMM)) 1033 regcache->raw_supply (regnum, zero); 1034 else 1035 regcache->raw_supply (regnum, 1036 XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum)); 1037 return; 1038 1039 case avx512_xmm_avx512: 1040 if ((clear_bv & X86_XSTATE_ZMM)) 1041 regcache->raw_supply (regnum, zero); 1042 else 1043 regcache->raw_supply (regnum, 1044 XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum)); 1045 return; 1046 1047 case avxh: 1048 if ((clear_bv & X86_XSTATE_AVX)) 1049 regcache->raw_supply (regnum, zero); 1050 else 1051 regcache->raw_supply (regnum, XSAVE_AVXH_ADDR (tdep, regs, regnum)); 1052 return; 1053 1054 case mpx: 1055 if ((clear_bv & X86_XSTATE_BNDREGS)) 1056 regcache->raw_supply (regnum, zero); 1057 else 1058 regcache->raw_supply (regnum, XSAVE_MPX_ADDR (tdep, regs, regnum)); 1059 return; 1060 1061 case sse: 1062 if ((clear_bv & X86_XSTATE_SSE)) 1063 regcache->raw_supply (regnum, zero); 1064 else 1065 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); 1066 return; 1067 1068 case x87: 1069 if ((clear_bv & X86_XSTATE_X87)) 1070 regcache->raw_supply (regnum, zero); 1071 else 1072 regcache->raw_supply (regnum, FXSAVE_ADDR (tdep, regs, regnum)); 1073 return; 1074 1075 case all: 1076 /* Handle PKEYS registers. */ 1077 if ((tdep->xcr0 & X86_XSTATE_PKRU)) 1078 { 1079 if ((clear_bv & X86_XSTATE_PKRU)) 1080 { 1081 for (i = I387_PKRU_REGNUM (tdep); 1082 i < I387_PKEYSEND_REGNUM (tdep); 1083 i++) 1084 regcache->raw_supply (i, zero); 1085 } 1086 else 1087 { 1088 for (i = I387_PKRU_REGNUM (tdep); 1089 i < I387_PKEYSEND_REGNUM (tdep); 1090 i++) 1091 regcache->raw_supply (i, XSAVE_PKEYS_ADDR (tdep, regs, i)); 1092 } 1093 } 1094 1095 /* Handle the upper halves of the low 8/16 ZMM registers. */ 1096 if ((tdep->xcr0 & X86_XSTATE_ZMM_H)) 1097 { 1098 if ((clear_bv & X86_XSTATE_ZMM_H)) 1099 { 1100 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) 1101 regcache->raw_supply (i, zero); 1102 } 1103 else 1104 { 1105 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) 1106 regcache->raw_supply (i, 1107 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); 1108 } 1109 } 1110 1111 /* Handle AVX512 OpMask registers. */ 1112 if ((tdep->xcr0 & X86_XSTATE_K)) 1113 { 1114 if ((clear_bv & X86_XSTATE_K)) 1115 { 1116 for (i = I387_K0_REGNUM (tdep); 1117 i < I387_KEND_REGNUM (tdep); 1118 i++) 1119 regcache->raw_supply (i, zero); 1120 } 1121 else 1122 { 1123 for (i = I387_K0_REGNUM (tdep); 1124 i < I387_KEND_REGNUM (tdep); 1125 i++) 1126 regcache->raw_supply (i, XSAVE_AVX512_K_ADDR (tdep, regs, i)); 1127 } 1128 } 1129 1130 /* Handle the upper 16 ZMM/YMM/XMM registers (if any). */ 1131 if ((tdep->xcr0 & X86_XSTATE_ZMM)) 1132 { 1133 if ((clear_bv & X86_XSTATE_ZMM)) 1134 { 1135 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) 1136 regcache->raw_supply (i, zero); 1137 for (i = I387_YMM16H_REGNUM (tdep); 1138 i < I387_YMMH_AVX512_END_REGNUM (tdep); 1139 i++) 1140 regcache->raw_supply (i, zero); 1141 for (i = I387_XMM16_REGNUM (tdep); 1142 i < I387_XMM_AVX512_END_REGNUM (tdep); 1143 i++) 1144 regcache->raw_supply (i, zero); 1145 } 1146 else 1147 { 1148 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) 1149 regcache->raw_supply (i, 1150 XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i)); 1151 for (i = I387_YMM16H_REGNUM (tdep); 1152 i < I387_YMMH_AVX512_END_REGNUM (tdep); 1153 i++) 1154 regcache->raw_supply (i, XSAVE_YMM_AVX512_ADDR (tdep, regs, i)); 1155 for (i = I387_XMM16_REGNUM (tdep); 1156 i < I387_XMM_AVX512_END_REGNUM (tdep); 1157 i++) 1158 regcache->raw_supply (i, XSAVE_XMM_AVX512_ADDR (tdep, regs, i)); 1159 } 1160 } 1161 /* Handle the upper YMM registers. */ 1162 if ((tdep->xcr0 & X86_XSTATE_AVX)) 1163 { 1164 if ((clear_bv & X86_XSTATE_AVX)) 1165 { 1166 for (i = I387_YMM0H_REGNUM (tdep); 1167 i < I387_YMMENDH_REGNUM (tdep); 1168 i++) 1169 regcache->raw_supply (i, zero); 1170 } 1171 else 1172 { 1173 for (i = I387_YMM0H_REGNUM (tdep); 1174 i < I387_YMMENDH_REGNUM (tdep); 1175 i++) 1176 regcache->raw_supply (i, XSAVE_AVXH_ADDR (tdep, regs, i)); 1177 } 1178 } 1179 1180 /* Handle the MPX registers. */ 1181 if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) 1182 { 1183 if (clear_bv & X86_XSTATE_BNDREGS) 1184 { 1185 for (i = I387_BND0R_REGNUM (tdep); 1186 i < I387_BNDCFGU_REGNUM (tdep); i++) 1187 regcache->raw_supply (i, zero); 1188 } 1189 else 1190 { 1191 for (i = I387_BND0R_REGNUM (tdep); 1192 i < I387_BNDCFGU_REGNUM (tdep); i++) 1193 regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); 1194 } 1195 } 1196 1197 /* Handle the MPX registers. */ 1198 if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) 1199 { 1200 if (clear_bv & X86_XSTATE_BNDCFG) 1201 { 1202 for (i = I387_BNDCFGU_REGNUM (tdep); 1203 i < I387_MPXEND_REGNUM (tdep); i++) 1204 regcache->raw_supply (i, zero); 1205 } 1206 else 1207 { 1208 for (i = I387_BNDCFGU_REGNUM (tdep); 1209 i < I387_MPXEND_REGNUM (tdep); i++) 1210 regcache->raw_supply (i, XSAVE_MPX_ADDR (tdep, regs, i)); 1211 } 1212 } 1213 1214 /* Handle the XMM registers. */ 1215 if ((tdep->xcr0 & X86_XSTATE_SSE)) 1216 { 1217 if ((clear_bv & X86_XSTATE_SSE)) 1218 { 1219 for (i = I387_XMM0_REGNUM (tdep); 1220 i < I387_MXCSR_REGNUM (tdep); 1221 i++) 1222 regcache->raw_supply (i, zero); 1223 } 1224 else 1225 { 1226 for (i = I387_XMM0_REGNUM (tdep); 1227 i < I387_MXCSR_REGNUM (tdep); i++) 1228 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); 1229 } 1230 } 1231 1232 /* Handle the x87 registers. */ 1233 if ((tdep->xcr0 & X86_XSTATE_X87)) 1234 { 1235 if ((clear_bv & X86_XSTATE_X87)) 1236 { 1237 for (i = I387_ST0_REGNUM (tdep); 1238 i < I387_FCTRL_REGNUM (tdep); 1239 i++) 1240 regcache->raw_supply (i, zero); 1241 } 1242 else 1243 { 1244 for (i = I387_ST0_REGNUM (tdep); 1245 i < I387_FCTRL_REGNUM (tdep); 1246 i++) 1247 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); 1248 } 1249 } 1250 break; 1251 } 1252 1253 /* Only handle x87 control registers. */ 1254 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) 1255 if (regnum == -1 || regnum == i) 1256 { 1257 if (clear_bv & X86_XSTATE_X87) 1258 { 1259 if (i == I387_FCTRL_REGNUM (tdep)) 1260 { 1261 gdb_byte buf[4]; 1262 1263 store_unsigned_integer (buf, 4, byte_order, 1264 I387_FCTRL_INIT_VAL); 1265 regcache->raw_supply (i, buf); 1266 } 1267 else if (i == I387_FTAG_REGNUM (tdep)) 1268 { 1269 gdb_byte buf[4]; 1270 1271 store_unsigned_integer (buf, 4, byte_order, 0xffff); 1272 regcache->raw_supply (i, buf); 1273 } 1274 else 1275 regcache->raw_supply (i, zero); 1276 } 1277 /* Most of the FPU control registers occupy only 16 bits in 1278 the xsave extended state. Give those a special treatment. */ 1279 else if (i != I387_FIOFF_REGNUM (tdep) 1280 && i != I387_FOOFF_REGNUM (tdep)) 1281 { 1282 gdb_byte val[4]; 1283 1284 memcpy (val, FXSAVE_ADDR (tdep, regs, i), 2); 1285 val[2] = val[3] = 0; 1286 if (i == I387_FOP_REGNUM (tdep)) 1287 val[1] &= ((1 << 3) - 1); 1288 else if (i == I387_FTAG_REGNUM (tdep)) 1289 { 1290 /* The fxsave area contains a simplified version of 1291 the tag word. We have to look at the actual 80-bit 1292 FP data to recreate the traditional i387 tag word. */ 1293 1294 unsigned long ftag = 0; 1295 int fpreg; 1296 int top; 1297 1298 top = ((FXSAVE_ADDR (tdep, regs, 1299 I387_FSTAT_REGNUM (tdep)))[1] >> 3); 1300 top &= 0x7; 1301 1302 for (fpreg = 7; fpreg >= 0; fpreg--) 1303 { 1304 int tag; 1305 1306 if (val[0] & (1 << fpreg)) 1307 { 1308 int thisreg = (fpreg + 8 - top) % 8 1309 + I387_ST0_REGNUM (tdep); 1310 tag = i387_tag (FXSAVE_ADDR (tdep, regs, thisreg)); 1311 } 1312 else 1313 tag = 3; /* Empty */ 1314 1315 ftag |= tag << (2 * fpreg); 1316 } 1317 val[0] = ftag & 0xff; 1318 val[1] = (ftag >> 8) & 0xff; 1319 } 1320 regcache->raw_supply (i, val); 1321 } 1322 else 1323 regcache->raw_supply (i, FXSAVE_ADDR (tdep, regs, i)); 1324 } 1325 1326 if (regnum == I387_MXCSR_REGNUM (tdep) || regnum == -1) 1327 { 1328 /* The MXCSR register is placed into the xsave buffer if either the 1329 AVX or SSE features are enabled. */ 1330 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) 1331 == (X86_XSTATE_AVX | X86_XSTATE_SSE)) 1332 { 1333 gdb_byte buf[4]; 1334 1335 store_unsigned_integer (buf, 4, byte_order, I387_MXCSR_INIT_VAL); 1336 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), buf); 1337 } 1338 else 1339 regcache->raw_supply (I387_MXCSR_REGNUM (tdep), 1340 FXSAVE_MXCSR_ADDR (regs)); 1341 } 1342 } 1343 1344 /* Similar to i387_collect_fxsave, but use XSAVE extended state. */ 1345 1346 void 1347 i387_collect_xsave (const struct regcache *regcache, int regnum, 1348 void *xsave, int gcore) 1349 { 1350 struct gdbarch *gdbarch = regcache->arch (); 1351 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); 1352 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 1353 gdb_byte *p, *regs = (gdb_byte *) xsave; 1354 gdb_byte raw[I386_MAX_REGISTER_SIZE]; 1355 ULONGEST initial_xstate_bv, clear_bv, xstate_bv = 0; 1356 unsigned int i; 1357 /* See the comment in i387_supply_xsave(). */ 1358 unsigned int zmm_endlo_regnum = I387_ZMM0H_REGNUM (tdep) 1359 + std::min (tdep->num_zmm_regs, 16); 1360 enum 1361 { 1362 x87_ctrl_or_mxcsr = 0x1, 1363 x87 = 0x2, 1364 sse = 0x4, 1365 avxh = 0x8, 1366 mpx = 0x10, 1367 avx512_k = 0x20, 1368 avx512_zmm_h = 0x40, 1369 avx512_ymmh_avx512 = 0x80, 1370 avx512_xmm_avx512 = 0x100, 1371 pkeys = 0x200, 1372 all = x87 | sse | avxh | mpx | avx512_k | avx512_zmm_h 1373 | avx512_ymmh_avx512 | avx512_xmm_avx512 | pkeys 1374 } regclass; 1375 1376 gdb_assert (tdep->st0_regnum >= I386_ST0_REGNUM); 1377 gdb_assert (tdep->num_xmm_regs > 0); 1378 1379 if (regnum == -1) 1380 regclass = all; 1381 else if (regnum >= I387_PKRU_REGNUM (tdep) 1382 && regnum < I387_PKEYSEND_REGNUM (tdep)) 1383 regclass = pkeys; 1384 else if (regnum >= I387_ZMM0H_REGNUM (tdep) 1385 && regnum < I387_ZMMENDH_REGNUM (tdep)) 1386 regclass = avx512_zmm_h; 1387 else if (regnum >= I387_K0_REGNUM (tdep) 1388 && regnum < I387_KEND_REGNUM (tdep)) 1389 regclass = avx512_k; 1390 else if (regnum >= I387_YMM16H_REGNUM (tdep) 1391 && regnum < I387_YMMH_AVX512_END_REGNUM (tdep)) 1392 regclass = avx512_ymmh_avx512; 1393 else if (regnum >= I387_XMM16_REGNUM (tdep) 1394 && regnum < I387_XMM_AVX512_END_REGNUM (tdep)) 1395 regclass = avx512_xmm_avx512; 1396 else if (regnum >= I387_YMM0H_REGNUM (tdep) 1397 && regnum < I387_YMMENDH_REGNUM (tdep)) 1398 regclass = avxh; 1399 else if (regnum >= I387_BND0R_REGNUM (tdep) 1400 && regnum < I387_MPXEND_REGNUM (tdep)) 1401 regclass = mpx; 1402 else if (regnum >= I387_XMM0_REGNUM (tdep) 1403 && regnum < I387_MXCSR_REGNUM (tdep)) 1404 regclass = sse; 1405 else if (regnum >= I387_ST0_REGNUM (tdep) 1406 && regnum < I387_FCTRL_REGNUM (tdep)) 1407 regclass = x87; 1408 else if ((regnum >= I387_FCTRL_REGNUM (tdep) 1409 && regnum < I387_XMM0_REGNUM (tdep)) 1410 || regnum == I387_MXCSR_REGNUM (tdep)) 1411 regclass = x87_ctrl_or_mxcsr; 1412 else 1413 internal_error (_("invalid i387 regnum %d"), regnum); 1414 1415 if (gcore) 1416 { 1417 /* Clear XSAVE extended state. */ 1418 memset (regs, 0, X86_XSTATE_SIZE (tdep->xcr0)); 1419 1420 /* Update XCR0 and `xstate_bv' with XCR0 for gcore. */ 1421 if (tdep->xsave_xcr0_offset != -1) 1422 memcpy (regs + tdep->xsave_xcr0_offset, &tdep->xcr0, 8); 1423 memcpy (XSAVE_XSTATE_BV_ADDR (regs), &tdep->xcr0, 8); 1424 } 1425 1426 /* The supported bits in `xstat_bv' are 8 bytes. */ 1427 initial_xstate_bv = extract_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), 1428 8, byte_order); 1429 clear_bv = (~(initial_xstate_bv)) & tdep->xcr0; 1430 1431 /* The XSAVE buffer was filled lazily by the kernel. Only those 1432 features that are enabled were written into the buffer, disabled 1433 features left the buffer uninitialised. In order to identify if any 1434 registers have changed we will be comparing the register cache 1435 version to the version in the XSAVE buffer, it is important then that 1436 at this point we initialise to the default values any features in 1437 XSAVE that are not yet initialised. 1438 1439 This could be made more efficient, we know which features (from 1440 REGNUM) we will be potentially updating, and could limit ourselves to 1441 only clearing that feature. However, the extra complexity does not 1442 seem justified at this point. */ 1443 if (clear_bv) 1444 { 1445 if ((clear_bv & X86_XSTATE_PKRU)) 1446 for (i = I387_PKRU_REGNUM (tdep); 1447 i < I387_PKEYSEND_REGNUM (tdep); i++) 1448 memset (XSAVE_PKEYS_ADDR (tdep, regs, i), 0, 4); 1449 1450 if ((clear_bv & X86_XSTATE_BNDREGS)) 1451 for (i = I387_BND0R_REGNUM (tdep); 1452 i < I387_BNDCFGU_REGNUM (tdep); i++) 1453 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 16); 1454 1455 if ((clear_bv & X86_XSTATE_BNDCFG)) 1456 for (i = I387_BNDCFGU_REGNUM (tdep); 1457 i < I387_MPXEND_REGNUM (tdep); i++) 1458 memset (XSAVE_MPX_ADDR (tdep, regs, i), 0, 8); 1459 1460 if ((clear_bv & X86_XSTATE_ZMM_H)) 1461 for (i = I387_ZMM0H_REGNUM (tdep); i < zmm_endlo_regnum; i++) 1462 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); 1463 1464 if ((clear_bv & X86_XSTATE_K)) 1465 for (i = I387_K0_REGNUM (tdep); 1466 i < I387_KEND_REGNUM (tdep); i++) 1467 memset (XSAVE_AVX512_K_ADDR (tdep, regs, i), 0, 8); 1468 1469 if ((clear_bv & X86_XSTATE_ZMM)) 1470 { 1471 for (i = zmm_endlo_regnum; i < I387_ZMMENDH_REGNUM (tdep); i++) 1472 memset (XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i), 0, 32); 1473 for (i = I387_YMM16H_REGNUM (tdep); 1474 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) 1475 memset (XSAVE_YMM_AVX512_ADDR (tdep, regs, i), 0, 16); 1476 for (i = I387_XMM16_REGNUM (tdep); 1477 i < I387_XMM_AVX512_END_REGNUM (tdep); i++) 1478 memset (XSAVE_XMM_AVX512_ADDR (tdep, regs, i), 0, 16); 1479 } 1480 1481 if ((clear_bv & X86_XSTATE_AVX)) 1482 for (i = I387_YMM0H_REGNUM (tdep); 1483 i < I387_YMMENDH_REGNUM (tdep); i++) 1484 memset (XSAVE_AVXH_ADDR (tdep, regs, i), 0, 16); 1485 1486 if ((clear_bv & X86_XSTATE_SSE)) 1487 for (i = I387_XMM0_REGNUM (tdep); 1488 i < I387_MXCSR_REGNUM (tdep); i++) 1489 memset (FXSAVE_ADDR (tdep, regs, i), 0, 16); 1490 1491 /* The mxcsr register is written into the xsave buffer if either AVX 1492 or SSE is enabled, so only clear it if both of those features 1493 require clearing. */ 1494 if ((clear_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) 1495 == (X86_XSTATE_AVX | X86_XSTATE_SSE)) 1496 store_unsigned_integer (FXSAVE_MXCSR_ADDR (regs), 2, byte_order, 1497 I387_MXCSR_INIT_VAL); 1498 1499 if ((clear_bv & X86_XSTATE_X87)) 1500 { 1501 for (i = I387_ST0_REGNUM (tdep); 1502 i < I387_FCTRL_REGNUM (tdep); i++) 1503 memset (FXSAVE_ADDR (tdep, regs, i), 0, 10); 1504 1505 for (i = I387_FCTRL_REGNUM (tdep); 1506 i < I387_XMM0_REGNUM (tdep); i++) 1507 { 1508 if (i == I387_FCTRL_REGNUM (tdep)) 1509 store_unsigned_integer (FXSAVE_ADDR (tdep, regs, i), 2, 1510 byte_order, I387_FCTRL_INIT_VAL); 1511 else 1512 memset (FXSAVE_ADDR (tdep, regs, i), 0, 1513 regcache_register_size (regcache, i)); 1514 } 1515 } 1516 } 1517 1518 if (regclass == all) 1519 { 1520 /* Check if any PKEYS registers are changed. */ 1521 if ((tdep->xcr0 & X86_XSTATE_PKRU)) 1522 for (i = I387_PKRU_REGNUM (tdep); 1523 i < I387_PKEYSEND_REGNUM (tdep); i++) 1524 { 1525 regcache->raw_collect (i, raw); 1526 p = XSAVE_PKEYS_ADDR (tdep, regs, i); 1527 if (memcmp (raw, p, 4) != 0) 1528 { 1529 xstate_bv |= X86_XSTATE_PKRU; 1530 memcpy (p, raw, 4); 1531 } 1532 } 1533 1534 /* Check if any ZMMH registers are changed. */ 1535 if ((tdep->xcr0 & (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM))) 1536 for (i = I387_ZMM0H_REGNUM (tdep); 1537 i < I387_ZMMENDH_REGNUM (tdep); i++) 1538 { 1539 regcache->raw_collect (i, raw); 1540 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, i); 1541 if (memcmp (raw, p, 32) != 0) 1542 { 1543 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); 1544 memcpy (p, raw, 32); 1545 } 1546 } 1547 1548 /* Check if any K registers are changed. */ 1549 if ((tdep->xcr0 & X86_XSTATE_K)) 1550 for (i = I387_K0_REGNUM (tdep); 1551 i < I387_KEND_REGNUM (tdep); i++) 1552 { 1553 regcache->raw_collect (i, raw); 1554 p = XSAVE_AVX512_K_ADDR (tdep, regs, i); 1555 if (memcmp (raw, p, 8) != 0) 1556 { 1557 xstate_bv |= X86_XSTATE_K; 1558 memcpy (p, raw, 8); 1559 } 1560 } 1561 1562 /* Check if any XMM or upper YMM registers are changed. */ 1563 if ((tdep->xcr0 & X86_XSTATE_ZMM)) 1564 { 1565 for (i = I387_YMM16H_REGNUM (tdep); 1566 i < I387_YMMH_AVX512_END_REGNUM (tdep); i++) 1567 { 1568 regcache->raw_collect (i, raw); 1569 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, i); 1570 if (memcmp (raw, p, 16) != 0) 1571 { 1572 xstate_bv |= X86_XSTATE_ZMM; 1573 memcpy (p, raw, 16); 1574 } 1575 } 1576 for (i = I387_XMM16_REGNUM (tdep); 1577 i < I387_XMM_AVX512_END_REGNUM (tdep); i++) 1578 { 1579 regcache->raw_collect (i, raw); 1580 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, i); 1581 if (memcmp (raw, p, 16) != 0) 1582 { 1583 xstate_bv |= X86_XSTATE_ZMM; 1584 memcpy (p, raw, 16); 1585 } 1586 } 1587 } 1588 1589 /* Check if any upper MPX registers are changed. */ 1590 if ((tdep->xcr0 & X86_XSTATE_BNDREGS)) 1591 for (i = I387_BND0R_REGNUM (tdep); 1592 i < I387_BNDCFGU_REGNUM (tdep); i++) 1593 { 1594 regcache->raw_collect (i, raw); 1595 p = XSAVE_MPX_ADDR (tdep, regs, i); 1596 if (memcmp (raw, p, 16)) 1597 { 1598 xstate_bv |= X86_XSTATE_BNDREGS; 1599 memcpy (p, raw, 16); 1600 } 1601 } 1602 1603 /* Check if any upper MPX registers are changed. */ 1604 if ((tdep->xcr0 & X86_XSTATE_BNDCFG)) 1605 for (i = I387_BNDCFGU_REGNUM (tdep); 1606 i < I387_MPXEND_REGNUM (tdep); i++) 1607 { 1608 regcache->raw_collect (i, raw); 1609 p = XSAVE_MPX_ADDR (tdep, regs, i); 1610 if (memcmp (raw, p, 8)) 1611 { 1612 xstate_bv |= X86_XSTATE_BNDCFG; 1613 memcpy (p, raw, 8); 1614 } 1615 } 1616 1617 /* Check if any upper YMM registers are changed. */ 1618 if ((tdep->xcr0 & X86_XSTATE_AVX)) 1619 for (i = I387_YMM0H_REGNUM (tdep); 1620 i < I387_YMMENDH_REGNUM (tdep); i++) 1621 { 1622 regcache->raw_collect (i, raw); 1623 p = XSAVE_AVXH_ADDR (tdep, regs, i); 1624 if (memcmp (raw, p, 16)) 1625 { 1626 xstate_bv |= X86_XSTATE_AVX; 1627 memcpy (p, raw, 16); 1628 } 1629 } 1630 1631 /* Check if any SSE registers are changed. */ 1632 if ((tdep->xcr0 & X86_XSTATE_SSE)) 1633 for (i = I387_XMM0_REGNUM (tdep); 1634 i < I387_MXCSR_REGNUM (tdep); i++) 1635 { 1636 regcache->raw_collect (i, raw); 1637 p = FXSAVE_ADDR (tdep, regs, i); 1638 if (memcmp (raw, p, 16)) 1639 { 1640 xstate_bv |= X86_XSTATE_SSE; 1641 memcpy (p, raw, 16); 1642 } 1643 } 1644 1645 if ((tdep->xcr0 & X86_XSTATE_AVX) || (tdep->xcr0 & X86_XSTATE_SSE)) 1646 { 1647 i = I387_MXCSR_REGNUM (tdep); 1648 regcache->raw_collect (i, raw); 1649 p = FXSAVE_MXCSR_ADDR (regs); 1650 if (memcmp (raw, p, 4)) 1651 { 1652 /* Now, we need to mark one of either SSE of AVX as enabled. 1653 We could pick either. What we do is check to see if one 1654 of the features is already enabled, if it is then we leave 1655 it at that, otherwise we pick SSE. */ 1656 if ((xstate_bv & (X86_XSTATE_SSE | X86_XSTATE_AVX)) == 0) 1657 xstate_bv |= X86_XSTATE_SSE; 1658 memcpy (p, raw, 4); 1659 } 1660 } 1661 1662 /* Check if any X87 registers are changed. Only the non-control 1663 registers are handled here, the control registers are all handled 1664 later on in this function. */ 1665 if ((tdep->xcr0 & X86_XSTATE_X87)) 1666 for (i = I387_ST0_REGNUM (tdep); 1667 i < I387_FCTRL_REGNUM (tdep); i++) 1668 { 1669 regcache->raw_collect (i, raw); 1670 p = FXSAVE_ADDR (tdep, regs, i); 1671 if (memcmp (raw, p, 10)) 1672 { 1673 xstate_bv |= X86_XSTATE_X87; 1674 memcpy (p, raw, 10); 1675 } 1676 } 1677 } 1678 else 1679 { 1680 /* Check if REGNUM is changed. */ 1681 regcache->raw_collect (regnum, raw); 1682 1683 switch (regclass) 1684 { 1685 default: 1686 internal_error (_("invalid i387 regclass")); 1687 1688 case pkeys: 1689 /* This is a PKEYS register. */ 1690 p = XSAVE_PKEYS_ADDR (tdep, regs, regnum); 1691 if (memcmp (raw, p, 4) != 0) 1692 { 1693 xstate_bv |= X86_XSTATE_PKRU; 1694 memcpy (p, raw, 4); 1695 } 1696 break; 1697 1698 case avx512_zmm_h: 1699 /* This is a ZMM register. */ 1700 p = XSAVE_AVX512_ZMM_H_ADDR (tdep, regs, regnum); 1701 if (memcmp (raw, p, 32) != 0) 1702 { 1703 xstate_bv |= (X86_XSTATE_ZMM_H | X86_XSTATE_ZMM); 1704 memcpy (p, raw, 32); 1705 } 1706 break; 1707 case avx512_k: 1708 /* This is a AVX512 mask register. */ 1709 p = XSAVE_AVX512_K_ADDR (tdep, regs, regnum); 1710 if (memcmp (raw, p, 8) != 0) 1711 { 1712 xstate_bv |= X86_XSTATE_K; 1713 memcpy (p, raw, 8); 1714 } 1715 break; 1716 1717 case avx512_ymmh_avx512: 1718 /* This is an upper YMM16-31 register. */ 1719 p = XSAVE_YMM_AVX512_ADDR (tdep, regs, regnum); 1720 if (memcmp (raw, p, 16) != 0) 1721 { 1722 xstate_bv |= X86_XSTATE_ZMM; 1723 memcpy (p, raw, 16); 1724 } 1725 break; 1726 1727 case avx512_xmm_avx512: 1728 /* This is an upper XMM16-31 register. */ 1729 p = XSAVE_XMM_AVX512_ADDR (tdep, regs, regnum); 1730 if (memcmp (raw, p, 16) != 0) 1731 { 1732 xstate_bv |= X86_XSTATE_ZMM; 1733 memcpy (p, raw, 16); 1734 } 1735 break; 1736 1737 case avxh: 1738 /* This is an upper YMM register. */ 1739 p = XSAVE_AVXH_ADDR (tdep, regs, regnum); 1740 if (memcmp (raw, p, 16)) 1741 { 1742 xstate_bv |= X86_XSTATE_AVX; 1743 memcpy (p, raw, 16); 1744 } 1745 break; 1746 1747 case mpx: 1748 if (regnum < I387_BNDCFGU_REGNUM (tdep)) 1749 { 1750 regcache->raw_collect (regnum, raw); 1751 p = XSAVE_MPX_ADDR (tdep, regs, regnum); 1752 if (memcmp (raw, p, 16)) 1753 { 1754 xstate_bv |= X86_XSTATE_BNDREGS; 1755 memcpy (p, raw, 16); 1756 } 1757 } 1758 else 1759 { 1760 p = XSAVE_MPX_ADDR (tdep, regs, regnum); 1761 xstate_bv |= X86_XSTATE_BNDCFG; 1762 memcpy (p, raw, 8); 1763 } 1764 break; 1765 1766 case sse: 1767 /* This is an SSE register. */ 1768 p = FXSAVE_ADDR (tdep, regs, regnum); 1769 if (memcmp (raw, p, 16)) 1770 { 1771 xstate_bv |= X86_XSTATE_SSE; 1772 memcpy (p, raw, 16); 1773 } 1774 break; 1775 1776 case x87: 1777 /* This is an x87 register. */ 1778 p = FXSAVE_ADDR (tdep, regs, regnum); 1779 if (memcmp (raw, p, 10)) 1780 { 1781 xstate_bv |= X86_XSTATE_X87; 1782 memcpy (p, raw, 10); 1783 } 1784 break; 1785 1786 case x87_ctrl_or_mxcsr: 1787 /* We only handle MXCSR here. All other x87 control registers 1788 are handled separately below. */ 1789 if (regnum == I387_MXCSR_REGNUM (tdep)) 1790 { 1791 p = FXSAVE_MXCSR_ADDR (regs); 1792 if (memcmp (raw, p, 2)) 1793 { 1794 /* We're only setting MXCSR, so check the initial state 1795 to see if either of AVX or SSE are already enabled. 1796 If they are then we'll attribute this changed MXCSR to 1797 that feature. If neither feature is enabled, then 1798 we'll attribute this change to the SSE feature. */ 1799 xstate_bv |= (initial_xstate_bv 1800 & (X86_XSTATE_AVX | X86_XSTATE_SSE)); 1801 if ((xstate_bv & (X86_XSTATE_AVX | X86_XSTATE_SSE)) == 0) 1802 xstate_bv |= X86_XSTATE_SSE; 1803 memcpy (p, raw, 2); 1804 } 1805 } 1806 } 1807 } 1808 1809 /* Only handle x87 control registers. */ 1810 for (i = I387_FCTRL_REGNUM (tdep); i < I387_XMM0_REGNUM (tdep); i++) 1811 if (regnum == -1 || regnum == i) 1812 { 1813 /* Most of the FPU control registers occupy only 16 bits in 1814 the xsave extended state. Give those a special treatment. */ 1815 if (i != I387_FIOFF_REGNUM (tdep) 1816 && i != I387_FOOFF_REGNUM (tdep)) 1817 { 1818 gdb_byte buf[4]; 1819 1820 regcache->raw_collect (i, buf); 1821 1822 if (i == I387_FOP_REGNUM (tdep)) 1823 { 1824 /* The opcode occupies only 11 bits. Make sure we 1825 don't touch the other bits. */ 1826 buf[1] &= ((1 << 3) - 1); 1827 buf[1] |= ((FXSAVE_ADDR (tdep, regs, i))[1] & ~((1 << 3) - 1)); 1828 } 1829 else if (i == I387_FTAG_REGNUM (tdep)) 1830 { 1831 /* Converting back is much easier. */ 1832 1833 unsigned short ftag; 1834 int fpreg; 1835 1836 ftag = (buf[1] << 8) | buf[0]; 1837 buf[0] = 0; 1838 buf[1] = 0; 1839 1840 for (fpreg = 7; fpreg >= 0; fpreg--) 1841 { 1842 int tag = (ftag >> (fpreg * 2)) & 3; 1843 1844 if (tag != 3) 1845 buf[0] |= (1 << fpreg); 1846 } 1847 } 1848 p = FXSAVE_ADDR (tdep, regs, i); 1849 if (memcmp (p, buf, 2)) 1850 { 1851 xstate_bv |= X86_XSTATE_X87; 1852 memcpy (p, buf, 2); 1853 } 1854 } 1855 else 1856 { 1857 int regsize; 1858 1859 regcache->raw_collect (i, raw); 1860 regsize = regcache_register_size (regcache, i); 1861 p = FXSAVE_ADDR (tdep, regs, i); 1862 if (memcmp (raw, p, regsize)) 1863 { 1864 xstate_bv |= X86_XSTATE_X87; 1865 memcpy (p, raw, regsize); 1866 } 1867 } 1868 } 1869 1870 /* Update the corresponding bits in `xstate_bv' if any 1871 registers are changed. */ 1872 if (xstate_bv) 1873 { 1874 /* The supported bits in `xstat_bv' are 8 bytes. */ 1875 initial_xstate_bv |= xstate_bv; 1876 store_unsigned_integer (XSAVE_XSTATE_BV_ADDR (regs), 1877 8, byte_order, 1878 initial_xstate_bv); 1879 } 1880 } 1881 1882 /* Recreate the FTW (tag word) valid bits from the 80-bit FP data in 1883 *RAW. */ 1884 1885 static int 1886 i387_tag (const gdb_byte *raw) 1887 { 1888 int integer; 1889 unsigned int exponent; 1890 unsigned long fraction[2]; 1891 1892 integer = raw[7] & 0x80; 1893 exponent = (((raw[9] & 0x7f) << 8) | raw[8]); 1894 fraction[0] = ((raw[3] << 24) | (raw[2] << 16) | (raw[1] << 8) | raw[0]); 1895 fraction[1] = (((raw[7] & 0x7f) << 24) | (raw[6] << 16) 1896 | (raw[5] << 8) | raw[4]); 1897 1898 if (exponent == 0x7fff) 1899 { 1900 /* Special. */ 1901 return (2); 1902 } 1903 else if (exponent == 0x0000) 1904 { 1905 if (fraction[0] == 0x0000 && fraction[1] == 0x0000 && !integer) 1906 { 1907 /* Zero. */ 1908 return (1); 1909 } 1910 else 1911 { 1912 /* Special. */ 1913 return (2); 1914 } 1915 } 1916 else 1917 { 1918 if (integer) 1919 { 1920 /* Valid. */ 1921 return (0); 1922 } 1923 else 1924 { 1925 /* Special. */ 1926 return (2); 1927 } 1928 } 1929 } 1930 1931 /* Prepare the FPU stack in REGCACHE for a function return. */ 1932 1933 void 1934 i387_return_value (struct gdbarch *gdbarch, struct regcache *regcache) 1935 { 1936 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 1937 ULONGEST fstat; 1938 1939 /* Set the top of the floating-point register stack to 7. The 1940 actual value doesn't really matter, but 7 is what a normal 1941 function return would end up with if the program started out with 1942 a freshly initialized FPU. */ 1943 regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat); 1944 fstat |= (7 << 11); 1945 regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat); 1946 1947 /* Mark %st(1) through %st(7) as empty. Since we set the top of the 1948 floating-point register stack to 7, the appropriate value for the 1949 tag word is 0x3fff. */ 1950 regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff); 1951 1952 } 1953 1954 /* See i387-tdep.h. */ 1955 1956 void 1957 i387_reset_bnd_regs (struct gdbarch *gdbarch, struct regcache *regcache) 1958 { 1959 i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); 1960 1961 if (I387_BND0R_REGNUM (tdep) > 0) 1962 { 1963 gdb_byte bnd_buf[16]; 1964 1965 memset (bnd_buf, 0, 16); 1966 for (int i = 0; i < I387_NUM_BND_REGS; i++) 1967 regcache->raw_write (I387_BND0R_REGNUM (tdep) + i, bnd_buf); 1968 } 1969 } 1970